drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 static const u32 hpd_ibx[] = {
  40         [HPD_CRT] = SDE_CRT_HOTPLUG,
  41         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  42         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  43         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  44         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  45 };
  46
  47 static const u32 hpd_cpt[] = {
  48         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  49         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  50         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  51         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  52         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  53 };
  54
  55 static const u32 hpd_mask_i915[] = {
  56         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  57         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  58         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  59         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  60         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  61         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  62 };
  63
  64 static const u32 hpd_status_gen4[] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  71 };
  72
  73 static const u32 hpd_status_i965[] = {
  74          [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75          [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  76          [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  77          [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78          [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79          [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  83         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  84         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  85         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  86         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  87         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  88         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  89 };
  90
  91 static void ibx_hpd_irq_setup(struct drm_device *dev);
  92 static void i915_hpd_irq_setup(struct drm_device *dev);
  93
  94 /* For display hotplug interrupt */
  95 static void
  96 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  97 {
  98         if ((dev_priv->irq_mask & mask) != 0) {
  99                 dev_priv->irq_mask &= ~mask;
 100                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 101                 POSTING_READ(DEIMR);
 102         }
 103 }
 104
 105 static void
 106 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 107 {
 108         if ((dev_priv->irq_mask & mask) != mask) {
 109                 dev_priv->irq_mask |= mask;
 110                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 111                 POSTING_READ(DEIMR);
 112         }
 113 }
 114
 115 static bool ivb_can_enable_err_int(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct intel_crtc *crtc;
 119         enum pipe pipe;
 120
 121         for_each_pipe(pipe) {
 122                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 123
 124                 if (crtc->cpu_fifo_underrun_disabled)
 125                         return false;
 126         }
 127
 128         return true;
 129 }
 130
 131 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 132 {
 133         struct drm_i915_private *dev_priv = dev->dev_private;
 134         enum pipe pipe;
 135         struct intel_crtc *crtc;
 136
 137         for_each_pipe(pipe) {
 138                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 139
 140                 if (crtc->pch_fifo_underrun_disabled)
 141                         return false;
 142         }
 143
 144         return true;
 145 }
 146
 147 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 148                                                  enum pipe pipe, bool enable)
 149 {
 150         struct drm_i915_private *dev_priv = dev->dev_private;
 151         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 152                                           DE_PIPEB_FIFO_UNDERRUN;
 153
 154         if (enable)
 155                 ironlake_enable_display_irq(dev_priv, bit);
 156         else
 157                 ironlake_disable_display_irq(dev_priv, bit);
 158 }
 159
 160 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 161                                                   bool enable)
 162 {
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164
 165         if (enable) {
 166                 if (!ivb_can_enable_err_int(dev))
 167                         return;
 168
 169                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
 170                                          ERR_INT_FIFO_UNDERRUN_B |
 171                                          ERR_INT_FIFO_UNDERRUN_C);
 172
 173                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 174         } else {
 175                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 176         }
 177 }
 178
 179 static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
 180                                             bool enable)
 181 {
 182         struct drm_device *dev = crtc->base.dev;
 183         struct drm_i915_private *dev_priv = dev->dev_private;
 184         uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
 185                                                 SDE_TRANSB_FIFO_UNDER;
 186
 187         if (enable)
 188                 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
 189         else
 190                 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
 191
 192         POSTING_READ(SDEIMR);
 193 }
 194
 195 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 196                                             enum transcoder pch_transcoder,
 197                                             bool enable)
 198 {
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200
 201         if (enable) {
 202                 if (!cpt_can_enable_serr_int(dev))
 203                         return;
 204
 205                 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
 206                                      SERR_INT_TRANS_B_FIFO_UNDERRUN |
 207                                      SERR_INT_TRANS_C_FIFO_UNDERRUN);
 208
 209                 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
 210         } else {
 211                 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
 212         }
 213
 214         POSTING_READ(SDEIMR);
 215 }
 216
 217 /**
 218  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 219  * @dev: drm device
 220  * @pipe: pipe
 221  * @enable: true if we want to report FIFO underrun errors, false otherwise
 222  *
 223  * This function makes us disable or enable CPU fifo underruns for a specific
 224  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 225  * reporting for one pipe may also disable all the other CPU error interruts for
 226  * the other pipes, due to the fact that there's just one interrupt mask/enable
 227  * bit for all the pipes.
 228  *
 229  * Returns the previous state of underrun reporting.
 230  */
 231 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 232                                            enum pipe pipe, bool enable)
 233 {
 234         struct drm_i915_private *dev_priv = dev->dev_private;
 235         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 237         unsigned long flags;
 238         bool ret;
 239
 240         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 241
 242         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 243
 244         if (enable == ret)
 245                 goto done;
 246
 247         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 248
 249         if (IS_GEN5(dev) || IS_GEN6(dev))
 250                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 251         else if (IS_GEN7(dev))
 252                 ivybridge_set_fifo_underrun_reporting(dev, enable);
 253
 254 done:
 255         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 256         return ret;
 257 }
 258
 259 /**
 260  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 261  * @dev: drm device
 262  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 263  * @enable: true if we want to report FIFO underrun errors, false otherwise
 264  *
 265  * This function makes us disable or enable PCH fifo underruns for a specific
 266  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 267  * underrun reporting for one transcoder may also disable all the other PCH
 268  * error interruts for the other transcoders, due to the fact that there's just
 269  * one interrupt mask/enable bit for all the transcoders.
 270  *
 271  * Returns the previous state of underrun reporting.
 272  */
 273 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 274                                            enum transcoder pch_transcoder,
 275                                            bool enable)
 276 {
 277         struct drm_i915_private *dev_priv = dev->dev_private;
 278         enum pipe p;
 279         struct drm_crtc *crtc;
 280         struct intel_crtc *intel_crtc;
 281         unsigned long flags;
 282         bool ret;
 283
 284         if (HAS_PCH_LPT(dev)) {
 285                 crtc = NULL;
 286                 for_each_pipe(p) {
 287                         struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
 288                         if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
 289                                 crtc = c;
 290                                 break;
 291                         }
 292                 }
 293                 if (!crtc) {
 294                         DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
 295                         return false;
 296                 }
 297         } else {
 298                 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 299         }
 300         intel_crtc = to_intel_crtc(crtc);
 301
 302         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 303
 304         ret = !intel_crtc->pch_fifo_underrun_disabled;
 305
 306         if (enable == ret)
 307                 goto done;
 308
 309         intel_crtc->pch_fifo_underrun_disabled = !enable;
 310
 311         if (HAS_PCH_IBX(dev))
 312                 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
 313         else
 314                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 315
 316 done:
 317         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 318         return ret;
 319 }
 320
 321
 322 void
 323 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 324 {
 325         u32 reg = PIPESTAT(pipe);
 326         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 327
 328         if ((pipestat & mask) == mask)
 329                 return;
 330
 331         /* Enable the interrupt, clear any pending status */
 332         pipestat |= mask | (mask >> 16);
 333         I915_WRITE(reg, pipestat);
 334         POSTING_READ(reg);
 335 }
 336
 337 void
 338 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 339 {
 340         u32 reg = PIPESTAT(pipe);
 341         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 342
 343         if ((pipestat & mask) == 0)
 344                 return;
 345
 346         pipestat &= ~mask;
 347         I915_WRITE(reg, pipestat);
 348         POSTING_READ(reg);
 349 }
 350
 351 /**
 352  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 353  */
 354 static void i915_enable_asle_pipestat(struct drm_device *dev)
 355 {
 356         drm_i915_private_t *dev_priv = dev->dev_private;
 357         unsigned long irqflags;
 358
 359         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 360                 return;
 361
 362         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 363
 364         i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
 365         if (INTEL_INFO(dev)->gen >= 4)
 366                 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
 367
 368         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 369 }
 370
 371 /**
 372  * i915_pipe_enabled - check if a pipe is enabled
 373  * @dev: DRM device
 374  * @pipe: pipe to check
 375  *
 376  * Reading certain registers when the pipe is disabled can hang the chip.
 377  * Use this routine to make sure the PLL is running and the pipe is active
 378  * before reading such registers if unsure.
 379  */
 380 static int
 381 i915_pipe_enabled(struct drm_device *dev, int pipe)
 382 {
 383         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 384
 385         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 386                 /* Locking is horribly broken here, but whatever. */
 387                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 388                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 389
 390                 return intel_crtc->active;
 391         } else {
 392                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 393         }
 394 }
 395
 396 /* Called from drm generic code, passed a 'crtc', which
 397  * we use as a pipe index
 398  */
 399 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 400 {
 401         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 402         unsigned long high_frame;
 403         unsigned long low_frame;
 404         u32 high1, high2, low;
 405
 406         if (!i915_pipe_enabled(dev, pipe)) {
 407                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 408                                 "pipe %c\n", pipe_name(pipe));
 409                 return 0;
 410         }
 411
 412         high_frame = PIPEFRAME(pipe);
 413         low_frame = PIPEFRAMEPIXEL(pipe);
 414
 415         /*
 416          * High & low register fields aren't synchronized, so make sure
 417          * we get a low value that's stable across two reads of the high
 418          * register.
 419          */
 420         do {
 421                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 422                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 423                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 424         } while (high1 != high2);
 425
 426         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 427         low >>= PIPE_FRAME_LOW_SHIFT;
 428         return (high1 << 8) | low;
 429 }
 430
 431 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 432 {
 433         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 434         int reg = PIPE_FRMCOUNT_GM45(pipe);
 435
 436         if (!i915_pipe_enabled(dev, pipe)) {
 437                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 438                                  "pipe %c\n", pipe_name(pipe));
 439                 return 0;
 440         }
 441
 442         return I915_READ(reg);
 443 }
 444
 445 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 446                              int *vpos, int *hpos)
 447 {
 448         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 449         u32 vbl = 0, position = 0;
 450         int vbl_start, vbl_end, htotal, vtotal;
 451         bool in_vbl = true;
 452         int ret = 0;
 453         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 454                                                                       pipe);
 455
 456         if (!i915_pipe_enabled(dev, pipe)) {
 457                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 458                                  "pipe %c\n", pipe_name(pipe));
 459                 return 0;
 460         }
 461
 462         /* Get vtotal. */
 463         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 464
 465         if (INTEL_INFO(dev)->gen >= 4) {
 466                 /* No obvious pixelcount register. Only query vertical
 467                  * scanout position from Display scan line register.
 468                  */
 469                 position = I915_READ(PIPEDSL(pipe));
 470
 471                 /* Decode into vertical scanout position. Don't have
 472                  * horizontal scanout position.
 473                  */
 474                 *vpos = position & 0x1fff;
 475                 *hpos = 0;
 476         } else {
 477                 /* Have access to pixelcount since start of frame.
 478                  * We can split this into vertical and horizontal
 479                  * scanout position.
 480                  */
 481                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 482
 483                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 484                 *vpos = position / htotal;
 485                 *hpos = position - (*vpos * htotal);
 486         }
 487
 488         /* Query vblank area. */
 489         vbl = I915_READ(VBLANK(cpu_transcoder));
 490
 491         /* Test position against vblank region. */
 492         vbl_start = vbl & 0x1fff;
 493         vbl_end = (vbl >> 16) & 0x1fff;
 494
 495         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 496                 in_vbl = false;
 497
 498         /* Inside "upper part" of vblank area? Apply corrective offset: */
 499         if (in_vbl && (*vpos >= vbl_start))
 500                 *vpos = *vpos - vtotal;
 501
 502         /* Readouts valid? */
 503         if (vbl > 0)
 504                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 505
 506         /* In vblank? */
 507         if (in_vbl)
 508                 ret |= DRM_SCANOUTPOS_INVBL;
 509
 510         return ret;
 511 }
 512
 513 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 514                               int *max_error,
 515                               struct timeval *vblank_time,
 516                               unsigned flags)
 517 {
 518         struct drm_crtc *crtc;
 519
 520         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 521                 DRM_ERROR("Invalid crtc %d\n", pipe);
 522                 return -EINVAL;
 523         }
 524
 525         /* Get drm_crtc to timestamp: */
 526         crtc = intel_get_crtc_for_pipe(dev, pipe);
 527         if (crtc == NULL) {
 528                 DRM_ERROR("Invalid crtc %d\n", pipe);
 529                 return -EINVAL;
 530         }
 531
 532         if (!crtc->enabled) {
 533                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 534                 return -EBUSY;
 535         }
 536
 537         /* Helper routine in DRM core does all the work: */
 538         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 539                                                      vblank_time, flags,
 540                                                      crtc);
 541 }
 542
 543 static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
 544 {
 545         enum drm_connector_status old_status;
 546
 547         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 548         old_status = connector->status;
 549
 550         connector->status = connector->funcs->detect(connector, false);
 551         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
 552                       connector->base.id,
 553                       drm_get_connector_name(connector),
 554                       old_status, connector->status);
 555         return (old_status != connector->status);
 556 }
 557
 558 /*
 559  * Handle hotplug events outside the interrupt handler proper.
 560  */
 561 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 562
 563 static void i915_hotplug_work_func(struct work_struct *work)
 564 {
 565         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 566                                                     hotplug_work);
 567         struct drm_device *dev = dev_priv->dev;
 568         struct drm_mode_config *mode_config = &dev->mode_config;
 569         struct intel_connector *intel_connector;
 570         struct intel_encoder *intel_encoder;
 571         struct drm_connector *connector;
 572         unsigned long irqflags;
 573         bool hpd_disabled = false;
 574         bool changed = false;
 575         u32 hpd_event_bits;
 576
 577         /* HPD irq before everything is fully set up. */
 578         if (!dev_priv->enable_hotplug_processing)
 579                 return;
 580
 581         mutex_lock(&mode_config->mutex);
 582         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 583
 584         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 585
 586         hpd_event_bits = dev_priv->hpd_event_bits;
 587         dev_priv->hpd_event_bits = 0;
 588         list_for_each_entry(connector, &mode_config->connector_list, head) {
 589                 intel_connector = to_intel_connector(connector);
 590                 intel_encoder = intel_connector->encoder;
 591                 if (intel_encoder->hpd_pin > HPD_NONE &&
 592                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 593                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 594                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 595                                  "switching from hotplug detection to polling\n",
 596                                 drm_get_connector_name(connector));
 597                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 598                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 599                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 600                         hpd_disabled = true;
 601                 }
 602                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 603                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 604                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 605                 }
 606         }
 607          /* if there were no outputs to poll, poll was disabled,
 608           * therefore make sure it's enabled when disabling HPD on
 609           * some connectors */
 610         if (hpd_disabled) {
 611                 drm_kms_helper_poll_enable(dev);
 612                 mod_timer(&dev_priv->hotplug_reenable_timer,
 613                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 614         }
 615
 616         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 617
 618         list_for_each_entry(connector, &mode_config->connector_list, head) {
 619                 intel_connector = to_intel_connector(connector);
 620                 intel_encoder = intel_connector->encoder;
 621                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 622                         if (intel_encoder->hot_plug)
 623                                 intel_encoder->hot_plug(intel_encoder);
 624                         if (intel_hpd_irq_event(dev, connector))
 625                                 changed = true;
 626                 }
 627         }
 628         mutex_unlock(&mode_config->mutex);
 629
 630         if (changed)
 631                 drm_kms_helper_hotplug_event(dev);
 632 }
 633
 634 static void ironlake_handle_rps_change(struct drm_device *dev)
 635 {
 636         drm_i915_private_t *dev_priv = dev->dev_private;
 637         u32 busy_up, busy_down, max_avg, min_avg;
 638         u8 new_delay;
 639         unsigned long flags;
 640
 641         spin_lock_irqsave(&mchdev_lock, flags);
 642
 643         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 644
 645         new_delay = dev_priv->ips.cur_delay;
 646
 647         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 648         busy_up = I915_READ(RCPREVBSYTUPAVG);
 649         busy_down = I915_READ(RCPREVBSYTDNAVG);
 650         max_avg = I915_READ(RCBMAXAVG);
 651         min_avg = I915_READ(RCBMINAVG);
 652
 653         /* Handle RCS change request from hw */
 654         if (busy_up > max_avg) {
 655                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 656                         new_delay = dev_priv->ips.cur_delay - 1;
 657                 if (new_delay < dev_priv->ips.max_delay)
 658                         new_delay = dev_priv->ips.max_delay;
 659         } else if (busy_down < min_avg) {
 660                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 661                         new_delay = dev_priv->ips.cur_delay + 1;
 662                 if (new_delay > dev_priv->ips.min_delay)
 663                         new_delay = dev_priv->ips.min_delay;
 664         }
 665
 666         if (ironlake_set_drps(dev, new_delay))
 667                 dev_priv->ips.cur_delay = new_delay;
 668
 669         spin_unlock_irqrestore(&mchdev_lock, flags);
 670
 671         return;
 672 }
 673
 674 static void notify_ring(struct drm_device *dev,
 675                         struct intel_ring_buffer *ring)
 676 {
 677         struct drm_i915_private *dev_priv = dev->dev_private;
 678
 679         if (ring->obj == NULL)
 680                 return;
 681
 682         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 683
 684         wake_up_all(&ring->irq_queue);
 685         if (i915_enable_hangcheck) {
 686                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 687                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 688         }
 689 }
 690
 691 static void gen6_pm_rps_work(struct work_struct *work)
 692 {
 693         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 694                                                     rps.work);
 695         u32 pm_iir, pm_imr;
 696         u8 new_delay;
 697
 698         spin_lock_irq(&dev_priv->rps.lock);
 699         pm_iir = dev_priv->rps.pm_iir;
 700         dev_priv->rps.pm_iir = 0;
 701         pm_imr = I915_READ(GEN6_PMIMR);
 702         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 703         I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
 704         spin_unlock_irq(&dev_priv->rps.lock);
 705
 706         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 707                 return;
 708
 709         mutex_lock(&dev_priv->rps.hw_lock);
 710
 711         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 712                 new_delay = dev_priv->rps.cur_delay + 1;
 713         else
 714                 new_delay = dev_priv->rps.cur_delay - 1;
 715
 716         /* sysfs frequency interfaces may have snuck in while servicing the
 717          * interrupt
 718          */
 719         if (!(new_delay > dev_priv->rps.max_delay ||
 720               new_delay < dev_priv->rps.min_delay)) {
 721                 if (IS_VALLEYVIEW(dev_priv->dev))
 722                         valleyview_set_rps(dev_priv->dev, new_delay);
 723                 else
 724                         gen6_set_rps(dev_priv->dev, new_delay);
 725         }
 726
 727         if (IS_VALLEYVIEW(dev_priv->dev)) {
 728                 /*
 729                  * On VLV, when we enter RC6 we may not be at the minimum
 730                  * voltage level, so arm a timer to check.  It should only
 731                  * fire when there's activity or once after we've entered
 732                  * RC6, and then won't be re-armed until the next RPS interrupt.
 733                  */
 734                 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
 735                                  msecs_to_jiffies(100));
 736         }
 737
 738         mutex_unlock(&dev_priv->rps.hw_lock);
 739 }
 740
 741
 742 /**
 743  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 744  * occurred.
 745  * @work: workqueue struct
 746  *
 747  * Doesn't actually do anything except notify userspace. As a consequence of
 748  * this event, userspace should try to remap the bad rows since statistically
 749  * it is likely the same row is more likely to go bad again.
 750  */
 751 static void ivybridge_parity_work(struct work_struct *work)
 752 {
 753         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 754                                                     l3_parity.error_work);
 755         u32 error_status, row, bank, subbank;
 756         char *parity_event[5];
 757         uint32_t misccpctl;
 758         unsigned long flags;
 759
 760         /* We must turn off DOP level clock gating to access the L3 registers.
 761          * In order to prevent a get/put style interface, acquire struct mutex
 762          * any time we access those registers.
 763          */
 764         mutex_lock(&dev_priv->dev->struct_mutex);
 765
 766         misccpctl = I915_READ(GEN7_MISCCPCTL);
 767         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 768         POSTING_READ(GEN7_MISCCPCTL);
 769
 770         error_status = I915_READ(GEN7_L3CDERRST1);
 771         row = GEN7_PARITY_ERROR_ROW(error_status);
 772         bank = GEN7_PARITY_ERROR_BANK(error_status);
 773         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 774
 775         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 776                                     GEN7_L3CDERRST1_ENABLE);
 777         POSTING_READ(GEN7_L3CDERRST1);
 778
 779         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 780
 781         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 782         dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 783         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 784         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 785
 786         mutex_unlock(&dev_priv->dev->struct_mutex);
 787
 788         parity_event[0] = "L3_PARITY_ERROR=1";
 789         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 790         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 791         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 792         parity_event[4] = NULL;
 793
 794         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 795                            KOBJ_CHANGE, parity_event);
 796
 797         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 798                   row, bank, subbank);
 799
 800         kfree(parity_event[3]);
 801         kfree(parity_event[2]);
 802         kfree(parity_event[1]);
 803 }
 804
 805 static void ivybridge_handle_parity_error(struct drm_device *dev)
 806 {
 807         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 808         unsigned long flags;
 809
 810         if (!HAS_L3_GPU_CACHE(dev))
 811                 return;
 812
 813         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 814         dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 815         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 816         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 817
 818         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 819 }
 820
 821 static void snb_gt_irq_handler(struct drm_device *dev,
 822                                struct drm_i915_private *dev_priv,
 823                                u32 gt_iir)
 824 {
 825
 826         if (gt_iir &
 827             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
 828                 notify_ring(dev, &dev_priv->ring[RCS]);
 829         if (gt_iir & GT_BSD_USER_INTERRUPT)
 830                 notify_ring(dev, &dev_priv->ring[VCS]);
 831         if (gt_iir & GT_BLT_USER_INTERRUPT)
 832                 notify_ring(dev, &dev_priv->ring[BCS]);
 833
 834         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 835                       GT_BSD_CS_ERROR_INTERRUPT |
 836                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
 837                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 838                 i915_handle_error(dev, false);
 839         }
 840
 841         if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
 842                 ivybridge_handle_parity_error(dev);
 843 }
 844
 845 /* Legacy way of handling PM interrupts */
 846 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 847                                 u32 pm_iir)
 848 {
 849         unsigned long flags;
 850
 851         /*
 852          * IIR bits should never already be set because IMR should
 853          * prevent an interrupt from being shown in IIR. The warning
 854          * displays a case where we've unsafely cleared
 855          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 856          * type is not a problem, it displays a problem in the logic.
 857          *
 858          * The mask bit in IMR is cleared by dev_priv->rps.work.
 859          */
 860
 861         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 862         dev_priv->rps.pm_iir |= pm_iir;
 863         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 864         POSTING_READ(GEN6_PMIMR);
 865         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 866
 867         queue_work(dev_priv->wq, &dev_priv->rps.work);
 868 }
 869
 870 #define HPD_STORM_DETECT_PERIOD 1000
 871 #define HPD_STORM_THRESHOLD 5
 872
 873 static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
 874                                             u32 hotplug_trigger,
 875                                             const u32 *hpd)
 876 {
 877         drm_i915_private_t *dev_priv = dev->dev_private;
 878         unsigned long irqflags;
 879         int i;
 880         bool ret = false;
 881
 882         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 883
 884         for (i = 1; i < HPD_NUM_PINS; i++) {
 885
 886                 if (!(hpd[i] & hotplug_trigger) ||
 887                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
 888                         continue;
 889
 890                 dev_priv->hpd_event_bits |= (1 << i);
 891                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
 892                                    dev_priv->hpd_stats[i].hpd_last_jiffies
 893                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
 894                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
 895                         dev_priv->hpd_stats[i].hpd_cnt = 0;
 896                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
 897                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
 898                         dev_priv->hpd_event_bits &= ~(1 << i);
 899                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
 900                         ret = true;
 901                 } else {
 902                         dev_priv->hpd_stats[i].hpd_cnt++;
 903                 }
 904         }
 905
 906         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 907
 908         return ret;
 909 }
 910
 911 static void gmbus_irq_handler(struct drm_device *dev)
 912 {
 913         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 914
 915         wake_up_all(&dev_priv->gmbus_wait_queue);
 916 }
 917
 918 static void dp_aux_irq_handler(struct drm_device *dev)
 919 {
 920         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 921
 922         wake_up_all(&dev_priv->gmbus_wait_queue);
 923 }
 924
 925 /* Unlike gen6_queue_rps_work() from which this function is originally derived,
 926  * we must be able to deal with other PM interrupts. This is complicated because
 927  * of the way in which we use the masks to defer the RPS work (which for
 928  * posterity is necessary because of forcewake).
 929  */
 930 static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
 931                                u32 pm_iir)
 932 {
 933         unsigned long flags;
 934
 935         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 936         dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
 937         if (dev_priv->rps.pm_iir) {
 938                 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 939                 /* never want to mask useful interrupts. (also posting read) */
 940                 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
 941                 /* TODO: if queue_work is slow, move it out of the spinlock */
 942                 queue_work(dev_priv->wq, &dev_priv->rps.work);
 943         }
 944         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 945
 946         if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
 947                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
 948                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
 949
 950                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
 951                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
 952                         i915_handle_error(dev_priv->dev, false);
 953                 }
 954         }
 955 }
 956
 957 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 958 {
 959         struct drm_device *dev = (struct drm_device *) arg;
 960         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 961         u32 iir, gt_iir, pm_iir;
 962         irqreturn_t ret = IRQ_NONE;
 963         unsigned long irqflags;
 964         int pipe;
 965         u32 pipe_stats[I915_MAX_PIPES];
 966
 967         atomic_inc(&dev_priv->irq_received);
 968
 969         while (true) {
 970                 iir = I915_READ(VLV_IIR);
 971                 gt_iir = I915_READ(GTIIR);
 972                 pm_iir = I915_READ(GEN6_PMIIR);
 973
 974                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 975                         goto out;
 976
 977                 ret = IRQ_HANDLED;
 978
 979                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 980
 981                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 982                 for_each_pipe(pipe) {
 983                         int reg = PIPESTAT(pipe);
 984                         pipe_stats[pipe] = I915_READ(reg);
 985
 986                         /*
 987                          * Clear the PIPE*STAT regs before the IIR
 988                          */
 989                         if (pipe_stats[pipe] & 0x8000ffff) {
 990                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 991                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 992                                                          pipe_name(pipe));
 993                                 I915_WRITE(reg, pipe_stats[pipe]);
 994                         }
 995                 }
 996                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 997
 998                 for_each_pipe(pipe) {
 999                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1000                                 drm_handle_vblank(dev, pipe);
1001
1002                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1003                                 intel_prepare_page_flip(dev, pipe);
1004                                 intel_finish_page_flip(dev, pipe);
1005                         }
1006                 }
1007
1008                 /* Consume port.  Then clear IIR or we'll miss events */
1009                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1010                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1011                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1012
1013                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1014                                          hotplug_status);
1015                         if (hotplug_trigger) {
1016                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
1017                                         i915_hpd_irq_setup(dev);
1018                                 queue_work(dev_priv->wq,
1019                                            &dev_priv->hotplug_work);
1020                         }
1021                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1022                         I915_READ(PORT_HOTPLUG_STAT);
1023                 }
1024
1025                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1026                         gmbus_irq_handler(dev);
1027
1028                 if (pm_iir & GEN6_PM_RPS_EVENTS)
1029                         gen6_queue_rps_work(dev_priv, pm_iir);
1030
1031                 I915_WRITE(GTIIR, gt_iir);
1032                 I915_WRITE(GEN6_PMIIR, pm_iir);
1033                 I915_WRITE(VLV_IIR, iir);
1034         }
1035
1036 out:
1037         return ret;
1038 }
1039
1040 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1041 {
1042         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1043         int pipe;
1044         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1045
1046         if (hotplug_trigger) {
1047                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
1048                         ibx_hpd_irq_setup(dev);
1049                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
1050         }
1051         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1052                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1053                                SDE_AUDIO_POWER_SHIFT);
1054                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1055                                  port_name(port));
1056         }
1057
1058         if (pch_iir & SDE_AUX_MASK)
1059                 dp_aux_irq_handler(dev);
1060
1061         if (pch_iir & SDE_GMBUS)
1062                 gmbus_irq_handler(dev);
1063
1064         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1065                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1066
1067         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1068                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1069
1070         if (pch_iir & SDE_POISON)
1071                 DRM_ERROR("PCH poison interrupt\n");
1072
1073         if (pch_iir & SDE_FDI_MASK)
1074                 for_each_pipe(pipe)
1075                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1076                                          pipe_name(pipe),
1077                                          I915_READ(FDI_RX_IIR(pipe)));
1078
1079         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1080                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1081
1082         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1083                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1084
1085         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1086                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1087                                                           false))
1088                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1089
1090         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1091                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1092                                                           false))
1093                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1094 }
1095
1096 static void ivb_err_int_handler(struct drm_device *dev)
1097 {
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         u32 err_int = I915_READ(GEN7_ERR_INT);
1100
1101         if (err_int & ERR_INT_POISON)
1102                 DRM_ERROR("Poison interrupt\n");
1103
1104         if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1105                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1106                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1107
1108         if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1109                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1110                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1111
1112         if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1113                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1114                         DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1115
1116         I915_WRITE(GEN7_ERR_INT, err_int);
1117 }
1118
1119 static void cpt_serr_int_handler(struct drm_device *dev)
1120 {
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122         u32 serr_int = I915_READ(SERR_INT);
1123
1124         if (serr_int & SERR_INT_POISON)
1125                 DRM_ERROR("PCH poison interrupt\n");
1126
1127         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1128                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1129                                                           false))
1130                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1131
1132         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1133                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1134                                                           false))
1135                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1136
1137         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1138                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1139                                                           false))
1140                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1141
1142         I915_WRITE(SERR_INT, serr_int);
1143 }
1144
1145 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1146 {
1147         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1148         int pipe;
1149         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1150
1151         if (hotplug_trigger) {
1152                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
1153                         ibx_hpd_irq_setup(dev);
1154                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
1155         }
1156         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1157                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1158                                SDE_AUDIO_POWER_SHIFT_CPT);
1159                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1160                                  port_name(port));
1161         }
1162
1163         if (pch_iir & SDE_AUX_MASK_CPT)
1164                 dp_aux_irq_handler(dev);
1165
1166         if (pch_iir & SDE_GMBUS_CPT)
1167                 gmbus_irq_handler(dev);
1168
1169         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1170                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1171
1172         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1173                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1174
1175         if (pch_iir & SDE_FDI_MASK_CPT)
1176                 for_each_pipe(pipe)
1177                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1178                                          pipe_name(pipe),
1179                                          I915_READ(FDI_RX_IIR(pipe)));
1180
1181         if (pch_iir & SDE_ERROR_CPT)
1182                 cpt_serr_int_handler(dev);
1183 }
1184
1185 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
1186 {
1187         struct drm_device *dev = (struct drm_device *) arg;
1188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1189         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
1190         irqreturn_t ret = IRQ_NONE;
1191         int i;
1192
1193         atomic_inc(&dev_priv->irq_received);
1194
1195         /* We get interrupts on unclaimed registers, so check for this before we
1196          * do any I915_{READ,WRITE}. */
1197         if (IS_HASWELL(dev) &&
1198             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1199                 DRM_ERROR("Unclaimed register before interrupt\n");
1200                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1201         }
1202
1203         /* disable master interrupt before clearing iir  */
1204         de_ier = I915_READ(DEIER);
1205         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1206
1207         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1208          * interrupts will will be stored on its back queue, and then we'll be
1209          * able to process them after we restore SDEIER (as soon as we restore
1210          * it, we'll get an interrupt if SDEIIR still has something to process
1211          * due to its back queue). */
1212         if (!HAS_PCH_NOP(dev)) {
1213                 sde_ier = I915_READ(SDEIER);
1214                 I915_WRITE(SDEIER, 0);
1215                 POSTING_READ(SDEIER);
1216         }
1217
1218         /* On Haswell, also mask ERR_INT because we don't want to risk
1219          * generating "unclaimed register" interrupts from inside the interrupt
1220          * handler. */
1221         if (IS_HASWELL(dev))
1222                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1223
1224         gt_iir = I915_READ(GTIIR);
1225         if (gt_iir) {
1226                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1227                 I915_WRITE(GTIIR, gt_iir);
1228                 ret = IRQ_HANDLED;
1229         }
1230
1231         de_iir = I915_READ(DEIIR);
1232         if (de_iir) {
1233                 if (de_iir & DE_ERR_INT_IVB)
1234                         ivb_err_int_handler(dev);
1235
1236                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1237                         dp_aux_irq_handler(dev);
1238
1239                 if (de_iir & DE_GSE_IVB)
1240                         intel_opregion_asle_intr(dev);
1241
1242                 for (i = 0; i < 3; i++) {
1243                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1244                                 drm_handle_vblank(dev, i);
1245                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1246                                 intel_prepare_page_flip(dev, i);
1247                                 intel_finish_page_flip_plane(dev, i);
1248                         }
1249                 }
1250
1251                 /* check event from PCH */
1252                 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1253                         u32 pch_iir = I915_READ(SDEIIR);
1254
1255                         cpt_irq_handler(dev, pch_iir);
1256
1257                         /* clear PCH hotplug event before clear CPU irq */
1258                         I915_WRITE(SDEIIR, pch_iir);
1259                 }
1260
1261                 I915_WRITE(DEIIR, de_iir);
1262                 ret = IRQ_HANDLED;
1263         }
1264
1265         pm_iir = I915_READ(GEN6_PMIIR);
1266         if (pm_iir) {
1267                 if (IS_HASWELL(dev))
1268                         hsw_pm_irq_handler(dev_priv, pm_iir);
1269                 else if (pm_iir & GEN6_PM_RPS_EVENTS)
1270                         gen6_queue_rps_work(dev_priv, pm_iir);
1271                 I915_WRITE(GEN6_PMIIR, pm_iir);
1272                 ret = IRQ_HANDLED;
1273         }
1274
1275         if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
1276                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1277
1278         I915_WRITE(DEIER, de_ier);
1279         POSTING_READ(DEIER);
1280         if (!HAS_PCH_NOP(dev)) {
1281                 I915_WRITE(SDEIER, sde_ier);
1282                 POSTING_READ(SDEIER);
1283         }
1284
1285         return ret;
1286 }
1287
1288 static void ilk_gt_irq_handler(struct drm_device *dev,
1289                                struct drm_i915_private *dev_priv,
1290                                u32 gt_iir)
1291 {
1292         if (gt_iir &
1293             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1294                 notify_ring(dev, &dev_priv->ring[RCS]);
1295         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1296                 notify_ring(dev, &dev_priv->ring[VCS]);
1297 }
1298
1299 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1300 {
1301         struct drm_device *dev = (struct drm_device *) arg;
1302         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1303         int ret = IRQ_NONE;
1304         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1305
1306         atomic_inc(&dev_priv->irq_received);
1307
1308         /* disable master interrupt before clearing iir  */
1309         de_ier = I915_READ(DEIER);
1310         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1311         POSTING_READ(DEIER);
1312
1313         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1314          * interrupts will will be stored on its back queue, and then we'll be
1315          * able to process them after we restore SDEIER (as soon as we restore
1316          * it, we'll get an interrupt if SDEIIR still has something to process
1317          * due to its back queue). */
1318         sde_ier = I915_READ(SDEIER);
1319         I915_WRITE(SDEIER, 0);
1320         POSTING_READ(SDEIER);
1321
1322         de_iir = I915_READ(DEIIR);
1323         gt_iir = I915_READ(GTIIR);
1324         pm_iir = I915_READ(GEN6_PMIIR);
1325
1326         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
1327                 goto done;
1328
1329         ret = IRQ_HANDLED;
1330
1331         if (IS_GEN5(dev))
1332                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1333         else
1334                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1335
1336         if (de_iir & DE_AUX_CHANNEL_A)
1337                 dp_aux_irq_handler(dev);
1338
1339         if (de_iir & DE_GSE)
1340                 intel_opregion_asle_intr(dev);
1341
1342         if (de_iir & DE_PIPEA_VBLANK)
1343                 drm_handle_vblank(dev, 0);
1344
1345         if (de_iir & DE_PIPEB_VBLANK)
1346                 drm_handle_vblank(dev, 1);
1347
1348         if (de_iir & DE_POISON)
1349                 DRM_ERROR("Poison interrupt\n");
1350
1351         if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1352                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1353                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1354
1355         if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1356                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1357                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1358
1359         if (de_iir & DE_PLANEA_FLIP_DONE) {
1360                 intel_prepare_page_flip(dev, 0);
1361                 intel_finish_page_flip_plane(dev, 0);
1362         }
1363
1364         if (de_iir & DE_PLANEB_FLIP_DONE) {
1365                 intel_prepare_page_flip(dev, 1);
1366                 intel_finish_page_flip_plane(dev, 1);
1367         }
1368
1369         /* check event from PCH */
1370         if (de_iir & DE_PCH_EVENT) {
1371                 u32 pch_iir = I915_READ(SDEIIR);
1372
1373                 if (HAS_PCH_CPT(dev))
1374                         cpt_irq_handler(dev, pch_iir);
1375                 else
1376                         ibx_irq_handler(dev, pch_iir);
1377
1378                 /* should clear PCH hotplug event before clear CPU irq */
1379                 I915_WRITE(SDEIIR, pch_iir);
1380         }
1381
1382         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
1383                 ironlake_handle_rps_change(dev);
1384
1385         if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
1386                 gen6_queue_rps_work(dev_priv, pm_iir);
1387
1388         I915_WRITE(GTIIR, gt_iir);
1389         I915_WRITE(DEIIR, de_iir);
1390         I915_WRITE(GEN6_PMIIR, pm_iir);
1391
1392 done:
1393         I915_WRITE(DEIER, de_ier);
1394         POSTING_READ(DEIER);
1395         I915_WRITE(SDEIER, sde_ier);
1396         POSTING_READ(SDEIER);
1397
1398         return ret;
1399 }
1400
1401 /**
1402  * i915_error_work_func - do process context error handling work
1403  * @work: work struct
1404  *
1405  * Fire an error uevent so userspace can see that a hang or error
1406  * was detected.
1407  */
1408 static void i915_error_work_func(struct work_struct *work)
1409 {
1410         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1411                                                     work);
1412         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1413                                                     gpu_error);
1414         struct drm_device *dev = dev_priv->dev;
1415         struct intel_ring_buffer *ring;
1416         char *error_event[] = { "ERROR=1", NULL };
1417         char *reset_event[] = { "RESET=1", NULL };
1418         char *reset_done_event[] = { "ERROR=0", NULL };
1419         int i, ret;
1420
1421         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1422
1423         /*
1424          * Note that there's only one work item which does gpu resets, so we
1425          * need not worry about concurrent gpu resets potentially incrementing
1426          * error->reset_counter twice. We only need to take care of another
1427          * racing irq/hangcheck declaring the gpu dead for a second time. A
1428          * quick check for that is good enough: schedule_work ensures the
1429          * correct ordering between hang detection and this work item, and since
1430          * the reset in-progress bit is only ever set by code outside of this
1431          * work we don't need to worry about any other races.
1432          */
1433         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1434                 DRM_DEBUG_DRIVER("resetting chip\n");
1435                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1436                                    reset_event);
1437
1438                 ret = i915_reset(dev);
1439
1440                 if (ret == 0) {
1441                         /*
1442                          * After all the gem state is reset, increment the reset
1443                          * counter and wake up everyone waiting for the reset to
1444                          * complete.
1445                          *
1446                          * Since unlock operations are a one-sided barrier only,
1447                          * we need to insert a barrier here to order any seqno
1448                          * updates before
1449                          * the counter increment.
1450                          */
1451                         smp_mb__before_atomic_inc();
1452                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1453
1454                         kobject_uevent_env(&dev->primary->kdev.kobj,
1455                                            KOBJ_CHANGE, reset_done_event);
1456                 } else {
1457                         atomic_set(&error->reset_counter, I915_WEDGED);
1458                 }
1459
1460                 for_each_ring(ring, dev_priv, i)
1461                         wake_up_all(&ring->irq_queue);
1462
1463                 intel_display_handle_reset(dev);
1464
1465                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1466         }
1467 }
1468
1469 /* NB: please notice the memset */
1470 static void i915_get_extra_instdone(struct drm_device *dev,
1471                                     uint32_t *instdone)
1472 {
1473         struct drm_i915_private *dev_priv = dev->dev_private;
1474         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1475
1476         switch(INTEL_INFO(dev)->gen) {
1477         case 2:
1478         case 3:
1479                 instdone[0] = I915_READ(INSTDONE);
1480                 break;
1481         case 4:
1482         case 5:
1483         case 6:
1484                 instdone[0] = I915_READ(INSTDONE_I965);
1485                 instdone[1] = I915_READ(INSTDONE1);
1486                 break;
1487         default:
1488                 WARN_ONCE(1, "Unsupported platform\n");
1489         case 7:
1490                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1491                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1492                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1493                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1494                 break;
1495         }
1496 }
1497
1498 #ifdef CONFIG_DEBUG_FS
1499 static struct drm_i915_error_object *
1500 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1501                                struct drm_i915_gem_object *src,
1502                                const int num_pages)
1503 {
1504         struct drm_i915_error_object *dst;
1505         int i;
1506         u32 reloc_offset;
1507
1508         if (src == NULL || src->pages == NULL)
1509                 return NULL;
1510
1511         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1512         if (dst == NULL)
1513                 return NULL;
1514
1515         reloc_offset = src->gtt_offset;
1516         for (i = 0; i < num_pages; i++) {
1517                 unsigned long flags;
1518                 void *d;
1519
1520                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1521                 if (d == NULL)
1522                         goto unwind;
1523
1524                 local_irq_save(flags);
1525                 if (reloc_offset < dev_priv->gtt.mappable_end &&
1526                     src->has_global_gtt_mapping) {
1527                         void __iomem *s;
1528
1529                         /* Simply ignore tiling or any overlapping fence.
1530                          * It's part of the error state, and this hopefully
1531                          * captures what the GPU read.
1532                          */
1533
1534                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1535                                                      reloc_offset);
1536                         memcpy_fromio(d, s, PAGE_SIZE);
1537                         io_mapping_unmap_atomic(s);
1538                 } else if (src->stolen) {
1539                         unsigned long offset;
1540
1541                         offset = dev_priv->mm.stolen_base;
1542                         offset += src->stolen->start;
1543                         offset += i << PAGE_SHIFT;
1544
1545                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1546                 } else {
1547                         struct page *page;
1548                         void *s;
1549
1550                         page = i915_gem_object_get_page(src, i);
1551
1552                         drm_clflush_pages(&page, 1);
1553
1554                         s = kmap_atomic(page);
1555                         memcpy(d, s, PAGE_SIZE);
1556                         kunmap_atomic(s);
1557
1558                         drm_clflush_pages(&page, 1);
1559                 }
1560                 local_irq_restore(flags);
1561
1562                 dst->pages[i] = d;
1563
1564                 reloc_offset += PAGE_SIZE;
1565         }
1566         dst->page_count = num_pages;
1567         dst->gtt_offset = src->gtt_offset;
1568
1569         return dst;
1570
1571 unwind:
1572         while (i--)
1573                 kfree(dst->pages[i]);
1574         kfree(dst);
1575         return NULL;
1576 }
1577 #define i915_error_object_create(dev_priv, src) \
1578         i915_error_object_create_sized((dev_priv), (src), \
1579                                        (src)->base.size>>PAGE_SHIFT)
1580
1581 static void
1582 i915_error_object_free(struct drm_i915_error_object *obj)
1583 {
1584         int page;
1585
1586         if (obj == NULL)
1587                 return;
1588
1589         for (page = 0; page < obj->page_count; page++)
1590                 kfree(obj->pages[page]);
1591
1592         kfree(obj);
1593 }
1594
1595 void
1596 i915_error_state_free(struct kref *error_ref)
1597 {
1598         struct drm_i915_error_state *error = container_of(error_ref,
1599                                                           typeof(*error), ref);
1600         int i;
1601
1602         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1603                 i915_error_object_free(error->ring[i].batchbuffer);
1604                 i915_error_object_free(error->ring[i].ringbuffer);
1605                 i915_error_object_free(error->ring[i].ctx);
1606                 kfree(error->ring[i].requests);
1607         }
1608
1609         kfree(error->active_bo);
1610         kfree(error->overlay);
1611         kfree(error->display);
1612         kfree(error);
1613 }
1614 static void capture_bo(struct drm_i915_error_buffer *err,
1615                        struct drm_i915_gem_object *obj)
1616 {
1617         err->size = obj->base.size;
1618         err->name = obj->base.name;
1619         err->rseqno = obj->last_read_seqno;
1620         err->wseqno = obj->last_write_seqno;
1621         err->gtt_offset = obj->gtt_offset;
1622         err->read_domains = obj->base.read_domains;
1623         err->write_domain = obj->base.write_domain;
1624         err->fence_reg = obj->fence_reg;
1625         err->pinned = 0;
1626         if (obj->pin_count > 0)
1627                 err->pinned = 1;
1628         if (obj->user_pin_count > 0)
1629                 err->pinned = -1;
1630         err->tiling = obj->tiling_mode;
1631         err->dirty = obj->dirty;
1632         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1633         err->ring = obj->ring ? obj->ring->id : -1;
1634         err->cache_level = obj->cache_level;
1635 }
1636
1637 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1638                              int count, struct list_head *head)
1639 {
1640         struct drm_i915_gem_object *obj;
1641         int i = 0;
1642
1643         list_for_each_entry(obj, head, mm_list) {
1644                 capture_bo(err++, obj);
1645                 if (++i == count)
1646                         break;
1647         }
1648
1649         return i;
1650 }
1651
1652 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1653                              int count, struct list_head *head)
1654 {
1655         struct drm_i915_gem_object *obj;
1656         int i = 0;
1657
1658         list_for_each_entry(obj, head, global_list) {
1659                 if (obj->pin_count == 0)
1660                         continue;
1661
1662                 capture_bo(err++, obj);
1663                 if (++i == count)
1664                         break;
1665         }
1666
1667         return i;
1668 }
1669
1670 static void i915_gem_record_fences(struct drm_device *dev,
1671                                    struct drm_i915_error_state *error)
1672 {
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         int i;
1675
1676         /* Fences */
1677         switch (INTEL_INFO(dev)->gen) {
1678         case 7:
1679         case 6:
1680                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1681                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1682                 break;
1683         case 5:
1684         case 4:
1685                 for (i = 0; i < 16; i++)
1686                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1687                 break;
1688         case 3:
1689                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1690                         for (i = 0; i < 8; i++)
1691                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1692         case 2:
1693                 for (i = 0; i < 8; i++)
1694                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1695                 break;
1696
1697         default:
1698                 BUG();
1699         }
1700 }
1701
1702 static struct drm_i915_error_object *
1703 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1704                              struct intel_ring_buffer *ring)
1705 {
1706         struct drm_i915_gem_object *obj;
1707         u32 seqno;
1708
1709         if (!ring->get_seqno)
1710                 return NULL;
1711
1712         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1713                 u32 acthd = I915_READ(ACTHD);
1714
1715                 if (WARN_ON(ring->id != RCS))
1716                         return NULL;
1717
1718                 obj = ring->private;
1719                 if (acthd >= obj->gtt_offset &&
1720                     acthd < obj->gtt_offset + obj->base.size)
1721                         return i915_error_object_create(dev_priv, obj);
1722         }
1723
1724         seqno = ring->get_seqno(ring, false);
1725         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1726                 if (obj->ring != ring)
1727                         continue;
1728
1729                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1730                         continue;
1731
1732                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1733                         continue;
1734
1735                 /* We need to copy these to an anonymous buffer as the simplest
1736                  * method to avoid being overwritten by userspace.
1737                  */
1738                 return i915_error_object_create(dev_priv, obj);
1739         }
1740
1741         return NULL;
1742 }
1743
1744 static void i915_record_ring_state(struct drm_device *dev,
1745                                    struct drm_i915_error_state *error,
1746                                    struct intel_ring_buffer *ring)
1747 {
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749
1750         if (INTEL_INFO(dev)->gen >= 6) {
1751                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1752                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1753                 error->semaphore_mboxes[ring->id][0]
1754                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1755                 error->semaphore_mboxes[ring->id][1]
1756                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1757                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1758                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1759         }
1760
1761         if (INTEL_INFO(dev)->gen >= 4) {
1762                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1763                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1764                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1765                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1766                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1767                 if (ring->id == RCS)
1768                         error->bbaddr = I915_READ64(BB_ADDR);
1769         } else {
1770                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1771                 error->ipeir[ring->id] = I915_READ(IPEIR);
1772                 error->ipehr[ring->id] = I915_READ(IPEHR);
1773                 error->instdone[ring->id] = I915_READ(INSTDONE);
1774         }
1775
1776         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1777         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1778         error->seqno[ring->id] = ring->get_seqno(ring, false);
1779         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1780         error->head[ring->id] = I915_READ_HEAD(ring);
1781         error->tail[ring->id] = I915_READ_TAIL(ring);
1782         error->ctl[ring->id] = I915_READ_CTL(ring);
1783
1784         error->cpu_ring_head[ring->id] = ring->head;
1785         error->cpu_ring_tail[ring->id] = ring->tail;
1786 }
1787
1788
1789 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1790                                            struct drm_i915_error_state *error,
1791                                            struct drm_i915_error_ring *ering)
1792 {
1793         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1794         struct drm_i915_gem_object *obj;
1795
1796         /* Currently render ring is the only HW context user */
1797         if (ring->id != RCS || !error->ccid)
1798                 return;
1799
1800         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1801                 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1802                         ering->ctx = i915_error_object_create_sized(dev_priv,
1803                                                                     obj, 1);
1804                 }
1805         }
1806 }
1807
1808 static void i915_gem_record_rings(struct drm_device *dev,
1809                                   struct drm_i915_error_state *error)
1810 {
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         struct intel_ring_buffer *ring;
1813         struct drm_i915_gem_request *request;
1814         int i, count;
1815
1816         for_each_ring(ring, dev_priv, i) {
1817                 i915_record_ring_state(dev, error, ring);
1818
1819                 error->ring[i].batchbuffer =
1820                         i915_error_first_batchbuffer(dev_priv, ring);
1821
1822                 error->ring[i].ringbuffer =
1823                         i915_error_object_create(dev_priv, ring->obj);
1824
1825
1826                 i915_gem_record_active_context(ring, error, &error->ring[i]);
1827
1828                 count = 0;
1829                 list_for_each_entry(request, &ring->request_list, list)
1830                         count++;
1831
1832                 error->ring[i].num_requests = count;
1833                 error->ring[i].requests =
1834                         kmalloc(count*sizeof(struct drm_i915_error_request),
1835                                 GFP_ATOMIC);
1836                 if (error->ring[i].requests == NULL) {
1837                         error->ring[i].num_requests = 0;
1838                         continue;
1839                 }
1840
1841                 count = 0;
1842                 list_for_each_entry(request, &ring->request_list, list) {
1843                         struct drm_i915_error_request *erq;
1844
1845                         erq = &error->ring[i].requests[count++];
1846                         erq->seqno = request->seqno;
1847                         erq->jiffies = request->emitted_jiffies;
1848                         erq->tail = request->tail;
1849                 }
1850         }
1851 }
1852
1853 /**
1854  * i915_capture_error_state - capture an error record for later analysis
1855  * @dev: drm device
1856  *
1857  * Should be called when an error is detected (either a hang or an error
1858  * interrupt) to capture error state from the time of the error.  Fills
1859  * out a structure which becomes available in debugfs for user level tools
1860  * to pick up.
1861  */
1862 static void i915_capture_error_state(struct drm_device *dev)
1863 {
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865         struct drm_i915_gem_object *obj;
1866         struct drm_i915_error_state *error;
1867         unsigned long flags;
1868         int i, pipe;
1869
1870         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1871         error = dev_priv->gpu_error.first_error;
1872         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1873         if (error)
1874                 return;
1875
1876         /* Account for pipe specific data like PIPE*STAT */
1877         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1878         if (!error) {
1879                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1880                 return;
1881         }
1882
1883         DRM_INFO("capturing error event; look for more information in "
1884                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1885                  dev->primary->index);
1886
1887         kref_init(&error->ref);
1888         error->eir = I915_READ(EIR);
1889         error->pgtbl_er = I915_READ(PGTBL_ER);
1890         if (HAS_HW_CONTEXTS(dev))
1891                 error->ccid = I915_READ(CCID);
1892
1893         if (HAS_PCH_SPLIT(dev))
1894                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1895         else if (IS_VALLEYVIEW(dev))
1896                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1897         else if (IS_GEN2(dev))
1898                 error->ier = I915_READ16(IER);
1899         else
1900                 error->ier = I915_READ(IER);
1901
1902         if (INTEL_INFO(dev)->gen >= 6)
1903                 error->derrmr = I915_READ(DERRMR);
1904
1905         if (IS_VALLEYVIEW(dev))
1906                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1907         else if (INTEL_INFO(dev)->gen >= 7)
1908                 error->forcewake = I915_READ(FORCEWAKE_MT);
1909         else if (INTEL_INFO(dev)->gen == 6)
1910                 error->forcewake = I915_READ(FORCEWAKE);
1911
1912         if (!HAS_PCH_SPLIT(dev))
1913                 for_each_pipe(pipe)
1914                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1915
1916         if (INTEL_INFO(dev)->gen >= 6) {
1917                 error->error = I915_READ(ERROR_GEN6);
1918                 error->done_reg = I915_READ(DONE_REG);
1919         }
1920
1921         if (INTEL_INFO(dev)->gen == 7)
1922                 error->err_int = I915_READ(GEN7_ERR_INT);
1923
1924         i915_get_extra_instdone(dev, error->extra_instdone);
1925
1926         i915_gem_record_fences(dev, error);
1927         i915_gem_record_rings(dev, error);
1928
1929         /* Record buffers on the active and pinned lists. */
1930         error->active_bo = NULL;
1931         error->pinned_bo = NULL;
1932
1933         i = 0;
1934         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1935                 i++;
1936         error->active_bo_count = i;
1937         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1938                 if (obj->pin_count)
1939                         i++;
1940         error->pinned_bo_count = i - error->active_bo_count;
1941
1942         error->active_bo = NULL;
1943         error->pinned_bo = NULL;
1944         if (i) {
1945                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1946                                            GFP_ATOMIC);
1947                 if (error->active_bo)
1948                         error->pinned_bo =
1949                                 error->active_bo + error->active_bo_count;
1950         }
1951
1952         if (error->active_bo)
1953                 error->active_bo_count =
1954                         capture_active_bo(error->active_bo,
1955                                           error->active_bo_count,
1956                                           &dev_priv->mm.active_list);
1957
1958         if (error->pinned_bo)
1959                 error->pinned_bo_count =
1960                         capture_pinned_bo(error->pinned_bo,
1961                                           error->pinned_bo_count,
1962                                           &dev_priv->mm.bound_list);
1963
1964         do_gettimeofday(&error->time);
1965
1966         error->overlay = intel_overlay_capture_error_state(dev);
1967         error->display = intel_display_capture_error_state(dev);
1968
1969         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1970         if (dev_priv->gpu_error.first_error == NULL) {
1971                 dev_priv->gpu_error.first_error = error;
1972                 error = NULL;
1973         }
1974         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1975
1976         if (error)
1977                 i915_error_state_free(&error->ref);
1978 }
1979
1980 void i915_destroy_error_state(struct drm_device *dev)
1981 {
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         struct drm_i915_error_state *error;
1984         unsigned long flags;
1985
1986         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1987         error = dev_priv->gpu_error.first_error;
1988         dev_priv->gpu_error.first_error = NULL;
1989         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1990
1991         if (error)
1992                 kref_put(&error->ref, i915_error_state_free);
1993 }
1994 #else
1995 #define i915_capture_error_state(x)
1996 #endif
1997
1998 static void i915_report_and_clear_eir(struct drm_device *dev)
1999 {
2000         struct drm_i915_private *dev_priv = dev->dev_private;
2001         uint32_t instdone[I915_NUM_INSTDONE_REG];
2002         u32 eir = I915_READ(EIR);
2003         int pipe, i;
2004
2005         if (!eir)
2006                 return;
2007
2008         pr_err("render error detected, EIR: 0x%08x\n", eir);
2009
2010         i915_get_extra_instdone(dev, instdone);
2011
2012         if (IS_G4X(dev)) {
2013                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2014                         u32 ipeir = I915_READ(IPEIR_I965);
2015
2016                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2017                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2018                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2019                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2020                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2021                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2022                         I915_WRITE(IPEIR_I965, ipeir);
2023                         POSTING_READ(IPEIR_I965);
2024                 }
2025                 if (eir & GM45_ERROR_PAGE_TABLE) {
2026                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2027                         pr_err("page table error\n");
2028                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2029                         I915_WRITE(PGTBL_ER, pgtbl_err);
2030                         POSTING_READ(PGTBL_ER);
2031                 }
2032         }
2033
2034         if (!IS_GEN2(dev)) {
2035                 if (eir & I915_ERROR_PAGE_TABLE) {
2036                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2037                         pr_err("page table error\n");
2038                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2039                         I915_WRITE(PGTBL_ER, pgtbl_err);
2040                         POSTING_READ(PGTBL_ER);
2041                 }
2042         }
2043
2044         if (eir & I915_ERROR_MEMORY_REFRESH) {
2045                 pr_err("memory refresh error:\n");
2046                 for_each_pipe(pipe)
2047                         pr_err("pipe %c stat: 0x%08x\n",
2048                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2049                 /* pipestat has already been acked */
2050         }
2051         if (eir & I915_ERROR_INSTRUCTION) {
2052                 pr_err("instruction error\n");
2053                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2054                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2055                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2056                 if (INTEL_INFO(dev)->gen < 4) {
2057                         u32 ipeir = I915_READ(IPEIR);
2058
2059                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2060                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2061                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2062                         I915_WRITE(IPEIR, ipeir);
2063                         POSTING_READ(IPEIR);
2064                 } else {
2065                         u32 ipeir = I915_READ(IPEIR_I965);
2066
2067                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2068                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2069                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2070                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2071                         I915_WRITE(IPEIR_I965, ipeir);
2072                         POSTING_READ(IPEIR_I965);
2073                 }
2074         }
2075
2076         I915_WRITE(EIR, eir);
2077         POSTING_READ(EIR);
2078         eir = I915_READ(EIR);
2079         if (eir) {
2080                 /*
2081                  * some errors might have become stuck,
2082                  * mask them.
2083                  */
2084                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2085                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2086                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2087         }
2088 }
2089
2090 /**
2091  * i915_handle_error - handle an error interrupt
2092  * @dev: drm device
2093  *
2094  * Do some basic checking of regsiter state at error interrupt time and
2095  * dump it to the syslog.  Also call i915_capture_error_state() to make
2096  * sure we get a record and make it available in debugfs.  Fire a uevent
2097  * so userspace knows something bad happened (should trigger collection
2098  * of a ring dump etc.).
2099  */
2100 void i915_handle_error(struct drm_device *dev, bool wedged)
2101 {
2102         struct drm_i915_private *dev_priv = dev->dev_private;
2103         struct intel_ring_buffer *ring;
2104         int i;
2105
2106         i915_capture_error_state(dev);
2107         i915_report_and_clear_eir(dev);
2108
2109         if (wedged) {
2110                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2111                                 &dev_priv->gpu_error.reset_counter);
2112
2113                 /*
2114                  * Wakeup waiting processes so that the reset work item
2115                  * doesn't deadlock trying to grab various locks.
2116                  */
2117                 for_each_ring(ring, dev_priv, i)
2118                         wake_up_all(&ring->irq_queue);
2119         }
2120
2121         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
2122 }
2123
2124 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2125 {
2126         drm_i915_private_t *dev_priv = dev->dev_private;
2127         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2129         struct drm_i915_gem_object *obj;
2130         struct intel_unpin_work *work;
2131         unsigned long flags;
2132         bool stall_detected;
2133
2134         /* Ignore early vblank irqs */
2135         if (intel_crtc == NULL)
2136                 return;
2137
2138         spin_lock_irqsave(&dev->event_lock, flags);
2139         work = intel_crtc->unpin_work;
2140
2141         if (work == NULL ||
2142             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2143             !work->enable_stall_check) {
2144                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2145                 spin_unlock_irqrestore(&dev->event_lock, flags);
2146                 return;
2147         }
2148
2149         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2150         obj = work->pending_flip_obj;
2151         if (INTEL_INFO(dev)->gen >= 4) {
2152                 int dspsurf = DSPSURF(intel_crtc->plane);
2153                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2154                                         obj->gtt_offset;
2155         } else {
2156                 int dspaddr = DSPADDR(intel_crtc->plane);
2157                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
2158                                                         crtc->y * crtc->fb->pitches[0] +
2159                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2160         }
2161
2162         spin_unlock_irqrestore(&dev->event_lock, flags);
2163
2164         if (stall_detected) {
2165                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2166                 intel_prepare_page_flip(dev, intel_crtc->plane);
2167         }
2168 }
2169
2170 /* Called from drm generic code, passed 'crtc' which
2171  * we use as a pipe index
2172  */
2173 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2174 {
2175         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2176         unsigned long irqflags;
2177
2178         if (!i915_pipe_enabled(dev, pipe))
2179                 return -EINVAL;
2180
2181         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2182         if (INTEL_INFO(dev)->gen >= 4)
2183                 i915_enable_pipestat(dev_priv, pipe,
2184                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
2185         else
2186                 i915_enable_pipestat(dev_priv, pipe,
2187                                      PIPE_VBLANK_INTERRUPT_ENABLE);
2188
2189         /* maintain vblank delivery even in deep C-states */
2190         if (dev_priv->info->gen == 3)
2191                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2192         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2193
2194         return 0;
2195 }
2196
2197 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2198 {
2199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2200         unsigned long irqflags;
2201
2202         if (!i915_pipe_enabled(dev, pipe))
2203                 return -EINVAL;
2204
2205         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2206         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
2207                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2208         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2209
2210         return 0;
2211 }
2212
2213 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
2214 {
2215         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2216         unsigned long irqflags;
2217
2218         if (!i915_pipe_enabled(dev, pipe))
2219                 return -EINVAL;
2220
2221         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2222         ironlake_enable_display_irq(dev_priv,
2223                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
2224         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2225
2226         return 0;
2227 }
2228
2229 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2230 {
2231         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2232         unsigned long irqflags;
2233         u32 imr;
2234
2235         if (!i915_pipe_enabled(dev, pipe))
2236                 return -EINVAL;
2237
2238         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2239         imr = I915_READ(VLV_IMR);
2240         if (pipe == 0)
2241                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2242         else
2243                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2244         I915_WRITE(VLV_IMR, imr);
2245         i915_enable_pipestat(dev_priv, pipe,
2246                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
2247         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2248
2249         return 0;
2250 }
2251
2252 /* Called from drm generic code, passed 'crtc' which
2253  * we use as a pipe index
2254  */
2255 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2256 {
2257         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2258         unsigned long irqflags;
2259
2260         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2261         if (dev_priv->info->gen == 3)
2262                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2263
2264         i915_disable_pipestat(dev_priv, pipe,
2265                               PIPE_VBLANK_INTERRUPT_ENABLE |
2266                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2267         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2268 }
2269
2270 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2271 {
2272         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2273         unsigned long irqflags;
2274
2275         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2276         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
2277                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2278         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2279 }
2280
2281 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
2282 {
2283         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2284         unsigned long irqflags;
2285
2286         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2287         ironlake_disable_display_irq(dev_priv,
2288                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
2289         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2290 }
2291
2292 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2293 {
2294         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2295         unsigned long irqflags;
2296         u32 imr;
2297
2298         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2299         i915_disable_pipestat(dev_priv, pipe,
2300                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2301         imr = I915_READ(VLV_IMR);
2302         if (pipe == 0)
2303                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2304         else
2305                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2306         I915_WRITE(VLV_IMR, imr);
2307         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2308 }
2309
2310 static u32
2311 ring_last_seqno(struct intel_ring_buffer *ring)
2312 {
2313         return list_entry(ring->request_list.prev,
2314                           struct drm_i915_gem_request, list)->seqno;
2315 }
2316
2317 static bool
2318 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2319 {
2320         return (list_empty(&ring->request_list) ||
2321                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2322 }
2323
2324 static struct intel_ring_buffer *
2325 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2326 {
2327         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2328         u32 cmd, ipehr, acthd, acthd_min;
2329
2330         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2331         if ((ipehr & ~(0x3 << 16)) !=
2332             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2333                 return NULL;
2334
2335         /* ACTHD is likely pointing to the dword after the actual command,
2336          * so scan backwards until we find the MBOX.
2337          */
2338         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2339         acthd_min = max((int)acthd - 3 * 4, 0);
2340         do {
2341                 cmd = ioread32(ring->virtual_start + acthd);
2342                 if (cmd == ipehr)
2343                         break;
2344
2345                 acthd -= 4;
2346                 if (acthd < acthd_min)
2347                         return NULL;
2348         } while (1);
2349
2350         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2351         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2352 }
2353
2354 static int semaphore_passed(struct intel_ring_buffer *ring)
2355 {
2356         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2357         struct intel_ring_buffer *signaller;
2358         u32 seqno, ctl;
2359
2360         ring->hangcheck.deadlock = true;
2361
2362         signaller = semaphore_waits_for(ring, &seqno);
2363         if (signaller == NULL || signaller->hangcheck.deadlock)
2364                 return -1;
2365
2366         /* cursory check for an unkickable deadlock */
2367         ctl = I915_READ_CTL(signaller);
2368         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2369                 return -1;
2370
2371         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2372 }
2373
2374 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2375 {
2376         struct intel_ring_buffer *ring;
2377         int i;
2378
2379         for_each_ring(ring, dev_priv, i)
2380                 ring->hangcheck.deadlock = false;
2381 }
2382
2383 static enum { wait, active, kick, hung } ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2384 {
2385         struct drm_device *dev = ring->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         u32 tmp;
2388
2389         if (ring->hangcheck.acthd != acthd)
2390                 return active;
2391
2392         if (IS_GEN2(dev))
2393                 return hung;
2394
2395         /* Is the chip hanging on a WAIT_FOR_EVENT?
2396          * If so we can simply poke the RB_WAIT bit
2397          * and break the hang. This should work on
2398          * all but the second generation chipsets.
2399          */
2400         tmp = I915_READ_CTL(ring);
2401         if (tmp & RING_WAIT) {
2402                 DRM_ERROR("Kicking stuck wait on %s\n",
2403                           ring->name);
2404                 I915_WRITE_CTL(ring, tmp);
2405                 return kick;
2406         }
2407
2408         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2409                 switch (semaphore_passed(ring)) {
2410                 default:
2411                         return hung;
2412                 case 1:
2413                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2414                                   ring->name);
2415                         I915_WRITE_CTL(ring, tmp);
2416                         return kick;
2417                 case 0:
2418                         return wait;
2419                 }
2420         }
2421
2422         return hung;
2423 }
2424
2425 /**
2426  * This is called when the chip hasn't reported back with completed
2427  * batchbuffers in a long time. We keep track per ring seqno progress and
2428  * if there are no progress, hangcheck score for that ring is increased.
2429  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2430  * we kick the ring. If we see no progress on three subsequent calls
2431  * we assume chip is wedged and try to fix it by resetting the chip.
2432  */
2433 void i915_hangcheck_elapsed(unsigned long data)
2434 {
2435         struct drm_device *dev = (struct drm_device *)data;
2436         drm_i915_private_t *dev_priv = dev->dev_private;
2437         struct intel_ring_buffer *ring;
2438         int i;
2439         int busy_count = 0, rings_hung = 0;
2440         bool stuck[I915_NUM_RINGS] = { 0 };
2441 #define BUSY 1
2442 #define KICK 5
2443 #define HUNG 20
2444 #define FIRE 30
2445
2446         if (!i915_enable_hangcheck)
2447                 return;
2448
2449         for_each_ring(ring, dev_priv, i) {
2450                 u32 seqno, acthd;
2451                 bool busy = true;
2452
2453                 semaphore_clear_deadlocks(dev_priv);
2454
2455                 seqno = ring->get_seqno(ring, false);
2456                 acthd = intel_ring_get_active_head(ring);
2457
2458                 if (ring->hangcheck.seqno == seqno) {
2459                         if (ring_idle(ring, seqno)) {
2460                                 if (waitqueue_active(&ring->irq_queue)) {
2461                                         /* Issue a wake-up to catch stuck h/w. */
2462                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2463                                                   ring->name);
2464                                         wake_up_all(&ring->irq_queue);
2465                                         ring->hangcheck.score += HUNG;
2466                                 } else
2467                                         busy = false;
2468                         } else {
2469                                 int score;
2470
2471                                 /* We always increment the hangcheck score
2472                                  * if the ring is busy and still processing
2473                                  * the same request, so that no single request
2474                                  * can run indefinitely (such as a chain of
2475                                  * batches). The only time we do not increment
2476                                  * the hangcheck score on this ring, if this
2477                                  * ring is in a legitimate wait for another
2478                                  * ring. In that case the waiting ring is a
2479                                  * victim and we want to be sure we catch the
2480                                  * right culprit. Then every time we do kick
2481                                  * the ring, add a small increment to the
2482                                  * score so that we can catch a batch that is
2483                                  * being repeatedly kicked and so responsible
2484                                  * for stalling the machine.
2485                                  */
2486                                 switch (ring_stuck(ring, acthd)) {
2487                                 case wait:
2488                                         score = 0;
2489                                         break;
2490                                 case active:
2491                                         score = BUSY;
2492                                         break;
2493                                 case kick:
2494                                         score = KICK;
2495                                         break;
2496                                 case hung:
2497                                         score = HUNG;
2498                                         stuck[i] = true;
2499                                         break;
2500                                 }
2501                                 ring->hangcheck.score += score;
2502                         }
2503                 } else {
2504                         /* Gradually reduce the count so that we catch DoS
2505                          * attempts across multiple batches.
2506                          */
2507                         if (ring->hangcheck.score > 0)
2508                                 ring->hangcheck.score--;
2509                 }
2510
2511                 ring->hangcheck.seqno = seqno;
2512                 ring->hangcheck.acthd = acthd;
2513                 busy_count += busy;
2514         }
2515
2516         for_each_ring(ring, dev_priv, i) {
2517                 if (ring->hangcheck.score > FIRE) {
2518                         DRM_ERROR("%s on %s ring\n",
2519                                   stuck[i] ? "stuck" : "no progress",
2520                                   ring->name);
2521                         rings_hung++;
2522                 }
2523         }
2524
2525         if (rings_hung)
2526                 return i915_handle_error(dev, true);
2527
2528         if (busy_count)
2529                 /* Reset timer case chip hangs without another request
2530                  * being added */
2531                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2532                           round_jiffies_up(jiffies +
2533                                            DRM_I915_HANGCHECK_JIFFIES));
2534 }
2535
2536 static void ibx_irq_preinstall(struct drm_device *dev)
2537 {
2538         struct drm_i915_private *dev_priv = dev->dev_private;
2539
2540         if (HAS_PCH_NOP(dev))
2541                 return;
2542
2543         /* south display irq */
2544         I915_WRITE(SDEIMR, 0xffffffff);
2545         /*
2546          * SDEIER is also touched by the interrupt handler to work around missed
2547          * PCH interrupts. Hence we can't update it after the interrupt handler
2548          * is enabled - instead we unconditionally enable all PCH interrupt
2549          * sources here, but then only unmask them as needed with SDEIMR.
2550          */
2551         I915_WRITE(SDEIER, 0xffffffff);
2552         POSTING_READ(SDEIER);
2553 }
2554
2555 /* drm_dma.h hooks
2556 */
2557 static void ironlake_irq_preinstall(struct drm_device *dev)
2558 {
2559         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2560
2561         atomic_set(&dev_priv->irq_received, 0);
2562
2563         I915_WRITE(HWSTAM, 0xeffe);
2564
2565         /* XXX hotplug from PCH */
2566
2567         I915_WRITE(DEIMR, 0xffffffff);
2568         I915_WRITE(DEIER, 0x0);
2569         POSTING_READ(DEIER);
2570
2571         /* and GT */
2572         I915_WRITE(GTIMR, 0xffffffff);
2573         I915_WRITE(GTIER, 0x0);
2574         POSTING_READ(GTIER);
2575
2576         ibx_irq_preinstall(dev);
2577 }
2578
2579 static void ivybridge_irq_preinstall(struct drm_device *dev)
2580 {
2581         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2582
2583         atomic_set(&dev_priv->irq_received, 0);
2584
2585         I915_WRITE(HWSTAM, 0xeffe);
2586
2587         /* XXX hotplug from PCH */
2588
2589         I915_WRITE(DEIMR, 0xffffffff);
2590         I915_WRITE(DEIER, 0x0);
2591         POSTING_READ(DEIER);
2592
2593         /* and GT */
2594         I915_WRITE(GTIMR, 0xffffffff);
2595         I915_WRITE(GTIER, 0x0);
2596         POSTING_READ(GTIER);
2597
2598         /* Power management */
2599         I915_WRITE(GEN6_PMIMR, 0xffffffff);
2600         I915_WRITE(GEN6_PMIER, 0x0);
2601         POSTING_READ(GEN6_PMIER);
2602
2603         ibx_irq_preinstall(dev);
2604 }
2605
2606 static void valleyview_irq_preinstall(struct drm_device *dev)
2607 {
2608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2609         int pipe;
2610
2611         atomic_set(&dev_priv->irq_received, 0);
2612
2613         /* VLV magic */
2614         I915_WRITE(VLV_IMR, 0);
2615         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2616         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2617         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2618
2619         /* and GT */
2620         I915_WRITE(GTIIR, I915_READ(GTIIR));
2621         I915_WRITE(GTIIR, I915_READ(GTIIR));
2622         I915_WRITE(GTIMR, 0xffffffff);
2623         I915_WRITE(GTIER, 0x0);
2624         POSTING_READ(GTIER);
2625
2626         I915_WRITE(DPINVGTT, 0xff);
2627
2628         I915_WRITE(PORT_HOTPLUG_EN, 0);
2629         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2630         for_each_pipe(pipe)
2631                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2632         I915_WRITE(VLV_IIR, 0xffffffff);
2633         I915_WRITE(VLV_IMR, 0xffffffff);
2634         I915_WRITE(VLV_IER, 0x0);
2635         POSTING_READ(VLV_IER);
2636 }
2637
2638 static void ibx_hpd_irq_setup(struct drm_device *dev)
2639 {
2640         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2641         struct drm_mode_config *mode_config = &dev->mode_config;
2642         struct intel_encoder *intel_encoder;
2643         u32 mask = ~I915_READ(SDEIMR);
2644         u32 hotplug;
2645
2646         if (HAS_PCH_IBX(dev)) {
2647                 mask &= ~SDE_HOTPLUG_MASK;
2648                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2649                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2650                                 mask |= hpd_ibx[intel_encoder->hpd_pin];
2651         } else {
2652                 mask &= ~SDE_HOTPLUG_MASK_CPT;
2653                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2654                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2655                                 mask |= hpd_cpt[intel_encoder->hpd_pin];
2656         }
2657
2658         I915_WRITE(SDEIMR, ~mask);
2659
2660         /*
2661          * Enable digital hotplug on the PCH, and configure the DP short pulse
2662          * duration to 2ms (which is the minimum in the Display Port spec)
2663          *
2664          * This register is the same on all known PCH chips.
2665          */
2666         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2667         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2668         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2669         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2670         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2671         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2672 }
2673
2674 static void ibx_irq_postinstall(struct drm_device *dev)
2675 {
2676         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2677         u32 mask;
2678
2679         if (HAS_PCH_NOP(dev))
2680                 return;
2681
2682         if (HAS_PCH_IBX(dev)) {
2683                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2684                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2685         } else {
2686                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2687
2688                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2689         }
2690
2691         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2692         I915_WRITE(SDEIMR, ~mask);
2693 }
2694
2695 static int ironlake_irq_postinstall(struct drm_device *dev)
2696 {
2697         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2698         /* enable kind of interrupts always enabled */
2699         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2700                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2701                            DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2702                            DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
2703         u32 gt_irqs;
2704
2705         dev_priv->irq_mask = ~display_mask;
2706
2707         /* should always can generate irq */
2708         I915_WRITE(DEIIR, I915_READ(DEIIR));
2709         I915_WRITE(DEIMR, dev_priv->irq_mask);
2710         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2711         POSTING_READ(DEIER);
2712
2713         dev_priv->gt_irq_mask = ~0;
2714
2715         I915_WRITE(GTIIR, I915_READ(GTIIR));
2716         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2717
2718         gt_irqs = GT_RENDER_USER_INTERRUPT;
2719
2720         if (IS_GEN6(dev))
2721                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2722         else
2723                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2724                            ILK_BSD_USER_INTERRUPT;
2725
2726         I915_WRITE(GTIER, gt_irqs);
2727         POSTING_READ(GTIER);
2728
2729         ibx_irq_postinstall(dev);
2730
2731         if (IS_IRONLAKE_M(dev)) {
2732                 /* Clear & enable PCU event interrupts */
2733                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2734                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2735                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2736         }
2737
2738         return 0;
2739 }
2740
2741 static int ivybridge_irq_postinstall(struct drm_device *dev)
2742 {
2743         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2744         /* enable kind of interrupts always enabled */
2745         u32 display_mask =
2746                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2747                 DE_PLANEC_FLIP_DONE_IVB |
2748                 DE_PLANEB_FLIP_DONE_IVB |
2749                 DE_PLANEA_FLIP_DONE_IVB |
2750                 DE_AUX_CHANNEL_A_IVB |
2751                 DE_ERR_INT_IVB;
2752         u32 pm_irqs = GEN6_PM_RPS_EVENTS;
2753         u32 gt_irqs;
2754
2755         dev_priv->irq_mask = ~display_mask;
2756
2757         /* should always can generate irq */
2758         I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2759         I915_WRITE(DEIIR, I915_READ(DEIIR));
2760         I915_WRITE(DEIMR, dev_priv->irq_mask);
2761         I915_WRITE(DEIER,
2762                    display_mask |
2763                    DE_PIPEC_VBLANK_IVB |
2764                    DE_PIPEB_VBLANK_IVB |
2765                    DE_PIPEA_VBLANK_IVB);
2766         POSTING_READ(DEIER);
2767
2768         dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2769
2770         I915_WRITE(GTIIR, I915_READ(GTIIR));
2771         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2772
2773         gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2774                   GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2775         I915_WRITE(GTIER, gt_irqs);
2776         POSTING_READ(GTIER);
2777
2778         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2779         if (HAS_VEBOX(dev))
2780                 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2781                         PM_VEBOX_CS_ERROR_INTERRUPT;
2782
2783         /* Our enable/disable rps functions may touch these registers so
2784          * make sure to set a known state for only the non-RPS bits.
2785          * The RMW is extra paranoia since this should be called after being set
2786          * to a known state in preinstall.
2787          * */
2788         I915_WRITE(GEN6_PMIMR,
2789                    (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2790         I915_WRITE(GEN6_PMIER,
2791                    (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2792         POSTING_READ(GEN6_PMIER);
2793
2794         ibx_irq_postinstall(dev);
2795
2796         return 0;
2797 }
2798
2799 static int valleyview_irq_postinstall(struct drm_device *dev)
2800 {
2801         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2802         u32 gt_irqs;
2803         u32 enable_mask;
2804         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2805
2806         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2807         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2808                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2809                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2810                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2811
2812         /*
2813          *Leave vblank interrupts masked initially.  enable/disable will
2814          * toggle them based on usage.
2815          */
2816         dev_priv->irq_mask = (~enable_mask) |
2817                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2818                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2819
2820         I915_WRITE(PORT_HOTPLUG_EN, 0);
2821         POSTING_READ(PORT_HOTPLUG_EN);
2822
2823         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2824         I915_WRITE(VLV_IER, enable_mask);
2825         I915_WRITE(VLV_IIR, 0xffffffff);
2826         I915_WRITE(PIPESTAT(0), 0xffff);
2827         I915_WRITE(PIPESTAT(1), 0xffff);
2828         POSTING_READ(VLV_IER);
2829
2830         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2831         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2832         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2833
2834         I915_WRITE(VLV_IIR, 0xffffffff);
2835         I915_WRITE(VLV_IIR, 0xffffffff);
2836
2837         I915_WRITE(GTIIR, I915_READ(GTIIR));
2838         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2839
2840         gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2841                 GT_BLT_USER_INTERRUPT;
2842         I915_WRITE(GTIER, gt_irqs);
2843         POSTING_READ(GTIER);
2844
2845         /* ack & enable invalid PTE error interrupts */
2846 #if 0 /* FIXME: add support to irq handler for checking these bits */
2847         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2848         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2849 #endif
2850
2851         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2852
2853         return 0;
2854 }
2855
2856 static void valleyview_irq_uninstall(struct drm_device *dev)
2857 {
2858         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2859         int pipe;
2860
2861         if (!dev_priv)
2862                 return;
2863
2864         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2865
2866         for_each_pipe(pipe)
2867                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2868
2869         I915_WRITE(HWSTAM, 0xffffffff);
2870         I915_WRITE(PORT_HOTPLUG_EN, 0);
2871         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2872         for_each_pipe(pipe)
2873                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2874         I915_WRITE(VLV_IIR, 0xffffffff);
2875         I915_WRITE(VLV_IMR, 0xffffffff);
2876         I915_WRITE(VLV_IER, 0x0);
2877         POSTING_READ(VLV_IER);
2878 }
2879
2880 static void ironlake_irq_uninstall(struct drm_device *dev)
2881 {
2882         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2883
2884         if (!dev_priv)
2885                 return;
2886
2887         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2888
2889         I915_WRITE(HWSTAM, 0xffffffff);
2890
2891         I915_WRITE(DEIMR, 0xffffffff);
2892         I915_WRITE(DEIER, 0x0);
2893         I915_WRITE(DEIIR, I915_READ(DEIIR));
2894         if (IS_GEN7(dev))
2895                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2896
2897         I915_WRITE(GTIMR, 0xffffffff);
2898         I915_WRITE(GTIER, 0x0);
2899         I915_WRITE(GTIIR, I915_READ(GTIIR));
2900
2901         if (HAS_PCH_NOP(dev))
2902                 return;
2903
2904         I915_WRITE(SDEIMR, 0xffffffff);
2905         I915_WRITE(SDEIER, 0x0);
2906         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2907         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2908                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2909 }
2910
2911 static void i8xx_irq_preinstall(struct drm_device * dev)
2912 {
2913         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2914         int pipe;
2915
2916         atomic_set(&dev_priv->irq_received, 0);
2917
2918         for_each_pipe(pipe)
2919                 I915_WRITE(PIPESTAT(pipe), 0);
2920         I915_WRITE16(IMR, 0xffff);
2921         I915_WRITE16(IER, 0x0);
2922         POSTING_READ16(IER);
2923 }
2924
2925 static int i8xx_irq_postinstall(struct drm_device *dev)
2926 {
2927         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2928
2929         I915_WRITE16(EMR,
2930                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2931
2932         /* Unmask the interrupts that we always want on. */
2933         dev_priv->irq_mask =
2934                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2935                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2936                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2937                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2938                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2939         I915_WRITE16(IMR, dev_priv->irq_mask);
2940
2941         I915_WRITE16(IER,
2942                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2943                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2944                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2945                      I915_USER_INTERRUPT);
2946         POSTING_READ16(IER);
2947
2948         return 0;
2949 }
2950
2951 /*
2952  * Returns true when a page flip has completed.
2953  */
2954 static bool i8xx_handle_vblank(struct drm_device *dev,
2955                                int pipe, u16 iir)
2956 {
2957         drm_i915_private_t *dev_priv = dev->dev_private;
2958         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2959
2960         if (!drm_handle_vblank(dev, pipe))
2961                 return false;
2962
2963         if ((iir & flip_pending) == 0)
2964                 return false;
2965
2966         intel_prepare_page_flip(dev, pipe);
2967
2968         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2969          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2970          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2971          * the flip is completed (no longer pending). Since this doesn't raise
2972          * an interrupt per se, we watch for the change at vblank.
2973          */
2974         if (I915_READ16(ISR) & flip_pending)
2975                 return false;
2976
2977         intel_finish_page_flip(dev, pipe);
2978
2979         return true;
2980 }
2981
2982 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2983 {
2984         struct drm_device *dev = (struct drm_device *) arg;
2985         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2986         u16 iir, new_iir;
2987         u32 pipe_stats[2];
2988         unsigned long irqflags;
2989         int irq_received;
2990         int pipe;
2991         u16 flip_mask =
2992                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2993                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2994
2995         atomic_inc(&dev_priv->irq_received);
2996
2997         iir = I915_READ16(IIR);
2998         if (iir == 0)
2999                 return IRQ_NONE;
3000
3001         while (iir & ~flip_mask) {
3002                 /* Can't rely on pipestat interrupt bit in iir as it might
3003                  * have been cleared after the pipestat interrupt was received.
3004                  * It doesn't set the bit in iir again, but it still produces
3005                  * interrupts (for non-MSI).
3006                  */
3007                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3008                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3009                         i915_handle_error(dev, false);
3010
3011                 for_each_pipe(pipe) {
3012                         int reg = PIPESTAT(pipe);
3013                         pipe_stats[pipe] = I915_READ(reg);
3014
3015                         /*
3016                          * Clear the PIPE*STAT regs before the IIR
3017                          */
3018                         if (pipe_stats[pipe] & 0x8000ffff) {
3019                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3020                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3021                                                          pipe_name(pipe));
3022                                 I915_WRITE(reg, pipe_stats[pipe]);
3023                                 irq_received = 1;
3024                         }
3025                 }
3026                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3027
3028                 I915_WRITE16(IIR, iir & ~flip_mask);
3029                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3030
3031                 i915_update_dri1_breadcrumb(dev);
3032
3033                 if (iir & I915_USER_INTERRUPT)
3034                         notify_ring(dev, &dev_priv->ring[RCS]);
3035
3036                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
3037                     i8xx_handle_vblank(dev, 0, iir))
3038                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
3039
3040                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
3041                     i8xx_handle_vblank(dev, 1, iir))
3042                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
3043
3044                 iir = new_iir;
3045         }
3046
3047         return IRQ_HANDLED;
3048 }
3049
3050 static void i8xx_irq_uninstall(struct drm_device * dev)
3051 {
3052         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3053         int pipe;
3054
3055         for_each_pipe(pipe) {
3056                 /* Clear enable bits; then clear status bits */
3057                 I915_WRITE(PIPESTAT(pipe), 0);
3058                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3059         }
3060         I915_WRITE16(IMR, 0xffff);
3061         I915_WRITE16(IER, 0x0);
3062         I915_WRITE16(IIR, I915_READ16(IIR));
3063 }
3064
3065 static void i915_irq_preinstall(struct drm_device * dev)
3066 {
3067         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3068         int pipe;
3069
3070         atomic_set(&dev_priv->irq_received, 0);
3071
3072         if (I915_HAS_HOTPLUG(dev)) {
3073                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3074                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3075         }
3076
3077         I915_WRITE16(HWSTAM, 0xeffe);
3078         for_each_pipe(pipe)
3079                 I915_WRITE(PIPESTAT(pipe), 0);
3080         I915_WRITE(IMR, 0xffffffff);
3081         I915_WRITE(IER, 0x0);
3082         POSTING_READ(IER);
3083 }
3084
3085 static int i915_irq_postinstall(struct drm_device *dev)
3086 {
3087         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3088         u32 enable_mask;
3089
3090         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3091
3092         /* Unmask the interrupts that we always want on. */
3093         dev_priv->irq_mask =
3094                 ~(I915_ASLE_INTERRUPT |
3095                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3096                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3097                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3098                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3099                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3100
3101         enable_mask =
3102                 I915_ASLE_INTERRUPT |
3103                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3104                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3105                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3106                 I915_USER_INTERRUPT;
3107
3108         if (I915_HAS_HOTPLUG(dev)) {
3109                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3110                 POSTING_READ(PORT_HOTPLUG_EN);
3111
3112                 /* Enable in IER... */
3113                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3114                 /* and unmask in IMR */
3115                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3116         }
3117
3118         I915_WRITE(IMR, dev_priv->irq_mask);
3119         I915_WRITE(IER, enable_mask);
3120         POSTING_READ(IER);
3121
3122         i915_enable_asle_pipestat(dev);
3123
3124         return 0;
3125 }
3126
3127 /*
3128  * Returns true when a page flip has completed.
3129  */
3130 static bool i915_handle_vblank(struct drm_device *dev,
3131                                int plane, int pipe, u32 iir)
3132 {
3133         drm_i915_private_t *dev_priv = dev->dev_private;
3134         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3135
3136         if (!drm_handle_vblank(dev, pipe))
3137                 return false;
3138
3139         if ((iir & flip_pending) == 0)
3140                 return false;
3141
3142         intel_prepare_page_flip(dev, plane);
3143
3144         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3145          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3146          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3147          * the flip is completed (no longer pending). Since this doesn't raise
3148          * an interrupt per se, we watch for the change at vblank.
3149          */
3150         if (I915_READ(ISR) & flip_pending)
3151                 return false;
3152
3153         intel_finish_page_flip(dev, pipe);
3154
3155         return true;
3156 }
3157
3158 static irqreturn_t i915_irq_handler(int irq, void *arg)
3159 {
3160         struct drm_device *dev = (struct drm_device *) arg;
3161         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3162         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3163         unsigned long irqflags;
3164         u32 flip_mask =
3165                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3166                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3167         int pipe, ret = IRQ_NONE;
3168
3169         atomic_inc(&dev_priv->irq_received);
3170
3171         iir = I915_READ(IIR);
3172         do {
3173                 bool irq_received = (iir & ~flip_mask) != 0;
3174                 bool blc_event = false;
3175
3176                 /* Can't rely on pipestat interrupt bit in iir as it might
3177                  * have been cleared after the pipestat interrupt was received.
3178                  * It doesn't set the bit in iir again, but it still produces
3179                  * interrupts (for non-MSI).
3180                  */
3181                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3182                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3183                         i915_handle_error(dev, false);
3184
3185                 for_each_pipe(pipe) {
3186                         int reg = PIPESTAT(pipe);
3187                         pipe_stats[pipe] = I915_READ(reg);
3188
3189                         /* Clear the PIPE*STAT regs before the IIR */
3190                         if (pipe_stats[pipe] & 0x8000ffff) {
3191                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3192                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3193                                                          pipe_name(pipe));
3194                                 I915_WRITE(reg, pipe_stats[pipe]);
3195                                 irq_received = true;
3196                         }
3197                 }
3198                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3199
3200                 if (!irq_received)
3201                         break;
3202
3203                 /* Consume port.  Then clear IIR or we'll miss events */
3204                 if ((I915_HAS_HOTPLUG(dev)) &&
3205                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3206                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3207                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3208
3209                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3210                                   hotplug_status);
3211                         if (hotplug_trigger) {
3212                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
3213                                         i915_hpd_irq_setup(dev);
3214                                 queue_work(dev_priv->wq,
3215                                            &dev_priv->hotplug_work);
3216                         }
3217                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3218                         POSTING_READ(PORT_HOTPLUG_STAT);
3219                 }
3220
3221                 I915_WRITE(IIR, iir & ~flip_mask);
3222                 new_iir = I915_READ(IIR); /* Flush posted writes */
3223
3224                 if (iir & I915_USER_INTERRUPT)
3225                         notify_ring(dev, &dev_priv->ring[RCS]);
3226
3227                 for_each_pipe(pipe) {
3228                         int plane = pipe;
3229                         if (IS_MOBILE(dev))
3230                                 plane = !plane;
3231
3232                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3233                             i915_handle_vblank(dev, plane, pipe, iir))
3234                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3235
3236                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3237                                 blc_event = true;
3238                 }
3239
3240                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3241                         intel_opregion_asle_intr(dev);
3242
3243                 /* With MSI, interrupts are only generated when iir
3244                  * transitions from zero to nonzero.  If another bit got
3245                  * set while we were handling the existing iir bits, then
3246                  * we would never get another interrupt.
3247                  *
3248                  * This is fine on non-MSI as well, as if we hit this path
3249                  * we avoid exiting the interrupt handler only to generate
3250                  * another one.
3251                  *
3252                  * Note that for MSI this could cause a stray interrupt report
3253                  * if an interrupt landed in the time between writing IIR and
3254                  * the posting read.  This should be rare enough to never
3255                  * trigger the 99% of 100,000 interrupts test for disabling
3256                  * stray interrupts.
3257                  */
3258                 ret = IRQ_HANDLED;
3259                 iir = new_iir;
3260         } while (iir & ~flip_mask);
3261
3262         i915_update_dri1_breadcrumb(dev);
3263
3264         return ret;
3265 }
3266
3267 static void i915_irq_uninstall(struct drm_device * dev)
3268 {
3269         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3270         int pipe;
3271
3272         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3273
3274         if (I915_HAS_HOTPLUG(dev)) {
3275                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3276                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3277         }
3278
3279         I915_WRITE16(HWSTAM, 0xffff);
3280         for_each_pipe(pipe) {
3281                 /* Clear enable bits; then clear status bits */
3282                 I915_WRITE(PIPESTAT(pipe), 0);
3283                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3284         }
3285         I915_WRITE(IMR, 0xffffffff);
3286         I915_WRITE(IER, 0x0);
3287
3288         I915_WRITE(IIR, I915_READ(IIR));
3289 }
3290
3291 static void i965_irq_preinstall(struct drm_device * dev)
3292 {
3293         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3294         int pipe;
3295
3296         atomic_set(&dev_priv->irq_received, 0);
3297
3298         I915_WRITE(PORT_HOTPLUG_EN, 0);
3299         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3300
3301         I915_WRITE(HWSTAM, 0xeffe);
3302         for_each_pipe(pipe)
3303                 I915_WRITE(PIPESTAT(pipe), 0);
3304         I915_WRITE(IMR, 0xffffffff);
3305         I915_WRITE(IER, 0x0);
3306         POSTING_READ(IER);
3307 }
3308
3309 static int i965_irq_postinstall(struct drm_device *dev)
3310 {
3311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3312         u32 enable_mask;
3313         u32 error_mask;
3314
3315         /* Unmask the interrupts that we always want on. */
3316         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3317                                I915_DISPLAY_PORT_INTERRUPT |
3318                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3319                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3320                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3321                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3322                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3323
3324         enable_mask = ~dev_priv->irq_mask;
3325         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3326                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3327         enable_mask |= I915_USER_INTERRUPT;
3328
3329         if (IS_G4X(dev))
3330                 enable_mask |= I915_BSD_USER_INTERRUPT;
3331
3332         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3333
3334         /*
3335          * Enable some error detection, note the instruction error mask
3336          * bit is reserved, so we leave it masked.
3337          */
3338         if (IS_G4X(dev)) {
3339                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3340                                GM45_ERROR_MEM_PRIV |
3341                                GM45_ERROR_CP_PRIV |
3342                                I915_ERROR_MEMORY_REFRESH);
3343         } else {
3344                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3345                                I915_ERROR_MEMORY_REFRESH);
3346         }
3347         I915_WRITE(EMR, error_mask);
3348
3349         I915_WRITE(IMR, dev_priv->irq_mask);
3350         I915_WRITE(IER, enable_mask);
3351         POSTING_READ(IER);
3352
3353         I915_WRITE(PORT_HOTPLUG_EN, 0);
3354         POSTING_READ(PORT_HOTPLUG_EN);
3355
3356         i915_enable_asle_pipestat(dev);
3357
3358         return 0;
3359 }
3360
3361 static void i915_hpd_irq_setup(struct drm_device *dev)
3362 {
3363         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3364         struct drm_mode_config *mode_config = &dev->mode_config;
3365         struct intel_encoder *intel_encoder;
3366         u32 hotplug_en;
3367
3368         if (I915_HAS_HOTPLUG(dev)) {
3369                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3370                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3371                 /* Note HDMI and DP share hotplug bits */
3372                 /* enable bits are the same for all generations */
3373                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3374                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3375                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3376                 /* Programming the CRT detection parameters tends
3377                    to generate a spurious hotplug event about three
3378                    seconds later.  So just do it once.
3379                 */
3380                 if (IS_G4X(dev))
3381                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3382                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3383                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3384
3385                 /* Ignore TV since it's buggy */
3386                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3387         }
3388 }
3389
3390 static irqreturn_t i965_irq_handler(int irq, void *arg)
3391 {
3392         struct drm_device *dev = (struct drm_device *) arg;
3393         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3394         u32 iir, new_iir;
3395         u32 pipe_stats[I915_MAX_PIPES];
3396         unsigned long irqflags;
3397         int irq_received;
3398         int ret = IRQ_NONE, pipe;
3399         u32 flip_mask =
3400                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3401                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3402
3403         atomic_inc(&dev_priv->irq_received);
3404
3405         iir = I915_READ(IIR);
3406
3407         for (;;) {
3408                 bool blc_event = false;
3409
3410                 irq_received = (iir & ~flip_mask) != 0;
3411
3412                 /* Can't rely on pipestat interrupt bit in iir as it might
3413                  * have been cleared after the pipestat interrupt was received.
3414                  * It doesn't set the bit in iir again, but it still produces
3415                  * interrupts (for non-MSI).
3416                  */
3417                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3418                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3419                         i915_handle_error(dev, false);
3420
3421                 for_each_pipe(pipe) {
3422                         int reg = PIPESTAT(pipe);
3423                         pipe_stats[pipe] = I915_READ(reg);
3424
3425                         /*
3426                          * Clear the PIPE*STAT regs before the IIR
3427                          */
3428                         if (pipe_stats[pipe] & 0x8000ffff) {
3429                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3430                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3431                                                          pipe_name(pipe));
3432                                 I915_WRITE(reg, pipe_stats[pipe]);
3433                                 irq_received = 1;
3434                         }
3435                 }
3436                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3437
3438                 if (!irq_received)
3439                         break;
3440
3441                 ret = IRQ_HANDLED;
3442
3443                 /* Consume port.  Then clear IIR or we'll miss events */
3444                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3445                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3446                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3447                                                                   HOTPLUG_INT_STATUS_G4X :
3448                                                                   HOTPLUG_INT_STATUS_I965);
3449
3450                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3451                                   hotplug_status);
3452                         if (hotplug_trigger) {
3453                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
3454                                                             IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
3455                                         i915_hpd_irq_setup(dev);
3456                                 queue_work(dev_priv->wq,
3457                                            &dev_priv->hotplug_work);
3458                         }
3459                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3460                         I915_READ(PORT_HOTPLUG_STAT);
3461                 }
3462
3463                 I915_WRITE(IIR, iir & ~flip_mask);
3464                 new_iir = I915_READ(IIR); /* Flush posted writes */
3465
3466                 if (iir & I915_USER_INTERRUPT)
3467                         notify_ring(dev, &dev_priv->ring[RCS]);
3468                 if (iir & I915_BSD_USER_INTERRUPT)
3469                         notify_ring(dev, &dev_priv->ring[VCS]);
3470
3471                 for_each_pipe(pipe) {
3472                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3473                             i915_handle_vblank(dev, pipe, pipe, iir))
3474                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3475
3476                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3477                                 blc_event = true;
3478                 }
3479
3480
3481                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3482                         intel_opregion_asle_intr(dev);
3483
3484                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3485                         gmbus_irq_handler(dev);
3486
3487                 /* With MSI, interrupts are only generated when iir
3488                  * transitions from zero to nonzero.  If another bit got
3489                  * set while we were handling the existing iir bits, then
3490                  * we would never get another interrupt.
3491                  *
3492                  * This is fine on non-MSI as well, as if we hit this path
3493                  * we avoid exiting the interrupt handler only to generate
3494                  * another one.
3495                  *
3496                  * Note that for MSI this could cause a stray interrupt report
3497                  * if an interrupt landed in the time between writing IIR and
3498                  * the posting read.  This should be rare enough to never
3499                  * trigger the 99% of 100,000 interrupts test for disabling
3500                  * stray interrupts.
3501                  */
3502                 iir = new_iir;
3503         }
3504
3505         i915_update_dri1_breadcrumb(dev);
3506
3507         return ret;
3508 }
3509
3510 static void i965_irq_uninstall(struct drm_device * dev)
3511 {
3512         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3513         int pipe;
3514
3515         if (!dev_priv)
3516                 return;
3517
3518         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3519
3520         I915_WRITE(PORT_HOTPLUG_EN, 0);
3521         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3522
3523         I915_WRITE(HWSTAM, 0xffffffff);
3524         for_each_pipe(pipe)
3525                 I915_WRITE(PIPESTAT(pipe), 0);
3526         I915_WRITE(IMR, 0xffffffff);
3527         I915_WRITE(IER, 0x0);
3528
3529         for_each_pipe(pipe)
3530                 I915_WRITE(PIPESTAT(pipe),
3531                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3532         I915_WRITE(IIR, I915_READ(IIR));
3533 }
3534
3535 static void i915_reenable_hotplug_timer_func(unsigned long data)
3536 {
3537         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3538         struct drm_device *dev = dev_priv->dev;
3539         struct drm_mode_config *mode_config = &dev->mode_config;
3540         unsigned long irqflags;
3541         int i;
3542
3543         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3544         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3545                 struct drm_connector *connector;
3546
3547                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3548                         continue;
3549
3550                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3551
3552                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3553                         struct intel_connector *intel_connector = to_intel_connector(connector);
3554
3555                         if (intel_connector->encoder->hpd_pin == i) {
3556                                 if (connector->polled != intel_connector->polled)
3557                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3558                                                          drm_get_connector_name(connector));
3559                                 connector->polled = intel_connector->polled;
3560                                 if (!connector->polled)
3561                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3562                         }
3563                 }
3564         }
3565         if (dev_priv->display.hpd_irq_setup)
3566                 dev_priv->display.hpd_irq_setup(dev);
3567         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3568 }
3569
3570 void intel_irq_init(struct drm_device *dev)
3571 {
3572         struct drm_i915_private *dev_priv = dev->dev_private;
3573
3574         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3575         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3576         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3577         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3578
3579         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3580                     i915_hangcheck_elapsed,
3581                     (unsigned long) dev);
3582         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3583                     (unsigned long) dev_priv);
3584
3585         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3586
3587         dev->driver->get_vblank_counter = i915_get_vblank_counter;
3588         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3589         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3590                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3591                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3592         }
3593
3594         if (drm_core_check_feature(dev, DRIVER_MODESET))
3595                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3596         else
3597                 dev->driver->get_vblank_timestamp = NULL;
3598         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3599
3600         if (IS_VALLEYVIEW(dev)) {
3601                 dev->driver->irq_handler = valleyview_irq_handler;
3602                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3603                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3604                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3605                 dev->driver->enable_vblank = valleyview_enable_vblank;
3606                 dev->driver->disable_vblank = valleyview_disable_vblank;
3607                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3608         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3609                 /* Share uninstall handlers with ILK/SNB */
3610                 dev->driver->irq_handler = ivybridge_irq_handler;
3611                 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
3612                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3613                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3614                 dev->driver->enable_vblank = ivybridge_enable_vblank;
3615                 dev->driver->disable_vblank = ivybridge_disable_vblank;
3616                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3617         } else if (HAS_PCH_SPLIT(dev)) {
3618                 dev->driver->irq_handler = ironlake_irq_handler;
3619                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3620                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3621                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3622                 dev->driver->enable_vblank = ironlake_enable_vblank;
3623                 dev->driver->disable_vblank = ironlake_disable_vblank;
3624                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3625         } else {
3626                 if (INTEL_INFO(dev)->gen == 2) {
3627                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3628                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3629                         dev->driver->irq_handler = i8xx_irq_handler;
3630                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3631                 } else if (INTEL_INFO(dev)->gen == 3) {
3632                         dev->driver->irq_preinstall = i915_irq_preinstall;
3633                         dev->driver->irq_postinstall = i915_irq_postinstall;
3634                         dev->driver->irq_uninstall = i915_irq_uninstall;
3635                         dev->driver->irq_handler = i915_irq_handler;
3636                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3637                 } else {
3638                         dev->driver->irq_preinstall = i965_irq_preinstall;
3639                         dev->driver->irq_postinstall = i965_irq_postinstall;
3640                         dev->driver->irq_uninstall = i965_irq_uninstall;
3641                         dev->driver->irq_handler = i965_irq_handler;
3642                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3643                 }
3644                 dev->driver->enable_vblank = i915_enable_vblank;
3645                 dev->driver->disable_vblank = i915_disable_vblank;
3646         }
3647 }
3648
3649 void intel_hpd_init(struct drm_device *dev)
3650 {
3651         struct drm_i915_private *dev_priv = dev->dev_private;
3652         struct drm_mode_config *mode_config = &dev->mode_config;
3653         struct drm_connector *connector;
3654         int i;
3655
3656         for (i = 1; i < HPD_NUM_PINS; i++) {
3657                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3658                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3659         }
3660         list_for_each_entry(connector, &mode_config->connector_list, head) {
3661                 struct intel_connector *intel_connector = to_intel_connector(connector);
3662                 connector->polled = intel_connector->polled;
3663                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3664                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3665         }
3666         if (dev_priv->display.hpd_irq_setup)
3667                 dev_priv->display.hpd_irq_setup(dev);
3668 }