drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173
 174 /* For display hotplug interrupt */
 175 static inline void
 176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 177                                      uint32_t mask,
 178                                      uint32_t bits)
 179 {
 180         uint32_t val;
 181
 182         assert_spin_locked(&dev_priv->irq_lock);
 183         WARN_ON(bits & ~mask);
 184
 185         val = I915_READ(PORT_HOTPLUG_EN);
 186         val &= ~mask;
 187         val |= bits;
 188         I915_WRITE(PORT_HOTPLUG_EN, val);
 189 }
 190
 191 /**
 192  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 193  * @dev_priv: driver private
 194  * @mask: bits to update
 195  * @bits: bits to enable
 196  * NOTE: the HPD enable bits are modified both inside and outside
 197  * of an interrupt context. To avoid that read-modify-write cycles
 198  * interfer, these bits are protected by a spinlock. Since this
 199  * function is usually not called from a context where the lock is
 200  * held already, this function acquires the lock itself. A non-locking
 201  * version is also available.
 202  */
 203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 204                                    uint32_t mask,
 205                                    uint32_t bits)
 206 {
 207         spin_lock_irq(&dev_priv->irq_lock);
 208         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 209         spin_unlock_irq(&dev_priv->irq_lock);
 210 }
 211
 212 /**
 213  * ilk_update_display_irq - update DEIMR
 214  * @dev_priv: driver private
 215  * @interrupt_mask: mask of interrupt bits to update
 216  * @enabled_irq_mask: mask of interrupt bits to enable
 217  */
 218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 219                             uint32_t interrupt_mask,
 220                             uint32_t enabled_irq_mask)
 221 {
 222         uint32_t new_val;
 223
 224         assert_spin_locked(&dev_priv->irq_lock);
 225
 226         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 227
 228         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 229                 return;
 230
 231         new_val = dev_priv->irq_mask;
 232         new_val &= ~interrupt_mask;
 233         new_val |= (~enabled_irq_mask & interrupt_mask);
 234
 235         if (new_val != dev_priv->irq_mask) {
 236                 dev_priv->irq_mask = new_val;
 237                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 238                 POSTING_READ(DEIMR);
 239         }
 240 }
 241
 242 /**
 243  * ilk_update_gt_irq - update GTIMR
 244  * @dev_priv: driver private
 245  * @interrupt_mask: mask of interrupt bits to update
 246  * @enabled_irq_mask: mask of interrupt bits to enable
 247  */
 248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 249                               uint32_t interrupt_mask,
 250                               uint32_t enabled_irq_mask)
 251 {
 252         assert_spin_locked(&dev_priv->irq_lock);
 253
 254         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 255
 256         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 257                 return;
 258
 259         dev_priv->gt_irq_mask &= ~interrupt_mask;
 260         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 261         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 262         POSTING_READ(GTIMR);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268 }
 269
 270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 271 {
 272         ilk_update_gt_irq(dev_priv, mask, 0);
 273 }
 274
 275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 276 {
 277         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 278 }
 279
 280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 281 {
 282         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 283 }
 284
 285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 286 {
 287         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 288 }
 289
 290 /**
 291  * snb_update_pm_irq - update GEN6_PMIMR
 292  * @dev_priv: driver private
 293  * @interrupt_mask: mask of interrupt bits to update
 294  * @enabled_irq_mask: mask of interrupt bits to enable
 295  */
 296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 297                               uint32_t interrupt_mask,
 298                               uint32_t enabled_irq_mask)
 299 {
 300         uint32_t new_val;
 301
 302         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 303
 304         assert_spin_locked(&dev_priv->irq_lock);
 305
 306         new_val = dev_priv->pm_irq_mask;
 307         new_val &= ~interrupt_mask;
 308         new_val |= (~enabled_irq_mask & interrupt_mask);
 309
 310         if (new_val != dev_priv->pm_irq_mask) {
 311                 dev_priv->pm_irq_mask = new_val;
 312                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 313                 POSTING_READ(gen6_pm_imr(dev_priv));
 314         }
 315 }
 316
 317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 318 {
 319         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 320                 return;
 321
 322         snb_update_pm_irq(dev_priv, mask, mask);
 323 }
 324
 325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 326                                   uint32_t mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_disable_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         spin_lock_irq(&dev_priv->irq_lock);
 344         I915_WRITE(reg, dev_priv->pm_rps_events);
 345         I915_WRITE(reg, dev_priv->pm_rps_events);
 346         POSTING_READ(reg);
 347         dev_priv->rps.pm_iir = 0;
 348         spin_unlock_irq(&dev_priv->irq_lock);
 349 }
 350
 351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 352 {
 353         spin_lock_irq(&dev_priv->irq_lock);
 354
 355         WARN_ON(dev_priv->rps.pm_iir);
 356         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 357         dev_priv->rps.interrupts_enabled = true;
 358         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 359                                 dev_priv->pm_rps_events);
 360         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 361
 362         spin_unlock_irq(&dev_priv->irq_lock);
 363 }
 364
 365 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 366 {
 367         /*
 368          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 369          * if GEN6_PM_UP_EI_EXPIRED is masked.
 370          *
 371          * TODO: verify if this can be reproduced on VLV,CHV.
 372          */
 373         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 374                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 375
 376         if (INTEL_INFO(dev_priv)->gen >= 8)
 377                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 378
 379         return mask;
 380 }
 381
 382 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 383 {
 384         spin_lock_irq(&dev_priv->irq_lock);
 385         dev_priv->rps.interrupts_enabled = false;
 386         spin_unlock_irq(&dev_priv->irq_lock);
 387
 388         cancel_work_sync(&dev_priv->rps.work);
 389
 390         spin_lock_irq(&dev_priv->irq_lock);
 391
 392         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 393
 394         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 395         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 396                                 ~dev_priv->pm_rps_events);
 397
 398         spin_unlock_irq(&dev_priv->irq_lock);
 399
 400         synchronize_irq(dev_priv->dev->irq);
 401 }
 402
 403 /**
 404  * bdw_update_port_irq - update DE port interrupt
 405  * @dev_priv: driver private
 406  * @interrupt_mask: mask of interrupt bits to update
 407  * @enabled_irq_mask: mask of interrupt bits to enable
 408  */
 409 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 410                                 uint32_t interrupt_mask,
 411                                 uint32_t enabled_irq_mask)
 412 {
 413         uint32_t new_val;
 414         uint32_t old_val;
 415
 416         assert_spin_locked(&dev_priv->irq_lock);
 417
 418         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 419
 420         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 421                 return;
 422
 423         old_val = I915_READ(GEN8_DE_PORT_IMR);
 424
 425         new_val = old_val;
 426         new_val &= ~interrupt_mask;
 427         new_val |= (~enabled_irq_mask & interrupt_mask);
 428
 429         if (new_val != old_val) {
 430                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 431                 POSTING_READ(GEN8_DE_PORT_IMR);
 432         }
 433 }
 434
 435 /**
 436  * bdw_update_pipe_irq - update DE pipe interrupt
 437  * @dev_priv: driver private
 438  * @pipe: pipe whose interrupt to update
 439  * @interrupt_mask: mask of interrupt bits to update
 440  * @enabled_irq_mask: mask of interrupt bits to enable
 441  */
 442 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 443                          enum pipe pipe,
 444                          uint32_t interrupt_mask,
 445                          uint32_t enabled_irq_mask)
 446 {
 447         uint32_t new_val;
 448
 449         assert_spin_locked(&dev_priv->irq_lock);
 450
 451         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 452
 453         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 454                 return;
 455
 456         new_val = dev_priv->de_irq_mask[pipe];
 457         new_val &= ~interrupt_mask;
 458         new_val |= (~enabled_irq_mask & interrupt_mask);
 459
 460         if (new_val != dev_priv->de_irq_mask[pipe]) {
 461                 dev_priv->de_irq_mask[pipe] = new_val;
 462                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 463                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 464         }
 465 }
 466
 467 /**
 468  * ibx_display_interrupt_update - update SDEIMR
 469  * @dev_priv: driver private
 470  * @interrupt_mask: mask of interrupt bits to update
 471  * @enabled_irq_mask: mask of interrupt bits to enable
 472  */
 473 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 474                                   uint32_t interrupt_mask,
 475                                   uint32_t enabled_irq_mask)
 476 {
 477         uint32_t sdeimr = I915_READ(SDEIMR);
 478         sdeimr &= ~interrupt_mask;
 479         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 480
 481         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 482
 483         assert_spin_locked(&dev_priv->irq_lock);
 484
 485         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 486                 return;
 487
 488         I915_WRITE(SDEIMR, sdeimr);
 489         POSTING_READ(SDEIMR);
 490 }
 491
 492 static void
 493 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 494                        u32 enable_mask, u32 status_mask)
 495 {
 496         i915_reg_t reg = PIPESTAT(pipe);
 497         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 498
 499         assert_spin_locked(&dev_priv->irq_lock);
 500         WARN_ON(!intel_irqs_enabled(dev_priv));
 501
 502         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 503                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 504                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 505                       pipe_name(pipe), enable_mask, status_mask))
 506                 return;
 507
 508         if ((pipestat & enable_mask) == enable_mask)
 509                 return;
 510
 511         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 512
 513         /* Enable the interrupt, clear any pending status */
 514         pipestat |= enable_mask | status_mask;
 515         I915_WRITE(reg, pipestat);
 516         POSTING_READ(reg);
 517 }
 518
 519 static void
 520 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 521                         u32 enable_mask, u32 status_mask)
 522 {
 523         i915_reg_t reg = PIPESTAT(pipe);
 524         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 525
 526         assert_spin_locked(&dev_priv->irq_lock);
 527         WARN_ON(!intel_irqs_enabled(dev_priv));
 528
 529         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 530                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 531                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 532                       pipe_name(pipe), enable_mask, status_mask))
 533                 return;
 534
 535         if ((pipestat & enable_mask) == 0)
 536                 return;
 537
 538         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 539
 540         pipestat &= ~enable_mask;
 541         I915_WRITE(reg, pipestat);
 542         POSTING_READ(reg);
 543 }
 544
 545 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 546 {
 547         u32 enable_mask = status_mask << 16;
 548
 549         /*
 550          * On pipe A we don't support the PSR interrupt yet,
 551          * on pipe B and C the same bit MBZ.
 552          */
 553         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 554                 return 0;
 555         /*
 556          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 557          * A the same bit is for perf counters which we don't use either.
 558          */
 559         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 560                 return 0;
 561
 562         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 563                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 564                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 565         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 566                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 567         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 568                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 569
 570         return enable_mask;
 571 }
 572
 573 void
 574 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 575                      u32 status_mask)
 576 {
 577         u32 enable_mask;
 578
 579         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 580                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 581                                                            status_mask);
 582         else
 583                 enable_mask = status_mask << 16;
 584         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 585 }
 586
 587 void
 588 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 589                       u32 status_mask)
 590 {
 591         u32 enable_mask;
 592
 593         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 594                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 595                                                            status_mask);
 596         else
 597                 enable_mask = status_mask << 16;
 598         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 599 }
 600
 601 /**
 602  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 603  * @dev: drm device
 604  */
 605 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 606 {
 607         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 608                 return;
 609
 610         spin_lock_irq(&dev_priv->irq_lock);
 611
 612         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 613         if (INTEL_GEN(dev_priv) >= 4)
 614                 i915_enable_pipestat(dev_priv, PIPE_A,
 615                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 616
 617         spin_unlock_irq(&dev_priv->irq_lock);
 618 }
 619
 620 /*
 621  * This timing diagram depicts the video signal in and
 622  * around the vertical blanking period.
 623  *
 624  * Assumptions about the fictitious mode used in this example:
 625  *  vblank_start >= 3
 626  *  vsync_start = vblank_start + 1
 627  *  vsync_end = vblank_start + 2
 628  *  vtotal = vblank_start + 3
 629  *
 630  *           start of vblank:
 631  *           latch double buffered registers
 632  *           increment frame counter (ctg+)
 633  *           generate start of vblank interrupt (gen4+)
 634  *           |
 635  *           |          frame start:
 636  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 637  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 638  *           |          |
 639  *           |          |  start of vsync:
 640  *           |          |  generate vsync interrupt
 641  *           |          |  |
 642  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 643  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 644  * ----va---> <-----------------vb--------------------> <--------va-------------
 645  *       |          |       <----vs----->                     |
 646  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 647  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 648  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 649  *       |          |                                         |
 650  *       last visible pixel                                   first visible pixel
 651  *                  |                                         increment frame counter (gen3/4)
 652  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 653  *
 654  * x  = horizontal active
 655  * _  = horizontal blanking
 656  * hs = horizontal sync
 657  * va = vertical active
 658  * vb = vertical blanking
 659  * vs = vertical sync
 660  * vbs = vblank_start (number)
 661  *
 662  * Summary:
 663  * - most events happen at the start of horizontal sync
 664  * - frame start happens at the start of horizontal blank, 1-4 lines
 665  *   (depending on PIPECONF settings) after the start of vblank
 666  * - gen3/4 pixel and frame counter are synchronized with the start
 667  *   of horizontal active on the first line of vertical active
 668  */
 669
 670 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 671 {
 672         /* Gen2 doesn't have a hardware frame counter */
 673         return 0;
 674 }
 675
 676 /* Called from drm generic code, passed a 'crtc', which
 677  * we use as a pipe index
 678  */
 679 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 680 {
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         i915_reg_t high_frame, low_frame;
 683         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 684         struct intel_crtc *intel_crtc =
 685                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 686         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 687
 688         htotal = mode->crtc_htotal;
 689         hsync_start = mode->crtc_hsync_start;
 690         vbl_start = mode->crtc_vblank_start;
 691         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 692                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 693
 694         /* Convert to pixel count */
 695         vbl_start *= htotal;
 696
 697         /* Start of vblank event occurs at start of hsync */
 698         vbl_start -= htotal - hsync_start;
 699
 700         high_frame = PIPEFRAME(pipe);
 701         low_frame = PIPEFRAMEPIXEL(pipe);
 702
 703         /*
 704          * High & low register fields aren't synchronized, so make sure
 705          * we get a low value that's stable across two reads of the high
 706          * register.
 707          */
 708         do {
 709                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 710                 low   = I915_READ(low_frame);
 711                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 712         } while (high1 != high2);
 713
 714         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 715         pixel = low & PIPE_PIXEL_MASK;
 716         low >>= PIPE_FRAME_LOW_SHIFT;
 717
 718         /*
 719          * The frame counter increments at beginning of active.
 720          * Cook up a vblank counter by also checking the pixel
 721          * counter against vblank start.
 722          */
 723         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 724 }
 725
 726 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 727 {
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729
 730         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 731 }
 732
 733 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 734 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 735 {
 736         struct drm_device *dev = crtc->base.dev;
 737         struct drm_i915_private *dev_priv = dev->dev_private;
 738         const struct drm_display_mode *mode = &crtc->base.hwmode;
 739         enum pipe pipe = crtc->pipe;
 740         int position, vtotal;
 741
 742         vtotal = mode->crtc_vtotal;
 743         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 744                 vtotal /= 2;
 745
 746         if (IS_GEN2(dev_priv))
 747                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 748         else
 749                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 750
 751         /*
 752          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 753          * read it just before the start of vblank.  So try it again
 754          * so we don't accidentally end up spanning a vblank frame
 755          * increment, causing the pipe_update_end() code to squak at us.
 756          *
 757          * The nature of this problem means we can't simply check the ISR
 758          * bit and return the vblank start value; nor can we use the scanline
 759          * debug register in the transcoder as it appears to have the same
 760          * problem.  We may need to extend this to include other platforms,
 761          * but so far testing only shows the problem on HSW.
 762          */
 763         if (HAS_DDI(dev_priv) && !position) {
 764                 int i, temp;
 765
 766                 for (i = 0; i < 100; i++) {
 767                         udelay(1);
 768                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 769                                 DSL_LINEMASK_GEN3;
 770                         if (temp != position) {
 771                                 position = temp;
 772                                 break;
 773                         }
 774                 }
 775         }
 776
 777         /*
 778          * See update_scanline_offset() for the details on the
 779          * scanline_offset adjustment.
 780          */
 781         return (position + crtc->scanline_offset) % vtotal;
 782 }
 783
 784 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 785                                     unsigned int flags, int *vpos, int *hpos,
 786                                     ktime_t *stime, ktime_t *etime,
 787                                     const struct drm_display_mode *mode)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 792         int position;
 793         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 794         bool in_vbl = true;
 795         int ret = 0;
 796         unsigned long irqflags;
 797
 798         if (WARN_ON(!mode->crtc_clock)) {
 799                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 800                                  "pipe %c\n", pipe_name(pipe));
 801                 return 0;
 802         }
 803
 804         htotal = mode->crtc_htotal;
 805         hsync_start = mode->crtc_hsync_start;
 806         vtotal = mode->crtc_vtotal;
 807         vbl_start = mode->crtc_vblank_start;
 808         vbl_end = mode->crtc_vblank_end;
 809
 810         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 811                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 812                 vbl_end /= 2;
 813                 vtotal /= 2;
 814         }
 815
 816         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 817
 818         /*
 819          * Lock uncore.lock, as we will do multiple timing critical raw
 820          * register reads, potentially with preemption disabled, so the
 821          * following code must not block on uncore.lock.
 822          */
 823         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 824
 825         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 826
 827         /* Get optional system timestamp before query. */
 828         if (stime)
 829                 *stime = ktime_get();
 830
 831         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 832                 /* No obvious pixelcount register. Only query vertical
 833                  * scanout position from Display scan line register.
 834                  */
 835                 position = __intel_get_crtc_scanline(intel_crtc);
 836         } else {
 837                 /* Have access to pixelcount since start of frame.
 838                  * We can split this into vertical and horizontal
 839                  * scanout position.
 840                  */
 841                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 842
 843                 /* convert to pixel counts */
 844                 vbl_start *= htotal;
 845                 vbl_end *= htotal;
 846                 vtotal *= htotal;
 847
 848                 /*
 849                  * In interlaced modes, the pixel counter counts all pixels,
 850                  * so one field will have htotal more pixels. In order to avoid
 851                  * the reported position from jumping backwards when the pixel
 852                  * counter is beyond the length of the shorter field, just
 853                  * clamp the position the length of the shorter field. This
 854                  * matches how the scanline counter based position works since
 855                  * the scanline counter doesn't count the two half lines.
 856                  */
 857                 if (position >= vtotal)
 858                         position = vtotal - 1;
 859
 860                 /*
 861                  * Start of vblank interrupt is triggered at start of hsync,
 862                  * just prior to the first active line of vblank. However we
 863                  * consider lines to start at the leading edge of horizontal
 864                  * active. So, should we get here before we've crossed into
 865                  * the horizontal active of the first line in vblank, we would
 866                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 867                  * always add htotal-hsync_start to the current pixel position.
 868                  */
 869                 position = (position + htotal - hsync_start) % vtotal;
 870         }
 871
 872         /* Get optional system timestamp after query. */
 873         if (etime)
 874                 *etime = ktime_get();
 875
 876         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 877
 878         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 879
 880         in_vbl = position >= vbl_start && position < vbl_end;
 881
 882         /*
 883          * While in vblank, position will be negative
 884          * counting up towards 0 at vbl_end. And outside
 885          * vblank, position will be positive counting
 886          * up since vbl_end.
 887          */
 888         if (position >= vbl_start)
 889                 position -= vbl_end;
 890         else
 891                 position += vtotal - vbl_end;
 892
 893         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 894                 *vpos = position;
 895                 *hpos = 0;
 896         } else {
 897                 *vpos = position / htotal;
 898                 *hpos = position - (*vpos * htotal);
 899         }
 900
 901         /* In vblank? */
 902         if (in_vbl)
 903                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 904
 905         return ret;
 906 }
 907
 908 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 909 {
 910         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 911         unsigned long irqflags;
 912         int position;
 913
 914         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 915         position = __intel_get_crtc_scanline(crtc);
 916         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 917
 918         return position;
 919 }
 920
 921 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 922                               int *max_error,
 923                               struct timeval *vblank_time,
 924                               unsigned flags)
 925 {
 926         struct drm_crtc *crtc;
 927
 928         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 929                 DRM_ERROR("Invalid crtc %u\n", pipe);
 930                 return -EINVAL;
 931         }
 932
 933         /* Get drm_crtc to timestamp: */
 934         crtc = intel_get_crtc_for_pipe(dev, pipe);
 935         if (crtc == NULL) {
 936                 DRM_ERROR("Invalid crtc %u\n", pipe);
 937                 return -EINVAL;
 938         }
 939
 940         if (!crtc->hwmode.crtc_clock) {
 941                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 942                 return -EBUSY;
 943         }
 944
 945         /* Helper routine in DRM core does all the work: */
 946         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 947                                                      vblank_time, flags,
 948                                                      &crtc->hwmode);
 949 }
 950
 951 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 952 {
 953         u32 busy_up, busy_down, max_avg, min_avg;
 954         u8 new_delay;
 955
 956         spin_lock(&mchdev_lock);
 957
 958         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 959
 960         new_delay = dev_priv->ips.cur_delay;
 961
 962         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 963         busy_up = I915_READ(RCPREVBSYTUPAVG);
 964         busy_down = I915_READ(RCPREVBSYTDNAVG);
 965         max_avg = I915_READ(RCBMAXAVG);
 966         min_avg = I915_READ(RCBMINAVG);
 967
 968         /* Handle RCS change request from hw */
 969         if (busy_up > max_avg) {
 970                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 971                         new_delay = dev_priv->ips.cur_delay - 1;
 972                 if (new_delay < dev_priv->ips.max_delay)
 973                         new_delay = dev_priv->ips.max_delay;
 974         } else if (busy_down < min_avg) {
 975                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 976                         new_delay = dev_priv->ips.cur_delay + 1;
 977                 if (new_delay > dev_priv->ips.min_delay)
 978                         new_delay = dev_priv->ips.min_delay;
 979         }
 980
 981         if (ironlake_set_drps(dev_priv, new_delay))
 982                 dev_priv->ips.cur_delay = new_delay;
 983
 984         spin_unlock(&mchdev_lock);
 985
 986         return;
 987 }
 988
 989 static void notify_ring(struct intel_engine_cs *engine)
 990 {
 991         if (!intel_engine_initialized(engine))
 992                 return;
 993
 994         trace_i915_gem_request_notify(engine);
 995         engine->user_interrupts++;
 996
 997         wake_up_all(&engine->irq_queue);
 998 }
 999
1000 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1001                         struct intel_rps_ei *ei)
1002 {
1003         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1004         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1005         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1006 }
1007
1008 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1009                          const struct intel_rps_ei *old,
1010                          const struct intel_rps_ei *now,
1011                          int threshold)
1012 {
1013         u64 time, c0;
1014         unsigned int mul = 100;
1015
1016         if (old->cz_clock == 0)
1017                 return false;
1018
1019         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1020                 mul <<= 8;
1021
1022         time = now->cz_clock - old->cz_clock;
1023         time *= threshold * dev_priv->czclk_freq;
1024
1025         /* Workload can be split between render + media, e.g. SwapBuffers
1026          * being blitted in X after being rendered in mesa. To account for
1027          * this we need to combine both engines into our activity counter.
1028          */
1029         c0 = now->render_c0 - old->render_c0;
1030         c0 += now->media_c0 - old->media_c0;
1031         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1032
1033         return c0 >= time;
1034 }
1035
1036 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1037 {
1038         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1039         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1040 }
1041
1042 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1043 {
1044         struct intel_rps_ei now;
1045         u32 events = 0;
1046
1047         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1048                 return 0;
1049
1050         vlv_c0_read(dev_priv, &now);
1051         if (now.cz_clock == 0)
1052                 return 0;
1053
1054         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1055                 if (!vlv_c0_above(dev_priv,
1056                                   &dev_priv->rps.down_ei, &now,
1057                                   dev_priv->rps.down_threshold))
1058                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1059                 dev_priv->rps.down_ei = now;
1060         }
1061
1062         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1063                 if (vlv_c0_above(dev_priv,
1064                                  &dev_priv->rps.up_ei, &now,
1065                                  dev_priv->rps.up_threshold))
1066                         events |= GEN6_PM_RP_UP_THRESHOLD;
1067                 dev_priv->rps.up_ei = now;
1068         }
1069
1070         return events;
1071 }
1072
1073 static bool any_waiters(struct drm_i915_private *dev_priv)
1074 {
1075         struct intel_engine_cs *engine;
1076
1077         for_each_engine(engine, dev_priv)
1078                 if (engine->irq_refcount)
1079                         return true;
1080
1081         return false;
1082 }
1083
1084 static void gen6_pm_rps_work(struct work_struct *work)
1085 {
1086         struct drm_i915_private *dev_priv =
1087                 container_of(work, struct drm_i915_private, rps.work);
1088         bool client_boost;
1089         int new_delay, adj, min, max;
1090         u32 pm_iir;
1091
1092         spin_lock_irq(&dev_priv->irq_lock);
1093         /* Speed up work cancelation during disabling rps interrupts. */
1094         if (!dev_priv->rps.interrupts_enabled) {
1095                 spin_unlock_irq(&dev_priv->irq_lock);
1096                 return;
1097         }
1098
1099         /*
1100          * The RPS work is synced during runtime suspend, we don't require a
1101          * wakeref. TODO: instead of disabling the asserts make sure that we
1102          * always hold an RPM reference while the work is running.
1103          */
1104         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1105
1106         pm_iir = dev_priv->rps.pm_iir;
1107         dev_priv->rps.pm_iir = 0;
1108         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1109         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1110         client_boost = dev_priv->rps.client_boost;
1111         dev_priv->rps.client_boost = false;
1112         spin_unlock_irq(&dev_priv->irq_lock);
1113
1114         /* Make sure we didn't queue anything we're not going to process. */
1115         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1116
1117         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1118                 goto out;
1119
1120         mutex_lock(&dev_priv->rps.hw_lock);
1121
1122         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1123
1124         adj = dev_priv->rps.last_adj;
1125         new_delay = dev_priv->rps.cur_freq;
1126         min = dev_priv->rps.min_freq_softlimit;
1127         max = dev_priv->rps.max_freq_softlimit;
1128
1129         if (client_boost) {
1130                 new_delay = dev_priv->rps.max_freq_softlimit;
1131                 adj = 0;
1132         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1133                 if (adj > 0)
1134                         adj *= 2;
1135                 else /* CHV needs even encode values */
1136                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1137                 /*
1138                  * For better performance, jump directly
1139                  * to RPe if we're below it.
1140                  */
1141                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1142                         new_delay = dev_priv->rps.efficient_freq;
1143                         adj = 0;
1144                 }
1145         } else if (any_waiters(dev_priv)) {
1146                 adj = 0;
1147         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1148                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1149                         new_delay = dev_priv->rps.efficient_freq;
1150                 else
1151                         new_delay = dev_priv->rps.min_freq_softlimit;
1152                 adj = 0;
1153         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1154                 if (adj < 0)
1155                         adj *= 2;
1156                 else /* CHV needs even encode values */
1157                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1158         } else { /* unknown event */
1159                 adj = 0;
1160         }
1161
1162         dev_priv->rps.last_adj = adj;
1163
1164         /* sysfs frequency interfaces may have snuck in while servicing the
1165          * interrupt
1166          */
1167         new_delay += adj;
1168         new_delay = clamp_t(int, new_delay, min, max);
1169
1170         intel_set_rps(dev_priv, new_delay);
1171
1172         mutex_unlock(&dev_priv->rps.hw_lock);
1173 out:
1174         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1175 }
1176
1177
1178 /**
1179  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1180  * occurred.
1181  * @work: workqueue struct
1182  *
1183  * Doesn't actually do anything except notify userspace. As a consequence of
1184  * this event, userspace should try to remap the bad rows since statistically
1185  * it is likely the same row is more likely to go bad again.
1186  */
1187 static void ivybridge_parity_work(struct work_struct *work)
1188 {
1189         struct drm_i915_private *dev_priv =
1190                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1191         u32 error_status, row, bank, subbank;
1192         char *parity_event[6];
1193         uint32_t misccpctl;
1194         uint8_t slice = 0;
1195
1196         /* We must turn off DOP level clock gating to access the L3 registers.
1197          * In order to prevent a get/put style interface, acquire struct mutex
1198          * any time we access those registers.
1199          */
1200         mutex_lock(&dev_priv->dev->struct_mutex);
1201
1202         /* If we've screwed up tracking, just let the interrupt fire again */
1203         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1204                 goto out;
1205
1206         misccpctl = I915_READ(GEN7_MISCCPCTL);
1207         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1208         POSTING_READ(GEN7_MISCCPCTL);
1209
1210         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1211                 i915_reg_t reg;
1212
1213                 slice--;
1214                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1215                         break;
1216
1217                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1218
1219                 reg = GEN7_L3CDERRST1(slice);
1220
1221                 error_status = I915_READ(reg);
1222                 row = GEN7_PARITY_ERROR_ROW(error_status);
1223                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1224                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1225
1226                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1227                 POSTING_READ(reg);
1228
1229                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1230                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1231                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1232                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1233                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1234                 parity_event[5] = NULL;
1235
1236                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1237                                    KOBJ_CHANGE, parity_event);
1238
1239                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1240                           slice, row, bank, subbank);
1241
1242                 kfree(parity_event[4]);
1243                 kfree(parity_event[3]);
1244                 kfree(parity_event[2]);
1245                 kfree(parity_event[1]);
1246         }
1247
1248         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1249
1250 out:
1251         WARN_ON(dev_priv->l3_parity.which_slice);
1252         spin_lock_irq(&dev_priv->irq_lock);
1253         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1254         spin_unlock_irq(&dev_priv->irq_lock);
1255
1256         mutex_unlock(&dev_priv->dev->struct_mutex);
1257 }
1258
1259 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1260                                                u32 iir)
1261 {
1262         if (!HAS_L3_DPF(dev_priv))
1263                 return;
1264
1265         spin_lock(&dev_priv->irq_lock);
1266         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1267         spin_unlock(&dev_priv->irq_lock);
1268
1269         iir &= GT_PARITY_ERROR(dev_priv);
1270         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1271                 dev_priv->l3_parity.which_slice |= 1 << 1;
1272
1273         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1274                 dev_priv->l3_parity.which_slice |= 1 << 0;
1275
1276         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1277 }
1278
1279 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1280                                u32 gt_iir)
1281 {
1282         if (gt_iir &
1283             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1284                 notify_ring(&dev_priv->engine[RCS]);
1285         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1286                 notify_ring(&dev_priv->engine[VCS]);
1287 }
1288
1289 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1290                                u32 gt_iir)
1291 {
1292
1293         if (gt_iir &
1294             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1295                 notify_ring(&dev_priv->engine[RCS]);
1296         if (gt_iir & GT_BSD_USER_INTERRUPT)
1297                 notify_ring(&dev_priv->engine[VCS]);
1298         if (gt_iir & GT_BLT_USER_INTERRUPT)
1299                 notify_ring(&dev_priv->engine[BCS]);
1300
1301         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1302                       GT_BSD_CS_ERROR_INTERRUPT |
1303                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1304                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1305
1306         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1307                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1308 }
1309
1310 static __always_inline void
1311 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1312 {
1313         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1314                 notify_ring(engine);
1315         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1316                 tasklet_schedule(&engine->irq_tasklet);
1317 }
1318
1319 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1320                                    u32 master_ctl,
1321                                    u32 gt_iir[4])
1322 {
1323         irqreturn_t ret = IRQ_NONE;
1324
1325         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1326                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1327                 if (gt_iir[0]) {
1328                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1329                         ret = IRQ_HANDLED;
1330                 } else
1331                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1332         }
1333
1334         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1335                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1336                 if (gt_iir[1]) {
1337                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1338                         ret = IRQ_HANDLED;
1339                 } else
1340                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1341         }
1342
1343         if (master_ctl & GEN8_GT_VECS_IRQ) {
1344                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1345                 if (gt_iir[3]) {
1346                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1347                         ret = IRQ_HANDLED;
1348                 } else
1349                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1350         }
1351
1352         if (master_ctl & GEN8_GT_PM_IRQ) {
1353                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1354                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1355                         I915_WRITE_FW(GEN8_GT_IIR(2),
1356                                       gt_iir[2] & dev_priv->pm_rps_events);
1357                         ret = IRQ_HANDLED;
1358                 } else
1359                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1360         }
1361
1362         return ret;
1363 }
1364
1365 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1366                                 u32 gt_iir[4])
1367 {
1368         if (gt_iir[0]) {
1369                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1370                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1371                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1372                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1373         }
1374
1375         if (gt_iir[1]) {
1376                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1377                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1378                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1379                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1380         }
1381
1382         if (gt_iir[3])
1383                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1384                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1385
1386         if (gt_iir[2] & dev_priv->pm_rps_events)
1387                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1388 }
1389
1390 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1391 {
1392         switch (port) {
1393         case PORT_A:
1394                 return val & PORTA_HOTPLUG_LONG_DETECT;
1395         case PORT_B:
1396                 return val & PORTB_HOTPLUG_LONG_DETECT;
1397         case PORT_C:
1398                 return val & PORTC_HOTPLUG_LONG_DETECT;
1399         default:
1400                 return false;
1401         }
1402 }
1403
1404 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1405 {
1406         switch (port) {
1407         case PORT_E:
1408                 return val & PORTE_HOTPLUG_LONG_DETECT;
1409         default:
1410                 return false;
1411         }
1412 }
1413
1414 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1415 {
1416         switch (port) {
1417         case PORT_A:
1418                 return val & PORTA_HOTPLUG_LONG_DETECT;
1419         case PORT_B:
1420                 return val & PORTB_HOTPLUG_LONG_DETECT;
1421         case PORT_C:
1422                 return val & PORTC_HOTPLUG_LONG_DETECT;
1423         case PORT_D:
1424                 return val & PORTD_HOTPLUG_LONG_DETECT;
1425         default:
1426                 return false;
1427         }
1428 }
1429
1430 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1431 {
1432         switch (port) {
1433         case PORT_A:
1434                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1435         default:
1436                 return false;
1437         }
1438 }
1439
1440 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1441 {
1442         switch (port) {
1443         case PORT_B:
1444                 return val & PORTB_HOTPLUG_LONG_DETECT;
1445         case PORT_C:
1446                 return val & PORTC_HOTPLUG_LONG_DETECT;
1447         case PORT_D:
1448                 return val & PORTD_HOTPLUG_LONG_DETECT;
1449         default:
1450                 return false;
1451         }
1452 }
1453
1454 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1455 {
1456         switch (port) {
1457         case PORT_B:
1458                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1459         case PORT_C:
1460                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1461         case PORT_D:
1462                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1463         default:
1464                 return false;
1465         }
1466 }
1467
1468 /*
1469  * Get a bit mask of pins that have triggered, and which ones may be long.
1470  * This can be called multiple times with the same masks to accumulate
1471  * hotplug detection results from several registers.
1472  *
1473  * Note that the caller is expected to zero out the masks initially.
1474  */
1475 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1476                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1477                              const u32 hpd[HPD_NUM_PINS],
1478                              bool long_pulse_detect(enum port port, u32 val))
1479 {
1480         enum port port;
1481         int i;
1482
1483         for_each_hpd_pin(i) {
1484                 if ((hpd[i] & hotplug_trigger) == 0)
1485                         continue;
1486
1487                 *pin_mask |= BIT(i);
1488
1489                 if (!intel_hpd_pin_to_port(i, &port))
1490                         continue;
1491
1492                 if (long_pulse_detect(port, dig_hotplug_reg))
1493                         *long_mask |= BIT(i);
1494         }
1495
1496         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1497                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1498
1499 }
1500
1501 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1502 {
1503         wake_up_all(&dev_priv->gmbus_wait_queue);
1504 }
1505
1506 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1507 {
1508         wake_up_all(&dev_priv->gmbus_wait_queue);
1509 }
1510
1511 #if defined(CONFIG_DEBUG_FS)
1512 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1513                                          enum pipe pipe,
1514                                          uint32_t crc0, uint32_t crc1,
1515                                          uint32_t crc2, uint32_t crc3,
1516                                          uint32_t crc4)
1517 {
1518         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1519         struct intel_pipe_crc_entry *entry;
1520         int head, tail;
1521
1522         spin_lock(&pipe_crc->lock);
1523
1524         if (!pipe_crc->entries) {
1525                 spin_unlock(&pipe_crc->lock);
1526                 DRM_DEBUG_KMS("spurious interrupt\n");
1527                 return;
1528         }
1529
1530         head = pipe_crc->head;
1531         tail = pipe_crc->tail;
1532
1533         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1534                 spin_unlock(&pipe_crc->lock);
1535                 DRM_ERROR("CRC buffer overflowing\n");
1536                 return;
1537         }
1538
1539         entry = &pipe_crc->entries[head];
1540
1541         entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
1542                                                                  pipe);
1543         entry->crc[0] = crc0;
1544         entry->crc[1] = crc1;
1545         entry->crc[2] = crc2;
1546         entry->crc[3] = crc3;
1547         entry->crc[4] = crc4;
1548
1549         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1550         pipe_crc->head = head;
1551
1552         spin_unlock(&pipe_crc->lock);
1553
1554         wake_up_interruptible(&pipe_crc->wq);
1555 }
1556 #else
1557 static inline void
1558 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1559                              enum pipe pipe,
1560                              uint32_t crc0, uint32_t crc1,
1561                              uint32_t crc2, uint32_t crc3,
1562                              uint32_t crc4) {}
1563 #endif
1564
1565
1566 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1567                                      enum pipe pipe)
1568 {
1569         display_pipe_crc_irq_handler(dev_priv, pipe,
1570                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1571                                      0, 0, 0, 0);
1572 }
1573
1574 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1575                                      enum pipe pipe)
1576 {
1577         display_pipe_crc_irq_handler(dev_priv, pipe,
1578                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1579                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1580                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1581                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1582                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1583 }
1584
1585 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1586                                       enum pipe pipe)
1587 {
1588         uint32_t res1, res2;
1589
1590         if (INTEL_GEN(dev_priv) >= 3)
1591                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1592         else
1593                 res1 = 0;
1594
1595         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1596                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1597         else
1598                 res2 = 0;
1599
1600         display_pipe_crc_irq_handler(dev_priv, pipe,
1601                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1602                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1603                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1604                                      res1, res2);
1605 }
1606
1607 /* The RPS events need forcewake, so we add them to a work queue and mask their
1608  * IMR bits until the work is done. Other interrupts can be processed without
1609  * the work queue. */
1610 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1611 {
1612         if (pm_iir & dev_priv->pm_rps_events) {
1613                 spin_lock(&dev_priv->irq_lock);
1614                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1615                 if (dev_priv->rps.interrupts_enabled) {
1616                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1617                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1618                 }
1619                 spin_unlock(&dev_priv->irq_lock);
1620         }
1621
1622         if (INTEL_INFO(dev_priv)->gen >= 8)
1623                 return;
1624
1625         if (HAS_VEBOX(dev_priv)) {
1626                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1627                         notify_ring(&dev_priv->engine[VECS]);
1628
1629                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1630                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1631         }
1632 }
1633
1634 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1635                                      enum pipe pipe)
1636 {
1637         bool ret;
1638
1639         ret = drm_handle_vblank(dev_priv->dev, pipe);
1640         if (ret)
1641                 intel_finish_page_flip_mmio(dev_priv, pipe);
1642
1643         return ret;
1644 }
1645
1646 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1647                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1648 {
1649         int pipe;
1650
1651         spin_lock(&dev_priv->irq_lock);
1652
1653         if (!dev_priv->display_irqs_enabled) {
1654                 spin_unlock(&dev_priv->irq_lock);
1655                 return;
1656         }
1657
1658         for_each_pipe(dev_priv, pipe) {
1659                 i915_reg_t reg;
1660                 u32 mask, iir_bit = 0;
1661
1662                 /*
1663                  * PIPESTAT bits get signalled even when the interrupt is
1664                  * disabled with the mask bits, and some of the status bits do
1665                  * not generate interrupts at all (like the underrun bit). Hence
1666                  * we need to be careful that we only handle what we want to
1667                  * handle.
1668                  */
1669
1670                 /* fifo underruns are filterered in the underrun handler. */
1671                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1672
1673                 switch (pipe) {
1674                 case PIPE_A:
1675                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1676                         break;
1677                 case PIPE_B:
1678                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1679                         break;
1680                 case PIPE_C:
1681                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1682                         break;
1683                 }
1684                 if (iir & iir_bit)
1685                         mask |= dev_priv->pipestat_irq_mask[pipe];
1686
1687                 if (!mask)
1688                         continue;
1689
1690                 reg = PIPESTAT(pipe);
1691                 mask |= PIPESTAT_INT_ENABLE_MASK;
1692                 pipe_stats[pipe] = I915_READ(reg) & mask;
1693
1694                 /*
1695                  * Clear the PIPE*STAT regs before the IIR
1696                  */
1697                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1698                                         PIPESTAT_INT_STATUS_MASK))
1699                         I915_WRITE(reg, pipe_stats[pipe]);
1700         }
1701         spin_unlock(&dev_priv->irq_lock);
1702 }
1703
1704 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1705                                             u32 pipe_stats[I915_MAX_PIPES])
1706 {
1707         enum pipe pipe;
1708
1709         for_each_pipe(dev_priv, pipe) {
1710                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1711                     intel_pipe_handle_vblank(dev_priv, pipe))
1712                         intel_check_page_flip(dev_priv, pipe);
1713
1714                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1715                         intel_finish_page_flip_cs(dev_priv, pipe);
1716
1717                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1718                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1719
1720                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1721                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1722         }
1723
1724         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1725                 gmbus_irq_handler(dev_priv);
1726 }
1727
1728 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1729 {
1730         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1731
1732         if (hotplug_status)
1733                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1734
1735         return hotplug_status;
1736 }
1737
1738 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1739                                  u32 hotplug_status)
1740 {
1741         u32 pin_mask = 0, long_mask = 0;
1742
1743         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1744             IS_CHERRYVIEW(dev_priv)) {
1745                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1746
1747                 if (hotplug_trigger) {
1748                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1749                                            hotplug_trigger, hpd_status_g4x,
1750                                            i9xx_port_hotplug_long_detect);
1751
1752                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1753                 }
1754
1755                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1756                         dp_aux_irq_handler(dev_priv);
1757         } else {
1758                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1759
1760                 if (hotplug_trigger) {
1761                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1762                                            hotplug_trigger, hpd_status_i915,
1763                                            i9xx_port_hotplug_long_detect);
1764                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1765                 }
1766         }
1767 }
1768
1769 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1770 {
1771         struct drm_device *dev = arg;
1772         struct drm_i915_private *dev_priv = dev->dev_private;
1773         irqreturn_t ret = IRQ_NONE;
1774
1775         if (!intel_irqs_enabled(dev_priv))
1776                 return IRQ_NONE;
1777
1778         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1779         disable_rpm_wakeref_asserts(dev_priv);
1780
1781         do {
1782                 u32 iir, gt_iir, pm_iir;
1783                 u32 pipe_stats[I915_MAX_PIPES] = {};
1784                 u32 hotplug_status = 0;
1785                 u32 ier = 0;
1786
1787                 gt_iir = I915_READ(GTIIR);
1788                 pm_iir = I915_READ(GEN6_PMIIR);
1789                 iir = I915_READ(VLV_IIR);
1790
1791                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1792                         break;
1793
1794                 ret = IRQ_HANDLED;
1795
1796                 /*
1797                  * Theory on interrupt generation, based on empirical evidence:
1798                  *
1799                  * x = ((VLV_IIR & VLV_IER) ||
1800                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1801                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1802                  *
1803                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1804                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1805                  * guarantee the CPU interrupt will be raised again even if we
1806                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1807                  * bits this time around.
1808                  */
1809                 I915_WRITE(VLV_MASTER_IER, 0);
1810                 ier = I915_READ(VLV_IER);
1811                 I915_WRITE(VLV_IER, 0);
1812
1813                 if (gt_iir)
1814                         I915_WRITE(GTIIR, gt_iir);
1815                 if (pm_iir)
1816                         I915_WRITE(GEN6_PMIIR, pm_iir);
1817
1818                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1819                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1820
1821                 /* Call regardless, as some status bits might not be
1822                  * signalled in iir */
1823                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1824
1825                 /*
1826                  * VLV_IIR is single buffered, and reflects the level
1827                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1828                  */
1829                 if (iir)
1830                         I915_WRITE(VLV_IIR, iir);
1831
1832                 I915_WRITE(VLV_IER, ier);
1833                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1834                 POSTING_READ(VLV_MASTER_IER);
1835
1836                 if (gt_iir)
1837                         snb_gt_irq_handler(dev_priv, gt_iir);
1838                 if (pm_iir)
1839                         gen6_rps_irq_handler(dev_priv, pm_iir);
1840
1841                 if (hotplug_status)
1842                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1843
1844                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1845         } while (0);
1846
1847         enable_rpm_wakeref_asserts(dev_priv);
1848
1849         return ret;
1850 }
1851
1852 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1853 {
1854         struct drm_device *dev = arg;
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         irqreturn_t ret = IRQ_NONE;
1857
1858         if (!intel_irqs_enabled(dev_priv))
1859                 return IRQ_NONE;
1860
1861         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1862         disable_rpm_wakeref_asserts(dev_priv);
1863
1864         do {
1865                 u32 master_ctl, iir;
1866                 u32 gt_iir[4] = {};
1867                 u32 pipe_stats[I915_MAX_PIPES] = {};
1868                 u32 hotplug_status = 0;
1869                 u32 ier = 0;
1870
1871                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1872                 iir = I915_READ(VLV_IIR);
1873
1874                 if (master_ctl == 0 && iir == 0)
1875                         break;
1876
1877                 ret = IRQ_HANDLED;
1878
1879                 /*
1880                  * Theory on interrupt generation, based on empirical evidence:
1881                  *
1882                  * x = ((VLV_IIR & VLV_IER) ||
1883                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1884                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1885                  *
1886                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1887                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1888                  * guarantee the CPU interrupt will be raised again even if we
1889                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1890                  * bits this time around.
1891                  */
1892                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1893                 ier = I915_READ(VLV_IER);
1894                 I915_WRITE(VLV_IER, 0);
1895
1896                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1897
1898                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1899                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1900
1901                 /* Call regardless, as some status bits might not be
1902                  * signalled in iir */
1903                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1904
1905                 /*
1906                  * VLV_IIR is single buffered, and reflects the level
1907                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1908                  */
1909                 if (iir)
1910                         I915_WRITE(VLV_IIR, iir);
1911
1912                 I915_WRITE(VLV_IER, ier);
1913                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1914                 POSTING_READ(GEN8_MASTER_IRQ);
1915
1916                 gen8_gt_irq_handler(dev_priv, gt_iir);
1917
1918                 if (hotplug_status)
1919                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1920
1921                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1922         } while (0);
1923
1924         enable_rpm_wakeref_asserts(dev_priv);
1925
1926         return ret;
1927 }
1928
1929 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1930                                 u32 hotplug_trigger,
1931                                 const u32 hpd[HPD_NUM_PINS])
1932 {
1933         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1934
1935         /*
1936          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1937          * unless we touch the hotplug register, even if hotplug_trigger is
1938          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1939          * errors.
1940          */
1941         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1942         if (!hotplug_trigger) {
1943                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1944                         PORTD_HOTPLUG_STATUS_MASK |
1945                         PORTC_HOTPLUG_STATUS_MASK |
1946                         PORTB_HOTPLUG_STATUS_MASK;
1947                 dig_hotplug_reg &= ~mask;
1948         }
1949
1950         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1951         if (!hotplug_trigger)
1952                 return;
1953
1954         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1955                            dig_hotplug_reg, hpd,
1956                            pch_port_hotplug_long_detect);
1957
1958         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1959 }
1960
1961 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1962 {
1963         int pipe;
1964         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1965
1966         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1967
1968         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1969                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1970                                SDE_AUDIO_POWER_SHIFT);
1971                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1972                                  port_name(port));
1973         }
1974
1975         if (pch_iir & SDE_AUX_MASK)
1976                 dp_aux_irq_handler(dev_priv);
1977
1978         if (pch_iir & SDE_GMBUS)
1979                 gmbus_irq_handler(dev_priv);
1980
1981         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1982                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1983
1984         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1985                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1986
1987         if (pch_iir & SDE_POISON)
1988                 DRM_ERROR("PCH poison interrupt\n");
1989
1990         if (pch_iir & SDE_FDI_MASK)
1991                 for_each_pipe(dev_priv, pipe)
1992                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1993                                          pipe_name(pipe),
1994                                          I915_READ(FDI_RX_IIR(pipe)));
1995
1996         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1997                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1998
1999         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2000                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2001
2002         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2003                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2004
2005         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2006                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2007 }
2008
2009 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2010 {
2011         u32 err_int = I915_READ(GEN7_ERR_INT);
2012         enum pipe pipe;
2013
2014         if (err_int & ERR_INT_POISON)
2015                 DRM_ERROR("Poison interrupt\n");
2016
2017         for_each_pipe(dev_priv, pipe) {
2018                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2019                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2020
2021                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2022                         if (IS_IVYBRIDGE(dev_priv))
2023                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2024                         else
2025                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2026                 }
2027         }
2028
2029         I915_WRITE(GEN7_ERR_INT, err_int);
2030 }
2031
2032 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2033 {
2034         u32 serr_int = I915_READ(SERR_INT);
2035
2036         if (serr_int & SERR_INT_POISON)
2037                 DRM_ERROR("PCH poison interrupt\n");
2038
2039         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2040                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2041
2042         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2043                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2044
2045         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2046                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2047
2048         I915_WRITE(SERR_INT, serr_int);
2049 }
2050
2051 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2052 {
2053         int pipe;
2054         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2055
2056         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2057
2058         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2059                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2060                                SDE_AUDIO_POWER_SHIFT_CPT);
2061                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2062                                  port_name(port));
2063         }
2064
2065         if (pch_iir & SDE_AUX_MASK_CPT)
2066                 dp_aux_irq_handler(dev_priv);
2067
2068         if (pch_iir & SDE_GMBUS_CPT)
2069                 gmbus_irq_handler(dev_priv);
2070
2071         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2072                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2073
2074         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2075                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2076
2077         if (pch_iir & SDE_FDI_MASK_CPT)
2078                 for_each_pipe(dev_priv, pipe)
2079                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2080                                          pipe_name(pipe),
2081                                          I915_READ(FDI_RX_IIR(pipe)));
2082
2083         if (pch_iir & SDE_ERROR_CPT)
2084                 cpt_serr_int_handler(dev_priv);
2085 }
2086
2087 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2088 {
2089         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2090                 ~SDE_PORTE_HOTPLUG_SPT;
2091         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2092         u32 pin_mask = 0, long_mask = 0;
2093
2094         if (hotplug_trigger) {
2095                 u32 dig_hotplug_reg;
2096
2097                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2098                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2099
2100                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2101                                    dig_hotplug_reg, hpd_spt,
2102                                    spt_port_hotplug_long_detect);
2103         }
2104
2105         if (hotplug2_trigger) {
2106                 u32 dig_hotplug_reg;
2107
2108                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2109                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2110
2111                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2112                                    dig_hotplug_reg, hpd_spt,
2113                                    spt_port_hotplug2_long_detect);
2114         }
2115
2116         if (pin_mask)
2117                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2118
2119         if (pch_iir & SDE_GMBUS_CPT)
2120                 gmbus_irq_handler(dev_priv);
2121 }
2122
2123 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2124                                 u32 hotplug_trigger,
2125                                 const u32 hpd[HPD_NUM_PINS])
2126 {
2127         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2128
2129         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2130         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2131
2132         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2133                            dig_hotplug_reg, hpd,
2134                            ilk_port_hotplug_long_detect);
2135
2136         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2137 }
2138
2139 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2140                                     u32 de_iir)
2141 {
2142         enum pipe pipe;
2143         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2144
2145         if (hotplug_trigger)
2146                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2147
2148         if (de_iir & DE_AUX_CHANNEL_A)
2149                 dp_aux_irq_handler(dev_priv);
2150
2151         if (de_iir & DE_GSE)
2152                 intel_opregion_asle_intr(dev_priv);
2153
2154         if (de_iir & DE_POISON)
2155                 DRM_ERROR("Poison interrupt\n");
2156
2157         for_each_pipe(dev_priv, pipe) {
2158                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2159                     intel_pipe_handle_vblank(dev_priv, pipe))
2160                         intel_check_page_flip(dev_priv, pipe);
2161
2162                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2163                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2164
2165                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2166                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2167
2168                 /* plane/pipes map 1:1 on ilk+ */
2169                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2170                         intel_finish_page_flip_cs(dev_priv, pipe);
2171         }
2172
2173         /* check event from PCH */
2174         if (de_iir & DE_PCH_EVENT) {
2175                 u32 pch_iir = I915_READ(SDEIIR);
2176
2177                 if (HAS_PCH_CPT(dev_priv))
2178                         cpt_irq_handler(dev_priv, pch_iir);
2179                 else
2180                         ibx_irq_handler(dev_priv, pch_iir);
2181
2182                 /* should clear PCH hotplug event before clear CPU irq */
2183                 I915_WRITE(SDEIIR, pch_iir);
2184         }
2185
2186         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2187                 ironlake_rps_change_irq_handler(dev_priv);
2188 }
2189
2190 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2191                                     u32 de_iir)
2192 {
2193         enum pipe pipe;
2194         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2195
2196         if (hotplug_trigger)
2197                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2198
2199         if (de_iir & DE_ERR_INT_IVB)
2200                 ivb_err_int_handler(dev_priv);
2201
2202         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2203                 dp_aux_irq_handler(dev_priv);
2204
2205         if (de_iir & DE_GSE_IVB)
2206                 intel_opregion_asle_intr(dev_priv);
2207
2208         for_each_pipe(dev_priv, pipe) {
2209                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2210                     intel_pipe_handle_vblank(dev_priv, pipe))
2211                         intel_check_page_flip(dev_priv, pipe);
2212
2213                 /* plane/pipes map 1:1 on ilk+ */
2214                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2215                         intel_finish_page_flip_cs(dev_priv, pipe);
2216         }
2217
2218         /* check event from PCH */
2219         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2220                 u32 pch_iir = I915_READ(SDEIIR);
2221
2222                 cpt_irq_handler(dev_priv, pch_iir);
2223
2224                 /* clear PCH hotplug event before clear CPU irq */
2225                 I915_WRITE(SDEIIR, pch_iir);
2226         }
2227 }
2228
2229 /*
2230  * To handle irqs with the minimum potential races with fresh interrupts, we:
2231  * 1 - Disable Master Interrupt Control.
2232  * 2 - Find the source(s) of the interrupt.
2233  * 3 - Clear the Interrupt Identity bits (IIR).
2234  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2235  * 5 - Re-enable Master Interrupt Control.
2236  */
2237 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2238 {
2239         struct drm_device *dev = arg;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2242         irqreturn_t ret = IRQ_NONE;
2243
2244         if (!intel_irqs_enabled(dev_priv))
2245                 return IRQ_NONE;
2246
2247         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2248         disable_rpm_wakeref_asserts(dev_priv);
2249
2250         /* disable master interrupt before clearing iir  */
2251         de_ier = I915_READ(DEIER);
2252         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2253         POSTING_READ(DEIER);
2254
2255         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2256          * interrupts will will be stored on its back queue, and then we'll be
2257          * able to process them after we restore SDEIER (as soon as we restore
2258          * it, we'll get an interrupt if SDEIIR still has something to process
2259          * due to its back queue). */
2260         if (!HAS_PCH_NOP(dev_priv)) {
2261                 sde_ier = I915_READ(SDEIER);
2262                 I915_WRITE(SDEIER, 0);
2263                 POSTING_READ(SDEIER);
2264         }
2265
2266         /* Find, clear, then process each source of interrupt */
2267
2268         gt_iir = I915_READ(GTIIR);
2269         if (gt_iir) {
2270                 I915_WRITE(GTIIR, gt_iir);
2271                 ret = IRQ_HANDLED;
2272                 if (INTEL_GEN(dev_priv) >= 6)
2273                         snb_gt_irq_handler(dev_priv, gt_iir);
2274                 else
2275                         ilk_gt_irq_handler(dev_priv, gt_iir);
2276         }
2277
2278         de_iir = I915_READ(DEIIR);
2279         if (de_iir) {
2280                 I915_WRITE(DEIIR, de_iir);
2281                 ret = IRQ_HANDLED;
2282                 if (INTEL_GEN(dev_priv) >= 7)
2283                         ivb_display_irq_handler(dev_priv, de_iir);
2284                 else
2285                         ilk_display_irq_handler(dev_priv, de_iir);
2286         }
2287
2288         if (INTEL_GEN(dev_priv) >= 6) {
2289                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2290                 if (pm_iir) {
2291                         I915_WRITE(GEN6_PMIIR, pm_iir);
2292                         ret = IRQ_HANDLED;
2293                         gen6_rps_irq_handler(dev_priv, pm_iir);
2294                 }
2295         }
2296
2297         I915_WRITE(DEIER, de_ier);
2298         POSTING_READ(DEIER);
2299         if (!HAS_PCH_NOP(dev_priv)) {
2300                 I915_WRITE(SDEIER, sde_ier);
2301                 POSTING_READ(SDEIER);
2302         }
2303
2304         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2305         enable_rpm_wakeref_asserts(dev_priv);
2306
2307         return ret;
2308 }
2309
2310 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2311                                 u32 hotplug_trigger,
2312                                 const u32 hpd[HPD_NUM_PINS])
2313 {
2314         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2315
2316         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2317         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2318
2319         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2320                            dig_hotplug_reg, hpd,
2321                            bxt_port_hotplug_long_detect);
2322
2323         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2324 }
2325
2326 static irqreturn_t
2327 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2328 {
2329         irqreturn_t ret = IRQ_NONE;
2330         u32 iir;
2331         enum pipe pipe;
2332
2333         if (master_ctl & GEN8_DE_MISC_IRQ) {
2334                 iir = I915_READ(GEN8_DE_MISC_IIR);
2335                 if (iir) {
2336                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2337                         ret = IRQ_HANDLED;
2338                         if (iir & GEN8_DE_MISC_GSE)
2339                                 intel_opregion_asle_intr(dev_priv);
2340                         else
2341                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2342                 }
2343                 else
2344                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2345         }
2346
2347         if (master_ctl & GEN8_DE_PORT_IRQ) {
2348                 iir = I915_READ(GEN8_DE_PORT_IIR);
2349                 if (iir) {
2350                         u32 tmp_mask;
2351                         bool found = false;
2352
2353                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2354                         ret = IRQ_HANDLED;
2355
2356                         tmp_mask = GEN8_AUX_CHANNEL_A;
2357                         if (INTEL_INFO(dev_priv)->gen >= 9)
2358                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2359                                             GEN9_AUX_CHANNEL_C |
2360                                             GEN9_AUX_CHANNEL_D;
2361
2362                         if (iir & tmp_mask) {
2363                                 dp_aux_irq_handler(dev_priv);
2364                                 found = true;
2365                         }
2366
2367                         if (IS_BROXTON(dev_priv)) {
2368                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2369                                 if (tmp_mask) {
2370                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2371                                                             hpd_bxt);
2372                                         found = true;
2373                                 }
2374                         } else if (IS_BROADWELL(dev_priv)) {
2375                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2376                                 if (tmp_mask) {
2377                                         ilk_hpd_irq_handler(dev_priv,
2378                                                             tmp_mask, hpd_bdw);
2379                                         found = true;
2380                                 }
2381                         }
2382
2383                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2384                                 gmbus_irq_handler(dev_priv);
2385                                 found = true;
2386                         }
2387
2388                         if (!found)
2389                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2390                 }
2391                 else
2392                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2393         }
2394
2395         for_each_pipe(dev_priv, pipe) {
2396                 u32 flip_done, fault_errors;
2397
2398                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2399                         continue;
2400
2401                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2402                 if (!iir) {
2403                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2404                         continue;
2405                 }
2406
2407                 ret = IRQ_HANDLED;
2408                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2409
2410                 if (iir & GEN8_PIPE_VBLANK &&
2411                     intel_pipe_handle_vblank(dev_priv, pipe))
2412                         intel_check_page_flip(dev_priv, pipe);
2413
2414                 flip_done = iir;
2415                 if (INTEL_INFO(dev_priv)->gen >= 9)
2416                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2417                 else
2418                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2419
2420                 if (flip_done)
2421                         intel_finish_page_flip_cs(dev_priv, pipe);
2422
2423                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2424                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2425
2426                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2427                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2428
2429                 fault_errors = iir;
2430                 if (INTEL_INFO(dev_priv)->gen >= 9)
2431                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2432                 else
2433                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2434
2435                 if (fault_errors)
2436                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2437                                   pipe_name(pipe),
2438                                   fault_errors);
2439         }
2440
2441         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2442             master_ctl & GEN8_DE_PCH_IRQ) {
2443                 /*
2444                  * FIXME(BDW): Assume for now that the new interrupt handling
2445                  * scheme also closed the SDE interrupt handling race we've seen
2446                  * on older pch-split platforms. But this needs testing.
2447                  */
2448                 iir = I915_READ(SDEIIR);
2449                 if (iir) {
2450                         I915_WRITE(SDEIIR, iir);
2451                         ret = IRQ_HANDLED;
2452
2453                         if (HAS_PCH_SPT(dev_priv))
2454                                 spt_irq_handler(dev_priv, iir);
2455                         else
2456                                 cpt_irq_handler(dev_priv, iir);
2457                 } else {
2458                         /*
2459                          * Like on previous PCH there seems to be something
2460                          * fishy going on with forwarding PCH interrupts.
2461                          */
2462                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2463                 }
2464         }
2465
2466         return ret;
2467 }
2468
2469 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2470 {
2471         struct drm_device *dev = arg;
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         u32 master_ctl;
2474         u32 gt_iir[4] = {};
2475         irqreturn_t ret;
2476
2477         if (!intel_irqs_enabled(dev_priv))
2478                 return IRQ_NONE;
2479
2480         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2481         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2482         if (!master_ctl)
2483                 return IRQ_NONE;
2484
2485         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2486
2487         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2488         disable_rpm_wakeref_asserts(dev_priv);
2489
2490         /* Find, clear, then process each source of interrupt */
2491         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2492         gen8_gt_irq_handler(dev_priv, gt_iir);
2493         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2494
2495         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2496         POSTING_READ_FW(GEN8_MASTER_IRQ);
2497
2498         enable_rpm_wakeref_asserts(dev_priv);
2499
2500         return ret;
2501 }
2502
2503 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2504                                bool reset_completed)
2505 {
2506         struct intel_engine_cs *engine;
2507
2508         /*
2509          * Notify all waiters for GPU completion events that reset state has
2510          * been changed, and that they need to restart their wait after
2511          * checking for potential errors (and bail out to drop locks if there is
2512          * a gpu reset pending so that i915_error_work_func can acquire them).
2513          */
2514
2515         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2516         for_each_engine(engine, dev_priv)
2517                 wake_up_all(&engine->irq_queue);
2518
2519         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2520         wake_up_all(&dev_priv->pending_flip_queue);
2521
2522         /*
2523          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2524          * reset state is cleared.
2525          */
2526         if (reset_completed)
2527                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2528 }
2529
2530 /**
2531  * i915_reset_and_wakeup - do process context error handling work
2532  * @dev: drm device
2533  *
2534  * Fire an error uevent so userspace can see that a hang or error
2535  * was detected.
2536  */
2537 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2538 {
2539         struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2540         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2541         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2542         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2543         int ret;
2544
2545         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2546
2547         /*
2548          * Note that there's only one work item which does gpu resets, so we
2549          * need not worry about concurrent gpu resets potentially incrementing
2550          * error->reset_counter twice. We only need to take care of another
2551          * racing irq/hangcheck declaring the gpu dead for a second time. A
2552          * quick check for that is good enough: schedule_work ensures the
2553          * correct ordering between hang detection and this work item, and since
2554          * the reset in-progress bit is only ever set by code outside of this
2555          * work we don't need to worry about any other races.
2556          */
2557         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2558                 DRM_DEBUG_DRIVER("resetting chip\n");
2559                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2560
2561                 /*
2562                  * In most cases it's guaranteed that we get here with an RPM
2563                  * reference held, for example because there is a pending GPU
2564                  * request that won't finish until the reset is done. This
2565                  * isn't the case at least when we get here by doing a
2566                  * simulated reset via debugs, so get an RPM reference.
2567                  */
2568                 intel_runtime_pm_get(dev_priv);
2569
2570                 intel_prepare_reset(dev_priv);
2571
2572                 /*
2573                  * All state reset _must_ be completed before we update the
2574                  * reset counter, for otherwise waiters might miss the reset
2575                  * pending state and not properly drop locks, resulting in
2576                  * deadlocks with the reset work.
2577                  */
2578                 ret = i915_reset(dev_priv);
2579
2580                 intel_finish_reset(dev_priv);
2581
2582                 intel_runtime_pm_put(dev_priv);
2583
2584                 if (ret == 0)
2585                         kobject_uevent_env(kobj,
2586                                            KOBJ_CHANGE, reset_done_event);
2587
2588                 /*
2589                  * Note: The wake_up also serves as a memory barrier so that
2590                  * waiters see the update value of the reset counter atomic_t.
2591                  */
2592                 i915_error_wake_up(dev_priv, true);
2593         }
2594 }
2595
2596 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2597 {
2598         uint32_t instdone[I915_NUM_INSTDONE_REG];
2599         u32 eir = I915_READ(EIR);
2600         int pipe, i;
2601
2602         if (!eir)
2603                 return;
2604
2605         pr_err("render error detected, EIR: 0x%08x\n", eir);
2606
2607         i915_get_extra_instdone(dev_priv, instdone);
2608
2609         if (IS_G4X(dev_priv)) {
2610                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2611                         u32 ipeir = I915_READ(IPEIR_I965);
2612
2613                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2614                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2615                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2616                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2617                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2618                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2619                         I915_WRITE(IPEIR_I965, ipeir);
2620                         POSTING_READ(IPEIR_I965);
2621                 }
2622                 if (eir & GM45_ERROR_PAGE_TABLE) {
2623                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2624                         pr_err("page table error\n");
2625                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2626                         I915_WRITE(PGTBL_ER, pgtbl_err);
2627                         POSTING_READ(PGTBL_ER);
2628                 }
2629         }
2630
2631         if (!IS_GEN2(dev_priv)) {
2632                 if (eir & I915_ERROR_PAGE_TABLE) {
2633                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2634                         pr_err("page table error\n");
2635                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2636                         I915_WRITE(PGTBL_ER, pgtbl_err);
2637                         POSTING_READ(PGTBL_ER);
2638                 }
2639         }
2640
2641         if (eir & I915_ERROR_MEMORY_REFRESH) {
2642                 pr_err("memory refresh error:\n");
2643                 for_each_pipe(dev_priv, pipe)
2644                         pr_err("pipe %c stat: 0x%08x\n",
2645                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2646                 /* pipestat has already been acked */
2647         }
2648         if (eir & I915_ERROR_INSTRUCTION) {
2649                 pr_err("instruction error\n");
2650                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2651                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2652                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2653                 if (INTEL_GEN(dev_priv) < 4) {
2654                         u32 ipeir = I915_READ(IPEIR);
2655
2656                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2657                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2658                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2659                         I915_WRITE(IPEIR, ipeir);
2660                         POSTING_READ(IPEIR);
2661                 } else {
2662                         u32 ipeir = I915_READ(IPEIR_I965);
2663
2664                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2665                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2666                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2667                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2668                         I915_WRITE(IPEIR_I965, ipeir);
2669                         POSTING_READ(IPEIR_I965);
2670                 }
2671         }
2672
2673         I915_WRITE(EIR, eir);
2674         POSTING_READ(EIR);
2675         eir = I915_READ(EIR);
2676         if (eir) {
2677                 /*
2678                  * some errors might have become stuck,
2679                  * mask them.
2680                  */
2681                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2682                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2683                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2684         }
2685 }
2686
2687 /**
2688  * i915_handle_error - handle a gpu error
2689  * @dev: drm device
2690  * @engine_mask: mask representing engines that are hung
2691  * Do some basic checking of register state at error time and
2692  * dump it to the syslog.  Also call i915_capture_error_state() to make
2693  * sure we get a record and make it available in debugfs.  Fire a uevent
2694  * so userspace knows something bad happened (should trigger collection
2695  * of a ring dump etc.).
2696  */
2697 void i915_handle_error(struct drm_i915_private *dev_priv,
2698                        u32 engine_mask,
2699                        const char *fmt, ...)
2700 {
2701         va_list args;
2702         char error_msg[80];
2703
2704         va_start(args, fmt);
2705         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2706         va_end(args);
2707
2708         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2709         i915_report_and_clear_eir(dev_priv);
2710
2711         if (engine_mask) {
2712                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2713                                 &dev_priv->gpu_error.reset_counter);
2714
2715                 /*
2716                  * Wakeup waiting processes so that the reset function
2717                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2718                  * various locks. By bumping the reset counter first, the woken
2719                  * processes will see a reset in progress and back off,
2720                  * releasing their locks and then wait for the reset completion.
2721                  * We must do this for _all_ gpu waiters that might hold locks
2722                  * that the reset work needs to acquire.
2723                  *
2724                  * Note: The wake_up serves as the required memory barrier to
2725                  * ensure that the waiters see the updated value of the reset
2726                  * counter atomic_t.
2727                  */
2728                 i915_error_wake_up(dev_priv, false);
2729         }
2730
2731         i915_reset_and_wakeup(dev_priv);
2732 }
2733
2734 /* Called from drm generic code, passed 'crtc' which
2735  * we use as a pipe index
2736  */
2737 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2738 {
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         unsigned long irqflags;
2741
2742         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2743         if (INTEL_INFO(dev)->gen >= 4)
2744                 i915_enable_pipestat(dev_priv, pipe,
2745                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2746         else
2747                 i915_enable_pipestat(dev_priv, pipe,
2748                                      PIPE_VBLANK_INTERRUPT_STATUS);
2749         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2750
2751         return 0;
2752 }
2753
2754 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2755 {
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757         unsigned long irqflags;
2758         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2759                                                      DE_PIPE_VBLANK(pipe);
2760
2761         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2762         ilk_enable_display_irq(dev_priv, bit);
2763         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2764
2765         return 0;
2766 }
2767
2768 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         unsigned long irqflags;
2772
2773         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2774         i915_enable_pipestat(dev_priv, pipe,
2775                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2776         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2777
2778         return 0;
2779 }
2780
2781 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         unsigned long irqflags;
2785
2786         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2787         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2788         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2789
2790         return 0;
2791 }
2792
2793 /* Called from drm generic code, passed 'crtc' which
2794  * we use as a pipe index
2795  */
2796 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2797 {
2798         struct drm_i915_private *dev_priv = dev->dev_private;
2799         unsigned long irqflags;
2800
2801         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2802         i915_disable_pipestat(dev_priv, pipe,
2803                               PIPE_VBLANK_INTERRUPT_STATUS |
2804                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2805         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2806 }
2807
2808 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2809 {
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         unsigned long irqflags;
2812         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2813                                                      DE_PIPE_VBLANK(pipe);
2814
2815         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2816         ilk_disable_display_irq(dev_priv, bit);
2817         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2818 }
2819
2820 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2821 {
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         unsigned long irqflags;
2824
2825         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2826         i915_disable_pipestat(dev_priv, pipe,
2827                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2828         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2829 }
2830
2831 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2832 {
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         unsigned long irqflags;
2835
2836         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2837         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2838         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2839 }
2840
2841 static bool
2842 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2843 {
2844         return i915_seqno_passed(seqno,
2845                                  READ_ONCE(engine->last_submitted_seqno));
2846 }
2847
2848 static bool
2849 ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
2850 {
2851         if (INTEL_GEN(dev_priv) >= 8) {
2852                 return (ipehr >> 23) == 0x1c;
2853         } else {
2854                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2855                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2856                                  MI_SEMAPHORE_REGISTER);
2857         }
2858 }
2859
2860 static struct intel_engine_cs *
2861 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2862                                  u64 offset)
2863 {
2864         struct drm_i915_private *dev_priv = engine->i915;
2865         struct intel_engine_cs *signaller;
2866
2867         if (INTEL_GEN(dev_priv) >= 8) {
2868                 for_each_engine(signaller, dev_priv) {
2869                         if (engine == signaller)
2870                                 continue;
2871
2872                         if (offset == signaller->semaphore.signal_ggtt[engine->id])
2873                                 return signaller;
2874                 }
2875         } else {
2876                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2877
2878                 for_each_engine(signaller, dev_priv) {
2879                         if(engine == signaller)
2880                                 continue;
2881
2882                         if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2883                                 return signaller;
2884                 }
2885         }
2886
2887         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2888                   engine->id, ipehr, offset);
2889
2890         return NULL;
2891 }
2892
2893 static struct intel_engine_cs *
2894 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2895 {
2896         struct drm_i915_private *dev_priv = engine->i915;
2897         u32 cmd, ipehr, head;
2898         u64 offset = 0;
2899         int i, backwards;
2900
2901         /*
2902          * This function does not support execlist mode - any attempt to
2903          * proceed further into this function will result in a kernel panic
2904          * when dereferencing ring->buffer, which is not set up in execlist
2905          * mode.
2906          *
2907          * The correct way of doing it would be to derive the currently
2908          * executing ring buffer from the current context, which is derived
2909          * from the currently running request. Unfortunately, to get the
2910          * current request we would have to grab the struct_mutex before doing
2911          * anything else, which would be ill-advised since some other thread
2912          * might have grabbed it already and managed to hang itself, causing
2913          * the hang checker to deadlock.
2914          *
2915          * Therefore, this function does not support execlist mode in its
2916          * current form. Just return NULL and move on.
2917          */
2918         if (engine->buffer == NULL)
2919                 return NULL;
2920
2921         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2922         if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
2923                 return NULL;
2924
2925         /*
2926          * HEAD is likely pointing to the dword after the actual command,
2927          * so scan backwards until we find the MBOX. But limit it to just 3
2928          * or 4 dwords depending on the semaphore wait command size.
2929          * Note that we don't care about ACTHD here since that might
2930          * point at at batch, and semaphores are always emitted into the
2931          * ringbuffer itself.
2932          */
2933         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2934         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2935
2936         for (i = backwards; i; --i) {
2937                 /*
2938                  * Be paranoid and presume the hw has gone off into the wild -
2939                  * our ring is smaller than what the hardware (and hence
2940                  * HEAD_ADDR) allows. Also handles wrap-around.
2941                  */
2942                 head &= engine->buffer->size - 1;
2943
2944                 /* This here seems to blow up */
2945                 cmd = ioread32(engine->buffer->virtual_start + head);
2946                 if (cmd == ipehr)
2947                         break;
2948
2949                 head -= 4;
2950         }
2951
2952         if (!i)
2953                 return NULL;
2954
2955         *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2956         if (INTEL_GEN(dev_priv) >= 8) {
2957                 offset = ioread32(engine->buffer->virtual_start + head + 12);
2958                 offset <<= 32;
2959                 offset = ioread32(engine->buffer->virtual_start + head + 8);
2960         }
2961         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2962 }
2963
2964 static int semaphore_passed(struct intel_engine_cs *engine)
2965 {
2966         struct drm_i915_private *dev_priv = engine->i915;
2967         struct intel_engine_cs *signaller;
2968         u32 seqno;
2969
2970         engine->hangcheck.deadlock++;
2971
2972         signaller = semaphore_waits_for(engine, &seqno);
2973         if (signaller == NULL)
2974                 return -1;
2975
2976         /* Prevent pathological recursion due to driver bugs */
2977         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2978                 return -1;
2979
2980         if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
2981                 return 1;
2982
2983         /* cursory check for an unkickable deadlock */
2984         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2985             semaphore_passed(signaller) < 0)
2986                 return -1;
2987
2988         return 0;
2989 }
2990
2991 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2992 {
2993         struct intel_engine_cs *engine;
2994
2995         for_each_engine(engine, dev_priv)
2996                 engine->hangcheck.deadlock = 0;
2997 }
2998
2999 static bool subunits_stuck(struct intel_engine_cs *engine)
3000 {
3001         u32 instdone[I915_NUM_INSTDONE_REG];
3002         bool stuck;
3003         int i;
3004
3005         if (engine->id != RCS)
3006                 return true;
3007
3008         i915_get_extra_instdone(engine->i915, instdone);
3009
3010         /* There might be unstable subunit states even when
3011          * actual head is not moving. Filter out the unstable ones by
3012          * accumulating the undone -> done transitions and only
3013          * consider those as progress.
3014          */
3015         stuck = true;
3016         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
3017                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
3018
3019                 if (tmp != engine->hangcheck.instdone[i])
3020                         stuck = false;
3021
3022                 engine->hangcheck.instdone[i] |= tmp;
3023         }
3024
3025         return stuck;
3026 }
3027
3028 static enum intel_ring_hangcheck_action
3029 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3030 {
3031         if (acthd != engine->hangcheck.acthd) {
3032
3033                 /* Clear subunit states on head movement */
3034                 memset(engine->hangcheck.instdone, 0,
3035                        sizeof(engine->hangcheck.instdone));
3036
3037                 return HANGCHECK_ACTIVE;
3038         }
3039
3040         if (!subunits_stuck(engine))
3041                 return HANGCHECK_ACTIVE;
3042
3043         return HANGCHECK_HUNG;
3044 }
3045
3046 static enum intel_ring_hangcheck_action
3047 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3048 {
3049         struct drm_i915_private *dev_priv = engine->i915;
3050         enum intel_ring_hangcheck_action ha;
3051         u32 tmp;
3052
3053         ha = head_stuck(engine, acthd);
3054         if (ha != HANGCHECK_HUNG)
3055                 return ha;
3056
3057         if (IS_GEN2(dev_priv))
3058                 return HANGCHECK_HUNG;
3059
3060         /* Is the chip hanging on a WAIT_FOR_EVENT?
3061          * If so we can simply poke the RB_WAIT bit
3062          * and break the hang. This should work on
3063          * all but the second generation chipsets.
3064          */
3065         tmp = I915_READ_CTL(engine);
3066         if (tmp & RING_WAIT) {
3067                 i915_handle_error(dev_priv, 0,
3068                                   "Kicking stuck wait on %s",
3069                                   engine->name);
3070                 I915_WRITE_CTL(engine, tmp);
3071                 return HANGCHECK_KICK;
3072         }
3073
3074         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3075                 switch (semaphore_passed(engine)) {
3076                 default:
3077                         return HANGCHECK_HUNG;
3078                 case 1:
3079                         i915_handle_error(dev_priv, 0,
3080                                           "Kicking stuck semaphore on %s",
3081                                           engine->name);
3082                         I915_WRITE_CTL(engine, tmp);
3083                         return HANGCHECK_KICK;
3084                 case 0:
3085                         return HANGCHECK_WAIT;
3086                 }
3087         }
3088
3089         return HANGCHECK_HUNG;
3090 }
3091
3092 static unsigned kick_waiters(struct intel_engine_cs *engine)
3093 {
3094         struct drm_i915_private *i915 = engine->i915;
3095         unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
3096
3097         if (engine->hangcheck.user_interrupts == user_interrupts &&
3098             !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3099                 if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine)))
3100                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3101                                   engine->name);
3102                 else
3103                         DRM_INFO("Fake missed irq on %s\n",
3104                                  engine->name);
3105                 wake_up_all(&engine->irq_queue);
3106         }
3107
3108         return user_interrupts;
3109 }
3110 /*
3111  * This is called when the chip hasn't reported back with completed
3112  * batchbuffers in a long time. We keep track per ring seqno progress and
3113  * if there are no progress, hangcheck score for that ring is increased.
3114  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3115  * we kick the ring. If we see no progress on three subsequent calls
3116  * we assume chip is wedged and try to fix it by resetting the chip.
3117  */
3118 static void i915_hangcheck_elapsed(struct work_struct *work)
3119 {
3120         struct drm_i915_private *dev_priv =
3121                 container_of(work, typeof(*dev_priv),
3122                              gpu_error.hangcheck_work.work);
3123         struct intel_engine_cs *engine;
3124         enum intel_engine_id id;
3125         int busy_count = 0, rings_hung = 0;
3126         bool stuck[I915_NUM_ENGINES] = { 0 };
3127 #define BUSY 1
3128 #define KICK 5
3129 #define HUNG 20
3130 #define ACTIVE_DECAY 15
3131
3132         if (!i915.enable_hangcheck)
3133                 return;
3134
3135         /*
3136          * The hangcheck work is synced during runtime suspend, we don't
3137          * require a wakeref. TODO: instead of disabling the asserts make
3138          * sure that we hold a reference when this work is running.
3139          */
3140         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3141
3142         /* As enabling the GPU requires fairly extensive mmio access,
3143          * periodically arm the mmio checker to see if we are triggering
3144          * any invalid access.
3145          */
3146         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3147
3148         for_each_engine_id(engine, dev_priv, id) {
3149                 u64 acthd;
3150                 u32 seqno;
3151                 unsigned user_interrupts;
3152                 bool busy = true;
3153
3154                 semaphore_clear_deadlocks(dev_priv);
3155
3156                 /* We don't strictly need an irq-barrier here, as we are not
3157                  * serving an interrupt request, be paranoid in case the
3158                  * barrier has side-effects (such as preventing a broken
3159                  * cacheline snoop) and so be sure that we can see the seqno
3160                  * advance. If the seqno should stick, due to a stale
3161                  * cacheline, we would erroneously declare the GPU hung.
3162                  */
3163                 if (engine->irq_seqno_barrier)
3164                         engine->irq_seqno_barrier(engine);
3165
3166                 acthd = intel_ring_get_active_head(engine);
3167                 seqno = engine->get_seqno(engine);
3168
3169                 /* Reset stuck interrupts between batch advances */
3170                 user_interrupts = 0;
3171
3172                 if (engine->hangcheck.seqno == seqno) {
3173                         if (ring_idle(engine, seqno)) {
3174                                 engine->hangcheck.action = HANGCHECK_IDLE;
3175                                 if (waitqueue_active(&engine->irq_queue)) {
3176                                         /* Safeguard against driver failure */
3177                                         user_interrupts = kick_waiters(engine);
3178                                         engine->hangcheck.score += BUSY;
3179                                 } else
3180                                         busy = false;
3181                         } else {
3182                                 /* We always increment the hangcheck score
3183                                  * if the ring is busy and still processing
3184                                  * the same request, so that no single request
3185                                  * can run indefinitely (such as a chain of
3186                                  * batches). The only time we do not increment
3187                                  * the hangcheck score on this ring, if this
3188                                  * ring is in a legitimate wait for another
3189                                  * ring. In that case the waiting ring is a
3190                                  * victim and we want to be sure we catch the
3191                                  * right culprit. Then every time we do kick
3192                                  * the ring, add a small increment to the
3193                                  * score so that we can catch a batch that is
3194                                  * being repeatedly kicked and so responsible
3195                                  * for stalling the machine.
3196                                  */
3197                                 engine->hangcheck.action = ring_stuck(engine,
3198                                                                       acthd);
3199
3200                                 switch (engine->hangcheck.action) {
3201                                 case HANGCHECK_IDLE:
3202                                 case HANGCHECK_WAIT:
3203                                         break;
3204                                 case HANGCHECK_ACTIVE:
3205                                         engine->hangcheck.score += BUSY;
3206                                         break;
3207                                 case HANGCHECK_KICK:
3208                                         engine->hangcheck.score += KICK;
3209                                         break;
3210                                 case HANGCHECK_HUNG:
3211                                         engine->hangcheck.score += HUNG;
3212                                         stuck[id] = true;
3213                                         break;
3214                                 }
3215                         }
3216                 } else {
3217                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3218
3219                         /* Gradually reduce the count so that we catch DoS
3220                          * attempts across multiple batches.
3221                          */
3222                         if (engine->hangcheck.score > 0)
3223                                 engine->hangcheck.score -= ACTIVE_DECAY;
3224                         if (engine->hangcheck.score < 0)
3225                                 engine->hangcheck.score = 0;
3226
3227                         /* Clear head and subunit states on seqno movement */
3228                         acthd = 0;
3229
3230                         memset(engine->hangcheck.instdone, 0,
3231                                sizeof(engine->hangcheck.instdone));
3232                 }
3233
3234                 engine->hangcheck.seqno = seqno;
3235                 engine->hangcheck.acthd = acthd;
3236                 engine->hangcheck.user_interrupts = user_interrupts;
3237                 busy_count += busy;
3238         }
3239
3240         for_each_engine_id(engine, dev_priv, id) {
3241                 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3242                         DRM_INFO("%s on %s\n",
3243                                  stuck[id] ? "stuck" : "no progress",
3244                                  engine->name);
3245                         rings_hung |= intel_engine_flag(engine);
3246                 }
3247         }
3248
3249         if (rings_hung) {
3250                 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
3251                 goto out;
3252         }
3253
3254         if (busy_count)
3255                 /* Reset timer case chip hangs without another request
3256                  * being added */
3257                 i915_queue_hangcheck(dev_priv);
3258
3259 out:
3260         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3261 }
3262
3263 void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3264 {
3265         struct i915_gpu_error *e = &dev_priv->gpu_error;
3266
3267         if (!i915.enable_hangcheck)
3268                 return;
3269
3270         /* Don't continually defer the hangcheck so that it is always run at
3271          * least once after work has been scheduled on any ring. Otherwise,
3272          * we will ignore a hung ring if a second ring is kept busy.
3273          */
3274
3275         queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3276                            round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3277 }
3278
3279 static void ibx_irq_reset(struct drm_device *dev)
3280 {
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282
3283         if (HAS_PCH_NOP(dev))
3284                 return;
3285
3286         GEN5_IRQ_RESET(SDE);
3287
3288         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3289                 I915_WRITE(SERR_INT, 0xffffffff);
3290 }
3291
3292 /*
3293  * SDEIER is also touched by the interrupt handler to work around missed PCH
3294  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3295  * instead we unconditionally enable all PCH interrupt sources here, but then
3296  * only unmask them as needed with SDEIMR.
3297  *
3298  * This function needs to be called before interrupts are enabled.
3299  */
3300 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3301 {
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303
3304         if (HAS_PCH_NOP(dev))
3305                 return;
3306
3307         WARN_ON(I915_READ(SDEIER) != 0);
3308         I915_WRITE(SDEIER, 0xffffffff);
3309         POSTING_READ(SDEIER);
3310 }
3311
3312 static void gen5_gt_irq_reset(struct drm_device *dev)
3313 {
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315
3316         GEN5_IRQ_RESET(GT);
3317         if (INTEL_INFO(dev)->gen >= 6)
3318                 GEN5_IRQ_RESET(GEN6_PM);
3319 }
3320
3321 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3322 {
3323         enum pipe pipe;
3324
3325         if (IS_CHERRYVIEW(dev_priv))
3326                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3327         else
3328                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3329
3330         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3331         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3332
3333         for_each_pipe(dev_priv, pipe) {
3334                 I915_WRITE(PIPESTAT(pipe),
3335                            PIPE_FIFO_UNDERRUN_STATUS |
3336                            PIPESTAT_INT_STATUS_MASK);
3337                 dev_priv->pipestat_irq_mask[pipe] = 0;
3338         }
3339
3340         GEN5_IRQ_RESET(VLV_);
3341         dev_priv->irq_mask = ~0;
3342 }
3343
3344 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3345 {
3346         u32 pipestat_mask;
3347         u32 enable_mask;
3348         enum pipe pipe;
3349
3350         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3351                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3352
3353         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3354         for_each_pipe(dev_priv, pipe)
3355                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3356
3357         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3358                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3359                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3360         if (IS_CHERRYVIEW(dev_priv))
3361                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3362
3363         WARN_ON(dev_priv->irq_mask != ~0);
3364
3365         dev_priv->irq_mask = ~enable_mask;
3366
3367         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3368 }
3369
3370 /* drm_dma.h hooks
3371 */
3372 static void ironlake_irq_reset(struct drm_device *dev)
3373 {
3374         struct drm_i915_private *dev_priv = dev->dev_private;
3375
3376         I915_WRITE(HWSTAM, 0xffffffff);
3377
3378         GEN5_IRQ_RESET(DE);
3379         if (IS_GEN7(dev))
3380                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3381
3382         gen5_gt_irq_reset(dev);
3383
3384         ibx_irq_reset(dev);
3385 }
3386
3387 static void valleyview_irq_preinstall(struct drm_device *dev)
3388 {
3389         struct drm_i915_private *dev_priv = dev->dev_private;
3390
3391         I915_WRITE(VLV_MASTER_IER, 0);
3392         POSTING_READ(VLV_MASTER_IER);
3393
3394         gen5_gt_irq_reset(dev);
3395
3396         spin_lock_irq(&dev_priv->irq_lock);
3397         if (dev_priv->display_irqs_enabled)
3398                 vlv_display_irq_reset(dev_priv);
3399         spin_unlock_irq(&dev_priv->irq_lock);
3400 }
3401
3402 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3403 {
3404         GEN8_IRQ_RESET_NDX(GT, 0);
3405         GEN8_IRQ_RESET_NDX(GT, 1);
3406         GEN8_IRQ_RESET_NDX(GT, 2);
3407         GEN8_IRQ_RESET_NDX(GT, 3);
3408 }
3409
3410 static void gen8_irq_reset(struct drm_device *dev)
3411 {
3412         struct drm_i915_private *dev_priv = dev->dev_private;
3413         int pipe;
3414
3415         I915_WRITE(GEN8_MASTER_IRQ, 0);
3416         POSTING_READ(GEN8_MASTER_IRQ);
3417
3418         gen8_gt_irq_reset(dev_priv);
3419
3420         for_each_pipe(dev_priv, pipe)
3421                 if (intel_display_power_is_enabled(dev_priv,
3422                                                    POWER_DOMAIN_PIPE(pipe)))
3423                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3424
3425         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3426         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3427         GEN5_IRQ_RESET(GEN8_PCU_);
3428
3429         if (HAS_PCH_SPLIT(dev))
3430                 ibx_irq_reset(dev);
3431 }
3432
3433 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3434                                      unsigned int pipe_mask)
3435 {
3436         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3437         enum pipe pipe;
3438
3439         spin_lock_irq(&dev_priv->irq_lock);
3440         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3441                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3442                                   dev_priv->de_irq_mask[pipe],
3443                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3444         spin_unlock_irq(&dev_priv->irq_lock);
3445 }
3446
3447 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3448                                      unsigned int pipe_mask)
3449 {
3450         enum pipe pipe;
3451
3452         spin_lock_irq(&dev_priv->irq_lock);
3453         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3454                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3455         spin_unlock_irq(&dev_priv->irq_lock);
3456
3457         /* make sure we're done processing display irqs */
3458         synchronize_irq(dev_priv->dev->irq);
3459 }
3460
3461 static void cherryview_irq_preinstall(struct drm_device *dev)
3462 {
3463         struct drm_i915_private *dev_priv = dev->dev_private;
3464
3465         I915_WRITE(GEN8_MASTER_IRQ, 0);
3466         POSTING_READ(GEN8_MASTER_IRQ);
3467
3468         gen8_gt_irq_reset(dev_priv);
3469
3470         GEN5_IRQ_RESET(GEN8_PCU_);
3471
3472         spin_lock_irq(&dev_priv->irq_lock);
3473         if (dev_priv->display_irqs_enabled)
3474                 vlv_display_irq_reset(dev_priv);
3475         spin_unlock_irq(&dev_priv->irq_lock);
3476 }
3477
3478 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3479                                   const u32 hpd[HPD_NUM_PINS])
3480 {
3481         struct intel_encoder *encoder;
3482         u32 enabled_irqs = 0;
3483
3484         for_each_intel_encoder(dev_priv->dev, encoder)
3485                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3486                         enabled_irqs |= hpd[encoder->hpd_pin];
3487
3488         return enabled_irqs;
3489 }
3490
3491 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3492 {
3493         u32 hotplug_irqs, hotplug, enabled_irqs;
3494
3495         if (HAS_PCH_IBX(dev_priv)) {
3496                 hotplug_irqs = SDE_HOTPLUG_MASK;
3497                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3498         } else {
3499                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3500                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3501         }
3502
3503         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3504
3505         /*
3506          * Enable digital hotplug on the PCH, and configure the DP short pulse
3507          * duration to 2ms (which is the minimum in the Display Port spec).
3508          * The pulse duration bits are reserved on LPT+.
3509          */
3510         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3511         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3512         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3513         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3514         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3515         /*
3516          * When CPU and PCH are on the same package, port A
3517          * HPD must be enabled in both north and south.
3518          */
3519         if (HAS_PCH_LPT_LP(dev_priv))
3520                 hotplug |= PORTA_HOTPLUG_ENABLE;
3521         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3522 }
3523
3524 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3525 {
3526         u32 hotplug_irqs, hotplug, enabled_irqs;
3527
3528         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3529         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3530
3531         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3532
3533         /* Enable digital hotplug on the PCH */
3534         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3535         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3536                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3537         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3538
3539         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3540         hotplug |= PORTE_HOTPLUG_ENABLE;
3541         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3542 }
3543
3544 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3545 {
3546         u32 hotplug_irqs, hotplug, enabled_irqs;
3547
3548         if (INTEL_GEN(dev_priv) >= 8) {
3549                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3550                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3551
3552                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3553         } else if (INTEL_GEN(dev_priv) >= 7) {
3554                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3555                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3556
3557                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3558         } else {
3559                 hotplug_irqs = DE_DP_A_HOTPLUG;
3560                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3561
3562                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3563         }
3564
3565         /*
3566          * Enable digital hotplug on the CPU, and configure the DP short pulse
3567          * duration to 2ms (which is the minimum in the Display Port spec)
3568          * The pulse duration bits are reserved on HSW+.
3569          */
3570         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3571         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3572         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3573         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3574
3575         ibx_hpd_irq_setup(dev_priv);
3576 }
3577
3578 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3579 {
3580         u32 hotplug_irqs, hotplug, enabled_irqs;
3581
3582         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3583         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3584
3585         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3586
3587         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3588         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3589                 PORTA_HOTPLUG_ENABLE;
3590
3591         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3592                       hotplug, enabled_irqs);
3593         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3594
3595         /*
3596          * For BXT invert bit has to be set based on AOB design
3597          * for HPD detection logic, update it based on VBT fields.
3598          */
3599
3600         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3601             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3602                 hotplug |= BXT_DDIA_HPD_INVERT;
3603         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3604             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3605                 hotplug |= BXT_DDIB_HPD_INVERT;
3606         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3607             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3608                 hotplug |= BXT_DDIC_HPD_INVERT;
3609
3610         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3611 }
3612
3613 static void ibx_irq_postinstall(struct drm_device *dev)
3614 {
3615         struct drm_i915_private *dev_priv = dev->dev_private;
3616         u32 mask;
3617
3618         if (HAS_PCH_NOP(dev))
3619                 return;
3620
3621         if (HAS_PCH_IBX(dev))
3622                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3623         else
3624                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3625
3626         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3627         I915_WRITE(SDEIMR, ~mask);
3628 }
3629
3630 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3631 {
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         u32 pm_irqs, gt_irqs;
3634
3635         pm_irqs = gt_irqs = 0;
3636
3637         dev_priv->gt_irq_mask = ~0;
3638         if (HAS_L3_DPF(dev)) {
3639                 /* L3 parity interrupt is always unmasked. */
3640                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3641                 gt_irqs |= GT_PARITY_ERROR(dev);
3642         }
3643
3644         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3645         if (IS_GEN5(dev)) {
3646                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3647                            ILK_BSD_USER_INTERRUPT;
3648         } else {
3649                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3650         }
3651
3652         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3653
3654         if (INTEL_INFO(dev)->gen >= 6) {
3655                 /*
3656                  * RPS interrupts will get enabled/disabled on demand when RPS
3657                  * itself is enabled/disabled.
3658                  */
3659                 if (HAS_VEBOX(dev))
3660                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3661
3662                 dev_priv->pm_irq_mask = 0xffffffff;
3663                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3664         }
3665 }
3666
3667 static int ironlake_irq_postinstall(struct drm_device *dev)
3668 {
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670         u32 display_mask, extra_mask;
3671
3672         if (INTEL_INFO(dev)->gen >= 7) {
3673                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3674                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3675                                 DE_PLANEB_FLIP_DONE_IVB |
3676                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3677                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3678                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3679                               DE_DP_A_HOTPLUG_IVB);
3680         } else {
3681                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3682                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3683                                 DE_AUX_CHANNEL_A |
3684                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3685                                 DE_POISON);
3686                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3687                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3688                               DE_DP_A_HOTPLUG);
3689         }
3690
3691         dev_priv->irq_mask = ~display_mask;
3692
3693         I915_WRITE(HWSTAM, 0xeffe);
3694
3695         ibx_irq_pre_postinstall(dev);
3696
3697         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3698
3699         gen5_gt_irq_postinstall(dev);
3700
3701         ibx_irq_postinstall(dev);
3702
3703         if (IS_IRONLAKE_M(dev)) {
3704                 /* Enable PCU event interrupts
3705                  *
3706                  * spinlocking not required here for correctness since interrupt
3707                  * setup is guaranteed to run in single-threaded context. But we
3708                  * need it to make the assert_spin_locked happy. */
3709                 spin_lock_irq(&dev_priv->irq_lock);
3710                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3711                 spin_unlock_irq(&dev_priv->irq_lock);
3712         }
3713
3714         return 0;
3715 }
3716
3717 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3718 {
3719         assert_spin_locked(&dev_priv->irq_lock);
3720
3721         if (dev_priv->display_irqs_enabled)
3722                 return;
3723
3724         dev_priv->display_irqs_enabled = true;
3725
3726         if (intel_irqs_enabled(dev_priv)) {
3727                 vlv_display_irq_reset(dev_priv);
3728                 vlv_display_irq_postinstall(dev_priv);
3729         }
3730 }
3731
3732 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3733 {
3734         assert_spin_locked(&dev_priv->irq_lock);
3735
3736         if (!dev_priv->display_irqs_enabled)
3737                 return;
3738
3739         dev_priv->display_irqs_enabled = false;
3740
3741         if (intel_irqs_enabled(dev_priv))
3742                 vlv_display_irq_reset(dev_priv);
3743 }
3744
3745
3746 static int valleyview_irq_postinstall(struct drm_device *dev)
3747 {
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749
3750         gen5_gt_irq_postinstall(dev);
3751
3752         spin_lock_irq(&dev_priv->irq_lock);
3753         if (dev_priv->display_irqs_enabled)
3754                 vlv_display_irq_postinstall(dev_priv);
3755         spin_unlock_irq(&dev_priv->irq_lock);
3756
3757         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3758         POSTING_READ(VLV_MASTER_IER);
3759
3760         return 0;
3761 }
3762
3763 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3764 {
3765         /* These are interrupts we'll toggle with the ring mask register */
3766         uint32_t gt_interrupts[] = {
3767                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3768                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3769                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3770                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3771                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3772                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3773                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3774                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3775                 0,
3776                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3777                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3778                 };
3779
3780         if (HAS_L3_DPF(dev_priv))
3781                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3782
3783         dev_priv->pm_irq_mask = 0xffffffff;
3784         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3785         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3786         /*
3787          * RPS interrupts will get enabled/disabled on demand when RPS itself
3788          * is enabled/disabled.
3789          */
3790         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3791         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3792 }
3793
3794 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3795 {
3796         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3797         uint32_t de_pipe_enables;
3798         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3799         u32 de_port_enables;
3800         enum pipe pipe;
3801
3802         if (INTEL_INFO(dev_priv)->gen >= 9) {
3803                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3804                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3805                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3806                                   GEN9_AUX_CHANNEL_D;
3807                 if (IS_BROXTON(dev_priv))
3808                         de_port_masked |= BXT_DE_PORT_GMBUS;
3809         } else {
3810                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3811                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3812         }
3813
3814         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3815                                            GEN8_PIPE_FIFO_UNDERRUN;
3816
3817         de_port_enables = de_port_masked;
3818         if (IS_BROXTON(dev_priv))
3819                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3820         else if (IS_BROADWELL(dev_priv))
3821                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3822
3823         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3824         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3825         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3826
3827         for_each_pipe(dev_priv, pipe)
3828                 if (intel_display_power_is_enabled(dev_priv,
3829                                 POWER_DOMAIN_PIPE(pipe)))
3830                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3831                                           dev_priv->de_irq_mask[pipe],
3832                                           de_pipe_enables);
3833
3834         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3835 }
3836
3837 static int gen8_irq_postinstall(struct drm_device *dev)
3838 {
3839         struct drm_i915_private *dev_priv = dev->dev_private;
3840
3841         if (HAS_PCH_SPLIT(dev))
3842                 ibx_irq_pre_postinstall(dev);
3843
3844         gen8_gt_irq_postinstall(dev_priv);
3845         gen8_de_irq_postinstall(dev_priv);
3846
3847         if (HAS_PCH_SPLIT(dev))
3848                 ibx_irq_postinstall(dev);
3849
3850         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3851         POSTING_READ(GEN8_MASTER_IRQ);
3852
3853         return 0;
3854 }
3855
3856 static int cherryview_irq_postinstall(struct drm_device *dev)
3857 {
3858         struct drm_i915_private *dev_priv = dev->dev_private;
3859
3860         gen8_gt_irq_postinstall(dev_priv);
3861
3862         spin_lock_irq(&dev_priv->irq_lock);
3863         if (dev_priv->display_irqs_enabled)
3864                 vlv_display_irq_postinstall(dev_priv);
3865         spin_unlock_irq(&dev_priv->irq_lock);
3866
3867         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3868         POSTING_READ(GEN8_MASTER_IRQ);
3869
3870         return 0;
3871 }
3872
3873 static void gen8_irq_uninstall(struct drm_device *dev)
3874 {
3875         struct drm_i915_private *dev_priv = dev->dev_private;
3876
3877         if (!dev_priv)
3878                 return;
3879
3880         gen8_irq_reset(dev);
3881 }
3882
3883 static void valleyview_irq_uninstall(struct drm_device *dev)
3884 {
3885         struct drm_i915_private *dev_priv = dev->dev_private;
3886
3887         if (!dev_priv)
3888                 return;
3889
3890         I915_WRITE(VLV_MASTER_IER, 0);
3891         POSTING_READ(VLV_MASTER_IER);
3892
3893         gen5_gt_irq_reset(dev);
3894
3895         I915_WRITE(HWSTAM, 0xffffffff);
3896
3897         spin_lock_irq(&dev_priv->irq_lock);
3898         if (dev_priv->display_irqs_enabled)
3899                 vlv_display_irq_reset(dev_priv);
3900         spin_unlock_irq(&dev_priv->irq_lock);
3901 }
3902
3903 static void cherryview_irq_uninstall(struct drm_device *dev)
3904 {
3905         struct drm_i915_private *dev_priv = dev->dev_private;
3906
3907         if (!dev_priv)
3908                 return;
3909
3910         I915_WRITE(GEN8_MASTER_IRQ, 0);
3911         POSTING_READ(GEN8_MASTER_IRQ);
3912
3913         gen8_gt_irq_reset(dev_priv);
3914
3915         GEN5_IRQ_RESET(GEN8_PCU_);
3916
3917         spin_lock_irq(&dev_priv->irq_lock);
3918         if (dev_priv->display_irqs_enabled)
3919                 vlv_display_irq_reset(dev_priv);
3920         spin_unlock_irq(&dev_priv->irq_lock);
3921 }
3922
3923 static void ironlake_irq_uninstall(struct drm_device *dev)
3924 {
3925         struct drm_i915_private *dev_priv = dev->dev_private;
3926
3927         if (!dev_priv)
3928                 return;
3929
3930         ironlake_irq_reset(dev);
3931 }
3932
3933 static void i8xx_irq_preinstall(struct drm_device * dev)
3934 {
3935         struct drm_i915_private *dev_priv = dev->dev_private;
3936         int pipe;
3937
3938         for_each_pipe(dev_priv, pipe)
3939                 I915_WRITE(PIPESTAT(pipe), 0);
3940         I915_WRITE16(IMR, 0xffff);
3941         I915_WRITE16(IER, 0x0);
3942         POSTING_READ16(IER);
3943 }
3944
3945 static int i8xx_irq_postinstall(struct drm_device *dev)
3946 {
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948
3949         I915_WRITE16(EMR,
3950                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3951
3952         /* Unmask the interrupts that we always want on. */
3953         dev_priv->irq_mask =
3954                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3955                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3956                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3957                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3958         I915_WRITE16(IMR, dev_priv->irq_mask);
3959
3960         I915_WRITE16(IER,
3961                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3962                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3963                      I915_USER_INTERRUPT);
3964         POSTING_READ16(IER);
3965
3966         /* Interrupt setup is already guaranteed to be single-threaded, this is
3967          * just to make the assert_spin_locked check happy. */
3968         spin_lock_irq(&dev_priv->irq_lock);
3969         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3970         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3971         spin_unlock_irq(&dev_priv->irq_lock);
3972
3973         return 0;
3974 }
3975
3976 /*
3977  * Returns true when a page flip has completed.
3978  */
3979 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3980                                int plane, int pipe, u32 iir)
3981 {
3982         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3983
3984         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3985                 return false;
3986
3987         if ((iir & flip_pending) == 0)
3988                 goto check_page_flip;
3989
3990         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3991          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3992          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3993          * the flip is completed (no longer pending). Since this doesn't raise
3994          * an interrupt per se, we watch for the change at vblank.
3995          */
3996         if (I915_READ16(ISR) & flip_pending)
3997                 goto check_page_flip;
3998
3999         intel_finish_page_flip_cs(dev_priv, pipe);
4000         return true;
4001
4002 check_page_flip:
4003         intel_check_page_flip(dev_priv, pipe);
4004         return false;
4005 }
4006
4007 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4008 {
4009         struct drm_device *dev = arg;
4010         struct drm_i915_private *dev_priv = dev->dev_private;
4011         u16 iir, new_iir;
4012         u32 pipe_stats[2];
4013         int pipe;
4014         u16 flip_mask =
4015                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4016                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4017         irqreturn_t ret;
4018
4019         if (!intel_irqs_enabled(dev_priv))
4020                 return IRQ_NONE;
4021
4022         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4023         disable_rpm_wakeref_asserts(dev_priv);
4024
4025         ret = IRQ_NONE;
4026         iir = I915_READ16(IIR);
4027         if (iir == 0)
4028                 goto out;
4029
4030         while (iir & ~flip_mask) {
4031                 /* Can't rely on pipestat interrupt bit in iir as it might
4032                  * have been cleared after the pipestat interrupt was received.
4033                  * It doesn't set the bit in iir again, but it still produces
4034                  * interrupts (for non-MSI).
4035                  */
4036                 spin_lock(&dev_priv->irq_lock);
4037                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4038                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4039
4040                 for_each_pipe(dev_priv, pipe) {
4041                         i915_reg_t reg = PIPESTAT(pipe);
4042                         pipe_stats[pipe] = I915_READ(reg);
4043
4044                         /*
4045                          * Clear the PIPE*STAT regs before the IIR
4046                          */
4047                         if (pipe_stats[pipe] & 0x8000ffff)
4048                                 I915_WRITE(reg, pipe_stats[pipe]);
4049                 }
4050                 spin_unlock(&dev_priv->irq_lock);
4051
4052                 I915_WRITE16(IIR, iir & ~flip_mask);
4053                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4054
4055                 if (iir & I915_USER_INTERRUPT)
4056                         notify_ring(&dev_priv->engine[RCS]);
4057
4058                 for_each_pipe(dev_priv, pipe) {
4059                         int plane = pipe;
4060                         if (HAS_FBC(dev_priv))
4061                                 plane = !plane;
4062
4063                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4064                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4065                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4066
4067                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4068                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4069
4070                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4071                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4072                                                                     pipe);
4073                 }
4074
4075                 iir = new_iir;
4076         }
4077         ret = IRQ_HANDLED;
4078
4079 out:
4080         enable_rpm_wakeref_asserts(dev_priv);
4081
4082         return ret;
4083 }
4084
4085 static void i8xx_irq_uninstall(struct drm_device * dev)
4086 {
4087         struct drm_i915_private *dev_priv = dev->dev_private;
4088         int pipe;
4089
4090         for_each_pipe(dev_priv, pipe) {
4091                 /* Clear enable bits; then clear status bits */
4092                 I915_WRITE(PIPESTAT(pipe), 0);
4093                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4094         }
4095         I915_WRITE16(IMR, 0xffff);
4096         I915_WRITE16(IER, 0x0);
4097         I915_WRITE16(IIR, I915_READ16(IIR));
4098 }
4099
4100 static void i915_irq_preinstall(struct drm_device * dev)
4101 {
4102         struct drm_i915_private *dev_priv = dev->dev_private;
4103         int pipe;
4104
4105         if (I915_HAS_HOTPLUG(dev)) {
4106                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4107                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4108         }
4109
4110         I915_WRITE16(HWSTAM, 0xeffe);
4111         for_each_pipe(dev_priv, pipe)
4112                 I915_WRITE(PIPESTAT(pipe), 0);
4113         I915_WRITE(IMR, 0xffffffff);
4114         I915_WRITE(IER, 0x0);
4115         POSTING_READ(IER);
4116 }
4117
4118 static int i915_irq_postinstall(struct drm_device *dev)
4119 {
4120         struct drm_i915_private *dev_priv = dev->dev_private;
4121         u32 enable_mask;
4122
4123         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4124
4125         /* Unmask the interrupts that we always want on. */
4126         dev_priv->irq_mask =
4127                 ~(I915_ASLE_INTERRUPT |
4128                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4129                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4130                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4131                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4132
4133         enable_mask =
4134                 I915_ASLE_INTERRUPT |
4135                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4136                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4137                 I915_USER_INTERRUPT;
4138
4139         if (I915_HAS_HOTPLUG(dev)) {
4140                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4141                 POSTING_READ(PORT_HOTPLUG_EN);
4142
4143                 /* Enable in IER... */
4144                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4145                 /* and unmask in IMR */
4146                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4147         }
4148
4149         I915_WRITE(IMR, dev_priv->irq_mask);
4150         I915_WRITE(IER, enable_mask);
4151         POSTING_READ(IER);
4152
4153         i915_enable_asle_pipestat(dev_priv);
4154
4155         /* Interrupt setup is already guaranteed to be single-threaded, this is
4156          * just to make the assert_spin_locked check happy. */
4157         spin_lock_irq(&dev_priv->irq_lock);
4158         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4159         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4160         spin_unlock_irq(&dev_priv->irq_lock);
4161
4162         return 0;
4163 }
4164
4165 /*
4166  * Returns true when a page flip has completed.
4167  */
4168 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4169                                int plane, int pipe, u32 iir)
4170 {
4171         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4172
4173         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4174                 return false;
4175
4176         if ((iir & flip_pending) == 0)
4177                 goto check_page_flip;
4178
4179         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4180          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4181          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4182          * the flip is completed (no longer pending). Since this doesn't raise
4183          * an interrupt per se, we watch for the change at vblank.
4184          */
4185         if (I915_READ(ISR) & flip_pending)
4186                 goto check_page_flip;
4187
4188         intel_finish_page_flip_cs(dev_priv, pipe);
4189         return true;
4190
4191 check_page_flip:
4192         intel_check_page_flip(dev_priv, pipe);
4193         return false;
4194 }
4195
4196 static irqreturn_t i915_irq_handler(int irq, void *arg)
4197 {
4198         struct drm_device *dev = arg;
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4201         u32 flip_mask =
4202                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4203                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4204         int pipe, ret = IRQ_NONE;
4205
4206         if (!intel_irqs_enabled(dev_priv))
4207                 return IRQ_NONE;
4208
4209         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4210         disable_rpm_wakeref_asserts(dev_priv);
4211
4212         iir = I915_READ(IIR);
4213         do {
4214                 bool irq_received = (iir & ~flip_mask) != 0;
4215                 bool blc_event = false;
4216
4217                 /* Can't rely on pipestat interrupt bit in iir as it might
4218                  * have been cleared after the pipestat interrupt was received.
4219                  * It doesn't set the bit in iir again, but it still produces
4220                  * interrupts (for non-MSI).
4221                  */
4222                 spin_lock(&dev_priv->irq_lock);
4223                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4224                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4225
4226                 for_each_pipe(dev_priv, pipe) {
4227                         i915_reg_t reg = PIPESTAT(pipe);
4228                         pipe_stats[pipe] = I915_READ(reg);
4229
4230                         /* Clear the PIPE*STAT regs before the IIR */
4231                         if (pipe_stats[pipe] & 0x8000ffff) {
4232                                 I915_WRITE(reg, pipe_stats[pipe]);
4233                                 irq_received = true;
4234                         }
4235                 }
4236                 spin_unlock(&dev_priv->irq_lock);
4237
4238                 if (!irq_received)
4239                         break;
4240
4241                 /* Consume port.  Then clear IIR or we'll miss events */
4242                 if (I915_HAS_HOTPLUG(dev_priv) &&
4243                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4244                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4245                         if (hotplug_status)
4246                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4247                 }
4248
4249                 I915_WRITE(IIR, iir & ~flip_mask);
4250                 new_iir = I915_READ(IIR); /* Flush posted writes */
4251
4252                 if (iir & I915_USER_INTERRUPT)
4253                         notify_ring(&dev_priv->engine[RCS]);
4254
4255                 for_each_pipe(dev_priv, pipe) {
4256                         int plane = pipe;
4257                         if (HAS_FBC(dev_priv))
4258                                 plane = !plane;
4259
4260                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4261                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4262                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4263
4264                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4265                                 blc_event = true;
4266
4267                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4268                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4269
4270                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4271                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4272                                                                     pipe);
4273                 }
4274
4275                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4276                         intel_opregion_asle_intr(dev_priv);
4277
4278                 /* With MSI, interrupts are only generated when iir
4279                  * transitions from zero to nonzero.  If another bit got
4280                  * set while we were handling the existing iir bits, then
4281                  * we would never get another interrupt.
4282                  *
4283                  * This is fine on non-MSI as well, as if we hit this path
4284                  * we avoid exiting the interrupt handler only to generate
4285                  * another one.
4286                  *
4287                  * Note that for MSI this could cause a stray interrupt report
4288                  * if an interrupt landed in the time between writing IIR and
4289                  * the posting read.  This should be rare enough to never
4290                  * trigger the 99% of 100,000 interrupts test for disabling
4291                  * stray interrupts.
4292                  */
4293                 ret = IRQ_HANDLED;
4294                 iir = new_iir;
4295         } while (iir & ~flip_mask);
4296
4297         enable_rpm_wakeref_asserts(dev_priv);
4298
4299         return ret;
4300 }
4301
4302 static void i915_irq_uninstall(struct drm_device * dev)
4303 {
4304         struct drm_i915_private *dev_priv = dev->dev_private;
4305         int pipe;
4306
4307         if (I915_HAS_HOTPLUG(dev)) {
4308                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4309                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4310         }
4311
4312         I915_WRITE16(HWSTAM, 0xffff);
4313         for_each_pipe(dev_priv, pipe) {
4314                 /* Clear enable bits; then clear status bits */
4315                 I915_WRITE(PIPESTAT(pipe), 0);
4316                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4317         }
4318         I915_WRITE(IMR, 0xffffffff);
4319         I915_WRITE(IER, 0x0);
4320
4321         I915_WRITE(IIR, I915_READ(IIR));
4322 }
4323
4324 static void i965_irq_preinstall(struct drm_device * dev)
4325 {
4326         struct drm_i915_private *dev_priv = dev->dev_private;
4327         int pipe;
4328
4329         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4330         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4331
4332         I915_WRITE(HWSTAM, 0xeffe);
4333         for_each_pipe(dev_priv, pipe)
4334                 I915_WRITE(PIPESTAT(pipe), 0);
4335         I915_WRITE(IMR, 0xffffffff);
4336         I915_WRITE(IER, 0x0);
4337         POSTING_READ(IER);
4338 }
4339
4340 static int i965_irq_postinstall(struct drm_device *dev)
4341 {
4342         struct drm_i915_private *dev_priv = dev->dev_private;
4343         u32 enable_mask;
4344         u32 error_mask;
4345
4346         /* Unmask the interrupts that we always want on. */
4347         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4348                                I915_DISPLAY_PORT_INTERRUPT |
4349                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4350                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4351                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4352                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4353                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4354
4355         enable_mask = ~dev_priv->irq_mask;
4356         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4357                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4358         enable_mask |= I915_USER_INTERRUPT;
4359
4360         if (IS_G4X(dev_priv))
4361                 enable_mask |= I915_BSD_USER_INTERRUPT;
4362
4363         /* Interrupt setup is already guaranteed to be single-threaded, this is
4364          * just to make the assert_spin_locked check happy. */
4365         spin_lock_irq(&dev_priv->irq_lock);
4366         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4367         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4368         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4369         spin_unlock_irq(&dev_priv->irq_lock);
4370
4371         /*
4372          * Enable some error detection, note the instruction error mask
4373          * bit is reserved, so we leave it masked.
4374          */
4375         if (IS_G4X(dev_priv)) {
4376                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4377                                GM45_ERROR_MEM_PRIV |
4378                                GM45_ERROR_CP_PRIV |
4379                                I915_ERROR_MEMORY_REFRESH);
4380         } else {
4381                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4382                                I915_ERROR_MEMORY_REFRESH);
4383         }
4384         I915_WRITE(EMR, error_mask);
4385
4386         I915_WRITE(IMR, dev_priv->irq_mask);
4387         I915_WRITE(IER, enable_mask);
4388         POSTING_READ(IER);
4389
4390         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4391         POSTING_READ(PORT_HOTPLUG_EN);
4392
4393         i915_enable_asle_pipestat(dev_priv);
4394
4395         return 0;
4396 }
4397
4398 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4399 {
4400         u32 hotplug_en;
4401
4402         assert_spin_locked(&dev_priv->irq_lock);
4403
4404         /* Note HDMI and DP share hotplug bits */
4405         /* enable bits are the same for all generations */
4406         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4407         /* Programming the CRT detection parameters tends
4408            to generate a spurious hotplug event about three
4409            seconds later.  So just do it once.
4410         */
4411         if (IS_G4X(dev_priv))
4412                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4413         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4414
4415         /* Ignore TV since it's buggy */
4416         i915_hotplug_interrupt_update_locked(dev_priv,
4417                                              HOTPLUG_INT_EN_MASK |
4418                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4419                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4420                                              hotplug_en);
4421 }
4422
4423 static irqreturn_t i965_irq_handler(int irq, void *arg)
4424 {
4425         struct drm_device *dev = arg;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         u32 iir, new_iir;
4428         u32 pipe_stats[I915_MAX_PIPES];
4429         int ret = IRQ_NONE, pipe;
4430         u32 flip_mask =
4431                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4432                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4433
4434         if (!intel_irqs_enabled(dev_priv))
4435                 return IRQ_NONE;
4436
4437         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4438         disable_rpm_wakeref_asserts(dev_priv);
4439
4440         iir = I915_READ(IIR);
4441
4442         for (;;) {
4443                 bool irq_received = (iir & ~flip_mask) != 0;
4444                 bool blc_event = false;
4445
4446                 /* Can't rely on pipestat interrupt bit in iir as it might
4447                  * have been cleared after the pipestat interrupt was received.
4448                  * It doesn't set the bit in iir again, but it still produces
4449                  * interrupts (for non-MSI).
4450                  */
4451                 spin_lock(&dev_priv->irq_lock);
4452                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4453                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4454
4455                 for_each_pipe(dev_priv, pipe) {
4456                         i915_reg_t reg = PIPESTAT(pipe);
4457                         pipe_stats[pipe] = I915_READ(reg);
4458
4459                         /*
4460                          * Clear the PIPE*STAT regs before the IIR
4461                          */
4462                         if (pipe_stats[pipe] & 0x8000ffff) {
4463                                 I915_WRITE(reg, pipe_stats[pipe]);
4464                                 irq_received = true;
4465                         }
4466                 }
4467                 spin_unlock(&dev_priv->irq_lock);
4468
4469                 if (!irq_received)
4470                         break;
4471
4472                 ret = IRQ_HANDLED;
4473
4474                 /* Consume port.  Then clear IIR or we'll miss events */
4475                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4476                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4477                         if (hotplug_status)
4478                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4479                 }
4480
4481                 I915_WRITE(IIR, iir & ~flip_mask);
4482                 new_iir = I915_READ(IIR); /* Flush posted writes */
4483
4484                 if (iir & I915_USER_INTERRUPT)
4485                         notify_ring(&dev_priv->engine[RCS]);
4486                 if (iir & I915_BSD_USER_INTERRUPT)
4487                         notify_ring(&dev_priv->engine[VCS]);
4488
4489                 for_each_pipe(dev_priv, pipe) {
4490                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4491                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4492                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4493
4494                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4495                                 blc_event = true;
4496
4497                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4498                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4499
4500                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4501                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4502                 }
4503
4504                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4505                         intel_opregion_asle_intr(dev_priv);
4506
4507                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4508                         gmbus_irq_handler(dev_priv);
4509
4510                 /* With MSI, interrupts are only generated when iir
4511                  * transitions from zero to nonzero.  If another bit got
4512                  * set while we were handling the existing iir bits, then
4513                  * we would never get another interrupt.
4514                  *
4515                  * This is fine on non-MSI as well, as if we hit this path
4516                  * we avoid exiting the interrupt handler only to generate
4517                  * another one.
4518                  *
4519                  * Note that for MSI this could cause a stray interrupt report
4520                  * if an interrupt landed in the time between writing IIR and
4521                  * the posting read.  This should be rare enough to never
4522                  * trigger the 99% of 100,000 interrupts test for disabling
4523                  * stray interrupts.
4524                  */
4525                 iir = new_iir;
4526         }
4527
4528         enable_rpm_wakeref_asserts(dev_priv);
4529
4530         return ret;
4531 }
4532
4533 static void i965_irq_uninstall(struct drm_device * dev)
4534 {
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536         int pipe;
4537
4538         if (!dev_priv)
4539                 return;
4540
4541         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4542         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4543
4544         I915_WRITE(HWSTAM, 0xffffffff);
4545         for_each_pipe(dev_priv, pipe)
4546                 I915_WRITE(PIPESTAT(pipe), 0);
4547         I915_WRITE(IMR, 0xffffffff);
4548         I915_WRITE(IER, 0x0);
4549
4550         for_each_pipe(dev_priv, pipe)
4551                 I915_WRITE(PIPESTAT(pipe),
4552                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4553         I915_WRITE(IIR, I915_READ(IIR));
4554 }
4555
4556 /**
4557  * intel_irq_init - initializes irq support
4558  * @dev_priv: i915 device instance
4559  *
4560  * This function initializes all the irq support including work items, timers
4561  * and all the vtables. It does not setup the interrupt itself though.
4562  */
4563 void intel_irq_init(struct drm_i915_private *dev_priv)
4564 {
4565         struct drm_device *dev = dev_priv->dev;
4566
4567         intel_hpd_init_work(dev_priv);
4568
4569         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4570         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4571
4572         /* Let's track the enabled rps events */
4573         if (IS_VALLEYVIEW(dev_priv))
4574                 /* WaGsvRC0ResidencyMethod:vlv */
4575                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4576         else
4577                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4578
4579         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4580                           i915_hangcheck_elapsed);
4581
4582         if (IS_GEN2(dev_priv)) {
4583                 dev->max_vblank_count = 0;
4584                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4585         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4586                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4587                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4588         } else {
4589                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4590                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4591         }
4592
4593         /*
4594          * Opt out of the vblank disable timer on everything except gen2.
4595          * Gen2 doesn't have a hardware frame counter and so depends on
4596          * vblank interrupts to produce sane vblank seuquence numbers.
4597          */
4598         if (!IS_GEN2(dev_priv))
4599                 dev->vblank_disable_immediate = true;
4600
4601         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4602         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4603
4604         if (IS_CHERRYVIEW(dev_priv)) {
4605                 dev->driver->irq_handler = cherryview_irq_handler;
4606                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4607                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4608                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4609                 dev->driver->enable_vblank = valleyview_enable_vblank;
4610                 dev->driver->disable_vblank = valleyview_disable_vblank;
4611                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4612         } else if (IS_VALLEYVIEW(dev_priv)) {
4613                 dev->driver->irq_handler = valleyview_irq_handler;
4614                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4615                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4616                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4617                 dev->driver->enable_vblank = valleyview_enable_vblank;
4618                 dev->driver->disable_vblank = valleyview_disable_vblank;
4619                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4620         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4621                 dev->driver->irq_handler = gen8_irq_handler;
4622                 dev->driver->irq_preinstall = gen8_irq_reset;
4623                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4624                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4625                 dev->driver->enable_vblank = gen8_enable_vblank;
4626                 dev->driver->disable_vblank = gen8_disable_vblank;
4627                 if (IS_BROXTON(dev))
4628                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4629                 else if (HAS_PCH_SPT(dev))
4630                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4631                 else
4632                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4633         } else if (HAS_PCH_SPLIT(dev)) {
4634                 dev->driver->irq_handler = ironlake_irq_handler;
4635                 dev->driver->irq_preinstall = ironlake_irq_reset;
4636                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4637                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4638                 dev->driver->enable_vblank = ironlake_enable_vblank;
4639                 dev->driver->disable_vblank = ironlake_disable_vblank;
4640                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4641         } else {
4642                 if (IS_GEN2(dev_priv)) {
4643                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4644                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4645                         dev->driver->irq_handler = i8xx_irq_handler;
4646                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4647                 } else if (IS_GEN3(dev_priv)) {
4648                         dev->driver->irq_preinstall = i915_irq_preinstall;
4649                         dev->driver->irq_postinstall = i915_irq_postinstall;
4650                         dev->driver->irq_uninstall = i915_irq_uninstall;
4651                         dev->driver->irq_handler = i915_irq_handler;
4652                 } else {
4653                         dev->driver->irq_preinstall = i965_irq_preinstall;
4654                         dev->driver->irq_postinstall = i965_irq_postinstall;
4655                         dev->driver->irq_uninstall = i965_irq_uninstall;
4656                         dev->driver->irq_handler = i965_irq_handler;
4657                 }
4658                 if (I915_HAS_HOTPLUG(dev_priv))
4659                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4660                 dev->driver->enable_vblank = i915_enable_vblank;
4661                 dev->driver->disable_vblank = i915_disable_vblank;
4662         }
4663 }
4664
4665 /**
4666  * intel_irq_install - enables the hardware interrupt
4667  * @dev_priv: i915 device instance
4668  *
4669  * This function enables the hardware interrupt handling, but leaves the hotplug
4670  * handling still disabled. It is called after intel_irq_init().
4671  *
4672  * In the driver load and resume code we need working interrupts in a few places
4673  * but don't want to deal with the hassle of concurrent probe and hotplug
4674  * workers. Hence the split into this two-stage approach.
4675  */
4676 int intel_irq_install(struct drm_i915_private *dev_priv)
4677 {
4678         /*
4679          * We enable some interrupt sources in our postinstall hooks, so mark
4680          * interrupts as enabled _before_ actually enabling them to avoid
4681          * special cases in our ordering checks.
4682          */
4683         dev_priv->pm.irqs_enabled = true;
4684
4685         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4686 }
4687
4688 /**
4689  * intel_irq_uninstall - finilizes all irq handling
4690  * @dev_priv: i915 device instance
4691  *
4692  * This stops interrupt and hotplug handling and unregisters and frees all
4693  * resources acquired in the init functions.
4694  */
4695 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4696 {
4697         drm_irq_uninstall(dev_priv->dev);
4698         intel_hpd_cancel_work(dev_priv);
4699         dev_priv->pm.irqs_enabled = false;
4700 }
4701
4702 /**
4703  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4704  * @dev_priv: i915 device instance
4705  *
4706  * This function is used to disable interrupts at runtime, both in the runtime
4707  * pm and the system suspend/resume code.
4708  */
4709 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4710 {
4711         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4712         dev_priv->pm.irqs_enabled = false;
4713         synchronize_irq(dev_priv->dev->irq);
4714 }
4715
4716 /**
4717  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4718  * @dev_priv: i915 device instance
4719  *
4720  * This function is used to enable interrupts at runtime, both in the runtime
4721  * pm and the system suspend/resume code.
4722  */
4723 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4724 {
4725         dev_priv->pm.irqs_enabled = true;
4726         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4727         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4728 }