drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         enum intel_display_power_domain power_domain;
  73         u32 tmp;
  74         bool ret;
  75
  76         power_domain = intel_display_port_power_domain(encoder);
  77         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  78                 return false;
  79
  80         ret = false;
  81
  82         tmp = I915_READ(crt->adpa_reg);
  83
  84         if (!(tmp & ADPA_DAC_ENABLE))
  85                 goto out;
  86
  87         if (HAS_PCH_CPT(dev))
  88                 *pipe = PORT_TO_PIPE_CPT(tmp);
  89         else
  90                 *pipe = PORT_TO_PIPE(tmp);
  91
  92         ret = true;
  93 out:
  94         intel_display_power_put(dev_priv, power_domain);
  95
  96         return ret;
  97 }
  98
  99 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 100 {
 101         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 102         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 103         u32 tmp, flags = 0;
 104
 105         tmp = I915_READ(crt->adpa_reg);
 106
 107         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 108                 flags |= DRM_MODE_FLAG_PHSYNC;
 109         else
 110                 flags |= DRM_MODE_FLAG_NHSYNC;
 111
 112         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 113                 flags |= DRM_MODE_FLAG_PVSYNC;
 114         else
 115                 flags |= DRM_MODE_FLAG_NVSYNC;
 116
 117         return flags;
 118 }
 119
 120 static void intel_crt_get_config(struct intel_encoder *encoder,
 121                                  struct intel_crtc_state *pipe_config)
 122 {
 123         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 124
 125         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 126 }
 127
 128 static void hsw_crt_get_config(struct intel_encoder *encoder,
 129                                struct intel_crtc_state *pipe_config)
 130 {
 131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 132
 133         intel_ddi_get_config(encoder, pipe_config);
 134
 135         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 136                                               DRM_MODE_FLAG_NHSYNC |
 137                                               DRM_MODE_FLAG_PVSYNC |
 138                                               DRM_MODE_FLAG_NVSYNC);
 139         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 140
 141         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 142 }
 143
 144 /* Note: The caller is required to filter out dpms modes not supported by the
 145  * platform. */
 146 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 147 {
 148         struct drm_device *dev = encoder->base.dev;
 149         struct drm_i915_private *dev_priv = dev->dev_private;
 150         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 151         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 152         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 153         u32 adpa;
 154
 155         if (INTEL_INFO(dev)->gen >= 5)
 156                 adpa = ADPA_HOTPLUG_BITS;
 157         else
 158                 adpa = 0;
 159
 160         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 161                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 162         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 163                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 164
 165         /* For CPT allow 3 pipe config, for others just use A or B */
 166         if (HAS_PCH_LPT(dev))
 167                 ; /* Those bits don't exist here */
 168         else if (HAS_PCH_CPT(dev))
 169                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 170         else if (crtc->pipe == 0)
 171                 adpa |= ADPA_PIPE_A_SELECT;
 172         else
 173                 adpa |= ADPA_PIPE_B_SELECT;
 174
 175         if (!HAS_PCH_SPLIT(dev))
 176                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 177
 178         switch (mode) {
 179         case DRM_MODE_DPMS_ON:
 180                 adpa |= ADPA_DAC_ENABLE;
 181                 break;
 182         case DRM_MODE_DPMS_STANDBY:
 183                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 184                 break;
 185         case DRM_MODE_DPMS_SUSPEND:
 186                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 187                 break;
 188         case DRM_MODE_DPMS_OFF:
 189                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 190                 break;
 191         }
 192
 193         I915_WRITE(crt->adpa_reg, adpa);
 194 }
 195
 196 static void intel_disable_crt(struct intel_encoder *encoder)
 197 {
 198         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 199 }
 200
 201 static void pch_disable_crt(struct intel_encoder *encoder)
 202 {
 203 }
 204
 205 static void pch_post_disable_crt(struct intel_encoder *encoder)
 206 {
 207         intel_disable_crt(encoder);
 208 }
 209
 210 static void intel_enable_crt(struct intel_encoder *encoder)
 211 {
 212         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON);
 213 }
 214
 215 static enum drm_mode_status
 216 intel_crt_mode_valid(struct drm_connector *connector,
 217                      struct drm_display_mode *mode)
 218 {
 219         struct drm_device *dev = connector->dev;
 220         int max_dotclk = to_i915(dev)->max_dotclk_freq;
 221         int max_clock;
 222
 223         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 224                 return MODE_NO_DBLESCAN;
 225
 226         if (mode->clock < 25000)
 227                 return MODE_CLOCK_LOW;
 228
 229         if (HAS_PCH_LPT(dev))
 230                 max_clock = 180000;
 231         else if (IS_VALLEYVIEW(dev))
 232                 /*
 233                  * 270 MHz due to current DPLL limits,
 234                  * DAC limit supposedly 355 MHz.
 235                  */
 236                 max_clock = 270000;
 237         else if (IS_GEN3(dev) || IS_GEN4(dev))
 238                 max_clock = 400000;
 239         else
 240                 max_clock = 350000;
 241         if (mode->clock > max_clock)
 242                 return MODE_CLOCK_HIGH;
 243
 244         if (mode->clock > max_dotclk)
 245                 return MODE_CLOCK_HIGH;
 246
 247         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 248         if (HAS_PCH_LPT(dev) &&
 249             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 250                 return MODE_CLOCK_HIGH;
 251
 252         return MODE_OK;
 253 }
 254
 255 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 256                                      struct intel_crtc_state *pipe_config)
 257 {
 258         struct drm_device *dev = encoder->base.dev;
 259
 260         if (HAS_PCH_SPLIT(dev))
 261                 pipe_config->has_pch_encoder = true;
 262
 263         /* LPT FDI RX only supports 8bpc. */
 264         if (HAS_PCH_LPT(dev)) {
 265                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 266                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 267                         return false;
 268                 }
 269
 270                 pipe_config->pipe_bpp = 24;
 271         }
 272
 273         /* FDI must always be 2.7 GHz */
 274         if (HAS_DDI(dev))
 275                 pipe_config->port_clock = 135000 * 2;
 276
 277         return true;
 278 }
 279
 280 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 281 {
 282         struct drm_device *dev = connector->dev;
 283         struct intel_crt *crt = intel_attached_crt(connector);
 284         struct drm_i915_private *dev_priv = dev->dev_private;
 285         u32 adpa;
 286         bool ret;
 287
 288         /* The first time through, trigger an explicit detection cycle */
 289         if (crt->force_hotplug_required) {
 290                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 291                 u32 save_adpa;
 292
 293                 crt->force_hotplug_required = 0;
 294
 295                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 296                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 297
 298                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 299                 if (turn_off_dac)
 300                         adpa &= ~ADPA_DAC_ENABLE;
 301
 302                 I915_WRITE(crt->adpa_reg, adpa);
 303
 304                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 305                              1000))
 306                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 307
 308                 if (turn_off_dac) {
 309                         I915_WRITE(crt->adpa_reg, save_adpa);
 310                         POSTING_READ(crt->adpa_reg);
 311                 }
 312         }
 313
 314         /* Check the status to see if both blue and green are on now */
 315         adpa = I915_READ(crt->adpa_reg);
 316         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 317                 ret = true;
 318         else
 319                 ret = false;
 320         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 321
 322         return ret;
 323 }
 324
 325 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 326 {
 327         struct drm_device *dev = connector->dev;
 328         struct intel_crt *crt = intel_attached_crt(connector);
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         u32 adpa;
 331         bool ret;
 332         u32 save_adpa;
 333
 334         save_adpa = adpa = I915_READ(crt->adpa_reg);
 335         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 336
 337         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 338
 339         I915_WRITE(crt->adpa_reg, adpa);
 340
 341         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 342                      1000)) {
 343                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 344                 I915_WRITE(crt->adpa_reg, save_adpa);
 345         }
 346
 347         /* Check the status to see if both blue and green are on now */
 348         adpa = I915_READ(crt->adpa_reg);
 349         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 350                 ret = true;
 351         else
 352                 ret = false;
 353
 354         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 355
 356         return ret;
 357 }
 358
 359 /**
 360  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 361  *
 362  * Not for i915G/i915GM
 363  *
 364  * \return true if CRT is connected.
 365  * \return false if CRT is disconnected.
 366  */
 367 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 368 {
 369         struct drm_device *dev = connector->dev;
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         u32 stat;
 372         bool ret = false;
 373         int i, tries = 0;
 374
 375         if (HAS_PCH_SPLIT(dev))
 376                 return intel_ironlake_crt_detect_hotplug(connector);
 377
 378         if (IS_VALLEYVIEW(dev))
 379                 return valleyview_crt_detect_hotplug(connector);
 380
 381         /*
 382          * On 4 series desktop, CRT detect sequence need to be done twice
 383          * to get a reliable result.
 384          */
 385
 386         if (IS_G4X(dev) && !IS_GM45(dev))
 387                 tries = 2;
 388         else
 389                 tries = 1;
 390
 391         for (i = 0; i < tries ; i++) {
 392                 /* turn on the FORCE_DETECT */
 393                 i915_hotplug_interrupt_update(dev_priv,
 394                                               CRT_HOTPLUG_FORCE_DETECT,
 395                                               CRT_HOTPLUG_FORCE_DETECT);
 396                 /* wait for FORCE_DETECT to go off */
 397                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 398                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 399                              1000))
 400                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 401         }
 402
 403         stat = I915_READ(PORT_HOTPLUG_STAT);
 404         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 405                 ret = true;
 406
 407         /* clear the interrupt we just generated, if any */
 408         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 409
 410         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 411
 412         return ret;
 413 }
 414
 415 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 416                                 struct i2c_adapter *i2c)
 417 {
 418         struct edid *edid;
 419
 420         edid = drm_get_edid(connector, i2c);
 421
 422         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 423                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 424                 intel_gmbus_force_bit(i2c, true);
 425                 edid = drm_get_edid(connector, i2c);
 426                 intel_gmbus_force_bit(i2c, false);
 427         }
 428
 429         return edid;
 430 }
 431
 432 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 433 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 434                                 struct i2c_adapter *adapter)
 435 {
 436         struct edid *edid;
 437         int ret;
 438
 439         edid = intel_crt_get_edid(connector, adapter);
 440         if (!edid)
 441                 return 0;
 442
 443         ret = intel_connector_update_modes(connector, edid);
 444         kfree(edid);
 445
 446         return ret;
 447 }
 448
 449 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 450 {
 451         struct intel_crt *crt = intel_attached_crt(connector);
 452         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 453         struct edid *edid;
 454         struct i2c_adapter *i2c;
 455
 456         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 457
 458         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 459         edid = intel_crt_get_edid(connector, i2c);
 460
 461         if (edid) {
 462                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 463
 464                 /*
 465                  * This may be a DVI-I connector with a shared DDC
 466                  * link between analog and digital outputs, so we
 467                  * have to check the EDID input spec of the attached device.
 468                  */
 469                 if (!is_digital) {
 470                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 471                         return true;
 472                 }
 473
 474                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 475         } else {
 476                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 477         }
 478
 479         kfree(edid);
 480
 481         return false;
 482 }
 483
 484 static enum drm_connector_status
 485 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 486 {
 487         struct drm_device *dev = crt->base.base.dev;
 488         struct drm_i915_private *dev_priv = dev->dev_private;
 489         uint32_t save_bclrpat;
 490         uint32_t save_vtotal;
 491         uint32_t vtotal, vactive;
 492         uint32_t vsample;
 493         uint32_t vblank, vblank_start, vblank_end;
 494         uint32_t dsl;
 495         i915_reg_t bclrpat_reg, vtotal_reg,
 496                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 497         uint8_t st00;
 498         enum drm_connector_status status;
 499
 500         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 501
 502         bclrpat_reg = BCLRPAT(pipe);
 503         vtotal_reg = VTOTAL(pipe);
 504         vblank_reg = VBLANK(pipe);
 505         vsync_reg = VSYNC(pipe);
 506         pipeconf_reg = PIPECONF(pipe);
 507         pipe_dsl_reg = PIPEDSL(pipe);
 508
 509         save_bclrpat = I915_READ(bclrpat_reg);
 510         save_vtotal = I915_READ(vtotal_reg);
 511         vblank = I915_READ(vblank_reg);
 512
 513         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 514         vactive = (save_vtotal & 0x7ff) + 1;
 515
 516         vblank_start = (vblank & 0xfff) + 1;
 517         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 518
 519         /* Set the border color to purple. */
 520         I915_WRITE(bclrpat_reg, 0x500050);
 521
 522         if (!IS_GEN2(dev)) {
 523                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 524                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 525                 POSTING_READ(pipeconf_reg);
 526                 /* Wait for next Vblank to substitue
 527                  * border color for Color info */
 528                 intel_wait_for_vblank(dev, pipe);
 529                 st00 = I915_READ8(_VGA_MSR_WRITE);
 530                 status = ((st00 & (1 << 4)) != 0) ?
 531                         connector_status_connected :
 532                         connector_status_disconnected;
 533
 534                 I915_WRITE(pipeconf_reg, pipeconf);
 535         } else {
 536                 bool restore_vblank = false;
 537                 int count, detect;
 538
 539                 /*
 540                 * If there isn't any border, add some.
 541                 * Yes, this will flicker
 542                 */
 543                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 544                         uint32_t vsync = I915_READ(vsync_reg);
 545                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 546
 547                         vblank_start = vsync_start;
 548                         I915_WRITE(vblank_reg,
 549                                    (vblank_start - 1) |
 550                                    ((vblank_end - 1) << 16));
 551                         restore_vblank = true;
 552                 }
 553                 /* sample in the vertical border, selecting the larger one */
 554                 if (vblank_start - vactive >= vtotal - vblank_end)
 555                         vsample = (vblank_start + vactive) >> 1;
 556                 else
 557                         vsample = (vtotal + vblank_end) >> 1;
 558
 559                 /*
 560                  * Wait for the border to be displayed
 561                  */
 562                 while (I915_READ(pipe_dsl_reg) >= vactive)
 563                         ;
 564                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 565                         ;
 566                 /*
 567                  * Watch ST00 for an entire scanline
 568                  */
 569                 detect = 0;
 570                 count = 0;
 571                 do {
 572                         count++;
 573                         /* Read the ST00 VGA status register */
 574                         st00 = I915_READ8(_VGA_MSR_WRITE);
 575                         if (st00 & (1 << 4))
 576                                 detect++;
 577                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 578
 579                 /* restore vblank if necessary */
 580                 if (restore_vblank)
 581                         I915_WRITE(vblank_reg, vblank);
 582                 /*
 583                  * If more than 3/4 of the scanline detected a monitor,
 584                  * then it is assumed to be present. This works even on i830,
 585                  * where there isn't any way to force the border color across
 586                  * the screen
 587                  */
 588                 status = detect * 4 > count * 3 ?
 589                          connector_status_connected :
 590                          connector_status_disconnected;
 591         }
 592
 593         /* Restore previous settings */
 594         I915_WRITE(bclrpat_reg, save_bclrpat);
 595
 596         return status;
 597 }
 598
 599 static enum drm_connector_status
 600 intel_crt_detect(struct drm_connector *connector, bool force)
 601 {
 602         struct drm_device *dev = connector->dev;
 603         struct drm_i915_private *dev_priv = dev->dev_private;
 604         struct intel_crt *crt = intel_attached_crt(connector);
 605         struct intel_encoder *intel_encoder = &crt->base;
 606         enum intel_display_power_domain power_domain;
 607         enum drm_connector_status status;
 608         struct intel_load_detect_pipe tmp;
 609         struct drm_modeset_acquire_ctx ctx;
 610
 611         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 612                       connector->base.id, connector->name,
 613                       force);
 614
 615         power_domain = intel_display_port_power_domain(intel_encoder);
 616         intel_display_power_get(dev_priv, power_domain);
 617
 618         if (I915_HAS_HOTPLUG(dev)) {
 619                 /* We can not rely on the HPD pin always being correctly wired
 620                  * up, for example many KVM do not pass it through, and so
 621                  * only trust an assertion that the monitor is connected.
 622                  */
 623                 if (intel_crt_detect_hotplug(connector)) {
 624                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 625                         status = connector_status_connected;
 626                         goto out;
 627                 } else
 628                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 629         }
 630
 631         if (intel_crt_detect_ddc(connector)) {
 632                 status = connector_status_connected;
 633                 goto out;
 634         }
 635
 636         /* Load detection is broken on HPD capable machines. Whoever wants a
 637          * broken monitor (without edid) to work behind a broken kvm (that fails
 638          * to have the right resistors for HP detection) needs to fix this up.
 639          * For now just bail out. */
 640         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
 641                 status = connector_status_disconnected;
 642                 goto out;
 643         }
 644
 645         if (!force) {
 646                 status = connector->status;
 647                 goto out;
 648         }
 649
 650         drm_modeset_acquire_init(&ctx, 0);
 651
 652         /* for pre-945g platforms use load detect */
 653         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
 654                 if (intel_crt_detect_ddc(connector))
 655                         status = connector_status_connected;
 656                 else if (INTEL_INFO(dev)->gen < 4)
 657                         status = intel_crt_load_detect(crt,
 658                                 to_intel_crtc(connector->state->crtc)->pipe);
 659                 else if (i915.load_detect_test)
 660                         status = connector_status_disconnected;
 661                 else
 662                         status = connector_status_unknown;
 663                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
 664         } else
 665                 status = connector_status_unknown;
 666
 667         drm_modeset_drop_locks(&ctx);
 668         drm_modeset_acquire_fini(&ctx);
 669
 670 out:
 671         intel_display_power_put(dev_priv, power_domain);
 672         return status;
 673 }
 674
 675 static void intel_crt_destroy(struct drm_connector *connector)
 676 {
 677         drm_connector_cleanup(connector);
 678         kfree(connector);
 679 }
 680
 681 static int intel_crt_get_modes(struct drm_connector *connector)
 682 {
 683         struct drm_device *dev = connector->dev;
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         struct intel_crt *crt = intel_attached_crt(connector);
 686         struct intel_encoder *intel_encoder = &crt->base;
 687         enum intel_display_power_domain power_domain;
 688         int ret;
 689         struct i2c_adapter *i2c;
 690
 691         power_domain = intel_display_port_power_domain(intel_encoder);
 692         intel_display_power_get(dev_priv, power_domain);
 693
 694         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 695         ret = intel_crt_ddc_get_modes(connector, i2c);
 696         if (ret || !IS_G4X(dev))
 697                 goto out;
 698
 699         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 700         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 701         ret = intel_crt_ddc_get_modes(connector, i2c);
 702
 703 out:
 704         intel_display_power_put(dev_priv, power_domain);
 705
 706         return ret;
 707 }
 708
 709 static int intel_crt_set_property(struct drm_connector *connector,
 710                                   struct drm_property *property,
 711                                   uint64_t value)
 712 {
 713         return 0;
 714 }
 715
 716 static void intel_crt_reset(struct drm_connector *connector)
 717 {
 718         struct drm_device *dev = connector->dev;
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         struct intel_crt *crt = intel_attached_crt(connector);
 721
 722         if (INTEL_INFO(dev)->gen >= 5) {
 723                 u32 adpa;
 724
 725                 adpa = I915_READ(crt->adpa_reg);
 726                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 727                 adpa |= ADPA_HOTPLUG_BITS;
 728                 I915_WRITE(crt->adpa_reg, adpa);
 729                 POSTING_READ(crt->adpa_reg);
 730
 731                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 732                 crt->force_hotplug_required = 1;
 733         }
 734
 735 }
 736
 737 /*
 738  * Routines for controlling stuff on the analog port
 739  */
 740
 741 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 742         .reset = intel_crt_reset,
 743         .dpms = drm_atomic_helper_connector_dpms,
 744         .detect = intel_crt_detect,
 745         .fill_modes = drm_helper_probe_single_connector_modes,
 746         .destroy = intel_crt_destroy,
 747         .set_property = intel_crt_set_property,
 748         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 749         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 750         .atomic_get_property = intel_connector_atomic_get_property,
 751 };
 752
 753 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 754         .mode_valid = intel_crt_mode_valid,
 755         .get_modes = intel_crt_get_modes,
 756         .best_encoder = intel_best_encoder,
 757 };
 758
 759 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 760         .destroy = intel_encoder_destroy,
 761 };
 762
 763 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
 764 {
 765         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
 766         return 1;
 767 }
 768
 769 static const struct dmi_system_id intel_no_crt[] = {
 770         {
 771                 .callback = intel_no_crt_dmi_callback,
 772                 .ident = "ACER ZGB",
 773                 .matches = {
 774                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 775                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 776                 },
 777         },
 778         {
 779                 .callback = intel_no_crt_dmi_callback,
 780                 .ident = "DELL XPS 8700",
 781                 .matches = {
 782                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 783                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
 784                 },
 785         },
 786         { }
 787 };
 788
 789 void intel_crt_init(struct drm_device *dev)
 790 {
 791         struct drm_connector *connector;
 792         struct intel_crt *crt;
 793         struct intel_connector *intel_connector;
 794         struct drm_i915_private *dev_priv = dev->dev_private;
 795         i915_reg_t adpa_reg;
 796         u32 adpa;
 797
 798         /* Skip machines without VGA that falsely report hotplug events */
 799         if (dmi_check_system(intel_no_crt))
 800                 return;
 801
 802         if (HAS_PCH_SPLIT(dev))
 803                 adpa_reg = PCH_ADPA;
 804         else if (IS_VALLEYVIEW(dev))
 805                 adpa_reg = VLV_ADPA;
 806         else
 807                 adpa_reg = ADPA;
 808
 809         adpa = I915_READ(adpa_reg);
 810         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 811                 /*
 812                  * On some machines (some IVB at least) CRT can be
 813                  * fused off, but there's no known fuse bit to
 814                  * indicate that. On these machine the ADPA register
 815                  * works normally, except the DAC enable bit won't
 816                  * take. So the only way to tell is attempt to enable
 817                  * it and see what happens.
 818                  */
 819                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 820                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 821                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 822                         return;
 823                 I915_WRITE(adpa_reg, adpa);
 824         }
 825
 826         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 827         if (!crt)
 828                 return;
 829
 830         intel_connector = intel_connector_alloc();
 831         if (!intel_connector) {
 832                 kfree(crt);
 833                 return;
 834         }
 835
 836         connector = &intel_connector->base;
 837         crt->connector = intel_connector;
 838         drm_connector_init(dev, &intel_connector->base,
 839                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 840
 841         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 842                          DRM_MODE_ENCODER_DAC, NULL);
 843
 844         intel_connector_attach_encoder(intel_connector, &crt->base);
 845
 846         crt->base.type = INTEL_OUTPUT_ANALOG;
 847         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 848         if (IS_I830(dev))
 849                 crt->base.crtc_mask = (1 << 0);
 850         else
 851                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 852
 853         if (IS_GEN2(dev))
 854                 connector->interlace_allowed = 0;
 855         else
 856                 connector->interlace_allowed = 1;
 857         connector->doublescan_allowed = 0;
 858
 859         crt->adpa_reg = adpa_reg;
 860
 861         crt->base.compute_config = intel_crt_compute_config;
 862         if (HAS_PCH_SPLIT(dev)) {
 863                 crt->base.disable = pch_disable_crt;
 864                 crt->base.post_disable = pch_post_disable_crt;
 865         } else {
 866                 crt->base.disable = intel_disable_crt;
 867         }
 868         crt->base.enable = intel_enable_crt;
 869         if (I915_HAS_HOTPLUG(dev))
 870                 crt->base.hpd_pin = HPD_CRT;
 871         if (HAS_DDI(dev)) {
 872                 crt->base.get_config = hsw_crt_get_config;
 873                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 874         } else {
 875                 crt->base.get_config = intel_crt_get_config;
 876                 crt->base.get_hw_state = intel_crt_get_hw_state;
 877         }
 878         intel_connector->get_hw_state = intel_connector_get_hw_state;
 879         intel_connector->unregister = intel_connector_unregister;
 880
 881         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 882
 883         drm_connector_register(connector);
 884
 885         if (!I915_HAS_HOTPLUG(dev))
 886                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 887
 888         /*
 889          * Configure the automatic hotplug detection stuff
 890          */
 891         crt->force_hotplug_required = 0;
 892
 893         /*
 894          * TODO: find a proper way to discover whether we need to set the the
 895          * polarity and link reversal bits or not, instead of relying on the
 896          * BIOS.
 897          */
 898         if (HAS_PCH_LPT(dev)) {
 899                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 900                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 901
 902                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
 903         }
 904
 905         intel_crt_reset(connector);
 906 }