drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34 };
  35
  36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  37  * them for both DP and FDI transports, allowing those ports to
  38  * automatically adapt to HDMI connections as well
  39  */
  40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  41         { 0x00FFFFFF, 0x0006000E },
  42         { 0x00D75FFF, 0x0005000A },
  43         { 0x00C30FFF, 0x00040006 },
  44         { 0x80AAAFFF, 0x000B0000 },
  45         { 0x00FFFFFF, 0x0005000A },
  46         { 0x00D75FFF, 0x000C0004 },
  47         { 0x80C30FFF, 0x000B0000 },
  48         { 0x00FFFFFF, 0x00040006 },
  49         { 0x80D75FFF, 0x000B0000 },
  50 };
  51
  52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  53         { 0x00FFFFFF, 0x0007000E },
  54         { 0x00D75FFF, 0x000F000A },
  55         { 0x00C30FFF, 0x00060006 },
  56         { 0x00AAAFFF, 0x001E0000 },
  57         { 0x00FFFFFF, 0x000F000A },
  58         { 0x00D75FFF, 0x00160004 },
  59         { 0x00C30FFF, 0x001E0000 },
  60         { 0x00FFFFFF, 0x00060006 },
  61         { 0x00D75FFF, 0x001E0000 },
  62 };
  63
  64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  65                                         /* Idx  NT mV d T mV d  db      */
  66         { 0x00FFFFFF, 0x0006000E },     /* 0:   400     400     0       */
  67         { 0x00E79FFF, 0x000E000C },     /* 1:   400     500     2       */
  68         { 0x00D75FFF, 0x0005000A },     /* 2:   400     600     3.5     */
  69         { 0x00FFFFFF, 0x0005000A },     /* 3:   600     600     0       */
  70         { 0x00E79FFF, 0x001D0007 },     /* 4:   600     750     2       */
  71         { 0x00D75FFF, 0x000C0004 },     /* 5:   600     900     3.5     */
  72         { 0x00FFFFFF, 0x00040006 },     /* 6:   800     800     0       */
  73         { 0x80E79FFF, 0x00030002 },     /* 7:   800     1000    2       */
  74         { 0x00FFFFFF, 0x00140005 },     /* 8:   850     850     0       */
  75         { 0x00FFFFFF, 0x000C0004 },     /* 9:   900     900     0       */
  76         { 0x00FFFFFF, 0x001C0003 },     /* 10:  950     950     0       */
  77         { 0x80FFFFFF, 0x00030002 },     /* 11:  1000    1000    0       */
  78 };
  79
  80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  81         { 0x00FFFFFF, 0x00000012 },
  82         { 0x00EBAFFF, 0x00020011 },
  83         { 0x00C71FFF, 0x0006000F },
  84         { 0x00AAAFFF, 0x000E000A },
  85         { 0x00FFFFFF, 0x00020011 },
  86         { 0x00DB6FFF, 0x0005000F },
  87         { 0x00BEEFFF, 0x000A000C },
  88         { 0x00FFFFFF, 0x0005000F },
  89         { 0x00DB6FFF, 0x000A000C },
  90 };
  91
  92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  93         { 0x00FFFFFF, 0x0007000E },
  94         { 0x00D75FFF, 0x000E000A },
  95         { 0x00BEFFFF, 0x00140006 },
  96         { 0x80B2CFFF, 0x001B0002 },
  97         { 0x00FFFFFF, 0x000E000A },
  98         { 0x00DB6FFF, 0x00160005 },
  99         { 0x80C71FFF, 0x001A0002 },
 100         { 0x00F7DFFF, 0x00180004 },
 101         { 0x80D75FFF, 0x001B0002 },
 102 };
 103
 104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 105         { 0x00FFFFFF, 0x0001000E },
 106         { 0x00D75FFF, 0x0004000A },
 107         { 0x00C30FFF, 0x00070006 },
 108         { 0x00AAAFFF, 0x000C0000 },
 109         { 0x00FFFFFF, 0x0004000A },
 110         { 0x00D75FFF, 0x00090004 },
 111         { 0x00C30FFF, 0x000C0000 },
 112         { 0x00FFFFFF, 0x00070006 },
 113         { 0x00D75FFF, 0x000C0000 },
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 117                                         /* Idx  NT mV d T mV df db      */
 118         { 0x00FFFFFF, 0x0007000E },     /* 0:   400     400     0       */
 119         { 0x00D75FFF, 0x000E000A },     /* 1:   400     600     3.5     */
 120         { 0x00BEFFFF, 0x00140006 },     /* 2:   400     800     6       */
 121         { 0x00FFFFFF, 0x0009000D },     /* 3:   450     450     0       */
 122         { 0x00FFFFFF, 0x000E000A },     /* 4:   600     600     0       */
 123         { 0x00D7FFFF, 0x00140006 },     /* 5:   600     800     2.5     */
 124         { 0x80CB2FFF, 0x001B0002 },     /* 6:   600     1000    4.5     */
 125         { 0x00FFFFFF, 0x00140006 },     /* 7:   800     800     0       */
 126         { 0x80E79FFF, 0x001B0002 },     /* 8:   800     1000    2       */
 127         { 0x80FFFFFF, 0x001B0002 },     /* 9:   1000    1000    0       */
 128 };
 129
 130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 131         { 0x00000018, 0x000000a2 },
 132         { 0x00004014, 0x0000009B },
 133         { 0x00006012, 0x00000088 },
 134         { 0x00008010, 0x00000087 },
 135         { 0x00000018, 0x0000009B },
 136         { 0x00004014, 0x00000088 },
 137         { 0x00006012, 0x00000087 },
 138         { 0x00000018, 0x00000088 },
 139         { 0x00004014, 0x00000087 },
 140 };
 141
 142 /* eDP 1.4 low vswing translation parameters */
 143 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 144         { 0x00000018, 0x000000a8 },
 145         { 0x00002016, 0x000000ab },
 146         { 0x00006012, 0x000000a2 },
 147         { 0x00008010, 0x00000088 },
 148         { 0x00000018, 0x000000ab },
 149         { 0x00004014, 0x000000a2 },
 150         { 0x00006012, 0x000000a6 },
 151         { 0x00000018, 0x000000a2 },
 152         { 0x00005013, 0x0000009c },
 153         { 0x00000018, 0x00000088 },
 154 };
 155
 156
 157 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 158                                         /* Idx  NT mV   T mV    db  */
 159         { 0x00004014, 0x00000087 },     /* 0:   800     1000    2   */
 160 };
 161
 162 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 163 {
 164         struct drm_encoder *encoder = &intel_encoder->base;
 165         int type = intel_encoder->type;
 166
 167         if (type == INTEL_OUTPUT_DP_MST) {
 168                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 169                 return intel_dig_port->port;
 170         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 171             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 172                 struct intel_digital_port *intel_dig_port =
 173                         enc_to_dig_port(encoder);
 174                 return intel_dig_port->port;
 175
 176         } else if (type == INTEL_OUTPUT_ANALOG) {
 177                 return PORT_E;
 178
 179         } else {
 180                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 181                 BUG();
 182         }
 183 }
 184
 185 /*
 186  * Starting with Haswell, DDI port buffers must be programmed with correct
 187  * values in advance. The buffer values are different for FDI and DP modes,
 188  * but the HDMI/DVI fields are shared among those. So we program the DDI
 189  * in either FDI or DP modes only, as HDMI connections will work with both
 190  * of those
 191  */
 192 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         u32 reg;
 196         int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 197             size;
 198         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 199         const struct ddi_buf_trans *ddi_translations_fdi;
 200         const struct ddi_buf_trans *ddi_translations_dp;
 201         const struct ddi_buf_trans *ddi_translations_edp;
 202         const struct ddi_buf_trans *ddi_translations_hdmi;
 203         const struct ddi_buf_trans *ddi_translations;
 204
 205         if (IS_SKYLAKE(dev)) {
 206                 ddi_translations_fdi = NULL;
 207                 ddi_translations_dp = skl_ddi_translations_dp;
 208                 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 209                 if (dev_priv->vbt.edp_low_vswing) {
 210                         ddi_translations_edp = skl_ddi_translations_edp;
 211                         n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 212                 } else {
 213                         ddi_translations_edp = skl_ddi_translations_dp;
 214                         n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 215                 }
 216
 217                 /*
 218                  * On SKL, the recommendation from the hw team is to always use
 219                  * a certain type of level shifter (and thus the corresponding
 220                  * 800mV+2dB entry). Given that's the only validated entry, we
 221                  * override what is in the VBT, at least until further notice.
 222                  */
 223                 hdmi_level = 0;
 224                 ddi_translations_hdmi = skl_ddi_translations_hdmi;
 225                 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 226                 hdmi_default_entry = 0;
 227         } else if (IS_BROADWELL(dev)) {
 228                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 229                 ddi_translations_dp = bdw_ddi_translations_dp;
 230                 ddi_translations_edp = bdw_ddi_translations_edp;
 231                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 232                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 233                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 234                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 235                 hdmi_default_entry = 7;
 236         } else if (IS_HASWELL(dev)) {
 237                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 238                 ddi_translations_dp = hsw_ddi_translations_dp;
 239                 ddi_translations_edp = hsw_ddi_translations_dp;
 240                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 241                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 242                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 243                 hdmi_default_entry = 6;
 244         } else {
 245                 WARN(1, "ddi translation table missing\n");
 246                 ddi_translations_edp = bdw_ddi_translations_dp;
 247                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 248                 ddi_translations_dp = bdw_ddi_translations_dp;
 249                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 250                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 251                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 252                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 253                 hdmi_default_entry = 7;
 254         }
 255
 256         switch (port) {
 257         case PORT_A:
 258                 ddi_translations = ddi_translations_edp;
 259                 size = n_edp_entries;
 260                 break;
 261         case PORT_B:
 262         case PORT_C:
 263                 ddi_translations = ddi_translations_dp;
 264                 size = n_dp_entries;
 265                 break;
 266         case PORT_D:
 267                 if (intel_dp_is_edp(dev, PORT_D)) {
 268                         ddi_translations = ddi_translations_edp;
 269                         size = n_edp_entries;
 270                 } else {
 271                         ddi_translations = ddi_translations_dp;
 272                         size = n_dp_entries;
 273                 }
 274                 break;
 275         case PORT_E:
 276                 if (ddi_translations_fdi)
 277                         ddi_translations = ddi_translations_fdi;
 278                 else
 279                         ddi_translations = ddi_translations_dp;
 280                 size = n_dp_entries;
 281                 break;
 282         default:
 283                 BUG();
 284         }
 285
 286         for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
 287                 I915_WRITE(reg, ddi_translations[i].trans1);
 288                 reg += 4;
 289                 I915_WRITE(reg, ddi_translations[i].trans2);
 290                 reg += 4;
 291         }
 292
 293         /* Choose a good default if VBT is badly populated */
 294         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 295             hdmi_level >= n_hdmi_entries)
 296                 hdmi_level = hdmi_default_entry;
 297
 298         /* Entry 9 is for HDMI: */
 299         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
 300         reg += 4;
 301         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 302         reg += 4;
 303 }
 304
 305 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 306  * mode and port E for FDI.
 307  */
 308 void intel_prepare_ddi(struct drm_device *dev)
 309 {
 310         int port;
 311
 312         if (!HAS_DDI(dev))
 313                 return;
 314
 315         for (port = PORT_A; port <= PORT_E; port++)
 316                 intel_prepare_ddi_buffers(dev, port);
 317 }
 318
 319 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 320                                     enum port port)
 321 {
 322         uint32_t reg = DDI_BUF_CTL(port);
 323         int i;
 324
 325         for (i = 0; i < 16; i++) {
 326                 udelay(1);
 327                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 328                         return;
 329         }
 330         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 331 }
 332
 333 /* Starting with Haswell, different DDI ports can work in FDI mode for
 334  * connection to the PCH-located connectors. For this, it is necessary to train
 335  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 336  *
 337  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 338  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 339  * DDI A (which is used for eDP)
 340  */
 341
 342 void hsw_fdi_link_train(struct drm_crtc *crtc)
 343 {
 344         struct drm_device *dev = crtc->dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 347         u32 temp, i, rx_ctl_val;
 348
 349         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 350          * mode set "sequence for CRT port" document:
 351          * - TP1 to TP2 time with the default value
 352          * - FDI delay to 90h
 353          *
 354          * WaFDIAutoLinkSetTimingOverrride:hsw
 355          */
 356         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 357                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 358                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 359
 360         /* Enable the PCH Receiver FDI PLL */
 361         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 362                      FDI_RX_PLL_ENABLE |
 363                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 364         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 365         POSTING_READ(_FDI_RXA_CTL);
 366         udelay(220);
 367
 368         /* Switch from Rawclk to PCDclk */
 369         rx_ctl_val |= FDI_PCDCLK;
 370         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 371
 372         /* Configure Port Clock Select */
 373         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 374         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 375
 376         /* Start the training iterating through available voltages and emphasis,
 377          * testing each value twice. */
 378         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 379                 /* Configure DP_TP_CTL with auto-training */
 380                 I915_WRITE(DP_TP_CTL(PORT_E),
 381                                         DP_TP_CTL_FDI_AUTOTRAIN |
 382                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 383                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 384                                         DP_TP_CTL_ENABLE);
 385
 386                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 387                  * DDI E does not support port reversal, the functionality is
 388                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 389                  * port reversal bit */
 390                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 391                            DDI_BUF_CTL_ENABLE |
 392                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 393                            DDI_BUF_TRANS_SELECT(i / 2));
 394                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 395
 396                 udelay(600);
 397
 398                 /* Program PCH FDI Receiver TU */
 399                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 400
 401                 /* Enable PCH FDI Receiver with auto-training */
 402                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 403                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 404                 POSTING_READ(_FDI_RXA_CTL);
 405
 406                 /* Wait for FDI receiver lane calibration */
 407                 udelay(30);
 408
 409                 /* Unset FDI_RX_MISC pwrdn lanes */
 410                 temp = I915_READ(_FDI_RXA_MISC);
 411                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 412                 I915_WRITE(_FDI_RXA_MISC, temp);
 413                 POSTING_READ(_FDI_RXA_MISC);
 414
 415                 /* Wait for FDI auto training time */
 416                 udelay(5);
 417
 418                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 419                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 420                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 421
 422                         /* Enable normal pixel sending for FDI */
 423                         I915_WRITE(DP_TP_CTL(PORT_E),
 424                                    DP_TP_CTL_FDI_AUTOTRAIN |
 425                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 426                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 427                                    DP_TP_CTL_ENABLE);
 428
 429                         return;
 430                 }
 431
 432                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 433                 temp &= ~DDI_BUF_CTL_ENABLE;
 434                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 435                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 436
 437                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 438                 temp = I915_READ(DP_TP_CTL(PORT_E));
 439                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 440                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 441                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 442                 POSTING_READ(DP_TP_CTL(PORT_E));
 443
 444                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 445
 446                 rx_ctl_val &= ~FDI_RX_ENABLE;
 447                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 448                 POSTING_READ(_FDI_RXA_CTL);
 449
 450                 /* Reset FDI_RX_MISC pwrdn lanes */
 451                 temp = I915_READ(_FDI_RXA_MISC);
 452                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 453                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 454                 I915_WRITE(_FDI_RXA_MISC, temp);
 455                 POSTING_READ(_FDI_RXA_MISC);
 456         }
 457
 458         DRM_ERROR("FDI link training failed!\n");
 459 }
 460
 461 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 462 {
 463         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 464         struct intel_digital_port *intel_dig_port =
 465                 enc_to_dig_port(&encoder->base);
 466
 467         intel_dp->DP = intel_dig_port->saved_port_bits |
 468                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 469         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 470
 471 }
 472
 473 static struct intel_encoder *
 474 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 475 {
 476         struct drm_device *dev = crtc->dev;
 477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 478         struct intel_encoder *intel_encoder, *ret = NULL;
 479         int num_encoders = 0;
 480
 481         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 482                 ret = intel_encoder;
 483                 num_encoders++;
 484         }
 485
 486         if (num_encoders != 1)
 487                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 488                      pipe_name(intel_crtc->pipe));
 489
 490         BUG_ON(ret == NULL);
 491         return ret;
 492 }
 493
 494 static struct intel_encoder *
 495 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 496 {
 497         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 498         struct intel_encoder *ret = NULL;
 499         struct drm_atomic_state *state;
 500         int num_encoders = 0;
 501         int i;
 502
 503         state = crtc_state->base.state;
 504
 505         for (i = 0; i < state->num_connector; i++) {
 506                 if (!state->connectors[i] ||
 507                     state->connector_states[i]->crtc != crtc_state->base.crtc)
 508                         continue;
 509
 510                 ret = to_intel_encoder(state->connector_states[i]->best_encoder);
 511                 num_encoders++;
 512         }
 513
 514         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 515              pipe_name(crtc->pipe));
 516
 517         BUG_ON(ret == NULL);
 518         return ret;
 519 }
 520
 521 #define LC_FREQ 2700
 522 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 523
 524 #define P_MIN 2
 525 #define P_MAX 64
 526 #define P_INC 2
 527
 528 /* Constraints for PLL good behavior */
 529 #define REF_MIN 48
 530 #define REF_MAX 400
 531 #define VCO_MIN 2400
 532 #define VCO_MAX 4800
 533
 534 #define abs_diff(a, b) ({                       \
 535         typeof(a) __a = (a);                    \
 536         typeof(b) __b = (b);                    \
 537         (void) (&__a == &__b);                  \
 538         __a > __b ? (__a - __b) : (__b - __a); })
 539
 540 struct wrpll_rnp {
 541         unsigned p, n2, r2;
 542 };
 543
 544 static unsigned wrpll_get_budget_for_freq(int clock)
 545 {
 546         unsigned budget;
 547
 548         switch (clock) {
 549         case 25175000:
 550         case 25200000:
 551         case 27000000:
 552         case 27027000:
 553         case 37762500:
 554         case 37800000:
 555         case 40500000:
 556         case 40541000:
 557         case 54000000:
 558         case 54054000:
 559         case 59341000:
 560         case 59400000:
 561         case 72000000:
 562         case 74176000:
 563         case 74250000:
 564         case 81000000:
 565         case 81081000:
 566         case 89012000:
 567         case 89100000:
 568         case 108000000:
 569         case 108108000:
 570         case 111264000:
 571         case 111375000:
 572         case 148352000:
 573         case 148500000:
 574         case 162000000:
 575         case 162162000:
 576         case 222525000:
 577         case 222750000:
 578         case 296703000:
 579         case 297000000:
 580                 budget = 0;
 581                 break;
 582         case 233500000:
 583         case 245250000:
 584         case 247750000:
 585         case 253250000:
 586         case 298000000:
 587                 budget = 1500;
 588                 break;
 589         case 169128000:
 590         case 169500000:
 591         case 179500000:
 592         case 202000000:
 593                 budget = 2000;
 594                 break;
 595         case 256250000:
 596         case 262500000:
 597         case 270000000:
 598         case 272500000:
 599         case 273750000:
 600         case 280750000:
 601         case 281250000:
 602         case 286000000:
 603         case 291750000:
 604                 budget = 4000;
 605                 break;
 606         case 267250000:
 607         case 268500000:
 608                 budget = 5000;
 609                 break;
 610         default:
 611                 budget = 1000;
 612                 break;
 613         }
 614
 615         return budget;
 616 }
 617
 618 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 619                              unsigned r2, unsigned n2, unsigned p,
 620                              struct wrpll_rnp *best)
 621 {
 622         uint64_t a, b, c, d, diff, diff_best;
 623
 624         /* No best (r,n,p) yet */
 625         if (best->p == 0) {
 626                 best->p = p;
 627                 best->n2 = n2;
 628                 best->r2 = r2;
 629                 return;
 630         }
 631
 632         /*
 633          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 634          * freq2k.
 635          *
 636          * delta = 1e6 *
 637          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 638          *         freq2k;
 639          *
 640          * and we would like delta <= budget.
 641          *
 642          * If the discrepancy is above the PPM-based budget, always prefer to
 643          * improve upon the previous solution.  However, if you're within the
 644          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 645          */
 646         a = freq2k * budget * p * r2;
 647         b = freq2k * budget * best->p * best->r2;
 648         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 649         diff_best = abs_diff(freq2k * best->p * best->r2,
 650                              LC_FREQ_2K * best->n2);
 651         c = 1000000 * diff;
 652         d = 1000000 * diff_best;
 653
 654         if (a < c && b < d) {
 655                 /* If both are above the budget, pick the closer */
 656                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 657                         best->p = p;
 658                         best->n2 = n2;
 659                         best->r2 = r2;
 660                 }
 661         } else if (a >= c && b < d) {
 662                 /* If A is below the threshold but B is above it?  Update. */
 663                 best->p = p;
 664                 best->n2 = n2;
 665                 best->r2 = r2;
 666         } else if (a >= c && b >= d) {
 667                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 668                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 669                         best->p = p;
 670                         best->n2 = n2;
 671                         best->r2 = r2;
 672                 }
 673         }
 674         /* Otherwise a < c && b >= d, do nothing */
 675 }
 676
 677 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 678                                      int reg)
 679 {
 680         int refclk = LC_FREQ;
 681         int n, p, r;
 682         u32 wrpll;
 683
 684         wrpll = I915_READ(reg);
 685         switch (wrpll & WRPLL_PLL_REF_MASK) {
 686         case WRPLL_PLL_SSC:
 687         case WRPLL_PLL_NON_SSC:
 688                 /*
 689                  * We could calculate spread here, but our checking
 690                  * code only cares about 5% accuracy, and spread is a max of
 691                  * 0.5% downspread.
 692                  */
 693                 refclk = 135;
 694                 break;
 695         case WRPLL_PLL_LCPLL:
 696                 refclk = LC_FREQ;
 697                 break;
 698         default:
 699                 WARN(1, "bad wrpll refclk\n");
 700                 return 0;
 701         }
 702
 703         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 704         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 705         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 706
 707         /* Convert to KHz, p & r have a fixed point portion */
 708         return (refclk * n * 100) / (p * r);
 709 }
 710
 711 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 712                                uint32_t dpll)
 713 {
 714         uint32_t cfgcr1_reg, cfgcr2_reg;
 715         uint32_t cfgcr1_val, cfgcr2_val;
 716         uint32_t p0, p1, p2, dco_freq;
 717
 718         cfgcr1_reg = GET_CFG_CR1_REG(dpll);
 719         cfgcr2_reg = GET_CFG_CR2_REG(dpll);
 720
 721         cfgcr1_val = I915_READ(cfgcr1_reg);
 722         cfgcr2_val = I915_READ(cfgcr2_reg);
 723
 724         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 725         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 726
 727         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 728                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 729         else
 730                 p1 = 1;
 731
 732
 733         switch (p0) {
 734         case DPLL_CFGCR2_PDIV_1:
 735                 p0 = 1;
 736                 break;
 737         case DPLL_CFGCR2_PDIV_2:
 738                 p0 = 2;
 739                 break;
 740         case DPLL_CFGCR2_PDIV_3:
 741                 p0 = 3;
 742                 break;
 743         case DPLL_CFGCR2_PDIV_7:
 744                 p0 = 7;
 745                 break;
 746         }
 747
 748         switch (p2) {
 749         case DPLL_CFGCR2_KDIV_5:
 750                 p2 = 5;
 751                 break;
 752         case DPLL_CFGCR2_KDIV_2:
 753                 p2 = 2;
 754                 break;
 755         case DPLL_CFGCR2_KDIV_3:
 756                 p2 = 3;
 757                 break;
 758         case DPLL_CFGCR2_KDIV_1:
 759                 p2 = 1;
 760                 break;
 761         }
 762
 763         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 764
 765         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 766                 1000) / 0x8000;
 767
 768         return dco_freq / (p0 * p1 * p2 * 5);
 769 }
 770
 771
 772 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 773                                 struct intel_crtc_state *pipe_config)
 774 {
 775         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 776         int link_clock = 0;
 777         uint32_t dpll_ctl1, dpll;
 778
 779         dpll = pipe_config->ddi_pll_sel;
 780
 781         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 782
 783         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 784                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 785         } else {
 786                 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
 787                 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
 788
 789                 switch (link_clock) {
 790                 case DPLL_CRTL1_LINK_RATE_810:
 791                         link_clock = 81000;
 792                         break;
 793                 case DPLL_CRTL1_LINK_RATE_1080:
 794                         link_clock = 108000;
 795                         break;
 796                 case DPLL_CRTL1_LINK_RATE_1350:
 797                         link_clock = 135000;
 798                         break;
 799                 case DPLL_CRTL1_LINK_RATE_1620:
 800                         link_clock = 162000;
 801                         break;
 802                 case DPLL_CRTL1_LINK_RATE_2160:
 803                         link_clock = 216000;
 804                         break;
 805                 case DPLL_CRTL1_LINK_RATE_2700:
 806                         link_clock = 270000;
 807                         break;
 808                 default:
 809                         WARN(1, "Unsupported link rate\n");
 810                         break;
 811                 }
 812                 link_clock *= 2;
 813         }
 814
 815         pipe_config->port_clock = link_clock;
 816
 817         if (pipe_config->has_dp_encoder)
 818                 pipe_config->base.adjusted_mode.crtc_clock =
 819                         intel_dotclock_calculate(pipe_config->port_clock,
 820                                                  &pipe_config->dp_m_n);
 821         else
 822                 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 823 }
 824
 825 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 826                               struct intel_crtc_state *pipe_config)
 827 {
 828         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 829         int link_clock = 0;
 830         u32 val, pll;
 831
 832         val = pipe_config->ddi_pll_sel;
 833         switch (val & PORT_CLK_SEL_MASK) {
 834         case PORT_CLK_SEL_LCPLL_810:
 835                 link_clock = 81000;
 836                 break;
 837         case PORT_CLK_SEL_LCPLL_1350:
 838                 link_clock = 135000;
 839                 break;
 840         case PORT_CLK_SEL_LCPLL_2700:
 841                 link_clock = 270000;
 842                 break;
 843         case PORT_CLK_SEL_WRPLL1:
 844                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 845                 break;
 846         case PORT_CLK_SEL_WRPLL2:
 847                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 848                 break;
 849         case PORT_CLK_SEL_SPLL:
 850                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 851                 if (pll == SPLL_PLL_FREQ_810MHz)
 852                         link_clock = 81000;
 853                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 854                         link_clock = 135000;
 855                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 856                         link_clock = 270000;
 857                 else {
 858                         WARN(1, "bad spll freq\n");
 859                         return;
 860                 }
 861                 break;
 862         default:
 863                 WARN(1, "bad port clock sel\n");
 864                 return;
 865         }
 866
 867         pipe_config->port_clock = link_clock * 2;
 868
 869         if (pipe_config->has_pch_encoder)
 870                 pipe_config->base.adjusted_mode.crtc_clock =
 871                         intel_dotclock_calculate(pipe_config->port_clock,
 872                                                  &pipe_config->fdi_m_n);
 873         else if (pipe_config->has_dp_encoder)
 874                 pipe_config->base.adjusted_mode.crtc_clock =
 875                         intel_dotclock_calculate(pipe_config->port_clock,
 876                                                  &pipe_config->dp_m_n);
 877         else
 878                 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 879 }
 880
 881 void intel_ddi_clock_get(struct intel_encoder *encoder,
 882                          struct intel_crtc_state *pipe_config)
 883 {
 884         struct drm_device *dev = encoder->base.dev;
 885
 886         if (INTEL_INFO(dev)->gen <= 8)
 887                 hsw_ddi_clock_get(encoder, pipe_config);
 888         else
 889                 skl_ddi_clock_get(encoder, pipe_config);
 890 }
 891
 892 static void
 893 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 894                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 895 {
 896         uint64_t freq2k;
 897         unsigned p, n2, r2;
 898         struct wrpll_rnp best = { 0, 0, 0 };
 899         unsigned budget;
 900
 901         freq2k = clock / 100;
 902
 903         budget = wrpll_get_budget_for_freq(clock);
 904
 905         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 906          * and directly pass the LC PLL to it. */
 907         if (freq2k == 5400000) {
 908                 *n2_out = 2;
 909                 *p_out = 1;
 910                 *r2_out = 2;
 911                 return;
 912         }
 913
 914         /*
 915          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 916          * the WR PLL.
 917          *
 918          * We want R so that REF_MIN <= Ref <= REF_MAX.
 919          * Injecting R2 = 2 * R gives:
 920          *   REF_MAX * r2 > LC_FREQ * 2 and
 921          *   REF_MIN * r2 < LC_FREQ * 2
 922          *
 923          * Which means the desired boundaries for r2 are:
 924          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 925          *
 926          */
 927         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 928              r2 <= LC_FREQ * 2 / REF_MIN;
 929              r2++) {
 930
 931                 /*
 932                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 933                  *
 934                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 935                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 936                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 937                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 938                  *
 939                  * Which means the desired boundaries for n2 are:
 940                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 941                  */
 942                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 943                      n2 <= VCO_MAX * r2 / LC_FREQ;
 944                      n2++) {
 945
 946                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 947                                 wrpll_update_rnp(freq2k, budget,
 948                                                  r2, n2, p, &best);
 949                 }
 950         }
 951
 952         *n2_out = best.n2;
 953         *p_out = best.p;
 954         *r2_out = best.r2;
 955 }
 956
 957 static bool
 958 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 959                    struct intel_crtc_state *crtc_state,
 960                    struct intel_encoder *intel_encoder,
 961                    int clock)
 962 {
 963         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 964                 struct intel_shared_dpll *pll;
 965                 uint32_t val;
 966                 unsigned p, n2, r2;
 967
 968                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 969
 970                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 971                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 972                       WRPLL_DIVIDER_POST(p);
 973
 974                 crtc_state->dpll_hw_state.wrpll = val;
 975
 976                 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
 977                 if (pll == NULL) {
 978                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 979                                          pipe_name(intel_crtc->pipe));
 980                         return false;
 981                 }
 982
 983                 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 984         }
 985
 986         return true;
 987 }
 988
 989 struct skl_wrpll_params {
 990         uint32_t        dco_fraction;
 991         uint32_t        dco_integer;
 992         uint32_t        qdiv_ratio;
 993         uint32_t        qdiv_mode;
 994         uint32_t        kdiv;
 995         uint32_t        pdiv;
 996         uint32_t        central_freq;
 997 };
 998
 999 static void
1000 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1001                         struct skl_wrpll_params *wrpll_params)
1002 {
1003         uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1004         uint64_t dco_central_freq[3] = {8400000000ULL,
1005                                         9000000000ULL,
1006                                         9600000000ULL};
1007         uint32_t min_dco_deviation = 400;
1008         uint32_t min_dco_index = 3;
1009         uint32_t P0[4] = {1, 2, 3, 7};
1010         uint32_t P2[4] = {1, 2, 3, 5};
1011         bool found = false;
1012         uint32_t candidate_p = 0;
1013         uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1014         uint32_t candidate_p2[3] = {0};
1015         uint32_t dco_central_freq_deviation[3];
1016         uint32_t i, P1, k, dco_count;
1017         bool retry_with_odd = false;
1018         uint64_t dco_freq;
1019
1020         /* Determine P0, P1 or P2 */
1021         for (dco_count = 0; dco_count < 3; dco_count++) {
1022                 found = false;
1023                 candidate_p =
1024                         div64_u64(dco_central_freq[dco_count], afe_clock);
1025                 if (retry_with_odd == false)
1026                         candidate_p = (candidate_p % 2 == 0 ?
1027                                 candidate_p : candidate_p + 1);
1028
1029                 for (P1 = 1; P1 < candidate_p; P1++) {
1030                         for (i = 0; i < 4; i++) {
1031                                 if (!(P0[i] != 1 || P1 == 1))
1032                                         continue;
1033
1034                                 for (k = 0; k < 4; k++) {
1035                                         if (P1 != 1 && P2[k] != 2)
1036                                                 continue;
1037
1038                                         if (candidate_p == P0[i] * P1 * P2[k]) {
1039                                                 /* Found possible P0, P1, P2 */
1040                                                 found = true;
1041                                                 candidate_p0[dco_count] = P0[i];
1042                                                 candidate_p1[dco_count] = P1;
1043                                                 candidate_p2[dco_count] = P2[k];
1044                                                 goto found;
1045                                         }
1046
1047                                 }
1048                         }
1049                 }
1050
1051 found:
1052                 if (found) {
1053                         dco_central_freq_deviation[dco_count] =
1054                                 div64_u64(10000 *
1055                                           abs_diff((candidate_p * afe_clock),
1056                                                    dco_central_freq[dco_count]),
1057                                           dco_central_freq[dco_count]);
1058
1059                         if (dco_central_freq_deviation[dco_count] <
1060                                 min_dco_deviation) {
1061                                 min_dco_deviation =
1062                                         dco_central_freq_deviation[dco_count];
1063                                 min_dco_index = dco_count;
1064                         }
1065                 }
1066
1067                 if (min_dco_index > 2 && dco_count == 2) {
1068                         retry_with_odd = true;
1069                         dco_count = 0;
1070                 }
1071         }
1072
1073         if (min_dco_index > 2) {
1074                 WARN(1, "No valid values found for the given pixel clock\n");
1075         } else {
1076                  wrpll_params->central_freq = dco_central_freq[min_dco_index];
1077
1078                  switch (dco_central_freq[min_dco_index]) {
1079                  case 9600000000ULL:
1080                         wrpll_params->central_freq = 0;
1081                         break;
1082                  case 9000000000ULL:
1083                         wrpll_params->central_freq = 1;
1084                         break;
1085                  case 8400000000ULL:
1086                         wrpll_params->central_freq = 3;
1087                  }
1088
1089                  switch (candidate_p0[min_dco_index]) {
1090                  case 1:
1091                         wrpll_params->pdiv = 0;
1092                         break;
1093                  case 2:
1094                         wrpll_params->pdiv = 1;
1095                         break;
1096                  case 3:
1097                         wrpll_params->pdiv = 2;
1098                         break;
1099                  case 7:
1100                         wrpll_params->pdiv = 4;
1101                         break;
1102                  default:
1103                         WARN(1, "Incorrect PDiv\n");
1104                  }
1105
1106                  switch (candidate_p2[min_dco_index]) {
1107                  case 5:
1108                         wrpll_params->kdiv = 0;
1109                         break;
1110                  case 2:
1111                         wrpll_params->kdiv = 1;
1112                         break;
1113                  case 3:
1114                         wrpll_params->kdiv = 2;
1115                         break;
1116                  case 1:
1117                         wrpll_params->kdiv = 3;
1118                         break;
1119                  default:
1120                         WARN(1, "Incorrect KDiv\n");
1121                  }
1122
1123                  wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1124                  wrpll_params->qdiv_mode =
1125                         (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1126
1127                  dco_freq = candidate_p0[min_dco_index] *
1128                          candidate_p1[min_dco_index] *
1129                          candidate_p2[min_dco_index] * afe_clock;
1130
1131                 /*
1132                 * Intermediate values are in Hz.
1133                 * Divide by MHz to match bsepc
1134                 */
1135                  wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1136                  wrpll_params->dco_fraction =
1137                          div_u64(((div_u64(dco_freq, 24) -
1138                                    wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1139
1140         }
1141 }
1142
1143
1144 static bool
1145 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1146                    struct intel_crtc_state *crtc_state,
1147                    struct intel_encoder *intel_encoder,
1148                    int clock)
1149 {
1150         struct intel_shared_dpll *pll;
1151         uint32_t ctrl1, cfgcr1, cfgcr2;
1152
1153         /*
1154          * See comment in intel_dpll_hw_state to understand why we always use 0
1155          * as the DPLL id in this function.
1156          */
1157
1158         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1159
1160         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1161                 struct skl_wrpll_params wrpll_params = { 0, };
1162
1163                 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1164
1165                 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1166
1167                 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1168                          DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1169                          wrpll_params.dco_integer;
1170
1171                 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1172                          DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1173                          DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1174                          DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1175                          wrpll_params.central_freq;
1176         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1177                 struct drm_encoder *encoder = &intel_encoder->base;
1178                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1179
1180                 switch (intel_dp->link_bw) {
1181                 case DP_LINK_BW_1_62:
1182                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1183                         break;
1184                 case DP_LINK_BW_2_7:
1185                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1186                         break;
1187                 case DP_LINK_BW_5_4:
1188                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1189                         break;
1190                 }
1191
1192                 cfgcr1 = cfgcr2 = 0;
1193         } else /* eDP */
1194                 return true;
1195
1196         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1197         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1198         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1199
1200         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1201         if (pll == NULL) {
1202                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1203                                  pipe_name(intel_crtc->pipe));
1204                 return false;
1205         }
1206
1207         /* shared DPLL id 0 is DPLL 1 */
1208         crtc_state->ddi_pll_sel = pll->id + 1;
1209
1210         return true;
1211 }
1212
1213 /*
1214  * Tries to find a *shared* PLL for the CRTC and store it in
1215  * intel_crtc->ddi_pll_sel.
1216  *
1217  * For private DPLLs, compute_config() should do the selection for us. This
1218  * function should be folded into compute_config() eventually.
1219  */
1220 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1221                           struct intel_crtc_state *crtc_state)
1222 {
1223         struct drm_device *dev = intel_crtc->base.dev;
1224         struct intel_encoder *intel_encoder =
1225                 intel_ddi_get_crtc_new_encoder(crtc_state);
1226         int clock = crtc_state->port_clock;
1227
1228         if (IS_SKYLAKE(dev))
1229                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1230                                           intel_encoder, clock);
1231         else
1232                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1233                                           intel_encoder, clock);
1234 }
1235
1236 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1237 {
1238         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1240         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1241         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1242         int type = intel_encoder->type;
1243         uint32_t temp;
1244
1245         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1246                 temp = TRANS_MSA_SYNC_CLK;
1247                 switch (intel_crtc->config->pipe_bpp) {
1248                 case 18:
1249                         temp |= TRANS_MSA_6_BPC;
1250                         break;
1251                 case 24:
1252                         temp |= TRANS_MSA_8_BPC;
1253                         break;
1254                 case 30:
1255                         temp |= TRANS_MSA_10_BPC;
1256                         break;
1257                 case 36:
1258                         temp |= TRANS_MSA_12_BPC;
1259                         break;
1260                 default:
1261                         BUG();
1262                 }
1263                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1264         }
1265 }
1266
1267 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1268 {
1269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1270         struct drm_device *dev = crtc->dev;
1271         struct drm_i915_private *dev_priv = dev->dev_private;
1272         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1273         uint32_t temp;
1274         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1275         if (state == true)
1276                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1277         else
1278                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1279         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1280 }
1281
1282 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1283 {
1284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1285         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1286         struct drm_encoder *encoder = &intel_encoder->base;
1287         struct drm_device *dev = crtc->dev;
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289         enum pipe pipe = intel_crtc->pipe;
1290         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1291         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1292         int type = intel_encoder->type;
1293         uint32_t temp;
1294
1295         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1296         temp = TRANS_DDI_FUNC_ENABLE;
1297         temp |= TRANS_DDI_SELECT_PORT(port);
1298
1299         switch (intel_crtc->config->pipe_bpp) {
1300         case 18:
1301                 temp |= TRANS_DDI_BPC_6;
1302                 break;
1303         case 24:
1304                 temp |= TRANS_DDI_BPC_8;
1305                 break;
1306         case 30:
1307                 temp |= TRANS_DDI_BPC_10;
1308                 break;
1309         case 36:
1310                 temp |= TRANS_DDI_BPC_12;
1311                 break;
1312         default:
1313                 BUG();
1314         }
1315
1316         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1317                 temp |= TRANS_DDI_PVSYNC;
1318         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1319                 temp |= TRANS_DDI_PHSYNC;
1320
1321         if (cpu_transcoder == TRANSCODER_EDP) {
1322                 switch (pipe) {
1323                 case PIPE_A:
1324                         /* On Haswell, can only use the always-on power well for
1325                          * eDP when not using the panel fitter, and when not
1326                          * using motion blur mitigation (which we don't
1327                          * support). */
1328                         if (IS_HASWELL(dev) &&
1329                             (intel_crtc->config->pch_pfit.enabled ||
1330                              intel_crtc->config->pch_pfit.force_thru))
1331                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1332                         else
1333                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1334                         break;
1335                 case PIPE_B:
1336                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1337                         break;
1338                 case PIPE_C:
1339                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1340                         break;
1341                 default:
1342                         BUG();
1343                         break;
1344                 }
1345         }
1346
1347         if (type == INTEL_OUTPUT_HDMI) {
1348                 if (intel_crtc->config->has_hdmi_sink)
1349                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1350                 else
1351                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1352
1353         } else if (type == INTEL_OUTPUT_ANALOG) {
1354                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1355                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1356
1357         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1358                    type == INTEL_OUTPUT_EDP) {
1359                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1360
1361                 if (intel_dp->is_mst) {
1362                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1363                 } else
1364                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1365
1366                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1367         } else if (type == INTEL_OUTPUT_DP_MST) {
1368                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1369
1370                 if (intel_dp->is_mst) {
1371                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1372                 } else
1373                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1374
1375                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1376         } else {
1377                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1378                      intel_encoder->type, pipe_name(pipe));
1379         }
1380
1381         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1382 }
1383
1384 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1385                                        enum transcoder cpu_transcoder)
1386 {
1387         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1388         uint32_t val = I915_READ(reg);
1389
1390         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1391         val |= TRANS_DDI_PORT_NONE;
1392         I915_WRITE(reg, val);
1393 }
1394
1395 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1396 {
1397         struct drm_device *dev = intel_connector->base.dev;
1398         struct drm_i915_private *dev_priv = dev->dev_private;
1399         struct intel_encoder *intel_encoder = intel_connector->encoder;
1400         int type = intel_connector->base.connector_type;
1401         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1402         enum pipe pipe = 0;
1403         enum transcoder cpu_transcoder;
1404         enum intel_display_power_domain power_domain;
1405         uint32_t tmp;
1406
1407         power_domain = intel_display_port_power_domain(intel_encoder);
1408         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1409                 return false;
1410
1411         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1412                 return false;
1413
1414         if (port == PORT_A)
1415                 cpu_transcoder = TRANSCODER_EDP;
1416         else
1417                 cpu_transcoder = (enum transcoder) pipe;
1418
1419         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1420
1421         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1422         case TRANS_DDI_MODE_SELECT_HDMI:
1423         case TRANS_DDI_MODE_SELECT_DVI:
1424                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1425
1426         case TRANS_DDI_MODE_SELECT_DP_SST:
1427                 if (type == DRM_MODE_CONNECTOR_eDP)
1428                         return true;
1429                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1430         case TRANS_DDI_MODE_SELECT_DP_MST:
1431                 /* if the transcoder is in MST state then
1432                  * connector isn't connected */
1433                 return false;
1434
1435         case TRANS_DDI_MODE_SELECT_FDI:
1436                 return (type == DRM_MODE_CONNECTOR_VGA);
1437
1438         default:
1439                 return false;
1440         }
1441 }
1442
1443 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1444                             enum pipe *pipe)
1445 {
1446         struct drm_device *dev = encoder->base.dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         enum port port = intel_ddi_get_encoder_port(encoder);
1449         enum intel_display_power_domain power_domain;
1450         u32 tmp;
1451         int i;
1452
1453         power_domain = intel_display_port_power_domain(encoder);
1454         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1455                 return false;
1456
1457         tmp = I915_READ(DDI_BUF_CTL(port));
1458
1459         if (!(tmp & DDI_BUF_CTL_ENABLE))
1460                 return false;
1461
1462         if (port == PORT_A) {
1463                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1464
1465                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1466                 case TRANS_DDI_EDP_INPUT_A_ON:
1467                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1468                         *pipe = PIPE_A;
1469                         break;
1470                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1471                         *pipe = PIPE_B;
1472                         break;
1473                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1474                         *pipe = PIPE_C;
1475                         break;
1476                 }
1477
1478                 return true;
1479         } else {
1480                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1481                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1482
1483                         if ((tmp & TRANS_DDI_PORT_MASK)
1484                             == TRANS_DDI_SELECT_PORT(port)) {
1485                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1486                                         return false;
1487
1488                                 *pipe = i;
1489                                 return true;
1490                         }
1491                 }
1492         }
1493
1494         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1495
1496         return false;
1497 }
1498
1499 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1500 {
1501         struct drm_crtc *crtc = &intel_crtc->base;
1502         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1503         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1504         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1505         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1506
1507         if (cpu_transcoder != TRANSCODER_EDP)
1508                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1509                            TRANS_CLK_SEL_PORT(port));
1510 }
1511
1512 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1513 {
1514         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1515         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1516
1517         if (cpu_transcoder != TRANSCODER_EDP)
1518                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1519                            TRANS_CLK_SEL_DISABLED);
1520 }
1521
1522 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1523 {
1524         struct drm_encoder *encoder = &intel_encoder->base;
1525         struct drm_device *dev = encoder->dev;
1526         struct drm_i915_private *dev_priv = dev->dev_private;
1527         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1528         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1529         int type = intel_encoder->type;
1530
1531         if (type == INTEL_OUTPUT_EDP) {
1532                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1533                 intel_edp_panel_on(intel_dp);
1534         }
1535
1536         if (IS_SKYLAKE(dev)) {
1537                 uint32_t dpll = crtc->config->ddi_pll_sel;
1538                 uint32_t val;
1539
1540                 /*
1541                  * DPLL0 is used for eDP and is the only "private" DPLL (as
1542                  * opposed to shared) on SKL
1543                  */
1544                 if (type == INTEL_OUTPUT_EDP) {
1545                         WARN_ON(dpll != SKL_DPLL0);
1546
1547                         val = I915_READ(DPLL_CTRL1);
1548
1549                         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1550                                  DPLL_CTRL1_SSC(dpll) |
1551                                  DPLL_CRTL1_LINK_RATE_MASK(dpll));
1552                         val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
1553
1554                         I915_WRITE(DPLL_CTRL1, val);
1555                         POSTING_READ(DPLL_CTRL1);
1556                 }
1557
1558                 /* DDI -> PLL mapping  */
1559                 val = I915_READ(DPLL_CTRL2);
1560
1561                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1562                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1563                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1564                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1565
1566                 I915_WRITE(DPLL_CTRL2, val);
1567
1568         } else {
1569                 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1570                 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
1571         }
1572
1573         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1574                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1575
1576                 intel_ddi_init_dp_buf_reg(intel_encoder);
1577
1578                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1579                 intel_dp_start_link_train(intel_dp);
1580                 intel_dp_complete_link_train(intel_dp);
1581                 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1582                         intel_dp_stop_link_train(intel_dp);
1583         } else if (type == INTEL_OUTPUT_HDMI) {
1584                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1585
1586                 intel_hdmi->set_infoframes(encoder,
1587                                            crtc->config->has_hdmi_sink,
1588                                            &crtc->config->base.adjusted_mode);
1589         }
1590 }
1591
1592 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1593 {
1594         struct drm_encoder *encoder = &intel_encoder->base;
1595         struct drm_device *dev = encoder->dev;
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1598         int type = intel_encoder->type;
1599         uint32_t val;
1600         bool wait = false;
1601
1602         val = I915_READ(DDI_BUF_CTL(port));
1603         if (val & DDI_BUF_CTL_ENABLE) {
1604                 val &= ~DDI_BUF_CTL_ENABLE;
1605                 I915_WRITE(DDI_BUF_CTL(port), val);
1606                 wait = true;
1607         }
1608
1609         val = I915_READ(DP_TP_CTL(port));
1610         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1611         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1612         I915_WRITE(DP_TP_CTL(port), val);
1613
1614         if (wait)
1615                 intel_wait_ddi_buf_idle(dev_priv, port);
1616
1617         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1618                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1619                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1620                 intel_edp_panel_vdd_on(intel_dp);
1621                 intel_edp_panel_off(intel_dp);
1622         }
1623
1624         if (IS_SKYLAKE(dev))
1625                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1626                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1627         else
1628                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1629 }
1630
1631 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1632 {
1633         struct drm_encoder *encoder = &intel_encoder->base;
1634         struct drm_crtc *crtc = encoder->crtc;
1635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636         struct drm_device *dev = encoder->dev;
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1639         int type = intel_encoder->type;
1640
1641         if (type == INTEL_OUTPUT_HDMI) {
1642                 struct intel_digital_port *intel_dig_port =
1643                         enc_to_dig_port(encoder);
1644
1645                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1646                  * are ignored so nothing special needs to be done besides
1647                  * enabling the port.
1648                  */
1649                 I915_WRITE(DDI_BUF_CTL(port),
1650                            intel_dig_port->saved_port_bits |
1651                            DDI_BUF_CTL_ENABLE);
1652         } else if (type == INTEL_OUTPUT_EDP) {
1653                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1654
1655                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1656                         intel_dp_stop_link_train(intel_dp);
1657
1658                 intel_edp_backlight_on(intel_dp);
1659                 intel_psr_enable(intel_dp);
1660                 intel_edp_drrs_enable(intel_dp);
1661         }
1662
1663         if (intel_crtc->config->has_audio) {
1664                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1665                 intel_audio_codec_enable(intel_encoder);
1666         }
1667 }
1668
1669 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1670 {
1671         struct drm_encoder *encoder = &intel_encoder->base;
1672         struct drm_crtc *crtc = encoder->crtc;
1673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1674         int type = intel_encoder->type;
1675         struct drm_device *dev = encoder->dev;
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677
1678         if (intel_crtc->config->has_audio) {
1679                 intel_audio_codec_disable(intel_encoder);
1680                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1681         }
1682
1683         if (type == INTEL_OUTPUT_EDP) {
1684                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1685
1686                 intel_edp_drrs_disable(intel_dp);
1687                 intel_psr_disable(intel_dp);
1688                 intel_edp_backlight_off(intel_dp);
1689         }
1690 }
1691
1692 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1693                                struct intel_shared_dpll *pll)
1694 {
1695         I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1696         POSTING_READ(WRPLL_CTL(pll->id));
1697         udelay(20);
1698 }
1699
1700 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1701                                 struct intel_shared_dpll *pll)
1702 {
1703         uint32_t val;
1704
1705         val = I915_READ(WRPLL_CTL(pll->id));
1706         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1707         POSTING_READ(WRPLL_CTL(pll->id));
1708 }
1709
1710 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1711                                      struct intel_shared_dpll *pll,
1712                                      struct intel_dpll_hw_state *hw_state)
1713 {
1714         uint32_t val;
1715
1716         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1717                 return false;
1718
1719         val = I915_READ(WRPLL_CTL(pll->id));
1720         hw_state->wrpll = val;
1721
1722         return val & WRPLL_PLL_ENABLE;
1723 }
1724
1725 static const char * const hsw_ddi_pll_names[] = {
1726         "WRPLL 1",
1727         "WRPLL 2",
1728 };
1729
1730 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1731 {
1732         int i;
1733
1734         dev_priv->num_shared_dpll = 2;
1735
1736         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1737                 dev_priv->shared_dplls[i].id = i;
1738                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1739                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1740                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1741                 dev_priv->shared_dplls[i].get_hw_state =
1742                         hsw_ddi_pll_get_hw_state;
1743         }
1744 }
1745
1746 static const char * const skl_ddi_pll_names[] = {
1747         "DPLL 1",
1748         "DPLL 2",
1749         "DPLL 3",
1750 };
1751
1752 struct skl_dpll_regs {
1753         u32 ctl, cfgcr1, cfgcr2;
1754 };
1755
1756 /* this array is indexed by the *shared* pll id */
1757 static const struct skl_dpll_regs skl_dpll_regs[3] = {
1758         {
1759                 /* DPLL 1 */
1760                 .ctl = LCPLL2_CTL,
1761                 .cfgcr1 = DPLL1_CFGCR1,
1762                 .cfgcr2 = DPLL1_CFGCR2,
1763         },
1764         {
1765                 /* DPLL 2 */
1766                 .ctl = WRPLL_CTL1,
1767                 .cfgcr1 = DPLL2_CFGCR1,
1768                 .cfgcr2 = DPLL2_CFGCR2,
1769         },
1770         {
1771                 /* DPLL 3 */
1772                 .ctl = WRPLL_CTL2,
1773                 .cfgcr1 = DPLL3_CFGCR1,
1774                 .cfgcr2 = DPLL3_CFGCR2,
1775         },
1776 };
1777
1778 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1779                                struct intel_shared_dpll *pll)
1780 {
1781         uint32_t val;
1782         unsigned int dpll;
1783         const struct skl_dpll_regs *regs = skl_dpll_regs;
1784
1785         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1786         dpll = pll->id + 1;
1787
1788         val = I915_READ(DPLL_CTRL1);
1789
1790         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1791                  DPLL_CRTL1_LINK_RATE_MASK(dpll));
1792         val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1793
1794         I915_WRITE(DPLL_CTRL1, val);
1795         POSTING_READ(DPLL_CTRL1);
1796
1797         I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1798         I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1799         POSTING_READ(regs[pll->id].cfgcr1);
1800         POSTING_READ(regs[pll->id].cfgcr2);
1801
1802         /* the enable bit is always bit 31 */
1803         I915_WRITE(regs[pll->id].ctl,
1804                    I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1805
1806         if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1807                 DRM_ERROR("DPLL %d not locked\n", dpll);
1808 }
1809
1810 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1811                                 struct intel_shared_dpll *pll)
1812 {
1813         const struct skl_dpll_regs *regs = skl_dpll_regs;
1814
1815         /* the enable bit is always bit 31 */
1816         I915_WRITE(regs[pll->id].ctl,
1817                    I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1818         POSTING_READ(regs[pll->id].ctl);
1819 }
1820
1821 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1822                                      struct intel_shared_dpll *pll,
1823                                      struct intel_dpll_hw_state *hw_state)
1824 {
1825         uint32_t val;
1826         unsigned int dpll;
1827         const struct skl_dpll_regs *regs = skl_dpll_regs;
1828
1829         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1830                 return false;
1831
1832         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1833         dpll = pll->id + 1;
1834
1835         val = I915_READ(regs[pll->id].ctl);
1836         if (!(val & LCPLL_PLL_ENABLE))
1837                 return false;
1838
1839         val = I915_READ(DPLL_CTRL1);
1840         hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1841
1842         /* avoid reading back stale values if HDMI mode is not enabled */
1843         if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1844                 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1845                 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1846         }
1847
1848         return true;
1849 }
1850
1851 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1852 {
1853         int i;
1854
1855         dev_priv->num_shared_dpll = 3;
1856
1857         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1858                 dev_priv->shared_dplls[i].id = i;
1859                 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1860                 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1861                 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1862                 dev_priv->shared_dplls[i].get_hw_state =
1863                         skl_ddi_pll_get_hw_state;
1864         }
1865 }
1866
1867 void intel_ddi_pll_init(struct drm_device *dev)
1868 {
1869         struct drm_i915_private *dev_priv = dev->dev_private;
1870         uint32_t val = I915_READ(LCPLL_CTL);
1871
1872         if (IS_SKYLAKE(dev))
1873                 skl_shared_dplls_init(dev_priv);
1874         else
1875                 hsw_shared_dplls_init(dev_priv);
1876
1877         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1878                       dev_priv->display.get_display_clock_speed(dev));
1879
1880         if (IS_SKYLAKE(dev)) {
1881                 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1882                         DRM_ERROR("LCPLL1 is disabled\n");
1883         } else {
1884                 /*
1885                  * The LCPLL register should be turned on by the BIOS. For now
1886                  * let's just check its state and print errors in case
1887                  * something is wrong.  Don't even try to turn it on.
1888                  */
1889
1890                 if (val & LCPLL_CD_SOURCE_FCLK)
1891                         DRM_ERROR("CDCLK source is not LCPLL\n");
1892
1893                 if (val & LCPLL_PLL_DISABLE)
1894                         DRM_ERROR("LCPLL is disabled\n");
1895         }
1896 }
1897
1898 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1899 {
1900         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1901         struct intel_dp *intel_dp = &intel_dig_port->dp;
1902         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1903         enum port port = intel_dig_port->port;
1904         uint32_t val;
1905         bool wait = false;
1906
1907         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1908                 val = I915_READ(DDI_BUF_CTL(port));
1909                 if (val & DDI_BUF_CTL_ENABLE) {
1910                         val &= ~DDI_BUF_CTL_ENABLE;
1911                         I915_WRITE(DDI_BUF_CTL(port), val);
1912                         wait = true;
1913                 }
1914
1915                 val = I915_READ(DP_TP_CTL(port));
1916                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1917                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1918                 I915_WRITE(DP_TP_CTL(port), val);
1919                 POSTING_READ(DP_TP_CTL(port));
1920
1921                 if (wait)
1922                         intel_wait_ddi_buf_idle(dev_priv, port);
1923         }
1924
1925         val = DP_TP_CTL_ENABLE |
1926               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1927         if (intel_dp->is_mst)
1928                 val |= DP_TP_CTL_MODE_MST;
1929         else {
1930                 val |= DP_TP_CTL_MODE_SST;
1931                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1932                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1933         }
1934         I915_WRITE(DP_TP_CTL(port), val);
1935         POSTING_READ(DP_TP_CTL(port));
1936
1937         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1938         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1939         POSTING_READ(DDI_BUF_CTL(port));
1940
1941         udelay(600);
1942 }
1943
1944 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1945 {
1946         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1947         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1948         uint32_t val;
1949
1950         intel_ddi_post_disable(intel_encoder);
1951
1952         val = I915_READ(_FDI_RXA_CTL);
1953         val &= ~FDI_RX_ENABLE;
1954         I915_WRITE(_FDI_RXA_CTL, val);
1955
1956         val = I915_READ(_FDI_RXA_MISC);
1957         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1958         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1959         I915_WRITE(_FDI_RXA_MISC, val);
1960
1961         val = I915_READ(_FDI_RXA_CTL);
1962         val &= ~FDI_PCDCLK;
1963         I915_WRITE(_FDI_RXA_CTL, val);
1964
1965         val = I915_READ(_FDI_RXA_CTL);
1966         val &= ~FDI_RX_PLL_ENABLE;
1967         I915_WRITE(_FDI_RXA_CTL, val);
1968 }
1969
1970 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1971 {
1972         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1973         int type = intel_dig_port->base.type;
1974
1975         if (type != INTEL_OUTPUT_DISPLAYPORT &&
1976             type != INTEL_OUTPUT_EDP &&
1977             type != INTEL_OUTPUT_UNKNOWN) {
1978                 return;
1979         }
1980
1981         intel_dp_hot_plug(intel_encoder);
1982 }
1983
1984 void intel_ddi_get_config(struct intel_encoder *encoder,
1985                           struct intel_crtc_state *pipe_config)
1986 {
1987         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1988         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1989         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1990         struct intel_hdmi *intel_hdmi;
1991         u32 temp, flags = 0;
1992
1993         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1994         if (temp & TRANS_DDI_PHSYNC)
1995                 flags |= DRM_MODE_FLAG_PHSYNC;
1996         else
1997                 flags |= DRM_MODE_FLAG_NHSYNC;
1998         if (temp & TRANS_DDI_PVSYNC)
1999                 flags |= DRM_MODE_FLAG_PVSYNC;
2000         else
2001                 flags |= DRM_MODE_FLAG_NVSYNC;
2002
2003         pipe_config->base.adjusted_mode.flags |= flags;
2004
2005         switch (temp & TRANS_DDI_BPC_MASK) {
2006         case TRANS_DDI_BPC_6:
2007                 pipe_config->pipe_bpp = 18;
2008                 break;
2009         case TRANS_DDI_BPC_8:
2010                 pipe_config->pipe_bpp = 24;
2011                 break;
2012         case TRANS_DDI_BPC_10:
2013                 pipe_config->pipe_bpp = 30;
2014                 break;
2015         case TRANS_DDI_BPC_12:
2016                 pipe_config->pipe_bpp = 36;
2017                 break;
2018         default:
2019                 break;
2020         }
2021
2022         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2023         case TRANS_DDI_MODE_SELECT_HDMI:
2024                 pipe_config->has_hdmi_sink = true;
2025                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2026
2027                 if (intel_hdmi->infoframe_enabled(&encoder->base))
2028                         pipe_config->has_infoframe = true;
2029                 break;
2030         case TRANS_DDI_MODE_SELECT_DVI:
2031         case TRANS_DDI_MODE_SELECT_FDI:
2032                 break;
2033         case TRANS_DDI_MODE_SELECT_DP_SST:
2034         case TRANS_DDI_MODE_SELECT_DP_MST:
2035                 pipe_config->has_dp_encoder = true;
2036                 intel_dp_get_m_n(intel_crtc, pipe_config);
2037                 break;
2038         default:
2039                 break;
2040         }
2041
2042         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2043                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2044                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2045                         pipe_config->has_audio = true;
2046         }
2047
2048         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2049             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2050                 /*
2051                  * This is a big fat ugly hack.
2052                  *
2053                  * Some machines in UEFI boot mode provide us a VBT that has 18
2054                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2055                  * unknown we fail to light up. Yet the same BIOS boots up with
2056                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2057                  * max, not what it tells us to use.
2058                  *
2059                  * Note: This will still be broken if the eDP panel is not lit
2060                  * up by the BIOS, and thus we can't get the mode at module
2061                  * load.
2062                  */
2063                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2064                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2065                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2066         }
2067
2068         intel_ddi_clock_get(encoder, pipe_config);
2069 }
2070
2071 static void intel_ddi_destroy(struct drm_encoder *encoder)
2072 {
2073         /* HDMI has nothing special to destroy, so we can go with this. */
2074         intel_dp_encoder_destroy(encoder);
2075 }
2076
2077 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2078                                      struct intel_crtc_state *pipe_config)
2079 {
2080         int type = encoder->type;
2081         int port = intel_ddi_get_encoder_port(encoder);
2082
2083         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2084
2085         if (port == PORT_A)
2086                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2087
2088         if (type == INTEL_OUTPUT_HDMI)
2089                 return intel_hdmi_compute_config(encoder, pipe_config);
2090         else
2091                 return intel_dp_compute_config(encoder, pipe_config);
2092 }
2093
2094 static const struct drm_encoder_funcs intel_ddi_funcs = {
2095         .destroy = intel_ddi_destroy,
2096 };
2097
2098 static struct intel_connector *
2099 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2100 {
2101         struct intel_connector *connector;
2102         enum port port = intel_dig_port->port;
2103
2104         connector = intel_connector_alloc();
2105         if (!connector)
2106                 return NULL;
2107
2108         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2109         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2110                 kfree(connector);
2111                 return NULL;
2112         }
2113
2114         return connector;
2115 }
2116
2117 static struct intel_connector *
2118 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2119 {
2120         struct intel_connector *connector;
2121         enum port port = intel_dig_port->port;
2122
2123         connector = intel_connector_alloc();
2124         if (!connector)
2125                 return NULL;
2126
2127         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2128         intel_hdmi_init_connector(intel_dig_port, connector);
2129
2130         return connector;
2131 }
2132
2133 void intel_ddi_init(struct drm_device *dev, enum port port)
2134 {
2135         struct drm_i915_private *dev_priv = dev->dev_private;
2136         struct intel_digital_port *intel_dig_port;
2137         struct intel_encoder *intel_encoder;
2138         struct drm_encoder *encoder;
2139         bool init_hdmi, init_dp;
2140
2141         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2142                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2143         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2144         if (!init_dp && !init_hdmi) {
2145                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2146                               port_name(port));
2147                 init_hdmi = true;
2148                 init_dp = true;
2149         }
2150
2151         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2152         if (!intel_dig_port)
2153                 return;
2154
2155         intel_encoder = &intel_dig_port->base;
2156         encoder = &intel_encoder->base;
2157
2158         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2159                          DRM_MODE_ENCODER_TMDS);
2160
2161         intel_encoder->compute_config = intel_ddi_compute_config;
2162         intel_encoder->enable = intel_enable_ddi;
2163         intel_encoder->pre_enable = intel_ddi_pre_enable;
2164         intel_encoder->disable = intel_disable_ddi;
2165         intel_encoder->post_disable = intel_ddi_post_disable;
2166         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2167         intel_encoder->get_config = intel_ddi_get_config;
2168
2169         intel_dig_port->port = port;
2170         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2171                                           (DDI_BUF_PORT_REVERSAL |
2172                                            DDI_A_4_LANES);
2173
2174         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2175         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2176         intel_encoder->cloneable = 0;
2177         intel_encoder->hot_plug = intel_ddi_hot_plug;
2178
2179         if (init_dp) {
2180                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2181                         goto err;
2182
2183                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2184                 dev_priv->hpd_irq_port[port] = intel_dig_port;
2185         }
2186
2187         /* In theory we don't need the encoder->type check, but leave it just in
2188          * case we have some really bad VBTs... */
2189         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2190                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2191                         goto err;
2192         }
2193
2194         return;
2195
2196 err:
2197         drm_encoder_cleanup(encoder);
2198         kfree(intel_dig_port);
2199 }