drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x80009010, 0x000000C0, 0x1 },
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x80007011, 0x000000C0, 0x1 },
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x80005012, 0x000000C0, 0x1 },
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x80007011, 0x000000CD, 0x1 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x80005012, 0x000000C0, 0x1 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x3 },
 162         { 0x80009010, 0x000000C0, 0x3 },
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x3 },
 165         { 0x80007011, 0x000000C0, 0x3 },
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x3 },
 168 };
 169
 170 /*
 171  * Skylake H and S
 172  * eDP 1.4 low vswing translation parameters
 173  */
 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 175         { 0x00000018, 0x000000A8, 0x0 },
 176         { 0x00004013, 0x000000A9, 0x0 },
 177         { 0x00007011, 0x000000A2, 0x0 },
 178         { 0x00009010, 0x0000009C, 0x0 },
 179         { 0x00000018, 0x000000A9, 0x0 },
 180         { 0x00006013, 0x000000A2, 0x0 },
 181         { 0x00007011, 0x000000A6, 0x0 },
 182         { 0x00000018, 0x000000AB, 0x0 },
 183         { 0x00007013, 0x0000009F, 0x0 },
 184         { 0x00000018, 0x000000DF, 0x0 },
 185 };
 186
 187 /*
 188  * Skylake U
 189  * eDP 1.4 low vswing translation parameters
 190  */
 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 192         { 0x00000018, 0x000000A8, 0x0 },
 193         { 0x00004013, 0x000000A9, 0x0 },
 194         { 0x00007011, 0x000000A2, 0x0 },
 195         { 0x00009010, 0x0000009C, 0x0 },
 196         { 0x00000018, 0x000000A9, 0x0 },
 197         { 0x00006013, 0x000000A2, 0x0 },
 198         { 0x00007011, 0x000000A6, 0x0 },
 199         { 0x00002016, 0x000000AB, 0x0 },
 200         { 0x00005013, 0x0000009F, 0x0 },
 201         { 0x00000018, 0x000000DF, 0x0 },
 202 };
 203
 204 /*
 205  * Skylake Y
 206  * eDP 1.4 low vswing translation parameters
 207  */
 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 209         { 0x00000018, 0x000000A8, 0x0 },
 210         { 0x00004013, 0x000000AB, 0x0 },
 211         { 0x00007011, 0x000000A4, 0x0 },
 212         { 0x00009010, 0x000000DF, 0x0 },
 213         { 0x00000018, 0x000000AA, 0x0 },
 214         { 0x00006013, 0x000000A4, 0x0 },
 215         { 0x00007011, 0x0000009D, 0x0 },
 216         { 0x00000018, 0x000000A0, 0x0 },
 217         { 0x00006012, 0x000000DF, 0x0 },
 218         { 0x00000018, 0x0000008A, 0x0 },
 219 };
 220
 221 /* Skylake U, H and S */
 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 223         { 0x00000018, 0x000000AC, 0x0 },
 224         { 0x00005012, 0x0000009D, 0x0 },
 225         { 0x00007011, 0x00000088, 0x0 },
 226         { 0x00000018, 0x000000A1, 0x0 },
 227         { 0x00000018, 0x00000098, 0x0 },
 228         { 0x00004013, 0x00000088, 0x0 },
 229         { 0x80006012, 0x000000CD, 0x1 },
 230         { 0x00000018, 0x000000DF, 0x0 },
 231         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 232         { 0x80003015, 0x000000C0, 0x1 },
 233         { 0x80000018, 0x000000C0, 0x1 },
 234 };
 235
 236 /* Skylake Y */
 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 238         { 0x00000018, 0x000000A1, 0x0 },
 239         { 0x00005012, 0x000000DF, 0x0 },
 240         { 0x80007011, 0x000000CB, 0x3 },
 241         { 0x00000018, 0x000000A4, 0x0 },
 242         { 0x00000018, 0x0000009D, 0x0 },
 243         { 0x00004013, 0x00000080, 0x0 },
 244         { 0x80006013, 0x000000C0, 0x3 },
 245         { 0x00000018, 0x0000008A, 0x0 },
 246         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 247         { 0x80003015, 0x000000C0, 0x3 },
 248         { 0x80000018, 0x000000C0, 0x3 },
 249 };
 250
 251 struct bxt_ddi_buf_trans {
 252         u32 margin;     /* swing value */
 253         u32 scale;      /* scale value */
 254         u32 enable;     /* scale enable */
 255         u32 deemphasis;
 256         bool default_index; /* true if the entry represents default value */
 257 };
 258
 259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 260                                         /* Idx  NT mV diff      db  */
 261         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 262         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 263         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 264         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 265         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 266         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 267         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 268         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 269         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 270         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 271 };
 272
 273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 274                                         /* Idx  NT mV diff      db  */
 275         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 276         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 277         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 278         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 279         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 280         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 281         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 282         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 283         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 284         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 285 };
 286
 287 /* BSpec has 2 recommended values - entries 0 and 8.
 288  * Using the entry with higher vswing.
 289  */
 290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 291                                         /* Idx  NT mV diff      db  */
 292         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 293         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 294         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 295         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 296         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 297         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 298         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 299         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 300         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 301         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 302 };
 303
 304 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 305 {
 306         switch (encoder->type) {
 307         case INTEL_OUTPUT_DP_MST:
 308                 return enc_to_mst(&encoder->base)->primary->port;
 309         case INTEL_OUTPUT_DP:
 310         case INTEL_OUTPUT_EDP:
 311         case INTEL_OUTPUT_HDMI:
 312         case INTEL_OUTPUT_UNKNOWN:
 313                 return enc_to_dig_port(&encoder->base)->port;
 314         case INTEL_OUTPUT_ANALOG:
 315                 return PORT_E;
 316         default:
 317                 MISSING_CASE(encoder->type);
 318                 return PORT_A;
 319         }
 320 }
 321
 322 static const struct ddi_buf_trans *
 323 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 324 {
 325         if (dev_priv->vbt.edp.low_vswing) {
 326                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 327                 return bdw_ddi_translations_edp;
 328         } else {
 329                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 330                 return bdw_ddi_translations_dp;
 331         }
 332 }
 333
 334 static const struct ddi_buf_trans *
 335 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 336 {
 337         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 338                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 339                 return skl_y_ddi_translations_dp;
 340         } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 341                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 342                 return skl_u_ddi_translations_dp;
 343         } else {
 344                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 345                 return skl_ddi_translations_dp;
 346         }
 347 }
 348
 349 static const struct ddi_buf_trans *
 350 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 351 {
 352         if (dev_priv->vbt.edp.low_vswing) {
 353                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 354                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 355                         return skl_y_ddi_translations_edp;
 356                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 357                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 358                         return skl_u_ddi_translations_edp;
 359                 } else {
 360                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 361                         return skl_ddi_translations_edp;
 362                 }
 363         }
 364
 365         return skl_get_buf_trans_dp(dev_priv, n_entries);
 366 }
 367
 368 static const struct ddi_buf_trans *
 369 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 370 {
 371         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 372                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 373                 return skl_y_ddi_translations_hdmi;
 374         } else {
 375                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 376                 return skl_ddi_translations_hdmi;
 377         }
 378 }
 379
 380 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 381 {
 382         int n_hdmi_entries;
 383         int hdmi_level;
 384         int hdmi_default_entry;
 385
 386         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 387
 388         if (IS_BROXTON(dev_priv))
 389                 return hdmi_level;
 390
 391         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 392                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 393                 hdmi_default_entry = 8;
 394         } else if (IS_BROADWELL(dev_priv)) {
 395                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 396                 hdmi_default_entry = 7;
 397         } else if (IS_HASWELL(dev_priv)) {
 398                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 399                 hdmi_default_entry = 6;
 400         } else {
 401                 WARN(1, "ddi translation table missing\n");
 402                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 403                 hdmi_default_entry = 7;
 404         }
 405
 406         /* Choose a good default if VBT is badly populated */
 407         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 408             hdmi_level >= n_hdmi_entries)
 409                 hdmi_level = hdmi_default_entry;
 410
 411         return hdmi_level;
 412 }
 413
 414 /*
 415  * Starting with Haswell, DDI port buffers must be programmed with correct
 416  * values in advance. This function programs the correct values for
 417  * DP/eDP/FDI use cases.
 418  */
 419 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 420 {
 421         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 422         u32 iboost_bit = 0;
 423         int i, n_dp_entries, n_edp_entries, size;
 424         enum port port = intel_ddi_get_encoder_port(encoder);
 425         const struct ddi_buf_trans *ddi_translations_fdi;
 426         const struct ddi_buf_trans *ddi_translations_dp;
 427         const struct ddi_buf_trans *ddi_translations_edp;
 428         const struct ddi_buf_trans *ddi_translations;
 429
 430         if (IS_BROXTON(dev_priv))
 431                 return;
 432
 433         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 434                 ddi_translations_fdi = NULL;
 435                 ddi_translations_dp =
 436                                 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
 437                 ddi_translations_edp =
 438                                 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
 439
 440                 /* If we're boosting the current, set bit 31 of trans1 */
 441                 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 442                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 443
 444                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 445                             port != PORT_A && port != PORT_E &&
 446                             n_edp_entries > 9))
 447                         n_edp_entries = 9;
 448         } else if (IS_BROADWELL(dev_priv)) {
 449                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 450                 ddi_translations_dp = bdw_ddi_translations_dp;
 451                 ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
 452                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 453         } else if (IS_HASWELL(dev_priv)) {
 454                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 455                 ddi_translations_dp = hsw_ddi_translations_dp;
 456                 ddi_translations_edp = hsw_ddi_translations_dp;
 457                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 458         } else {
 459                 WARN(1, "ddi translation table missing\n");
 460                 ddi_translations_edp = bdw_ddi_translations_dp;
 461                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 462                 ddi_translations_dp = bdw_ddi_translations_dp;
 463                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 464                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 465         }
 466
 467         switch (encoder->type) {
 468         case INTEL_OUTPUT_EDP:
 469                 ddi_translations = ddi_translations_edp;
 470                 size = n_edp_entries;
 471                 break;
 472         case INTEL_OUTPUT_DP:
 473                 ddi_translations = ddi_translations_dp;
 474                 size = n_dp_entries;
 475                 break;
 476         case INTEL_OUTPUT_ANALOG:
 477                 ddi_translations = ddi_translations_fdi;
 478                 size = n_dp_entries;
 479                 break;
 480         default:
 481                 BUG();
 482         }
 483
 484         for (i = 0; i < size; i++) {
 485                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 486                            ddi_translations[i].trans1 | iboost_bit);
 487                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 488                            ddi_translations[i].trans2);
 489         }
 490 }
 491
 492 /*
 493  * Starting with Haswell, DDI port buffers must be programmed with correct
 494  * values in advance. This function programs the correct values for
 495  * HDMI/DVI use cases.
 496  */
 497 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 498 {
 499         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 500         u32 iboost_bit = 0;
 501         int n_hdmi_entries, hdmi_level;
 502         enum port port = intel_ddi_get_encoder_port(encoder);
 503         const struct ddi_buf_trans *ddi_translations_hdmi;
 504
 505         if (IS_BROXTON(dev_priv))
 506                 return;
 507
 508         hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 509
 510         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 511                 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 512
 513                 /* If we're boosting the current, set bit 31 of trans1 */
 514                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 515                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 516         } else if (IS_BROADWELL(dev_priv)) {
 517                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 518                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 519         } else if (IS_HASWELL(dev_priv)) {
 520                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 521                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 522         } else {
 523                 WARN(1, "ddi translation table missing\n");
 524                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 525                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 526         }
 527
 528         /* Entry 9 is for HDMI: */
 529         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 530                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 531         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 532                    ddi_translations_hdmi[hdmi_level].trans2);
 533 }
 534
 535 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 536                                     enum port port)
 537 {
 538         i915_reg_t reg = DDI_BUF_CTL(port);
 539         int i;
 540
 541         for (i = 0; i < 16; i++) {
 542                 udelay(1);
 543                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 544                         return;
 545         }
 546         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 547 }
 548
 549 /* Starting with Haswell, different DDI ports can work in FDI mode for
 550  * connection to the PCH-located connectors. For this, it is necessary to train
 551  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 552  *
 553  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 554  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 555  * DDI A (which is used for eDP)
 556  */
 557
 558 void hsw_fdi_link_train(struct drm_crtc *crtc)
 559 {
 560         struct drm_device *dev = crtc->dev;
 561         struct drm_i915_private *dev_priv = to_i915(dev);
 562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 563         struct intel_encoder *encoder;
 564         u32 temp, i, rx_ctl_val;
 565
 566         for_each_encoder_on_crtc(dev, crtc, encoder) {
 567                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 568                 intel_prepare_dp_ddi_buffers(encoder);
 569         }
 570
 571         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 572          * mode set "sequence for CRT port" document:
 573          * - TP1 to TP2 time with the default value
 574          * - FDI delay to 90h
 575          *
 576          * WaFDIAutoLinkSetTimingOverrride:hsw
 577          */
 578         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 579                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 580                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 581
 582         /* Enable the PCH Receiver FDI PLL */
 583         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 584                      FDI_RX_PLL_ENABLE |
 585                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 586         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 587         POSTING_READ(FDI_RX_CTL(PIPE_A));
 588         udelay(220);
 589
 590         /* Switch from Rawclk to PCDclk */
 591         rx_ctl_val |= FDI_PCDCLK;
 592         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 593
 594         /* Configure Port Clock Select */
 595         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 596         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 597
 598         /* Start the training iterating through available voltages and emphasis,
 599          * testing each value twice. */
 600         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 601                 /* Configure DP_TP_CTL with auto-training */
 602                 I915_WRITE(DP_TP_CTL(PORT_E),
 603                                         DP_TP_CTL_FDI_AUTOTRAIN |
 604                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 605                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 606                                         DP_TP_CTL_ENABLE);
 607
 608                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 609                  * DDI E does not support port reversal, the functionality is
 610                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 611                  * port reversal bit */
 612                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 613                            DDI_BUF_CTL_ENABLE |
 614                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 615                            DDI_BUF_TRANS_SELECT(i / 2));
 616                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 617
 618                 udelay(600);
 619
 620                 /* Program PCH FDI Receiver TU */
 621                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 622
 623                 /* Enable PCH FDI Receiver with auto-training */
 624                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 625                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 626                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 627
 628                 /* Wait for FDI receiver lane calibration */
 629                 udelay(30);
 630
 631                 /* Unset FDI_RX_MISC pwrdn lanes */
 632                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 633                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 634                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 635                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 636
 637                 /* Wait for FDI auto training time */
 638                 udelay(5);
 639
 640                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 641                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 642                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 643                         break;
 644                 }
 645
 646                 /*
 647                  * Leave things enabled even if we failed to train FDI.
 648                  * Results in less fireworks from the state checker.
 649                  */
 650                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 651                         DRM_ERROR("FDI link training failed!\n");
 652                         break;
 653                 }
 654
 655                 rx_ctl_val &= ~FDI_RX_ENABLE;
 656                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 657                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 658
 659                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 660                 temp &= ~DDI_BUF_CTL_ENABLE;
 661                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 662                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 663
 664                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 665                 temp = I915_READ(DP_TP_CTL(PORT_E));
 666                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 667                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 668                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 669                 POSTING_READ(DP_TP_CTL(PORT_E));
 670
 671                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 672
 673                 /* Reset FDI_RX_MISC pwrdn lanes */
 674                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 675                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 676                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 677                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 678                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 679         }
 680
 681         /* Enable normal pixel sending for FDI */
 682         I915_WRITE(DP_TP_CTL(PORT_E),
 683                    DP_TP_CTL_FDI_AUTOTRAIN |
 684                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 685                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 686                    DP_TP_CTL_ENABLE);
 687 }
 688
 689 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 690 {
 691         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 692         struct intel_digital_port *intel_dig_port =
 693                 enc_to_dig_port(&encoder->base);
 694
 695         intel_dp->DP = intel_dig_port->saved_port_bits |
 696                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 697         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 698 }
 699
 700 static struct intel_encoder *
 701 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 702 {
 703         struct drm_device *dev = crtc->dev;
 704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 705         struct intel_encoder *intel_encoder, *ret = NULL;
 706         int num_encoders = 0;
 707
 708         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 709                 ret = intel_encoder;
 710                 num_encoders++;
 711         }
 712
 713         if (num_encoders != 1)
 714                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 715                      pipe_name(intel_crtc->pipe));
 716
 717         BUG_ON(ret == NULL);
 718         return ret;
 719 }
 720
 721 struct intel_encoder *
 722 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 723 {
 724         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 725         struct intel_encoder *ret = NULL;
 726         struct drm_atomic_state *state;
 727         struct drm_connector *connector;
 728         struct drm_connector_state *connector_state;
 729         int num_encoders = 0;
 730         int i;
 731
 732         state = crtc_state->base.state;
 733
 734         for_each_connector_in_state(state, connector, connector_state, i) {
 735                 if (connector_state->crtc != crtc_state->base.crtc)
 736                         continue;
 737
 738                 ret = to_intel_encoder(connector_state->best_encoder);
 739                 num_encoders++;
 740         }
 741
 742         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 743              pipe_name(crtc->pipe));
 744
 745         BUG_ON(ret == NULL);
 746         return ret;
 747 }
 748
 749 #define LC_FREQ 2700
 750
 751 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 752                                    i915_reg_t reg)
 753 {
 754         int refclk = LC_FREQ;
 755         int n, p, r;
 756         u32 wrpll;
 757
 758         wrpll = I915_READ(reg);
 759         switch (wrpll & WRPLL_PLL_REF_MASK) {
 760         case WRPLL_PLL_SSC:
 761         case WRPLL_PLL_NON_SSC:
 762                 /*
 763                  * We could calculate spread here, but our checking
 764                  * code only cares about 5% accuracy, and spread is a max of
 765                  * 0.5% downspread.
 766                  */
 767                 refclk = 135;
 768                 break;
 769         case WRPLL_PLL_LCPLL:
 770                 refclk = LC_FREQ;
 771                 break;
 772         default:
 773                 WARN(1, "bad wrpll refclk\n");
 774                 return 0;
 775         }
 776
 777         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 778         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 779         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 780
 781         /* Convert to KHz, p & r have a fixed point portion */
 782         return (refclk * n * 100) / (p * r);
 783 }
 784
 785 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 786                                uint32_t dpll)
 787 {
 788         i915_reg_t cfgcr1_reg, cfgcr2_reg;
 789         uint32_t cfgcr1_val, cfgcr2_val;
 790         uint32_t p0, p1, p2, dco_freq;
 791
 792         cfgcr1_reg = DPLL_CFGCR1(dpll);
 793         cfgcr2_reg = DPLL_CFGCR2(dpll);
 794
 795         cfgcr1_val = I915_READ(cfgcr1_reg);
 796         cfgcr2_val = I915_READ(cfgcr2_reg);
 797
 798         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 799         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 800
 801         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 802                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 803         else
 804                 p1 = 1;
 805
 806
 807         switch (p0) {
 808         case DPLL_CFGCR2_PDIV_1:
 809                 p0 = 1;
 810                 break;
 811         case DPLL_CFGCR2_PDIV_2:
 812                 p0 = 2;
 813                 break;
 814         case DPLL_CFGCR2_PDIV_3:
 815                 p0 = 3;
 816                 break;
 817         case DPLL_CFGCR2_PDIV_7:
 818                 p0 = 7;
 819                 break;
 820         }
 821
 822         switch (p2) {
 823         case DPLL_CFGCR2_KDIV_5:
 824                 p2 = 5;
 825                 break;
 826         case DPLL_CFGCR2_KDIV_2:
 827                 p2 = 2;
 828                 break;
 829         case DPLL_CFGCR2_KDIV_3:
 830                 p2 = 3;
 831                 break;
 832         case DPLL_CFGCR2_KDIV_1:
 833                 p2 = 1;
 834                 break;
 835         }
 836
 837         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 838
 839         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 840                 1000) / 0x8000;
 841
 842         return dco_freq / (p0 * p1 * p2 * 5);
 843 }
 844
 845 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 846 {
 847         int dotclock;
 848
 849         if (pipe_config->has_pch_encoder)
 850                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 851                                                     &pipe_config->fdi_m_n);
 852         else if (intel_crtc_has_dp_encoder(pipe_config))
 853                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 854                                                     &pipe_config->dp_m_n);
 855         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
 856                 dotclock = pipe_config->port_clock * 2 / 3;
 857         else
 858                 dotclock = pipe_config->port_clock;
 859
 860         if (pipe_config->pixel_multiplier)
 861                 dotclock /= pipe_config->pixel_multiplier;
 862
 863         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 864 }
 865
 866 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 867                                 struct intel_crtc_state *pipe_config)
 868 {
 869         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 870         int link_clock = 0;
 871         uint32_t dpll_ctl1, dpll;
 872
 873         dpll = pipe_config->ddi_pll_sel;
 874
 875         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 876
 877         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 878                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 879         } else {
 880                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
 881                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
 882
 883                 switch (link_clock) {
 884                 case DPLL_CTRL1_LINK_RATE_810:
 885                         link_clock = 81000;
 886                         break;
 887                 case DPLL_CTRL1_LINK_RATE_1080:
 888                         link_clock = 108000;
 889                         break;
 890                 case DPLL_CTRL1_LINK_RATE_1350:
 891                         link_clock = 135000;
 892                         break;
 893                 case DPLL_CTRL1_LINK_RATE_1620:
 894                         link_clock = 162000;
 895                         break;
 896                 case DPLL_CTRL1_LINK_RATE_2160:
 897                         link_clock = 216000;
 898                         break;
 899                 case DPLL_CTRL1_LINK_RATE_2700:
 900                         link_clock = 270000;
 901                         break;
 902                 default:
 903                         WARN(1, "Unsupported link rate\n");
 904                         break;
 905                 }
 906                 link_clock *= 2;
 907         }
 908
 909         pipe_config->port_clock = link_clock;
 910
 911         ddi_dotclock_get(pipe_config);
 912 }
 913
 914 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 915                               struct intel_crtc_state *pipe_config)
 916 {
 917         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 918         int link_clock = 0;
 919         u32 val, pll;
 920
 921         val = pipe_config->ddi_pll_sel;
 922         switch (val & PORT_CLK_SEL_MASK) {
 923         case PORT_CLK_SEL_LCPLL_810:
 924                 link_clock = 81000;
 925                 break;
 926         case PORT_CLK_SEL_LCPLL_1350:
 927                 link_clock = 135000;
 928                 break;
 929         case PORT_CLK_SEL_LCPLL_2700:
 930                 link_clock = 270000;
 931                 break;
 932         case PORT_CLK_SEL_WRPLL1:
 933                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
 934                 break;
 935         case PORT_CLK_SEL_WRPLL2:
 936                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
 937                 break;
 938         case PORT_CLK_SEL_SPLL:
 939                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 940                 if (pll == SPLL_PLL_FREQ_810MHz)
 941                         link_clock = 81000;
 942                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 943                         link_clock = 135000;
 944                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 945                         link_clock = 270000;
 946                 else {
 947                         WARN(1, "bad spll freq\n");
 948                         return;
 949                 }
 950                 break;
 951         default:
 952                 WARN(1, "bad port clock sel\n");
 953                 return;
 954         }
 955
 956         pipe_config->port_clock = link_clock * 2;
 957
 958         ddi_dotclock_get(pipe_config);
 959 }
 960
 961 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
 962                                 enum intel_dpll_id dpll)
 963 {
 964         struct intel_shared_dpll *pll;
 965         struct intel_dpll_hw_state *state;
 966         struct dpll clock;
 967
 968         /* For DDI ports we always use a shared PLL. */
 969         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
 970                 return 0;
 971
 972         pll = &dev_priv->shared_dplls[dpll];
 973         state = &pll->config.hw_state;
 974
 975         clock.m1 = 2;
 976         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
 977         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
 978                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
 979         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
 980         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
 981         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
 982
 983         return chv_calc_dpll_params(100000, &clock);
 984 }
 985
 986 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
 987                                 struct intel_crtc_state *pipe_config)
 988 {
 989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 990         enum port port = intel_ddi_get_encoder_port(encoder);
 991         uint32_t dpll = port;
 992
 993         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
 994
 995         ddi_dotclock_get(pipe_config);
 996 }
 997
 998 void intel_ddi_clock_get(struct intel_encoder *encoder,
 999                          struct intel_crtc_state *pipe_config)
1000 {
1001         struct drm_device *dev = encoder->base.dev;
1002
1003         if (INTEL_INFO(dev)->gen <= 8)
1004                 hsw_ddi_clock_get(encoder, pipe_config);
1005         else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1006                 skl_ddi_clock_get(encoder, pipe_config);
1007         else if (IS_BROXTON(dev))
1008                 bxt_ddi_clock_get(encoder, pipe_config);
1009 }
1010
1011 static bool
1012 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1013                    struct intel_crtc_state *crtc_state,
1014                    struct intel_encoder *intel_encoder)
1015 {
1016         struct intel_shared_dpll *pll;
1017
1018         pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1019                                     intel_encoder);
1020         if (!pll)
1021                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022                                  pipe_name(intel_crtc->pipe));
1023
1024         return pll;
1025 }
1026
1027 static bool
1028 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1029                    struct intel_crtc_state *crtc_state,
1030                    struct intel_encoder *intel_encoder)
1031 {
1032         struct intel_shared_dpll *pll;
1033
1034         pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1035         if (pll == NULL) {
1036                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1037                                  pipe_name(intel_crtc->pipe));
1038                 return false;
1039         }
1040
1041         return true;
1042 }
1043
1044 static bool
1045 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1046                    struct intel_crtc_state *crtc_state,
1047                    struct intel_encoder *intel_encoder)
1048 {
1049         return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1050 }
1051
1052 /*
1053  * Tries to find a *shared* PLL for the CRTC and store it in
1054  * intel_crtc->ddi_pll_sel.
1055  *
1056  * For private DPLLs, compute_config() should do the selection for us. This
1057  * function should be folded into compute_config() eventually.
1058  */
1059 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1060                           struct intel_crtc_state *crtc_state)
1061 {
1062         struct drm_device *dev = intel_crtc->base.dev;
1063         struct intel_encoder *intel_encoder =
1064                 intel_ddi_get_crtc_new_encoder(crtc_state);
1065
1066         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1067                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1068                                           intel_encoder);
1069         else if (IS_BROXTON(dev))
1070                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1071                                           intel_encoder);
1072         else
1073                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1074                                           intel_encoder);
1075 }
1076
1077 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1078 {
1079         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1081         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1082         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1083         int type = intel_encoder->type;
1084         uint32_t temp;
1085
1086         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1087                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1088
1089                 temp = TRANS_MSA_SYNC_CLK;
1090                 switch (intel_crtc->config->pipe_bpp) {
1091                 case 18:
1092                         temp |= TRANS_MSA_6_BPC;
1093                         break;
1094                 case 24:
1095                         temp |= TRANS_MSA_8_BPC;
1096                         break;
1097                 case 30:
1098                         temp |= TRANS_MSA_10_BPC;
1099                         break;
1100                 case 36:
1101                         temp |= TRANS_MSA_12_BPC;
1102                         break;
1103                 default:
1104                         BUG();
1105                 }
1106                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1107         }
1108 }
1109
1110 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1111 {
1112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1113         struct drm_device *dev = crtc->dev;
1114         struct drm_i915_private *dev_priv = to_i915(dev);
1115         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1116         uint32_t temp;
1117         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1118         if (state == true)
1119                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1120         else
1121                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1122         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1123 }
1124
1125 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1126 {
1127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1128         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1129         struct drm_device *dev = crtc->dev;
1130         struct drm_i915_private *dev_priv = to_i915(dev);
1131         enum pipe pipe = intel_crtc->pipe;
1132         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1133         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1134         int type = intel_encoder->type;
1135         uint32_t temp;
1136
1137         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1138         temp = TRANS_DDI_FUNC_ENABLE;
1139         temp |= TRANS_DDI_SELECT_PORT(port);
1140
1141         switch (intel_crtc->config->pipe_bpp) {
1142         case 18:
1143                 temp |= TRANS_DDI_BPC_6;
1144                 break;
1145         case 24:
1146                 temp |= TRANS_DDI_BPC_8;
1147                 break;
1148         case 30:
1149                 temp |= TRANS_DDI_BPC_10;
1150                 break;
1151         case 36:
1152                 temp |= TRANS_DDI_BPC_12;
1153                 break;
1154         default:
1155                 BUG();
1156         }
1157
1158         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1159                 temp |= TRANS_DDI_PVSYNC;
1160         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1161                 temp |= TRANS_DDI_PHSYNC;
1162
1163         if (cpu_transcoder == TRANSCODER_EDP) {
1164                 switch (pipe) {
1165                 case PIPE_A:
1166                         /* On Haswell, can only use the always-on power well for
1167                          * eDP when not using the panel fitter, and when not
1168                          * using motion blur mitigation (which we don't
1169                          * support). */
1170                         if (IS_HASWELL(dev) &&
1171                             (intel_crtc->config->pch_pfit.enabled ||
1172                              intel_crtc->config->pch_pfit.force_thru))
1173                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1174                         else
1175                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1176                         break;
1177                 case PIPE_B:
1178                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1179                         break;
1180                 case PIPE_C:
1181                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1182                         break;
1183                 default:
1184                         BUG();
1185                         break;
1186                 }
1187         }
1188
1189         if (type == INTEL_OUTPUT_HDMI) {
1190                 if (intel_crtc->config->has_hdmi_sink)
1191                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1192                 else
1193                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1194         } else if (type == INTEL_OUTPUT_ANALOG) {
1195                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1196                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1197         } else if (type == INTEL_OUTPUT_DP ||
1198                    type == INTEL_OUTPUT_EDP) {
1199                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1200                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1201         } else if (type == INTEL_OUTPUT_DP_MST) {
1202                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1203                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1204         } else {
1205                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1206                      intel_encoder->type, pipe_name(pipe));
1207         }
1208
1209         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1210 }
1211
1212 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1213                                        enum transcoder cpu_transcoder)
1214 {
1215         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1216         uint32_t val = I915_READ(reg);
1217
1218         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1219         val |= TRANS_DDI_PORT_NONE;
1220         I915_WRITE(reg, val);
1221 }
1222
1223 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1224 {
1225         struct drm_device *dev = intel_connector->base.dev;
1226         struct drm_i915_private *dev_priv = to_i915(dev);
1227         struct intel_encoder *intel_encoder = intel_connector->encoder;
1228         int type = intel_connector->base.connector_type;
1229         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1230         enum pipe pipe = 0;
1231         enum transcoder cpu_transcoder;
1232         enum intel_display_power_domain power_domain;
1233         uint32_t tmp;
1234         bool ret;
1235
1236         power_domain = intel_display_port_power_domain(intel_encoder);
1237         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1238                 return false;
1239
1240         if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1241                 ret = false;
1242                 goto out;
1243         }
1244
1245         if (port == PORT_A)
1246                 cpu_transcoder = TRANSCODER_EDP;
1247         else
1248                 cpu_transcoder = (enum transcoder) pipe;
1249
1250         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1251
1252         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1253         case TRANS_DDI_MODE_SELECT_HDMI:
1254         case TRANS_DDI_MODE_SELECT_DVI:
1255                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1256                 break;
1257
1258         case TRANS_DDI_MODE_SELECT_DP_SST:
1259                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1260                       type == DRM_MODE_CONNECTOR_DisplayPort;
1261                 break;
1262
1263         case TRANS_DDI_MODE_SELECT_DP_MST:
1264                 /* if the transcoder is in MST state then
1265                  * connector isn't connected */
1266                 ret = false;
1267                 break;
1268
1269         case TRANS_DDI_MODE_SELECT_FDI:
1270                 ret = type == DRM_MODE_CONNECTOR_VGA;
1271                 break;
1272
1273         default:
1274                 ret = false;
1275                 break;
1276         }
1277
1278 out:
1279         intel_display_power_put(dev_priv, power_domain);
1280
1281         return ret;
1282 }
1283
1284 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1285                             enum pipe *pipe)
1286 {
1287         struct drm_device *dev = encoder->base.dev;
1288         struct drm_i915_private *dev_priv = to_i915(dev);
1289         enum port port = intel_ddi_get_encoder_port(encoder);
1290         enum intel_display_power_domain power_domain;
1291         u32 tmp;
1292         int i;
1293         bool ret;
1294
1295         power_domain = intel_display_port_power_domain(encoder);
1296         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1297                 return false;
1298
1299         ret = false;
1300
1301         tmp = I915_READ(DDI_BUF_CTL(port));
1302
1303         if (!(tmp & DDI_BUF_CTL_ENABLE))
1304                 goto out;
1305
1306         if (port == PORT_A) {
1307                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1308
1309                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1310                 case TRANS_DDI_EDP_INPUT_A_ON:
1311                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1312                         *pipe = PIPE_A;
1313                         break;
1314                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1315                         *pipe = PIPE_B;
1316                         break;
1317                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1318                         *pipe = PIPE_C;
1319                         break;
1320                 }
1321
1322                 ret = true;
1323
1324                 goto out;
1325         }
1326
1327         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1328                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1329
1330                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1331                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1332                             TRANS_DDI_MODE_SELECT_DP_MST)
1333                                 goto out;
1334
1335                         *pipe = i;
1336                         ret = true;
1337
1338                         goto out;
1339                 }
1340         }
1341
1342         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1343
1344 out:
1345         if (ret && IS_BROXTON(dev_priv)) {
1346                 tmp = I915_READ(BXT_PHY_CTL(port));
1347                 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1348                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1349                         DRM_ERROR("Port %c enabled but PHY powered down? "
1350                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1351         }
1352
1353         intel_display_power_put(dev_priv, power_domain);
1354
1355         return ret;
1356 }
1357
1358 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1359 {
1360         struct drm_crtc *crtc = &intel_crtc->base;
1361         struct drm_device *dev = crtc->dev;
1362         struct drm_i915_private *dev_priv = to_i915(dev);
1363         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1364         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1365         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1366
1367         if (cpu_transcoder != TRANSCODER_EDP)
1368                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1369                            TRANS_CLK_SEL_PORT(port));
1370 }
1371
1372 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1373 {
1374         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1375         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1376
1377         if (cpu_transcoder != TRANSCODER_EDP)
1378                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1379                            TRANS_CLK_SEL_DISABLED);
1380 }
1381
1382 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1383                                 enum port port, uint8_t iboost)
1384 {
1385         u32 tmp;
1386
1387         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1388         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1389         if (iboost)
1390                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1391         else
1392                 tmp |= BALANCE_LEG_DISABLE(port);
1393         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1394 }
1395
1396 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1397 {
1398         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1399         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1400         enum port port = intel_dig_port->port;
1401         int type = encoder->type;
1402         const struct ddi_buf_trans *ddi_translations;
1403         uint8_t iboost;
1404         uint8_t dp_iboost, hdmi_iboost;
1405         int n_entries;
1406
1407         /* VBT may override standard boost values */
1408         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1409         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1410
1411         if (type == INTEL_OUTPUT_DP) {
1412                 if (dp_iboost) {
1413                         iboost = dp_iboost;
1414                 } else {
1415                         ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
1416                         iboost = ddi_translations[level].i_boost;
1417                 }
1418         } else if (type == INTEL_OUTPUT_EDP) {
1419                 if (dp_iboost) {
1420                         iboost = dp_iboost;
1421                 } else {
1422                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1423
1424                         if (WARN_ON(port != PORT_A &&
1425                                     port != PORT_E && n_entries > 9))
1426                                 n_entries = 9;
1427
1428                         iboost = ddi_translations[level].i_boost;
1429                 }
1430         } else if (type == INTEL_OUTPUT_HDMI) {
1431                 if (hdmi_iboost) {
1432                         iboost = hdmi_iboost;
1433                 } else {
1434                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1435                         iboost = ddi_translations[level].i_boost;
1436                 }
1437         } else {
1438                 return;
1439         }
1440
1441         /* Make sure that the requested I_boost is valid */
1442         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1443                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1444                 return;
1445         }
1446
1447         _skl_ddi_set_iboost(dev_priv, port, iboost);
1448
1449         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1450                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1451 }
1452
1453 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1454                                     u32 level, enum port port, int type)
1455 {
1456         const struct bxt_ddi_buf_trans *ddi_translations;
1457         u32 n_entries, i;
1458         uint32_t val;
1459
1460         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1461                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1462                 ddi_translations = bxt_ddi_translations_edp;
1463         } else if (type == INTEL_OUTPUT_DP
1464                         || type == INTEL_OUTPUT_EDP) {
1465                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1466                 ddi_translations = bxt_ddi_translations_dp;
1467         } else if (type == INTEL_OUTPUT_HDMI) {
1468                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1469                 ddi_translations = bxt_ddi_translations_hdmi;
1470         } else {
1471                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1472                                 type);
1473                 return;
1474         }
1475
1476         /* Check if default value has to be used */
1477         if (level >= n_entries ||
1478             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1479                 for (i = 0; i < n_entries; i++) {
1480                         if (ddi_translations[i].default_index) {
1481                                 level = i;
1482                                 break;
1483                         }
1484                 }
1485         }
1486
1487         /*
1488          * While we write to the group register to program all lanes at once we
1489          * can read only lane registers and we pick lanes 0/1 for that.
1490          */
1491         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1492         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1493         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1494
1495         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1496         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1497         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1498                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1499         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1500
1501         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1502         val &= ~SCALE_DCOMP_METHOD;
1503         if (ddi_translations[level].enable)
1504                 val |= SCALE_DCOMP_METHOD;
1505
1506         if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1507                 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1508
1509         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1510
1511         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1512         val &= ~DE_EMPHASIS;
1513         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1514         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1515
1516         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1517         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1518         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1519 }
1520
1521 static uint32_t translate_signal_level(int signal_levels)
1522 {
1523         uint32_t level;
1524
1525         switch (signal_levels) {
1526         default:
1527                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1528                               signal_levels);
1529         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1530                 level = 0;
1531                 break;
1532         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1533                 level = 1;
1534                 break;
1535         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1536                 level = 2;
1537                 break;
1538         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1539                 level = 3;
1540                 break;
1541
1542         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1543                 level = 4;
1544                 break;
1545         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1546                 level = 5;
1547                 break;
1548         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1549                 level = 6;
1550                 break;
1551
1552         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1553                 level = 7;
1554                 break;
1555         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1556                 level = 8;
1557                 break;
1558
1559         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1560                 level = 9;
1561                 break;
1562         }
1563
1564         return level;
1565 }
1566
1567 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1568 {
1569         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1570         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1571         struct intel_encoder *encoder = &dport->base;
1572         uint8_t train_set = intel_dp->train_set[0];
1573         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1574                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1575         enum port port = dport->port;
1576         uint32_t level;
1577
1578         level = translate_signal_level(signal_levels);
1579
1580         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1581                 skl_ddi_set_iboost(encoder, level);
1582         else if (IS_BROXTON(dev_priv))
1583                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1584
1585         return DDI_BUF_TRANS_SELECT(level);
1586 }
1587
1588 void intel_ddi_clk_select(struct intel_encoder *encoder,
1589                           const struct intel_crtc_state *pipe_config)
1590 {
1591         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1592         enum port port = intel_ddi_get_encoder_port(encoder);
1593
1594         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1595                 uint32_t dpll = pipe_config->ddi_pll_sel;
1596                 uint32_t val;
1597
1598                 /* DDI -> PLL mapping  */
1599                 val = I915_READ(DPLL_CTRL2);
1600
1601                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1602                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1603                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1604                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1605
1606                 I915_WRITE(DPLL_CTRL2, val);
1607
1608         } else if (INTEL_INFO(dev_priv)->gen < 9) {
1609                 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1610                 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
1611         }
1612 }
1613
1614 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1615 {
1616         struct drm_encoder *encoder = &intel_encoder->base;
1617         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1618         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1619         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1620         int type = intel_encoder->type;
1621
1622         if (type == INTEL_OUTPUT_HDMI) {
1623                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1624
1625                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1626         }
1627
1628         if (type == INTEL_OUTPUT_EDP) {
1629                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1630                 intel_edp_panel_on(intel_dp);
1631         }
1632
1633         intel_ddi_clk_select(intel_encoder, crtc->config);
1634
1635         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1636                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1637
1638                 intel_prepare_dp_ddi_buffers(intel_encoder);
1639
1640                 intel_dp_set_link_params(intel_dp, crtc->config);
1641
1642                 intel_ddi_init_dp_buf_reg(intel_encoder);
1643
1644                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1645                 intel_dp_start_link_train(intel_dp);
1646                 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
1647                         intel_dp_stop_link_train(intel_dp);
1648         } else if (type == INTEL_OUTPUT_HDMI) {
1649                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1650                 int level = intel_ddi_hdmi_level(dev_priv, port);
1651
1652                 intel_prepare_hdmi_ddi_buffers(intel_encoder);
1653
1654                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1655                         skl_ddi_set_iboost(intel_encoder, level);
1656                 else if (IS_BROXTON(dev_priv))
1657                         bxt_ddi_vswing_sequence(dev_priv, level, port,
1658                                                 INTEL_OUTPUT_HDMI);
1659
1660                 intel_hdmi->set_infoframes(encoder,
1661                                            crtc->config->has_hdmi_sink,
1662                                            &crtc->config->base.adjusted_mode);
1663         }
1664 }
1665
1666 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1667 {
1668         struct drm_encoder *encoder = &intel_encoder->base;
1669         struct drm_device *dev = encoder->dev;
1670         struct drm_i915_private *dev_priv = to_i915(dev);
1671         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1672         int type = intel_encoder->type;
1673         uint32_t val;
1674         bool wait = false;
1675
1676         val = I915_READ(DDI_BUF_CTL(port));
1677         if (val & DDI_BUF_CTL_ENABLE) {
1678                 val &= ~DDI_BUF_CTL_ENABLE;
1679                 I915_WRITE(DDI_BUF_CTL(port), val);
1680                 wait = true;
1681         }
1682
1683         val = I915_READ(DP_TP_CTL(port));
1684         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1685         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1686         I915_WRITE(DP_TP_CTL(port), val);
1687
1688         if (wait)
1689                 intel_wait_ddi_buf_idle(dev_priv, port);
1690
1691         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1692                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1693                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1694                 intel_edp_panel_vdd_on(intel_dp);
1695                 intel_edp_panel_off(intel_dp);
1696         }
1697
1698         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1699                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1700                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1701         else if (INTEL_INFO(dev)->gen < 9)
1702                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1703
1704         if (type == INTEL_OUTPUT_HDMI) {
1705                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1706
1707                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1708         }
1709 }
1710
1711 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1712 {
1713         struct drm_encoder *encoder = &intel_encoder->base;
1714         struct drm_crtc *crtc = encoder->crtc;
1715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1716         struct drm_device *dev = encoder->dev;
1717         struct drm_i915_private *dev_priv = to_i915(dev);
1718         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1719         int type = intel_encoder->type;
1720
1721         if (type == INTEL_OUTPUT_HDMI) {
1722                 struct intel_digital_port *intel_dig_port =
1723                         enc_to_dig_port(encoder);
1724
1725                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1726                  * are ignored so nothing special needs to be done besides
1727                  * enabling the port.
1728                  */
1729                 I915_WRITE(DDI_BUF_CTL(port),
1730                            intel_dig_port->saved_port_bits |
1731                            DDI_BUF_CTL_ENABLE);
1732         } else if (type == INTEL_OUTPUT_EDP) {
1733                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1734
1735                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1736                         intel_dp_stop_link_train(intel_dp);
1737
1738                 intel_edp_backlight_on(intel_dp);
1739                 intel_psr_enable(intel_dp);
1740                 intel_edp_drrs_enable(intel_dp);
1741         }
1742
1743         if (intel_crtc->config->has_audio) {
1744                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1745                 intel_audio_codec_enable(intel_encoder);
1746         }
1747 }
1748
1749 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1750 {
1751         struct drm_encoder *encoder = &intel_encoder->base;
1752         struct drm_crtc *crtc = encoder->crtc;
1753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1754         int type = intel_encoder->type;
1755         struct drm_device *dev = encoder->dev;
1756         struct drm_i915_private *dev_priv = to_i915(dev);
1757
1758         if (intel_crtc->config->has_audio) {
1759                 intel_audio_codec_disable(intel_encoder);
1760                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1761         }
1762
1763         if (type == INTEL_OUTPUT_EDP) {
1764                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1765
1766                 intel_edp_drrs_disable(intel_dp);
1767                 intel_psr_disable(intel_dp);
1768                 intel_edp_backlight_off(intel_dp);
1769         }
1770 }
1771
1772 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1773                             enum dpio_phy phy)
1774 {
1775         enum port port;
1776
1777         if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1778                 return false;
1779
1780         if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1781              (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1782                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1783                                  phy);
1784
1785                 return false;
1786         }
1787
1788         if (phy == DPIO_PHY1 &&
1789             !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1790                 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1791
1792                 return false;
1793         }
1794
1795         if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1796                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1797                                  phy);
1798
1799                 return false;
1800         }
1801
1802         for_each_port_masked(port,
1803                              phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1804                                                 BIT(PORT_A)) {
1805                 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1806
1807                 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1808                         DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1809                                          "for port %c powered down "
1810                                          "(PHY_CTL %08x)\n",
1811                                          phy, port_name(port), tmp);
1812
1813                         return false;
1814                 }
1815         }
1816
1817         return true;
1818 }
1819
1820 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1821 {
1822         u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1823
1824         return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1825 }
1826
1827 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1828                                   enum dpio_phy phy)
1829 {
1830         if (intel_wait_for_register(dev_priv,
1831                                     BXT_PORT_REF_DW3(phy),
1832                                     GRC_DONE, GRC_DONE,
1833                                     10))
1834                 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1835 }
1836
1837 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1838 {
1839         u32 val;
1840
1841         if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
1842                 /* Still read out the GRC value for state verification */
1843                 if (phy == DPIO_PHY0)
1844                         dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
1845
1846                 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
1847                         DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1848                                          "won't reprogram it\n", phy);
1849
1850                         return;
1851                 }
1852
1853                 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1854                                  "force reprogramming it\n", phy);
1855         }
1856
1857         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1858         val |= GT_DISPLAY_POWER_ON(phy);
1859         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1860
1861         /*
1862          * The PHY registers start out inaccessible and respond to reads with
1863          * all 1s.  Eventually they become accessible as they power up, then
1864          * the reserved bit will give the default 0.  Poll on the reserved bit
1865          * becoming 0 to find when the PHY is accessible.
1866          * HW team confirmed that the time to reach phypowergood status is
1867          * anywhere between 50 us and 100us.
1868          */
1869         if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1870                 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
1871                 DRM_ERROR("timeout during PHY%d power on\n", phy);
1872         }
1873
1874         /* Program PLL Rcomp code offset */
1875         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1876         val &= ~IREF0RC_OFFSET_MASK;
1877         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1878         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1879
1880         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1881         val &= ~IREF1RC_OFFSET_MASK;
1882         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1883         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1884
1885         /* Program power gating */
1886         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1887         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1888                 SUS_CLK_CONFIG;
1889         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1890
1891         if (phy == DPIO_PHY0) {
1892                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1893                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1894                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1895         }
1896
1897         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1898         val &= ~OCL2_LDOFUSE_PWR_DIS;
1899         /*
1900          * On PHY1 disable power on the second channel, since no port is
1901          * connected there. On PHY0 both channels have a port, so leave it
1902          * enabled.
1903          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1904          * power down the second channel on PHY0 as well.
1905          *
1906          * FIXME: Clarify programming of the following, the register is
1907          * read-only with bit 6 fixed at 0 at least in stepping A.
1908          */
1909         if (phy == DPIO_PHY1)
1910                 val |= OCL2_LDOFUSE_PWR_DIS;
1911         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1912
1913         if (phy == DPIO_PHY0) {
1914                 uint32_t grc_code;
1915                 /*
1916                  * PHY0 isn't connected to an RCOMP resistor so copy over
1917                  * the corresponding calibrated value from PHY1, and disable
1918                  * the automatic calibration on PHY0.
1919                  */
1920                 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
1921                 grc_code = val << GRC_CODE_FAST_SHIFT |
1922                            val << GRC_CODE_SLOW_SHIFT |
1923                            val;
1924                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1925
1926                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1927                 val |= GRC_DIS | GRC_RDY_OVRD;
1928                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1929         }
1930
1931         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1932         val |= COMMON_RESET_DIS;
1933         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1934
1935         if (phy == DPIO_PHY1)
1936                 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
1937 }
1938
1939 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1940 {
1941         uint32_t val;
1942
1943         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1944         val &= ~COMMON_RESET_DIS;
1945         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1946
1947         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1948         val &= ~GT_DISPLAY_POWER_ON(phy);
1949         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1950 }
1951
1952 static bool __printf(6, 7)
1953 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1954                        i915_reg_t reg, u32 mask, u32 expected,
1955                        const char *reg_fmt, ...)
1956 {
1957         struct va_format vaf;
1958         va_list args;
1959         u32 val;
1960
1961         val = I915_READ(reg);
1962         if ((val & mask) == expected)
1963                 return true;
1964
1965         va_start(args, reg_fmt);
1966         vaf.fmt = reg_fmt;
1967         vaf.va = &args;
1968
1969         DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1970                          "current %08x, expected %08x (mask %08x)\n",
1971                          phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1972                          mask);
1973
1974         va_end(args);
1975
1976         return false;
1977 }
1978
1979 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1980                               enum dpio_phy phy)
1981 {
1982         uint32_t mask;
1983         bool ok;
1984
1985 #define _CHK(reg, mask, exp, fmt, ...)                                  \
1986         __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,      \
1987                                ## __VA_ARGS__)
1988
1989         if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
1990                 return false;
1991
1992         ok = true;
1993
1994         /* PLL Rcomp code offset */
1995         ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
1996                     IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
1997                     "BXT_PORT_CL1CM_DW9(%d)", phy);
1998         ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
1999                     IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2000                     "BXT_PORT_CL1CM_DW10(%d)", phy);
2001
2002         /* Power gating */
2003         mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2004         ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2005                     "BXT_PORT_CL1CM_DW28(%d)", phy);
2006
2007         if (phy == DPIO_PHY0)
2008                 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2009                            DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2010                            "BXT_PORT_CL2CM_DW6_BC");
2011
2012         /*
2013          * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2014          * at least on stepping A this bit is read-only and fixed at 0.
2015          */
2016
2017         if (phy == DPIO_PHY0) {
2018                 u32 grc_code = dev_priv->bxt_phy_grc;
2019
2020                 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2021                            grc_code << GRC_CODE_SLOW_SHIFT |
2022                            grc_code;
2023                 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2024                        GRC_CODE_NOM_MASK;
2025                 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2026                             "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2027
2028                 mask = GRC_DIS | GRC_RDY_OVRD;
2029                 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2030                             "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2031         }
2032
2033         return ok;
2034 #undef _CHK
2035 }
2036
2037 static uint8_t
2038 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2039                                      struct intel_crtc_state *pipe_config)
2040 {
2041         switch (pipe_config->lane_count) {
2042         case 1:
2043                 return 0;
2044         case 2:
2045                 return BIT(2) | BIT(0);
2046         case 4:
2047                 return BIT(3) | BIT(2) | BIT(0);
2048         default:
2049                 MISSING_CASE(pipe_config->lane_count);
2050
2051                 return 0;
2052         }
2053 }
2054
2055 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder)
2056 {
2057         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2058         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2059         enum port port = dport->port;
2060         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2061         int lane;
2062
2063         for (lane = 0; lane < 4; lane++) {
2064                 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2065
2066                 /*
2067                  * Note that on CHV this flag is called UPAR, but has
2068                  * the same function.
2069                  */
2070                 val &= ~LATENCY_OPTIM;
2071                 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2072                         val |= LATENCY_OPTIM;
2073
2074                 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2075         }
2076 }
2077
2078 static uint8_t
2079 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2080 {
2081         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2082         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2083         enum port port = dport->port;
2084         int lane;
2085         uint8_t mask;
2086
2087         mask = 0;
2088         for (lane = 0; lane < 4; lane++) {
2089                 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2090
2091                 if (val & LATENCY_OPTIM)
2092                         mask |= BIT(lane);
2093         }
2094
2095         return mask;
2096 }
2097
2098 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2099 {
2100         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2101         struct drm_i915_private *dev_priv =
2102                 to_i915(intel_dig_port->base.base.dev);
2103         enum port port = intel_dig_port->port;
2104         uint32_t val;
2105         bool wait = false;
2106
2107         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2108                 val = I915_READ(DDI_BUF_CTL(port));
2109                 if (val & DDI_BUF_CTL_ENABLE) {
2110                         val &= ~DDI_BUF_CTL_ENABLE;
2111                         I915_WRITE(DDI_BUF_CTL(port), val);
2112                         wait = true;
2113                 }
2114
2115                 val = I915_READ(DP_TP_CTL(port));
2116                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2117                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2118                 I915_WRITE(DP_TP_CTL(port), val);
2119                 POSTING_READ(DP_TP_CTL(port));
2120
2121                 if (wait)
2122                         intel_wait_ddi_buf_idle(dev_priv, port);
2123         }
2124
2125         val = DP_TP_CTL_ENABLE |
2126               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2127         if (intel_dp->link_mst)
2128                 val |= DP_TP_CTL_MODE_MST;
2129         else {
2130                 val |= DP_TP_CTL_MODE_SST;
2131                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2132                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2133         }
2134         I915_WRITE(DP_TP_CTL(port), val);
2135         POSTING_READ(DP_TP_CTL(port));
2136
2137         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2138         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2139         POSTING_READ(DDI_BUF_CTL(port));
2140
2141         udelay(600);
2142 }
2143
2144 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2145 {
2146         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2147         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2148         uint32_t val;
2149
2150         /*
2151          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2152          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2153          * step 13 is the correct place for it. Step 18 is where it was
2154          * originally before the BUN.
2155          */
2156         val = I915_READ(FDI_RX_CTL(PIPE_A));
2157         val &= ~FDI_RX_ENABLE;
2158         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2159
2160         intel_ddi_post_disable(intel_encoder);
2161
2162         val = I915_READ(FDI_RX_MISC(PIPE_A));
2163         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2164         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2165         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2166
2167         val = I915_READ(FDI_RX_CTL(PIPE_A));
2168         val &= ~FDI_PCDCLK;
2169         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2170
2171         val = I915_READ(FDI_RX_CTL(PIPE_A));
2172         val &= ~FDI_RX_PLL_ENABLE;
2173         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2174 }
2175
2176 void intel_ddi_get_config(struct intel_encoder *encoder,
2177                           struct intel_crtc_state *pipe_config)
2178 {
2179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2180         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2181         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2182         struct intel_hdmi *intel_hdmi;
2183         u32 temp, flags = 0;
2184
2185         /* XXX: DSI transcoder paranoia */
2186         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2187                 return;
2188
2189         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2190         if (temp & TRANS_DDI_PHSYNC)
2191                 flags |= DRM_MODE_FLAG_PHSYNC;
2192         else
2193                 flags |= DRM_MODE_FLAG_NHSYNC;
2194         if (temp & TRANS_DDI_PVSYNC)
2195                 flags |= DRM_MODE_FLAG_PVSYNC;
2196         else
2197                 flags |= DRM_MODE_FLAG_NVSYNC;
2198
2199         pipe_config->base.adjusted_mode.flags |= flags;
2200
2201         switch (temp & TRANS_DDI_BPC_MASK) {
2202         case TRANS_DDI_BPC_6:
2203                 pipe_config->pipe_bpp = 18;
2204                 break;
2205         case TRANS_DDI_BPC_8:
2206                 pipe_config->pipe_bpp = 24;
2207                 break;
2208         case TRANS_DDI_BPC_10:
2209                 pipe_config->pipe_bpp = 30;
2210                 break;
2211         case TRANS_DDI_BPC_12:
2212                 pipe_config->pipe_bpp = 36;
2213                 break;
2214         default:
2215                 break;
2216         }
2217
2218         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2219         case TRANS_DDI_MODE_SELECT_HDMI:
2220                 pipe_config->has_hdmi_sink = true;
2221                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2222
2223                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2224                         pipe_config->has_infoframe = true;
2225                 /* fall through */
2226         case TRANS_DDI_MODE_SELECT_DVI:
2227                 pipe_config->lane_count = 4;
2228                 break;
2229         case TRANS_DDI_MODE_SELECT_FDI:
2230                 break;
2231         case TRANS_DDI_MODE_SELECT_DP_SST:
2232         case TRANS_DDI_MODE_SELECT_DP_MST:
2233                 pipe_config->lane_count =
2234                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2235                 intel_dp_get_m_n(intel_crtc, pipe_config);
2236                 break;
2237         default:
2238                 break;
2239         }
2240
2241         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2242                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2243                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2244                         pipe_config->has_audio = true;
2245         }
2246
2247         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2248             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2249                 /*
2250                  * This is a big fat ugly hack.
2251                  *
2252                  * Some machines in UEFI boot mode provide us a VBT that has 18
2253                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2254                  * unknown we fail to light up. Yet the same BIOS boots up with
2255                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2256                  * max, not what it tells us to use.
2257                  *
2258                  * Note: This will still be broken if the eDP panel is not lit
2259                  * up by the BIOS, and thus we can't get the mode at module
2260                  * load.
2261                  */
2262                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2263                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2264                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2265         }
2266
2267         intel_ddi_clock_get(encoder, pipe_config);
2268
2269         if (IS_BROXTON(dev_priv))
2270                 pipe_config->lane_lat_optim_mask =
2271                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2272 }
2273
2274 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2275                                      struct intel_crtc_state *pipe_config)
2276 {
2277         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2278         int type = encoder->type;
2279         int port = intel_ddi_get_encoder_port(encoder);
2280         int ret;
2281
2282         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2283
2284         if (port == PORT_A)
2285                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2286
2287         if (type == INTEL_OUTPUT_HDMI)
2288                 ret = intel_hdmi_compute_config(encoder, pipe_config);
2289         else
2290                 ret = intel_dp_compute_config(encoder, pipe_config);
2291
2292         if (IS_BROXTON(dev_priv) && ret)
2293                 pipe_config->lane_lat_optim_mask =
2294                         bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2295                                                              pipe_config);
2296
2297         return ret;
2298
2299 }
2300
2301 static const struct drm_encoder_funcs intel_ddi_funcs = {
2302         .reset = intel_dp_encoder_reset,
2303         .destroy = intel_dp_encoder_destroy,
2304 };
2305
2306 static struct intel_connector *
2307 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2308 {
2309         struct intel_connector *connector;
2310         enum port port = intel_dig_port->port;
2311
2312         connector = intel_connector_alloc();
2313         if (!connector)
2314                 return NULL;
2315
2316         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2317         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2318                 kfree(connector);
2319                 return NULL;
2320         }
2321
2322         return connector;
2323 }
2324
2325 static struct intel_connector *
2326 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2327 {
2328         struct intel_connector *connector;
2329         enum port port = intel_dig_port->port;
2330
2331         connector = intel_connector_alloc();
2332         if (!connector)
2333                 return NULL;
2334
2335         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2336         intel_hdmi_init_connector(intel_dig_port, connector);
2337
2338         return connector;
2339 }
2340
2341 void intel_ddi_init(struct drm_device *dev, enum port port)
2342 {
2343         struct drm_i915_private *dev_priv = to_i915(dev);
2344         struct intel_digital_port *intel_dig_port;
2345         struct intel_encoder *intel_encoder;
2346         struct drm_encoder *encoder;
2347         bool init_hdmi, init_dp;
2348         int max_lanes;
2349
2350         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2351                 switch (port) {
2352                 case PORT_A:
2353                         max_lanes = 4;
2354                         break;
2355                 case PORT_E:
2356                         max_lanes = 0;
2357                         break;
2358                 default:
2359                         max_lanes = 4;
2360                         break;
2361                 }
2362         } else {
2363                 switch (port) {
2364                 case PORT_A:
2365                         max_lanes = 2;
2366                         break;
2367                 case PORT_E:
2368                         max_lanes = 2;
2369                         break;
2370                 default:
2371                         max_lanes = 4;
2372                         break;
2373                 }
2374         }
2375
2376         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2377                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2378         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2379         if (!init_dp && !init_hdmi) {
2380                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2381                               port_name(port));
2382                 return;
2383         }
2384
2385         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2386         if (!intel_dig_port)
2387                 return;
2388
2389         intel_encoder = &intel_dig_port->base;
2390         encoder = &intel_encoder->base;
2391
2392         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2393                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2394
2395         intel_encoder->compute_config = intel_ddi_compute_config;
2396         intel_encoder->enable = intel_enable_ddi;
2397         if (IS_BROXTON(dev_priv))
2398                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2399         intel_encoder->pre_enable = intel_ddi_pre_enable;
2400         intel_encoder->disable = intel_disable_ddi;
2401         intel_encoder->post_disable = intel_ddi_post_disable;
2402         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2403         intel_encoder->get_config = intel_ddi_get_config;
2404         intel_encoder->suspend = intel_dp_encoder_suspend;
2405
2406         intel_dig_port->port = port;
2407         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2408                                           (DDI_BUF_PORT_REVERSAL |
2409                                            DDI_A_4_LANES);
2410
2411         /*
2412          * Bspec says that DDI_A_4_LANES is the only supported configuration
2413          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2414          * wasn't lit up at boot.  Force this bit on in our internal
2415          * configuration so that we use the proper lane count for our
2416          * calculations.
2417          */
2418         if (IS_BROXTON(dev) && port == PORT_A) {
2419                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2420                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2421                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2422                         max_lanes = 4;
2423                 }
2424         }
2425
2426         intel_dig_port->max_lanes = max_lanes;
2427
2428         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2429         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2430         intel_encoder->cloneable = 0;
2431
2432         if (init_dp) {
2433                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2434                         goto err;
2435
2436                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2437                 /*
2438                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2439                  * interrupts to check the external panel connection.
2440                  */
2441                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
2442                         dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2443                 else
2444                         dev_priv->hotplug.irq_port[port] = intel_dig_port;
2445         }
2446
2447         /* In theory we don't need the encoder->type check, but leave it just in
2448          * case we have some really bad VBTs... */
2449         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2450                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2451                         goto err;
2452         }
2453
2454         return;
2455
2456 err:
2457         drm_encoder_cleanup(encoder);
2458         kfree(intel_dig_port);
2459 }