drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45 };
  46
  47 static const u32 hsw_ddi_translations_fdi[] = {
  48         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  49         0x00D75FFF, 0x000F000A,
  50         0x00C30FFF, 0x00060006,
  51         0x00AAAFFF, 0x001E0000,
  52         0x00FFFFFF, 0x000F000A,
  53         0x00D75FFF, 0x00160004,
  54         0x00C30FFF, 0x001E0000,
  55         0x00FFFFFF, 0x00060006,
  56         0x00D75FFF, 0x001E0000,
  57 };
  58
  59 static const u32 hsw_ddi_translations_hdmi[] = {
  60                                 /* Idx  NT mV diff      T mV diff       db  */
  61         0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
  62         0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
  63         0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
  64         0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
  65         0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
  66         0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
  67         0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
  68         0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
  69         0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
  70         0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
  71         0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
  72         0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
  73 };
  74
  75 static const u32 bdw_ddi_translations_edp[] = {
  76         0x00FFFFFF, 0x00000012,         /* eDP parameters */
  77         0x00EBAFFF, 0x00020011,
  78         0x00C71FFF, 0x0006000F,
  79         0x00AAAFFF, 0x000E000A,
  80         0x00FFFFFF, 0x00020011,
  81         0x00DB6FFF, 0x0005000F,
  82         0x00BEEFFF, 0x000A000C,
  83         0x00FFFFFF, 0x0005000F,
  84         0x00DB6FFF, 0x000A000C,
  85         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  86 };
  87
  88 static const u32 bdw_ddi_translations_dp[] = {
  89         0x00FFFFFF, 0x0007000E,         /* DP parameters */
  90         0x00D75FFF, 0x000E000A,
  91         0x00BEFFFF, 0x00140006,
  92         0x80B2CFFF, 0x001B0002,
  93         0x00FFFFFF, 0x000E000A,
  94         0x00D75FFF, 0x00180004,
  95         0x80CB2FFF, 0x001B0002,
  96         0x00F7DFFF, 0x00180004,
  97         0x80D75FFF, 0x001B0002,
  98         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  99 };
 100
 101 static const u32 bdw_ddi_translations_fdi[] = {
 102         0x00FFFFFF, 0x0001000E,         /* FDI parameters */
 103         0x00D75FFF, 0x0004000A,
 104         0x00C30FFF, 0x00070006,
 105         0x00AAAFFF, 0x000C0000,
 106         0x00FFFFFF, 0x0004000A,
 107         0x00D75FFF, 0x00090004,
 108         0x00C30FFF, 0x000C0000,
 109         0x00FFFFFF, 0x00070006,
 110         0x00D75FFF, 0x000C0000,
 111         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
 112 };
 113
 114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 115 {
 116         struct drm_encoder *encoder = &intel_encoder->base;
 117         int type = intel_encoder->type;
 118
 119         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 120             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 121                 struct intel_digital_port *intel_dig_port =
 122                         enc_to_dig_port(encoder);
 123                 return intel_dig_port->port;
 124
 125         } else if (type == INTEL_OUTPUT_ANALOG) {
 126                 return PORT_E;
 127
 128         } else {
 129                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 130                 BUG();
 131         }
 132 }
 133
 134 /*
 135  * Starting with Haswell, DDI port buffers must be programmed with correct
 136  * values in advance. The buffer values are different for FDI and DP modes,
 137  * but the HDMI/DVI fields are shared among those. So we program the DDI
 138  * in either FDI or DP modes only, as HDMI connections will work with both
 139  * of those
 140  */
 141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144         u32 reg;
 145         int i;
 146         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 147         const u32 *ddi_translations_fdi;
 148         const u32 *ddi_translations_dp;
 149         const u32 *ddi_translations_edp;
 150         const u32 *ddi_translations;
 151
 152         if (IS_BROADWELL(dev)) {
 153                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 154                 ddi_translations_dp = bdw_ddi_translations_dp;
 155                 ddi_translations_edp = bdw_ddi_translations_edp;
 156         } else if (IS_HASWELL(dev)) {
 157                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 158                 ddi_translations_dp = hsw_ddi_translations_dp;
 159                 ddi_translations_edp = hsw_ddi_translations_dp;
 160         } else {
 161                 WARN(1, "ddi translation table missing\n");
 162                 ddi_translations_edp = bdw_ddi_translations_dp;
 163                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 164                 ddi_translations_dp = bdw_ddi_translations_dp;
 165         }
 166
 167         switch (port) {
 168         case PORT_A:
 169                 ddi_translations = ddi_translations_edp;
 170                 break;
 171         case PORT_B:
 172         case PORT_C:
 173                 ddi_translations = ddi_translations_dp;
 174                 break;
 175         case PORT_D:
 176                 if (intel_dp_is_edp(dev, PORT_D))
 177                         ddi_translations = ddi_translations_edp;
 178                 else
 179                         ddi_translations = ddi_translations_dp;
 180                 break;
 181         case PORT_E:
 182                 ddi_translations = ddi_translations_fdi;
 183                 break;
 184         default:
 185                 BUG();
 186         }
 187
 188         for (i = 0, reg = DDI_BUF_TRANS(port);
 189              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 190                 I915_WRITE(reg, ddi_translations[i]);
 191                 reg += 4;
 192         }
 193         /* Entry 9 is for HDMI: */
 194         for (i = 0; i < 2; i++) {
 195                 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
 196                 reg += 4;
 197         }
 198 }
 199
 200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 201  * mode and port E for FDI.
 202  */
 203 void intel_prepare_ddi(struct drm_device *dev)
 204 {
 205         int port;
 206
 207         if (!HAS_DDI(dev))
 208                 return;
 209
 210         for (port = PORT_A; port <= PORT_E; port++)
 211                 intel_prepare_ddi_buffers(dev, port);
 212 }
 213
 214 static const long hsw_ddi_buf_ctl_values[] = {
 215         DDI_BUF_EMP_400MV_0DB_HSW,
 216         DDI_BUF_EMP_400MV_3_5DB_HSW,
 217         DDI_BUF_EMP_400MV_6DB_HSW,
 218         DDI_BUF_EMP_400MV_9_5DB_HSW,
 219         DDI_BUF_EMP_600MV_0DB_HSW,
 220         DDI_BUF_EMP_600MV_3_5DB_HSW,
 221         DDI_BUF_EMP_600MV_6DB_HSW,
 222         DDI_BUF_EMP_800MV_0DB_HSW,
 223         DDI_BUF_EMP_800MV_3_5DB_HSW
 224 };
 225
 226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 227                                     enum port port)
 228 {
 229         uint32_t reg = DDI_BUF_CTL(port);
 230         int i;
 231
 232         for (i = 0; i < 8; i++) {
 233                 udelay(1);
 234                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 235                         return;
 236         }
 237         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 238 }
 239
 240 /* Starting with Haswell, different DDI ports can work in FDI mode for
 241  * connection to the PCH-located connectors. For this, it is necessary to train
 242  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 243  *
 244  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 245  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 246  * DDI A (which is used for eDP)
 247  */
 248
 249 void hsw_fdi_link_train(struct drm_crtc *crtc)
 250 {
 251         struct drm_device *dev = crtc->dev;
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254         u32 temp, i, rx_ctl_val;
 255
 256         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 257          * mode set "sequence for CRT port" document:
 258          * - TP1 to TP2 time with the default value
 259          * - FDI delay to 90h
 260          *
 261          * WaFDIAutoLinkSetTimingOverrride:hsw
 262          */
 263         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 264                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 265                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 266
 267         /* Enable the PCH Receiver FDI PLL */
 268         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 269                      FDI_RX_PLL_ENABLE |
 270                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 271         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 272         POSTING_READ(_FDI_RXA_CTL);
 273         udelay(220);
 274
 275         /* Switch from Rawclk to PCDclk */
 276         rx_ctl_val |= FDI_PCDCLK;
 277         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 278
 279         /* Configure Port Clock Select */
 280         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 281         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 282
 283         /* Start the training iterating through available voltages and emphasis,
 284          * testing each value twice. */
 285         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 286                 /* Configure DP_TP_CTL with auto-training */
 287                 I915_WRITE(DP_TP_CTL(PORT_E),
 288                                         DP_TP_CTL_FDI_AUTOTRAIN |
 289                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 290                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 291                                         DP_TP_CTL_ENABLE);
 292
 293                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 294                  * DDI E does not support port reversal, the functionality is
 295                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 296                  * port reversal bit */
 297                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 298                            DDI_BUF_CTL_ENABLE |
 299                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 300                            hsw_ddi_buf_ctl_values[i / 2]);
 301                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 302
 303                 udelay(600);
 304
 305                 /* Program PCH FDI Receiver TU */
 306                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 307
 308                 /* Enable PCH FDI Receiver with auto-training */
 309                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 310                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 311                 POSTING_READ(_FDI_RXA_CTL);
 312
 313                 /* Wait for FDI receiver lane calibration */
 314                 udelay(30);
 315
 316                 /* Unset FDI_RX_MISC pwrdn lanes */
 317                 temp = I915_READ(_FDI_RXA_MISC);
 318                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 319                 I915_WRITE(_FDI_RXA_MISC, temp);
 320                 POSTING_READ(_FDI_RXA_MISC);
 321
 322                 /* Wait for FDI auto training time */
 323                 udelay(5);
 324
 325                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 326                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 327                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 328
 329                         /* Enable normal pixel sending for FDI */
 330                         I915_WRITE(DP_TP_CTL(PORT_E),
 331                                    DP_TP_CTL_FDI_AUTOTRAIN |
 332                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 333                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 334                                    DP_TP_CTL_ENABLE);
 335
 336                         return;
 337                 }
 338
 339                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 340                 temp &= ~DDI_BUF_CTL_ENABLE;
 341                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 342                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 343
 344                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 345                 temp = I915_READ(DP_TP_CTL(PORT_E));
 346                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 347                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 348                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 349                 POSTING_READ(DP_TP_CTL(PORT_E));
 350
 351                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 352
 353                 rx_ctl_val &= ~FDI_RX_ENABLE;
 354                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 355                 POSTING_READ(_FDI_RXA_CTL);
 356
 357                 /* Reset FDI_RX_MISC pwrdn lanes */
 358                 temp = I915_READ(_FDI_RXA_MISC);
 359                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 360                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 361                 I915_WRITE(_FDI_RXA_MISC, temp);
 362                 POSTING_READ(_FDI_RXA_MISC);
 363         }
 364
 365         DRM_ERROR("FDI link training failed!\n");
 366 }
 367
 368 static struct intel_encoder *
 369 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 370 {
 371         struct drm_device *dev = crtc->dev;
 372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 373         struct intel_encoder *intel_encoder, *ret = NULL;
 374         int num_encoders = 0;
 375
 376         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 377                 ret = intel_encoder;
 378                 num_encoders++;
 379         }
 380
 381         if (num_encoders != 1)
 382                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 383                      pipe_name(intel_crtc->pipe));
 384
 385         BUG_ON(ret == NULL);
 386         return ret;
 387 }
 388
 389 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 390 {
 391         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 392         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 394         uint32_t val;
 395
 396         switch (intel_crtc->config.ddi_pll_sel) {
 397         case PORT_CLK_SEL_WRPLL1:
 398                 plls->wrpll1_refcount--;
 399                 if (plls->wrpll1_refcount == 0) {
 400                         DRM_DEBUG_KMS("Disabling WRPLL 1\n");
 401                         val = I915_READ(WRPLL_CTL1);
 402                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 403                         I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 404                         POSTING_READ(WRPLL_CTL1);
 405                 }
 406                 break;
 407         case PORT_CLK_SEL_WRPLL2:
 408                 plls->wrpll2_refcount--;
 409                 if (plls->wrpll2_refcount == 0) {
 410                         DRM_DEBUG_KMS("Disabling WRPLL 2\n");
 411                         val = I915_READ(WRPLL_CTL2);
 412                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 413                         I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 414                         POSTING_READ(WRPLL_CTL2);
 415                 }
 416                 break;
 417         }
 418
 419         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 420         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 421
 422         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 423 }
 424
 425 #define LC_FREQ 2700
 426 #define LC_FREQ_2K (LC_FREQ * 2000)
 427
 428 #define P_MIN 2
 429 #define P_MAX 64
 430 #define P_INC 2
 431
 432 /* Constraints for PLL good behavior */
 433 #define REF_MIN 48
 434 #define REF_MAX 400
 435 #define VCO_MIN 2400
 436 #define VCO_MAX 4800
 437
 438 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 439
 440 struct wrpll_rnp {
 441         unsigned p, n2, r2;
 442 };
 443
 444 static unsigned wrpll_get_budget_for_freq(int clock)
 445 {
 446         unsigned budget;
 447
 448         switch (clock) {
 449         case 25175000:
 450         case 25200000:
 451         case 27000000:
 452         case 27027000:
 453         case 37762500:
 454         case 37800000:
 455         case 40500000:
 456         case 40541000:
 457         case 54000000:
 458         case 54054000:
 459         case 59341000:
 460         case 59400000:
 461         case 72000000:
 462         case 74176000:
 463         case 74250000:
 464         case 81000000:
 465         case 81081000:
 466         case 89012000:
 467         case 89100000:
 468         case 108000000:
 469         case 108108000:
 470         case 111264000:
 471         case 111375000:
 472         case 148352000:
 473         case 148500000:
 474         case 162000000:
 475         case 162162000:
 476         case 222525000:
 477         case 222750000:
 478         case 296703000:
 479         case 297000000:
 480                 budget = 0;
 481                 break;
 482         case 233500000:
 483         case 245250000:
 484         case 247750000:
 485         case 253250000:
 486         case 298000000:
 487                 budget = 1500;
 488                 break;
 489         case 169128000:
 490         case 169500000:
 491         case 179500000:
 492         case 202000000:
 493                 budget = 2000;
 494                 break;
 495         case 256250000:
 496         case 262500000:
 497         case 270000000:
 498         case 272500000:
 499         case 273750000:
 500         case 280750000:
 501         case 281250000:
 502         case 286000000:
 503         case 291750000:
 504                 budget = 4000;
 505                 break;
 506         case 267250000:
 507         case 268500000:
 508                 budget = 5000;
 509                 break;
 510         default:
 511                 budget = 1000;
 512                 break;
 513         }
 514
 515         return budget;
 516 }
 517
 518 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 519                              unsigned r2, unsigned n2, unsigned p,
 520                              struct wrpll_rnp *best)
 521 {
 522         uint64_t a, b, c, d, diff, diff_best;
 523
 524         /* No best (r,n,p) yet */
 525         if (best->p == 0) {
 526                 best->p = p;
 527                 best->n2 = n2;
 528                 best->r2 = r2;
 529                 return;
 530         }
 531
 532         /*
 533          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 534          * freq2k.
 535          *
 536          * delta = 1e6 *
 537          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 538          *         freq2k;
 539          *
 540          * and we would like delta <= budget.
 541          *
 542          * If the discrepancy is above the PPM-based budget, always prefer to
 543          * improve upon the previous solution.  However, if you're within the
 544          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 545          */
 546         a = freq2k * budget * p * r2;
 547         b = freq2k * budget * best->p * best->r2;
 548         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 549         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 550                              (LC_FREQ_2K * best->n2));
 551         c = 1000000 * diff;
 552         d = 1000000 * diff_best;
 553
 554         if (a < c && b < d) {
 555                 /* If both are above the budget, pick the closer */
 556                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 557                         best->p = p;
 558                         best->n2 = n2;
 559                         best->r2 = r2;
 560                 }
 561         } else if (a >= c && b < d) {
 562                 /* If A is below the threshold but B is above it?  Update. */
 563                 best->p = p;
 564                 best->n2 = n2;
 565                 best->r2 = r2;
 566         } else if (a >= c && b >= d) {
 567                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 568                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 569                         best->p = p;
 570                         best->n2 = n2;
 571                         best->r2 = r2;
 572                 }
 573         }
 574         /* Otherwise a < c && b >= d, do nothing */
 575 }
 576
 577 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 578                                      int reg)
 579 {
 580         int refclk = LC_FREQ;
 581         int n, p, r;
 582         u32 wrpll;
 583
 584         wrpll = I915_READ(reg);
 585         switch (wrpll & WRPLL_PLL_REF_MASK) {
 586         case WRPLL_PLL_SSC:
 587         case WRPLL_PLL_NON_SSC:
 588                 /*
 589                  * We could calculate spread here, but our checking
 590                  * code only cares about 5% accuracy, and spread is a max of
 591                  * 0.5% downspread.
 592                  */
 593                 refclk = 135;
 594                 break;
 595         case WRPLL_PLL_LCPLL:
 596                 refclk = LC_FREQ;
 597                 break;
 598         default:
 599                 WARN(1, "bad wrpll refclk\n");
 600                 return 0;
 601         }
 602
 603         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 604         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 605         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 606
 607         /* Convert to KHz, p & r have a fixed point portion */
 608         return (refclk * n * 100) / (p * r);
 609 }
 610
 611 static void intel_ddi_clock_get(struct intel_encoder *encoder,
 612                                 struct intel_crtc_config *pipe_config)
 613 {
 614         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 615         int link_clock = 0;
 616         u32 val, pll;
 617
 618         val = pipe_config->ddi_pll_sel;
 619         switch (val & PORT_CLK_SEL_MASK) {
 620         case PORT_CLK_SEL_LCPLL_810:
 621                 link_clock = 81000;
 622                 break;
 623         case PORT_CLK_SEL_LCPLL_1350:
 624                 link_clock = 135000;
 625                 break;
 626         case PORT_CLK_SEL_LCPLL_2700:
 627                 link_clock = 270000;
 628                 break;
 629         case PORT_CLK_SEL_WRPLL1:
 630                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 631                 break;
 632         case PORT_CLK_SEL_WRPLL2:
 633                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 634                 break;
 635         case PORT_CLK_SEL_SPLL:
 636                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 637                 if (pll == SPLL_PLL_FREQ_810MHz)
 638                         link_clock = 81000;
 639                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 640                         link_clock = 135000;
 641                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 642                         link_clock = 270000;
 643                 else {
 644                         WARN(1, "bad spll freq\n");
 645                         return;
 646                 }
 647                 break;
 648         default:
 649                 WARN(1, "bad port clock sel\n");
 650                 return;
 651         }
 652
 653         pipe_config->port_clock = link_clock * 2;
 654
 655         if (pipe_config->has_pch_encoder)
 656                 pipe_config->adjusted_mode.crtc_clock =
 657                         intel_dotclock_calculate(pipe_config->port_clock,
 658                                                  &pipe_config->fdi_m_n);
 659         else if (pipe_config->has_dp_encoder)
 660                 pipe_config->adjusted_mode.crtc_clock =
 661                         intel_dotclock_calculate(pipe_config->port_clock,
 662                                                  &pipe_config->dp_m_n);
 663         else
 664                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 665 }
 666
 667 static void
 668 intel_ddi_calculate_wrpll(int clock /* in Hz */,
 669                           unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 670 {
 671         uint64_t freq2k;
 672         unsigned p, n2, r2;
 673         struct wrpll_rnp best = { 0, 0, 0 };
 674         unsigned budget;
 675
 676         freq2k = clock / 100;
 677
 678         budget = wrpll_get_budget_for_freq(clock);
 679
 680         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 681          * and directly pass the LC PLL to it. */
 682         if (freq2k == 5400000) {
 683                 *n2_out = 2;
 684                 *p_out = 1;
 685                 *r2_out = 2;
 686                 return;
 687         }
 688
 689         /*
 690          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 691          * the WR PLL.
 692          *
 693          * We want R so that REF_MIN <= Ref <= REF_MAX.
 694          * Injecting R2 = 2 * R gives:
 695          *   REF_MAX * r2 > LC_FREQ * 2 and
 696          *   REF_MIN * r2 < LC_FREQ * 2
 697          *
 698          * Which means the desired boundaries for r2 are:
 699          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 700          *
 701          */
 702         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 703              r2 <= LC_FREQ * 2 / REF_MIN;
 704              r2++) {
 705
 706                 /*
 707                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 708                  *
 709                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 710                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 711                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 712                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 713                  *
 714                  * Which means the desired boundaries for n2 are:
 715                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 716                  */
 717                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 718                      n2 <= VCO_MAX * r2 / LC_FREQ;
 719                      n2++) {
 720
 721                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 722                                 wrpll_update_rnp(freq2k, budget,
 723                                                  r2, n2, p, &best);
 724                 }
 725         }
 726
 727         *n2_out = best.n2;
 728         *p_out = best.p;
 729         *r2_out = best.r2;
 730 }
 731
 732 /*
 733  * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
 734  * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
 735  * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
 736  * enable the PLL.
 737  */
 738 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 739 {
 740         struct drm_crtc *crtc = &intel_crtc->base;
 741         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 742         struct drm_encoder *encoder = &intel_encoder->base;
 743         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 744         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 745         int type = intel_encoder->type;
 746         enum pipe pipe = intel_crtc->pipe;
 747         int clock = intel_crtc->config.port_clock;
 748
 749         intel_ddi_put_crtc_pll(crtc);
 750
 751         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 752                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 753
 754                 switch (intel_dp->link_bw) {
 755                 case DP_LINK_BW_1_62:
 756                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 757                         break;
 758                 case DP_LINK_BW_2_7:
 759                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 760                         break;
 761                 case DP_LINK_BW_5_4:
 762                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 763                         break;
 764                 default:
 765                         DRM_ERROR("Link bandwidth %d unsupported\n",
 766                                   intel_dp->link_bw);
 767                         return false;
 768                 }
 769
 770         } else if (type == INTEL_OUTPUT_HDMI) {
 771                 uint32_t reg, val;
 772                 unsigned p, n2, r2;
 773
 774                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 775
 776                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 777                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 778                       WRPLL_DIVIDER_POST(p);
 779
 780                 if (val == I915_READ(WRPLL_CTL1)) {
 781                         DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
 782                                       pipe_name(pipe));
 783                         reg = WRPLL_CTL1;
 784                 } else if (val == I915_READ(WRPLL_CTL2)) {
 785                         DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
 786                                       pipe_name(pipe));
 787                         reg = WRPLL_CTL2;
 788                 } else if (plls->wrpll1_refcount == 0) {
 789                         DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
 790                                       pipe_name(pipe));
 791                         reg = WRPLL_CTL1;
 792                 } else if (plls->wrpll2_refcount == 0) {
 793                         DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
 794                                       pipe_name(pipe));
 795                         reg = WRPLL_CTL2;
 796                 } else {
 797                         DRM_ERROR("No WRPLLs available!\n");
 798                         return false;
 799                 }
 800
 801                 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
 802                               clock, p, n2, r2);
 803
 804                 if (reg == WRPLL_CTL1) {
 805                         plls->wrpll1_refcount++;
 806                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 807                 } else {
 808                         plls->wrpll2_refcount++;
 809                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 810                 }
 811
 812         } else if (type == INTEL_OUTPUT_ANALOG) {
 813                 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 814                               pipe_name(pipe));
 815                 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
 816         } else {
 817                 WARN(1, "Invalid DDI encoder type %d\n", type);
 818                 return false;
 819         }
 820
 821         return true;
 822 }
 823
 824 /*
 825  * To be called after intel_ddi_pll_select(). That one selects the PLL to be
 826  * used, this one actually enables the PLL.
 827  */
 828 void intel_ddi_pll_enable(struct intel_crtc *crtc)
 829 {
 830         struct drm_device *dev = crtc->base.dev;
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 833         int clock = crtc->config.port_clock;
 834         uint32_t reg, cur_val, new_val;
 835         int refcount;
 836         const char *pll_name;
 837         uint32_t enable_bit = (1 << 31);
 838         unsigned int p, n2, r2;
 839
 840         BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
 841         BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
 842
 843         switch (crtc->config.ddi_pll_sel) {
 844         case PORT_CLK_SEL_WRPLL1:
 845         case PORT_CLK_SEL_WRPLL2:
 846                 if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
 847                         pll_name = "WRPLL1";
 848                         reg = WRPLL_CTL1;
 849                         refcount = plls->wrpll1_refcount;
 850                 } else {
 851                         pll_name = "WRPLL2";
 852                         reg = WRPLL_CTL2;
 853                         refcount = plls->wrpll2_refcount;
 854                 }
 855
 856                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 857
 858                 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 859                           WRPLL_DIVIDER_REFERENCE(r2) |
 860                           WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
 861
 862                 break;
 863
 864         case PORT_CLK_SEL_NONE:
 865                 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
 866                 return;
 867         default:
 868                 return;
 869         }
 870
 871         cur_val = I915_READ(reg);
 872
 873         WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
 874         if (refcount == 1) {
 875                 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
 876                 I915_WRITE(reg, new_val);
 877                 POSTING_READ(reg);
 878                 udelay(20);
 879         } else {
 880                 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
 881         }
 882 }
 883
 884 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 885 {
 886         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 888         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 889         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 890         int type = intel_encoder->type;
 891         uint32_t temp;
 892
 893         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 894
 895                 temp = TRANS_MSA_SYNC_CLK;
 896                 switch (intel_crtc->config.pipe_bpp) {
 897                 case 18:
 898                         temp |= TRANS_MSA_6_BPC;
 899                         break;
 900                 case 24:
 901                         temp |= TRANS_MSA_8_BPC;
 902                         break;
 903                 case 30:
 904                         temp |= TRANS_MSA_10_BPC;
 905                         break;
 906                 case 36:
 907                         temp |= TRANS_MSA_12_BPC;
 908                         break;
 909                 default:
 910                         BUG();
 911                 }
 912                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 913         }
 914 }
 915
 916 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 917 {
 918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 919         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 920         struct drm_encoder *encoder = &intel_encoder->base;
 921         struct drm_device *dev = crtc->dev;
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923         enum pipe pipe = intel_crtc->pipe;
 924         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 925         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 926         int type = intel_encoder->type;
 927         uint32_t temp;
 928
 929         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 930         temp = TRANS_DDI_FUNC_ENABLE;
 931         temp |= TRANS_DDI_SELECT_PORT(port);
 932
 933         switch (intel_crtc->config.pipe_bpp) {
 934         case 18:
 935                 temp |= TRANS_DDI_BPC_6;
 936                 break;
 937         case 24:
 938                 temp |= TRANS_DDI_BPC_8;
 939                 break;
 940         case 30:
 941                 temp |= TRANS_DDI_BPC_10;
 942                 break;
 943         case 36:
 944                 temp |= TRANS_DDI_BPC_12;
 945                 break;
 946         default:
 947                 BUG();
 948         }
 949
 950         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 951                 temp |= TRANS_DDI_PVSYNC;
 952         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 953                 temp |= TRANS_DDI_PHSYNC;
 954
 955         if (cpu_transcoder == TRANSCODER_EDP) {
 956                 switch (pipe) {
 957                 case PIPE_A:
 958                         /* On Haswell, can only use the always-on power well for
 959                          * eDP when not using the panel fitter, and when not
 960                          * using motion blur mitigation (which we don't
 961                          * support). */
 962                         if (IS_HASWELL(dev) &&
 963                             (intel_crtc->config.pch_pfit.enabled ||
 964                              intel_crtc->config.pch_pfit.force_thru))
 965                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 966                         else
 967                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 968                         break;
 969                 case PIPE_B:
 970                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 971                         break;
 972                 case PIPE_C:
 973                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 974                         break;
 975                 default:
 976                         BUG();
 977                         break;
 978                 }
 979         }
 980
 981         if (type == INTEL_OUTPUT_HDMI) {
 982                 if (intel_crtc->config.has_hdmi_sink)
 983                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 984                 else
 985                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 986
 987         } else if (type == INTEL_OUTPUT_ANALOG) {
 988                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 989                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 990
 991         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 992                    type == INTEL_OUTPUT_EDP) {
 993                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 994
 995                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 996
 997                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 998         } else {
 999                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1000                      intel_encoder->type, pipe_name(pipe));
1001         }
1002
1003         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1004 }
1005
1006 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1007                                        enum transcoder cpu_transcoder)
1008 {
1009         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010         uint32_t val = I915_READ(reg);
1011
1012         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1013         val |= TRANS_DDI_PORT_NONE;
1014         I915_WRITE(reg, val);
1015 }
1016
1017 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1018 {
1019         struct drm_device *dev = intel_connector->base.dev;
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         struct intel_encoder *intel_encoder = intel_connector->encoder;
1022         int type = intel_connector->base.connector_type;
1023         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1024         enum pipe pipe = 0;
1025         enum transcoder cpu_transcoder;
1026         enum intel_display_power_domain power_domain;
1027         uint32_t tmp;
1028
1029         power_domain = intel_display_port_power_domain(intel_encoder);
1030         if (!intel_display_power_enabled(dev_priv, power_domain))
1031                 return false;
1032
1033         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1034                 return false;
1035
1036         if (port == PORT_A)
1037                 cpu_transcoder = TRANSCODER_EDP;
1038         else
1039                 cpu_transcoder = (enum transcoder) pipe;
1040
1041         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1042
1043         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1044         case TRANS_DDI_MODE_SELECT_HDMI:
1045         case TRANS_DDI_MODE_SELECT_DVI:
1046                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1047
1048         case TRANS_DDI_MODE_SELECT_DP_SST:
1049                 if (type == DRM_MODE_CONNECTOR_eDP)
1050                         return true;
1051         case TRANS_DDI_MODE_SELECT_DP_MST:
1052                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1053
1054         case TRANS_DDI_MODE_SELECT_FDI:
1055                 return (type == DRM_MODE_CONNECTOR_VGA);
1056
1057         default:
1058                 return false;
1059         }
1060 }
1061
1062 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1063                             enum pipe *pipe)
1064 {
1065         struct drm_device *dev = encoder->base.dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         enum port port = intel_ddi_get_encoder_port(encoder);
1068         enum intel_display_power_domain power_domain;
1069         u32 tmp;
1070         int i;
1071
1072         power_domain = intel_display_port_power_domain(encoder);
1073         if (!intel_display_power_enabled(dev_priv, power_domain))
1074                 return false;
1075
1076         tmp = I915_READ(DDI_BUF_CTL(port));
1077
1078         if (!(tmp & DDI_BUF_CTL_ENABLE))
1079                 return false;
1080
1081         if (port == PORT_A) {
1082                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1083
1084                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1085                 case TRANS_DDI_EDP_INPUT_A_ON:
1086                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1087                         *pipe = PIPE_A;
1088                         break;
1089                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1090                         *pipe = PIPE_B;
1091                         break;
1092                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1093                         *pipe = PIPE_C;
1094                         break;
1095                 }
1096
1097                 return true;
1098         } else {
1099                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1100                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1101
1102                         if ((tmp & TRANS_DDI_PORT_MASK)
1103                             == TRANS_DDI_SELECT_PORT(port)) {
1104                                 *pipe = i;
1105                                 return true;
1106                         }
1107                 }
1108         }
1109
1110         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1111
1112         return false;
1113 }
1114
1115 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1116 {
1117         struct drm_i915_private *dev_priv = dev->dev_private;
1118         enum pipe pipe;
1119         struct intel_crtc *intel_crtc;
1120
1121         dev_priv->ddi_plls.wrpll1_refcount = 0;
1122         dev_priv->ddi_plls.wrpll2_refcount = 0;
1123
1124         for_each_pipe(pipe) {
1125                 intel_crtc =
1126                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1127
1128                 if (!intel_crtc->active) {
1129                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
1130                         continue;
1131                 }
1132
1133                 switch (intel_crtc->config.ddi_pll_sel) {
1134                 case PORT_CLK_SEL_WRPLL1:
1135                         dev_priv->ddi_plls.wrpll1_refcount++;
1136                         break;
1137                 case PORT_CLK_SEL_WRPLL2:
1138                         dev_priv->ddi_plls.wrpll2_refcount++;
1139                         break;
1140                 }
1141         }
1142 }
1143
1144 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1145 {
1146         struct drm_crtc *crtc = &intel_crtc->base;
1147         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1148         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1149         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1150         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1151
1152         if (cpu_transcoder != TRANSCODER_EDP)
1153                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1154                            TRANS_CLK_SEL_PORT(port));
1155 }
1156
1157 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1158 {
1159         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1160         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1161
1162         if (cpu_transcoder != TRANSCODER_EDP)
1163                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1164                            TRANS_CLK_SEL_DISABLED);
1165 }
1166
1167 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1168 {
1169         struct drm_encoder *encoder = &intel_encoder->base;
1170         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1171         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1172         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1173         int type = intel_encoder->type;
1174
1175         if (crtc->config.has_audio) {
1176                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1177                                  pipe_name(crtc->pipe));
1178
1179                 /* write eld */
1180                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1181                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1182         }
1183
1184         if (type == INTEL_OUTPUT_EDP) {
1185                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1186                 intel_edp_panel_on(intel_dp);
1187         }
1188
1189         WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1190         I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1191
1192         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1193                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1194                 struct intel_digital_port *intel_dig_port =
1195                         enc_to_dig_port(encoder);
1196
1197                 intel_dp->DP = intel_dig_port->saved_port_bits |
1198                                DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
1199                 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1200
1201                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1202                 intel_dp_start_link_train(intel_dp);
1203                 intel_dp_complete_link_train(intel_dp);
1204                 if (port != PORT_A)
1205                         intel_dp_stop_link_train(intel_dp);
1206         } else if (type == INTEL_OUTPUT_HDMI) {
1207                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1208
1209                 intel_hdmi->set_infoframes(encoder,
1210                                            crtc->config.has_hdmi_sink,
1211                                            &crtc->config.adjusted_mode);
1212         }
1213 }
1214
1215 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1216 {
1217         struct drm_encoder *encoder = &intel_encoder->base;
1218         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1219         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1220         int type = intel_encoder->type;
1221         uint32_t val;
1222         bool wait = false;
1223
1224         val = I915_READ(DDI_BUF_CTL(port));
1225         if (val & DDI_BUF_CTL_ENABLE) {
1226                 val &= ~DDI_BUF_CTL_ENABLE;
1227                 I915_WRITE(DDI_BUF_CTL(port), val);
1228                 wait = true;
1229         }
1230
1231         val = I915_READ(DP_TP_CTL(port));
1232         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1233         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1234         I915_WRITE(DP_TP_CTL(port), val);
1235
1236         if (wait)
1237                 intel_wait_ddi_buf_idle(dev_priv, port);
1238
1239         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1240                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1241                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1242                 intel_edp_panel_vdd_on(intel_dp);
1243                 intel_edp_panel_off(intel_dp);
1244         }
1245
1246         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1247 }
1248
1249 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1250 {
1251         struct drm_encoder *encoder = &intel_encoder->base;
1252         struct drm_crtc *crtc = encoder->crtc;
1253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1254         int pipe = intel_crtc->pipe;
1255         struct drm_device *dev = encoder->dev;
1256         struct drm_i915_private *dev_priv = dev->dev_private;
1257         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1258         int type = intel_encoder->type;
1259         uint32_t tmp;
1260
1261         if (type == INTEL_OUTPUT_HDMI) {
1262                 struct intel_digital_port *intel_dig_port =
1263                         enc_to_dig_port(encoder);
1264
1265                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1266                  * are ignored so nothing special needs to be done besides
1267                  * enabling the port.
1268                  */
1269                 I915_WRITE(DDI_BUF_CTL(port),
1270                            intel_dig_port->saved_port_bits |
1271                            DDI_BUF_CTL_ENABLE);
1272         } else if (type == INTEL_OUTPUT_EDP) {
1273                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1274
1275                 if (port == PORT_A)
1276                         intel_dp_stop_link_train(intel_dp);
1277
1278                 intel_edp_backlight_on(intel_dp);
1279                 intel_edp_psr_enable(intel_dp);
1280         }
1281
1282         if (intel_crtc->config.has_audio) {
1283                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1284                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1285                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1286                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1287         }
1288 }
1289
1290 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1291 {
1292         struct drm_encoder *encoder = &intel_encoder->base;
1293         struct drm_crtc *crtc = encoder->crtc;
1294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1295         int pipe = intel_crtc->pipe;
1296         int type = intel_encoder->type;
1297         struct drm_device *dev = encoder->dev;
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         uint32_t tmp;
1300
1301         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1302          * register is part of the power well on Haswell. */
1303         if (intel_crtc->config.has_audio) {
1304                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1305                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1306                          (pipe * 4));
1307                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1308                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1309         }
1310
1311         if (type == INTEL_OUTPUT_EDP) {
1312                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1313
1314                 intel_edp_psr_disable(intel_dp);
1315                 intel_edp_backlight_off(intel_dp);
1316         }
1317 }
1318
1319 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1320 {
1321         struct drm_device *dev = dev_priv->dev;
1322         uint32_t lcpll = I915_READ(LCPLL_CTL);
1323         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1324
1325         if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1326                 return 800000;
1327         } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1328                 return 450000;
1329         } else if (freq == LCPLL_CLK_FREQ_450) {
1330                 return 450000;
1331         } else if (IS_HASWELL(dev)) {
1332                 if (IS_ULT(dev))
1333                         return 337500;
1334                 else
1335                         return 540000;
1336         } else {
1337                 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1338                         return 540000;
1339                 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1340                         return 337500;
1341                 else
1342                         return 675000;
1343         }
1344 }
1345
1346 void intel_ddi_pll_init(struct drm_device *dev)
1347 {
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         uint32_t val = I915_READ(LCPLL_CTL);
1350
1351         /* The LCPLL register should be turned on by the BIOS. For now let's
1352          * just check its state and print errors in case something is wrong.
1353          * Don't even try to turn it on.
1354          */
1355
1356         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1357                       intel_ddi_get_cdclk_freq(dev_priv));
1358
1359         if (val & LCPLL_CD_SOURCE_FCLK)
1360                 DRM_ERROR("CDCLK source is not LCPLL\n");
1361
1362         if (val & LCPLL_PLL_DISABLE)
1363                 DRM_ERROR("LCPLL is disabled\n");
1364 }
1365
1366 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1367 {
1368         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1369         struct intel_dp *intel_dp = &intel_dig_port->dp;
1370         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1371         enum port port = intel_dig_port->port;
1372         uint32_t val;
1373         bool wait = false;
1374
1375         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1376                 val = I915_READ(DDI_BUF_CTL(port));
1377                 if (val & DDI_BUF_CTL_ENABLE) {
1378                         val &= ~DDI_BUF_CTL_ENABLE;
1379                         I915_WRITE(DDI_BUF_CTL(port), val);
1380                         wait = true;
1381                 }
1382
1383                 val = I915_READ(DP_TP_CTL(port));
1384                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1385                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1386                 I915_WRITE(DP_TP_CTL(port), val);
1387                 POSTING_READ(DP_TP_CTL(port));
1388
1389                 if (wait)
1390                         intel_wait_ddi_buf_idle(dev_priv, port);
1391         }
1392
1393         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1394               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1395         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1396                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1397         I915_WRITE(DP_TP_CTL(port), val);
1398         POSTING_READ(DP_TP_CTL(port));
1399
1400         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1401         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1402         POSTING_READ(DDI_BUF_CTL(port));
1403
1404         udelay(600);
1405 }
1406
1407 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1408 {
1409         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1410         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1411         uint32_t val;
1412
1413         intel_ddi_post_disable(intel_encoder);
1414
1415         val = I915_READ(_FDI_RXA_CTL);
1416         val &= ~FDI_RX_ENABLE;
1417         I915_WRITE(_FDI_RXA_CTL, val);
1418
1419         val = I915_READ(_FDI_RXA_MISC);
1420         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1421         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1422         I915_WRITE(_FDI_RXA_MISC, val);
1423
1424         val = I915_READ(_FDI_RXA_CTL);
1425         val &= ~FDI_PCDCLK;
1426         I915_WRITE(_FDI_RXA_CTL, val);
1427
1428         val = I915_READ(_FDI_RXA_CTL);
1429         val &= ~FDI_RX_PLL_ENABLE;
1430         I915_WRITE(_FDI_RXA_CTL, val);
1431 }
1432
1433 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1434 {
1435         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1436         int type = intel_encoder->type;
1437
1438         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1439                 intel_dp_check_link_status(intel_dp);
1440 }
1441
1442 void intel_ddi_get_config(struct intel_encoder *encoder,
1443                           struct intel_crtc_config *pipe_config)
1444 {
1445         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1446         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1447         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1448         u32 temp, flags = 0;
1449
1450         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1451         if (temp & TRANS_DDI_PHSYNC)
1452                 flags |= DRM_MODE_FLAG_PHSYNC;
1453         else
1454                 flags |= DRM_MODE_FLAG_NHSYNC;
1455         if (temp & TRANS_DDI_PVSYNC)
1456                 flags |= DRM_MODE_FLAG_PVSYNC;
1457         else
1458                 flags |= DRM_MODE_FLAG_NVSYNC;
1459
1460         pipe_config->adjusted_mode.flags |= flags;
1461
1462         switch (temp & TRANS_DDI_BPC_MASK) {
1463         case TRANS_DDI_BPC_6:
1464                 pipe_config->pipe_bpp = 18;
1465                 break;
1466         case TRANS_DDI_BPC_8:
1467                 pipe_config->pipe_bpp = 24;
1468                 break;
1469         case TRANS_DDI_BPC_10:
1470                 pipe_config->pipe_bpp = 30;
1471                 break;
1472         case TRANS_DDI_BPC_12:
1473                 pipe_config->pipe_bpp = 36;
1474                 break;
1475         default:
1476                 break;
1477         }
1478
1479         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1480         case TRANS_DDI_MODE_SELECT_HDMI:
1481                 pipe_config->has_hdmi_sink = true;
1482         case TRANS_DDI_MODE_SELECT_DVI:
1483         case TRANS_DDI_MODE_SELECT_FDI:
1484                 break;
1485         case TRANS_DDI_MODE_SELECT_DP_SST:
1486         case TRANS_DDI_MODE_SELECT_DP_MST:
1487                 pipe_config->has_dp_encoder = true;
1488                 intel_dp_get_m_n(intel_crtc, pipe_config);
1489                 break;
1490         default:
1491                 break;
1492         }
1493
1494         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1495                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1496                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1497                         pipe_config->has_audio = true;
1498         }
1499
1500         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1501             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1502                 /*
1503                  * This is a big fat ugly hack.
1504                  *
1505                  * Some machines in UEFI boot mode provide us a VBT that has 18
1506                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1507                  * unknown we fail to light up. Yet the same BIOS boots up with
1508                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1509                  * max, not what it tells us to use.
1510                  *
1511                  * Note: This will still be broken if the eDP panel is not lit
1512                  * up by the BIOS, and thus we can't get the mode at module
1513                  * load.
1514                  */
1515                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1516                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1517                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1518         }
1519
1520         intel_ddi_clock_get(encoder, pipe_config);
1521 }
1522
1523 static void intel_ddi_destroy(struct drm_encoder *encoder)
1524 {
1525         /* HDMI has nothing special to destroy, so we can go with this. */
1526         intel_dp_encoder_destroy(encoder);
1527 }
1528
1529 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1530                                      struct intel_crtc_config *pipe_config)
1531 {
1532         int type = encoder->type;
1533         int port = intel_ddi_get_encoder_port(encoder);
1534
1535         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1536
1537         if (port == PORT_A)
1538                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1539
1540         if (type == INTEL_OUTPUT_HDMI)
1541                 return intel_hdmi_compute_config(encoder, pipe_config);
1542         else
1543                 return intel_dp_compute_config(encoder, pipe_config);
1544 }
1545
1546 static const struct drm_encoder_funcs intel_ddi_funcs = {
1547         .destroy = intel_ddi_destroy,
1548 };
1549
1550 static struct intel_connector *
1551 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1552 {
1553         struct intel_connector *connector;
1554         enum port port = intel_dig_port->port;
1555
1556         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1557         if (!connector)
1558                 return NULL;
1559
1560         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1561         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1562                 kfree(connector);
1563                 return NULL;
1564         }
1565
1566         return connector;
1567 }
1568
1569 static struct intel_connector *
1570 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1571 {
1572         struct intel_connector *connector;
1573         enum port port = intel_dig_port->port;
1574
1575         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1576         if (!connector)
1577                 return NULL;
1578
1579         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1580         intel_hdmi_init_connector(intel_dig_port, connector);
1581
1582         return connector;
1583 }
1584
1585 void intel_ddi_init(struct drm_device *dev, enum port port)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588         struct intel_digital_port *intel_dig_port;
1589         struct intel_encoder *intel_encoder;
1590         struct drm_encoder *encoder;
1591         struct intel_connector *hdmi_connector = NULL;
1592         struct intel_connector *dp_connector = NULL;
1593         bool init_hdmi, init_dp;
1594
1595         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1596                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1597         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1598         if (!init_dp && !init_hdmi) {
1599                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1600                               port_name(port));
1601                 init_hdmi = true;
1602                 init_dp = true;
1603         }
1604
1605         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1606         if (!intel_dig_port)
1607                 return;
1608
1609         intel_encoder = &intel_dig_port->base;
1610         encoder = &intel_encoder->base;
1611
1612         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1613                          DRM_MODE_ENCODER_TMDS);
1614
1615         intel_encoder->compute_config = intel_ddi_compute_config;
1616         intel_encoder->enable = intel_enable_ddi;
1617         intel_encoder->pre_enable = intel_ddi_pre_enable;
1618         intel_encoder->disable = intel_disable_ddi;
1619         intel_encoder->post_disable = intel_ddi_post_disable;
1620         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1621         intel_encoder->get_config = intel_ddi_get_config;
1622
1623         intel_dig_port->port = port;
1624         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1625                                           (DDI_BUF_PORT_REVERSAL |
1626                                            DDI_A_4_LANES);
1627
1628         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1629         intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
1630         intel_encoder->cloneable = 0;
1631         intel_encoder->hot_plug = intel_ddi_hot_plug;
1632
1633         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1634         dev_priv->hpd_irq_port[port] = intel_dig_port;
1635
1636         if (init_dp)
1637                 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
1638
1639         /* In theory we don't need the encoder->type check, but leave it just in
1640          * case we have some really bad VBTs... */
1641         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1642                 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
1643
1644         if (!dp_connector && !hdmi_connector) {
1645                 drm_encoder_cleanup(encoder);
1646                 kfree(intel_dig_port);
1647         }
1648 }