drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 int
 173 intel_pch_rawclk(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176
 177         WARN_ON(!HAS_PCH_SPLIT(dev));
 178
 179         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 180 }
 181
 182 /* hrawclock is 1/4 the FSB frequency */
 183 int intel_hrawclk(struct drm_device *dev)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         uint32_t clkcfg;
 187
 188         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 189         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 190                 return 200;
 191
 192         clkcfg = I915_READ(CLKCFG);
 193         switch (clkcfg & CLKCFG_FSB_MASK) {
 194         case CLKCFG_FSB_400:
 195                 return 100;
 196         case CLKCFG_FSB_533:
 197                 return 133;
 198         case CLKCFG_FSB_667:
 199                 return 166;
 200         case CLKCFG_FSB_800:
 201                 return 200;
 202         case CLKCFG_FSB_1067:
 203                 return 266;
 204         case CLKCFG_FSB_1333:
 205                 return 333;
 206         /* these two are just a guess; one of them might be right */
 207         case CLKCFG_FSB_1600:
 208         case CLKCFG_FSB_1600_ALT:
 209                 return 400;
 210         default:
 211                 return 133;
 212         }
 213 }
 214
 215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 216 {
 217         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 218                 return;
 219
 220         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 221                                                       CCK_CZ_CLOCK_CONTROL);
 222
 223         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 224 }
 225
 226 static inline u32 /* units of 100MHz */
 227 intel_fdi_link_freq(struct drm_device *dev)
 228 {
 229         if (IS_GEN5(dev)) {
 230                 struct drm_i915_private *dev_priv = dev->dev_private;
 231                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 232         } else
 233                 return 27;
 234 }
 235
 236 static const intel_limit_t intel_limits_i8xx_dac = {
 237         .dot = { .min = 25000, .max = 350000 },
 238         .vco = { .min = 908000, .max = 1512000 },
 239         .n = { .min = 2, .max = 16 },
 240         .m = { .min = 96, .max = 140 },
 241         .m1 = { .min = 18, .max = 26 },
 242         .m2 = { .min = 6, .max = 16 },
 243         .p = { .min = 4, .max = 128 },
 244         .p1 = { .min = 2, .max = 33 },
 245         .p2 = { .dot_limit = 165000,
 246                 .p2_slow = 4, .p2_fast = 2 },
 247 };
 248
 249 static const intel_limit_t intel_limits_i8xx_dvo = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 908000, .max = 1512000 },
 252         .n = { .min = 2, .max = 16 },
 253         .m = { .min = 96, .max = 140 },
 254         .m1 = { .min = 18, .max = 26 },
 255         .m2 = { .min = 6, .max = 16 },
 256         .p = { .min = 4, .max = 128 },
 257         .p1 = { .min = 2, .max = 33 },
 258         .p2 = { .dot_limit = 165000,
 259                 .p2_slow = 4, .p2_fast = 4 },
 260 };
 261
 262 static const intel_limit_t intel_limits_i8xx_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 1, .max = 6 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 14, .p2_fast = 7 },
 273 };
 274
 275 static const intel_limit_t intel_limits_i9xx_sdvo = {
 276         .dot = { .min = 20000, .max = 400000 },
 277         .vco = { .min = 1400000, .max = 2800000 },
 278         .n = { .min = 1, .max = 6 },
 279         .m = { .min = 70, .max = 120 },
 280         .m1 = { .min = 8, .max = 18 },
 281         .m2 = { .min = 3, .max = 7 },
 282         .p = { .min = 5, .max = 80 },
 283         .p1 = { .min = 1, .max = 8 },
 284         .p2 = { .dot_limit = 200000,
 285                 .p2_slow = 10, .p2_fast = 5 },
 286 };
 287
 288 static const intel_limit_t intel_limits_i9xx_lvds = {
 289         .dot = { .min = 20000, .max = 400000 },
 290         .vco = { .min = 1400000, .max = 2800000 },
 291         .n = { .min = 1, .max = 6 },
 292         .m = { .min = 70, .max = 120 },
 293         .m1 = { .min = 8, .max = 18 },
 294         .m2 = { .min = 3, .max = 7 },
 295         .p = { .min = 7, .max = 98 },
 296         .p1 = { .min = 1, .max = 8 },
 297         .p2 = { .dot_limit = 112000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301
 302 static const intel_limit_t intel_limits_g4x_sdvo = {
 303         .dot = { .min = 25000, .max = 270000 },
 304         .vco = { .min = 1750000, .max = 3500000},
 305         .n = { .min = 1, .max = 4 },
 306         .m = { .min = 104, .max = 138 },
 307         .m1 = { .min = 17, .max = 23 },
 308         .m2 = { .min = 5, .max = 11 },
 309         .p = { .min = 10, .max = 30 },
 310         .p1 = { .min = 1, .max = 3},
 311         .p2 = { .dot_limit = 270000,
 312                 .p2_slow = 10,
 313                 .p2_fast = 10
 314         },
 315 };
 316
 317 static const intel_limit_t intel_limits_g4x_hdmi = {
 318         .dot = { .min = 22000, .max = 400000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 16, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 5, .max = 80 },
 325         .p1 = { .min = 1, .max = 8},
 326         .p2 = { .dot_limit = 165000,
 327                 .p2_slow = 10, .p2_fast = 5 },
 328 };
 329
 330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 331         .dot = { .min = 20000, .max = 115000 },
 332         .vco = { .min = 1750000, .max = 3500000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 104, .max = 138 },
 335         .m1 = { .min = 17, .max = 23 },
 336         .m2 = { .min = 5, .max = 11 },
 337         .p = { .min = 28, .max = 112 },
 338         .p1 = { .min = 2, .max = 8 },
 339         .p2 = { .dot_limit = 0,
 340                 .p2_slow = 14, .p2_fast = 14
 341         },
 342 };
 343
 344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 345         .dot = { .min = 80000, .max = 224000 },
 346         .vco = { .min = 1750000, .max = 3500000 },
 347         .n = { .min = 1, .max = 3 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 17, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 14, .max = 42 },
 352         .p1 = { .min = 2, .max = 6 },
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 7, .p2_fast = 7
 355         },
 356 };
 357
 358 static const intel_limit_t intel_limits_pineview_sdvo = {
 359         .dot = { .min = 20000, .max = 400000},
 360         .vco = { .min = 1700000, .max = 3500000 },
 361         /* Pineview's Ncounter is a ring counter */
 362         .n = { .min = 3, .max = 6 },
 363         .m = { .min = 2, .max = 256 },
 364         /* Pineview only has one combined m divider, which we treat as m2. */
 365         .m1 = { .min = 0, .max = 0 },
 366         .m2 = { .min = 0, .max = 254 },
 367         .p = { .min = 5, .max = 80 },
 368         .p1 = { .min = 1, .max = 8 },
 369         .p2 = { .dot_limit = 200000,
 370                 .p2_slow = 10, .p2_fast = 5 },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_lvds = {
 374         .dot = { .min = 20000, .max = 400000 },
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         .n = { .min = 3, .max = 6 },
 377         .m = { .min = 2, .max = 256 },
 378         .m1 = { .min = 0, .max = 0 },
 379         .m2 = { .min = 0, .max = 254 },
 380         .p = { .min = 7, .max = 112 },
 381         .p1 = { .min = 1, .max = 8 },
 382         .p2 = { .dot_limit = 112000,
 383                 .p2_slow = 14, .p2_fast = 14 },
 384 };
 385
 386 /* Ironlake / Sandybridge
 387  *
 388  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 389  * the range value for them is (actual_value - 2).
 390  */
 391 static const intel_limit_t intel_limits_ironlake_dac = {
 392         .dot = { .min = 25000, .max = 350000 },
 393         .vco = { .min = 1760000, .max = 3510000 },
 394         .n = { .min = 1, .max = 5 },
 395         .m = { .min = 79, .max = 127 },
 396         .m1 = { .min = 12, .max = 22 },
 397         .m2 = { .min = 5, .max = 9 },
 398         .p = { .min = 5, .max = 80 },
 399         .p1 = { .min = 1, .max = 8 },
 400         .p2 = { .dot_limit = 225000,
 401                 .p2_slow = 10, .p2_fast = 5 },
 402 };
 403
 404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 405         .dot = { .min = 25000, .max = 350000 },
 406         .vco = { .min = 1760000, .max = 3510000 },
 407         .n = { .min = 1, .max = 3 },
 408         .m = { .min = 79, .max = 118 },
 409         .m1 = { .min = 12, .max = 22 },
 410         .m2 = { .min = 5, .max = 9 },
 411         .p = { .min = 28, .max = 112 },
 412         .p1 = { .min = 2, .max = 8 },
 413         .p2 = { .dot_limit = 225000,
 414                 .p2_slow = 14, .p2_fast = 14 },
 415 };
 416
 417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 3 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 14, .max = 56 },
 425         .p1 = { .min = 2, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 7, .p2_fast = 7 },
 428 };
 429
 430 /* LVDS 100mhz refclk limits. */
 431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 2 },
 435         .m = { .min = 79, .max = 126 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 126 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 42 },
 452         .p1 = { .min = 2, .max = 6 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 static const intel_limit_t intel_limits_vlv = {
 458          /*
 459           * These are the data rate limits (measured in fast clocks)
 460           * since those are the strictest limits we have. The fast
 461           * clock and actual rate limits are more relaxed, so checking
 462           * them would make no difference.
 463           */
 464         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 465         .vco = { .min = 4000000, .max = 6000000 },
 466         .n = { .min = 1, .max = 7 },
 467         .m1 = { .min = 2, .max = 3 },
 468         .m2 = { .min = 11, .max = 156 },
 469         .p1 = { .min = 2, .max = 3 },
 470         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 471 };
 472
 473 static const intel_limit_t intel_limits_chv = {
 474         /*
 475          * These are the data rate limits (measured in fast clocks)
 476          * since those are the strictest limits we have.  The fast
 477          * clock and actual rate limits are more relaxed, so checking
 478          * them would make no difference.
 479          */
 480         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 481         .vco = { .min = 4800000, .max = 6480000 },
 482         .n = { .min = 1, .max = 1 },
 483         .m1 = { .min = 2, .max = 2 },
 484         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 485         .p1 = { .min = 2, .max = 4 },
 486         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 487 };
 488
 489 static const intel_limit_t intel_limits_bxt = {
 490         /* FIXME: find real dot limits */
 491         .dot = { .min = 0, .max = INT_MAX },
 492         .vco = { .min = 4800000, .max = 6700000 },
 493         .n = { .min = 1, .max = 1 },
 494         .m1 = { .min = 2, .max = 2 },
 495         /* FIXME: find real m2 limits */
 496         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 497         .p1 = { .min = 2, .max = 4 },
 498         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 499 };
 500
 501 static bool
 502 needs_modeset(struct drm_crtc_state *state)
 503 {
 504         return drm_atomic_crtc_needs_modeset(state);
 505 }
 506
 507 /**
 508  * Returns whether any output on the specified pipe is of the specified type
 509  */
 510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 511 {
 512         struct drm_device *dev = crtc->base.dev;
 513         struct intel_encoder *encoder;
 514
 515         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 516                 if (encoder->type == type)
 517                         return true;
 518
 519         return false;
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe will have the specified
 524  * type after a staged modeset is complete, i.e., the same as
 525  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 526  * encoder->crtc.
 527  */
 528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 529                                       int type)
 530 {
 531         struct drm_atomic_state *state = crtc_state->base.state;
 532         struct drm_connector *connector;
 533         struct drm_connector_state *connector_state;
 534         struct intel_encoder *encoder;
 535         int i, num_connectors = 0;
 536
 537         for_each_connector_in_state(state, connector, connector_state, i) {
 538                 if (connector_state->crtc != crtc_state->base.crtc)
 539                         continue;
 540
 541                 num_connectors++;
 542
 543                 encoder = to_intel_encoder(connector_state->best_encoder);
 544                 if (encoder->type == type)
 545                         return true;
 546         }
 547
 548         WARN_ON(num_connectors == 0);
 549
 550         return false;
 551 }
 552
 553 static const intel_limit_t *
 554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 555 {
 556         struct drm_device *dev = crtc_state->base.crtc->dev;
 557         const intel_limit_t *limit;
 558
 559         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 560                 if (intel_is_dual_link_lvds(dev)) {
 561                         if (refclk == 100000)
 562                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 563                         else
 564                                 limit = &intel_limits_ironlake_dual_lvds;
 565                 } else {
 566                         if (refclk == 100000)
 567                                 limit = &intel_limits_ironlake_single_lvds_100m;
 568                         else
 569                                 limit = &intel_limits_ironlake_single_lvds;
 570                 }
 571         } else
 572                 limit = &intel_limits_ironlake_dac;
 573
 574         return limit;
 575 }
 576
 577 static const intel_limit_t *
 578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 579 {
 580         struct drm_device *dev = crtc_state->base.crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 584                 if (intel_is_dual_link_lvds(dev))
 585                         limit = &intel_limits_g4x_dual_channel_lvds;
 586                 else
 587                         limit = &intel_limits_g4x_single_channel_lvds;
 588         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 589                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 590                 limit = &intel_limits_g4x_hdmi;
 591         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 592                 limit = &intel_limits_g4x_sdvo;
 593         } else /* The option is for other outputs */
 594                 limit = &intel_limits_i9xx_sdvo;
 595
 596         return limit;
 597 }
 598
 599 static const intel_limit_t *
 600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 601 {
 602         struct drm_device *dev = crtc_state->base.crtc->dev;
 603         const intel_limit_t *limit;
 604
 605         if (IS_BROXTON(dev))
 606                 limit = &intel_limits_bxt;
 607         else if (HAS_PCH_SPLIT(dev))
 608                 limit = intel_ironlake_limit(crtc_state, refclk);
 609         else if (IS_G4X(dev)) {
 610                 limit = intel_g4x_limit(crtc_state);
 611         } else if (IS_PINEVIEW(dev)) {
 612                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 613                         limit = &intel_limits_pineview_lvds;
 614                 else
 615                         limit = &intel_limits_pineview_sdvo;
 616         } else if (IS_CHERRYVIEW(dev)) {
 617                 limit = &intel_limits_chv;
 618         } else if (IS_VALLEYVIEW(dev)) {
 619                 limit = &intel_limits_vlv;
 620         } else if (!IS_GEN2(dev)) {
 621                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 622                         limit = &intel_limits_i9xx_lvds;
 623                 else
 624                         limit = &intel_limits_i9xx_sdvo;
 625         } else {
 626                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 627                         limit = &intel_limits_i8xx_lvds;
 628                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 629                         limit = &intel_limits_i8xx_dvo;
 630                 else
 631                         limit = &intel_limits_i8xx_dac;
 632         }
 633         return limit;
 634 }
 635
 636 /*
 637  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 638  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 639  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 640  * The helpers' return value is the rate of the clock that is fed to the
 641  * display engine's pipe which can be the above fast dot clock rate or a
 642  * divided-down version of it.
 643  */
 644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 646 {
 647         clock->m = clock->m2 + 2;
 648         clock->p = clock->p1 * clock->p2;
 649         if (WARN_ON(clock->n == 0 || clock->p == 0))
 650                 return 0;
 651         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 652         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 653
 654         return clock->dot;
 655 }
 656
 657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 658 {
 659         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 660 }
 661
 662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 663 {
 664         clock->m = i9xx_dpll_compute_m(clock);
 665         clock->p = clock->p1 * clock->p2;
 666         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 667                 return 0;
 668         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 669         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 670
 671         return clock->dot;
 672 }
 673
 674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 675 {
 676         clock->m = clock->m1 * clock->m2;
 677         clock->p = clock->p1 * clock->p2;
 678         if (WARN_ON(clock->n == 0 || clock->p == 0))
 679                 return 0;
 680         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 681         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 682
 683         return clock->dot / 5;
 684 }
 685
 686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 687 {
 688         clock->m = clock->m1 * clock->m2;
 689         clock->p = clock->p1 * clock->p2;
 690         if (WARN_ON(clock->n == 0 || clock->p == 0))
 691                 return 0;
 692         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 693                         clock->n << 22);
 694         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 695
 696         return clock->dot / 5;
 697 }
 698
 699 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 700 /**
 701  * Returns whether the given set of divisors are valid for a given refclk with
 702  * the given connectors.
 703  */
 704
 705 static bool intel_PLL_is_valid(struct drm_device *dev,
 706                                const intel_limit_t *limit,
 707                                const intel_clock_t *clock)
 708 {
 709         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 710                 INTELPllInvalid("n out of range\n");
 711         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 712                 INTELPllInvalid("p1 out of range\n");
 713         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 714                 INTELPllInvalid("m2 out of range\n");
 715         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 716                 INTELPllInvalid("m1 out of range\n");
 717
 718         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 719             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 static const char *state_string(bool enabled)
1154 {
1155         return enabled ? "on" : "off";
1156 }
1157
1158 /* Only for pre-ILK configs */
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state)
1161 {
1162         u32 val;
1163         bool cur_state;
1164
1165         val = I915_READ(DPLL(pipe));
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         if (HAS_DDI(dev_priv->dev)) {
1227                 /* DDI does not have a specific FDI_TX register */
1228                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1229                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1230         } else {
1231                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1232                 cur_state = !!(val & FDI_TX_ENABLE);
1233         }
1234         I915_STATE_WARN(cur_state != state,
1235              "FDI TX state assertion failure (expected %s, current %s)\n",
1236              state_string(state), state_string(cur_state));
1237 }
1238 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1239 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1240
1241 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1242                           enum pipe pipe, bool state)
1243 {
1244         u32 val;
1245         bool cur_state;
1246
1247         val = I915_READ(FDI_RX_CTL(pipe));
1248         cur_state = !!(val & FDI_RX_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX state assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1254 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1255
1256 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1257                                       enum pipe pipe)
1258 {
1259         u32 val;
1260
1261         /* ILK FDI PLL is always enabled */
1262         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263                 return;
1264
1265         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1266         if (HAS_DDI(dev_priv->dev))
1267                 return;
1268
1269         val = I915_READ(FDI_TX_CTL(pipe));
1270         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 }
1272
1273 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1274                        enum pipe pipe, bool state)
1275 {
1276         u32 val;
1277         bool cur_state;
1278
1279         val = I915_READ(FDI_RX_CTL(pipe));
1280         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1281         I915_STATE_WARN(cur_state != state,
1282              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1283              state_string(state), state_string(cur_state));
1284 }
1285
1286 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287                            enum pipe pipe)
1288 {
1289         struct drm_device *dev = dev_priv->dev;
1290         i915_reg_t pp_reg;
1291         u32 val;
1292         enum pipe panel_pipe = PIPE_A;
1293         bool locked = true;
1294
1295         if (WARN_ON(HAS_DDI(dev)))
1296                 return;
1297
1298         if (HAS_PCH_SPLIT(dev)) {
1299                 u32 port_sel;
1300
1301                 pp_reg = PCH_PP_CONTROL;
1302                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1303
1304                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1305                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1306                         panel_pipe = PIPE_B;
1307                 /* XXX: else fix for eDP */
1308         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1309                 /* presumably write lock depends on pipe, not port select */
1310                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311                 panel_pipe = pipe;
1312         } else {
1313                 pp_reg = PP_CONTROL;
1314                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1315                         panel_pipe = PIPE_B;
1316         }
1317
1318         val = I915_READ(pp_reg);
1319         if (!(val & PANEL_POWER_ON) ||
1320             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321                 locked = false;
1322
1323         I915_STATE_WARN(panel_pipe == pipe && locked,
1324              "panel assertion failure, pipe %c regs locked\n",
1325              pipe_name(pipe));
1326 }
1327
1328 static void assert_cursor(struct drm_i915_private *dev_priv,
1329                           enum pipe pipe, bool state)
1330 {
1331         struct drm_device *dev = dev_priv->dev;
1332         bool cur_state;
1333
1334         if (IS_845G(dev) || IS_I865G(dev))
1335                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1336         else
1337                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1338
1339         I915_STATE_WARN(cur_state != state,
1340              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1341              pipe_name(pipe), state_string(state), state_string(cur_state));
1342 }
1343 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1344 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1345
1346 void assert_pipe(struct drm_i915_private *dev_priv,
1347                  enum pipe pipe, bool state)
1348 {
1349         bool cur_state;
1350         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351                                                                       pipe);
1352
1353         /* if we need the pipe quirk it must be always on */
1354         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1355             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356                 state = true;
1357
1358         if (!intel_display_power_is_enabled(dev_priv,
1359                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360                 cur_state = false;
1361         } else {
1362                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1363                 cur_state = !!(val & PIPECONF_ENABLE);
1364         }
1365
1366         I915_STATE_WARN(cur_state != state,
1367              "pipe %c assertion failure (expected %s, current %s)\n",
1368              pipe_name(pipe), state_string(state), state_string(cur_state));
1369 }
1370
1371 static void assert_plane(struct drm_i915_private *dev_priv,
1372                          enum plane plane, bool state)
1373 {
1374         u32 val;
1375         bool cur_state;
1376
1377         val = I915_READ(DSPCNTR(plane));
1378         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1379         I915_STATE_WARN(cur_state != state,
1380              "plane %c assertion failure (expected %s, current %s)\n",
1381              plane_name(plane), state_string(state), state_string(cur_state));
1382 }
1383
1384 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1385 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1386
1387 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388                                    enum pipe pipe)
1389 {
1390         struct drm_device *dev = dev_priv->dev;
1391         int i;
1392
1393         /* Primary planes are fixed to pipes on gen4+ */
1394         if (INTEL_INFO(dev)->gen >= 4) {
1395                 u32 val = I915_READ(DSPCNTR(pipe));
1396                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1397                      "plane %c assertion failure, should be disabled but not\n",
1398                      plane_name(pipe));
1399                 return;
1400         }
1401
1402         /* Need to check both planes against the pipe */
1403         for_each_pipe(dev_priv, i) {
1404                 u32 val = I915_READ(DSPCNTR(i));
1405                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1406                         DISPPLANE_SEL_PIPE_SHIFT;
1407                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1408                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(i), pipe_name(pipe));
1410         }
1411 }
1412
1413 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414                                     enum pipe pipe)
1415 {
1416         struct drm_device *dev = dev_priv->dev;
1417         int sprite;
1418
1419         if (INTEL_INFO(dev)->gen >= 9) {
1420                 for_each_sprite(dev_priv, pipe, sprite) {
1421                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1422                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1423                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1424                              sprite, pipe_name(pipe));
1425                 }
1426         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1427                 for_each_sprite(dev_priv, pipe, sprite) {
1428                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1429                         I915_STATE_WARN(val & SP_ENABLE,
1430                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                              sprite_name(pipe, sprite), pipe_name(pipe));
1432                 }
1433         } else if (INTEL_INFO(dev)->gen >= 7) {
1434                 u32 val = I915_READ(SPRCTL(pipe));
1435                 I915_STATE_WARN(val & SPRITE_ENABLE,
1436                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1437                      plane_name(pipe), pipe_name(pipe));
1438         } else if (INTEL_INFO(dev)->gen >= 5) {
1439                 u32 val = I915_READ(DVSCNTR(pipe));
1440                 I915_STATE_WARN(val & DVS_ENABLE,
1441                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442                      plane_name(pipe), pipe_name(pipe));
1443         }
1444 }
1445
1446 static void assert_vblank_disabled(struct drm_crtc *crtc)
1447 {
1448         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1449                 drm_crtc_vblank_put(crtc);
1450 }
1451
1452 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1453 {
1454         u32 val;
1455         bool enabled;
1456
1457         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1458
1459         val = I915_READ(PCH_DREF_CONTROL);
1460         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1461                             DREF_SUPERSPREAD_SOURCE_MASK));
1462         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 }
1464
1465 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1466                                            enum pipe pipe)
1467 {
1468         u32 val;
1469         bool enabled;
1470
1471         val = I915_READ(PCH_TRANSCONF(pipe));
1472         enabled = !!(val & TRANS_ENABLE);
1473         I915_STATE_WARN(enabled,
1474              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1475              pipe_name(pipe));
1476 }
1477
1478 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1479                             enum pipe pipe, u32 port_sel, u32 val)
1480 {
1481         if ((val & DP_PORT_EN) == 0)
1482                 return false;
1483
1484         if (HAS_PCH_CPT(dev_priv->dev)) {
1485                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1486                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487                         return false;
1488         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490                         return false;
1491         } else {
1492                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1493                         return false;
1494         }
1495         return true;
1496 }
1497
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499                               enum pipe pipe, u32 val)
1500 {
1501         if ((val & SDVO_ENABLE) == 0)
1502                 return false;
1503
1504         if (HAS_PCH_CPT(dev_priv->dev)) {
1505                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506                         return false;
1507         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & LVDS_PORT_EN) == 0)
1521                 return false;
1522
1523         if (HAS_PCH_CPT(dev_priv->dev)) {
1524                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525                         return false;
1526         } else {
1527                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528                         return false;
1529         }
1530         return true;
1531 }
1532
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534                               enum pipe pipe, u32 val)
1535 {
1536         if ((val & ADPA_DAC_ENABLE) == 0)
1537                 return false;
1538         if (HAS_PCH_CPT(dev_priv->dev)) {
1539                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540                         return false;
1541         } else {
1542                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543                         return false;
1544         }
1545         return true;
1546 }
1547
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549                                    enum pipe pipe, i915_reg_t reg,
1550                                    u32 port_sel)
1551 {
1552         u32 val = I915_READ(reg);
1553         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1554              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1555              i915_mmio_reg_offset(reg), pipe_name(pipe));
1556
1557         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1558              && (val & DP_PIPEB_SELECT),
1559              "IBX PCH dp port still using transcoder B\n");
1560 }
1561
1562 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1563                                      enum pipe pipe, i915_reg_t reg)
1564 {
1565         u32 val = I915_READ(reg);
1566         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1567              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1568              i915_mmio_reg_offset(reg), pipe_name(pipe));
1569
1570         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1571              && (val & SDVO_PIPE_B_SELECT),
1572              "IBX PCH hdmi port still using transcoder B\n");
1573 }
1574
1575 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576                                       enum pipe pipe)
1577 {
1578         u32 val;
1579
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1581         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1582         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1583
1584         val = I915_READ(PCH_ADPA);
1585         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1586              "PCH VGA enabled on transcoder %c, should be disabled\n",
1587              pipe_name(pipe));
1588
1589         val = I915_READ(PCH_LVDS);
1590         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1591              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592              pipe_name(pipe));
1593
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1595         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1596         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 }
1598
1599 static void vlv_enable_pll(struct intel_crtc *crtc,
1600                            const struct intel_crtc_state *pipe_config)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         i915_reg_t reg = DPLL(crtc->pipe);
1605         u32 dpll = pipe_config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev_priv->dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         I915_WRITE(reg, dpll);
1614         POSTING_READ(reg);
1615         udelay(150);
1616
1617         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1618                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1619
1620         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1621         POSTING_READ(DPLL_MD(crtc->pipe));
1622
1623         /* We do this three times for luck */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150); /* wait for warmup */
1633 }
1634
1635 static void chv_enable_pll(struct intel_crtc *crtc,
1636                            const struct intel_crtc_state *pipe_config)
1637 {
1638         struct drm_device *dev = crtc->base.dev;
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640         int pipe = crtc->pipe;
1641         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1642         u32 tmp;
1643
1644         assert_pipe_disabled(dev_priv, crtc->pipe);
1645
1646         mutex_lock(&dev_priv->sb_lock);
1647
1648         /* Enable back the 10bit clock to display controller */
1649         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1650         tmp |= DPIO_DCLKP_EN;
1651         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1652
1653         mutex_unlock(&dev_priv->sb_lock);
1654
1655         /*
1656          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1657          */
1658         udelay(1);
1659
1660         /* Enable PLL */
1661         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1662
1663         /* Check PLL is locked */
1664         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1665                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1666
1667         /* not sure when this should be written */
1668         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1669         POSTING_READ(DPLL_MD(pipe));
1670 }
1671
1672 static int intel_num_dvo_pipes(struct drm_device *dev)
1673 {
1674         struct intel_crtc *crtc;
1675         int count = 0;
1676
1677         for_each_intel_crtc(dev, crtc)
1678                 count += crtc->base.state->active &&
1679                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1680
1681         return count;
1682 }
1683
1684 static void i9xx_enable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         i915_reg_t reg = DPLL(crtc->pipe);
1689         u32 dpll = crtc->config->dpll_hw_state.dpll;
1690
1691         assert_pipe_disabled(dev_priv, crtc->pipe);
1692
1693         /* No really, not for ILK+ */
1694         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1695
1696         /* PLL is protected by panel, make sure we can write it */
1697         if (IS_MOBILE(dev) && !IS_I830(dev))
1698                 assert_panel_unlocked(dev_priv, crtc->pipe);
1699
1700         /* Enable DVO 2x clock on both PLLs if necessary */
1701         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1702                 /*
1703                  * It appears to be important that we don't enable this
1704                  * for the current pipe before otherwise configuring the
1705                  * PLL. No idea how this should be handled if multiple
1706                  * DVO outputs are enabled simultaneosly.
1707                  */
1708                 dpll |= DPLL_DVO_2X_MODE;
1709                 I915_WRITE(DPLL(!crtc->pipe),
1710                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1711         }
1712
1713         /*
1714          * Apparently we need to have VGA mode enabled prior to changing
1715          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1716          * dividers, even though the register value does change.
1717          */
1718         I915_WRITE(reg, 0);
1719
1720         I915_WRITE(reg, dpll);
1721
1722         /* Wait for the clocks to stabilize. */
1723         POSTING_READ(reg);
1724         udelay(150);
1725
1726         if (INTEL_INFO(dev)->gen >= 4) {
1727                 I915_WRITE(DPLL_MD(crtc->pipe),
1728                            crtc->config->dpll_hw_state.dpll_md);
1729         } else {
1730                 /* The pixel multiplier can only be updated once the
1731                  * DPLL is enabled and the clocks are stable.
1732                  *
1733                  * So write it again.
1734                  */
1735                 I915_WRITE(reg, dpll);
1736         }
1737
1738         /* We do this three times for luck */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748 }
1749
1750 /**
1751  * i9xx_disable_pll - disable a PLL
1752  * @dev_priv: i915 private structure
1753  * @pipe: pipe PLL to disable
1754  *
1755  * Disable the PLL for @pipe, making sure the pipe is off first.
1756  *
1757  * Note!  This is for pre-ILK only.
1758  */
1759 static void i9xx_disable_pll(struct intel_crtc *crtc)
1760 {
1761         struct drm_device *dev = crtc->base.dev;
1762         struct drm_i915_private *dev_priv = dev->dev_private;
1763         enum pipe pipe = crtc->pipe;
1764
1765         /* Disable DVO 2x clock on both PLLs if necessary */
1766         if (IS_I830(dev) &&
1767             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1768             !intel_num_dvo_pipes(dev)) {
1769                 I915_WRITE(DPLL(PIPE_B),
1770                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1771                 I915_WRITE(DPLL(PIPE_A),
1772                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1773         }
1774
1775         /* Don't disable pipe or pipe PLLs if needed */
1776         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1777             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1778                 return;
1779
1780         /* Make sure the pipe isn't still relying on us */
1781         assert_pipe_disabled(dev_priv, pipe);
1782
1783         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1784         POSTING_READ(DPLL(pipe));
1785 }
1786
1787 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1788 {
1789         u32 val;
1790
1791         /* Make sure the pipe isn't still relying on us */
1792         assert_pipe_disabled(dev_priv, pipe);
1793
1794         /*
1795          * Leave integrated clock source and reference clock enabled for pipe B.
1796          * The latter is needed for VGA hotplug / manual detection.
1797          */
1798         val = DPLL_VGA_MODE_DIS;
1799         if (pipe == PIPE_B)
1800                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1801         I915_WRITE(DPLL(pipe), val);
1802         POSTING_READ(DPLL(pipe));
1803
1804 }
1805
1806 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1807 {
1808         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1809         u32 val;
1810
1811         /* Make sure the pipe isn't still relying on us */
1812         assert_pipe_disabled(dev_priv, pipe);
1813
1814         /* Set PLL en = 0 */
1815         val = DPLL_SSC_REF_CLK_CHV |
1816                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1817         if (pipe != PIPE_A)
1818                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1819         I915_WRITE(DPLL(pipe), val);
1820         POSTING_READ(DPLL(pipe));
1821
1822         mutex_lock(&dev_priv->sb_lock);
1823
1824         /* Disable 10bit clock to display controller */
1825         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1826         val &= ~DPIO_DCLKP_EN;
1827         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1828
1829         mutex_unlock(&dev_priv->sb_lock);
1830 }
1831
1832 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1833                          struct intel_digital_port *dport,
1834                          unsigned int expected_mask)
1835 {
1836         u32 port_mask;
1837         i915_reg_t dpll_reg;
1838
1839         switch (dport->port) {
1840         case PORT_B:
1841                 port_mask = DPLL_PORTB_READY_MASK;
1842                 dpll_reg = DPLL(0);
1843                 break;
1844         case PORT_C:
1845                 port_mask = DPLL_PORTC_READY_MASK;
1846                 dpll_reg = DPLL(0);
1847                 expected_mask <<= 4;
1848                 break;
1849         case PORT_D:
1850                 port_mask = DPLL_PORTD_READY_MASK;
1851                 dpll_reg = DPIO_PHY_STATUS;
1852                 break;
1853         default:
1854                 BUG();
1855         }
1856
1857         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1858                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1859                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1860 }
1861
1862 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1863 {
1864         struct drm_device *dev = crtc->base.dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1867
1868         if (WARN_ON(pll == NULL))
1869                 return;
1870
1871         WARN_ON(!pll->config.crtc_mask);
1872         if (pll->active == 0) {
1873                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1874                 WARN_ON(pll->on);
1875                 assert_shared_dpll_disabled(dev_priv, pll);
1876
1877                 pll->mode_set(dev_priv, pll);
1878         }
1879 }
1880
1881 /**
1882  * intel_enable_shared_dpll - enable PCH PLL
1883  * @dev_priv: i915 private structure
1884  * @pipe: pipe PLL to enable
1885  *
1886  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1887  * drives the transcoder clock.
1888  */
1889 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1890 {
1891         struct drm_device *dev = crtc->base.dev;
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1894
1895         if (WARN_ON(pll == NULL))
1896                 return;
1897
1898         if (WARN_ON(pll->config.crtc_mask == 0))
1899                 return;
1900
1901         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1902                       pll->name, pll->active, pll->on,
1903                       crtc->base.base.id);
1904
1905         if (pll->active++) {
1906                 WARN_ON(!pll->on);
1907                 assert_shared_dpll_enabled(dev_priv, pll);
1908                 return;
1909         }
1910         WARN_ON(pll->on);
1911
1912         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1913
1914         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1915         pll->enable(dev_priv, pll);
1916         pll->on = true;
1917 }
1918
1919 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1920 {
1921         struct drm_device *dev = crtc->base.dev;
1922         struct drm_i915_private *dev_priv = dev->dev_private;
1923         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1924
1925         /* PCH only available on ILK+ */
1926         if (INTEL_INFO(dev)->gen < 5)
1927                 return;
1928
1929         if (pll == NULL)
1930                 return;
1931
1932         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1933                 return;
1934
1935         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1936                       pll->name, pll->active, pll->on,
1937                       crtc->base.base.id);
1938
1939         if (WARN_ON(pll->active == 0)) {
1940                 assert_shared_dpll_disabled(dev_priv, pll);
1941                 return;
1942         }
1943
1944         assert_shared_dpll_enabled(dev_priv, pll);
1945         WARN_ON(!pll->on);
1946         if (--pll->active)
1947                 return;
1948
1949         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1950         pll->disable(dev_priv, pll);
1951         pll->on = false;
1952
1953         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1954 }
1955
1956 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1957                                            enum pipe pipe)
1958 {
1959         struct drm_device *dev = dev_priv->dev;
1960         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1962         i915_reg_t reg;
1963         uint32_t val, pipeconf_val;
1964
1965         /* PCH only available on ILK+ */
1966         BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968         /* Make sure PCH DPLL is enabled */
1969         assert_shared_dpll_enabled(dev_priv,
1970                                    intel_crtc_to_shared_dpll(intel_crtc));
1971
1972         /* FDI must be feeding us bits for PCH ports */
1973         assert_fdi_tx_enabled(dev_priv, pipe);
1974         assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976         if (HAS_PCH_CPT(dev)) {
1977                 /* Workaround: Set the timing override bit before enabling the
1978                  * pch transcoder. */
1979                 reg = TRANS_CHICKEN2(pipe);
1980                 val = I915_READ(reg);
1981                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982                 I915_WRITE(reg, val);
1983         }
1984
1985         reg = PCH_TRANSCONF(pipe);
1986         val = I915_READ(reg);
1987         pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989         if (HAS_PCH_IBX(dev_priv->dev)) {
1990                 /*
1991                  * Make the BPC in transcoder be consistent with
1992                  * that in pipeconf reg. For HDMI we must use 8bpc
1993                  * here for both 8bpc and 12bpc.
1994                  */
1995                 val &= ~PIPECONF_BPC_MASK;
1996                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997                         val |= PIPECONF_8BPC;
1998                 else
1999                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2000         }
2001
2002         val &= ~TRANS_INTERLACE_MASK;
2003         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004                 if (HAS_PCH_IBX(dev_priv->dev) &&
2005                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006                         val |= TRANS_LEGACY_INTERLACED_ILK;
2007                 else
2008                         val |= TRANS_INTERLACED;
2009         else
2010                 val |= TRANS_PROGRESSIVE;
2011
2012         I915_WRITE(reg, val | TRANS_ENABLE);
2013         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018                                       enum transcoder cpu_transcoder)
2019 {
2020         u32 val, pipeconf_val;
2021
2022         /* PCH only available on ILK+ */
2023         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025         /* FDI must be feeding us bits for PCH ports */
2026         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029         /* Workaround: set timing override bit. */
2030         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2031         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2033
2034         val = TRANS_ENABLE;
2035         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038             PIPECONF_INTERLACED_ILK)
2039                 val |= TRANS_INTERLACED;
2040         else
2041                 val |= TRANS_PROGRESSIVE;
2042
2043         I915_WRITE(LPT_TRANSCONF, val);
2044         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045                 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049                                             enum pipe pipe)
2050 {
2051         struct drm_device *dev = dev_priv->dev;
2052         i915_reg_t reg;
2053         uint32_t val;
2054
2055         /* FDI relies on the transcoder */
2056         assert_fdi_tx_disabled(dev_priv, pipe);
2057         assert_fdi_rx_disabled(dev_priv, pipe);
2058
2059         /* Ports must be off as well */
2060         assert_pch_ports_disabled(dev_priv, pipe);
2061
2062         reg = PCH_TRANSCONF(pipe);
2063         val = I915_READ(reg);
2064         val &= ~TRANS_ENABLE;
2065         I915_WRITE(reg, val);
2066         /* wait for PCH transcoder off, transcoder state */
2067         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2068                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2069
2070         if (HAS_PCH_CPT(dev)) {
2071                 /* Workaround: Clear the timing override chicken bit again. */
2072                 reg = TRANS_CHICKEN2(pipe);
2073                 val = I915_READ(reg);
2074                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2075                 I915_WRITE(reg, val);
2076         }
2077 }
2078
2079 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2080 {
2081         u32 val;
2082
2083         val = I915_READ(LPT_TRANSCONF);
2084         val &= ~TRANS_ENABLE;
2085         I915_WRITE(LPT_TRANSCONF, val);
2086         /* wait for PCH transcoder off, transcoder state */
2087         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2088                 DRM_ERROR("Failed to disable PCH transcoder\n");
2089
2090         /* Workaround: clear timing override bit. */
2091         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2092         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2093         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2094 }
2095
2096 /**
2097  * intel_enable_pipe - enable a pipe, asserting requirements
2098  * @crtc: crtc responsible for the pipe
2099  *
2100  * Enable @crtc's pipe, making sure that various hardware specific requirements
2101  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2102  */
2103 static void intel_enable_pipe(struct intel_crtc *crtc)
2104 {
2105         struct drm_device *dev = crtc->base.dev;
2106         struct drm_i915_private *dev_priv = dev->dev_private;
2107         enum pipe pipe = crtc->pipe;
2108         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2109         enum pipe pch_transcoder;
2110         i915_reg_t reg;
2111         u32 val;
2112
2113         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2114
2115         assert_planes_disabled(dev_priv, pipe);
2116         assert_cursor_disabled(dev_priv, pipe);
2117         assert_sprites_disabled(dev_priv, pipe);
2118
2119         if (HAS_PCH_LPT(dev_priv->dev))
2120                 pch_transcoder = TRANSCODER_A;
2121         else
2122                 pch_transcoder = pipe;
2123
2124         /*
2125          * A pipe without a PLL won't actually be able to drive bits from
2126          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2127          * need the check.
2128          */
2129         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2130                 if (crtc->config->has_dsi_encoder)
2131                         assert_dsi_pll_enabled(dev_priv);
2132                 else
2133                         assert_pll_enabled(dev_priv, pipe);
2134         else {
2135                 if (crtc->config->has_pch_encoder) {
2136                         /* if driving the PCH, we need FDI enabled */
2137                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2138                         assert_fdi_tx_pll_enabled(dev_priv,
2139                                                   (enum pipe) cpu_transcoder);
2140                 }
2141                 /* FIXME: assert CPU port conditions for SNB+ */
2142         }
2143
2144         reg = PIPECONF(cpu_transcoder);
2145         val = I915_READ(reg);
2146         if (val & PIPECONF_ENABLE) {
2147                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2148                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2149                 return;
2150         }
2151
2152         I915_WRITE(reg, val | PIPECONF_ENABLE);
2153         POSTING_READ(reg);
2154 }
2155
2156 /**
2157  * intel_disable_pipe - disable a pipe, asserting requirements
2158  * @crtc: crtc whose pipes is to be disabled
2159  *
2160  * Disable the pipe of @crtc, making sure that various hardware
2161  * specific requirements are met, if applicable, e.g. plane
2162  * disabled, panel fitter off, etc.
2163  *
2164  * Will wait until the pipe has shut down before returning.
2165  */
2166 static void intel_disable_pipe(struct intel_crtc *crtc)
2167 {
2168         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2169         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2170         enum pipe pipe = crtc->pipe;
2171         i915_reg_t reg;
2172         u32 val;
2173
2174         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2175
2176         /*
2177          * Make sure planes won't keep trying to pump pixels to us,
2178          * or we might hang the display.
2179          */
2180         assert_planes_disabled(dev_priv, pipe);
2181         assert_cursor_disabled(dev_priv, pipe);
2182         assert_sprites_disabled(dev_priv, pipe);
2183
2184         reg = PIPECONF(cpu_transcoder);
2185         val = I915_READ(reg);
2186         if ((val & PIPECONF_ENABLE) == 0)
2187                 return;
2188
2189         /*
2190          * Double wide has implications for planes
2191          * so best keep it disabled when not needed.
2192          */
2193         if (crtc->config->double_wide)
2194                 val &= ~PIPECONF_DOUBLE_WIDE;
2195
2196         /* Don't disable pipe or pipe PLLs if needed */
2197         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2198             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2199                 val &= ~PIPECONF_ENABLE;
2200
2201         I915_WRITE(reg, val);
2202         if ((val & PIPECONF_ENABLE) == 0)
2203                 intel_wait_for_pipe_off(crtc);
2204 }
2205
2206 static bool need_vtd_wa(struct drm_device *dev)
2207 {
2208 #ifdef CONFIG_INTEL_IOMMU
2209         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2210                 return true;
2211 #endif
2212         return false;
2213 }
2214
2215 unsigned int
2216 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2217                   uint64_t fb_format_modifier, unsigned int plane)
2218 {
2219         unsigned int tile_height;
2220         uint32_t pixel_bytes;
2221
2222         switch (fb_format_modifier) {
2223         case DRM_FORMAT_MOD_NONE:
2224                 tile_height = 1;
2225                 break;
2226         case I915_FORMAT_MOD_X_TILED:
2227                 tile_height = IS_GEN2(dev) ? 16 : 8;
2228                 break;
2229         case I915_FORMAT_MOD_Y_TILED:
2230                 tile_height = 32;
2231                 break;
2232         case I915_FORMAT_MOD_Yf_TILED:
2233                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2234                 switch (pixel_bytes) {
2235                 default:
2236                 case 1:
2237                         tile_height = 64;
2238                         break;
2239                 case 2:
2240                 case 4:
2241                         tile_height = 32;
2242                         break;
2243                 case 8:
2244                         tile_height = 16;
2245                         break;
2246                 case 16:
2247                         WARN_ONCE(1,
2248                                   "128-bit pixels are not supported for display!");
2249                         tile_height = 16;
2250                         break;
2251                 }
2252                 break;
2253         default:
2254                 MISSING_CASE(fb_format_modifier);
2255                 tile_height = 1;
2256                 break;
2257         }
2258
2259         return tile_height;
2260 }
2261
2262 unsigned int
2263 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2264                       uint32_t pixel_format, uint64_t fb_format_modifier)
2265 {
2266         return ALIGN(height, intel_tile_height(dev, pixel_format,
2267                                                fb_format_modifier, 0));
2268 }
2269
2270 static void
2271 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2272                         const struct drm_plane_state *plane_state)
2273 {
2274         struct intel_rotation_info *info = &view->params.rotation_info;
2275         unsigned int tile_height, tile_pitch;
2276
2277         *view = i915_ggtt_view_normal;
2278
2279         if (!plane_state)
2280                 return;
2281
2282         if (!intel_rotation_90_or_270(plane_state->rotation))
2283                 return;
2284
2285         *view = i915_ggtt_view_rotated;
2286
2287         info->height = fb->height;
2288         info->pixel_format = fb->pixel_format;
2289         info->pitch = fb->pitches[0];
2290         info->uv_offset = fb->offsets[1];
2291         info->fb_modifier = fb->modifier[0];
2292
2293         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2294                                         fb->modifier[0], 0);
2295         tile_pitch = PAGE_SIZE / tile_height;
2296         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2297         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2298         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2299
2300         if (info->pixel_format == DRM_FORMAT_NV12) {
2301                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2302                                                 fb->modifier[0], 1);
2303                 tile_pitch = PAGE_SIZE / tile_height;
2304                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2305                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2306                                                      tile_height);
2307                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2308                                 PAGE_SIZE;
2309         }
2310 }
2311
2312 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2313 {
2314         if (INTEL_INFO(dev_priv)->gen >= 9)
2315                 return 256 * 1024;
2316         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2317                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2318                 return 128 * 1024;
2319         else if (INTEL_INFO(dev_priv)->gen >= 4)
2320                 return 4 * 1024;
2321         else
2322                 return 0;
2323 }
2324
2325 int
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327                            struct drm_framebuffer *fb,
2328                            const struct drm_plane_state *plane_state)
2329 {
2330         struct drm_device *dev = fb->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333         struct i915_ggtt_view view;
2334         u32 alignment;
2335         int ret;
2336
2337         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
2339         switch (fb->modifier[0]) {
2340         case DRM_FORMAT_MOD_NONE:
2341                 alignment = intel_linear_alignment(dev_priv);
2342                 break;
2343         case I915_FORMAT_MOD_X_TILED:
2344                 if (INTEL_INFO(dev)->gen >= 9)
2345                         alignment = 256 * 1024;
2346                 else {
2347                         /* pin() will align the object as required by fence */
2348                         alignment = 0;
2349                 }
2350                 break;
2351         case I915_FORMAT_MOD_Y_TILED:
2352         case I915_FORMAT_MOD_Yf_TILED:
2353                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2354                           "Y tiling bo slipped through, driver bug!\n"))
2355                         return -EINVAL;
2356                 alignment = 1 * 1024 * 1024;
2357                 break;
2358         default:
2359                 MISSING_CASE(fb->modifier[0]);
2360                 return -EINVAL;
2361         }
2362
2363         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2364
2365         /* Note that the w/a also requires 64 PTE of padding following the
2366          * bo. We currently fill all unused PTE with the shadow page and so
2367          * we should always have valid PTE following the scanout preventing
2368          * the VT-d warning.
2369          */
2370         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2371                 alignment = 256 * 1024;
2372
2373         /*
2374          * Global gtt pte registers are special registers which actually forward
2375          * writes to a chunk of system memory. Which means that there is no risk
2376          * that the register values disappear as soon as we call
2377          * intel_runtime_pm_put(), so it is correct to wrap only the
2378          * pin/unpin/fence and not more.
2379          */
2380         intel_runtime_pm_get(dev_priv);
2381
2382         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2383                                                    &view);
2384         if (ret)
2385                 goto err_pm;
2386
2387         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2388          * fence, whereas 965+ only requires a fence if using
2389          * framebuffer compression.  For simplicity, we always install
2390          * a fence as the cost is not that onerous.
2391          */
2392         if (view.type == I915_GGTT_VIEW_NORMAL) {
2393                 ret = i915_gem_object_get_fence(obj);
2394                 if (ret == -EDEADLK) {
2395                         /*
2396                          * -EDEADLK means there are no free fences
2397                          * no pending flips.
2398                          *
2399                          * This is propagated to atomic, but it uses
2400                          * -EDEADLK to force a locking recovery, so
2401                          * change the returned error to -EBUSY.
2402                          */
2403                         ret = -EBUSY;
2404                         goto err_unpin;
2405                 } else if (ret)
2406                         goto err_unpin;
2407
2408                 i915_gem_object_pin_fence(obj);
2409         }
2410
2411         intel_runtime_pm_put(dev_priv);
2412         return 0;
2413
2414 err_unpin:
2415         i915_gem_object_unpin_from_display_plane(obj, &view);
2416 err_pm:
2417         intel_runtime_pm_put(dev_priv);
2418         return ret;
2419 }
2420
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422                                const struct drm_plane_state *plane_state)
2423 {
2424         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425         struct i915_ggtt_view view;
2426
2427         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
2429         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430
2431         if (view.type == I915_GGTT_VIEW_NORMAL)
2432                 i915_gem_object_unpin_fence(obj);
2433
2434         i915_gem_object_unpin_from_display_plane(obj, &view);
2435 }
2436
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438  * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2440                                              int *x, int *y,
2441                                              unsigned int tiling_mode,
2442                                              unsigned int cpp,
2443                                              unsigned int pitch)
2444 {
2445         if (tiling_mode != I915_TILING_NONE) {
2446                 unsigned int tile_rows, tiles;
2447
2448                 tile_rows = *y / 8;
2449                 *y %= 8;
2450
2451                 tiles = *x / (512/cpp);
2452                 *x %= 512/cpp;
2453
2454                 return tile_rows * pitch * 8 + tiles * 4096;
2455         } else {
2456                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2457                 unsigned int offset;
2458
2459                 offset = *y * pitch + *x * cpp;
2460                 *y = (offset & alignment) / pitch;
2461                 *x = ((offset & alignment) - *y * pitch) / cpp;
2462                 return offset & ~alignment;
2463         }
2464 }
2465
2466 static int i9xx_format_to_fourcc(int format)
2467 {
2468         switch (format) {
2469         case DISPPLANE_8BPP:
2470                 return DRM_FORMAT_C8;
2471         case DISPPLANE_BGRX555:
2472                 return DRM_FORMAT_XRGB1555;
2473         case DISPPLANE_BGRX565:
2474                 return DRM_FORMAT_RGB565;
2475         default:
2476         case DISPPLANE_BGRX888:
2477                 return DRM_FORMAT_XRGB8888;
2478         case DISPPLANE_RGBX888:
2479                 return DRM_FORMAT_XBGR8888;
2480         case DISPPLANE_BGRX101010:
2481                 return DRM_FORMAT_XRGB2101010;
2482         case DISPPLANE_RGBX101010:
2483                 return DRM_FORMAT_XBGR2101010;
2484         }
2485 }
2486
2487 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2488 {
2489         switch (format) {
2490         case PLANE_CTL_FORMAT_RGB_565:
2491                 return DRM_FORMAT_RGB565;
2492         default:
2493         case PLANE_CTL_FORMAT_XRGB_8888:
2494                 if (rgb_order) {
2495                         if (alpha)
2496                                 return DRM_FORMAT_ABGR8888;
2497                         else
2498                                 return DRM_FORMAT_XBGR8888;
2499                 } else {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ARGB8888;
2502                         else
2503                                 return DRM_FORMAT_XRGB8888;
2504                 }
2505         case PLANE_CTL_FORMAT_XRGB_2101010:
2506                 if (rgb_order)
2507                         return DRM_FORMAT_XBGR2101010;
2508                 else
2509                         return DRM_FORMAT_XRGB2101010;
2510         }
2511 }
2512
2513 static bool
2514 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515                               struct intel_initial_plane_config *plane_config)
2516 {
2517         struct drm_device *dev = crtc->base.dev;
2518         struct drm_i915_private *dev_priv = to_i915(dev);
2519         struct drm_i915_gem_object *obj = NULL;
2520         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521         struct drm_framebuffer *fb = &plane_config->fb->base;
2522         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2524                                     PAGE_SIZE);
2525
2526         size_aligned -= base_aligned;
2527
2528         if (plane_config->size == 0)
2529                 return false;
2530
2531         /* If the FB is too big, just don't use it since fbdev is not very
2532          * important and we should probably use that space with FBC or other
2533          * features. */
2534         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2535                 return false;
2536
2537         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538                                                              base_aligned,
2539                                                              base_aligned,
2540                                                              size_aligned);
2541         if (!obj)
2542                 return false;
2543
2544         obj->tiling_mode = plane_config->tiling;
2545         if (obj->tiling_mode == I915_TILING_X)
2546                 obj->stride = fb->pitches[0];
2547
2548         mode_cmd.pixel_format = fb->pixel_format;
2549         mode_cmd.width = fb->width;
2550         mode_cmd.height = fb->height;
2551         mode_cmd.pitches[0] = fb->pitches[0];
2552         mode_cmd.modifier[0] = fb->modifier[0];
2553         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2554
2555         mutex_lock(&dev->struct_mutex);
2556         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2557                                    &mode_cmd, obj)) {
2558                 DRM_DEBUG_KMS("intel fb init failed\n");
2559                 goto out_unref_obj;
2560         }
2561         mutex_unlock(&dev->struct_mutex);
2562
2563         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2564         return true;
2565
2566 out_unref_obj:
2567         drm_gem_object_unreference(&obj->base);
2568         mutex_unlock(&dev->struct_mutex);
2569         return false;
2570 }
2571
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 static void
2574 update_state_fb(struct drm_plane *plane)
2575 {
2576         if (plane->fb == plane->state->fb)
2577                 return;
2578
2579         if (plane->state->fb)
2580                 drm_framebuffer_unreference(plane->state->fb);
2581         plane->state->fb = plane->fb;
2582         if (plane->state->fb)
2583                 drm_framebuffer_reference(plane->state->fb);
2584 }
2585
2586 static void
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588                              struct intel_initial_plane_config *plane_config)
2589 {
2590         struct drm_device *dev = intel_crtc->base.dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         struct drm_crtc *c;
2593         struct intel_crtc *i;
2594         struct drm_i915_gem_object *obj;
2595         struct drm_plane *primary = intel_crtc->base.primary;
2596         struct drm_plane_state *plane_state = primary->state;
2597         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2598         struct intel_plane *intel_plane = to_intel_plane(primary);
2599         struct intel_plane_state *intel_state =
2600                 to_intel_plane_state(plane_state);
2601         struct drm_framebuffer *fb;
2602
2603         if (!plane_config->fb)
2604                 return;
2605
2606         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2607                 fb = &plane_config->fb->base;
2608                 goto valid_fb;
2609         }
2610
2611         kfree(plane_config->fb);
2612
2613         /*
2614          * Failed to alloc the obj, check to see if we should share
2615          * an fb with another CRTC instead
2616          */
2617         for_each_crtc(dev, c) {
2618                 i = to_intel_crtc(c);
2619
2620                 if (c == &intel_crtc->base)
2621                         continue;
2622
2623                 if (!i->active)
2624                         continue;
2625
2626                 fb = c->primary->fb;
2627                 if (!fb)
2628                         continue;
2629
2630                 obj = intel_fb_obj(fb);
2631                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2632                         drm_framebuffer_reference(fb);
2633                         goto valid_fb;
2634                 }
2635         }
2636
2637         /*
2638          * We've failed to reconstruct the BIOS FB.  Current display state
2639          * indicates that the primary plane is visible, but has a NULL FB,
2640          * which will lead to problems later if we don't fix it up.  The
2641          * simplest solution is to just disable the primary plane now and
2642          * pretend the BIOS never had it enabled.
2643          */
2644         to_intel_plane_state(plane_state)->visible = false;
2645         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2646         intel_pre_disable_primary(&intel_crtc->base);
2647         intel_plane->disable_plane(primary, &intel_crtc->base);
2648
2649         return;
2650
2651 valid_fb:
2652         plane_state->src_x = 0;
2653         plane_state->src_y = 0;
2654         plane_state->src_w = fb->width << 16;
2655         plane_state->src_h = fb->height << 16;
2656
2657         plane_state->crtc_x = 0;
2658         plane_state->crtc_y = 0;
2659         plane_state->crtc_w = fb->width;
2660         plane_state->crtc_h = fb->height;
2661
2662         intel_state->src.x1 = plane_state->src_x;
2663         intel_state->src.y1 = plane_state->src_y;
2664         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2665         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2666         intel_state->dst.x1 = plane_state->crtc_x;
2667         intel_state->dst.y1 = plane_state->crtc_y;
2668         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2669         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2670
2671         obj = intel_fb_obj(fb);
2672         if (obj->tiling_mode != I915_TILING_NONE)
2673                 dev_priv->preserve_bios_swizzle = true;
2674
2675         drm_framebuffer_reference(fb);
2676         primary->fb = primary->state->fb = fb;
2677         primary->crtc = primary->state->crtc = &intel_crtc->base;
2678         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2679         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2680 }
2681
2682 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2683                                       struct drm_framebuffer *fb,
2684                                       int x, int y)
2685 {
2686         struct drm_device *dev = crtc->dev;
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2689         struct drm_plane *primary = crtc->primary;
2690         bool visible = to_intel_plane_state(primary->state)->visible;
2691         struct drm_i915_gem_object *obj;
2692         int plane = intel_crtc->plane;
2693         unsigned long linear_offset;
2694         u32 dspcntr;
2695         i915_reg_t reg = DSPCNTR(plane);
2696         int pixel_size;
2697
2698         if (!visible || !fb) {
2699                 I915_WRITE(reg, 0);
2700                 if (INTEL_INFO(dev)->gen >= 4)
2701                         I915_WRITE(DSPSURF(plane), 0);
2702                 else
2703                         I915_WRITE(DSPADDR(plane), 0);
2704                 POSTING_READ(reg);
2705                 return;
2706         }
2707
2708         obj = intel_fb_obj(fb);
2709         if (WARN_ON(obj == NULL))
2710                 return;
2711
2712         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2713
2714         dspcntr = DISPPLANE_GAMMA_ENABLE;
2715
2716         dspcntr |= DISPLAY_PLANE_ENABLE;
2717
2718         if (INTEL_INFO(dev)->gen < 4) {
2719                 if (intel_crtc->pipe == PIPE_B)
2720                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2721
2722                 /* pipesrc and dspsize control the size that is scaled from,
2723                  * which should always be the user's requested size.
2724                  */
2725                 I915_WRITE(DSPSIZE(plane),
2726                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2727                            (intel_crtc->config->pipe_src_w - 1));
2728                 I915_WRITE(DSPPOS(plane), 0);
2729         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2730                 I915_WRITE(PRIMSIZE(plane),
2731                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2732                            (intel_crtc->config->pipe_src_w - 1));
2733                 I915_WRITE(PRIMPOS(plane), 0);
2734                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2735         }
2736
2737         switch (fb->pixel_format) {
2738         case DRM_FORMAT_C8:
2739                 dspcntr |= DISPPLANE_8BPP;
2740                 break;
2741         case DRM_FORMAT_XRGB1555:
2742                 dspcntr |= DISPPLANE_BGRX555;
2743                 break;
2744         case DRM_FORMAT_RGB565:
2745                 dspcntr |= DISPPLANE_BGRX565;
2746                 break;
2747         case DRM_FORMAT_XRGB8888:
2748                 dspcntr |= DISPPLANE_BGRX888;
2749                 break;
2750         case DRM_FORMAT_XBGR8888:
2751                 dspcntr |= DISPPLANE_RGBX888;
2752                 break;
2753         case DRM_FORMAT_XRGB2101010:
2754                 dspcntr |= DISPPLANE_BGRX101010;
2755                 break;
2756         case DRM_FORMAT_XBGR2101010:
2757                 dspcntr |= DISPPLANE_RGBX101010;
2758                 break;
2759         default:
2760                 BUG();
2761         }
2762
2763         if (INTEL_INFO(dev)->gen >= 4 &&
2764             obj->tiling_mode != I915_TILING_NONE)
2765                 dspcntr |= DISPPLANE_TILED;
2766
2767         if (IS_G4X(dev))
2768                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2769
2770         linear_offset = y * fb->pitches[0] + x * pixel_size;
2771
2772         if (INTEL_INFO(dev)->gen >= 4) {
2773                 intel_crtc->dspaddr_offset =
2774                         intel_gen4_compute_page_offset(dev_priv,
2775                                                        &x, &y, obj->tiling_mode,
2776                                                        pixel_size,
2777                                                        fb->pitches[0]);
2778                 linear_offset -= intel_crtc->dspaddr_offset;
2779         } else {
2780                 intel_crtc->dspaddr_offset = linear_offset;
2781         }
2782
2783         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2784                 dspcntr |= DISPPLANE_ROTATE_180;
2785
2786                 x += (intel_crtc->config->pipe_src_w - 1);
2787                 y += (intel_crtc->config->pipe_src_h - 1);
2788
2789                 /* Finding the last pixel of the last line of the display
2790                 data and adding to linear_offset*/
2791                 linear_offset +=
2792                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2793                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2794         }
2795
2796         intel_crtc->adjusted_x = x;
2797         intel_crtc->adjusted_y = y;
2798
2799         I915_WRITE(reg, dspcntr);
2800
2801         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2802         if (INTEL_INFO(dev)->gen >= 4) {
2803                 I915_WRITE(DSPSURF(plane),
2804                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2805                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2806                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2807         } else
2808                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2809         POSTING_READ(reg);
2810 }
2811
2812 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2813                                           struct drm_framebuffer *fb,
2814                                           int x, int y)
2815 {
2816         struct drm_device *dev = crtc->dev;
2817         struct drm_i915_private *dev_priv = dev->dev_private;
2818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819         struct drm_plane *primary = crtc->primary;
2820         bool visible = to_intel_plane_state(primary->state)->visible;
2821         struct drm_i915_gem_object *obj;
2822         int plane = intel_crtc->plane;
2823         unsigned long linear_offset;
2824         u32 dspcntr;
2825         i915_reg_t reg = DSPCNTR(plane);
2826         int pixel_size;
2827
2828         if (!visible || !fb) {
2829                 I915_WRITE(reg, 0);
2830                 I915_WRITE(DSPSURF(plane), 0);
2831                 POSTING_READ(reg);
2832                 return;
2833         }
2834
2835         obj = intel_fb_obj(fb);
2836         if (WARN_ON(obj == NULL))
2837                 return;
2838
2839         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2840
2841         dspcntr = DISPPLANE_GAMMA_ENABLE;
2842
2843         dspcntr |= DISPLAY_PLANE_ENABLE;
2844
2845         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2846                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2847
2848         switch (fb->pixel_format) {
2849         case DRM_FORMAT_C8:
2850                 dspcntr |= DISPPLANE_8BPP;
2851                 break;
2852         case DRM_FORMAT_RGB565:
2853                 dspcntr |= DISPPLANE_BGRX565;
2854                 break;
2855         case DRM_FORMAT_XRGB8888:
2856                 dspcntr |= DISPPLANE_BGRX888;
2857                 break;
2858         case DRM_FORMAT_XBGR8888:
2859                 dspcntr |= DISPPLANE_RGBX888;
2860                 break;
2861         case DRM_FORMAT_XRGB2101010:
2862                 dspcntr |= DISPPLANE_BGRX101010;
2863                 break;
2864         case DRM_FORMAT_XBGR2101010:
2865                 dspcntr |= DISPPLANE_RGBX101010;
2866                 break;
2867         default:
2868                 BUG();
2869         }
2870
2871         if (obj->tiling_mode != I915_TILING_NONE)
2872                 dspcntr |= DISPPLANE_TILED;
2873
2874         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2875                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2876
2877         linear_offset = y * fb->pitches[0] + x * pixel_size;
2878         intel_crtc->dspaddr_offset =
2879                 intel_gen4_compute_page_offset(dev_priv,
2880                                                &x, &y, obj->tiling_mode,
2881                                                pixel_size,
2882                                                fb->pitches[0]);
2883         linear_offset -= intel_crtc->dspaddr_offset;
2884         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2885                 dspcntr |= DISPPLANE_ROTATE_180;
2886
2887                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2888                         x += (intel_crtc->config->pipe_src_w - 1);
2889                         y += (intel_crtc->config->pipe_src_h - 1);
2890
2891                         /* Finding the last pixel of the last line of the display
2892                         data and adding to linear_offset*/
2893                         linear_offset +=
2894                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2895                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2896                 }
2897         }
2898
2899         intel_crtc->adjusted_x = x;
2900         intel_crtc->adjusted_y = y;
2901
2902         I915_WRITE(reg, dspcntr);
2903
2904         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2905         I915_WRITE(DSPSURF(plane),
2906                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2907         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2908                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2909         } else {
2910                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2911                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2912         }
2913         POSTING_READ(reg);
2914 }
2915
2916 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2917                               uint32_t pixel_format)
2918 {
2919         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2920
2921         /*
2922          * The stride is either expressed as a multiple of 64 bytes
2923          * chunks for linear buffers or in number of tiles for tiled
2924          * buffers.
2925          */
2926         switch (fb_modifier) {
2927         case DRM_FORMAT_MOD_NONE:
2928                 return 64;
2929         case I915_FORMAT_MOD_X_TILED:
2930                 if (INTEL_INFO(dev)->gen == 2)
2931                         return 128;
2932                 return 512;
2933         case I915_FORMAT_MOD_Y_TILED:
2934                 /* No need to check for old gens and Y tiling since this is
2935                  * about the display engine and those will be blocked before
2936                  * we get here.
2937                  */
2938                 return 128;
2939         case I915_FORMAT_MOD_Yf_TILED:
2940                 if (bits_per_pixel == 8)
2941                         return 64;
2942                 else
2943                         return 128;
2944         default:
2945                 MISSING_CASE(fb_modifier);
2946                 return 64;
2947         }
2948 }
2949
2950 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2951                            struct drm_i915_gem_object *obj,
2952                            unsigned int plane)
2953 {
2954         struct i915_ggtt_view view;
2955         struct i915_vma *vma;
2956         u64 offset;
2957
2958         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2959                                 intel_plane->base.state);
2960
2961         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2962         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2963                 view.type))
2964                 return -1;
2965
2966         offset = vma->node.start;
2967
2968         if (plane == 1) {
2969                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2970                           PAGE_SIZE;
2971         }
2972
2973         WARN_ON(upper_32_bits(offset));
2974
2975         return lower_32_bits(offset);
2976 }
2977
2978 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2979 {
2980         struct drm_device *dev = intel_crtc->base.dev;
2981         struct drm_i915_private *dev_priv = dev->dev_private;
2982
2983         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2984         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2985         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2986 }
2987
2988 /*
2989  * This function detaches (aka. unbinds) unused scalers in hardware
2990  */
2991 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2992 {
2993         struct intel_crtc_scaler_state *scaler_state;
2994         int i;
2995
2996         scaler_state = &intel_crtc->config->scaler_state;
2997
2998         /* loop through and disable scalers that aren't in use */
2999         for (i = 0; i < intel_crtc->num_scalers; i++) {
3000                 if (!scaler_state->scalers[i].in_use)
3001                         skl_detach_scaler(intel_crtc, i);
3002         }
3003 }
3004
3005 u32 skl_plane_ctl_format(uint32_t pixel_format)
3006 {
3007         switch (pixel_format) {
3008         case DRM_FORMAT_C8:
3009                 return PLANE_CTL_FORMAT_INDEXED;
3010         case DRM_FORMAT_RGB565:
3011                 return PLANE_CTL_FORMAT_RGB_565;
3012         case DRM_FORMAT_XBGR8888:
3013                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3014         case DRM_FORMAT_XRGB8888:
3015                 return PLANE_CTL_FORMAT_XRGB_8888;
3016         /*
3017          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3018          * to be already pre-multiplied. We need to add a knob (or a different
3019          * DRM_FORMAT) for user-space to configure that.
3020          */
3021         case DRM_FORMAT_ABGR8888:
3022                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3023                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3024         case DRM_FORMAT_ARGB8888:
3025                 return PLANE_CTL_FORMAT_XRGB_8888 |
3026                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3027         case DRM_FORMAT_XRGB2101010:
3028                 return PLANE_CTL_FORMAT_XRGB_2101010;
3029         case DRM_FORMAT_XBGR2101010:
3030                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3031         case DRM_FORMAT_YUYV:
3032                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3033         case DRM_FORMAT_YVYU:
3034                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3035         case DRM_FORMAT_UYVY:
3036                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3037         case DRM_FORMAT_VYUY:
3038                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3039         default:
3040                 MISSING_CASE(pixel_format);
3041         }
3042
3043         return 0;
3044 }
3045
3046 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3047 {
3048         switch (fb_modifier) {
3049         case DRM_FORMAT_MOD_NONE:
3050                 break;
3051         case I915_FORMAT_MOD_X_TILED:
3052                 return PLANE_CTL_TILED_X;
3053         case I915_FORMAT_MOD_Y_TILED:
3054                 return PLANE_CTL_TILED_Y;
3055         case I915_FORMAT_MOD_Yf_TILED:
3056                 return PLANE_CTL_TILED_YF;
3057         default:
3058                 MISSING_CASE(fb_modifier);
3059         }
3060
3061         return 0;
3062 }
3063
3064 u32 skl_plane_ctl_rotation(unsigned int rotation)
3065 {
3066         switch (rotation) {
3067         case BIT(DRM_ROTATE_0):
3068                 break;
3069         /*
3070          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3071          * while i915 HW rotation is clockwise, thats why this swapping.
3072          */
3073         case BIT(DRM_ROTATE_90):
3074                 return PLANE_CTL_ROTATE_270;
3075         case BIT(DRM_ROTATE_180):
3076                 return PLANE_CTL_ROTATE_180;
3077         case BIT(DRM_ROTATE_270):
3078                 return PLANE_CTL_ROTATE_90;
3079         default:
3080                 MISSING_CASE(rotation);
3081         }
3082
3083         return 0;
3084 }
3085
3086 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3087                                          struct drm_framebuffer *fb,
3088                                          int x, int y)
3089 {
3090         struct drm_device *dev = crtc->dev;
3091         struct drm_i915_private *dev_priv = dev->dev_private;
3092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093         struct drm_plane *plane = crtc->primary;
3094         bool visible = to_intel_plane_state(plane->state)->visible;
3095         struct drm_i915_gem_object *obj;
3096         int pipe = intel_crtc->pipe;
3097         u32 plane_ctl, stride_div, stride;
3098         u32 tile_height, plane_offset, plane_size;
3099         unsigned int rotation;
3100         int x_offset, y_offset;
3101         u32 surf_addr;
3102         struct intel_crtc_state *crtc_state = intel_crtc->config;
3103         struct intel_plane_state *plane_state;
3104         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3105         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3106         int scaler_id = -1;
3107
3108         plane_state = to_intel_plane_state(plane->state);
3109
3110         if (!visible || !fb) {
3111                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3112                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3113                 POSTING_READ(PLANE_CTL(pipe, 0));
3114                 return;
3115         }
3116
3117         plane_ctl = PLANE_CTL_ENABLE |
3118                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3119                     PLANE_CTL_PIPE_CSC_ENABLE;
3120
3121         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3122         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3123         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3124
3125         rotation = plane->state->rotation;
3126         plane_ctl |= skl_plane_ctl_rotation(rotation);
3127
3128         obj = intel_fb_obj(fb);
3129         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3130                                                fb->pixel_format);
3131         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3132
3133         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3134
3135         scaler_id = plane_state->scaler_id;
3136         src_x = plane_state->src.x1 >> 16;
3137         src_y = plane_state->src.y1 >> 16;
3138         src_w = drm_rect_width(&plane_state->src) >> 16;
3139         src_h = drm_rect_height(&plane_state->src) >> 16;
3140         dst_x = plane_state->dst.x1;
3141         dst_y = plane_state->dst.y1;
3142         dst_w = drm_rect_width(&plane_state->dst);
3143         dst_h = drm_rect_height(&plane_state->dst);
3144
3145         WARN_ON(x != src_x || y != src_y);
3146
3147         if (intel_rotation_90_or_270(rotation)) {
3148                 /* stride = Surface height in tiles */
3149                 tile_height = intel_tile_height(dev, fb->pixel_format,
3150                                                 fb->modifier[0], 0);
3151                 stride = DIV_ROUND_UP(fb->height, tile_height);
3152                 x_offset = stride * tile_height - y - src_h;
3153                 y_offset = x;
3154                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3155         } else {
3156                 stride = fb->pitches[0] / stride_div;
3157                 x_offset = x;
3158                 y_offset = y;
3159                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3160         }
3161         plane_offset = y_offset << 16 | x_offset;
3162
3163         intel_crtc->adjusted_x = x_offset;
3164         intel_crtc->adjusted_y = y_offset;
3165
3166         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3167         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3168         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3169         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3170
3171         if (scaler_id >= 0) {
3172                 uint32_t ps_ctrl = 0;
3173
3174                 WARN_ON(!dst_w || !dst_h);
3175                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3176                         crtc_state->scaler_state.scalers[scaler_id].mode;
3177                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3178                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3179                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3180                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3181                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3182         } else {
3183                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3184         }
3185
3186         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3187
3188         POSTING_READ(PLANE_SURF(pipe, 0));
3189 }
3190
3191 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3192 static int
3193 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3194                            int x, int y, enum mode_set_atomic state)
3195 {
3196         struct drm_device *dev = crtc->dev;
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198
3199         if (dev_priv->fbc.deactivate)
3200                 dev_priv->fbc.deactivate(dev_priv);
3201
3202         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3203
3204         return 0;
3205 }
3206
3207 static void intel_complete_page_flips(struct drm_device *dev)
3208 {
3209         struct drm_crtc *crtc;
3210
3211         for_each_crtc(dev, crtc) {
3212                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213                 enum plane plane = intel_crtc->plane;
3214
3215                 intel_prepare_page_flip(dev, plane);
3216                 intel_finish_page_flip_plane(dev, plane);
3217         }
3218 }
3219
3220 static void intel_update_primary_planes(struct drm_device *dev)
3221 {
3222         struct drm_crtc *crtc;
3223
3224         for_each_crtc(dev, crtc) {
3225                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3226                 struct intel_plane_state *plane_state;
3227
3228                 drm_modeset_lock_crtc(crtc, &plane->base);
3229                 plane_state = to_intel_plane_state(plane->base.state);
3230
3231                 if (crtc->state->active && plane_state->base.fb)
3232                         plane->commit_plane(&plane->base, plane_state);
3233
3234                 drm_modeset_unlock_crtc(crtc);
3235         }
3236 }
3237
3238 void intel_prepare_reset(struct drm_device *dev)
3239 {
3240         /* no reset support for gen2 */
3241         if (IS_GEN2(dev))
3242                 return;
3243
3244         /* reset doesn't touch the display */
3245         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3246                 return;
3247
3248         drm_modeset_lock_all(dev);
3249         /*
3250          * Disabling the crtcs gracefully seems nicer. Also the
3251          * g33 docs say we should at least disable all the planes.
3252          */
3253         intel_display_suspend(dev);
3254 }
3255
3256 void intel_finish_reset(struct drm_device *dev)
3257 {
3258         struct drm_i915_private *dev_priv = to_i915(dev);
3259
3260         /*
3261          * Flips in the rings will be nuked by the reset,
3262          * so complete all pending flips so that user space
3263          * will get its events and not get stuck.
3264          */
3265         intel_complete_page_flips(dev);
3266
3267         /* no reset support for gen2 */
3268         if (IS_GEN2(dev))
3269                 return;
3270
3271         /* reset doesn't touch the display */
3272         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3273                 /*
3274                  * Flips in the rings have been nuked by the reset,
3275                  * so update the base address of all primary
3276                  * planes to the the last fb to make sure we're
3277                  * showing the correct fb after a reset.
3278                  *
3279                  * FIXME: Atomic will make this obsolete since we won't schedule
3280                  * CS-based flips (which might get lost in gpu resets) any more.
3281                  */
3282                 intel_update_primary_planes(dev);
3283                 return;
3284         }
3285
3286         /*
3287          * The display has been reset as well,
3288          * so need a full re-initialization.
3289          */
3290         intel_runtime_pm_disable_interrupts(dev_priv);
3291         intel_runtime_pm_enable_interrupts(dev_priv);
3292
3293         intel_modeset_init_hw(dev);
3294
3295         spin_lock_irq(&dev_priv->irq_lock);
3296         if (dev_priv->display.hpd_irq_setup)
3297                 dev_priv->display.hpd_irq_setup(dev);
3298         spin_unlock_irq(&dev_priv->irq_lock);
3299
3300         intel_display_resume(dev);
3301
3302         intel_hpd_init(dev_priv);
3303
3304         drm_modeset_unlock_all(dev);
3305 }
3306
3307 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308 {
3309         struct drm_device *dev = crtc->dev;
3310         struct drm_i915_private *dev_priv = dev->dev_private;
3311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312         bool pending;
3313
3314         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316                 return false;
3317
3318         spin_lock_irq(&dev->event_lock);
3319         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3320         spin_unlock_irq(&dev->event_lock);
3321
3322         return pending;
3323 }
3324
3325 static void intel_update_pipe_config(struct intel_crtc *crtc,
3326                                      struct intel_crtc_state *old_crtc_state)
3327 {
3328         struct drm_device *dev = crtc->base.dev;
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         struct intel_crtc_state *pipe_config =
3331                 to_intel_crtc_state(crtc->base.state);
3332
3333         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3334         crtc->base.mode = crtc->base.state->mode;
3335
3336         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3337                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3338                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3339
3340         if (HAS_DDI(dev))
3341                 intel_set_pipe_csc(&crtc->base);
3342
3343         /*
3344          * Update pipe size and adjust fitter if needed: the reason for this is
3345          * that in compute_mode_changes we check the native mode (not the pfit
3346          * mode) to see if we can flip rather than do a full mode set. In the
3347          * fastboot case, we'll flip, but if we don't update the pipesrc and
3348          * pfit state, we'll end up with a big fb scanned out into the wrong
3349          * sized surface.
3350          */
3351
3352         I915_WRITE(PIPESRC(crtc->pipe),
3353                    ((pipe_config->pipe_src_w - 1) << 16) |
3354                    (pipe_config->pipe_src_h - 1));
3355
3356         /* on skylake this is done by detaching scalers */
3357         if (INTEL_INFO(dev)->gen >= 9) {
3358                 skl_detach_scalers(crtc);
3359
3360                 if (pipe_config->pch_pfit.enabled)
3361                         skylake_pfit_enable(crtc);
3362         } else if (HAS_PCH_SPLIT(dev)) {
3363                 if (pipe_config->pch_pfit.enabled)
3364                         ironlake_pfit_enable(crtc);
3365                 else if (old_crtc_state->pch_pfit.enabled)
3366                         ironlake_pfit_disable(crtc, true);
3367         }
3368 }
3369
3370 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3371 {
3372         struct drm_device *dev = crtc->dev;
3373         struct drm_i915_private *dev_priv = dev->dev_private;
3374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375         int pipe = intel_crtc->pipe;
3376         i915_reg_t reg;
3377         u32 temp;
3378
3379         /* enable normal train */
3380         reg = FDI_TX_CTL(pipe);
3381         temp = I915_READ(reg);
3382         if (IS_IVYBRIDGE(dev)) {
3383                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3384                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3385         } else {
3386                 temp &= ~FDI_LINK_TRAIN_NONE;
3387                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3388         }
3389         I915_WRITE(reg, temp);
3390
3391         reg = FDI_RX_CTL(pipe);
3392         temp = I915_READ(reg);
3393         if (HAS_PCH_CPT(dev)) {
3394                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3395                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3396         } else {
3397                 temp &= ~FDI_LINK_TRAIN_NONE;
3398                 temp |= FDI_LINK_TRAIN_NONE;
3399         }
3400         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3401
3402         /* wait one idle pattern time */
3403         POSTING_READ(reg);
3404         udelay(1000);
3405
3406         /* IVB wants error correction enabled */
3407         if (IS_IVYBRIDGE(dev))
3408                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3409                            FDI_FE_ERRC_ENABLE);
3410 }
3411
3412 /* The FDI link training functions for ILK/Ibexpeak. */
3413 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3414 {
3415         struct drm_device *dev = crtc->dev;
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418         int pipe = intel_crtc->pipe;
3419         i915_reg_t reg;
3420         u32 temp, tries;
3421
3422         /* FDI needs bits from pipe first */
3423         assert_pipe_enabled(dev_priv, pipe);
3424
3425         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426            for train result */
3427         reg = FDI_RX_IMR(pipe);
3428         temp = I915_READ(reg);
3429         temp &= ~FDI_RX_SYMBOL_LOCK;
3430         temp &= ~FDI_RX_BIT_LOCK;
3431         I915_WRITE(reg, temp);
3432         I915_READ(reg);
3433         udelay(150);
3434
3435         /* enable CPU FDI TX and PCH FDI RX */
3436         reg = FDI_TX_CTL(pipe);
3437         temp = I915_READ(reg);
3438         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3439         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3440         temp &= ~FDI_LINK_TRAIN_NONE;
3441         temp |= FDI_LINK_TRAIN_PATTERN_1;
3442         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3443
3444         reg = FDI_RX_CTL(pipe);
3445         temp = I915_READ(reg);
3446         temp &= ~FDI_LINK_TRAIN_NONE;
3447         temp |= FDI_LINK_TRAIN_PATTERN_1;
3448         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3449
3450         POSTING_READ(reg);
3451         udelay(150);
3452
3453         /* Ironlake workaround, enable clock pointer after FDI enable*/
3454         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3455         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3456                    FDI_RX_PHASE_SYNC_POINTER_EN);
3457
3458         reg = FDI_RX_IIR(pipe);
3459         for (tries = 0; tries < 5; tries++) {
3460                 temp = I915_READ(reg);
3461                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3462
3463                 if ((temp & FDI_RX_BIT_LOCK)) {
3464                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3465                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3466                         break;
3467                 }
3468         }
3469         if (tries == 5)
3470                 DRM_ERROR("FDI train 1 fail!\n");
3471
3472         /* Train 2 */
3473         reg = FDI_TX_CTL(pipe);
3474         temp = I915_READ(reg);
3475         temp &= ~FDI_LINK_TRAIN_NONE;
3476         temp |= FDI_LINK_TRAIN_PATTERN_2;
3477         I915_WRITE(reg, temp);
3478
3479         reg = FDI_RX_CTL(pipe);
3480         temp = I915_READ(reg);
3481         temp &= ~FDI_LINK_TRAIN_NONE;
3482         temp |= FDI_LINK_TRAIN_PATTERN_2;
3483         I915_WRITE(reg, temp);
3484
3485         POSTING_READ(reg);
3486         udelay(150);
3487
3488         reg = FDI_RX_IIR(pipe);
3489         for (tries = 0; tries < 5; tries++) {
3490                 temp = I915_READ(reg);
3491                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3492
3493                 if (temp & FDI_RX_SYMBOL_LOCK) {
3494                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3495                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3496                         break;
3497                 }
3498         }
3499         if (tries == 5)
3500                 DRM_ERROR("FDI train 2 fail!\n");
3501
3502         DRM_DEBUG_KMS("FDI train done\n");
3503
3504 }
3505
3506 static const int snb_b_fdi_train_param[] = {
3507         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3508         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3509         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3510         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3511 };
3512
3513 /* The FDI link training functions for SNB/Cougarpoint. */
3514 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3519         int pipe = intel_crtc->pipe;
3520         i915_reg_t reg;
3521         u32 temp, i, retry;
3522
3523         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3524            for train result */
3525         reg = FDI_RX_IMR(pipe);
3526         temp = I915_READ(reg);
3527         temp &= ~FDI_RX_SYMBOL_LOCK;
3528         temp &= ~FDI_RX_BIT_LOCK;
3529         I915_WRITE(reg, temp);
3530
3531         POSTING_READ(reg);
3532         udelay(150);
3533
3534         /* enable CPU FDI TX and PCH FDI RX */
3535         reg = FDI_TX_CTL(pipe);
3536         temp = I915_READ(reg);
3537         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3538         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3539         temp &= ~FDI_LINK_TRAIN_NONE;
3540         temp |= FDI_LINK_TRAIN_PATTERN_1;
3541         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3542         /* SNB-B */
3543         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3544         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3545
3546         I915_WRITE(FDI_RX_MISC(pipe),
3547                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3548
3549         reg = FDI_RX_CTL(pipe);
3550         temp = I915_READ(reg);
3551         if (HAS_PCH_CPT(dev)) {
3552                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3553                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3554         } else {
3555                 temp &= ~FDI_LINK_TRAIN_NONE;
3556                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3557         }
3558         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3559
3560         POSTING_READ(reg);
3561         udelay(150);
3562
3563         for (i = 0; i < 4; i++) {
3564                 reg = FDI_TX_CTL(pipe);
3565                 temp = I915_READ(reg);
3566                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3567                 temp |= snb_b_fdi_train_param[i];
3568                 I915_WRITE(reg, temp);
3569
3570                 POSTING_READ(reg);
3571                 udelay(500);
3572
3573                 for (retry = 0; retry < 5; retry++) {
3574                         reg = FDI_RX_IIR(pipe);
3575                         temp = I915_READ(reg);
3576                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3577                         if (temp & FDI_RX_BIT_LOCK) {
3578                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3579                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3580                                 break;
3581                         }
3582                         udelay(50);
3583                 }
3584                 if (retry < 5)
3585                         break;
3586         }
3587         if (i == 4)
3588                 DRM_ERROR("FDI train 1 fail!\n");
3589
3590         /* Train 2 */
3591         reg = FDI_TX_CTL(pipe);
3592         temp = I915_READ(reg);
3593         temp &= ~FDI_LINK_TRAIN_NONE;
3594         temp |= FDI_LINK_TRAIN_PATTERN_2;
3595         if (IS_GEN6(dev)) {
3596                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597                 /* SNB-B */
3598                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3599         }
3600         I915_WRITE(reg, temp);
3601
3602         reg = FDI_RX_CTL(pipe);
3603         temp = I915_READ(reg);
3604         if (HAS_PCH_CPT(dev)) {
3605                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3606                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3607         } else {
3608                 temp &= ~FDI_LINK_TRAIN_NONE;
3609                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3610         }
3611         I915_WRITE(reg, temp);
3612
3613         POSTING_READ(reg);
3614         udelay(150);
3615
3616         for (i = 0; i < 4; i++) {
3617                 reg = FDI_TX_CTL(pipe);
3618                 temp = I915_READ(reg);
3619                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3620                 temp |= snb_b_fdi_train_param[i];
3621                 I915_WRITE(reg, temp);
3622
3623                 POSTING_READ(reg);
3624                 udelay(500);
3625
3626                 for (retry = 0; retry < 5; retry++) {
3627                         reg = FDI_RX_IIR(pipe);
3628                         temp = I915_READ(reg);
3629                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3630                         if (temp & FDI_RX_SYMBOL_LOCK) {
3631                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3632                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3633                                 break;
3634                         }
3635                         udelay(50);
3636                 }
3637                 if (retry < 5)
3638                         break;
3639         }
3640         if (i == 4)
3641                 DRM_ERROR("FDI train 2 fail!\n");
3642
3643         DRM_DEBUG_KMS("FDI train done.\n");
3644 }
3645
3646 /* Manual link training for Ivy Bridge A0 parts */
3647 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3648 {
3649         struct drm_device *dev = crtc->dev;
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652         int pipe = intel_crtc->pipe;
3653         i915_reg_t reg;
3654         u32 temp, i, j;
3655
3656         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3657            for train result */
3658         reg = FDI_RX_IMR(pipe);
3659         temp = I915_READ(reg);
3660         temp &= ~FDI_RX_SYMBOL_LOCK;
3661         temp &= ~FDI_RX_BIT_LOCK;
3662         I915_WRITE(reg, temp);
3663
3664         POSTING_READ(reg);
3665         udelay(150);
3666
3667         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3668                       I915_READ(FDI_RX_IIR(pipe)));
3669
3670         /* Try each vswing and preemphasis setting twice before moving on */
3671         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3672                 /* disable first in case we need to retry */
3673                 reg = FDI_TX_CTL(pipe);
3674                 temp = I915_READ(reg);
3675                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3676                 temp &= ~FDI_TX_ENABLE;
3677                 I915_WRITE(reg, temp);
3678
3679                 reg = FDI_RX_CTL(pipe);
3680                 temp = I915_READ(reg);
3681                 temp &= ~FDI_LINK_TRAIN_AUTO;
3682                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3683                 temp &= ~FDI_RX_ENABLE;
3684                 I915_WRITE(reg, temp);
3685
3686                 /* enable CPU FDI TX and PCH FDI RX */
3687                 reg = FDI_TX_CTL(pipe);
3688                 temp = I915_READ(reg);
3689                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3690                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3691                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3692                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3693                 temp |= snb_b_fdi_train_param[j/2];
3694                 temp |= FDI_COMPOSITE_SYNC;
3695                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3696
3697                 I915_WRITE(FDI_RX_MISC(pipe),
3698                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3699
3700                 reg = FDI_RX_CTL(pipe);
3701                 temp = I915_READ(reg);
3702                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3703                 temp |= FDI_COMPOSITE_SYNC;
3704                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3705
3706                 POSTING_READ(reg);
3707                 udelay(1); /* should be 0.5us */
3708
3709                 for (i = 0; i < 4; i++) {
3710                         reg = FDI_RX_IIR(pipe);
3711                         temp = I915_READ(reg);
3712                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3713
3714                         if (temp & FDI_RX_BIT_LOCK ||
3715                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3716                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3717                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3718                                               i);
3719                                 break;
3720                         }
3721                         udelay(1); /* should be 0.5us */
3722                 }
3723                 if (i == 4) {
3724                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3725                         continue;
3726                 }
3727
3728                 /* Train 2 */
3729                 reg = FDI_TX_CTL(pipe);
3730                 temp = I915_READ(reg);
3731                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3732                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3733                 I915_WRITE(reg, temp);
3734
3735                 reg = FDI_RX_CTL(pipe);
3736                 temp = I915_READ(reg);
3737                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3738                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3739                 I915_WRITE(reg, temp);
3740
3741                 POSTING_READ(reg);
3742                 udelay(2); /* should be 1.5us */
3743
3744                 for (i = 0; i < 4; i++) {
3745                         reg = FDI_RX_IIR(pipe);
3746                         temp = I915_READ(reg);
3747                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3748
3749                         if (temp & FDI_RX_SYMBOL_LOCK ||
3750                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3751                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3752                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3753                                               i);
3754                                 goto train_done;
3755                         }
3756                         udelay(2); /* should be 1.5us */
3757                 }
3758                 if (i == 4)
3759                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3760         }
3761
3762 train_done:
3763         DRM_DEBUG_KMS("FDI train done.\n");
3764 }
3765
3766 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3767 {
3768         struct drm_device *dev = intel_crtc->base.dev;
3769         struct drm_i915_private *dev_priv = dev->dev_private;
3770         int pipe = intel_crtc->pipe;
3771         i915_reg_t reg;
3772         u32 temp;
3773
3774         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3775         reg = FDI_RX_CTL(pipe);
3776         temp = I915_READ(reg);
3777         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3778         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3779         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3780         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3781
3782         POSTING_READ(reg);
3783         udelay(200);
3784
3785         /* Switch from Rawclk to PCDclk */
3786         temp = I915_READ(reg);
3787         I915_WRITE(reg, temp | FDI_PCDCLK);
3788
3789         POSTING_READ(reg);
3790         udelay(200);
3791
3792         /* Enable CPU FDI TX PLL, always on for Ironlake */
3793         reg = FDI_TX_CTL(pipe);
3794         temp = I915_READ(reg);
3795         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3796                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3797
3798                 POSTING_READ(reg);
3799                 udelay(100);
3800         }
3801 }
3802
3803 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3804 {
3805         struct drm_device *dev = intel_crtc->base.dev;
3806         struct drm_i915_private *dev_priv = dev->dev_private;
3807         int pipe = intel_crtc->pipe;
3808         i915_reg_t reg;
3809         u32 temp;
3810
3811         /* Switch from PCDclk to Rawclk */
3812         reg = FDI_RX_CTL(pipe);
3813         temp = I915_READ(reg);
3814         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3815
3816         /* Disable CPU FDI TX PLL */
3817         reg = FDI_TX_CTL(pipe);
3818         temp = I915_READ(reg);
3819         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3820
3821         POSTING_READ(reg);
3822         udelay(100);
3823
3824         reg = FDI_RX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3827
3828         /* Wait for the clocks to turn off. */
3829         POSTING_READ(reg);
3830         udelay(100);
3831 }
3832
3833 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3834 {
3835         struct drm_device *dev = crtc->dev;
3836         struct drm_i915_private *dev_priv = dev->dev_private;
3837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3838         int pipe = intel_crtc->pipe;
3839         i915_reg_t reg;
3840         u32 temp;
3841
3842         /* disable CPU FDI tx and PCH FDI rx */
3843         reg = FDI_TX_CTL(pipe);
3844         temp = I915_READ(reg);
3845         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3846         POSTING_READ(reg);
3847
3848         reg = FDI_RX_CTL(pipe);
3849         temp = I915_READ(reg);
3850         temp &= ~(0x7 << 16);
3851         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3852         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3853
3854         POSTING_READ(reg);
3855         udelay(100);
3856
3857         /* Ironlake workaround, disable clock pointer after downing FDI */
3858         if (HAS_PCH_IBX(dev))
3859                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3860
3861         /* still set train pattern 1 */
3862         reg = FDI_TX_CTL(pipe);
3863         temp = I915_READ(reg);
3864         temp &= ~FDI_LINK_TRAIN_NONE;
3865         temp |= FDI_LINK_TRAIN_PATTERN_1;
3866         I915_WRITE(reg, temp);
3867
3868         reg = FDI_RX_CTL(pipe);
3869         temp = I915_READ(reg);
3870         if (HAS_PCH_CPT(dev)) {
3871                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3872                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3873         } else {
3874                 temp &= ~FDI_LINK_TRAIN_NONE;
3875                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3876         }
3877         /* BPC in FDI rx is consistent with that in PIPECONF */
3878         temp &= ~(0x07 << 16);
3879         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3880         I915_WRITE(reg, temp);
3881
3882         POSTING_READ(reg);
3883         udelay(100);
3884 }
3885
3886 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3887 {
3888         struct intel_crtc *crtc;
3889
3890         /* Note that we don't need to be called with mode_config.lock here
3891          * as our list of CRTC objects is static for the lifetime of the
3892          * device and so cannot disappear as we iterate. Similarly, we can
3893          * happily treat the predicates as racy, atomic checks as userspace
3894          * cannot claim and pin a new fb without at least acquring the
3895          * struct_mutex and so serialising with us.
3896          */
3897         for_each_intel_crtc(dev, crtc) {
3898                 if (atomic_read(&crtc->unpin_work_count) == 0)
3899                         continue;
3900
3901                 if (crtc->unpin_work)
3902                         intel_wait_for_vblank(dev, crtc->pipe);
3903
3904                 return true;
3905         }
3906
3907         return false;
3908 }
3909
3910 static void page_flip_completed(struct intel_crtc *intel_crtc)
3911 {
3912         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3913         struct intel_unpin_work *work = intel_crtc->unpin_work;
3914
3915         /* ensure that the unpin work is consistent wrt ->pending. */
3916         smp_rmb();
3917         intel_crtc->unpin_work = NULL;
3918
3919         if (work->event)
3920                 drm_send_vblank_event(intel_crtc->base.dev,
3921                                       intel_crtc->pipe,
3922                                       work->event);
3923
3924         drm_crtc_vblank_put(&intel_crtc->base);
3925
3926         wake_up_all(&dev_priv->pending_flip_queue);
3927         queue_work(dev_priv->wq, &work->work);
3928
3929         trace_i915_flip_complete(intel_crtc->plane,
3930                                  work->pending_flip_obj);
3931 }
3932
3933 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3934 {
3935         struct drm_device *dev = crtc->dev;
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         long ret;
3938
3939         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3940
3941         ret = wait_event_interruptible_timeout(
3942                                         dev_priv->pending_flip_queue,
3943                                         !intel_crtc_has_pending_flip(crtc),
3944                                         60*HZ);
3945
3946         if (ret < 0)
3947                 return ret;
3948
3949         if (ret == 0) {
3950                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3951
3952                 spin_lock_irq(&dev->event_lock);
3953                 if (intel_crtc->unpin_work) {
3954                         WARN_ONCE(1, "Removing stuck page flip\n");
3955                         page_flip_completed(intel_crtc);
3956                 }
3957                 spin_unlock_irq(&dev->event_lock);
3958         }
3959
3960         return 0;
3961 }
3962
3963 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3964 {
3965         u32 temp;
3966
3967         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3968
3969         mutex_lock(&dev_priv->sb_lock);
3970
3971         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3972         temp |= SBI_SSCCTL_DISABLE;
3973         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3974
3975         mutex_unlock(&dev_priv->sb_lock);
3976 }
3977
3978 /* Program iCLKIP clock to the desired frequency */
3979 static void lpt_program_iclkip(struct drm_crtc *crtc)
3980 {
3981         struct drm_device *dev = crtc->dev;
3982         struct drm_i915_private *dev_priv = dev->dev_private;
3983         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3984         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3985         u32 temp;
3986
3987         lpt_disable_iclkip(dev_priv);
3988
3989         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3990         if (clock == 20000) {
3991                 auxdiv = 1;
3992                 divsel = 0x41;
3993                 phaseinc = 0x20;
3994         } else {
3995                 /* The iCLK virtual clock root frequency is in MHz,
3996                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3997                  * divisors, it is necessary to divide one by another, so we
3998                  * convert the virtual clock precision to KHz here for higher
3999                  * precision.
4000                  */
4001                 u32 iclk_virtual_root_freq = 172800 * 1000;
4002                 u32 iclk_pi_range = 64;
4003                 u32 desired_divisor, msb_divisor_value, pi_value;
4004
4005                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
4006                 msb_divisor_value = desired_divisor / iclk_pi_range;
4007                 pi_value = desired_divisor % iclk_pi_range;
4008
4009                 auxdiv = 0;
4010                 divsel = msb_divisor_value - 2;
4011                 phaseinc = pi_value;
4012         }
4013
4014         /* This should not happen with any sane values */
4015         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4016                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4017         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4018                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4019
4020         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4021                         clock,
4022                         auxdiv,
4023                         divsel,
4024                         phasedir,
4025                         phaseinc);
4026
4027         mutex_lock(&dev_priv->sb_lock);
4028
4029         /* Program SSCDIVINTPHASE6 */
4030         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4031         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4032         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4033         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4034         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4035         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4036         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4037         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4038
4039         /* Program SSCAUXDIV */
4040         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4041         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4042         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4043         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4044
4045         /* Enable modulator and associated divider */
4046         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4047         temp &= ~SBI_SSCCTL_DISABLE;
4048         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4049
4050         mutex_unlock(&dev_priv->sb_lock);
4051
4052         /* Wait for initialization time */
4053         udelay(24);
4054
4055         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4056 }
4057
4058 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4059                                                 enum pipe pch_transcoder)
4060 {
4061         struct drm_device *dev = crtc->base.dev;
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4064
4065         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4066                    I915_READ(HTOTAL(cpu_transcoder)));
4067         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4068                    I915_READ(HBLANK(cpu_transcoder)));
4069         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4070                    I915_READ(HSYNC(cpu_transcoder)));
4071
4072         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4073                    I915_READ(VTOTAL(cpu_transcoder)));
4074         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4075                    I915_READ(VBLANK(cpu_transcoder)));
4076         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4077                    I915_READ(VSYNC(cpu_transcoder)));
4078         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4079                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4080 }
4081
4082 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4083 {
4084         struct drm_i915_private *dev_priv = dev->dev_private;
4085         uint32_t temp;
4086
4087         temp = I915_READ(SOUTH_CHICKEN1);
4088         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4089                 return;
4090
4091         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4092         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4093
4094         temp &= ~FDI_BC_BIFURCATION_SELECT;
4095         if (enable)
4096                 temp |= FDI_BC_BIFURCATION_SELECT;
4097
4098         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4099         I915_WRITE(SOUTH_CHICKEN1, temp);
4100         POSTING_READ(SOUTH_CHICKEN1);
4101 }
4102
4103 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4104 {
4105         struct drm_device *dev = intel_crtc->base.dev;
4106
4107         switch (intel_crtc->pipe) {
4108         case PIPE_A:
4109                 break;
4110         case PIPE_B:
4111                 if (intel_crtc->config->fdi_lanes > 2)
4112                         cpt_set_fdi_bc_bifurcation(dev, false);
4113                 else
4114                         cpt_set_fdi_bc_bifurcation(dev, true);
4115
4116                 break;
4117         case PIPE_C:
4118                 cpt_set_fdi_bc_bifurcation(dev, true);
4119
4120                 break;
4121         default:
4122                 BUG();
4123         }
4124 }
4125
4126 /* Return which DP Port should be selected for Transcoder DP control */
4127 static enum port
4128 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4129 {
4130         struct drm_device *dev = crtc->dev;
4131         struct intel_encoder *encoder;
4132
4133         for_each_encoder_on_crtc(dev, crtc, encoder) {
4134                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4135                     encoder->type == INTEL_OUTPUT_EDP)
4136                         return enc_to_dig_port(&encoder->base)->port;
4137         }
4138
4139         return -1;
4140 }
4141
4142 /*
4143  * Enable PCH resources required for PCH ports:
4144  *   - PCH PLLs
4145  *   - FDI training & RX/TX
4146  *   - update transcoder timings
4147  *   - DP transcoding bits
4148  *   - transcoder
4149  */
4150 static void ironlake_pch_enable(struct drm_crtc *crtc)
4151 {
4152         struct drm_device *dev = crtc->dev;
4153         struct drm_i915_private *dev_priv = dev->dev_private;
4154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155         int pipe = intel_crtc->pipe;
4156         u32 temp;
4157
4158         assert_pch_transcoder_disabled(dev_priv, pipe);
4159
4160         if (IS_IVYBRIDGE(dev))
4161                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4162
4163         /* Write the TU size bits before fdi link training, so that error
4164          * detection works. */
4165         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4166                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4167
4168         /*
4169          * Sometimes spurious CPU pipe underruns happen during FDI
4170          * training, at least with VGA+HDMI cloning. Suppress them.
4171          */
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4173
4174         /* For PCH output, training FDI link */
4175         dev_priv->display.fdi_link_train(crtc);
4176
4177         /* We need to program the right clock selection before writing the pixel
4178          * mutliplier into the DPLL. */
4179         if (HAS_PCH_CPT(dev)) {
4180                 u32 sel;
4181
4182                 temp = I915_READ(PCH_DPLL_SEL);
4183                 temp |= TRANS_DPLL_ENABLE(pipe);
4184                 sel = TRANS_DPLLB_SEL(pipe);
4185                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4186                         temp |= sel;
4187                 else
4188                         temp &= ~sel;
4189                 I915_WRITE(PCH_DPLL_SEL, temp);
4190         }
4191
4192         /* XXX: pch pll's can be enabled any time before we enable the PCH
4193          * transcoder, and we actually should do this to not upset any PCH
4194          * transcoder that already use the clock when we share it.
4195          *
4196          * Note that enable_shared_dpll tries to do the right thing, but
4197          * get_shared_dpll unconditionally resets the pll - we need that to have
4198          * the right LVDS enable sequence. */
4199         intel_enable_shared_dpll(intel_crtc);
4200
4201         /* set transcoder timing, panel must allow it */
4202         assert_panel_unlocked(dev_priv, pipe);
4203         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4204
4205         intel_fdi_normal_train(crtc);
4206
4207         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4208
4209         /* For PCH DP, enable TRANS_DP_CTL */
4210         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4211                 const struct drm_display_mode *adjusted_mode =
4212                         &intel_crtc->config->base.adjusted_mode;
4213                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4214                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4215                 temp = I915_READ(reg);
4216                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4217                           TRANS_DP_SYNC_MASK |
4218                           TRANS_DP_BPC_MASK);
4219                 temp |= TRANS_DP_OUTPUT_ENABLE;
4220                 temp |= bpc << 9; /* same format but at 11:9 */
4221
4222                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4223                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4224                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4225                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4226
4227                 switch (intel_trans_dp_port_sel(crtc)) {
4228                 case PORT_B:
4229                         temp |= TRANS_DP_PORT_SEL_B;
4230                         break;
4231                 case PORT_C:
4232                         temp |= TRANS_DP_PORT_SEL_C;
4233                         break;
4234                 case PORT_D:
4235                         temp |= TRANS_DP_PORT_SEL_D;
4236                         break;
4237                 default:
4238                         BUG();
4239                 }
4240
4241                 I915_WRITE(reg, temp);
4242         }
4243
4244         ironlake_enable_pch_transcoder(dev_priv, pipe);
4245 }
4246
4247 static void lpt_pch_enable(struct drm_crtc *crtc)
4248 {
4249         struct drm_device *dev = crtc->dev;
4250         struct drm_i915_private *dev_priv = dev->dev_private;
4251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4253
4254         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4255
4256         lpt_program_iclkip(crtc);
4257
4258         /* Set transcoder timing. */
4259         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4260
4261         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4262 }
4263
4264 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4265                                                 struct intel_crtc_state *crtc_state)
4266 {
4267         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4268         struct intel_shared_dpll *pll;
4269         struct intel_shared_dpll_config *shared_dpll;
4270         enum intel_dpll_id i;
4271         int max = dev_priv->num_shared_dpll;
4272
4273         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4274
4275         if (HAS_PCH_IBX(dev_priv->dev)) {
4276                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4277                 i = (enum intel_dpll_id) crtc->pipe;
4278                 pll = &dev_priv->shared_dplls[i];
4279
4280                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4281                               crtc->base.base.id, pll->name);
4282
4283                 WARN_ON(shared_dpll[i].crtc_mask);
4284
4285                 goto found;
4286         }
4287
4288         if (IS_BROXTON(dev_priv->dev)) {
4289                 /* PLL is attached to port in bxt */
4290                 struct intel_encoder *encoder;
4291                 struct intel_digital_port *intel_dig_port;
4292
4293                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4294                 if (WARN_ON(!encoder))
4295                         return NULL;
4296
4297                 intel_dig_port = enc_to_dig_port(&encoder->base);
4298                 /* 1:1 mapping between ports and PLLs */
4299                 i = (enum intel_dpll_id)intel_dig_port->port;
4300                 pll = &dev_priv->shared_dplls[i];
4301                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4302                         crtc->base.base.id, pll->name);
4303                 WARN_ON(shared_dpll[i].crtc_mask);
4304
4305                 goto found;
4306         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4307                 /* Do not consider SPLL */
4308                 max = 2;
4309
4310         for (i = 0; i < max; i++) {
4311                 pll = &dev_priv->shared_dplls[i];
4312
4313                 /* Only want to check enabled timings first */
4314                 if (shared_dpll[i].crtc_mask == 0)
4315                         continue;
4316
4317                 if (memcmp(&crtc_state->dpll_hw_state,
4318                            &shared_dpll[i].hw_state,
4319                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4320                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4321                                       crtc->base.base.id, pll->name,
4322                                       shared_dpll[i].crtc_mask,
4323                                       pll->active);
4324                         goto found;
4325                 }
4326         }
4327
4328         /* Ok no matching timings, maybe there's a free one? */
4329         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4330                 pll = &dev_priv->shared_dplls[i];
4331                 if (shared_dpll[i].crtc_mask == 0) {
4332                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4333                                       crtc->base.base.id, pll->name);
4334                         goto found;
4335                 }
4336         }
4337
4338         return NULL;
4339
4340 found:
4341         if (shared_dpll[i].crtc_mask == 0)
4342                 shared_dpll[i].hw_state =
4343                         crtc_state->dpll_hw_state;
4344
4345         crtc_state->shared_dpll = i;
4346         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4347                          pipe_name(crtc->pipe));
4348
4349         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4350
4351         return pll;
4352 }
4353
4354 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4355 {
4356         struct drm_i915_private *dev_priv = to_i915(state->dev);
4357         struct intel_shared_dpll_config *shared_dpll;
4358         struct intel_shared_dpll *pll;
4359         enum intel_dpll_id i;
4360
4361         if (!to_intel_atomic_state(state)->dpll_set)
4362                 return;
4363
4364         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4365         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4366                 pll = &dev_priv->shared_dplls[i];
4367                 pll->config = shared_dpll[i];
4368         }
4369 }
4370
4371 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4372 {
4373         struct drm_i915_private *dev_priv = dev->dev_private;
4374         i915_reg_t dslreg = PIPEDSL(pipe);
4375         u32 temp;
4376
4377         temp = I915_READ(dslreg);
4378         udelay(500);
4379         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4380                 if (wait_for(I915_READ(dslreg) != temp, 5))
4381                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4382         }
4383 }
4384
4385 static int
4386 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4387                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4388                   int src_w, int src_h, int dst_w, int dst_h)
4389 {
4390         struct intel_crtc_scaler_state *scaler_state =
4391                 &crtc_state->scaler_state;
4392         struct intel_crtc *intel_crtc =
4393                 to_intel_crtc(crtc_state->base.crtc);
4394         int need_scaling;
4395
4396         need_scaling = intel_rotation_90_or_270(rotation) ?
4397                 (src_h != dst_w || src_w != dst_h):
4398                 (src_w != dst_w || src_h != dst_h);
4399
4400         /*
4401          * if plane is being disabled or scaler is no more required or force detach
4402          *  - free scaler binded to this plane/crtc
4403          *  - in order to do this, update crtc->scaler_usage
4404          *
4405          * Here scaler state in crtc_state is set free so that
4406          * scaler can be assigned to other user. Actual register
4407          * update to free the scaler is done in plane/panel-fit programming.
4408          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4409          */
4410         if (force_detach || !need_scaling) {
4411                 if (*scaler_id >= 0) {
4412                         scaler_state->scaler_users &= ~(1 << scaler_user);
4413                         scaler_state->scalers[*scaler_id].in_use = 0;
4414
4415                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4416                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4417                                 intel_crtc->pipe, scaler_user, *scaler_id,
4418                                 scaler_state->scaler_users);
4419                         *scaler_id = -1;
4420                 }
4421                 return 0;
4422         }
4423
4424         /* range checks */
4425         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4426                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4427
4428                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4429                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4430                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4431                         "size is out of scaler range\n",
4432                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4433                 return -EINVAL;
4434         }
4435
4436         /* mark this plane as a scaler user in crtc_state */
4437         scaler_state->scaler_users |= (1 << scaler_user);
4438         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4439                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4440                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4441                 scaler_state->scaler_users);
4442
4443         return 0;
4444 }
4445
4446 /**
4447  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4448  *
4449  * @state: crtc's scaler state
4450  *
4451  * Return
4452  *     0 - scaler_usage updated successfully
4453  *    error - requested scaling cannot be supported or other error condition
4454  */
4455 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4456 {
4457         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4458         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4459
4460         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4461                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4462
4463         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4464                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4465                 state->pipe_src_w, state->pipe_src_h,
4466                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4467 }
4468
4469 /**
4470  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4471  *
4472  * @state: crtc's scaler state
4473  * @plane_state: atomic plane state to update
4474  *
4475  * Return
4476  *     0 - scaler_usage updated successfully
4477  *    error - requested scaling cannot be supported or other error condition
4478  */
4479 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4480                                    struct intel_plane_state *plane_state)
4481 {
4482
4483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4484         struct intel_plane *intel_plane =
4485                 to_intel_plane(plane_state->base.plane);
4486         struct drm_framebuffer *fb = plane_state->base.fb;
4487         int ret;
4488
4489         bool force_detach = !fb || !plane_state->visible;
4490
4491         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4492                       intel_plane->base.base.id, intel_crtc->pipe,
4493                       drm_plane_index(&intel_plane->base));
4494
4495         ret = skl_update_scaler(crtc_state, force_detach,
4496                                 drm_plane_index(&intel_plane->base),
4497                                 &plane_state->scaler_id,
4498                                 plane_state->base.rotation,
4499                                 drm_rect_width(&plane_state->src) >> 16,
4500                                 drm_rect_height(&plane_state->src) >> 16,
4501                                 drm_rect_width(&plane_state->dst),
4502                                 drm_rect_height(&plane_state->dst));
4503
4504         if (ret || plane_state->scaler_id < 0)
4505                 return ret;
4506
4507         /* check colorkey */
4508         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4509                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4510                               intel_plane->base.base.id);
4511                 return -EINVAL;
4512         }
4513
4514         /* Check src format */
4515         switch (fb->pixel_format) {
4516         case DRM_FORMAT_RGB565:
4517         case DRM_FORMAT_XBGR8888:
4518         case DRM_FORMAT_XRGB8888:
4519         case DRM_FORMAT_ABGR8888:
4520         case DRM_FORMAT_ARGB8888:
4521         case DRM_FORMAT_XRGB2101010:
4522         case DRM_FORMAT_XBGR2101010:
4523         case DRM_FORMAT_YUYV:
4524         case DRM_FORMAT_YVYU:
4525         case DRM_FORMAT_UYVY:
4526         case DRM_FORMAT_VYUY:
4527                 break;
4528         default:
4529                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4530                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4531                 return -EINVAL;
4532         }
4533
4534         return 0;
4535 }
4536
4537 static void skylake_scaler_disable(struct intel_crtc *crtc)
4538 {
4539         int i;
4540
4541         for (i = 0; i < crtc->num_scalers; i++)
4542                 skl_detach_scaler(crtc, i);
4543 }
4544
4545 static void skylake_pfit_enable(struct intel_crtc *crtc)
4546 {
4547         struct drm_device *dev = crtc->base.dev;
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         int pipe = crtc->pipe;
4550         struct intel_crtc_scaler_state *scaler_state =
4551                 &crtc->config->scaler_state;
4552
4553         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4554
4555         if (crtc->config->pch_pfit.enabled) {
4556                 int id;
4557
4558                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4559                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4560                         return;
4561                 }
4562
4563                 id = scaler_state->scaler_id;
4564                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4565                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4566                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4567                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4568
4569                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4570         }
4571 }
4572
4573 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4574 {
4575         struct drm_device *dev = crtc->base.dev;
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         int pipe = crtc->pipe;
4578
4579         if (crtc->config->pch_pfit.enabled) {
4580                 /* Force use of hard-coded filter coefficients
4581                  * as some pre-programmed values are broken,
4582                  * e.g. x201.
4583                  */
4584                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4585                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4586                                                  PF_PIPE_SEL_IVB(pipe));
4587                 else
4588                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4589                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4590                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4591         }
4592 }
4593
4594 void hsw_enable_ips(struct intel_crtc *crtc)
4595 {
4596         struct drm_device *dev = crtc->base.dev;
4597         struct drm_i915_private *dev_priv = dev->dev_private;
4598
4599         if (!crtc->config->ips_enabled)
4600                 return;
4601
4602         /* We can only enable IPS after we enable a plane and wait for a vblank */
4603         intel_wait_for_vblank(dev, crtc->pipe);
4604
4605         assert_plane_enabled(dev_priv, crtc->plane);
4606         if (IS_BROADWELL(dev)) {
4607                 mutex_lock(&dev_priv->rps.hw_lock);
4608                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4609                 mutex_unlock(&dev_priv->rps.hw_lock);
4610                 /* Quoting Art Runyan: "its not safe to expect any particular
4611                  * value in IPS_CTL bit 31 after enabling IPS through the
4612                  * mailbox." Moreover, the mailbox may return a bogus state,
4613                  * so we need to just enable it and continue on.
4614                  */
4615         } else {
4616                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4617                 /* The bit only becomes 1 in the next vblank, so this wait here
4618                  * is essentially intel_wait_for_vblank. If we don't have this
4619                  * and don't wait for vblanks until the end of crtc_enable, then
4620                  * the HW state readout code will complain that the expected
4621                  * IPS_CTL value is not the one we read. */
4622                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4623                         DRM_ERROR("Timed out waiting for IPS enable\n");
4624         }
4625 }
4626
4627 void hsw_disable_ips(struct intel_crtc *crtc)
4628 {
4629         struct drm_device *dev = crtc->base.dev;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631
4632         if (!crtc->config->ips_enabled)
4633                 return;
4634
4635         assert_plane_enabled(dev_priv, crtc->plane);
4636         if (IS_BROADWELL(dev)) {
4637                 mutex_lock(&dev_priv->rps.hw_lock);
4638                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4639                 mutex_unlock(&dev_priv->rps.hw_lock);
4640                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4641                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4642                         DRM_ERROR("Timed out waiting for IPS disable\n");
4643         } else {
4644                 I915_WRITE(IPS_CTL, 0);
4645                 POSTING_READ(IPS_CTL);
4646         }
4647
4648         /* We need to wait for a vblank before we can disable the plane. */
4649         intel_wait_for_vblank(dev, crtc->pipe);
4650 }
4651
4652 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4653 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4654 {
4655         struct drm_device *dev = crtc->dev;
4656         struct drm_i915_private *dev_priv = dev->dev_private;
4657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4658         enum pipe pipe = intel_crtc->pipe;
4659         int i;
4660         bool reenable_ips = false;
4661
4662         /* The clocks have to be on to load the palette. */
4663         if (!crtc->state->active)
4664                 return;
4665
4666         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4667                 if (intel_crtc->config->has_dsi_encoder)
4668                         assert_dsi_pll_enabled(dev_priv);
4669                 else
4670                         assert_pll_enabled(dev_priv, pipe);
4671         }
4672
4673         /* Workaround : Do not read or write the pipe palette/gamma data while
4674          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4675          */
4676         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4677             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4678              GAMMA_MODE_MODE_SPLIT)) {
4679                 hsw_disable_ips(intel_crtc);
4680                 reenable_ips = true;
4681         }
4682
4683         for (i = 0; i < 256; i++) {
4684                 i915_reg_t palreg;
4685
4686                 if (HAS_GMCH_DISPLAY(dev))
4687                         palreg = PALETTE(pipe, i);
4688                 else
4689                         palreg = LGC_PALETTE(pipe, i);
4690
4691                 I915_WRITE(palreg,
4692                            (intel_crtc->lut_r[i] << 16) |
4693                            (intel_crtc->lut_g[i] << 8) |
4694                            intel_crtc->lut_b[i]);
4695         }
4696
4697         if (reenable_ips)
4698                 hsw_enable_ips(intel_crtc);
4699 }
4700
4701 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4702 {
4703         if (intel_crtc->overlay) {
4704                 struct drm_device *dev = intel_crtc->base.dev;
4705                 struct drm_i915_private *dev_priv = dev->dev_private;
4706
4707                 mutex_lock(&dev->struct_mutex);
4708                 dev_priv->mm.interruptible = false;
4709                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4710                 dev_priv->mm.interruptible = true;
4711                 mutex_unlock(&dev->struct_mutex);
4712         }
4713
4714         /* Let userspace switch the overlay on again. In most cases userspace
4715          * has to recompute where to put it anyway.
4716          */
4717 }
4718
4719 /**
4720  * intel_post_enable_primary - Perform operations after enabling primary plane
4721  * @crtc: the CRTC whose primary plane was just enabled
4722  *
4723  * Performs potentially sleeping operations that must be done after the primary
4724  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4725  * called due to an explicit primary plane update, or due to an implicit
4726  * re-enable that is caused when a sprite plane is updated to no longer
4727  * completely hide the primary plane.
4728  */
4729 static void
4730 intel_post_enable_primary(struct drm_crtc *crtc)
4731 {
4732         struct drm_device *dev = crtc->dev;
4733         struct drm_i915_private *dev_priv = dev->dev_private;
4734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4735         int pipe = intel_crtc->pipe;
4736
4737         /*
4738          * FIXME IPS should be fine as long as one plane is
4739          * enabled, but in practice it seems to have problems
4740          * when going from primary only to sprite only and vice
4741          * versa.
4742          */
4743         hsw_enable_ips(intel_crtc);
4744
4745         /*
4746          * Gen2 reports pipe underruns whenever all planes are disabled.
4747          * So don't enable underrun reporting before at least some planes
4748          * are enabled.
4749          * FIXME: Need to fix the logic to work when we turn off all planes
4750          * but leave the pipe running.
4751          */
4752         if (IS_GEN2(dev))
4753                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4754
4755         /* Underruns don't always raise interrupts, so check manually. */
4756         intel_check_cpu_fifo_underruns(dev_priv);
4757         intel_check_pch_fifo_underruns(dev_priv);
4758 }
4759
4760 /**
4761  * intel_pre_disable_primary - Perform operations before disabling primary plane
4762  * @crtc: the CRTC whose primary plane is to be disabled
4763  *
4764  * Performs potentially sleeping operations that must be done before the
4765  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4766  * be called due to an explicit primary plane update, or due to an implicit
4767  * disable that is caused when a sprite plane completely hides the primary
4768  * plane.
4769  */
4770 static void
4771 intel_pre_disable_primary(struct drm_crtc *crtc)
4772 {
4773         struct drm_device *dev = crtc->dev;
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4776         int pipe = intel_crtc->pipe;
4777
4778         /*
4779          * Gen2 reports pipe underruns whenever all planes are disabled.
4780          * So diasble underrun reporting before all the planes get disabled.
4781          * FIXME: Need to fix the logic to work when we turn off all planes
4782          * but leave the pipe running.
4783          */
4784         if (IS_GEN2(dev))
4785                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4786
4787         /*
4788          * Vblank time updates from the shadow to live plane control register
4789          * are blocked if the memory self-refresh mode is active at that
4790          * moment. So to make sure the plane gets truly disabled, disable
4791          * first the self-refresh mode. The self-refresh enable bit in turn
4792          * will be checked/applied by the HW only at the next frame start
4793          * event which is after the vblank start event, so we need to have a
4794          * wait-for-vblank between disabling the plane and the pipe.
4795          */
4796         if (HAS_GMCH_DISPLAY(dev)) {
4797                 intel_set_memory_cxsr(dev_priv, false);
4798                 dev_priv->wm.vlv.cxsr = false;
4799                 intel_wait_for_vblank(dev, pipe);
4800         }
4801
4802         /*
4803          * FIXME IPS should be fine as long as one plane is
4804          * enabled, but in practice it seems to have problems
4805          * when going from primary only to sprite only and vice
4806          * versa.
4807          */
4808         hsw_disable_ips(intel_crtc);
4809 }
4810
4811 static void intel_post_plane_update(struct intel_crtc *crtc)
4812 {
4813         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4814         struct intel_crtc_state *pipe_config =
4815                 to_intel_crtc_state(crtc->base.state);
4816         struct drm_device *dev = crtc->base.dev;
4817
4818         if (atomic->wait_vblank)
4819                 intel_wait_for_vblank(dev, crtc->pipe);
4820
4821         intel_frontbuffer_flip(dev, atomic->fb_bits);
4822
4823         crtc->wm.cxsr_allowed = true;
4824
4825         if (pipe_config->wm_changed && pipe_config->base.active)
4826                 intel_update_watermarks(&crtc->base);
4827
4828         if (atomic->update_fbc)
4829                 intel_fbc_update(crtc);
4830
4831         if (atomic->post_enable_primary)
4832                 intel_post_enable_primary(&crtc->base);
4833
4834         memset(atomic, 0, sizeof(*atomic));
4835 }
4836
4837 static void intel_pre_plane_update(struct intel_crtc *crtc)
4838 {
4839         struct drm_device *dev = crtc->base.dev;
4840         struct drm_i915_private *dev_priv = dev->dev_private;
4841         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4842         struct intel_crtc_state *pipe_config =
4843                 to_intel_crtc_state(crtc->base.state);
4844
4845         if (atomic->disable_fbc)
4846                 intel_fbc_deactivate(crtc);
4847
4848         if (crtc->atomic.disable_ips)
4849                 hsw_disable_ips(crtc);
4850
4851         if (atomic->pre_disable_primary)
4852                 intel_pre_disable_primary(&crtc->base);
4853
4854         if (pipe_config->disable_cxsr) {
4855                 crtc->wm.cxsr_allowed = false;
4856                 intel_set_memory_cxsr(dev_priv, false);
4857         }
4858
4859         /*
4860          * IVB workaround: must disable low power watermarks for at least
4861          * one frame before enabling scaling.  LP watermarks can be re-enabled
4862          * when scaling is disabled.
4863          *
4864          * WaCxSRDisabledForSpriteScaling:ivb
4865          */
4866         if (pipe_config->disable_lp_wm) {
4867                 ilk_disable_lp_wm(dev);
4868                 intel_wait_for_vblank(dev, crtc->pipe);
4869         }
4870
4871         /*
4872          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4873          * watermark programming here.
4874          */
4875         if (needs_modeset(&pipe_config->base))
4876                 return;
4877
4878         /*
4879          * For platforms that support atomic watermarks, program the
4880          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4881          * will be the intermediate values that are safe for both pre- and
4882          * post- vblank; when vblank happens, the 'active' values will be set
4883          * to the final 'target' values and we'll do this again to get the
4884          * optimal watermarks.  For gen9+ platforms, the values we program here
4885          * will be the final target values which will get automatically latched
4886          * at vblank time; no further programming will be necessary.
4887          *
4888          * If a platform hasn't been transitioned to atomic watermarks yet,
4889          * we'll continue to update watermarks the old way, if flags tell
4890          * us to.
4891          */
4892         if (dev_priv->display.initial_watermarks != NULL)
4893                 dev_priv->display.initial_watermarks(pipe_config);
4894         else if (pipe_config->wm_changed)
4895                 intel_update_watermarks(&crtc->base);
4896 }
4897
4898 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4899 {
4900         struct drm_device *dev = crtc->dev;
4901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4902         struct drm_plane *p;
4903         int pipe = intel_crtc->pipe;
4904
4905         intel_crtc_dpms_overlay_disable(intel_crtc);
4906
4907         drm_for_each_plane_mask(p, dev, plane_mask)
4908                 to_intel_plane(p)->disable_plane(p, crtc);
4909
4910         /*
4911          * FIXME: Once we grow proper nuclear flip support out of this we need
4912          * to compute the mask of flip planes precisely. For the time being
4913          * consider this a flip to a NULL plane.
4914          */
4915         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4916 }
4917
4918 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4919 {
4920         struct drm_device *dev = crtc->dev;
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923         struct intel_encoder *encoder;
4924         int pipe = intel_crtc->pipe;
4925
4926         if (WARN_ON(intel_crtc->active))
4927                 return;
4928
4929         if (intel_crtc->config->has_pch_encoder)
4930                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4931
4932         if (intel_crtc->config->has_pch_encoder)
4933                 intel_prepare_shared_dpll(intel_crtc);
4934
4935         if (intel_crtc->config->has_dp_encoder)
4936                 intel_dp_set_m_n(intel_crtc, M1_N1);
4937
4938         intel_set_pipe_timings(intel_crtc);
4939
4940         if (intel_crtc->config->has_pch_encoder) {
4941                 intel_cpu_transcoder_set_m_n(intel_crtc,
4942                                      &intel_crtc->config->fdi_m_n, NULL);
4943         }
4944
4945         ironlake_set_pipeconf(crtc);
4946
4947         intel_crtc->active = true;
4948
4949         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4950
4951         for_each_encoder_on_crtc(dev, crtc, encoder)
4952                 if (encoder->pre_enable)
4953                         encoder->pre_enable(encoder);
4954
4955         if (intel_crtc->config->has_pch_encoder) {
4956                 /* Note: FDI PLL enabling _must_ be done before we enable the
4957                  * cpu pipes, hence this is separate from all the other fdi/pch
4958                  * enabling. */
4959                 ironlake_fdi_pll_enable(intel_crtc);
4960         } else {
4961                 assert_fdi_tx_disabled(dev_priv, pipe);
4962                 assert_fdi_rx_disabled(dev_priv, pipe);
4963         }
4964
4965         ironlake_pfit_enable(intel_crtc);
4966
4967         /*
4968          * On ILK+ LUT must be loaded before the pipe is running but with
4969          * clocks enabled
4970          */
4971         intel_crtc_load_lut(crtc);
4972
4973         intel_update_watermarks(crtc);
4974         intel_enable_pipe(intel_crtc);
4975
4976         if (intel_crtc->config->has_pch_encoder)
4977                 ironlake_pch_enable(crtc);
4978
4979         assert_vblank_disabled(crtc);
4980         drm_crtc_vblank_on(crtc);
4981
4982         for_each_encoder_on_crtc(dev, crtc, encoder)
4983                 encoder->enable(encoder);
4984
4985         if (HAS_PCH_CPT(dev))
4986                 cpt_verify_modeset(dev, intel_crtc->pipe);
4987
4988         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4989         if (intel_crtc->config->has_pch_encoder)
4990                 intel_wait_for_vblank(dev, pipe);
4991         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4992
4993         intel_fbc_enable(intel_crtc);
4994 }
4995
4996 /* IPS only exists on ULT machines and is tied to pipe A. */
4997 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4998 {
4999         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5000 }
5001
5002 static void haswell_crtc_enable(struct drm_crtc *crtc)
5003 {
5004         struct drm_device *dev = crtc->dev;
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007         struct intel_encoder *encoder;
5008         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5009         struct intel_crtc_state *pipe_config =
5010                 to_intel_crtc_state(crtc->state);
5011
5012         if (WARN_ON(intel_crtc->active))
5013                 return;
5014
5015         if (intel_crtc->config->has_pch_encoder)
5016                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5017                                                       false);
5018
5019         if (intel_crtc_to_shared_dpll(intel_crtc))
5020                 intel_enable_shared_dpll(intel_crtc);
5021
5022         if (intel_crtc->config->has_dp_encoder)
5023                 intel_dp_set_m_n(intel_crtc, M1_N1);
5024
5025         intel_set_pipe_timings(intel_crtc);
5026
5027         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5028                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5029                            intel_crtc->config->pixel_multiplier - 1);
5030         }
5031
5032         if (intel_crtc->config->has_pch_encoder) {
5033                 intel_cpu_transcoder_set_m_n(intel_crtc,
5034                                      &intel_crtc->config->fdi_m_n, NULL);
5035         }
5036
5037         haswell_set_pipeconf(crtc);
5038
5039         intel_set_pipe_csc(crtc);
5040
5041         intel_crtc->active = true;
5042
5043         if (intel_crtc->config->has_pch_encoder)
5044                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5045         else
5046                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5047
5048         for_each_encoder_on_crtc(dev, crtc, encoder) {
5049                 if (encoder->pre_enable)
5050                         encoder->pre_enable(encoder);
5051         }
5052
5053         if (intel_crtc->config->has_pch_encoder)
5054                 dev_priv->display.fdi_link_train(crtc);
5055
5056         if (!intel_crtc->config->has_dsi_encoder)
5057                 intel_ddi_enable_pipe_clock(intel_crtc);
5058
5059         if (INTEL_INFO(dev)->gen >= 9)
5060                 skylake_pfit_enable(intel_crtc);
5061         else
5062                 ironlake_pfit_enable(intel_crtc);
5063
5064         /*
5065          * On ILK+ LUT must be loaded before the pipe is running but with
5066          * clocks enabled
5067          */
5068         intel_crtc_load_lut(crtc);
5069
5070         intel_ddi_set_pipe_settings(crtc);
5071         if (!intel_crtc->config->has_dsi_encoder)
5072                 intel_ddi_enable_transcoder_func(crtc);
5073
5074         intel_update_watermarks(crtc);
5075         intel_enable_pipe(intel_crtc);
5076
5077         if (intel_crtc->config->has_pch_encoder)
5078                 lpt_pch_enable(crtc);
5079
5080         if (intel_crtc->config->dp_encoder_is_mst)
5081                 intel_ddi_set_vc_payload_alloc(crtc, true);
5082
5083         assert_vblank_disabled(crtc);
5084         drm_crtc_vblank_on(crtc);
5085
5086         for_each_encoder_on_crtc(dev, crtc, encoder) {
5087                 encoder->enable(encoder);
5088                 intel_opregion_notify_encoder(encoder, true);
5089         }
5090
5091         if (intel_crtc->config->has_pch_encoder) {
5092                 intel_wait_for_vblank(dev, pipe);
5093                 intel_wait_for_vblank(dev, pipe);
5094                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5095                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5096                                                       true);
5097         }
5098
5099         /* If we change the relative order between pipe/planes enabling, we need
5100          * to change the workaround. */
5101         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5102         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5103                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5104                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5105         }
5106
5107         intel_fbc_enable(intel_crtc);
5108 }
5109
5110 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5111 {
5112         struct drm_device *dev = crtc->base.dev;
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114         int pipe = crtc->pipe;
5115
5116         /* To avoid upsetting the power well on haswell only disable the pfit if
5117          * it's in use. The hw state code will make sure we get this right. */
5118         if (force || crtc->config->pch_pfit.enabled) {
5119                 I915_WRITE(PF_CTL(pipe), 0);
5120                 I915_WRITE(PF_WIN_POS(pipe), 0);
5121                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5122         }
5123 }
5124
5125 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5126 {
5127         struct drm_device *dev = crtc->dev;
5128         struct drm_i915_private *dev_priv = dev->dev_private;
5129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5130         struct intel_encoder *encoder;
5131         int pipe = intel_crtc->pipe;
5132
5133         if (intel_crtc->config->has_pch_encoder)
5134                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5135
5136         for_each_encoder_on_crtc(dev, crtc, encoder)
5137                 encoder->disable(encoder);
5138
5139         drm_crtc_vblank_off(crtc);
5140         assert_vblank_disabled(crtc);
5141
5142         /*
5143          * Sometimes spurious CPU pipe underruns happen when the
5144          * pipe is already disabled, but FDI RX/TX is still enabled.
5145          * Happens at least with VGA+HDMI cloning. Suppress them.
5146          */
5147         if (intel_crtc->config->has_pch_encoder)
5148                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5149
5150         intel_disable_pipe(intel_crtc);
5151
5152         ironlake_pfit_disable(intel_crtc, false);
5153
5154         if (intel_crtc->config->has_pch_encoder) {
5155                 ironlake_fdi_disable(crtc);
5156                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5157         }
5158
5159         for_each_encoder_on_crtc(dev, crtc, encoder)
5160                 if (encoder->post_disable)
5161                         encoder->post_disable(encoder);
5162
5163         if (intel_crtc->config->has_pch_encoder) {
5164                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5165
5166                 if (HAS_PCH_CPT(dev)) {
5167                         i915_reg_t reg;
5168                         u32 temp;
5169
5170                         /* disable TRANS_DP_CTL */
5171                         reg = TRANS_DP_CTL(pipe);
5172                         temp = I915_READ(reg);
5173                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5174                                   TRANS_DP_PORT_SEL_MASK);
5175                         temp |= TRANS_DP_PORT_SEL_NONE;
5176                         I915_WRITE(reg, temp);
5177
5178                         /* disable DPLL_SEL */
5179                         temp = I915_READ(PCH_DPLL_SEL);
5180                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5181                         I915_WRITE(PCH_DPLL_SEL, temp);
5182                 }
5183
5184                 ironlake_fdi_pll_disable(intel_crtc);
5185         }
5186
5187         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5188
5189         intel_fbc_disable_crtc(intel_crtc);
5190 }
5191
5192 static void haswell_crtc_disable(struct drm_crtc *crtc)
5193 {
5194         struct drm_device *dev = crtc->dev;
5195         struct drm_i915_private *dev_priv = dev->dev_private;
5196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5197         struct intel_encoder *encoder;
5198         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5199
5200         if (intel_crtc->config->has_pch_encoder)
5201                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5202                                                       false);
5203
5204         for_each_encoder_on_crtc(dev, crtc, encoder) {
5205                 intel_opregion_notify_encoder(encoder, false);
5206                 encoder->disable(encoder);
5207         }
5208
5209         drm_crtc_vblank_off(crtc);
5210         assert_vblank_disabled(crtc);
5211
5212         intel_disable_pipe(intel_crtc);
5213
5214         if (intel_crtc->config->dp_encoder_is_mst)
5215                 intel_ddi_set_vc_payload_alloc(crtc, false);
5216
5217         if (!intel_crtc->config->has_dsi_encoder)
5218                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5219
5220         if (INTEL_INFO(dev)->gen >= 9)
5221                 skylake_scaler_disable(intel_crtc);
5222         else
5223                 ironlake_pfit_disable(intel_crtc, false);
5224
5225         if (!intel_crtc->config->has_dsi_encoder)
5226                 intel_ddi_disable_pipe_clock(intel_crtc);
5227
5228         for_each_encoder_on_crtc(dev, crtc, encoder)
5229                 if (encoder->post_disable)
5230                         encoder->post_disable(encoder);
5231
5232         if (intel_crtc->config->has_pch_encoder) {
5233                 lpt_disable_pch_transcoder(dev_priv);
5234                 lpt_disable_iclkip(dev_priv);
5235                 intel_ddi_fdi_disable(crtc);
5236
5237                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5238                                                       true);
5239         }
5240
5241         intel_fbc_disable_crtc(intel_crtc);
5242 }
5243
5244 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5245 {
5246         struct drm_device *dev = crtc->base.dev;
5247         struct drm_i915_private *dev_priv = dev->dev_private;
5248         struct intel_crtc_state *pipe_config = crtc->config;
5249
5250         if (!pipe_config->gmch_pfit.control)
5251                 return;
5252
5253         /*
5254          * The panel fitter should only be adjusted whilst the pipe is disabled,
5255          * according to register description and PRM.
5256          */
5257         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5258         assert_pipe_disabled(dev_priv, crtc->pipe);
5259
5260         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5261         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5262
5263         /* Border color in case we don't scale up to the full screen. Black by
5264          * default, change to something else for debugging. */
5265         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5266 }
5267
5268 static enum intel_display_power_domain port_to_power_domain(enum port port)
5269 {
5270         switch (port) {
5271         case PORT_A:
5272                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5273         case PORT_B:
5274                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5275         case PORT_C:
5276                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5277         case PORT_D:
5278                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5279         case PORT_E:
5280                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5281         default:
5282                 MISSING_CASE(port);
5283                 return POWER_DOMAIN_PORT_OTHER;
5284         }
5285 }
5286
5287 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5288 {
5289         switch (port) {
5290         case PORT_A:
5291                 return POWER_DOMAIN_AUX_A;
5292         case PORT_B:
5293                 return POWER_DOMAIN_AUX_B;
5294         case PORT_C:
5295                 return POWER_DOMAIN_AUX_C;
5296         case PORT_D:
5297                 return POWER_DOMAIN_AUX_D;
5298         case PORT_E:
5299                 /* FIXME: Check VBT for actual wiring of PORT E */
5300                 return POWER_DOMAIN_AUX_D;
5301         default:
5302                 MISSING_CASE(port);
5303                 return POWER_DOMAIN_AUX_A;
5304         }
5305 }
5306
5307 enum intel_display_power_domain
5308 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5309 {
5310         struct drm_device *dev = intel_encoder->base.dev;
5311         struct intel_digital_port *intel_dig_port;
5312
5313         switch (intel_encoder->type) {
5314         case INTEL_OUTPUT_UNKNOWN:
5315                 /* Only DDI platforms should ever use this output type */
5316                 WARN_ON_ONCE(!HAS_DDI(dev));
5317         case INTEL_OUTPUT_DISPLAYPORT:
5318         case INTEL_OUTPUT_HDMI:
5319         case INTEL_OUTPUT_EDP:
5320                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5321                 return port_to_power_domain(intel_dig_port->port);
5322         case INTEL_OUTPUT_DP_MST:
5323                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5324                 return port_to_power_domain(intel_dig_port->port);
5325         case INTEL_OUTPUT_ANALOG:
5326                 return POWER_DOMAIN_PORT_CRT;
5327         case INTEL_OUTPUT_DSI:
5328                 return POWER_DOMAIN_PORT_DSI;
5329         default:
5330                 return POWER_DOMAIN_PORT_OTHER;
5331         }
5332 }
5333
5334 enum intel_display_power_domain
5335 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5336 {
5337         struct drm_device *dev = intel_encoder->base.dev;
5338         struct intel_digital_port *intel_dig_port;
5339
5340         switch (intel_encoder->type) {
5341         case INTEL_OUTPUT_UNKNOWN:
5342         case INTEL_OUTPUT_HDMI:
5343                 /*
5344                  * Only DDI platforms should ever use these output types.
5345                  * We can get here after the HDMI detect code has already set
5346                  * the type of the shared encoder. Since we can't be sure
5347                  * what's the status of the given connectors, play safe and
5348                  * run the DP detection too.
5349                  */
5350                 WARN_ON_ONCE(!HAS_DDI(dev));
5351         case INTEL_OUTPUT_DISPLAYPORT:
5352         case INTEL_OUTPUT_EDP:
5353                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5354                 return port_to_aux_power_domain(intel_dig_port->port);
5355         case INTEL_OUTPUT_DP_MST:
5356                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5357                 return port_to_aux_power_domain(intel_dig_port->port);
5358         default:
5359                 MISSING_CASE(intel_encoder->type);
5360                 return POWER_DOMAIN_AUX_A;
5361         }
5362 }
5363
5364 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5365 {
5366         struct drm_device *dev = crtc->dev;
5367         struct intel_encoder *intel_encoder;
5368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5369         enum pipe pipe = intel_crtc->pipe;
5370         unsigned long mask;
5371         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5372
5373         if (!crtc->state->active)
5374                 return 0;
5375
5376         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5377         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5378         if (intel_crtc->config->pch_pfit.enabled ||
5379             intel_crtc->config->pch_pfit.force_thru)
5380                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5381
5382         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5383                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5384
5385         return mask;
5386 }
5387
5388 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5389 {
5390         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5392         enum intel_display_power_domain domain;
5393         unsigned long domains, new_domains, old_domains;
5394
5395         old_domains = intel_crtc->enabled_power_domains;
5396         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5397
5398         domains = new_domains & ~old_domains;
5399
5400         for_each_power_domain(domain, domains)
5401                 intel_display_power_get(dev_priv, domain);
5402
5403         return old_domains & ~new_domains;
5404 }
5405
5406 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5407                                       unsigned long domains)
5408 {
5409         enum intel_display_power_domain domain;
5410
5411         for_each_power_domain(domain, domains)
5412                 intel_display_power_put(dev_priv, domain);
5413 }
5414
5415 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5416 {
5417         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5418         struct drm_device *dev = state->dev;
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         unsigned long put_domains[I915_MAX_PIPES] = {};
5421         struct drm_crtc_state *crtc_state;
5422         struct drm_crtc *crtc;
5423         int i;
5424
5425         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5426                 if (needs_modeset(crtc->state))
5427                         put_domains[to_intel_crtc(crtc)->pipe] =
5428                                 modeset_get_crtc_power_domains(crtc);
5429         }
5430
5431         if (dev_priv->display.modeset_commit_cdclk &&
5432             intel_state->dev_cdclk != dev_priv->cdclk_freq)
5433                 dev_priv->display.modeset_commit_cdclk(state);
5434
5435         for (i = 0; i < I915_MAX_PIPES; i++)
5436                 if (put_domains[i])
5437                         modeset_put_power_domains(dev_priv, put_domains[i]);
5438 }
5439
5440 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5441 {
5442         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5443
5444         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5445             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5446                 return max_cdclk_freq;
5447         else if (IS_CHERRYVIEW(dev_priv))
5448                 return max_cdclk_freq*95/100;
5449         else if (INTEL_INFO(dev_priv)->gen < 4)
5450                 return 2*max_cdclk_freq*90/100;
5451         else
5452                 return max_cdclk_freq*90/100;
5453 }
5454
5455 static void intel_update_max_cdclk(struct drm_device *dev)
5456 {
5457         struct drm_i915_private *dev_priv = dev->dev_private;
5458
5459         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5460                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5461
5462                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5463                         dev_priv->max_cdclk_freq = 675000;
5464                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5465                         dev_priv->max_cdclk_freq = 540000;
5466                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5467                         dev_priv->max_cdclk_freq = 450000;
5468                 else
5469                         dev_priv->max_cdclk_freq = 337500;
5470         } else if (IS_BROADWELL(dev))  {
5471                 /*
5472                  * FIXME with extra cooling we can allow
5473                  * 540 MHz for ULX and 675 Mhz for ULT.
5474                  * How can we know if extra cooling is
5475                  * available? PCI ID, VTB, something else?
5476                  */
5477                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5478                         dev_priv->max_cdclk_freq = 450000;
5479                 else if (IS_BDW_ULX(dev))
5480                         dev_priv->max_cdclk_freq = 450000;
5481                 else if (IS_BDW_ULT(dev))
5482                         dev_priv->max_cdclk_freq = 540000;
5483                 else
5484                         dev_priv->max_cdclk_freq = 675000;
5485         } else if (IS_CHERRYVIEW(dev)) {
5486                 dev_priv->max_cdclk_freq = 320000;
5487         } else if (IS_VALLEYVIEW(dev)) {
5488                 dev_priv->max_cdclk_freq = 400000;
5489         } else {
5490                 /* otherwise assume cdclk is fixed */
5491                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5492         }
5493
5494         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5495
5496         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5497                          dev_priv->max_cdclk_freq);
5498
5499         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5500                          dev_priv->max_dotclk_freq);
5501 }
5502
5503 static void intel_update_cdclk(struct drm_device *dev)
5504 {
5505         struct drm_i915_private *dev_priv = dev->dev_private;
5506
5507         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5508         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5509                          dev_priv->cdclk_freq);
5510
5511         /*
5512          * Program the gmbus_freq based on the cdclk frequency.
5513          * BSpec erroneously claims we should aim for 4MHz, but
5514          * in fact 1MHz is the correct frequency.
5515          */
5516         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5517                 /*
5518                  * Program the gmbus_freq based on the cdclk frequency.
5519                  * BSpec erroneously claims we should aim for 4MHz, but
5520                  * in fact 1MHz is the correct frequency.
5521                  */
5522                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5523         }
5524
5525         if (dev_priv->max_cdclk_freq == 0)
5526                 intel_update_max_cdclk(dev);
5527 }
5528
5529 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5530 {
5531         struct drm_i915_private *dev_priv = dev->dev_private;
5532         uint32_t divider;
5533         uint32_t ratio;
5534         uint32_t current_freq;
5535         int ret;
5536
5537         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5538         switch (frequency) {
5539         case 144000:
5540                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5541                 ratio = BXT_DE_PLL_RATIO(60);
5542                 break;
5543         case 288000:
5544                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5545                 ratio = BXT_DE_PLL_RATIO(60);
5546                 break;
5547         case 384000:
5548                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5549                 ratio = BXT_DE_PLL_RATIO(60);
5550                 break;
5551         case 576000:
5552                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5553                 ratio = BXT_DE_PLL_RATIO(60);
5554                 break;
5555         case 624000:
5556                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5557                 ratio = BXT_DE_PLL_RATIO(65);
5558                 break;
5559         case 19200:
5560                 /*
5561                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5562                  * to suppress GCC warning.
5563                  */
5564                 ratio = 0;
5565                 divider = 0;
5566                 break;
5567         default:
5568                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5569
5570                 return;
5571         }
5572
5573         mutex_lock(&dev_priv->rps.hw_lock);
5574         /* Inform power controller of upcoming frequency change */
5575         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5576                                       0x80000000);
5577         mutex_unlock(&dev_priv->rps.hw_lock);
5578
5579         if (ret) {
5580                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5581                           ret, frequency);
5582                 return;
5583         }
5584
5585         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5586         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5587         current_freq = current_freq * 500 + 1000;
5588
5589         /*
5590          * DE PLL has to be disabled when
5591          * - setting to 19.2MHz (bypass, PLL isn't used)
5592          * - before setting to 624MHz (PLL needs toggling)
5593          * - before setting to any frequency from 624MHz (PLL needs toggling)
5594          */
5595         if (frequency == 19200 || frequency == 624000 ||
5596             current_freq == 624000) {
5597                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5598                 /* Timeout 200us */
5599                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5600                              1))
5601                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5602         }
5603
5604         if (frequency != 19200) {
5605                 uint32_t val;
5606
5607                 val = I915_READ(BXT_DE_PLL_CTL);
5608                 val &= ~BXT_DE_PLL_RATIO_MASK;
5609                 val |= ratio;
5610                 I915_WRITE(BXT_DE_PLL_CTL, val);
5611
5612                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5613                 /* Timeout 200us */
5614                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5615                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5616
5617                 val = I915_READ(CDCLK_CTL);
5618                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5619                 val |= divider;
5620                 /*
5621                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5622                  * enable otherwise.
5623                  */
5624                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5625                 if (frequency >= 500000)
5626                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5627
5628                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5629                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5630                 val |= (frequency - 1000) / 500;
5631                 I915_WRITE(CDCLK_CTL, val);
5632         }
5633
5634         mutex_lock(&dev_priv->rps.hw_lock);
5635         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5636                                       DIV_ROUND_UP(frequency, 25000));
5637         mutex_unlock(&dev_priv->rps.hw_lock);
5638
5639         if (ret) {
5640                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5641                           ret, frequency);
5642                 return;
5643         }
5644
5645         intel_update_cdclk(dev);
5646 }
5647
5648 void broxton_init_cdclk(struct drm_device *dev)
5649 {
5650         struct drm_i915_private *dev_priv = dev->dev_private;
5651         uint32_t val;
5652
5653         /*
5654          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5655          * or else the reset will hang because there is no PCH to respond.
5656          * Move the handshake programming to initialization sequence.
5657          * Previously was left up to BIOS.
5658          */
5659         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5660         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5661         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5662
5663         /* Enable PG1 for cdclk */
5664         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5665
5666         /* check if cd clock is enabled */
5667         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5668                 DRM_DEBUG_KMS("Display already initialized\n");
5669                 return;
5670         }
5671
5672         /*
5673          * FIXME:
5674          * - The initial CDCLK needs to be read from VBT.
5675          *   Need to make this change after VBT has changes for BXT.
5676          * - check if setting the max (or any) cdclk freq is really necessary
5677          *   here, it belongs to modeset time
5678          */
5679         broxton_set_cdclk(dev, 624000);
5680
5681         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5682         POSTING_READ(DBUF_CTL);
5683
5684         udelay(10);
5685
5686         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5687                 DRM_ERROR("DBuf power enable timeout!\n");
5688 }
5689
5690 void broxton_uninit_cdclk(struct drm_device *dev)
5691 {
5692         struct drm_i915_private *dev_priv = dev->dev_private;
5693
5694         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5695         POSTING_READ(DBUF_CTL);
5696
5697         udelay(10);
5698
5699         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5700                 DRM_ERROR("DBuf power disable timeout!\n");
5701
5702         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5703         broxton_set_cdclk(dev, 19200);
5704
5705         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5706 }
5707
5708 static const struct skl_cdclk_entry {
5709         unsigned int freq;
5710         unsigned int vco;
5711 } skl_cdclk_frequencies[] = {
5712         { .freq = 308570, .vco = 8640 },
5713         { .freq = 337500, .vco = 8100 },
5714         { .freq = 432000, .vco = 8640 },
5715         { .freq = 450000, .vco = 8100 },
5716         { .freq = 540000, .vco = 8100 },
5717         { .freq = 617140, .vco = 8640 },
5718         { .freq = 675000, .vco = 8100 },
5719 };
5720
5721 static unsigned int skl_cdclk_decimal(unsigned int freq)
5722 {
5723         return (freq - 1000) / 500;
5724 }
5725
5726 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5727 {
5728         unsigned int i;
5729
5730         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5731                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5732
5733                 if (e->freq == freq)
5734                         return e->vco;
5735         }
5736
5737         return 8100;
5738 }
5739
5740 static void
5741 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5742 {
5743         unsigned int min_freq;
5744         u32 val;
5745
5746         /* select the minimum CDCLK before enabling DPLL 0 */
5747         val = I915_READ(CDCLK_CTL);
5748         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5749         val |= CDCLK_FREQ_337_308;
5750
5751         if (required_vco == 8640)
5752                 min_freq = 308570;
5753         else
5754                 min_freq = 337500;
5755
5756         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5757
5758         I915_WRITE(CDCLK_CTL, val);
5759         POSTING_READ(CDCLK_CTL);
5760
5761         /*
5762          * We always enable DPLL0 with the lowest link rate possible, but still
5763          * taking into account the VCO required to operate the eDP panel at the
5764          * desired frequency. The usual DP link rates operate with a VCO of
5765          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5766          * The modeset code is responsible for the selection of the exact link
5767          * rate later on, with the constraint of choosing a frequency that
5768          * works with required_vco.
5769          */
5770         val = I915_READ(DPLL_CTRL1);
5771
5772         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5773                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5774         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5775         if (required_vco == 8640)
5776                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5777                                             SKL_DPLL0);
5778         else
5779                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5780                                             SKL_DPLL0);
5781
5782         I915_WRITE(DPLL_CTRL1, val);
5783         POSTING_READ(DPLL_CTRL1);
5784
5785         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5786
5787         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5788                 DRM_ERROR("DPLL0 not locked\n");
5789 }
5790
5791 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5792 {
5793         int ret;
5794         u32 val;
5795
5796         /* inform PCU we want to change CDCLK */
5797         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5798         mutex_lock(&dev_priv->rps.hw_lock);
5799         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5800         mutex_unlock(&dev_priv->rps.hw_lock);
5801
5802         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5803 }
5804
5805 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5806 {
5807         unsigned int i;
5808
5809         for (i = 0; i < 15; i++) {
5810                 if (skl_cdclk_pcu_ready(dev_priv))
5811                         return true;
5812                 udelay(10);
5813         }
5814
5815         return false;
5816 }
5817
5818 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5819 {
5820         struct drm_device *dev = dev_priv->dev;
5821         u32 freq_select, pcu_ack;
5822
5823         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5824
5825         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5826                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5827                 return;
5828         }
5829
5830         /* set CDCLK_CTL */
5831         switch(freq) {
5832         case 450000:
5833         case 432000:
5834                 freq_select = CDCLK_FREQ_450_432;
5835                 pcu_ack = 1;
5836                 break;
5837         case 540000:
5838                 freq_select = CDCLK_FREQ_540;
5839                 pcu_ack = 2;
5840                 break;
5841         case 308570:
5842         case 337500:
5843         default:
5844                 freq_select = CDCLK_FREQ_337_308;
5845                 pcu_ack = 0;
5846                 break;
5847         case 617140:
5848         case 675000:
5849                 freq_select = CDCLK_FREQ_675_617;
5850                 pcu_ack = 3;
5851                 break;
5852         }
5853
5854         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5855         POSTING_READ(CDCLK_CTL);
5856
5857         /* inform PCU of the change */
5858         mutex_lock(&dev_priv->rps.hw_lock);
5859         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5860         mutex_unlock(&dev_priv->rps.hw_lock);
5861
5862         intel_update_cdclk(dev);
5863 }
5864
5865 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5866 {
5867         /* disable DBUF power */
5868         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5869         POSTING_READ(DBUF_CTL);
5870
5871         udelay(10);
5872
5873         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5874                 DRM_ERROR("DBuf power disable timeout\n");
5875
5876         /* disable DPLL0 */
5877         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5878         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5879                 DRM_ERROR("Couldn't disable DPLL0\n");
5880 }
5881
5882 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5883 {
5884         unsigned int required_vco;
5885
5886         /* DPLL0 not enabled (happens on early BIOS versions) */
5887         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5888                 /* enable DPLL0 */
5889                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5890                 skl_dpll0_enable(dev_priv, required_vco);
5891         }
5892
5893         /* set CDCLK to the frequency the BIOS chose */
5894         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5895
5896         /* enable DBUF power */
5897         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5898         POSTING_READ(DBUF_CTL);
5899
5900         udelay(10);
5901
5902         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5903                 DRM_ERROR("DBuf power enable timeout\n");
5904 }
5905
5906 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5907 {
5908         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5909         uint32_t cdctl = I915_READ(CDCLK_CTL);
5910         int freq = dev_priv->skl_boot_cdclk;
5911
5912         /*
5913          * check if the pre-os intialized the display
5914          * There is SWF18 scratchpad register defined which is set by the
5915          * pre-os which can be used by the OS drivers to check the status
5916          */
5917         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5918                 goto sanitize;
5919
5920         /* Is PLL enabled and locked ? */
5921         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5922                 goto sanitize;
5923
5924         /* DPLL okay; verify the cdclock
5925          *
5926          * Noticed in some instances that the freq selection is correct but
5927          * decimal part is programmed wrong from BIOS where pre-os does not
5928          * enable display. Verify the same as well.
5929          */
5930         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5931                 /* All well; nothing to sanitize */
5932                 return false;
5933 sanitize:
5934         /*
5935          * As of now initialize with max cdclk till
5936          * we get dynamic cdclk support
5937          * */
5938         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5939         skl_init_cdclk(dev_priv);
5940
5941         /* we did have to sanitize */
5942         return true;
5943 }
5944
5945 /* Adjust CDclk dividers to allow high res or save power if possible */
5946 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5947 {
5948         struct drm_i915_private *dev_priv = dev->dev_private;
5949         u32 val, cmd;
5950
5951         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5952                                         != dev_priv->cdclk_freq);
5953
5954         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5955                 cmd = 2;
5956         else if (cdclk == 266667)
5957                 cmd = 1;
5958         else
5959                 cmd = 0;
5960
5961         mutex_lock(&dev_priv->rps.hw_lock);
5962         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5963         val &= ~DSPFREQGUAR_MASK;
5964         val |= (cmd << DSPFREQGUAR_SHIFT);
5965         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5966         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5967                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5968                      50)) {
5969                 DRM_ERROR("timed out waiting for CDclk change\n");
5970         }
5971         mutex_unlock(&dev_priv->rps.hw_lock);
5972
5973         mutex_lock(&dev_priv->sb_lock);
5974
5975         if (cdclk == 400000) {
5976                 u32 divider;
5977
5978                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5979
5980                 /* adjust cdclk divider */
5981                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5982                 val &= ~CCK_FREQUENCY_VALUES;
5983                 val |= divider;
5984                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5985
5986                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5987                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5988                              50))
5989                         DRM_ERROR("timed out waiting for CDclk change\n");
5990         }
5991
5992         /* adjust self-refresh exit latency value */
5993         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5994         val &= ~0x7f;
5995
5996         /*
5997          * For high bandwidth configs, we set a higher latency in the bunit
5998          * so that the core display fetch happens in time to avoid underruns.
5999          */
6000         if (cdclk == 400000)
6001                 val |= 4500 / 250; /* 4.5 usec */
6002         else
6003                 val |= 3000 / 250; /* 3.0 usec */
6004         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6005
6006         mutex_unlock(&dev_priv->sb_lock);
6007
6008         intel_update_cdclk(dev);
6009 }
6010
6011 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6012 {
6013         struct drm_i915_private *dev_priv = dev->dev_private;
6014         u32 val, cmd;
6015
6016         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6017                                                 != dev_priv->cdclk_freq);
6018
6019         switch (cdclk) {
6020         case 333333:
6021         case 320000:
6022         case 266667:
6023         case 200000:
6024                 break;
6025         default:
6026                 MISSING_CASE(cdclk);
6027                 return;
6028         }
6029
6030         /*
6031          * Specs are full of misinformation, but testing on actual
6032          * hardware has shown that we just need to write the desired
6033          * CCK divider into the Punit register.
6034          */
6035         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6036
6037         mutex_lock(&dev_priv->rps.hw_lock);
6038         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6039         val &= ~DSPFREQGUAR_MASK_CHV;
6040         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6041         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6042         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6043                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6044                      50)) {
6045                 DRM_ERROR("timed out waiting for CDclk change\n");
6046         }
6047         mutex_unlock(&dev_priv->rps.hw_lock);
6048
6049         intel_update_cdclk(dev);
6050 }
6051
6052 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6053                                  int max_pixclk)
6054 {
6055         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6056         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6057
6058         /*
6059          * Really only a few cases to deal with, as only 4 CDclks are supported:
6060          *   200MHz
6061          *   267MHz
6062          *   320/333MHz (depends on HPLL freq)
6063          *   400MHz (VLV only)
6064          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6065          * of the lower bin and adjust if needed.
6066          *
6067          * We seem to get an unstable or solid color picture at 200MHz.
6068          * Not sure what's wrong. For now use 200MHz only when all pipes
6069          * are off.
6070          */
6071         if (!IS_CHERRYVIEW(dev_priv) &&
6072             max_pixclk > freq_320*limit/100)
6073                 return 400000;
6074         else if (max_pixclk > 266667*limit/100)
6075                 return freq_320;
6076         else if (max_pixclk > 0)
6077                 return 266667;
6078         else
6079                 return 200000;
6080 }
6081
6082 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6083                               int max_pixclk)
6084 {
6085         /*
6086          * FIXME:
6087          * - remove the guardband, it's not needed on BXT
6088          * - set 19.2MHz bypass frequency if there are no active pipes
6089          */
6090         if (max_pixclk > 576000*9/10)
6091                 return 624000;
6092         else if (max_pixclk > 384000*9/10)
6093                 return 576000;
6094         else if (max_pixclk > 288000*9/10)
6095                 return 384000;
6096         else if (max_pixclk > 144000*9/10)
6097                 return 288000;
6098         else
6099                 return 144000;
6100 }
6101
6102 /* Compute the max pixel clock for new configuration. Uses atomic state if
6103  * that's non-NULL, look at current state otherwise. */
6104 static int intel_mode_max_pixclk(struct drm_device *dev,
6105                                  struct drm_atomic_state *state)
6106 {
6107         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6108         struct drm_i915_private *dev_priv = dev->dev_private;
6109         struct drm_crtc *crtc;
6110         struct drm_crtc_state *crtc_state;
6111         unsigned max_pixclk = 0, i;
6112         enum pipe pipe;
6113
6114         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6115                sizeof(intel_state->min_pixclk));
6116
6117         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6118                 int pixclk = 0;
6119
6120                 if (crtc_state->enable)
6121                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6122
6123                 intel_state->min_pixclk[i] = pixclk;
6124         }
6125
6126         if (!intel_state->active_crtcs)
6127                 return 0;
6128
6129         for_each_pipe(dev_priv, pipe)
6130                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6131
6132         return max_pixclk;
6133 }
6134
6135 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6136 {
6137         struct drm_device *dev = state->dev;
6138         struct drm_i915_private *dev_priv = dev->dev_private;
6139         int max_pixclk = intel_mode_max_pixclk(dev, state);
6140         struct intel_atomic_state *intel_state =
6141                 to_intel_atomic_state(state);
6142
6143         if (max_pixclk < 0)
6144                 return max_pixclk;
6145
6146         intel_state->cdclk = intel_state->dev_cdclk =
6147                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6148
6149         if (!intel_state->active_crtcs)
6150                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6151
6152         return 0;
6153 }
6154
6155 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6156 {
6157         struct drm_device *dev = state->dev;
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159         int max_pixclk = intel_mode_max_pixclk(dev, state);
6160         struct intel_atomic_state *intel_state =
6161                 to_intel_atomic_state(state);
6162
6163         if (max_pixclk < 0)
6164                 return max_pixclk;
6165
6166         intel_state->cdclk = intel_state->dev_cdclk =
6167                 broxton_calc_cdclk(dev_priv, max_pixclk);
6168
6169         if (!intel_state->active_crtcs)
6170                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6171
6172         return 0;
6173 }
6174
6175 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6176 {
6177         unsigned int credits, default_credits;
6178
6179         if (IS_CHERRYVIEW(dev_priv))
6180                 default_credits = PFI_CREDIT(12);
6181         else
6182                 default_credits = PFI_CREDIT(8);
6183
6184         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6185                 /* CHV suggested value is 31 or 63 */
6186                 if (IS_CHERRYVIEW(dev_priv))
6187                         credits = PFI_CREDIT_63;
6188                 else
6189                         credits = PFI_CREDIT(15);
6190         } else {
6191                 credits = default_credits;
6192         }
6193
6194         /*
6195          * WA - write default credits before re-programming
6196          * FIXME: should we also set the resend bit here?
6197          */
6198         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6199                    default_credits);
6200
6201         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6202                    credits | PFI_CREDIT_RESEND);
6203
6204         /*
6205          * FIXME is this guaranteed to clear
6206          * immediately or should we poll for it?
6207          */
6208         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6209 }
6210
6211 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6212 {
6213         struct drm_device *dev = old_state->dev;
6214         struct drm_i915_private *dev_priv = dev->dev_private;
6215         struct intel_atomic_state *old_intel_state =
6216                 to_intel_atomic_state(old_state);
6217         unsigned req_cdclk = old_intel_state->dev_cdclk;
6218
6219         /*
6220          * FIXME: We can end up here with all power domains off, yet
6221          * with a CDCLK frequency other than the minimum. To account
6222          * for this take the PIPE-A power domain, which covers the HW
6223          * blocks needed for the following programming. This can be
6224          * removed once it's guaranteed that we get here either with
6225          * the minimum CDCLK set, or the required power domains
6226          * enabled.
6227          */
6228         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6229
6230         if (IS_CHERRYVIEW(dev))
6231                 cherryview_set_cdclk(dev, req_cdclk);
6232         else
6233                 valleyview_set_cdclk(dev, req_cdclk);
6234
6235         vlv_program_pfi_credits(dev_priv);
6236
6237         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6238 }
6239
6240 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6241 {
6242         struct drm_device *dev = crtc->dev;
6243         struct drm_i915_private *dev_priv = to_i915(dev);
6244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245         struct intel_encoder *encoder;
6246         int pipe = intel_crtc->pipe;
6247
6248         if (WARN_ON(intel_crtc->active))
6249                 return;
6250
6251         if (intel_crtc->config->has_dp_encoder)
6252                 intel_dp_set_m_n(intel_crtc, M1_N1);
6253
6254         intel_set_pipe_timings(intel_crtc);
6255
6256         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6257                 struct drm_i915_private *dev_priv = dev->dev_private;
6258
6259                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6260                 I915_WRITE(CHV_CANVAS(pipe), 0);
6261         }
6262
6263         i9xx_set_pipeconf(intel_crtc);
6264
6265         intel_crtc->active = true;
6266
6267         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6268
6269         for_each_encoder_on_crtc(dev, crtc, encoder)
6270                 if (encoder->pre_pll_enable)
6271                         encoder->pre_pll_enable(encoder);
6272
6273         if (!intel_crtc->config->has_dsi_encoder) {
6274                 if (IS_CHERRYVIEW(dev)) {
6275                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6276                         chv_enable_pll(intel_crtc, intel_crtc->config);
6277                 } else {
6278                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6279                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6280                 }
6281         }
6282
6283         for_each_encoder_on_crtc(dev, crtc, encoder)
6284                 if (encoder->pre_enable)
6285                         encoder->pre_enable(encoder);
6286
6287         i9xx_pfit_enable(intel_crtc);
6288
6289         intel_crtc_load_lut(crtc);
6290
6291         intel_enable_pipe(intel_crtc);
6292
6293         assert_vblank_disabled(crtc);
6294         drm_crtc_vblank_on(crtc);
6295
6296         for_each_encoder_on_crtc(dev, crtc, encoder)
6297                 encoder->enable(encoder);
6298 }
6299
6300 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6301 {
6302         struct drm_device *dev = crtc->base.dev;
6303         struct drm_i915_private *dev_priv = dev->dev_private;
6304
6305         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6306         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6307 }
6308
6309 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6310 {
6311         struct drm_device *dev = crtc->dev;
6312         struct drm_i915_private *dev_priv = to_i915(dev);
6313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314         struct intel_encoder *encoder;
6315         int pipe = intel_crtc->pipe;
6316
6317         if (WARN_ON(intel_crtc->active))
6318                 return;
6319
6320         i9xx_set_pll_dividers(intel_crtc);
6321
6322         if (intel_crtc->config->has_dp_encoder)
6323                 intel_dp_set_m_n(intel_crtc, M1_N1);
6324
6325         intel_set_pipe_timings(intel_crtc);
6326
6327         i9xx_set_pipeconf(intel_crtc);
6328
6329         intel_crtc->active = true;
6330
6331         if (!IS_GEN2(dev))
6332                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6333
6334         for_each_encoder_on_crtc(dev, crtc, encoder)
6335                 if (encoder->pre_enable)
6336                         encoder->pre_enable(encoder);
6337
6338         i9xx_enable_pll(intel_crtc);
6339
6340         i9xx_pfit_enable(intel_crtc);
6341
6342         intel_crtc_load_lut(crtc);
6343
6344         intel_update_watermarks(crtc);
6345         intel_enable_pipe(intel_crtc);
6346
6347         assert_vblank_disabled(crtc);
6348         drm_crtc_vblank_on(crtc);
6349
6350         for_each_encoder_on_crtc(dev, crtc, encoder)
6351                 encoder->enable(encoder);
6352
6353         intel_fbc_enable(intel_crtc);
6354 }
6355
6356 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6357 {
6358         struct drm_device *dev = crtc->base.dev;
6359         struct drm_i915_private *dev_priv = dev->dev_private;
6360
6361         if (!crtc->config->gmch_pfit.control)
6362                 return;
6363
6364         assert_pipe_disabled(dev_priv, crtc->pipe);
6365
6366         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6367                          I915_READ(PFIT_CONTROL));
6368         I915_WRITE(PFIT_CONTROL, 0);
6369 }
6370
6371 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6372 {
6373         struct drm_device *dev = crtc->dev;
6374         struct drm_i915_private *dev_priv = dev->dev_private;
6375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376         struct intel_encoder *encoder;
6377         int pipe = intel_crtc->pipe;
6378
6379         /*
6380          * On gen2 planes are double buffered but the pipe isn't, so we must
6381          * wait for planes to fully turn off before disabling the pipe.
6382          * We also need to wait on all gmch platforms because of the
6383          * self-refresh mode constraint explained above.
6384          */
6385         intel_wait_for_vblank(dev, pipe);
6386
6387         for_each_encoder_on_crtc(dev, crtc, encoder)
6388                 encoder->disable(encoder);
6389
6390         drm_crtc_vblank_off(crtc);
6391         assert_vblank_disabled(crtc);
6392
6393         intel_disable_pipe(intel_crtc);
6394
6395         i9xx_pfit_disable(intel_crtc);
6396
6397         for_each_encoder_on_crtc(dev, crtc, encoder)
6398                 if (encoder->post_disable)
6399                         encoder->post_disable(encoder);
6400
6401         if (!intel_crtc->config->has_dsi_encoder) {
6402                 if (IS_CHERRYVIEW(dev))
6403                         chv_disable_pll(dev_priv, pipe);
6404                 else if (IS_VALLEYVIEW(dev))
6405                         vlv_disable_pll(dev_priv, pipe);
6406                 else
6407                         i9xx_disable_pll(intel_crtc);
6408         }
6409
6410         for_each_encoder_on_crtc(dev, crtc, encoder)
6411                 if (encoder->post_pll_disable)
6412                         encoder->post_pll_disable(encoder);
6413
6414         if (!IS_GEN2(dev))
6415                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6416
6417         intel_fbc_disable_crtc(intel_crtc);
6418 }
6419
6420 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6421 {
6422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6423         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6424         enum intel_display_power_domain domain;
6425         unsigned long domains;
6426
6427         if (!intel_crtc->active)
6428                 return;
6429
6430         if (to_intel_plane_state(crtc->primary->state)->visible) {
6431                 WARN_ON(intel_crtc->unpin_work);
6432
6433                 intel_pre_disable_primary(crtc);
6434
6435                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6436                 to_intel_plane_state(crtc->primary->state)->visible = false;
6437         }
6438
6439         dev_priv->display.crtc_disable(crtc);
6440         intel_crtc->active = false;
6441         intel_update_watermarks(crtc);
6442         intel_disable_shared_dpll(intel_crtc);
6443
6444         domains = intel_crtc->enabled_power_domains;
6445         for_each_power_domain(domain, domains)
6446                 intel_display_power_put(dev_priv, domain);
6447         intel_crtc->enabled_power_domains = 0;
6448
6449         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6450         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6451 }
6452
6453 /*
6454  * turn all crtc's off, but do not adjust state
6455  * This has to be paired with a call to intel_modeset_setup_hw_state.
6456  */
6457 int intel_display_suspend(struct drm_device *dev)
6458 {
6459         struct drm_mode_config *config = &dev->mode_config;
6460         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6461         struct drm_atomic_state *state;
6462         struct drm_crtc *crtc;
6463         unsigned crtc_mask = 0;
6464         int ret = 0;
6465
6466         if (WARN_ON(!ctx))
6467                 return 0;
6468
6469         lockdep_assert_held(&ctx->ww_ctx);
6470         state = drm_atomic_state_alloc(dev);
6471         if (WARN_ON(!state))
6472                 return -ENOMEM;
6473
6474         state->acquire_ctx = ctx;
6475         state->allow_modeset = true;
6476
6477         for_each_crtc(dev, crtc) {
6478                 struct drm_crtc_state *crtc_state =
6479                         drm_atomic_get_crtc_state(state, crtc);
6480
6481                 ret = PTR_ERR_OR_ZERO(crtc_state);
6482                 if (ret)
6483                         goto free;
6484
6485                 if (!crtc_state->active)
6486                         continue;
6487
6488                 crtc_state->active = false;
6489                 crtc_mask |= 1 << drm_crtc_index(crtc);
6490         }
6491
6492         if (crtc_mask) {
6493                 ret = drm_atomic_commit(state);
6494
6495                 if (!ret) {
6496                         for_each_crtc(dev, crtc)
6497                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6498                                         crtc->state->active = true;
6499
6500                         return ret;
6501                 }
6502         }
6503
6504 free:
6505         if (ret)
6506                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6507         drm_atomic_state_free(state);
6508         return ret;
6509 }
6510
6511 void intel_encoder_destroy(struct drm_encoder *encoder)
6512 {
6513         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6514
6515         drm_encoder_cleanup(encoder);
6516         kfree(intel_encoder);
6517 }
6518
6519 /* Cross check the actual hw state with our own modeset state tracking (and it's
6520  * internal consistency). */
6521 static void intel_connector_check_state(struct intel_connector *connector)
6522 {
6523         struct drm_crtc *crtc = connector->base.state->crtc;
6524
6525         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6526                       connector->base.base.id,
6527                       connector->base.name);
6528
6529         if (connector->get_hw_state(connector)) {
6530                 struct intel_encoder *encoder = connector->encoder;
6531                 struct drm_connector_state *conn_state = connector->base.state;
6532
6533                 I915_STATE_WARN(!crtc,
6534                          "connector enabled without attached crtc\n");
6535
6536                 if (!crtc)
6537                         return;
6538
6539                 I915_STATE_WARN(!crtc->state->active,
6540                       "connector is active, but attached crtc isn't\n");
6541
6542                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6543                         return;
6544
6545                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6546                         "atomic encoder doesn't match attached encoder\n");
6547
6548                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6549                         "attached encoder crtc differs from connector crtc\n");
6550         } else {
6551                 I915_STATE_WARN(crtc && crtc->state->active,
6552                         "attached crtc is active, but connector isn't\n");
6553                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6554                         "best encoder set without crtc!\n");
6555         }
6556 }
6557
6558 int intel_connector_init(struct intel_connector *connector)
6559 {
6560         struct drm_connector_state *connector_state;
6561
6562         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6563         if (!connector_state)
6564                 return -ENOMEM;
6565
6566         connector->base.state = connector_state;
6567         return 0;
6568 }
6569
6570 struct intel_connector *intel_connector_alloc(void)
6571 {
6572         struct intel_connector *connector;
6573
6574         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6575         if (!connector)
6576                 return NULL;
6577
6578         if (intel_connector_init(connector) < 0) {
6579                 kfree(connector);
6580                 return NULL;
6581         }
6582
6583         return connector;
6584 }
6585
6586 /* Simple connector->get_hw_state implementation for encoders that support only
6587  * one connector and no cloning and hence the encoder state determines the state
6588  * of the connector. */
6589 bool intel_connector_get_hw_state(struct intel_connector *connector)
6590 {
6591         enum pipe pipe = 0;
6592         struct intel_encoder *encoder = connector->encoder;
6593
6594         return encoder->get_hw_state(encoder, &pipe);
6595 }
6596
6597 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6598 {
6599         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6600                 return crtc_state->fdi_lanes;
6601
6602         return 0;
6603 }
6604
6605 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6606                                      struct intel_crtc_state *pipe_config)
6607 {
6608         struct drm_atomic_state *state = pipe_config->base.state;
6609         struct intel_crtc *other_crtc;
6610         struct intel_crtc_state *other_crtc_state;
6611
6612         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6613                       pipe_name(pipe), pipe_config->fdi_lanes);
6614         if (pipe_config->fdi_lanes > 4) {
6615                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6616                               pipe_name(pipe), pipe_config->fdi_lanes);
6617                 return -EINVAL;
6618         }
6619
6620         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6621                 if (pipe_config->fdi_lanes > 2) {
6622                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6623                                       pipe_config->fdi_lanes);
6624                         return -EINVAL;
6625                 } else {
6626                         return 0;
6627                 }
6628         }
6629
6630         if (INTEL_INFO(dev)->num_pipes == 2)
6631                 return 0;
6632
6633         /* Ivybridge 3 pipe is really complicated */
6634         switch (pipe) {
6635         case PIPE_A:
6636                 return 0;
6637         case PIPE_B:
6638                 if (pipe_config->fdi_lanes <= 2)
6639                         return 0;
6640
6641                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6642                 other_crtc_state =
6643                         intel_atomic_get_crtc_state(state, other_crtc);
6644                 if (IS_ERR(other_crtc_state))
6645                         return PTR_ERR(other_crtc_state);
6646
6647                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6648                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6649                                       pipe_name(pipe), pipe_config->fdi_lanes);
6650                         return -EINVAL;
6651                 }
6652                 return 0;
6653         case PIPE_C:
6654                 if (pipe_config->fdi_lanes > 2) {
6655                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6656                                       pipe_name(pipe), pipe_config->fdi_lanes);
6657                         return -EINVAL;
6658                 }
6659
6660                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6661                 other_crtc_state =
6662                         intel_atomic_get_crtc_state(state, other_crtc);
6663                 if (IS_ERR(other_crtc_state))
6664                         return PTR_ERR(other_crtc_state);
6665
6666                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6667                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6668                         return -EINVAL;
6669                 }
6670                 return 0;
6671         default:
6672                 BUG();
6673         }
6674 }
6675
6676 #define RETRY 1
6677 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6678                                        struct intel_crtc_state *pipe_config)
6679 {
6680         struct drm_device *dev = intel_crtc->base.dev;
6681         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6682         int lane, link_bw, fdi_dotclock, ret;
6683         bool needs_recompute = false;
6684
6685 retry:
6686         /* FDI is a binary signal running at ~2.7GHz, encoding
6687          * each output octet as 10 bits. The actual frequency
6688          * is stored as a divider into a 100MHz clock, and the
6689          * mode pixel clock is stored in units of 1KHz.
6690          * Hence the bw of each lane in terms of the mode signal
6691          * is:
6692          */
6693         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6694
6695         fdi_dotclock = adjusted_mode->crtc_clock;
6696
6697         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6698                                            pipe_config->pipe_bpp);
6699
6700         pipe_config->fdi_lanes = lane;
6701
6702         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6703                                link_bw, &pipe_config->fdi_m_n);
6704
6705         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6706                                        intel_crtc->pipe, pipe_config);
6707         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6708                 pipe_config->pipe_bpp -= 2*3;
6709                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6710                               pipe_config->pipe_bpp);
6711                 needs_recompute = true;
6712                 pipe_config->bw_constrained = true;
6713
6714                 goto retry;
6715         }
6716
6717         if (needs_recompute)
6718                 return RETRY;
6719
6720         return ret;
6721 }
6722
6723 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6724                                      struct intel_crtc_state *pipe_config)
6725 {
6726         if (pipe_config->pipe_bpp > 24)
6727                 return false;
6728
6729         /* HSW can handle pixel rate up to cdclk? */
6730         if (IS_HASWELL(dev_priv->dev))
6731                 return true;
6732
6733         /*
6734          * We compare against max which means we must take
6735          * the increased cdclk requirement into account when
6736          * calculating the new cdclk.
6737          *
6738          * Should measure whether using a lower cdclk w/o IPS
6739          */
6740         return ilk_pipe_pixel_rate(pipe_config) <=
6741                 dev_priv->max_cdclk_freq * 95 / 100;
6742 }
6743
6744 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6745                                    struct intel_crtc_state *pipe_config)
6746 {
6747         struct drm_device *dev = crtc->base.dev;
6748         struct drm_i915_private *dev_priv = dev->dev_private;
6749
6750         pipe_config->ips_enabled = i915.enable_ips &&
6751                 hsw_crtc_supports_ips(crtc) &&
6752                 pipe_config_supports_ips(dev_priv, pipe_config);
6753 }
6754
6755 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6756 {
6757         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6758
6759         /* GDG double wide on either pipe, otherwise pipe A only */
6760         return INTEL_INFO(dev_priv)->gen < 4 &&
6761                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6762 }
6763
6764 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6765                                      struct intel_crtc_state *pipe_config)
6766 {
6767         struct drm_device *dev = crtc->base.dev;
6768         struct drm_i915_private *dev_priv = dev->dev_private;
6769         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6770
6771         /* FIXME should check pixel clock limits on all platforms */
6772         if (INTEL_INFO(dev)->gen < 4) {
6773                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6774
6775                 /*
6776                  * Enable double wide mode when the dot clock
6777                  * is > 90% of the (display) core speed.
6778                  */
6779                 if (intel_crtc_supports_double_wide(crtc) &&
6780                     adjusted_mode->crtc_clock > clock_limit) {
6781                         clock_limit *= 2;
6782                         pipe_config->double_wide = true;
6783                 }
6784
6785                 if (adjusted_mode->crtc_clock > clock_limit) {
6786                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6787                                       adjusted_mode->crtc_clock, clock_limit,
6788                                       yesno(pipe_config->double_wide));
6789                         return -EINVAL;
6790                 }
6791         }
6792
6793         /*
6794          * Pipe horizontal size must be even in:
6795          * - DVO ganged mode
6796          * - LVDS dual channel mode
6797          * - Double wide pipe
6798          */
6799         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6800              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6801                 pipe_config->pipe_src_w &= ~1;
6802
6803         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6804          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6805          */
6806         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6807                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6808                 return -EINVAL;
6809
6810         if (HAS_IPS(dev))
6811                 hsw_compute_ips_config(crtc, pipe_config);
6812
6813         if (pipe_config->has_pch_encoder)
6814                 return ironlake_fdi_compute_config(crtc, pipe_config);
6815
6816         return 0;
6817 }
6818
6819 static int skylake_get_display_clock_speed(struct drm_device *dev)
6820 {
6821         struct drm_i915_private *dev_priv = to_i915(dev);
6822         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6823         uint32_t cdctl = I915_READ(CDCLK_CTL);
6824         uint32_t linkrate;
6825
6826         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6827                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6828
6829         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6830                 return 540000;
6831
6832         linkrate = (I915_READ(DPLL_CTRL1) &
6833                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6834
6835         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6836             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6837                 /* vco 8640 */
6838                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6839                 case CDCLK_FREQ_450_432:
6840                         return 432000;
6841                 case CDCLK_FREQ_337_308:
6842                         return 308570;
6843                 case CDCLK_FREQ_675_617:
6844                         return 617140;
6845                 default:
6846                         WARN(1, "Unknown cd freq selection\n");
6847                 }
6848         } else {
6849                 /* vco 8100 */
6850                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6851                 case CDCLK_FREQ_450_432:
6852                         return 450000;
6853                 case CDCLK_FREQ_337_308:
6854                         return 337500;
6855                 case CDCLK_FREQ_675_617:
6856                         return 675000;
6857                 default:
6858                         WARN(1, "Unknown cd freq selection\n");
6859                 }
6860         }
6861
6862         /* error case, do as if DPLL0 isn't enabled */
6863         return 24000;
6864 }
6865
6866 static int broxton_get_display_clock_speed(struct drm_device *dev)
6867 {
6868         struct drm_i915_private *dev_priv = to_i915(dev);
6869         uint32_t cdctl = I915_READ(CDCLK_CTL);
6870         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6871         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6872         int cdclk;
6873
6874         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6875                 return 19200;
6876
6877         cdclk = 19200 * pll_ratio / 2;
6878
6879         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6880         case BXT_CDCLK_CD2X_DIV_SEL_1:
6881                 return cdclk;  /* 576MHz or 624MHz */
6882         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6883                 return cdclk * 2 / 3; /* 384MHz */
6884         case BXT_CDCLK_CD2X_DIV_SEL_2:
6885                 return cdclk / 2; /* 288MHz */
6886         case BXT_CDCLK_CD2X_DIV_SEL_4:
6887                 return cdclk / 4; /* 144MHz */
6888         }
6889
6890         /* error case, do as if DE PLL isn't enabled */
6891         return 19200;
6892 }
6893
6894 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6895 {
6896         struct drm_i915_private *dev_priv = dev->dev_private;
6897         uint32_t lcpll = I915_READ(LCPLL_CTL);
6898         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6899
6900         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6901                 return 800000;
6902         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6903                 return 450000;
6904         else if (freq == LCPLL_CLK_FREQ_450)
6905                 return 450000;
6906         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6907                 return 540000;
6908         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6909                 return 337500;
6910         else
6911                 return 675000;
6912 }
6913
6914 static int haswell_get_display_clock_speed(struct drm_device *dev)
6915 {
6916         struct drm_i915_private *dev_priv = dev->dev_private;
6917         uint32_t lcpll = I915_READ(LCPLL_CTL);
6918         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6919
6920         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6921                 return 800000;
6922         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6923                 return 450000;
6924         else if (freq == LCPLL_CLK_FREQ_450)
6925                 return 450000;
6926         else if (IS_HSW_ULT(dev))
6927                 return 337500;
6928         else
6929                 return 540000;
6930 }
6931
6932 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6933 {
6934         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6935                                       CCK_DISPLAY_CLOCK_CONTROL);
6936 }
6937
6938 static int ilk_get_display_clock_speed(struct drm_device *dev)
6939 {
6940         return 450000;
6941 }
6942
6943 static int i945_get_display_clock_speed(struct drm_device *dev)
6944 {
6945         return 400000;
6946 }
6947
6948 static int i915_get_display_clock_speed(struct drm_device *dev)
6949 {
6950         return 333333;
6951 }
6952
6953 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6954 {
6955         return 200000;
6956 }
6957
6958 static int pnv_get_display_clock_speed(struct drm_device *dev)
6959 {
6960         u16 gcfgc = 0;
6961
6962         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6963
6964         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6965         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6966                 return 266667;
6967         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6968                 return 333333;
6969         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6970                 return 444444;
6971         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6972                 return 200000;
6973         default:
6974                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6975         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6976                 return 133333;
6977         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6978                 return 166667;
6979         }
6980 }
6981
6982 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6983 {
6984         u16 gcfgc = 0;
6985
6986         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6987
6988         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6989                 return 133333;
6990         else {
6991                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6992                 case GC_DISPLAY_CLOCK_333_MHZ:
6993                         return 333333;
6994                 default:
6995                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6996                         return 190000;
6997                 }
6998         }
6999 }
7000
7001 static int i865_get_display_clock_speed(struct drm_device *dev)
7002 {
7003         return 266667;
7004 }
7005
7006 static int i85x_get_display_clock_speed(struct drm_device *dev)
7007 {
7008         u16 hpllcc = 0;
7009
7010         /*
7011          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7012          * encoding is different :(
7013          * FIXME is this the right way to detect 852GM/852GMV?
7014          */
7015         if (dev->pdev->revision == 0x1)
7016                 return 133333;
7017
7018         pci_bus_read_config_word(dev->pdev->bus,
7019                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7020
7021         /* Assume that the hardware is in the high speed state.  This
7022          * should be the default.
7023          */
7024         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7025         case GC_CLOCK_133_200:
7026         case GC_CLOCK_133_200_2:
7027         case GC_CLOCK_100_200:
7028                 return 200000;
7029         case GC_CLOCK_166_250:
7030                 return 250000;
7031         case GC_CLOCK_100_133:
7032                 return 133333;
7033         case GC_CLOCK_133_266:
7034         case GC_CLOCK_133_266_2:
7035         case GC_CLOCK_166_266:
7036                 return 266667;
7037         }
7038
7039         /* Shouldn't happen */
7040         return 0;
7041 }
7042
7043 static int i830_get_display_clock_speed(struct drm_device *dev)
7044 {
7045         return 133333;
7046 }
7047
7048 static unsigned int intel_hpll_vco(struct drm_device *dev)
7049 {
7050         struct drm_i915_private *dev_priv = dev->dev_private;
7051         static const unsigned int blb_vco[8] = {
7052                 [0] = 3200000,
7053                 [1] = 4000000,
7054                 [2] = 5333333,
7055                 [3] = 4800000,
7056                 [4] = 6400000,
7057         };
7058         static const unsigned int pnv_vco[8] = {
7059                 [0] = 3200000,
7060                 [1] = 4000000,
7061                 [2] = 5333333,
7062                 [3] = 4800000,
7063                 [4] = 2666667,
7064         };
7065         static const unsigned int cl_vco[8] = {
7066                 [0] = 3200000,
7067                 [1] = 4000000,
7068                 [2] = 5333333,
7069                 [3] = 6400000,
7070                 [4] = 3333333,
7071                 [5] = 3566667,
7072                 [6] = 4266667,
7073         };
7074         static const unsigned int elk_vco[8] = {
7075                 [0] = 3200000,
7076                 [1] = 4000000,
7077                 [2] = 5333333,
7078                 [3] = 4800000,
7079         };
7080         static const unsigned int ctg_vco[8] = {
7081                 [0] = 3200000,
7082                 [1] = 4000000,
7083                 [2] = 5333333,
7084                 [3] = 6400000,
7085                 [4] = 2666667,
7086                 [5] = 4266667,
7087         };
7088         const unsigned int *vco_table;
7089         unsigned int vco;
7090         uint8_t tmp = 0;
7091
7092         /* FIXME other chipsets? */
7093         if (IS_GM45(dev))
7094                 vco_table = ctg_vco;
7095         else if (IS_G4X(dev))
7096                 vco_table = elk_vco;
7097         else if (IS_CRESTLINE(dev))
7098                 vco_table = cl_vco;
7099         else if (IS_PINEVIEW(dev))
7100                 vco_table = pnv_vco;
7101         else if (IS_G33(dev))
7102                 vco_table = blb_vco;
7103         else
7104                 return 0;
7105
7106         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7107
7108         vco = vco_table[tmp & 0x7];
7109         if (vco == 0)
7110                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7111         else
7112                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7113
7114         return vco;
7115 }
7116
7117 static int gm45_get_display_clock_speed(struct drm_device *dev)
7118 {
7119         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7120         uint16_t tmp = 0;
7121
7122         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7123
7124         cdclk_sel = (tmp >> 12) & 0x1;
7125
7126         switch (vco) {
7127         case 2666667:
7128         case 4000000:
7129         case 5333333:
7130                 return cdclk_sel ? 333333 : 222222;
7131         case 3200000:
7132                 return cdclk_sel ? 320000 : 228571;
7133         default:
7134                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7135                 return 222222;
7136         }
7137 }
7138
7139 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7140 {
7141         static const uint8_t div_3200[] = { 16, 10,  8 };
7142         static const uint8_t div_4000[] = { 20, 12, 10 };
7143         static const uint8_t div_5333[] = { 24, 16, 14 };
7144         const uint8_t *div_table;
7145         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7146         uint16_t tmp = 0;
7147
7148         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7149
7150         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7151
7152         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7153                 goto fail;
7154
7155         switch (vco) {
7156         case 3200000:
7157                 div_table = div_3200;
7158                 break;
7159         case 4000000:
7160                 div_table = div_4000;
7161                 break;
7162         case 5333333:
7163                 div_table = div_5333;
7164                 break;
7165         default:
7166                 goto fail;
7167         }
7168
7169         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7170
7171 fail:
7172         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7173         return 200000;
7174 }
7175
7176 static int g33_get_display_clock_speed(struct drm_device *dev)
7177 {
7178         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7179         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7180         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7181         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7182         const uint8_t *div_table;
7183         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7184         uint16_t tmp = 0;
7185
7186         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7187
7188         cdclk_sel = (tmp >> 4) & 0x7;
7189
7190         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7191                 goto fail;
7192
7193         switch (vco) {
7194         case 3200000:
7195                 div_table = div_3200;
7196                 break;
7197         case 4000000:
7198                 div_table = div_4000;
7199                 break;
7200         case 4800000:
7201                 div_table = div_4800;
7202                 break;
7203         case 5333333:
7204                 div_table = div_5333;
7205                 break;
7206         default:
7207                 goto fail;
7208         }
7209
7210         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7211
7212 fail:
7213         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7214         return 190476;
7215 }
7216
7217 static void
7218 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7219 {
7220         while (*num > DATA_LINK_M_N_MASK ||
7221                *den > DATA_LINK_M_N_MASK) {
7222                 *num >>= 1;
7223                 *den >>= 1;
7224         }
7225 }
7226
7227 static void compute_m_n(unsigned int m, unsigned int n,
7228                         uint32_t *ret_m, uint32_t *ret_n)
7229 {
7230         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7231         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7232         intel_reduce_m_n_ratio(ret_m, ret_n);
7233 }
7234
7235 void
7236 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7237                        int pixel_clock, int link_clock,
7238                        struct intel_link_m_n *m_n)
7239 {
7240         m_n->tu = 64;
7241
7242         compute_m_n(bits_per_pixel * pixel_clock,
7243                     link_clock * nlanes * 8,
7244                     &m_n->gmch_m, &m_n->gmch_n);
7245
7246         compute_m_n(pixel_clock, link_clock,
7247                     &m_n->link_m, &m_n->link_n);
7248 }
7249
7250 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7251 {
7252         if (i915.panel_use_ssc >= 0)
7253                 return i915.panel_use_ssc != 0;
7254         return dev_priv->vbt.lvds_use_ssc
7255                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7256 }
7257
7258 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7259                            int num_connectors)
7260 {
7261         struct drm_device *dev = crtc_state->base.crtc->dev;
7262         struct drm_i915_private *dev_priv = dev->dev_private;
7263         int refclk;
7264
7265         WARN_ON(!crtc_state->base.state);
7266
7267         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7268                 refclk = 100000;
7269         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7270             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7271                 refclk = dev_priv->vbt.lvds_ssc_freq;
7272                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7273         } else if (!IS_GEN2(dev)) {
7274                 refclk = 96000;
7275         } else {
7276                 refclk = 48000;
7277         }
7278
7279         return refclk;
7280 }
7281
7282 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7283 {
7284         return (1 << dpll->n) << 16 | dpll->m2;
7285 }
7286
7287 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7288 {
7289         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7290 }
7291
7292 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7293                                      struct intel_crtc_state *crtc_state,
7294                                      intel_clock_t *reduced_clock)
7295 {
7296         struct drm_device *dev = crtc->base.dev;
7297         u32 fp, fp2 = 0;
7298
7299         if (IS_PINEVIEW(dev)) {
7300                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7301                 if (reduced_clock)
7302                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7303         } else {
7304                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7305                 if (reduced_clock)
7306                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7307         }
7308
7309         crtc_state->dpll_hw_state.fp0 = fp;
7310
7311         crtc->lowfreq_avail = false;
7312         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7313             reduced_clock) {
7314                 crtc_state->dpll_hw_state.fp1 = fp2;
7315                 crtc->lowfreq_avail = true;
7316         } else {
7317                 crtc_state->dpll_hw_state.fp1 = fp;
7318         }
7319 }
7320
7321 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7322                 pipe)
7323 {
7324         u32 reg_val;
7325
7326         /*
7327          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7328          * and set it to a reasonable value instead.
7329          */
7330         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7331         reg_val &= 0xffffff00;
7332         reg_val |= 0x00000030;
7333         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7334
7335         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7336         reg_val &= 0x8cffffff;
7337         reg_val = 0x8c000000;
7338         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7339
7340         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7341         reg_val &= 0xffffff00;
7342         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7343
7344         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7345         reg_val &= 0x00ffffff;
7346         reg_val |= 0xb0000000;
7347         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7348 }
7349
7350 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7351                                          struct intel_link_m_n *m_n)
7352 {
7353         struct drm_device *dev = crtc->base.dev;
7354         struct drm_i915_private *dev_priv = dev->dev_private;
7355         int pipe = crtc->pipe;
7356
7357         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7358         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7359         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7360         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7361 }
7362
7363 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7364                                          struct intel_link_m_n *m_n,
7365                                          struct intel_link_m_n *m2_n2)
7366 {
7367         struct drm_device *dev = crtc->base.dev;
7368         struct drm_i915_private *dev_priv = dev->dev_private;
7369         int pipe = crtc->pipe;
7370         enum transcoder transcoder = crtc->config->cpu_transcoder;
7371
7372         if (INTEL_INFO(dev)->gen >= 5) {
7373                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7374                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7375                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7376                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7377                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7378                  * for gen < 8) and if DRRS is supported (to make sure the
7379                  * registers are not unnecessarily accessed).
7380                  */
7381                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7382                         crtc->config->has_drrs) {
7383                         I915_WRITE(PIPE_DATA_M2(transcoder),
7384                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7385                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7386                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7387                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7388                 }
7389         } else {
7390                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7391                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7392                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7393                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7394         }
7395 }
7396
7397 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7398 {
7399         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7400
7401         if (m_n == M1_N1) {
7402                 dp_m_n = &crtc->config->dp_m_n;
7403                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7404         } else if (m_n == M2_N2) {
7405
7406                 /*
7407                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7408                  * needs to be programmed into M1_N1.
7409                  */
7410                 dp_m_n = &crtc->config->dp_m2_n2;
7411         } else {
7412                 DRM_ERROR("Unsupported divider value\n");
7413                 return;
7414         }
7415
7416         if (crtc->config->has_pch_encoder)
7417                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7418         else
7419                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7420 }
7421
7422 static void vlv_compute_dpll(struct intel_crtc *crtc,
7423                              struct intel_crtc_state *pipe_config)
7424 {
7425         u32 dpll, dpll_md;
7426
7427         /*
7428          * Enable DPIO clock input. We should never disable the reference
7429          * clock for pipe B, since VGA hotplug / manual detection depends
7430          * on it.
7431          */
7432         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7433                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7434         /* We should never disable this, set it here for state tracking */
7435         if (crtc->pipe == PIPE_B)
7436                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7437         dpll |= DPLL_VCO_ENABLE;
7438         pipe_config->dpll_hw_state.dpll = dpll;
7439
7440         dpll_md = (pipe_config->pixel_multiplier - 1)
7441                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7442         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7443 }
7444
7445 static void vlv_prepare_pll(struct intel_crtc *crtc,
7446                             const struct intel_crtc_state *pipe_config)
7447 {
7448         struct drm_device *dev = crtc->base.dev;
7449         struct drm_i915_private *dev_priv = dev->dev_private;
7450         int pipe = crtc->pipe;
7451         u32 mdiv;
7452         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7453         u32 coreclk, reg_val;
7454
7455         mutex_lock(&dev_priv->sb_lock);
7456
7457         bestn = pipe_config->dpll.n;
7458         bestm1 = pipe_config->dpll.m1;
7459         bestm2 = pipe_config->dpll.m2;
7460         bestp1 = pipe_config->dpll.p1;
7461         bestp2 = pipe_config->dpll.p2;
7462
7463         /* See eDP HDMI DPIO driver vbios notes doc */
7464
7465         /* PLL B needs special handling */
7466         if (pipe == PIPE_B)
7467                 vlv_pllb_recal_opamp(dev_priv, pipe);
7468
7469         /* Set up Tx target for periodic Rcomp update */
7470         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7471
7472         /* Disable target IRef on PLL */
7473         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7474         reg_val &= 0x00ffffff;
7475         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7476
7477         /* Disable fast lock */
7478         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7479
7480         /* Set idtafcrecal before PLL is enabled */
7481         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7482         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7483         mdiv |= ((bestn << DPIO_N_SHIFT));
7484         mdiv |= (1 << DPIO_K_SHIFT);
7485
7486         /*
7487          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7488          * but we don't support that).
7489          * Note: don't use the DAC post divider as it seems unstable.
7490          */
7491         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7492         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7493
7494         mdiv |= DPIO_ENABLE_CALIBRATION;
7495         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7496
7497         /* Set HBR and RBR LPF coefficients */
7498         if (pipe_config->port_clock == 162000 ||
7499             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7500             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7501                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7502                                  0x009f0003);
7503         else
7504                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7505                                  0x00d0000f);
7506
7507         if (pipe_config->has_dp_encoder) {
7508                 /* Use SSC source */
7509                 if (pipe == PIPE_A)
7510                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7511                                          0x0df40000);
7512                 else
7513                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7514                                          0x0df70000);
7515         } else { /* HDMI or VGA */
7516                 /* Use bend source */
7517                 if (pipe == PIPE_A)
7518                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7519                                          0x0df70000);
7520                 else
7521                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7522                                          0x0df40000);
7523         }
7524
7525         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7526         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7527         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7528             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7529                 coreclk |= 0x01000000;
7530         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7531
7532         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7533         mutex_unlock(&dev_priv->sb_lock);
7534 }
7535
7536 static void chv_compute_dpll(struct intel_crtc *crtc,
7537                              struct intel_crtc_state *pipe_config)
7538 {
7539         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7540                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7541                 DPLL_VCO_ENABLE;
7542         if (crtc->pipe != PIPE_A)
7543                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7544
7545         pipe_config->dpll_hw_state.dpll_md =
7546                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7547 }
7548
7549 static void chv_prepare_pll(struct intel_crtc *crtc,
7550                             const struct intel_crtc_state *pipe_config)
7551 {
7552         struct drm_device *dev = crtc->base.dev;
7553         struct drm_i915_private *dev_priv = dev->dev_private;
7554         int pipe = crtc->pipe;
7555         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7556         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7557         u32 loopfilter, tribuf_calcntr;
7558         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7559         u32 dpio_val;
7560         int vco;
7561
7562         bestn = pipe_config->dpll.n;
7563         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7564         bestm1 = pipe_config->dpll.m1;
7565         bestm2 = pipe_config->dpll.m2 >> 22;
7566         bestp1 = pipe_config->dpll.p1;
7567         bestp2 = pipe_config->dpll.p2;
7568         vco = pipe_config->dpll.vco;
7569         dpio_val = 0;
7570         loopfilter = 0;
7571
7572         /*
7573          * Enable Refclk and SSC
7574          */
7575         I915_WRITE(dpll_reg,
7576                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7577
7578         mutex_lock(&dev_priv->sb_lock);
7579
7580         /* p1 and p2 divider */
7581         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7582                         5 << DPIO_CHV_S1_DIV_SHIFT |
7583                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7584                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7585                         1 << DPIO_CHV_K_DIV_SHIFT);
7586
7587         /* Feedback post-divider - m2 */
7588         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7589
7590         /* Feedback refclk divider - n and m1 */
7591         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7592                         DPIO_CHV_M1_DIV_BY_2 |
7593                         1 << DPIO_CHV_N_DIV_SHIFT);
7594
7595         /* M2 fraction division */
7596         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7597
7598         /* M2 fraction division enable */
7599         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7600         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7601         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7602         if (bestm2_frac)
7603                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7604         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7605
7606         /* Program digital lock detect threshold */
7607         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7608         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7609                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7610         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7611         if (!bestm2_frac)
7612                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7613         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7614
7615         /* Loop filter */
7616         if (vco == 5400000) {
7617                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7618                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7619                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7620                 tribuf_calcntr = 0x9;
7621         } else if (vco <= 6200000) {
7622                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7623                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7624                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7625                 tribuf_calcntr = 0x9;
7626         } else if (vco <= 6480000) {
7627                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7628                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7629                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7630                 tribuf_calcntr = 0x8;
7631         } else {
7632                 /* Not supported. Apply the same limits as in the max case */
7633                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7634                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7635                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7636                 tribuf_calcntr = 0;
7637         }
7638         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7639
7640         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7641         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7642         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7643         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7644
7645         /* AFC Recal */
7646         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7647                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7648                         DPIO_AFC_RECAL);
7649
7650         mutex_unlock(&dev_priv->sb_lock);
7651 }
7652
7653 /**
7654  * vlv_force_pll_on - forcibly enable just the PLL
7655  * @dev_priv: i915 private structure
7656  * @pipe: pipe PLL to enable
7657  * @dpll: PLL configuration
7658  *
7659  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7660  * in cases where we need the PLL enabled even when @pipe is not going to
7661  * be enabled.
7662  */
7663 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7664                       const struct dpll *dpll)
7665 {
7666         struct intel_crtc *crtc =
7667                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7668         struct intel_crtc_state pipe_config = {
7669                 .base.crtc = &crtc->base,
7670                 .pixel_multiplier = 1,
7671                 .dpll = *dpll,
7672         };
7673
7674         if (IS_CHERRYVIEW(dev)) {
7675                 chv_compute_dpll(crtc, &pipe_config);
7676                 chv_prepare_pll(crtc, &pipe_config);
7677                 chv_enable_pll(crtc, &pipe_config);
7678         } else {
7679                 vlv_compute_dpll(crtc, &pipe_config);
7680                 vlv_prepare_pll(crtc, &pipe_config);
7681                 vlv_enable_pll(crtc, &pipe_config);
7682         }
7683 }
7684
7685 /**
7686  * vlv_force_pll_off - forcibly disable just the PLL
7687  * @dev_priv: i915 private structure
7688  * @pipe: pipe PLL to disable
7689  *
7690  * Disable the PLL for @pipe. To be used in cases where we need
7691  * the PLL enabled even when @pipe is not going to be enabled.
7692  */
7693 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7694 {
7695         if (IS_CHERRYVIEW(dev))
7696                 chv_disable_pll(to_i915(dev), pipe);
7697         else
7698                 vlv_disable_pll(to_i915(dev), pipe);
7699 }
7700
7701 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7702                               struct intel_crtc_state *crtc_state,
7703                               intel_clock_t *reduced_clock,
7704                               int num_connectors)
7705 {
7706         struct drm_device *dev = crtc->base.dev;
7707         struct drm_i915_private *dev_priv = dev->dev_private;
7708         u32 dpll;
7709         bool is_sdvo;
7710         struct dpll *clock = &crtc_state->dpll;
7711
7712         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7713
7714         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7715                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7716
7717         dpll = DPLL_VGA_MODE_DIS;
7718
7719         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7720                 dpll |= DPLLB_MODE_LVDS;
7721         else
7722                 dpll |= DPLLB_MODE_DAC_SERIAL;
7723
7724         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7725                 dpll |= (crtc_state->pixel_multiplier - 1)
7726                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7727         }
7728
7729         if (is_sdvo)
7730                 dpll |= DPLL_SDVO_HIGH_SPEED;
7731
7732         if (crtc_state->has_dp_encoder)
7733                 dpll |= DPLL_SDVO_HIGH_SPEED;
7734
7735         /* compute bitmask from p1 value */
7736         if (IS_PINEVIEW(dev))
7737                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7738         else {
7739                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7740                 if (IS_G4X(dev) && reduced_clock)
7741                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7742         }
7743         switch (clock->p2) {
7744         case 5:
7745                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7746                 break;
7747         case 7:
7748                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7749                 break;
7750         case 10:
7751                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7752                 break;
7753         case 14:
7754                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7755                 break;
7756         }
7757         if (INTEL_INFO(dev)->gen >= 4)
7758                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7759
7760         if (crtc_state->sdvo_tv_clock)
7761                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7762         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7763                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7764                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7765         else
7766                 dpll |= PLL_REF_INPUT_DREFCLK;
7767
7768         dpll |= DPLL_VCO_ENABLE;
7769         crtc_state->dpll_hw_state.dpll = dpll;
7770
7771         if (INTEL_INFO(dev)->gen >= 4) {
7772                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7773                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7774                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7775         }
7776 }
7777
7778 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7779                               struct intel_crtc_state *crtc_state,
7780                               intel_clock_t *reduced_clock,
7781                               int num_connectors)
7782 {
7783         struct drm_device *dev = crtc->base.dev;
7784         struct drm_i915_private *dev_priv = dev->dev_private;
7785         u32 dpll;
7786         struct dpll *clock = &crtc_state->dpll;
7787
7788         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7789
7790         dpll = DPLL_VGA_MODE_DIS;
7791
7792         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7793                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7794         } else {
7795                 if (clock->p1 == 2)
7796                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7797                 else
7798                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7799                 if (clock->p2 == 4)
7800                         dpll |= PLL_P2_DIVIDE_BY_4;
7801         }
7802
7803         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7804                 dpll |= DPLL_DVO_2X_MODE;
7805
7806         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7807                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7808                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7809         else
7810                 dpll |= PLL_REF_INPUT_DREFCLK;
7811
7812         dpll |= DPLL_VCO_ENABLE;
7813         crtc_state->dpll_hw_state.dpll = dpll;
7814 }
7815
7816 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7817 {
7818         struct drm_device *dev = intel_crtc->base.dev;
7819         struct drm_i915_private *dev_priv = dev->dev_private;
7820         enum pipe pipe = intel_crtc->pipe;
7821         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7822         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7823         uint32_t crtc_vtotal, crtc_vblank_end;
7824         int vsyncshift = 0;
7825
7826         /* We need to be careful not to changed the adjusted mode, for otherwise
7827          * the hw state checker will get angry at the mismatch. */
7828         crtc_vtotal = adjusted_mode->crtc_vtotal;
7829         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7830
7831         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7832                 /* the chip adds 2 halflines automatically */
7833                 crtc_vtotal -= 1;
7834                 crtc_vblank_end -= 1;
7835
7836                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7837                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7838                 else
7839                         vsyncshift = adjusted_mode->crtc_hsync_start -
7840                                 adjusted_mode->crtc_htotal / 2;
7841                 if (vsyncshift < 0)
7842                         vsyncshift += adjusted_mode->crtc_htotal;
7843         }
7844
7845         if (INTEL_INFO(dev)->gen > 3)
7846                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7847
7848         I915_WRITE(HTOTAL(cpu_transcoder),
7849                    (adjusted_mode->crtc_hdisplay - 1) |
7850                    ((adjusted_mode->crtc_htotal - 1) << 16));
7851         I915_WRITE(HBLANK(cpu_transcoder),
7852                    (adjusted_mode->crtc_hblank_start - 1) |
7853                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7854         I915_WRITE(HSYNC(cpu_transcoder),
7855                    (adjusted_mode->crtc_hsync_start - 1) |
7856                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7857
7858         I915_WRITE(VTOTAL(cpu_transcoder),
7859                    (adjusted_mode->crtc_vdisplay - 1) |
7860                    ((crtc_vtotal - 1) << 16));
7861         I915_WRITE(VBLANK(cpu_transcoder),
7862                    (adjusted_mode->crtc_vblank_start - 1) |
7863                    ((crtc_vblank_end - 1) << 16));
7864         I915_WRITE(VSYNC(cpu_transcoder),
7865                    (adjusted_mode->crtc_vsync_start - 1) |
7866                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7867
7868         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7869          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7870          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7871          * bits. */
7872         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7873             (pipe == PIPE_B || pipe == PIPE_C))
7874                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7875
7876         /* pipesrc controls the size that is scaled from, which should
7877          * always be the user's requested size.
7878          */
7879         I915_WRITE(PIPESRC(pipe),
7880                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7881                    (intel_crtc->config->pipe_src_h - 1));
7882 }
7883
7884 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7885                                    struct intel_crtc_state *pipe_config)
7886 {
7887         struct drm_device *dev = crtc->base.dev;
7888         struct drm_i915_private *dev_priv = dev->dev_private;
7889         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7890         uint32_t tmp;
7891
7892         tmp = I915_READ(HTOTAL(cpu_transcoder));
7893         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7894         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7895         tmp = I915_READ(HBLANK(cpu_transcoder));
7896         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7897         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7898         tmp = I915_READ(HSYNC(cpu_transcoder));
7899         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7900         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7901
7902         tmp = I915_READ(VTOTAL(cpu_transcoder));
7903         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7904         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7905         tmp = I915_READ(VBLANK(cpu_transcoder));
7906         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7907         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7908         tmp = I915_READ(VSYNC(cpu_transcoder));
7909         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7910         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7911
7912         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7913                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7914                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7915                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7916         }
7917
7918         tmp = I915_READ(PIPESRC(crtc->pipe));
7919         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7920         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7921
7922         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7923         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7924 }
7925
7926 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7927                                  struct intel_crtc_state *pipe_config)
7928 {
7929         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7930         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7931         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7932         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7933
7934         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7935         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7936         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7937         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7938
7939         mode->flags = pipe_config->base.adjusted_mode.flags;
7940         mode->type = DRM_MODE_TYPE_DRIVER;
7941
7942         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7943         mode->flags |= pipe_config->base.adjusted_mode.flags;
7944
7945         mode->hsync = drm_mode_hsync(mode);
7946         mode->vrefresh = drm_mode_vrefresh(mode);
7947         drm_mode_set_name(mode);
7948 }
7949
7950 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7951 {
7952         struct drm_device *dev = intel_crtc->base.dev;
7953         struct drm_i915_private *dev_priv = dev->dev_private;
7954         uint32_t pipeconf;
7955
7956         pipeconf = 0;
7957
7958         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7959             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7960                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7961
7962         if (intel_crtc->config->double_wide)
7963                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7964
7965         /* only g4x and later have fancy bpc/dither controls */
7966         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7967                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7968                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7969                         pipeconf |= PIPECONF_DITHER_EN |
7970                                     PIPECONF_DITHER_TYPE_SP;
7971
7972                 switch (intel_crtc->config->pipe_bpp) {
7973                 case 18:
7974                         pipeconf |= PIPECONF_6BPC;
7975                         break;
7976                 case 24:
7977                         pipeconf |= PIPECONF_8BPC;
7978                         break;
7979                 case 30:
7980                         pipeconf |= PIPECONF_10BPC;
7981                         break;
7982                 default:
7983                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7984                         BUG();
7985                 }
7986         }
7987
7988         if (HAS_PIPE_CXSR(dev)) {
7989                 if (intel_crtc->lowfreq_avail) {
7990                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7991                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7992                 } else {
7993                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7994                 }
7995         }
7996
7997         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7998                 if (INTEL_INFO(dev)->gen < 4 ||
7999                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
8000                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8001                 else
8002                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8003         } else
8004                 pipeconf |= PIPECONF_PROGRESSIVE;
8005
8006         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8007              intel_crtc->config->limited_color_range)
8008                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8009
8010         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8011         POSTING_READ(PIPECONF(intel_crtc->pipe));
8012 }
8013
8014 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8015                                    struct intel_crtc_state *crtc_state)
8016 {
8017         struct drm_device *dev = crtc->base.dev;
8018         struct drm_i915_private *dev_priv = dev->dev_private;
8019         int refclk, num_connectors = 0;
8020         intel_clock_t clock;
8021         bool ok;
8022         const intel_limit_t *limit;
8023         struct drm_atomic_state *state = crtc_state->base.state;
8024         struct drm_connector *connector;
8025         struct drm_connector_state *connector_state;
8026         int i;
8027
8028         memset(&crtc_state->dpll_hw_state, 0,
8029                sizeof(crtc_state->dpll_hw_state));
8030
8031         if (crtc_state->has_dsi_encoder)
8032                 return 0;
8033
8034         for_each_connector_in_state(state, connector, connector_state, i) {
8035                 if (connector_state->crtc == &crtc->base)
8036                         num_connectors++;
8037         }
8038
8039         if (!crtc_state->clock_set) {
8040                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
8041
8042                 /*
8043                  * Returns a set of divisors for the desired target clock with
8044                  * the given refclk, or FALSE.  The returned values represent
8045                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
8046                  * 2) / p1 / p2.
8047                  */
8048                 limit = intel_limit(crtc_state, refclk);
8049                 ok = dev_priv->display.find_dpll(limit, crtc_state,
8050                                                  crtc_state->port_clock,
8051                                                  refclk, NULL, &clock);
8052                 if (!ok) {
8053                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
8054                         return -EINVAL;
8055                 }
8056
8057                 /* Compat-code for transition, will disappear. */
8058                 crtc_state->dpll.n = clock.n;
8059                 crtc_state->dpll.m1 = clock.m1;
8060                 crtc_state->dpll.m2 = clock.m2;
8061                 crtc_state->dpll.p1 = clock.p1;
8062                 crtc_state->dpll.p2 = clock.p2;
8063         }
8064
8065         if (IS_GEN2(dev)) {
8066                 i8xx_compute_dpll(crtc, crtc_state, NULL,
8067                                   num_connectors);
8068         } else if (IS_CHERRYVIEW(dev)) {
8069                 chv_compute_dpll(crtc, crtc_state);
8070         } else if (IS_VALLEYVIEW(dev)) {
8071                 vlv_compute_dpll(crtc, crtc_state);
8072         } else {
8073                 i9xx_compute_dpll(crtc, crtc_state, NULL,
8074                                   num_connectors);
8075         }
8076
8077         return 0;
8078 }
8079
8080 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8081                                  struct intel_crtc_state *pipe_config)
8082 {
8083         struct drm_device *dev = crtc->base.dev;
8084         struct drm_i915_private *dev_priv = dev->dev_private;
8085         uint32_t tmp;
8086
8087         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8088                 return;
8089
8090         tmp = I915_READ(PFIT_CONTROL);
8091         if (!(tmp & PFIT_ENABLE))
8092                 return;
8093
8094         /* Check whether the pfit is attached to our pipe. */
8095         if (INTEL_INFO(dev)->gen < 4) {
8096                 if (crtc->pipe != PIPE_B)
8097                         return;
8098         } else {
8099                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8100                         return;
8101         }
8102
8103         pipe_config->gmch_pfit.control = tmp;
8104         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8105         if (INTEL_INFO(dev)->gen < 5)
8106                 pipe_config->gmch_pfit.lvds_border_bits =
8107                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8108 }
8109
8110 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8111                                struct intel_crtc_state *pipe_config)
8112 {
8113         struct drm_device *dev = crtc->base.dev;
8114         struct drm_i915_private *dev_priv = dev->dev_private;
8115         int pipe = pipe_config->cpu_transcoder;
8116         intel_clock_t clock;
8117         u32 mdiv;
8118         int refclk = 100000;
8119
8120         /* In case of MIPI DPLL will not even be used */
8121         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8122                 return;
8123
8124         mutex_lock(&dev_priv->sb_lock);
8125         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8126         mutex_unlock(&dev_priv->sb_lock);
8127
8128         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8129         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8130         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8131         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8132         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8133
8134         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8135 }
8136
8137 static void
8138 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8139                               struct intel_initial_plane_config *plane_config)
8140 {
8141         struct drm_device *dev = crtc->base.dev;
8142         struct drm_i915_private *dev_priv = dev->dev_private;
8143         u32 val, base, offset;
8144         int pipe = crtc->pipe, plane = crtc->plane;
8145         int fourcc, pixel_format;
8146         unsigned int aligned_height;
8147         struct drm_framebuffer *fb;
8148         struct intel_framebuffer *intel_fb;
8149
8150         val = I915_READ(DSPCNTR(plane));
8151         if (!(val & DISPLAY_PLANE_ENABLE))
8152                 return;
8153
8154         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8155         if (!intel_fb) {
8156                 DRM_DEBUG_KMS("failed to alloc fb\n");
8157                 return;
8158         }
8159
8160         fb = &intel_fb->base;
8161
8162         if (INTEL_INFO(dev)->gen >= 4) {
8163                 if (val & DISPPLANE_TILED) {
8164                         plane_config->tiling = I915_TILING_X;
8165                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8166                 }
8167         }
8168
8169         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8170         fourcc = i9xx_format_to_fourcc(pixel_format);
8171         fb->pixel_format = fourcc;
8172         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8173
8174         if (INTEL_INFO(dev)->gen >= 4) {
8175                 if (plane_config->tiling)
8176                         offset = I915_READ(DSPTILEOFF(plane));
8177                 else
8178                         offset = I915_READ(DSPLINOFF(plane));
8179                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8180         } else {
8181                 base = I915_READ(DSPADDR(plane));
8182         }
8183         plane_config->base = base;
8184
8185         val = I915_READ(PIPESRC(pipe));
8186         fb->width = ((val >> 16) & 0xfff) + 1;
8187         fb->height = ((val >> 0) & 0xfff) + 1;
8188
8189         val = I915_READ(DSPSTRIDE(pipe));
8190         fb->pitches[0] = val & 0xffffffc0;
8191
8192         aligned_height = intel_fb_align_height(dev, fb->height,
8193                                                fb->pixel_format,
8194                                                fb->modifier[0]);
8195
8196         plane_config->size = fb->pitches[0] * aligned_height;
8197
8198         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8199                       pipe_name(pipe), plane, fb->width, fb->height,
8200                       fb->bits_per_pixel, base, fb->pitches[0],
8201                       plane_config->size);
8202
8203         plane_config->fb = intel_fb;
8204 }
8205
8206 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8207                                struct intel_crtc_state *pipe_config)
8208 {
8209         struct drm_device *dev = crtc->base.dev;
8210         struct drm_i915_private *dev_priv = dev->dev_private;
8211         int pipe = pipe_config->cpu_transcoder;
8212         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8213         intel_clock_t clock;
8214         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8215         int refclk = 100000;
8216
8217         mutex_lock(&dev_priv->sb_lock);
8218         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8219         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8220         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8221         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8222         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8223         mutex_unlock(&dev_priv->sb_lock);
8224
8225         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8226         clock.m2 = (pll_dw0 & 0xff) << 22;
8227         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8228                 clock.m2 |= pll_dw2 & 0x3fffff;
8229         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8230         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8231         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8232
8233         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8234 }
8235
8236 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8237                                  struct intel_crtc_state *pipe_config)
8238 {
8239         struct drm_device *dev = crtc->base.dev;
8240         struct drm_i915_private *dev_priv = dev->dev_private;
8241         uint32_t tmp;
8242
8243         if (!intel_display_power_is_enabled(dev_priv,
8244                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8245                 return false;
8246
8247         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8248         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8249
8250         tmp = I915_READ(PIPECONF(crtc->pipe));
8251         if (!(tmp & PIPECONF_ENABLE))
8252                 return false;
8253
8254         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8255                 switch (tmp & PIPECONF_BPC_MASK) {
8256                 case PIPECONF_6BPC:
8257                         pipe_config->pipe_bpp = 18;
8258                         break;
8259                 case PIPECONF_8BPC:
8260                         pipe_config->pipe_bpp = 24;
8261                         break;
8262                 case PIPECONF_10BPC:
8263                         pipe_config->pipe_bpp = 30;
8264                         break;
8265                 default:
8266                         break;
8267                 }
8268         }
8269
8270         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8271             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8272                 pipe_config->limited_color_range = true;
8273
8274         if (INTEL_INFO(dev)->gen < 4)
8275                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8276
8277         intel_get_pipe_timings(crtc, pipe_config);
8278
8279         i9xx_get_pfit_config(crtc, pipe_config);
8280
8281         if (INTEL_INFO(dev)->gen >= 4) {
8282                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8283                 pipe_config->pixel_multiplier =
8284                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8285                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8286                 pipe_config->dpll_hw_state.dpll_md = tmp;
8287         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8288                 tmp = I915_READ(DPLL(crtc->pipe));
8289                 pipe_config->pixel_multiplier =
8290                         ((tmp & SDVO_MULTIPLIER_MASK)
8291                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8292         } else {
8293                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8294                  * port and will be fixed up in the encoder->get_config
8295                  * function. */
8296                 pipe_config->pixel_multiplier = 1;
8297         }
8298         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8299         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8300                 /*
8301                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8302                  * on 830. Filter it out here so that we don't
8303                  * report errors due to that.
8304                  */
8305                 if (IS_I830(dev))
8306                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8307
8308                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8309                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8310         } else {
8311                 /* Mask out read-only status bits. */
8312                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8313                                                      DPLL_PORTC_READY_MASK |
8314                                                      DPLL_PORTB_READY_MASK);
8315         }
8316
8317         if (IS_CHERRYVIEW(dev))
8318                 chv_crtc_clock_get(crtc, pipe_config);
8319         else if (IS_VALLEYVIEW(dev))
8320                 vlv_crtc_clock_get(crtc, pipe_config);
8321         else
8322                 i9xx_crtc_clock_get(crtc, pipe_config);
8323
8324         /*
8325          * Normally the dotclock is filled in by the encoder .get_config()
8326          * but in case the pipe is enabled w/o any ports we need a sane
8327          * default.
8328          */
8329         pipe_config->base.adjusted_mode.crtc_clock =
8330                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8331
8332         return true;
8333 }
8334
8335 static void ironlake_init_pch_refclk(struct drm_device *dev)
8336 {
8337         struct drm_i915_private *dev_priv = dev->dev_private;
8338         struct intel_encoder *encoder;
8339         u32 val, final;
8340         bool has_lvds = false;
8341         bool has_cpu_edp = false;
8342         bool has_panel = false;
8343         bool has_ck505 = false;
8344         bool can_ssc = false;
8345
8346         /* We need to take the global config into account */
8347         for_each_intel_encoder(dev, encoder) {
8348                 switch (encoder->type) {
8349                 case INTEL_OUTPUT_LVDS:
8350                         has_panel = true;
8351                         has_lvds = true;
8352                         break;
8353                 case INTEL_OUTPUT_EDP:
8354                         has_panel = true;
8355                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8356                                 has_cpu_edp = true;
8357                         break;
8358                 default:
8359                         break;
8360                 }
8361         }
8362
8363         if (HAS_PCH_IBX(dev)) {
8364                 has_ck505 = dev_priv->vbt.display_clock_mode;
8365                 can_ssc = has_ck505;
8366         } else {
8367                 has_ck505 = false;
8368                 can_ssc = true;
8369         }
8370
8371         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8372                       has_panel, has_lvds, has_ck505);
8373
8374         /* Ironlake: try to setup display ref clock before DPLL
8375          * enabling. This is only under driver's control after
8376          * PCH B stepping, previous chipset stepping should be
8377          * ignoring this setting.
8378          */
8379         val = I915_READ(PCH_DREF_CONTROL);
8380
8381         /* As we must carefully and slowly disable/enable each source in turn,
8382          * compute the final state we want first and check if we need to
8383          * make any changes at all.
8384          */
8385         final = val;
8386         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8387         if (has_ck505)
8388                 final |= DREF_NONSPREAD_CK505_ENABLE;
8389         else
8390                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8391
8392         final &= ~DREF_SSC_SOURCE_MASK;
8393         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8394         final &= ~DREF_SSC1_ENABLE;
8395
8396         if (has_panel) {
8397                 final |= DREF_SSC_SOURCE_ENABLE;
8398
8399                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8400                         final |= DREF_SSC1_ENABLE;
8401
8402                 if (has_cpu_edp) {
8403                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8404                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8405                         else
8406                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8407                 } else
8408                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8409         } else {
8410                 final |= DREF_SSC_SOURCE_DISABLE;
8411                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8412         }
8413
8414         if (final == val)
8415                 return;
8416
8417         /* Always enable nonspread source */
8418         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8419
8420         if (has_ck505)
8421                 val |= DREF_NONSPREAD_CK505_ENABLE;
8422         else
8423                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8424
8425         if (has_panel) {
8426                 val &= ~DREF_SSC_SOURCE_MASK;
8427                 val |= DREF_SSC_SOURCE_ENABLE;
8428
8429                 /* SSC must be turned on before enabling the CPU output  */
8430                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8431                         DRM_DEBUG_KMS("Using SSC on panel\n");
8432                         val |= DREF_SSC1_ENABLE;
8433                 } else
8434                         val &= ~DREF_SSC1_ENABLE;
8435
8436                 /* Get SSC going before enabling the outputs */
8437                 I915_WRITE(PCH_DREF_CONTROL, val);
8438                 POSTING_READ(PCH_DREF_CONTROL);
8439                 udelay(200);
8440
8441                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8442
8443                 /* Enable CPU source on CPU attached eDP */
8444                 if (has_cpu_edp) {
8445                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8446                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8447                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8448                         } else
8449                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8450                 } else
8451                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8452
8453                 I915_WRITE(PCH_DREF_CONTROL, val);
8454                 POSTING_READ(PCH_DREF_CONTROL);
8455                 udelay(200);
8456         } else {
8457                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8458
8459                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8460
8461                 /* Turn off CPU output */
8462                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8463
8464                 I915_WRITE(PCH_DREF_CONTROL, val);
8465                 POSTING_READ(PCH_DREF_CONTROL);
8466                 udelay(200);
8467
8468                 /* Turn off the SSC source */
8469                 val &= ~DREF_SSC_SOURCE_MASK;
8470                 val |= DREF_SSC_SOURCE_DISABLE;
8471
8472                 /* Turn off SSC1 */
8473                 val &= ~DREF_SSC1_ENABLE;
8474
8475                 I915_WRITE(PCH_DREF_CONTROL, val);
8476                 POSTING_READ(PCH_DREF_CONTROL);
8477                 udelay(200);
8478         }
8479
8480         BUG_ON(val != final);
8481 }
8482
8483 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8484 {
8485         uint32_t tmp;
8486
8487         tmp = I915_READ(SOUTH_CHICKEN2);
8488         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8489         I915_WRITE(SOUTH_CHICKEN2, tmp);
8490
8491         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8492                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8493                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8494
8495         tmp = I915_READ(SOUTH_CHICKEN2);
8496         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8497         I915_WRITE(SOUTH_CHICKEN2, tmp);
8498
8499         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8500                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8501                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8502 }
8503
8504 /* WaMPhyProgramming:hsw */
8505 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8506 {
8507         uint32_t tmp;
8508
8509         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8510         tmp &= ~(0xFF << 24);
8511         tmp |= (0x12 << 24);
8512         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8513
8514         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8515         tmp |= (1 << 11);
8516         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8517
8518         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8519         tmp |= (1 << 11);
8520         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8521
8522         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8523         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8524         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8525
8526         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8527         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8528         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8529
8530         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8531         tmp &= ~(7 << 13);
8532         tmp |= (5 << 13);
8533         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8534
8535         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8536         tmp &= ~(7 << 13);
8537         tmp |= (5 << 13);
8538         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8539
8540         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8541         tmp &= ~0xFF;
8542         tmp |= 0x1C;
8543         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8544
8545         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8546         tmp &= ~0xFF;
8547         tmp |= 0x1C;
8548         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8549
8550         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8551         tmp &= ~(0xFF << 16);
8552         tmp |= (0x1C << 16);
8553         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8554
8555         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8556         tmp &= ~(0xFF << 16);
8557         tmp |= (0x1C << 16);
8558         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8559
8560         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8561         tmp |= (1 << 27);
8562         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8563
8564         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8565         tmp |= (1 << 27);
8566         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8567
8568         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8569         tmp &= ~(0xF << 28);
8570         tmp |= (4 << 28);
8571         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8572
8573         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8574         tmp &= ~(0xF << 28);
8575         tmp |= (4 << 28);
8576         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8577 }
8578
8579 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8580  * Programming" based on the parameters passed:
8581  * - Sequence to enable CLKOUT_DP
8582  * - Sequence to enable CLKOUT_DP without spread
8583  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8584  */
8585 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8586                                  bool with_fdi)
8587 {
8588         struct drm_i915_private *dev_priv = dev->dev_private;
8589         uint32_t reg, tmp;
8590
8591         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8592                 with_spread = true;
8593         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8594                 with_fdi = false;
8595
8596         mutex_lock(&dev_priv->sb_lock);
8597
8598         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8599         tmp &= ~SBI_SSCCTL_DISABLE;
8600         tmp |= SBI_SSCCTL_PATHALT;
8601         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8602
8603         udelay(24);
8604
8605         if (with_spread) {
8606                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8607                 tmp &= ~SBI_SSCCTL_PATHALT;
8608                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8609
8610                 if (with_fdi) {
8611                         lpt_reset_fdi_mphy(dev_priv);
8612                         lpt_program_fdi_mphy(dev_priv);
8613                 }
8614         }
8615
8616         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8617         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8618         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8619         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8620
8621         mutex_unlock(&dev_priv->sb_lock);
8622 }
8623
8624 /* Sequence to disable CLKOUT_DP */
8625 static void lpt_disable_clkout_dp(struct drm_device *dev)
8626 {
8627         struct drm_i915_private *dev_priv = dev->dev_private;
8628         uint32_t reg, tmp;
8629
8630         mutex_lock(&dev_priv->sb_lock);
8631
8632         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8633         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8634         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8635         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8636
8637         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8638         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8639                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8640                         tmp |= SBI_SSCCTL_PATHALT;
8641                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8642                         udelay(32);
8643                 }
8644                 tmp |= SBI_SSCCTL_DISABLE;
8645                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8646         }
8647
8648         mutex_unlock(&dev_priv->sb_lock);
8649 }
8650
8651 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8652
8653 static const uint16_t sscdivintphase[] = {
8654         [BEND_IDX( 50)] = 0x3B23,
8655         [BEND_IDX( 45)] = 0x3B23,
8656         [BEND_IDX( 40)] = 0x3C23,
8657         [BEND_IDX( 35)] = 0x3C23,
8658         [BEND_IDX( 30)] = 0x3D23,
8659         [BEND_IDX( 25)] = 0x3D23,
8660         [BEND_IDX( 20)] = 0x3E23,
8661         [BEND_IDX( 15)] = 0x3E23,
8662         [BEND_IDX( 10)] = 0x3F23,
8663         [BEND_IDX(  5)] = 0x3F23,
8664         [BEND_IDX(  0)] = 0x0025,
8665         [BEND_IDX( -5)] = 0x0025,
8666         [BEND_IDX(-10)] = 0x0125,
8667         [BEND_IDX(-15)] = 0x0125,
8668         [BEND_IDX(-20)] = 0x0225,
8669         [BEND_IDX(-25)] = 0x0225,
8670         [BEND_IDX(-30)] = 0x0325,
8671         [BEND_IDX(-35)] = 0x0325,
8672         [BEND_IDX(-40)] = 0x0425,
8673         [BEND_IDX(-45)] = 0x0425,
8674         [BEND_IDX(-50)] = 0x0525,
8675 };
8676
8677 /*
8678  * Bend CLKOUT_DP
8679  * steps -50 to 50 inclusive, in steps of 5
8680  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8681  * change in clock period = -(steps / 10) * 5.787 ps
8682  */
8683 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8684 {
8685         uint32_t tmp;
8686         int idx = BEND_IDX(steps);
8687
8688         if (WARN_ON(steps % 5 != 0))
8689                 return;
8690
8691         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8692                 return;
8693
8694         mutex_lock(&dev_priv->sb_lock);
8695
8696         if (steps % 10 != 0)
8697                 tmp = 0xAAAAAAAB;
8698         else
8699                 tmp = 0x00000000;
8700         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8701
8702         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8703         tmp &= 0xffff0000;
8704         tmp |= sscdivintphase[idx];
8705         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8706
8707         mutex_unlock(&dev_priv->sb_lock);
8708 }
8709
8710 #undef BEND_IDX
8711
8712 static void lpt_init_pch_refclk(struct drm_device *dev)
8713 {
8714         struct intel_encoder *encoder;
8715         bool has_vga = false;
8716
8717         for_each_intel_encoder(dev, encoder) {
8718                 switch (encoder->type) {
8719                 case INTEL_OUTPUT_ANALOG:
8720                         has_vga = true;
8721                         break;
8722                 default:
8723                         break;
8724                 }
8725         }
8726
8727         if (has_vga) {
8728                 lpt_bend_clkout_dp(to_i915(dev), 0);
8729                 lpt_enable_clkout_dp(dev, true, true);
8730         } else {
8731                 lpt_disable_clkout_dp(dev);
8732         }
8733 }
8734
8735 /*
8736  * Initialize reference clocks when the driver loads
8737  */
8738 void intel_init_pch_refclk(struct drm_device *dev)
8739 {
8740         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8741                 ironlake_init_pch_refclk(dev);
8742         else if (HAS_PCH_LPT(dev))
8743                 lpt_init_pch_refclk(dev);
8744 }
8745
8746 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8747 {
8748         struct drm_device *dev = crtc_state->base.crtc->dev;
8749         struct drm_i915_private *dev_priv = dev->dev_private;
8750         struct drm_atomic_state *state = crtc_state->base.state;
8751         struct drm_connector *connector;
8752         struct drm_connector_state *connector_state;
8753         struct intel_encoder *encoder;
8754         int num_connectors = 0, i;
8755         bool is_lvds = false;
8756
8757         for_each_connector_in_state(state, connector, connector_state, i) {
8758                 if (connector_state->crtc != crtc_state->base.crtc)
8759                         continue;
8760
8761                 encoder = to_intel_encoder(connector_state->best_encoder);
8762
8763                 switch (encoder->type) {
8764                 case INTEL_OUTPUT_LVDS:
8765                         is_lvds = true;
8766                         break;
8767                 default:
8768                         break;
8769                 }
8770                 num_connectors++;
8771         }
8772
8773         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8774                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8775                               dev_priv->vbt.lvds_ssc_freq);
8776                 return dev_priv->vbt.lvds_ssc_freq;
8777         }
8778
8779         return 120000;
8780 }
8781
8782 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8783 {
8784         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8786         int pipe = intel_crtc->pipe;
8787         uint32_t val;
8788
8789         val = 0;
8790
8791         switch (intel_crtc->config->pipe_bpp) {
8792         case 18:
8793                 val |= PIPECONF_6BPC;
8794                 break;
8795         case 24:
8796                 val |= PIPECONF_8BPC;
8797                 break;
8798         case 30:
8799                 val |= PIPECONF_10BPC;
8800                 break;
8801         case 36:
8802                 val |= PIPECONF_12BPC;
8803                 break;
8804         default:
8805                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8806                 BUG();
8807         }
8808
8809         if (intel_crtc->config->dither)
8810                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8811
8812         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8813                 val |= PIPECONF_INTERLACED_ILK;
8814         else
8815                 val |= PIPECONF_PROGRESSIVE;
8816
8817         if (intel_crtc->config->limited_color_range)
8818                 val |= PIPECONF_COLOR_RANGE_SELECT;
8819
8820         I915_WRITE(PIPECONF(pipe), val);
8821         POSTING_READ(PIPECONF(pipe));
8822 }
8823
8824 /*
8825  * Set up the pipe CSC unit.
8826  *
8827  * Currently only full range RGB to limited range RGB conversion
8828  * is supported, but eventually this should handle various
8829  * RGB<->YCbCr scenarios as well.
8830  */
8831 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8832 {
8833         struct drm_device *dev = crtc->dev;
8834         struct drm_i915_private *dev_priv = dev->dev_private;
8835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8836         int pipe = intel_crtc->pipe;
8837         uint16_t coeff = 0x7800; /* 1.0 */
8838
8839         /*
8840          * TODO: Check what kind of values actually come out of the pipe
8841          * with these coeff/postoff values and adjust to get the best
8842          * accuracy. Perhaps we even need to take the bpc value into
8843          * consideration.
8844          */
8845
8846         if (intel_crtc->config->limited_color_range)
8847                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8848
8849         /*
8850          * GY/GU and RY/RU should be the other way around according
8851          * to BSpec, but reality doesn't agree. Just set them up in
8852          * a way that results in the correct picture.
8853          */
8854         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8855         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8856
8857         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8858         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8859
8860         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8861         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8862
8863         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8864         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8865         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8866
8867         if (INTEL_INFO(dev)->gen > 6) {
8868                 uint16_t postoff = 0;
8869
8870                 if (intel_crtc->config->limited_color_range)
8871                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8872
8873                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8874                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8875                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8876
8877                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8878         } else {
8879                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8880
8881                 if (intel_crtc->config->limited_color_range)
8882                         mode |= CSC_BLACK_SCREEN_OFFSET;
8883
8884                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8885         }
8886 }
8887
8888 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8889 {
8890         struct drm_device *dev = crtc->dev;
8891         struct drm_i915_private *dev_priv = dev->dev_private;
8892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8893         enum pipe pipe = intel_crtc->pipe;
8894         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8895         uint32_t val;
8896
8897         val = 0;
8898
8899         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8900                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8901
8902         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8903                 val |= PIPECONF_INTERLACED_ILK;
8904         else
8905                 val |= PIPECONF_PROGRESSIVE;
8906
8907         I915_WRITE(PIPECONF(cpu_transcoder), val);
8908         POSTING_READ(PIPECONF(cpu_transcoder));
8909
8910         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8911         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8912
8913         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8914                 val = 0;
8915
8916                 switch (intel_crtc->config->pipe_bpp) {
8917                 case 18:
8918                         val |= PIPEMISC_DITHER_6_BPC;
8919                         break;
8920                 case 24:
8921                         val |= PIPEMISC_DITHER_8_BPC;
8922                         break;
8923                 case 30:
8924                         val |= PIPEMISC_DITHER_10_BPC;
8925                         break;
8926                 case 36:
8927                         val |= PIPEMISC_DITHER_12_BPC;
8928                         break;
8929                 default:
8930                         /* Case prevented by pipe_config_set_bpp. */
8931                         BUG();
8932                 }
8933
8934                 if (intel_crtc->config->dither)
8935                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8936
8937                 I915_WRITE(PIPEMISC(pipe), val);
8938         }
8939 }
8940
8941 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8942                                     struct intel_crtc_state *crtc_state,
8943                                     intel_clock_t *clock,
8944                                     bool *has_reduced_clock,
8945                                     intel_clock_t *reduced_clock)
8946 {
8947         struct drm_device *dev = crtc->dev;
8948         struct drm_i915_private *dev_priv = dev->dev_private;
8949         int refclk;
8950         const intel_limit_t *limit;
8951         bool ret;
8952
8953         refclk = ironlake_get_refclk(crtc_state);
8954
8955         /*
8956          * Returns a set of divisors for the desired target clock with the given
8957          * refclk, or FALSE.  The returned values represent the clock equation:
8958          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8959          */
8960         limit = intel_limit(crtc_state, refclk);
8961         ret = dev_priv->display.find_dpll(limit, crtc_state,
8962                                           crtc_state->port_clock,
8963                                           refclk, NULL, clock);
8964         if (!ret)
8965                 return false;
8966
8967         return true;
8968 }
8969
8970 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8971 {
8972         /*
8973          * Account for spread spectrum to avoid
8974          * oversubscribing the link. Max center spread
8975          * is 2.5%; use 5% for safety's sake.
8976          */
8977         u32 bps = target_clock * bpp * 21 / 20;
8978         return DIV_ROUND_UP(bps, link_bw * 8);
8979 }
8980
8981 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8982 {
8983         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8984 }
8985
8986 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8987                                       struct intel_crtc_state *crtc_state,
8988                                       u32 *fp,
8989                                       intel_clock_t *reduced_clock, u32 *fp2)
8990 {
8991         struct drm_crtc *crtc = &intel_crtc->base;
8992         struct drm_device *dev = crtc->dev;
8993         struct drm_i915_private *dev_priv = dev->dev_private;
8994         struct drm_atomic_state *state = crtc_state->base.state;
8995         struct drm_connector *connector;
8996         struct drm_connector_state *connector_state;
8997         struct intel_encoder *encoder;
8998         uint32_t dpll;
8999         int factor, num_connectors = 0, i;
9000         bool is_lvds = false, is_sdvo = false;
9001
9002         for_each_connector_in_state(state, connector, connector_state, i) {
9003                 if (connector_state->crtc != crtc_state->base.crtc)
9004                         continue;
9005
9006                 encoder = to_intel_encoder(connector_state->best_encoder);
9007
9008                 switch (encoder->type) {
9009                 case INTEL_OUTPUT_LVDS:
9010                         is_lvds = true;
9011                         break;
9012                 case INTEL_OUTPUT_SDVO:
9013                 case INTEL_OUTPUT_HDMI:
9014                         is_sdvo = true;
9015                         break;
9016                 default:
9017                         break;
9018                 }
9019
9020                 num_connectors++;
9021         }
9022
9023         /* Enable autotuning of the PLL clock (if permissible) */
9024         factor = 21;
9025         if (is_lvds) {
9026                 if ((intel_panel_use_ssc(dev_priv) &&
9027                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9028                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9029                         factor = 25;
9030         } else if (crtc_state->sdvo_tv_clock)
9031                 factor = 20;
9032
9033         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9034                 *fp |= FP_CB_TUNE;
9035
9036         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
9037                 *fp2 |= FP_CB_TUNE;
9038
9039         dpll = 0;
9040
9041         if (is_lvds)
9042                 dpll |= DPLLB_MODE_LVDS;
9043         else
9044                 dpll |= DPLLB_MODE_DAC_SERIAL;
9045
9046         dpll |= (crtc_state->pixel_multiplier - 1)
9047                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9048
9049         if (is_sdvo)
9050                 dpll |= DPLL_SDVO_HIGH_SPEED;
9051         if (crtc_state->has_dp_encoder)
9052                 dpll |= DPLL_SDVO_HIGH_SPEED;
9053
9054         /* compute bitmask from p1 value */
9055         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9056         /* also FPA1 */
9057         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9058
9059         switch (crtc_state->dpll.p2) {
9060         case 5:
9061                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9062                 break;
9063         case 7:
9064                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9065                 break;
9066         case 10:
9067                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9068                 break;
9069         case 14:
9070                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9071                 break;
9072         }
9073
9074         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9075                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9076         else
9077                 dpll |= PLL_REF_INPUT_DREFCLK;
9078
9079         return dpll | DPLL_VCO_ENABLE;
9080 }
9081
9082 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9083                                        struct intel_crtc_state *crtc_state)
9084 {
9085         struct drm_device *dev = crtc->base.dev;
9086         intel_clock_t clock, reduced_clock;
9087         u32 dpll = 0, fp = 0, fp2 = 0;
9088         bool ok, has_reduced_clock = false;
9089         bool is_lvds = false;
9090         struct intel_shared_dpll *pll;
9091
9092         memset(&crtc_state->dpll_hw_state, 0,
9093                sizeof(crtc_state->dpll_hw_state));
9094
9095         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9096
9097         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9098              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9099
9100         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9101                                      &has_reduced_clock, &reduced_clock);
9102         if (!ok && !crtc_state->clock_set) {
9103                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9104                 return -EINVAL;
9105         }
9106         /* Compat-code for transition, will disappear. */
9107         if (!crtc_state->clock_set) {
9108                 crtc_state->dpll.n = clock.n;
9109                 crtc_state->dpll.m1 = clock.m1;
9110                 crtc_state->dpll.m2 = clock.m2;
9111                 crtc_state->dpll.p1 = clock.p1;
9112                 crtc_state->dpll.p2 = clock.p2;
9113         }
9114
9115         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9116         if (crtc_state->has_pch_encoder) {
9117                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9118                 if (has_reduced_clock)
9119                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9120
9121                 dpll = ironlake_compute_dpll(crtc, crtc_state,
9122                                              &fp, &reduced_clock,
9123                                              has_reduced_clock ? &fp2 : NULL);
9124
9125                 crtc_state->dpll_hw_state.dpll = dpll;
9126                 crtc_state->dpll_hw_state.fp0 = fp;
9127                 if (has_reduced_clock)
9128                         crtc_state->dpll_hw_state.fp1 = fp2;
9129                 else
9130                         crtc_state->dpll_hw_state.fp1 = fp;
9131
9132                 pll = intel_get_shared_dpll(crtc, crtc_state);
9133                 if (pll == NULL) {
9134                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9135                                          pipe_name(crtc->pipe));
9136                         return -EINVAL;
9137                 }
9138         }
9139
9140         if (is_lvds && has_reduced_clock)
9141                 crtc->lowfreq_avail = true;
9142         else
9143                 crtc->lowfreq_avail = false;
9144
9145         return 0;
9146 }
9147
9148 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9149                                          struct intel_link_m_n *m_n)
9150 {
9151         struct drm_device *dev = crtc->base.dev;
9152         struct drm_i915_private *dev_priv = dev->dev_private;
9153         enum pipe pipe = crtc->pipe;
9154
9155         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9156         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9157         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9158                 & ~TU_SIZE_MASK;
9159         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9160         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9161                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9162 }
9163
9164 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9165                                          enum transcoder transcoder,
9166                                          struct intel_link_m_n *m_n,
9167                                          struct intel_link_m_n *m2_n2)
9168 {
9169         struct drm_device *dev = crtc->base.dev;
9170         struct drm_i915_private *dev_priv = dev->dev_private;
9171         enum pipe pipe = crtc->pipe;
9172
9173         if (INTEL_INFO(dev)->gen >= 5) {
9174                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9175                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9176                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9177                         & ~TU_SIZE_MASK;
9178                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9179                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9180                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9181                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9182                  * gen < 8) and if DRRS is supported (to make sure the
9183                  * registers are not unnecessarily read).
9184                  */
9185                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9186                         crtc->config->has_drrs) {
9187                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9188                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9189                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9190                                         & ~TU_SIZE_MASK;
9191                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9192                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9193                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9194                 }
9195         } else {
9196                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9197                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9198                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9199                         & ~TU_SIZE_MASK;
9200                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9201                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9202                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9203         }
9204 }
9205
9206 void intel_dp_get_m_n(struct intel_crtc *crtc,
9207                       struct intel_crtc_state *pipe_config)
9208 {
9209         if (pipe_config->has_pch_encoder)
9210                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9211         else
9212                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9213                                              &pipe_config->dp_m_n,
9214                                              &pipe_config->dp_m2_n2);
9215 }
9216
9217 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9218                                         struct intel_crtc_state *pipe_config)
9219 {
9220         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9221                                      &pipe_config->fdi_m_n, NULL);
9222 }
9223
9224 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9225                                     struct intel_crtc_state *pipe_config)
9226 {
9227         struct drm_device *dev = crtc->base.dev;
9228         struct drm_i915_private *dev_priv = dev->dev_private;
9229         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9230         uint32_t ps_ctrl = 0;
9231         int id = -1;
9232         int i;
9233
9234         /* find scaler attached to this pipe */
9235         for (i = 0; i < crtc->num_scalers; i++) {
9236                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9237                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9238                         id = i;
9239                         pipe_config->pch_pfit.enabled = true;
9240                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9241                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9242                         break;
9243                 }
9244         }
9245
9246         scaler_state->scaler_id = id;
9247         if (id >= 0) {
9248                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9249         } else {
9250                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9251         }
9252 }
9253
9254 static void
9255 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9256                                  struct intel_initial_plane_config *plane_config)
9257 {
9258         struct drm_device *dev = crtc->base.dev;
9259         struct drm_i915_private *dev_priv = dev->dev_private;
9260         u32 val, base, offset, stride_mult, tiling;
9261         int pipe = crtc->pipe;
9262         int fourcc, pixel_format;
9263         unsigned int aligned_height;
9264         struct drm_framebuffer *fb;
9265         struct intel_framebuffer *intel_fb;
9266
9267         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9268         if (!intel_fb) {
9269                 DRM_DEBUG_KMS("failed to alloc fb\n");
9270                 return;
9271         }
9272
9273         fb = &intel_fb->base;
9274
9275         val = I915_READ(PLANE_CTL(pipe, 0));
9276         if (!(val & PLANE_CTL_ENABLE))
9277                 goto error;
9278
9279         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9280         fourcc = skl_format_to_fourcc(pixel_format,
9281                                       val & PLANE_CTL_ORDER_RGBX,
9282                                       val & PLANE_CTL_ALPHA_MASK);
9283         fb->pixel_format = fourcc;
9284         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9285
9286         tiling = val & PLANE_CTL_TILED_MASK;
9287         switch (tiling) {
9288         case PLANE_CTL_TILED_LINEAR:
9289                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9290                 break;
9291         case PLANE_CTL_TILED_X:
9292                 plane_config->tiling = I915_TILING_X;
9293                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9294                 break;
9295         case PLANE_CTL_TILED_Y:
9296                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9297                 break;
9298         case PLANE_CTL_TILED_YF:
9299                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9300                 break;
9301         default:
9302                 MISSING_CASE(tiling);
9303                 goto error;
9304         }
9305
9306         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9307         plane_config->base = base;
9308
9309         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9310
9311         val = I915_READ(PLANE_SIZE(pipe, 0));
9312         fb->height = ((val >> 16) & 0xfff) + 1;
9313         fb->width = ((val >> 0) & 0x1fff) + 1;
9314
9315         val = I915_READ(PLANE_STRIDE(pipe, 0));
9316         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9317                                                 fb->pixel_format);
9318         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9319
9320         aligned_height = intel_fb_align_height(dev, fb->height,
9321                                                fb->pixel_format,
9322                                                fb->modifier[0]);
9323
9324         plane_config->size = fb->pitches[0] * aligned_height;
9325
9326         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9327                       pipe_name(pipe), fb->width, fb->height,
9328                       fb->bits_per_pixel, base, fb->pitches[0],
9329                       plane_config->size);
9330
9331         plane_config->fb = intel_fb;
9332         return;
9333
9334 error:
9335         kfree(fb);
9336 }
9337
9338 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9339                                      struct intel_crtc_state *pipe_config)
9340 {
9341         struct drm_device *dev = crtc->base.dev;
9342         struct drm_i915_private *dev_priv = dev->dev_private;
9343         uint32_t tmp;
9344
9345         tmp = I915_READ(PF_CTL(crtc->pipe));
9346
9347         if (tmp & PF_ENABLE) {
9348                 pipe_config->pch_pfit.enabled = true;
9349                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9350                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9351
9352                 /* We currently do not free assignements of panel fitters on
9353                  * ivb/hsw (since we don't use the higher upscaling modes which
9354                  * differentiates them) so just WARN about this case for now. */
9355                 if (IS_GEN7(dev)) {
9356                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9357                                 PF_PIPE_SEL_IVB(crtc->pipe));
9358                 }
9359         }
9360 }
9361
9362 static void
9363 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9364                                   struct intel_initial_plane_config *plane_config)
9365 {
9366         struct drm_device *dev = crtc->base.dev;
9367         struct drm_i915_private *dev_priv = dev->dev_private;
9368         u32 val, base, offset;
9369         int pipe = crtc->pipe;
9370         int fourcc, pixel_format;
9371         unsigned int aligned_height;
9372         struct drm_framebuffer *fb;
9373         struct intel_framebuffer *intel_fb;
9374
9375         val = I915_READ(DSPCNTR(pipe));
9376         if (!(val & DISPLAY_PLANE_ENABLE))
9377                 return;
9378
9379         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9380         if (!intel_fb) {
9381                 DRM_DEBUG_KMS("failed to alloc fb\n");
9382                 return;
9383         }
9384
9385         fb = &intel_fb->base;
9386
9387         if (INTEL_INFO(dev)->gen >= 4) {
9388                 if (val & DISPPLANE_TILED) {
9389                         plane_config->tiling = I915_TILING_X;
9390                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9391                 }
9392         }
9393
9394         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9395         fourcc = i9xx_format_to_fourcc(pixel_format);
9396         fb->pixel_format = fourcc;
9397         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9398
9399         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9400         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9401                 offset = I915_READ(DSPOFFSET(pipe));
9402         } else {
9403                 if (plane_config->tiling)
9404                         offset = I915_READ(DSPTILEOFF(pipe));
9405                 else
9406                         offset = I915_READ(DSPLINOFF(pipe));
9407         }
9408         plane_config->base = base;
9409
9410         val = I915_READ(PIPESRC(pipe));
9411         fb->width = ((val >> 16) & 0xfff) + 1;
9412         fb->height = ((val >> 0) & 0xfff) + 1;
9413
9414         val = I915_READ(DSPSTRIDE(pipe));
9415         fb->pitches[0] = val & 0xffffffc0;
9416
9417         aligned_height = intel_fb_align_height(dev, fb->height,
9418                                                fb->pixel_format,
9419                                                fb->modifier[0]);
9420
9421         plane_config->size = fb->pitches[0] * aligned_height;
9422
9423         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9424                       pipe_name(pipe), fb->width, fb->height,
9425                       fb->bits_per_pixel, base, fb->pitches[0],
9426                       plane_config->size);
9427
9428         plane_config->fb = intel_fb;
9429 }
9430
9431 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9432                                      struct intel_crtc_state *pipe_config)
9433 {
9434         struct drm_device *dev = crtc->base.dev;
9435         struct drm_i915_private *dev_priv = dev->dev_private;
9436         uint32_t tmp;
9437
9438         if (!intel_display_power_is_enabled(dev_priv,
9439                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9440                 return false;
9441
9442         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9443         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9444
9445         tmp = I915_READ(PIPECONF(crtc->pipe));
9446         if (!(tmp & PIPECONF_ENABLE))
9447                 return false;
9448
9449         switch (tmp & PIPECONF_BPC_MASK) {
9450         case PIPECONF_6BPC:
9451                 pipe_config->pipe_bpp = 18;
9452                 break;
9453         case PIPECONF_8BPC:
9454                 pipe_config->pipe_bpp = 24;
9455                 break;
9456         case PIPECONF_10BPC:
9457                 pipe_config->pipe_bpp = 30;
9458                 break;
9459         case PIPECONF_12BPC:
9460                 pipe_config->pipe_bpp = 36;
9461                 break;
9462         default:
9463                 break;
9464         }
9465
9466         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9467                 pipe_config->limited_color_range = true;
9468
9469         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9470                 struct intel_shared_dpll *pll;
9471
9472                 pipe_config->has_pch_encoder = true;
9473
9474                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9475                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9476                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9477
9478                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9479
9480                 if (HAS_PCH_IBX(dev_priv->dev)) {
9481                         pipe_config->shared_dpll =
9482                                 (enum intel_dpll_id) crtc->pipe;
9483                 } else {
9484                         tmp = I915_READ(PCH_DPLL_SEL);
9485                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9486                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9487                         else
9488                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9489                 }
9490
9491                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9492
9493                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9494                                            &pipe_config->dpll_hw_state));
9495
9496                 tmp = pipe_config->dpll_hw_state.dpll;
9497                 pipe_config->pixel_multiplier =
9498                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9499                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9500
9501                 ironlake_pch_clock_get(crtc, pipe_config);
9502         } else {
9503                 pipe_config->pixel_multiplier = 1;
9504         }
9505
9506         intel_get_pipe_timings(crtc, pipe_config);
9507
9508         ironlake_get_pfit_config(crtc, pipe_config);
9509
9510         return true;
9511 }
9512
9513 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9514 {
9515         struct drm_device *dev = dev_priv->dev;
9516         struct intel_crtc *crtc;
9517
9518         for_each_intel_crtc(dev, crtc)
9519                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9520                      pipe_name(crtc->pipe));
9521
9522         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9523         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9524         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9525         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9526         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9527         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9528              "CPU PWM1 enabled\n");
9529         if (IS_HASWELL(dev))
9530                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9531                      "CPU PWM2 enabled\n");
9532         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9533              "PCH PWM1 enabled\n");
9534         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9535              "Utility pin enabled\n");
9536         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9537
9538         /*
9539          * In theory we can still leave IRQs enabled, as long as only the HPD
9540          * interrupts remain enabled. We used to check for that, but since it's
9541          * gen-specific and since we only disable LCPLL after we fully disable
9542          * the interrupts, the check below should be enough.
9543          */
9544         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9545 }
9546
9547 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9548 {
9549         struct drm_device *dev = dev_priv->dev;
9550
9551         if (IS_HASWELL(dev))
9552                 return I915_READ(D_COMP_HSW);
9553         else
9554                 return I915_READ(D_COMP_BDW);
9555 }
9556
9557 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9558 {
9559         struct drm_device *dev = dev_priv->dev;
9560
9561         if (IS_HASWELL(dev)) {
9562                 mutex_lock(&dev_priv->rps.hw_lock);
9563                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9564                                             val))
9565                         DRM_ERROR("Failed to write to D_COMP\n");
9566                 mutex_unlock(&dev_priv->rps.hw_lock);
9567         } else {
9568                 I915_WRITE(D_COMP_BDW, val);
9569                 POSTING_READ(D_COMP_BDW);
9570         }
9571 }
9572
9573 /*
9574  * This function implements pieces of two sequences from BSpec:
9575  * - Sequence for display software to disable LCPLL
9576  * - Sequence for display software to allow package C8+
9577  * The steps implemented here are just the steps that actually touch the LCPLL
9578  * register. Callers should take care of disabling all the display engine
9579  * functions, doing the mode unset, fixing interrupts, etc.
9580  */
9581 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9582                               bool switch_to_fclk, bool allow_power_down)
9583 {
9584         uint32_t val;
9585
9586         assert_can_disable_lcpll(dev_priv);
9587
9588         val = I915_READ(LCPLL_CTL);
9589
9590         if (switch_to_fclk) {
9591                 val |= LCPLL_CD_SOURCE_FCLK;
9592                 I915_WRITE(LCPLL_CTL, val);
9593
9594                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9595                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9596                         DRM_ERROR("Switching to FCLK failed\n");
9597
9598                 val = I915_READ(LCPLL_CTL);
9599         }
9600
9601         val |= LCPLL_PLL_DISABLE;
9602         I915_WRITE(LCPLL_CTL, val);
9603         POSTING_READ(LCPLL_CTL);
9604
9605         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9606                 DRM_ERROR("LCPLL still locked\n");
9607
9608         val = hsw_read_dcomp(dev_priv);
9609         val |= D_COMP_COMP_DISABLE;
9610         hsw_write_dcomp(dev_priv, val);
9611         ndelay(100);
9612
9613         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9614                      1))
9615                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9616
9617         if (allow_power_down) {
9618                 val = I915_READ(LCPLL_CTL);
9619                 val |= LCPLL_POWER_DOWN_ALLOW;
9620                 I915_WRITE(LCPLL_CTL, val);
9621                 POSTING_READ(LCPLL_CTL);
9622         }
9623 }
9624
9625 /*
9626  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9627  * source.
9628  */
9629 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9630 {
9631         uint32_t val;
9632
9633         val = I915_READ(LCPLL_CTL);
9634
9635         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9636                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9637                 return;
9638
9639         /*
9640          * Make sure we're not on PC8 state before disabling PC8, otherwise
9641          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9642          */
9643         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9644
9645         if (val & LCPLL_POWER_DOWN_ALLOW) {
9646                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9647                 I915_WRITE(LCPLL_CTL, val);
9648                 POSTING_READ(LCPLL_CTL);
9649         }
9650
9651         val = hsw_read_dcomp(dev_priv);
9652         val |= D_COMP_COMP_FORCE;
9653         val &= ~D_COMP_COMP_DISABLE;
9654         hsw_write_dcomp(dev_priv, val);
9655
9656         val = I915_READ(LCPLL_CTL);
9657         val &= ~LCPLL_PLL_DISABLE;
9658         I915_WRITE(LCPLL_CTL, val);
9659
9660         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9661                 DRM_ERROR("LCPLL not locked yet\n");
9662
9663         if (val & LCPLL_CD_SOURCE_FCLK) {
9664                 val = I915_READ(LCPLL_CTL);
9665                 val &= ~LCPLL_CD_SOURCE_FCLK;
9666                 I915_WRITE(LCPLL_CTL, val);
9667
9668                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9669                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9670                         DRM_ERROR("Switching back to LCPLL failed\n");
9671         }
9672
9673         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9674         intel_update_cdclk(dev_priv->dev);
9675 }
9676
9677 /*
9678  * Package states C8 and deeper are really deep PC states that can only be
9679  * reached when all the devices on the system allow it, so even if the graphics
9680  * device allows PC8+, it doesn't mean the system will actually get to these
9681  * states. Our driver only allows PC8+ when going into runtime PM.
9682  *
9683  * The requirements for PC8+ are that all the outputs are disabled, the power
9684  * well is disabled and most interrupts are disabled, and these are also
9685  * requirements for runtime PM. When these conditions are met, we manually do
9686  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9687  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9688  * hang the machine.
9689  *
9690  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9691  * the state of some registers, so when we come back from PC8+ we need to
9692  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9693  * need to take care of the registers kept by RC6. Notice that this happens even
9694  * if we don't put the device in PCI D3 state (which is what currently happens
9695  * because of the runtime PM support).
9696  *
9697  * For more, read "Display Sequences for Package C8" on the hardware
9698  * documentation.
9699  */
9700 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9701 {
9702         struct drm_device *dev = dev_priv->dev;
9703         uint32_t val;
9704
9705         DRM_DEBUG_KMS("Enabling package C8+\n");
9706
9707         if (HAS_PCH_LPT_LP(dev)) {
9708                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9709                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9710                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9711         }
9712
9713         lpt_disable_clkout_dp(dev);
9714         hsw_disable_lcpll(dev_priv, true, true);
9715 }
9716
9717 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9718 {
9719         struct drm_device *dev = dev_priv->dev;
9720         uint32_t val;
9721
9722         DRM_DEBUG_KMS("Disabling package C8+\n");
9723
9724         hsw_restore_lcpll(dev_priv);
9725         lpt_init_pch_refclk(dev);
9726
9727         if (HAS_PCH_LPT_LP(dev)) {
9728                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9729                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9730                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9731         }
9732
9733         intel_prepare_ddi(dev);
9734 }
9735
9736 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9737 {
9738         struct drm_device *dev = old_state->dev;
9739         struct intel_atomic_state *old_intel_state =
9740                 to_intel_atomic_state(old_state);
9741         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9742
9743         broxton_set_cdclk(dev, req_cdclk);
9744 }
9745
9746 /* compute the max rate for new configuration */
9747 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9748 {
9749         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9750         struct drm_i915_private *dev_priv = state->dev->dev_private;
9751         struct drm_crtc *crtc;
9752         struct drm_crtc_state *cstate;
9753         struct intel_crtc_state *crtc_state;
9754         unsigned max_pixel_rate = 0, i;
9755         enum pipe pipe;
9756
9757         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9758                sizeof(intel_state->min_pixclk));
9759
9760         for_each_crtc_in_state(state, crtc, cstate, i) {
9761                 int pixel_rate;
9762
9763                 crtc_state = to_intel_crtc_state(cstate);
9764                 if (!crtc_state->base.enable) {
9765                         intel_state->min_pixclk[i] = 0;
9766                         continue;
9767                 }
9768
9769                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9770
9771                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9772                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9773                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9774
9775                 intel_state->min_pixclk[i] = pixel_rate;
9776         }
9777
9778         if (!intel_state->active_crtcs)
9779                 return 0;
9780
9781         for_each_pipe(dev_priv, pipe)
9782                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9783
9784         return max_pixel_rate;
9785 }
9786
9787 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9788 {
9789         struct drm_i915_private *dev_priv = dev->dev_private;
9790         uint32_t val, data;
9791         int ret;
9792
9793         if (WARN((I915_READ(LCPLL_CTL) &
9794                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9795                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9796                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9797                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9798                  "trying to change cdclk frequency with cdclk not enabled\n"))
9799                 return;
9800
9801         mutex_lock(&dev_priv->rps.hw_lock);
9802         ret = sandybridge_pcode_write(dev_priv,
9803                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9804         mutex_unlock(&dev_priv->rps.hw_lock);
9805         if (ret) {
9806                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9807                 return;
9808         }
9809
9810         val = I915_READ(LCPLL_CTL);
9811         val |= LCPLL_CD_SOURCE_FCLK;
9812         I915_WRITE(LCPLL_CTL, val);
9813
9814         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9815                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9816                 DRM_ERROR("Switching to FCLK failed\n");
9817
9818         val = I915_READ(LCPLL_CTL);
9819         val &= ~LCPLL_CLK_FREQ_MASK;
9820
9821         switch (cdclk) {
9822         case 450000:
9823                 val |= LCPLL_CLK_FREQ_450;
9824                 data = 0;
9825                 break;
9826         case 540000:
9827                 val |= LCPLL_CLK_FREQ_54O_BDW;
9828                 data = 1;
9829                 break;
9830         case 337500:
9831                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9832                 data = 2;
9833                 break;
9834         case 675000:
9835                 val |= LCPLL_CLK_FREQ_675_BDW;
9836                 data = 3;
9837                 break;
9838         default:
9839                 WARN(1, "invalid cdclk frequency\n");
9840                 return;
9841         }
9842
9843         I915_WRITE(LCPLL_CTL, val);
9844
9845         val = I915_READ(LCPLL_CTL);
9846         val &= ~LCPLL_CD_SOURCE_FCLK;
9847         I915_WRITE(LCPLL_CTL, val);
9848
9849         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9850                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9851                 DRM_ERROR("Switching back to LCPLL failed\n");
9852
9853         mutex_lock(&dev_priv->rps.hw_lock);
9854         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9855         mutex_unlock(&dev_priv->rps.hw_lock);
9856
9857         intel_update_cdclk(dev);
9858
9859         WARN(cdclk != dev_priv->cdclk_freq,
9860              "cdclk requested %d kHz but got %d kHz\n",
9861              cdclk, dev_priv->cdclk_freq);
9862 }
9863
9864 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9865 {
9866         struct drm_i915_private *dev_priv = to_i915(state->dev);
9867         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9868         int max_pixclk = ilk_max_pixel_rate(state);
9869         int cdclk;
9870
9871         /*
9872          * FIXME should also account for plane ratio
9873          * once 64bpp pixel formats are supported.
9874          */
9875         if (max_pixclk > 540000)
9876                 cdclk = 675000;
9877         else if (max_pixclk > 450000)
9878                 cdclk = 540000;
9879         else if (max_pixclk > 337500)
9880                 cdclk = 450000;
9881         else
9882                 cdclk = 337500;
9883
9884         if (cdclk > dev_priv->max_cdclk_freq) {
9885                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9886                               cdclk, dev_priv->max_cdclk_freq);
9887                 return -EINVAL;
9888         }
9889
9890         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9891         if (!intel_state->active_crtcs)
9892                 intel_state->dev_cdclk = 337500;
9893
9894         return 0;
9895 }
9896
9897 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9898 {
9899         struct drm_device *dev = old_state->dev;
9900         struct intel_atomic_state *old_intel_state =
9901                 to_intel_atomic_state(old_state);
9902         unsigned req_cdclk = old_intel_state->dev_cdclk;
9903
9904         broadwell_set_cdclk(dev, req_cdclk);
9905 }
9906
9907 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9908                                       struct intel_crtc_state *crtc_state)
9909 {
9910         if (!intel_ddi_pll_select(crtc, crtc_state))
9911                 return -EINVAL;
9912
9913         crtc->lowfreq_avail = false;
9914
9915         return 0;
9916 }
9917
9918 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9919                                 enum port port,
9920                                 struct intel_crtc_state *pipe_config)
9921 {
9922         switch (port) {
9923         case PORT_A:
9924                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9925                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9926                 break;
9927         case PORT_B:
9928                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9929                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9930                 break;
9931         case PORT_C:
9932                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9933                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9934                 break;
9935         default:
9936                 DRM_ERROR("Incorrect port type\n");
9937         }
9938 }
9939
9940 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9941                                 enum port port,
9942                                 struct intel_crtc_state *pipe_config)
9943 {
9944         u32 temp, dpll_ctl1;
9945
9946         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9947         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9948
9949         switch (pipe_config->ddi_pll_sel) {
9950         case SKL_DPLL0:
9951                 /*
9952                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9953                  * of the shared DPLL framework and thus needs to be read out
9954                  * separately
9955                  */
9956                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9957                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9958                 break;
9959         case SKL_DPLL1:
9960                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9961                 break;
9962         case SKL_DPLL2:
9963                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9964                 break;
9965         case SKL_DPLL3:
9966                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9967                 break;
9968         }
9969 }
9970
9971 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9972                                 enum port port,
9973                                 struct intel_crtc_state *pipe_config)
9974 {
9975         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9976
9977         switch (pipe_config->ddi_pll_sel) {
9978         case PORT_CLK_SEL_WRPLL1:
9979                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9980                 break;
9981         case PORT_CLK_SEL_WRPLL2:
9982                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9983                 break;
9984         case PORT_CLK_SEL_SPLL:
9985                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9986                 break;
9987         }
9988 }
9989
9990 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9991                                        struct intel_crtc_state *pipe_config)
9992 {
9993         struct drm_device *dev = crtc->base.dev;
9994         struct drm_i915_private *dev_priv = dev->dev_private;
9995         struct intel_shared_dpll *pll;
9996         enum port port;
9997         uint32_t tmp;
9998
9999         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10000
10001         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10002
10003         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10004                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10005         else if (IS_BROXTON(dev))
10006                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10007         else
10008                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10009
10010         if (pipe_config->shared_dpll >= 0) {
10011                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
10012
10013                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
10014                                            &pipe_config->dpll_hw_state));
10015         }
10016
10017         /*
10018          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10019          * DDI E. So just check whether this pipe is wired to DDI E and whether
10020          * the PCH transcoder is on.
10021          */
10022         if (INTEL_INFO(dev)->gen < 9 &&
10023             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10024                 pipe_config->has_pch_encoder = true;
10025
10026                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10027                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10028                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10029
10030                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10031         }
10032 }
10033
10034 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10035                                     struct intel_crtc_state *pipe_config)
10036 {
10037         struct drm_device *dev = crtc->base.dev;
10038         struct drm_i915_private *dev_priv = dev->dev_private;
10039         enum intel_display_power_domain pfit_domain;
10040         uint32_t tmp;
10041
10042         if (!intel_display_power_is_enabled(dev_priv,
10043                                          POWER_DOMAIN_PIPE(crtc->pipe)))
10044                 return false;
10045
10046         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10047         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10048
10049         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10050         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10051                 enum pipe trans_edp_pipe;
10052                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10053                 default:
10054                         WARN(1, "unknown pipe linked to edp transcoder\n");
10055                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10056                 case TRANS_DDI_EDP_INPUT_A_ON:
10057                         trans_edp_pipe = PIPE_A;
10058                         break;
10059                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10060                         trans_edp_pipe = PIPE_B;
10061                         break;
10062                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10063                         trans_edp_pipe = PIPE_C;
10064                         break;
10065                 }
10066
10067                 if (trans_edp_pipe == crtc->pipe)
10068                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10069         }
10070
10071         if (!intel_display_power_is_enabled(dev_priv,
10072                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10073                 return false;
10074
10075         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10076         if (!(tmp & PIPECONF_ENABLE))
10077                 return false;
10078
10079         haswell_get_ddi_port_state(crtc, pipe_config);
10080
10081         intel_get_pipe_timings(crtc, pipe_config);
10082
10083         if (INTEL_INFO(dev)->gen >= 9) {
10084                 skl_init_scalers(dev, crtc, pipe_config);
10085         }
10086
10087         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10088
10089         if (INTEL_INFO(dev)->gen >= 9) {
10090                 pipe_config->scaler_state.scaler_id = -1;
10091                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10092         }
10093
10094         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10095                 if (INTEL_INFO(dev)->gen >= 9)
10096                         skylake_get_pfit_config(crtc, pipe_config);
10097                 else
10098                         ironlake_get_pfit_config(crtc, pipe_config);
10099         }
10100
10101         if (IS_HASWELL(dev))
10102                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10103                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10104
10105         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10106                 pipe_config->pixel_multiplier =
10107                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10108         } else {
10109                 pipe_config->pixel_multiplier = 1;
10110         }
10111
10112         return true;
10113 }
10114
10115 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10116                                const struct intel_plane_state *plane_state)
10117 {
10118         struct drm_device *dev = crtc->dev;
10119         struct drm_i915_private *dev_priv = dev->dev_private;
10120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10121         uint32_t cntl = 0, size = 0;
10122
10123         if (plane_state && plane_state->visible) {
10124                 unsigned int width = plane_state->base.crtc_w;
10125                 unsigned int height = plane_state->base.crtc_h;
10126                 unsigned int stride = roundup_pow_of_two(width) * 4;
10127
10128                 switch (stride) {
10129                 default:
10130                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10131                                   width, stride);
10132                         stride = 256;
10133                         /* fallthrough */
10134                 case 256:
10135                 case 512:
10136                 case 1024:
10137                 case 2048:
10138                         break;
10139                 }
10140
10141                 cntl |= CURSOR_ENABLE |
10142                         CURSOR_GAMMA_ENABLE |
10143                         CURSOR_FORMAT_ARGB |
10144                         CURSOR_STRIDE(stride);
10145
10146                 size = (height << 12) | width;
10147         }
10148
10149         if (intel_crtc->cursor_cntl != 0 &&
10150             (intel_crtc->cursor_base != base ||
10151              intel_crtc->cursor_size != size ||
10152              intel_crtc->cursor_cntl != cntl)) {
10153                 /* On these chipsets we can only modify the base/size/stride
10154                  * whilst the cursor is disabled.
10155                  */
10156                 I915_WRITE(CURCNTR(PIPE_A), 0);
10157                 POSTING_READ(CURCNTR(PIPE_A));
10158                 intel_crtc->cursor_cntl = 0;
10159         }
10160
10161         if (intel_crtc->cursor_base != base) {
10162                 I915_WRITE(CURBASE(PIPE_A), base);
10163                 intel_crtc->cursor_base = base;
10164         }
10165
10166         if (intel_crtc->cursor_size != size) {
10167                 I915_WRITE(CURSIZE, size);
10168                 intel_crtc->cursor_size = size;
10169         }
10170
10171         if (intel_crtc->cursor_cntl != cntl) {
10172                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10173                 POSTING_READ(CURCNTR(PIPE_A));
10174                 intel_crtc->cursor_cntl = cntl;
10175         }
10176 }
10177
10178 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10179                                const struct intel_plane_state *plane_state)
10180 {
10181         struct drm_device *dev = crtc->dev;
10182         struct drm_i915_private *dev_priv = dev->dev_private;
10183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10184         int pipe = intel_crtc->pipe;
10185         uint32_t cntl = 0;
10186
10187         if (plane_state && plane_state->visible) {
10188                 cntl = MCURSOR_GAMMA_ENABLE;
10189                 switch (plane_state->base.crtc_w) {
10190                         case 64:
10191                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10192                                 break;
10193                         case 128:
10194                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10195                                 break;
10196                         case 256:
10197                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10198                                 break;
10199                         default:
10200                                 MISSING_CASE(plane_state->base.crtc_w);
10201                                 return;
10202                 }
10203                 cntl |= pipe << 28; /* Connect to correct pipe */
10204
10205                 if (HAS_DDI(dev))
10206                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10207
10208                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10209                         cntl |= CURSOR_ROTATE_180;
10210         }
10211
10212         if (intel_crtc->cursor_cntl != cntl) {
10213                 I915_WRITE(CURCNTR(pipe), cntl);
10214                 POSTING_READ(CURCNTR(pipe));
10215                 intel_crtc->cursor_cntl = cntl;
10216         }
10217
10218         /* and commit changes on next vblank */
10219         I915_WRITE(CURBASE(pipe), base);
10220         POSTING_READ(CURBASE(pipe));
10221
10222         intel_crtc->cursor_base = base;
10223 }
10224
10225 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10226 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10227                                      const struct intel_plane_state *plane_state)
10228 {
10229         struct drm_device *dev = crtc->dev;
10230         struct drm_i915_private *dev_priv = dev->dev_private;
10231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10232         int pipe = intel_crtc->pipe;
10233         u32 base = intel_crtc->cursor_addr;
10234         u32 pos = 0;
10235
10236         if (plane_state) {
10237                 int x = plane_state->base.crtc_x;
10238                 int y = plane_state->base.crtc_y;
10239
10240                 if (x < 0) {
10241                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10242                         x = -x;
10243                 }
10244                 pos |= x << CURSOR_X_SHIFT;
10245
10246                 if (y < 0) {
10247                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10248                         y = -y;
10249                 }
10250                 pos |= y << CURSOR_Y_SHIFT;
10251
10252                 /* ILK+ do this automagically */
10253                 if (HAS_GMCH_DISPLAY(dev) &&
10254                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10255                         base += (plane_state->base.crtc_h *
10256                                  plane_state->base.crtc_w - 1) * 4;
10257                 }
10258         }
10259
10260         I915_WRITE(CURPOS(pipe), pos);
10261
10262         if (IS_845G(dev) || IS_I865G(dev))
10263                 i845_update_cursor(crtc, base, plane_state);
10264         else
10265                 i9xx_update_cursor(crtc, base, plane_state);
10266 }
10267
10268 static bool cursor_size_ok(struct drm_device *dev,
10269                            uint32_t width, uint32_t height)
10270 {
10271         if (width == 0 || height == 0)
10272                 return false;
10273
10274         /*
10275          * 845g/865g are special in that they are only limited by
10276          * the width of their cursors, the height is arbitrary up to
10277          * the precision of the register. Everything else requires
10278          * square cursors, limited to a few power-of-two sizes.
10279          */
10280         if (IS_845G(dev) || IS_I865G(dev)) {
10281                 if ((width & 63) != 0)
10282                         return false;
10283
10284                 if (width > (IS_845G(dev) ? 64 : 512))
10285                         return false;
10286
10287                 if (height > 1023)
10288                         return false;
10289         } else {
10290                 switch (width | height) {
10291                 case 256:
10292                 case 128:
10293                         if (IS_GEN2(dev))
10294                                 return false;
10295                 case 64:
10296                         break;
10297                 default:
10298                         return false;
10299                 }
10300         }
10301
10302         return true;
10303 }
10304
10305 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10306                                  u16 *blue, uint32_t start, uint32_t size)
10307 {
10308         int end = (start + size > 256) ? 256 : start + size, i;
10309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10310
10311         for (i = start; i < end; i++) {
10312                 intel_crtc->lut_r[i] = red[i] >> 8;
10313                 intel_crtc->lut_g[i] = green[i] >> 8;
10314                 intel_crtc->lut_b[i] = blue[i] >> 8;
10315         }
10316
10317         intel_crtc_load_lut(crtc);
10318 }
10319
10320 /* VESA 640x480x72Hz mode to set on the pipe */
10321 static struct drm_display_mode load_detect_mode = {
10322         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10323                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10324 };
10325
10326 struct drm_framebuffer *
10327 __intel_framebuffer_create(struct drm_device *dev,
10328                            struct drm_mode_fb_cmd2 *mode_cmd,
10329                            struct drm_i915_gem_object *obj)
10330 {
10331         struct intel_framebuffer *intel_fb;
10332         int ret;
10333
10334         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10335         if (!intel_fb)
10336                 return ERR_PTR(-ENOMEM);
10337
10338         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10339         if (ret)
10340                 goto err;
10341
10342         return &intel_fb->base;
10343
10344 err:
10345         kfree(intel_fb);
10346         return ERR_PTR(ret);
10347 }
10348
10349 static struct drm_framebuffer *
10350 intel_framebuffer_create(struct drm_device *dev,
10351                          struct drm_mode_fb_cmd2 *mode_cmd,
10352                          struct drm_i915_gem_object *obj)
10353 {
10354         struct drm_framebuffer *fb;
10355         int ret;
10356
10357         ret = i915_mutex_lock_interruptible(dev);
10358         if (ret)
10359                 return ERR_PTR(ret);
10360         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10361         mutex_unlock(&dev->struct_mutex);
10362
10363         return fb;
10364 }
10365
10366 static u32
10367 intel_framebuffer_pitch_for_width(int width, int bpp)
10368 {
10369         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10370         return ALIGN(pitch, 64);
10371 }
10372
10373 static u32
10374 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10375 {
10376         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10377         return PAGE_ALIGN(pitch * mode->vdisplay);
10378 }
10379
10380 static struct drm_framebuffer *
10381 intel_framebuffer_create_for_mode(struct drm_device *dev,
10382                                   struct drm_display_mode *mode,
10383                                   int depth, int bpp)
10384 {
10385         struct drm_framebuffer *fb;
10386         struct drm_i915_gem_object *obj;
10387         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10388
10389         obj = i915_gem_alloc_object(dev,
10390                                     intel_framebuffer_size_for_mode(mode, bpp));
10391         if (obj == NULL)
10392                 return ERR_PTR(-ENOMEM);
10393
10394         mode_cmd.width = mode->hdisplay;
10395         mode_cmd.height = mode->vdisplay;
10396         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10397                                                                 bpp);
10398         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10399
10400         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10401         if (IS_ERR(fb))
10402                 drm_gem_object_unreference_unlocked(&obj->base);
10403
10404         return fb;
10405 }
10406
10407 static struct drm_framebuffer *
10408 mode_fits_in_fbdev(struct drm_device *dev,
10409                    struct drm_display_mode *mode)
10410 {
10411 #ifdef CONFIG_DRM_FBDEV_EMULATION
10412         struct drm_i915_private *dev_priv = dev->dev_private;
10413         struct drm_i915_gem_object *obj;
10414         struct drm_framebuffer *fb;
10415
10416         if (!dev_priv->fbdev)
10417                 return NULL;
10418
10419         if (!dev_priv->fbdev->fb)
10420                 return NULL;
10421
10422         obj = dev_priv->fbdev->fb->obj;
10423         BUG_ON(!obj);
10424
10425         fb = &dev_priv->fbdev->fb->base;
10426         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10427                                                                fb->bits_per_pixel))
10428                 return NULL;
10429
10430         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10431                 return NULL;
10432
10433         return fb;
10434 #else
10435         return NULL;
10436 #endif
10437 }
10438
10439 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10440                                            struct drm_crtc *crtc,
10441                                            struct drm_display_mode *mode,
10442                                            struct drm_framebuffer *fb,
10443                                            int x, int y)
10444 {
10445         struct drm_plane_state *plane_state;
10446         int hdisplay, vdisplay;
10447         int ret;
10448
10449         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10450         if (IS_ERR(plane_state))
10451                 return PTR_ERR(plane_state);
10452
10453         if (mode)
10454                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10455         else
10456                 hdisplay = vdisplay = 0;
10457
10458         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10459         if (ret)
10460                 return ret;
10461         drm_atomic_set_fb_for_plane(plane_state, fb);
10462         plane_state->crtc_x = 0;
10463         plane_state->crtc_y = 0;
10464         plane_state->crtc_w = hdisplay;
10465         plane_state->crtc_h = vdisplay;
10466         plane_state->src_x = x << 16;
10467         plane_state->src_y = y << 16;
10468         plane_state->src_w = hdisplay << 16;
10469         plane_state->src_h = vdisplay << 16;
10470
10471         return 0;
10472 }
10473
10474 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10475                                 struct drm_display_mode *mode,
10476                                 struct intel_load_detect_pipe *old,
10477                                 struct drm_modeset_acquire_ctx *ctx)
10478 {
10479         struct intel_crtc *intel_crtc;
10480         struct intel_encoder *intel_encoder =
10481                 intel_attached_encoder(connector);
10482         struct drm_crtc *possible_crtc;
10483         struct drm_encoder *encoder = &intel_encoder->base;
10484         struct drm_crtc *crtc = NULL;
10485         struct drm_device *dev = encoder->dev;
10486         struct drm_framebuffer *fb;
10487         struct drm_mode_config *config = &dev->mode_config;
10488         struct drm_atomic_state *state = NULL;
10489         struct drm_connector_state *connector_state;
10490         struct intel_crtc_state *crtc_state;
10491         int ret, i = -1;
10492
10493         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10494                       connector->base.id, connector->name,
10495                       encoder->base.id, encoder->name);
10496
10497 retry:
10498         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10499         if (ret)
10500                 goto fail;
10501
10502         /*
10503          * Algorithm gets a little messy:
10504          *
10505          *   - if the connector already has an assigned crtc, use it (but make
10506          *     sure it's on first)
10507          *
10508          *   - try to find the first unused crtc that can drive this connector,
10509          *     and use that if we find one
10510          */
10511
10512         /* See if we already have a CRTC for this connector */
10513         if (encoder->crtc) {
10514                 crtc = encoder->crtc;
10515
10516                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10517                 if (ret)
10518                         goto fail;
10519                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10520                 if (ret)
10521                         goto fail;
10522
10523                 old->dpms_mode = connector->dpms;
10524                 old->load_detect_temp = false;
10525
10526                 /* Make sure the crtc and connector are running */
10527                 if (connector->dpms != DRM_MODE_DPMS_ON)
10528                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10529
10530                 return true;
10531         }
10532
10533         /* Find an unused one (if possible) */
10534         for_each_crtc(dev, possible_crtc) {
10535                 i++;
10536                 if (!(encoder->possible_crtcs & (1 << i)))
10537                         continue;
10538                 if (possible_crtc->state->enable)
10539                         continue;
10540
10541                 crtc = possible_crtc;
10542                 break;
10543         }
10544
10545         /*
10546          * If we didn't find an unused CRTC, don't use any.
10547          */
10548         if (!crtc) {
10549                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10550                 goto fail;
10551         }
10552
10553         ret = drm_modeset_lock(&crtc->mutex, ctx);
10554         if (ret)
10555                 goto fail;
10556         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10557         if (ret)
10558                 goto fail;
10559
10560         intel_crtc = to_intel_crtc(crtc);
10561         old->dpms_mode = connector->dpms;
10562         old->load_detect_temp = true;
10563         old->release_fb = NULL;
10564
10565         state = drm_atomic_state_alloc(dev);
10566         if (!state)
10567                 return false;
10568
10569         state->acquire_ctx = ctx;
10570
10571         connector_state = drm_atomic_get_connector_state(state, connector);
10572         if (IS_ERR(connector_state)) {
10573                 ret = PTR_ERR(connector_state);
10574                 goto fail;
10575         }
10576
10577         connector_state->crtc = crtc;
10578         connector_state->best_encoder = &intel_encoder->base;
10579
10580         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10581         if (IS_ERR(crtc_state)) {
10582                 ret = PTR_ERR(crtc_state);
10583                 goto fail;
10584         }
10585
10586         crtc_state->base.active = crtc_state->base.enable = true;
10587
10588         if (!mode)
10589                 mode = &load_detect_mode;
10590
10591         /* We need a framebuffer large enough to accommodate all accesses
10592          * that the plane may generate whilst we perform load detection.
10593          * We can not rely on the fbcon either being present (we get called
10594          * during its initialisation to detect all boot displays, or it may
10595          * not even exist) or that it is large enough to satisfy the
10596          * requested mode.
10597          */
10598         fb = mode_fits_in_fbdev(dev, mode);
10599         if (fb == NULL) {
10600                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10601                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10602                 old->release_fb = fb;
10603         } else
10604                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10605         if (IS_ERR(fb)) {
10606                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10607                 goto fail;
10608         }
10609
10610         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10611         if (ret)
10612                 goto fail;
10613
10614         drm_mode_copy(&crtc_state->base.mode, mode);
10615
10616         if (drm_atomic_commit(state)) {
10617                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10618                 if (old->release_fb)
10619                         old->release_fb->funcs->destroy(old->release_fb);
10620                 goto fail;
10621         }
10622         crtc->primary->crtc = crtc;
10623
10624         /* let the connector get through one full cycle before testing */
10625         intel_wait_for_vblank(dev, intel_crtc->pipe);
10626         return true;
10627
10628 fail:
10629         drm_atomic_state_free(state);
10630         state = NULL;
10631
10632         if (ret == -EDEADLK) {
10633                 drm_modeset_backoff(ctx);
10634                 goto retry;
10635         }
10636
10637         return false;
10638 }
10639
10640 void intel_release_load_detect_pipe(struct drm_connector *connector,
10641                                     struct intel_load_detect_pipe *old,
10642                                     struct drm_modeset_acquire_ctx *ctx)
10643 {
10644         struct drm_device *dev = connector->dev;
10645         struct intel_encoder *intel_encoder =
10646                 intel_attached_encoder(connector);
10647         struct drm_encoder *encoder = &intel_encoder->base;
10648         struct drm_crtc *crtc = encoder->crtc;
10649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10650         struct drm_atomic_state *state;
10651         struct drm_connector_state *connector_state;
10652         struct intel_crtc_state *crtc_state;
10653         int ret;
10654
10655         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10656                       connector->base.id, connector->name,
10657                       encoder->base.id, encoder->name);
10658
10659         if (old->load_detect_temp) {
10660                 state = drm_atomic_state_alloc(dev);
10661                 if (!state)
10662                         goto fail;
10663
10664                 state->acquire_ctx = ctx;
10665
10666                 connector_state = drm_atomic_get_connector_state(state, connector);
10667                 if (IS_ERR(connector_state))
10668                         goto fail;
10669
10670                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10671                 if (IS_ERR(crtc_state))
10672                         goto fail;
10673
10674                 connector_state->best_encoder = NULL;
10675                 connector_state->crtc = NULL;
10676
10677                 crtc_state->base.enable = crtc_state->base.active = false;
10678
10679                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10680                                                       0, 0);
10681                 if (ret)
10682                         goto fail;
10683
10684                 ret = drm_atomic_commit(state);
10685                 if (ret)
10686                         goto fail;
10687
10688                 if (old->release_fb) {
10689                         drm_framebuffer_unregister_private(old->release_fb);
10690                         drm_framebuffer_unreference(old->release_fb);
10691                 }
10692
10693                 return;
10694         }
10695
10696         /* Switch crtc and encoder back off if necessary */
10697         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10698                 connector->funcs->dpms(connector, old->dpms_mode);
10699
10700         return;
10701 fail:
10702         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10703         drm_atomic_state_free(state);
10704 }
10705
10706 static int i9xx_pll_refclk(struct drm_device *dev,
10707                            const struct intel_crtc_state *pipe_config)
10708 {
10709         struct drm_i915_private *dev_priv = dev->dev_private;
10710         u32 dpll = pipe_config->dpll_hw_state.dpll;
10711
10712         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10713                 return dev_priv->vbt.lvds_ssc_freq;
10714         else if (HAS_PCH_SPLIT(dev))
10715                 return 120000;
10716         else if (!IS_GEN2(dev))
10717                 return 96000;
10718         else
10719                 return 48000;
10720 }
10721
10722 /* Returns the clock of the currently programmed mode of the given pipe. */
10723 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10724                                 struct intel_crtc_state *pipe_config)
10725 {
10726         struct drm_device *dev = crtc->base.dev;
10727         struct drm_i915_private *dev_priv = dev->dev_private;
10728         int pipe = pipe_config->cpu_transcoder;
10729         u32 dpll = pipe_config->dpll_hw_state.dpll;
10730         u32 fp;
10731         intel_clock_t clock;
10732         int port_clock;
10733         int refclk = i9xx_pll_refclk(dev, pipe_config);
10734
10735         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10736                 fp = pipe_config->dpll_hw_state.fp0;
10737         else
10738                 fp = pipe_config->dpll_hw_state.fp1;
10739
10740         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10741         if (IS_PINEVIEW(dev)) {
10742                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10743                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10744         } else {
10745                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10746                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10747         }
10748
10749         if (!IS_GEN2(dev)) {
10750                 if (IS_PINEVIEW(dev))
10751                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10752                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10753                 else
10754                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10755                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10756
10757                 switch (dpll & DPLL_MODE_MASK) {
10758                 case DPLLB_MODE_DAC_SERIAL:
10759                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10760                                 5 : 10;
10761                         break;
10762                 case DPLLB_MODE_LVDS:
10763                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10764                                 7 : 14;
10765                         break;
10766                 default:
10767                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10768                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10769                         return;
10770                 }
10771
10772                 if (IS_PINEVIEW(dev))
10773                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10774                 else
10775                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10776         } else {
10777                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10778                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10779
10780                 if (is_lvds) {
10781                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10782                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10783
10784                         if (lvds & LVDS_CLKB_POWER_UP)
10785                                 clock.p2 = 7;
10786                         else
10787                                 clock.p2 = 14;
10788                 } else {
10789                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10790                                 clock.p1 = 2;
10791                         else {
10792                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10793                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10794                         }
10795                         if (dpll & PLL_P2_DIVIDE_BY_4)
10796                                 clock.p2 = 4;
10797                         else
10798                                 clock.p2 = 2;
10799                 }
10800
10801                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10802         }
10803
10804         /*
10805          * This value includes pixel_multiplier. We will use
10806          * port_clock to compute adjusted_mode.crtc_clock in the
10807          * encoder's get_config() function.
10808          */
10809         pipe_config->port_clock = port_clock;
10810 }
10811
10812 int intel_dotclock_calculate(int link_freq,
10813                              const struct intel_link_m_n *m_n)
10814 {
10815         /*
10816          * The calculation for the data clock is:
10817          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10818          * But we want to avoid losing precison if possible, so:
10819          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10820          *
10821          * and the link clock is simpler:
10822          * link_clock = (m * link_clock) / n
10823          */
10824
10825         if (!m_n->link_n)
10826                 return 0;
10827
10828         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10829 }
10830
10831 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10832                                    struct intel_crtc_state *pipe_config)
10833 {
10834         struct drm_device *dev = crtc->base.dev;
10835
10836         /* read out port_clock from the DPLL */
10837         i9xx_crtc_clock_get(crtc, pipe_config);
10838
10839         /*
10840          * This value does not include pixel_multiplier.
10841          * We will check that port_clock and adjusted_mode.crtc_clock
10842          * agree once we know their relationship in the encoder's
10843          * get_config() function.
10844          */
10845         pipe_config->base.adjusted_mode.crtc_clock =
10846                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10847                                          &pipe_config->fdi_m_n);
10848 }
10849
10850 /** Returns the currently programmed mode of the given pipe. */
10851 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10852                                              struct drm_crtc *crtc)
10853 {
10854         struct drm_i915_private *dev_priv = dev->dev_private;
10855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10856         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10857         struct drm_display_mode *mode;
10858         struct intel_crtc_state pipe_config;
10859         int htot = I915_READ(HTOTAL(cpu_transcoder));
10860         int hsync = I915_READ(HSYNC(cpu_transcoder));
10861         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10862         int vsync = I915_READ(VSYNC(cpu_transcoder));
10863         enum pipe pipe = intel_crtc->pipe;
10864
10865         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10866         if (!mode)
10867                 return NULL;
10868
10869         /*
10870          * Construct a pipe_config sufficient for getting the clock info
10871          * back out of crtc_clock_get.
10872          *
10873          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10874          * to use a real value here instead.
10875          */
10876         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10877         pipe_config.pixel_multiplier = 1;
10878         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10879         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10880         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10881         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10882
10883         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10884         mode->hdisplay = (htot & 0xffff) + 1;
10885         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10886         mode->hsync_start = (hsync & 0xffff) + 1;
10887         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10888         mode->vdisplay = (vtot & 0xffff) + 1;
10889         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10890         mode->vsync_start = (vsync & 0xffff) + 1;
10891         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10892
10893         drm_mode_set_name(mode);
10894
10895         return mode;
10896 }
10897
10898 void intel_mark_busy(struct drm_device *dev)
10899 {
10900         struct drm_i915_private *dev_priv = dev->dev_private;
10901
10902         if (dev_priv->mm.busy)
10903                 return;
10904
10905         intel_runtime_pm_get(dev_priv);
10906         i915_update_gfx_val(dev_priv);
10907         if (INTEL_INFO(dev)->gen >= 6)
10908                 gen6_rps_busy(dev_priv);
10909         dev_priv->mm.busy = true;
10910 }
10911
10912 void intel_mark_idle(struct drm_device *dev)
10913 {
10914         struct drm_i915_private *dev_priv = dev->dev_private;
10915
10916         if (!dev_priv->mm.busy)
10917                 return;
10918
10919         dev_priv->mm.busy = false;
10920
10921         if (INTEL_INFO(dev)->gen >= 6)
10922                 gen6_rps_idle(dev->dev_private);
10923
10924         intel_runtime_pm_put(dev_priv);
10925 }
10926
10927 static void intel_crtc_destroy(struct drm_crtc *crtc)
10928 {
10929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10930         struct drm_device *dev = crtc->dev;
10931         struct intel_unpin_work *work;
10932
10933         spin_lock_irq(&dev->event_lock);
10934         work = intel_crtc->unpin_work;
10935         intel_crtc->unpin_work = NULL;
10936         spin_unlock_irq(&dev->event_lock);
10937
10938         if (work) {
10939                 cancel_work_sync(&work->work);
10940                 kfree(work);
10941         }
10942
10943         drm_crtc_cleanup(crtc);
10944
10945         kfree(intel_crtc);
10946 }
10947
10948 static void intel_unpin_work_fn(struct work_struct *__work)
10949 {
10950         struct intel_unpin_work *work =
10951                 container_of(__work, struct intel_unpin_work, work);
10952         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10953         struct drm_device *dev = crtc->base.dev;
10954         struct drm_plane *primary = crtc->base.primary;
10955
10956         mutex_lock(&dev->struct_mutex);
10957         intel_unpin_fb_obj(work->old_fb, primary->state);
10958         drm_gem_object_unreference(&work->pending_flip_obj->base);
10959
10960         if (work->flip_queued_req)
10961                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10962         mutex_unlock(&dev->struct_mutex);
10963
10964         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10965         drm_framebuffer_unreference(work->old_fb);
10966
10967         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10968         atomic_dec(&crtc->unpin_work_count);
10969
10970         kfree(work);
10971 }
10972
10973 static void do_intel_finish_page_flip(struct drm_device *dev,
10974                                       struct drm_crtc *crtc)
10975 {
10976         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10977         struct intel_unpin_work *work;
10978         unsigned long flags;
10979
10980         /* Ignore early vblank irqs */
10981         if (intel_crtc == NULL)
10982                 return;
10983
10984         /*
10985          * This is called both by irq handlers and the reset code (to complete
10986          * lost pageflips) so needs the full irqsave spinlocks.
10987          */
10988         spin_lock_irqsave(&dev->event_lock, flags);
10989         work = intel_crtc->unpin_work;
10990
10991         /* Ensure we don't miss a work->pending update ... */
10992         smp_rmb();
10993
10994         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10995                 spin_unlock_irqrestore(&dev->event_lock, flags);
10996                 return;
10997         }
10998
10999         page_flip_completed(intel_crtc);
11000
11001         spin_unlock_irqrestore(&dev->event_lock, flags);
11002 }
11003
11004 void intel_finish_page_flip(struct drm_device *dev, int pipe)
11005 {
11006         struct drm_i915_private *dev_priv = dev->dev_private;
11007         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11008
11009         do_intel_finish_page_flip(dev, crtc);
11010 }
11011
11012 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
11013 {
11014         struct drm_i915_private *dev_priv = dev->dev_private;
11015         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
11016
11017         do_intel_finish_page_flip(dev, crtc);
11018 }
11019
11020 /* Is 'a' after or equal to 'b'? */
11021 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11022 {
11023         return !((a - b) & 0x80000000);
11024 }
11025
11026 static bool page_flip_finished(struct intel_crtc *crtc)
11027 {
11028         struct drm_device *dev = crtc->base.dev;
11029         struct drm_i915_private *dev_priv = dev->dev_private;
11030
11031         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
11032             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
11033                 return true;
11034
11035         /*
11036          * The relevant registers doen't exist on pre-ctg.
11037          * As the flip done interrupt doesn't trigger for mmio
11038          * flips on gmch platforms, a flip count check isn't
11039          * really needed there. But since ctg has the registers,
11040          * include it in the check anyway.
11041          */
11042         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11043                 return true;
11044
11045         /*
11046          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11047          * used the same base address. In that case the mmio flip might
11048          * have completed, but the CS hasn't even executed the flip yet.
11049          *
11050          * A flip count check isn't enough as the CS might have updated
11051          * the base address just after start of vblank, but before we
11052          * managed to process the interrupt. This means we'd complete the
11053          * CS flip too soon.
11054          *
11055          * Combining both checks should get us a good enough result. It may
11056          * still happen that the CS flip has been executed, but has not
11057          * yet actually completed. But in case the base address is the same
11058          * anyway, we don't really care.
11059          */
11060         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11061                 crtc->unpin_work->gtt_offset &&
11062                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11063                                     crtc->unpin_work->flip_count);
11064 }
11065
11066 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11067 {
11068         struct drm_i915_private *dev_priv = dev->dev_private;
11069         struct intel_crtc *intel_crtc =
11070                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11071         unsigned long flags;
11072
11073
11074         /*
11075          * This is called both by irq handlers and the reset code (to complete
11076          * lost pageflips) so needs the full irqsave spinlocks.
11077          *
11078          * NB: An MMIO update of the plane base pointer will also
11079          * generate a page-flip completion irq, i.e. every modeset
11080          * is also accompanied by a spurious intel_prepare_page_flip().
11081          */
11082         spin_lock_irqsave(&dev->event_lock, flags);
11083         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11084                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11085         spin_unlock_irqrestore(&dev->event_lock, flags);
11086 }
11087
11088 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11089 {
11090         /* Ensure that the work item is consistent when activating it ... */
11091         smp_wmb();
11092         atomic_set(&work->pending, INTEL_FLIP_PENDING);
11093         /* and that it is marked active as soon as the irq could fire. */
11094         smp_wmb();
11095 }
11096
11097 static int intel_gen2_queue_flip(struct drm_device *dev,
11098                                  struct drm_crtc *crtc,
11099                                  struct drm_framebuffer *fb,
11100                                  struct drm_i915_gem_object *obj,
11101                                  struct drm_i915_gem_request *req,
11102                                  uint32_t flags)
11103 {
11104         struct intel_engine_cs *ring = req->ring;
11105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11106         u32 flip_mask;
11107         int ret;
11108
11109         ret = intel_ring_begin(req, 6);
11110         if (ret)
11111                 return ret;
11112
11113         /* Can't queue multiple flips, so wait for the previous
11114          * one to finish before executing the next.
11115          */
11116         if (intel_crtc->plane)
11117                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11118         else
11119                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11120         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11121         intel_ring_emit(ring, MI_NOOP);
11122         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11123                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11124         intel_ring_emit(ring, fb->pitches[0]);
11125         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11126         intel_ring_emit(ring, 0); /* aux display base address, unused */
11127
11128         intel_mark_page_flip_active(intel_crtc->unpin_work);
11129         return 0;
11130 }
11131
11132 static int intel_gen3_queue_flip(struct drm_device *dev,
11133                                  struct drm_crtc *crtc,
11134                                  struct drm_framebuffer *fb,
11135                                  struct drm_i915_gem_object *obj,
11136                                  struct drm_i915_gem_request *req,
11137                                  uint32_t flags)
11138 {
11139         struct intel_engine_cs *ring = req->ring;
11140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11141         u32 flip_mask;
11142         int ret;
11143
11144         ret = intel_ring_begin(req, 6);
11145         if (ret)
11146                 return ret;
11147
11148         if (intel_crtc->plane)
11149                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11150         else
11151                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11152         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11153         intel_ring_emit(ring, MI_NOOP);
11154         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11155                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11156         intel_ring_emit(ring, fb->pitches[0]);
11157         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11158         intel_ring_emit(ring, MI_NOOP);
11159
11160         intel_mark_page_flip_active(intel_crtc->unpin_work);
11161         return 0;
11162 }
11163
11164 static int intel_gen4_queue_flip(struct drm_device *dev,
11165                                  struct drm_crtc *crtc,
11166                                  struct drm_framebuffer *fb,
11167                                  struct drm_i915_gem_object *obj,
11168                                  struct drm_i915_gem_request *req,
11169                                  uint32_t flags)
11170 {
11171         struct intel_engine_cs *ring = req->ring;
11172         struct drm_i915_private *dev_priv = dev->dev_private;
11173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11174         uint32_t pf, pipesrc;
11175         int ret;
11176
11177         ret = intel_ring_begin(req, 4);
11178         if (ret)
11179                 return ret;
11180
11181         /* i965+ uses the linear or tiled offsets from the
11182          * Display Registers (which do not change across a page-flip)
11183          * so we need only reprogram the base address.
11184          */
11185         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11186                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11187         intel_ring_emit(ring, fb->pitches[0]);
11188         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11189                         obj->tiling_mode);
11190
11191         /* XXX Enabling the panel-fitter across page-flip is so far
11192          * untested on non-native modes, so ignore it for now.
11193          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11194          */
11195         pf = 0;
11196         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11197         intel_ring_emit(ring, pf | pipesrc);
11198
11199         intel_mark_page_flip_active(intel_crtc->unpin_work);
11200         return 0;
11201 }
11202
11203 static int intel_gen6_queue_flip(struct drm_device *dev,
11204                                  struct drm_crtc *crtc,
11205                                  struct drm_framebuffer *fb,
11206                                  struct drm_i915_gem_object *obj,
11207                                  struct drm_i915_gem_request *req,
11208                                  uint32_t flags)
11209 {
11210         struct intel_engine_cs *ring = req->ring;
11211         struct drm_i915_private *dev_priv = dev->dev_private;
11212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11213         uint32_t pf, pipesrc;
11214         int ret;
11215
11216         ret = intel_ring_begin(req, 4);
11217         if (ret)
11218                 return ret;
11219
11220         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11221                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11222         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11223         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11224
11225         /* Contrary to the suggestions in the documentation,
11226          * "Enable Panel Fitter" does not seem to be required when page
11227          * flipping with a non-native mode, and worse causes a normal
11228          * modeset to fail.
11229          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11230          */
11231         pf = 0;
11232         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11233         intel_ring_emit(ring, pf | pipesrc);
11234
11235         intel_mark_page_flip_active(intel_crtc->unpin_work);
11236         return 0;
11237 }
11238
11239 static int intel_gen7_queue_flip(struct drm_device *dev,
11240                                  struct drm_crtc *crtc,
11241                                  struct drm_framebuffer *fb,
11242                                  struct drm_i915_gem_object *obj,
11243                                  struct drm_i915_gem_request *req,
11244                                  uint32_t flags)
11245 {
11246         struct intel_engine_cs *ring = req->ring;
11247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11248         uint32_t plane_bit = 0;
11249         int len, ret;
11250
11251         switch (intel_crtc->plane) {
11252         case PLANE_A:
11253                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11254                 break;
11255         case PLANE_B:
11256                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11257                 break;
11258         case PLANE_C:
11259                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11260                 break;
11261         default:
11262                 WARN_ONCE(1, "unknown plane in flip command\n");
11263                 return -ENODEV;
11264         }
11265
11266         len = 4;
11267         if (ring->id == RCS) {
11268                 len += 6;
11269                 /*
11270                  * On Gen 8, SRM is now taking an extra dword to accommodate
11271                  * 48bits addresses, and we need a NOOP for the batch size to
11272                  * stay even.
11273                  */
11274                 if (IS_GEN8(dev))
11275                         len += 2;
11276         }
11277
11278         /*
11279          * BSpec MI_DISPLAY_FLIP for IVB:
11280          * "The full packet must be contained within the same cache line."
11281          *
11282          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11283          * cacheline, if we ever start emitting more commands before
11284          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11285          * then do the cacheline alignment, and finally emit the
11286          * MI_DISPLAY_FLIP.
11287          */
11288         ret = intel_ring_cacheline_align(req);
11289         if (ret)
11290                 return ret;
11291
11292         ret = intel_ring_begin(req, len);
11293         if (ret)
11294                 return ret;
11295
11296         /* Unmask the flip-done completion message. Note that the bspec says that
11297          * we should do this for both the BCS and RCS, and that we must not unmask
11298          * more than one flip event at any time (or ensure that one flip message
11299          * can be sent by waiting for flip-done prior to queueing new flips).
11300          * Experimentation says that BCS works despite DERRMR masking all
11301          * flip-done completion events and that unmasking all planes at once
11302          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11303          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11304          */
11305         if (ring->id == RCS) {
11306                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11307                 intel_ring_emit_reg(ring, DERRMR);
11308                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11309                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11310                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11311                 if (IS_GEN8(dev))
11312                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11313                                               MI_SRM_LRM_GLOBAL_GTT);
11314                 else
11315                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11316                                               MI_SRM_LRM_GLOBAL_GTT);
11317                 intel_ring_emit_reg(ring, DERRMR);
11318                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11319                 if (IS_GEN8(dev)) {
11320                         intel_ring_emit(ring, 0);
11321                         intel_ring_emit(ring, MI_NOOP);
11322                 }
11323         }
11324
11325         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11326         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11327         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11328         intel_ring_emit(ring, (MI_NOOP));
11329
11330         intel_mark_page_flip_active(intel_crtc->unpin_work);
11331         return 0;
11332 }
11333
11334 static bool use_mmio_flip(struct intel_engine_cs *ring,
11335                           struct drm_i915_gem_object *obj)
11336 {
11337         /*
11338          * This is not being used for older platforms, because
11339          * non-availability of flip done interrupt forces us to use
11340          * CS flips. Older platforms derive flip done using some clever
11341          * tricks involving the flip_pending status bits and vblank irqs.
11342          * So using MMIO flips there would disrupt this mechanism.
11343          */
11344
11345         if (ring == NULL)
11346                 return true;
11347
11348         if (INTEL_INFO(ring->dev)->gen < 5)
11349                 return false;
11350
11351         if (i915.use_mmio_flip < 0)
11352                 return false;
11353         else if (i915.use_mmio_flip > 0)
11354                 return true;
11355         else if (i915.enable_execlists)
11356                 return true;
11357         else if (obj->base.dma_buf &&
11358                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11359                                                        false))
11360                 return true;
11361         else
11362                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11363 }
11364
11365 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11366                              unsigned int rotation,
11367                              struct intel_unpin_work *work)
11368 {
11369         struct drm_device *dev = intel_crtc->base.dev;
11370         struct drm_i915_private *dev_priv = dev->dev_private;
11371         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11372         const enum pipe pipe = intel_crtc->pipe;
11373         u32 ctl, stride, tile_height;
11374
11375         ctl = I915_READ(PLANE_CTL(pipe, 0));
11376         ctl &= ~PLANE_CTL_TILED_MASK;
11377         switch (fb->modifier[0]) {
11378         case DRM_FORMAT_MOD_NONE:
11379                 break;
11380         case I915_FORMAT_MOD_X_TILED:
11381                 ctl |= PLANE_CTL_TILED_X;
11382                 break;
11383         case I915_FORMAT_MOD_Y_TILED:
11384                 ctl |= PLANE_CTL_TILED_Y;
11385                 break;
11386         case I915_FORMAT_MOD_Yf_TILED:
11387                 ctl |= PLANE_CTL_TILED_YF;
11388                 break;
11389         default:
11390                 MISSING_CASE(fb->modifier[0]);
11391         }
11392
11393         /*
11394          * The stride is either expressed as a multiple of 64 bytes chunks for
11395          * linear buffers or in number of tiles for tiled buffers.
11396          */
11397         if (intel_rotation_90_or_270(rotation)) {
11398                 /* stride = Surface height in tiles */
11399                 tile_height = intel_tile_height(dev, fb->pixel_format,
11400                                                 fb->modifier[0], 0);
11401                 stride = DIV_ROUND_UP(fb->height, tile_height);
11402         } else {
11403                 stride = fb->pitches[0] /
11404                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11405                                                           fb->pixel_format);
11406         }
11407
11408         /*
11409          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11410          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11411          */
11412         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11413         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11414
11415         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11416         POSTING_READ(PLANE_SURF(pipe, 0));
11417 }
11418
11419 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11420                              struct intel_unpin_work *work)
11421 {
11422         struct drm_device *dev = intel_crtc->base.dev;
11423         struct drm_i915_private *dev_priv = dev->dev_private;
11424         struct intel_framebuffer *intel_fb =
11425                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11426         struct drm_i915_gem_object *obj = intel_fb->obj;
11427         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11428         u32 dspcntr;
11429
11430         dspcntr = I915_READ(reg);
11431
11432         if (obj->tiling_mode != I915_TILING_NONE)
11433                 dspcntr |= DISPPLANE_TILED;
11434         else
11435                 dspcntr &= ~DISPPLANE_TILED;
11436
11437         I915_WRITE(reg, dspcntr);
11438
11439         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11440         POSTING_READ(DSPSURF(intel_crtc->plane));
11441 }
11442
11443 /*
11444  * XXX: This is the temporary way to update the plane registers until we get
11445  * around to using the usual plane update functions for MMIO flips
11446  */
11447 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11448 {
11449         struct intel_crtc *crtc = mmio_flip->crtc;
11450         struct intel_unpin_work *work;
11451
11452         spin_lock_irq(&crtc->base.dev->event_lock);
11453         work = crtc->unpin_work;
11454         spin_unlock_irq(&crtc->base.dev->event_lock);
11455         if (work == NULL)
11456                 return;
11457
11458         intel_mark_page_flip_active(work);
11459
11460         intel_pipe_update_start(crtc);
11461
11462         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11463                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11464         else
11465                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11466                 ilk_do_mmio_flip(crtc, work);
11467
11468         intel_pipe_update_end(crtc);
11469 }
11470
11471 static void intel_mmio_flip_work_func(struct work_struct *work)
11472 {
11473         struct intel_mmio_flip *mmio_flip =
11474                 container_of(work, struct intel_mmio_flip, work);
11475         struct intel_framebuffer *intel_fb =
11476                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11477         struct drm_i915_gem_object *obj = intel_fb->obj;
11478
11479         if (mmio_flip->req) {
11480                 WARN_ON(__i915_wait_request(mmio_flip->req,
11481                                             mmio_flip->crtc->reset_counter,
11482                                             false, NULL,
11483                                             &mmio_flip->i915->rps.mmioflips));
11484                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11485         }
11486
11487         /* For framebuffer backed by dmabuf, wait for fence */
11488         if (obj->base.dma_buf)
11489                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11490                                                             false, false,
11491                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11492
11493         intel_do_mmio_flip(mmio_flip);
11494         kfree(mmio_flip);
11495 }
11496
11497 static int intel_queue_mmio_flip(struct drm_device *dev,
11498                                  struct drm_crtc *crtc,
11499                                  struct drm_i915_gem_object *obj)
11500 {
11501         struct intel_mmio_flip *mmio_flip;
11502
11503         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11504         if (mmio_flip == NULL)
11505                 return -ENOMEM;
11506
11507         mmio_flip->i915 = to_i915(dev);
11508         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11509         mmio_flip->crtc = to_intel_crtc(crtc);
11510         mmio_flip->rotation = crtc->primary->state->rotation;
11511
11512         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11513         schedule_work(&mmio_flip->work);
11514
11515         return 0;
11516 }
11517
11518 static int intel_default_queue_flip(struct drm_device *dev,
11519                                     struct drm_crtc *crtc,
11520                                     struct drm_framebuffer *fb,
11521                                     struct drm_i915_gem_object *obj,
11522                                     struct drm_i915_gem_request *req,
11523                                     uint32_t flags)
11524 {
11525         return -ENODEV;
11526 }
11527
11528 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11529                                          struct drm_crtc *crtc)
11530 {
11531         struct drm_i915_private *dev_priv = dev->dev_private;
11532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11533         struct intel_unpin_work *work = intel_crtc->unpin_work;
11534         u32 addr;
11535
11536         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11537                 return true;
11538
11539         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11540                 return false;
11541
11542         if (!work->enable_stall_check)
11543                 return false;
11544
11545         if (work->flip_ready_vblank == 0) {
11546                 if (work->flip_queued_req &&
11547                     !i915_gem_request_completed(work->flip_queued_req, true))
11548                         return false;
11549
11550                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11551         }
11552
11553         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11554                 return false;
11555
11556         /* Potential stall - if we see that the flip has happened,
11557          * assume a missed interrupt. */
11558         if (INTEL_INFO(dev)->gen >= 4)
11559                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11560         else
11561                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11562
11563         /* There is a potential issue here with a false positive after a flip
11564          * to the same address. We could address this by checking for a
11565          * non-incrementing frame counter.
11566          */
11567         return addr == work->gtt_offset;
11568 }
11569
11570 void intel_check_page_flip(struct drm_device *dev, int pipe)
11571 {
11572         struct drm_i915_private *dev_priv = dev->dev_private;
11573         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11575         struct intel_unpin_work *work;
11576
11577         WARN_ON(!in_interrupt());
11578
11579         if (crtc == NULL)
11580                 return;
11581
11582         spin_lock(&dev->event_lock);
11583         work = intel_crtc->unpin_work;
11584         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11585                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11586                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11587                 page_flip_completed(intel_crtc);
11588                 work = NULL;
11589         }
11590         if (work != NULL &&
11591             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11592                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11593         spin_unlock(&dev->event_lock);
11594 }
11595
11596 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11597                                 struct drm_framebuffer *fb,
11598                                 struct drm_pending_vblank_event *event,
11599                                 uint32_t page_flip_flags)
11600 {
11601         struct drm_device *dev = crtc->dev;
11602         struct drm_i915_private *dev_priv = dev->dev_private;
11603         struct drm_framebuffer *old_fb = crtc->primary->fb;
11604         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11606         struct drm_plane *primary = crtc->primary;
11607         enum pipe pipe = intel_crtc->pipe;
11608         struct intel_unpin_work *work;
11609         struct intel_engine_cs *ring;
11610         bool mmio_flip;
11611         struct drm_i915_gem_request *request = NULL;
11612         int ret;
11613
11614         /*
11615          * drm_mode_page_flip_ioctl() should already catch this, but double
11616          * check to be safe.  In the future we may enable pageflipping from
11617          * a disabled primary plane.
11618          */
11619         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11620                 return -EBUSY;
11621
11622         /* Can't change pixel format via MI display flips. */
11623         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11624                 return -EINVAL;
11625
11626         /*
11627          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11628          * Note that pitch changes could also affect these register.
11629          */
11630         if (INTEL_INFO(dev)->gen > 3 &&
11631             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11632              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11633                 return -EINVAL;
11634
11635         if (i915_terminally_wedged(&dev_priv->gpu_error))
11636                 goto out_hang;
11637
11638         work = kzalloc(sizeof(*work), GFP_KERNEL);
11639         if (work == NULL)
11640                 return -ENOMEM;
11641
11642         work->event = event;
11643         work->crtc = crtc;
11644         work->old_fb = old_fb;
11645         INIT_WORK(&work->work, intel_unpin_work_fn);
11646
11647         ret = drm_crtc_vblank_get(crtc);
11648         if (ret)
11649                 goto free_work;
11650
11651         /* We borrow the event spin lock for protecting unpin_work */
11652         spin_lock_irq(&dev->event_lock);
11653         if (intel_crtc->unpin_work) {
11654                 /* Before declaring the flip queue wedged, check if
11655                  * the hardware completed the operation behind our backs.
11656                  */
11657                 if (__intel_pageflip_stall_check(dev, crtc)) {
11658                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11659                         page_flip_completed(intel_crtc);
11660                 } else {
11661                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11662                         spin_unlock_irq(&dev->event_lock);
11663
11664                         drm_crtc_vblank_put(crtc);
11665                         kfree(work);
11666                         return -EBUSY;
11667                 }
11668         }
11669         intel_crtc->unpin_work = work;
11670         spin_unlock_irq(&dev->event_lock);
11671
11672         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11673                 flush_workqueue(dev_priv->wq);
11674
11675         /* Reference the objects for the scheduled work. */
11676         drm_framebuffer_reference(work->old_fb);
11677         drm_gem_object_reference(&obj->base);
11678
11679         crtc->primary->fb = fb;
11680         update_state_fb(crtc->primary);
11681
11682         work->pending_flip_obj = obj;
11683
11684         ret = i915_mutex_lock_interruptible(dev);
11685         if (ret)
11686                 goto cleanup;
11687
11688         atomic_inc(&intel_crtc->unpin_work_count);
11689         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11690
11691         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11692                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11693
11694         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11695                 ring = &dev_priv->ring[BCS];
11696                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11697                         /* vlv: DISPLAY_FLIP fails to change tiling */
11698                         ring = NULL;
11699         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11700                 ring = &dev_priv->ring[BCS];
11701         } else if (INTEL_INFO(dev)->gen >= 7) {
11702                 ring = i915_gem_request_get_ring(obj->last_write_req);
11703                 if (ring == NULL || ring->id != RCS)
11704                         ring = &dev_priv->ring[BCS];
11705         } else {
11706                 ring = &dev_priv->ring[RCS];
11707         }
11708
11709         mmio_flip = use_mmio_flip(ring, obj);
11710
11711         /* When using CS flips, we want to emit semaphores between rings.
11712          * However, when using mmio flips we will create a task to do the
11713          * synchronisation, so all we want here is to pin the framebuffer
11714          * into the display plane and skip any waits.
11715          */
11716         if (!mmio_flip) {
11717                 ret = i915_gem_object_sync(obj, ring, &request);
11718                 if (ret)
11719                         goto cleanup_pending;
11720         }
11721
11722         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11723                                          crtc->primary->state);
11724         if (ret)
11725                 goto cleanup_pending;
11726
11727         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11728                                                   obj, 0);
11729         work->gtt_offset += intel_crtc->dspaddr_offset;
11730
11731         if (mmio_flip) {
11732                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11733                 if (ret)
11734                         goto cleanup_unpin;
11735
11736                 i915_gem_request_assign(&work->flip_queued_req,
11737                                         obj->last_write_req);
11738         } else {
11739                 if (!request) {
11740                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11741                         if (ret)
11742                                 goto cleanup_unpin;
11743                 }
11744
11745                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11746                                                    page_flip_flags);
11747                 if (ret)
11748                         goto cleanup_unpin;
11749
11750                 i915_gem_request_assign(&work->flip_queued_req, request);
11751         }
11752
11753         if (request)
11754                 i915_add_request_no_flush(request);
11755
11756         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11757         work->enable_stall_check = true;
11758
11759         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11760                           to_intel_plane(primary)->frontbuffer_bit);
11761         mutex_unlock(&dev->struct_mutex);
11762
11763         intel_fbc_deactivate(intel_crtc);
11764         intel_frontbuffer_flip_prepare(dev,
11765                                        to_intel_plane(primary)->frontbuffer_bit);
11766
11767         trace_i915_flip_request(intel_crtc->plane, obj);
11768
11769         return 0;
11770
11771 cleanup_unpin:
11772         intel_unpin_fb_obj(fb, crtc->primary->state);
11773 cleanup_pending:
11774         if (request)
11775                 i915_gem_request_cancel(request);
11776         atomic_dec(&intel_crtc->unpin_work_count);
11777         mutex_unlock(&dev->struct_mutex);
11778 cleanup:
11779         crtc->primary->fb = old_fb;
11780         update_state_fb(crtc->primary);
11781
11782         drm_gem_object_unreference_unlocked(&obj->base);
11783         drm_framebuffer_unreference(work->old_fb);
11784
11785         spin_lock_irq(&dev->event_lock);
11786         intel_crtc->unpin_work = NULL;
11787         spin_unlock_irq(&dev->event_lock);
11788
11789         drm_crtc_vblank_put(crtc);
11790 free_work:
11791         kfree(work);
11792
11793         if (ret == -EIO) {
11794                 struct drm_atomic_state *state;
11795                 struct drm_plane_state *plane_state;
11796
11797 out_hang:
11798                 state = drm_atomic_state_alloc(dev);
11799                 if (!state)
11800                         return -ENOMEM;
11801                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11802
11803 retry:
11804                 plane_state = drm_atomic_get_plane_state(state, primary);
11805                 ret = PTR_ERR_OR_ZERO(plane_state);
11806                 if (!ret) {
11807                         drm_atomic_set_fb_for_plane(plane_state, fb);
11808
11809                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11810                         if (!ret)
11811                                 ret = drm_atomic_commit(state);
11812                 }
11813
11814                 if (ret == -EDEADLK) {
11815                         drm_modeset_backoff(state->acquire_ctx);
11816                         drm_atomic_state_clear(state);
11817                         goto retry;
11818                 }
11819
11820                 if (ret)
11821                         drm_atomic_state_free(state);
11822
11823                 if (ret == 0 && event) {
11824                         spin_lock_irq(&dev->event_lock);
11825                         drm_send_vblank_event(dev, pipe, event);
11826                         spin_unlock_irq(&dev->event_lock);
11827                 }
11828         }
11829         return ret;
11830 }
11831
11832
11833 /**
11834  * intel_wm_need_update - Check whether watermarks need updating
11835  * @plane: drm plane
11836  * @state: new plane state
11837  *
11838  * Check current plane state versus the new one to determine whether
11839  * watermarks need to be recalculated.
11840  *
11841  * Returns true or false.
11842  */
11843 static bool intel_wm_need_update(struct drm_plane *plane,
11844                                  struct drm_plane_state *state)
11845 {
11846         struct intel_plane_state *new = to_intel_plane_state(state);
11847         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11848
11849         /* Update watermarks on tiling or size changes. */
11850         if (new->visible != cur->visible)
11851                 return true;
11852
11853         if (!cur->base.fb || !new->base.fb)
11854                 return false;
11855
11856         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11857             cur->base.rotation != new->base.rotation ||
11858             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11859             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11860             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11861             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11862                 return true;
11863
11864         return false;
11865 }
11866
11867 static bool needs_scaling(struct intel_plane_state *state)
11868 {
11869         int src_w = drm_rect_width(&state->src) >> 16;
11870         int src_h = drm_rect_height(&state->src) >> 16;
11871         int dst_w = drm_rect_width(&state->dst);
11872         int dst_h = drm_rect_height(&state->dst);
11873
11874         return (src_w != dst_w || src_h != dst_h);
11875 }
11876
11877 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11878                                     struct drm_plane_state *plane_state)
11879 {
11880         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11881         struct drm_crtc *crtc = crtc_state->crtc;
11882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11883         struct drm_plane *plane = plane_state->plane;
11884         struct drm_device *dev = crtc->dev;
11885         struct drm_i915_private *dev_priv = dev->dev_private;
11886         struct intel_plane_state *old_plane_state =
11887                 to_intel_plane_state(plane->state);
11888         int idx = intel_crtc->base.base.id, ret;
11889         int i = drm_plane_index(plane);
11890         bool mode_changed = needs_modeset(crtc_state);
11891         bool was_crtc_enabled = crtc->state->active;
11892         bool is_crtc_enabled = crtc_state->active;
11893         bool turn_off, turn_on, visible, was_visible;
11894         struct drm_framebuffer *fb = plane_state->fb;
11895
11896         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11897             plane->type != DRM_PLANE_TYPE_CURSOR) {
11898                 ret = skl_update_scaler_plane(
11899                         to_intel_crtc_state(crtc_state),
11900                         to_intel_plane_state(plane_state));
11901                 if (ret)
11902                         return ret;
11903         }
11904
11905         was_visible = old_plane_state->visible;
11906         visible = to_intel_plane_state(plane_state)->visible;
11907
11908         if (!was_crtc_enabled && WARN_ON(was_visible))
11909                 was_visible = false;
11910
11911         /*
11912          * Visibility is calculated as if the crtc was on, but
11913          * after scaler setup everything depends on it being off
11914          * when the crtc isn't active.
11915          */
11916         if (!is_crtc_enabled)
11917                 to_intel_plane_state(plane_state)->visible = visible = false;
11918
11919         if (!was_visible && !visible)
11920                 return 0;
11921
11922         turn_off = was_visible && (!visible || mode_changed);
11923         turn_on = visible && (!was_visible || mode_changed);
11924
11925         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11926                          plane->base.id, fb ? fb->base.id : -1);
11927
11928         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11929                          plane->base.id, was_visible, visible,
11930                          turn_off, turn_on, mode_changed);
11931
11932         if (turn_on || turn_off) {
11933                 pipe_config->wm_changed = true;
11934
11935                 /* must disable cxsr around plane enable/disable */
11936                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11937                         if (is_crtc_enabled)
11938                                 intel_crtc->atomic.wait_vblank = true;
11939                         pipe_config->disable_cxsr = true;
11940                 }
11941         } else if (intel_wm_need_update(plane, plane_state)) {
11942                 pipe_config->wm_changed = true;
11943         }
11944
11945         /* Pre-gen9 platforms need two-step watermark updates */
11946         if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 &&
11947             dev_priv->display.optimize_watermarks)
11948                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11949
11950         if (visible || was_visible)
11951                 intel_crtc->atomic.fb_bits |=
11952                         to_intel_plane(plane)->frontbuffer_bit;
11953
11954         switch (plane->type) {
11955         case DRM_PLANE_TYPE_PRIMARY:
11956                 intel_crtc->atomic.pre_disable_primary = turn_off;
11957                 intel_crtc->atomic.post_enable_primary = turn_on;
11958
11959                 if (turn_off) {
11960                         /*
11961                          * FIXME: Actually if we will still have any other
11962                          * plane enabled on the pipe we could let IPS enabled
11963                          * still, but for now lets consider that when we make
11964                          * primary invisible by setting DSPCNTR to 0 on
11965                          * update_primary_plane function IPS needs to be
11966                          * disable.
11967                          */
11968                         intel_crtc->atomic.disable_ips = true;
11969
11970                         intel_crtc->atomic.disable_fbc = true;
11971                 }
11972
11973                 /*
11974                  * FBC does not work on some platforms for rotated
11975                  * planes, so disable it when rotation is not 0 and
11976                  * update it when rotation is set back to 0.
11977                  *
11978                  * FIXME: This is redundant with the fbc update done in
11979                  * the primary plane enable function except that that
11980                  * one is done too late. We eventually need to unify
11981                  * this.
11982                  */
11983
11984                 if (visible &&
11985                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11986                     dev_priv->fbc.crtc == intel_crtc &&
11987                     plane_state->rotation != BIT(DRM_ROTATE_0))
11988                         intel_crtc->atomic.disable_fbc = true;
11989
11990                 /*
11991                  * BDW signals flip done immediately if the plane
11992                  * is disabled, even if the plane enable is already
11993                  * armed to occur at the next vblank :(
11994                  */
11995                 if (turn_on && IS_BROADWELL(dev))
11996                         intel_crtc->atomic.wait_vblank = true;
11997
11998                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11999                 break;
12000         case DRM_PLANE_TYPE_CURSOR:
12001                 break;
12002         case DRM_PLANE_TYPE_OVERLAY:
12003                 /*
12004                  * WaCxSRDisabledForSpriteScaling:ivb
12005                  *
12006                  * cstate->update_wm was already set above, so this flag will
12007                  * take effect when we commit and program watermarks.
12008                  */
12009                 if (IS_IVYBRIDGE(dev) &&
12010                     needs_scaling(to_intel_plane_state(plane_state)) &&
12011                     !needs_scaling(old_plane_state)) {
12012                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
12013                 } else if (turn_off && !mode_changed) {
12014                         intel_crtc->atomic.wait_vblank = true;
12015                         intel_crtc->atomic.update_sprite_watermarks |=
12016                                 1 << i;
12017                 }
12018
12019                 break;
12020         }
12021         return 0;
12022 }
12023
12024 static bool encoders_cloneable(const struct intel_encoder *a,
12025                                const struct intel_encoder *b)
12026 {
12027         /* masks could be asymmetric, so check both ways */
12028         return a == b || (a->cloneable & (1 << b->type) &&
12029                           b->cloneable & (1 << a->type));
12030 }
12031
12032 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12033                                          struct intel_crtc *crtc,
12034                                          struct intel_encoder *encoder)
12035 {
12036         struct intel_encoder *source_encoder;
12037         struct drm_connector *connector;
12038         struct drm_connector_state *connector_state;
12039         int i;
12040
12041         for_each_connector_in_state(state, connector, connector_state, i) {
12042                 if (connector_state->crtc != &crtc->base)
12043                         continue;
12044
12045                 source_encoder =
12046                         to_intel_encoder(connector_state->best_encoder);
12047                 if (!encoders_cloneable(encoder, source_encoder))
12048                         return false;
12049         }
12050
12051         return true;
12052 }
12053
12054 static bool check_encoder_cloning(struct drm_atomic_state *state,
12055                                   struct intel_crtc *crtc)
12056 {
12057         struct intel_encoder *encoder;
12058         struct drm_connector *connector;
12059         struct drm_connector_state *connector_state;
12060         int i;
12061
12062         for_each_connector_in_state(state, connector, connector_state, i) {
12063                 if (connector_state->crtc != &crtc->base)
12064                         continue;
12065
12066                 encoder = to_intel_encoder(connector_state->best_encoder);
12067                 if (!check_single_encoder_cloning(state, crtc, encoder))
12068                         return false;
12069         }
12070
12071         return true;
12072 }
12073
12074 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12075                                    struct drm_crtc_state *crtc_state)
12076 {
12077         struct drm_device *dev = crtc->dev;
12078         struct drm_i915_private *dev_priv = dev->dev_private;
12079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12080         struct intel_crtc_state *pipe_config =
12081                 to_intel_crtc_state(crtc_state);
12082         struct drm_atomic_state *state = crtc_state->state;
12083         int ret;
12084         bool mode_changed = needs_modeset(crtc_state);
12085
12086         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12087                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12088                 return -EINVAL;
12089         }
12090
12091         if (mode_changed && !crtc_state->active)
12092                 pipe_config->wm_changed = true;
12093
12094         if (mode_changed && crtc_state->enable &&
12095             dev_priv->display.crtc_compute_clock &&
12096             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12097                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12098                                                            pipe_config);
12099                 if (ret)
12100                         return ret;
12101         }
12102
12103         ret = 0;
12104         if (dev_priv->display.compute_pipe_wm) {
12105                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12106                 if (ret) {
12107                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12108                         return ret;
12109                 }
12110         }
12111
12112         if (dev_priv->display.compute_intermediate_wm &&
12113             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12114                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12115                         return 0;
12116
12117                 /*
12118                  * Calculate 'intermediate' watermarks that satisfy both the
12119                  * old state and the new state.  We can program these
12120                  * immediately.
12121                  */
12122                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12123                                                                 intel_crtc,
12124                                                                 pipe_config);
12125                 if (ret) {
12126                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12127                         return ret;
12128                 }
12129         }
12130
12131         if (INTEL_INFO(dev)->gen >= 9) {
12132                 if (mode_changed)
12133                         ret = skl_update_scaler_crtc(pipe_config);
12134
12135                 if (!ret)
12136                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12137                                                          pipe_config);
12138         }
12139
12140         return ret;
12141 }
12142
12143 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12144         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12145         .load_lut = intel_crtc_load_lut,
12146         .atomic_begin = intel_begin_crtc_commit,
12147         .atomic_flush = intel_finish_crtc_commit,
12148         .atomic_check = intel_crtc_atomic_check,
12149 };
12150
12151 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12152 {
12153         struct intel_connector *connector;
12154
12155         for_each_intel_connector(dev, connector) {
12156                 if (connector->base.encoder) {
12157                         connector->base.state->best_encoder =
12158                                 connector->base.encoder;
12159                         connector->base.state->crtc =
12160                                 connector->base.encoder->crtc;
12161                 } else {
12162                         connector->base.state->best_encoder = NULL;
12163                         connector->base.state->crtc = NULL;
12164                 }
12165         }
12166 }
12167
12168 static void
12169 connected_sink_compute_bpp(struct intel_connector *connector,
12170                            struct intel_crtc_state *pipe_config)
12171 {
12172         int bpp = pipe_config->pipe_bpp;
12173
12174         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12175                 connector->base.base.id,
12176                 connector->base.name);
12177
12178         /* Don't use an invalid EDID bpc value */
12179         if (connector->base.display_info.bpc &&
12180             connector->base.display_info.bpc * 3 < bpp) {
12181                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12182                               bpp, connector->base.display_info.bpc*3);
12183                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12184         }
12185
12186         /* Clamp bpp to 8 on screens without EDID 1.4 */
12187         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12188                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12189                               bpp);
12190                 pipe_config->pipe_bpp = 24;
12191         }
12192 }
12193
12194 static int
12195 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12196                           struct intel_crtc_state *pipe_config)
12197 {
12198         struct drm_device *dev = crtc->base.dev;
12199         struct drm_atomic_state *state;
12200         struct drm_connector *connector;
12201         struct drm_connector_state *connector_state;
12202         int bpp, i;
12203
12204         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12205                 bpp = 10*3;
12206         else if (INTEL_INFO(dev)->gen >= 5)
12207                 bpp = 12*3;
12208         else
12209                 bpp = 8*3;
12210
12211
12212         pipe_config->pipe_bpp = bpp;
12213
12214         state = pipe_config->base.state;
12215
12216         /* Clamp display bpp to EDID value */
12217         for_each_connector_in_state(state, connector, connector_state, i) {
12218                 if (connector_state->crtc != &crtc->base)
12219                         continue;
12220
12221                 connected_sink_compute_bpp(to_intel_connector(connector),
12222                                            pipe_config);
12223         }
12224
12225         return bpp;
12226 }
12227
12228 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12229 {
12230         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12231                         "type: 0x%x flags: 0x%x\n",
12232                 mode->crtc_clock,
12233                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12234                 mode->crtc_hsync_end, mode->crtc_htotal,
12235                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12236                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12237 }
12238
12239 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12240                                    struct intel_crtc_state *pipe_config,
12241                                    const char *context)
12242 {
12243         struct drm_device *dev = crtc->base.dev;
12244         struct drm_plane *plane;
12245         struct intel_plane *intel_plane;
12246         struct intel_plane_state *state;
12247         struct drm_framebuffer *fb;
12248
12249         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12250                       context, pipe_config, pipe_name(crtc->pipe));
12251
12252         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12253         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12254                       pipe_config->pipe_bpp, pipe_config->dither);
12255         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12256                       pipe_config->has_pch_encoder,
12257                       pipe_config->fdi_lanes,
12258                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12259                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12260                       pipe_config->fdi_m_n.tu);
12261         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12262                       pipe_config->has_dp_encoder,
12263                       pipe_config->lane_count,
12264                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12265                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12266                       pipe_config->dp_m_n.tu);
12267
12268         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12269                       pipe_config->has_dp_encoder,
12270                       pipe_config->lane_count,
12271                       pipe_config->dp_m2_n2.gmch_m,
12272                       pipe_config->dp_m2_n2.gmch_n,
12273                       pipe_config->dp_m2_n2.link_m,
12274                       pipe_config->dp_m2_n2.link_n,
12275                       pipe_config->dp_m2_n2.tu);
12276
12277         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12278                       pipe_config->has_audio,
12279                       pipe_config->has_infoframe);
12280
12281         DRM_DEBUG_KMS("requested mode:\n");
12282         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12283         DRM_DEBUG_KMS("adjusted mode:\n");
12284         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12285         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12286         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12287         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12288                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12289         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12290                       crtc->num_scalers,
12291                       pipe_config->scaler_state.scaler_users,
12292                       pipe_config->scaler_state.scaler_id);
12293         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12294                       pipe_config->gmch_pfit.control,
12295                       pipe_config->gmch_pfit.pgm_ratios,
12296                       pipe_config->gmch_pfit.lvds_border_bits);
12297         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12298                       pipe_config->pch_pfit.pos,
12299                       pipe_config->pch_pfit.size,
12300                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12301         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12302         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12303
12304         if (IS_BROXTON(dev)) {
12305                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12306                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12307                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12308                               pipe_config->ddi_pll_sel,
12309                               pipe_config->dpll_hw_state.ebb0,
12310                               pipe_config->dpll_hw_state.ebb4,
12311                               pipe_config->dpll_hw_state.pll0,
12312                               pipe_config->dpll_hw_state.pll1,
12313                               pipe_config->dpll_hw_state.pll2,
12314                               pipe_config->dpll_hw_state.pll3,
12315                               pipe_config->dpll_hw_state.pll6,
12316                               pipe_config->dpll_hw_state.pll8,
12317                               pipe_config->dpll_hw_state.pll9,
12318                               pipe_config->dpll_hw_state.pll10,
12319                               pipe_config->dpll_hw_state.pcsdw12);
12320         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12321                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12322                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12323                               pipe_config->ddi_pll_sel,
12324                               pipe_config->dpll_hw_state.ctrl1,
12325                               pipe_config->dpll_hw_state.cfgcr1,
12326                               pipe_config->dpll_hw_state.cfgcr2);
12327         } else if (HAS_DDI(dev)) {
12328                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12329                               pipe_config->ddi_pll_sel,
12330                               pipe_config->dpll_hw_state.wrpll,
12331                               pipe_config->dpll_hw_state.spll);
12332         } else {
12333                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12334                               "fp0: 0x%x, fp1: 0x%x\n",
12335                               pipe_config->dpll_hw_state.dpll,
12336                               pipe_config->dpll_hw_state.dpll_md,
12337                               pipe_config->dpll_hw_state.fp0,
12338                               pipe_config->dpll_hw_state.fp1);
12339         }
12340
12341         DRM_DEBUG_KMS("planes on this crtc\n");
12342         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12343                 intel_plane = to_intel_plane(plane);
12344                 if (intel_plane->pipe != crtc->pipe)
12345                         continue;
12346
12347                 state = to_intel_plane_state(plane->state);
12348                 fb = state->base.fb;
12349                 if (!fb) {
12350                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12351                                 "disabled, scaler_id = %d\n",
12352                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12353                                 plane->base.id, intel_plane->pipe,
12354                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12355                                 drm_plane_index(plane), state->scaler_id);
12356                         continue;
12357                 }
12358
12359                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12360                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12361                         plane->base.id, intel_plane->pipe,
12362                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12363                         drm_plane_index(plane));
12364                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12365                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12366                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12367                         state->scaler_id,
12368                         state->src.x1 >> 16, state->src.y1 >> 16,
12369                         drm_rect_width(&state->src) >> 16,
12370                         drm_rect_height(&state->src) >> 16,
12371                         state->dst.x1, state->dst.y1,
12372                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12373         }
12374 }
12375
12376 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12377 {
12378         struct drm_device *dev = state->dev;
12379         struct drm_connector *connector;
12380         unsigned int used_ports = 0;
12381
12382         /*
12383          * Walk the connector list instead of the encoder
12384          * list to detect the problem on ddi platforms
12385          * where there's just one encoder per digital port.
12386          */
12387         drm_for_each_connector(connector, dev) {
12388                 struct drm_connector_state *connector_state;
12389                 struct intel_encoder *encoder;
12390
12391                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12392                 if (!connector_state)
12393                         connector_state = connector->state;
12394
12395                 if (!connector_state->best_encoder)
12396                         continue;
12397
12398                 encoder = to_intel_encoder(connector_state->best_encoder);
12399
12400                 WARN_ON(!connector_state->crtc);
12401
12402                 switch (encoder->type) {
12403                         unsigned int port_mask;
12404                 case INTEL_OUTPUT_UNKNOWN:
12405                         if (WARN_ON(!HAS_DDI(dev)))
12406                                 break;
12407                 case INTEL_OUTPUT_DISPLAYPORT:
12408                 case INTEL_OUTPUT_HDMI:
12409                 case INTEL_OUTPUT_EDP:
12410                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12411
12412                         /* the same port mustn't appear more than once */
12413                         if (used_ports & port_mask)
12414                                 return false;
12415
12416                         used_ports |= port_mask;
12417                 default:
12418                         break;
12419                 }
12420         }
12421
12422         return true;
12423 }
12424
12425 static void
12426 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12427 {
12428         struct drm_crtc_state tmp_state;
12429         struct intel_crtc_scaler_state scaler_state;
12430         struct intel_dpll_hw_state dpll_hw_state;
12431         enum intel_dpll_id shared_dpll;
12432         uint32_t ddi_pll_sel;
12433         bool force_thru;
12434
12435         /* FIXME: before the switch to atomic started, a new pipe_config was
12436          * kzalloc'd. Code that depends on any field being zero should be
12437          * fixed, so that the crtc_state can be safely duplicated. For now,
12438          * only fields that are know to not cause problems are preserved. */
12439
12440         tmp_state = crtc_state->base;
12441         scaler_state = crtc_state->scaler_state;
12442         shared_dpll = crtc_state->shared_dpll;
12443         dpll_hw_state = crtc_state->dpll_hw_state;
12444         ddi_pll_sel = crtc_state->ddi_pll_sel;
12445         force_thru = crtc_state->pch_pfit.force_thru;
12446
12447         memset(crtc_state, 0, sizeof *crtc_state);
12448
12449         crtc_state->base = tmp_state;
12450         crtc_state->scaler_state = scaler_state;
12451         crtc_state->shared_dpll = shared_dpll;
12452         crtc_state->dpll_hw_state = dpll_hw_state;
12453         crtc_state->ddi_pll_sel = ddi_pll_sel;
12454         crtc_state->pch_pfit.force_thru = force_thru;
12455 }
12456
12457 static int
12458 intel_modeset_pipe_config(struct drm_crtc *crtc,
12459                           struct intel_crtc_state *pipe_config)
12460 {
12461         struct drm_atomic_state *state = pipe_config->base.state;
12462         struct intel_encoder *encoder;
12463         struct drm_connector *connector;
12464         struct drm_connector_state *connector_state;
12465         int base_bpp, ret = -EINVAL;
12466         int i;
12467         bool retry = true;
12468
12469         clear_intel_crtc_state(pipe_config);
12470
12471         pipe_config->cpu_transcoder =
12472                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12473
12474         /*
12475          * Sanitize sync polarity flags based on requested ones. If neither
12476          * positive or negative polarity is requested, treat this as meaning
12477          * negative polarity.
12478          */
12479         if (!(pipe_config->base.adjusted_mode.flags &
12480               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12481                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12482
12483         if (!(pipe_config->base.adjusted_mode.flags &
12484               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12485                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12486
12487         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12488                                              pipe_config);
12489         if (base_bpp < 0)
12490                 goto fail;
12491
12492         /*
12493          * Determine the real pipe dimensions. Note that stereo modes can
12494          * increase the actual pipe size due to the frame doubling and
12495          * insertion of additional space for blanks between the frame. This
12496          * is stored in the crtc timings. We use the requested mode to do this
12497          * computation to clearly distinguish it from the adjusted mode, which
12498          * can be changed by the connectors in the below retry loop.
12499          */
12500         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12501                                &pipe_config->pipe_src_w,
12502                                &pipe_config->pipe_src_h);
12503
12504 encoder_retry:
12505         /* Ensure the port clock defaults are reset when retrying. */
12506         pipe_config->port_clock = 0;
12507         pipe_config->pixel_multiplier = 1;
12508
12509         /* Fill in default crtc timings, allow encoders to overwrite them. */
12510         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12511                               CRTC_STEREO_DOUBLE);
12512
12513         /* Pass our mode to the connectors and the CRTC to give them a chance to
12514          * adjust it according to limitations or connector properties, and also
12515          * a chance to reject the mode entirely.
12516          */
12517         for_each_connector_in_state(state, connector, connector_state, i) {
12518                 if (connector_state->crtc != crtc)
12519                         continue;
12520
12521                 encoder = to_intel_encoder(connector_state->best_encoder);
12522
12523                 if (!(encoder->compute_config(encoder, pipe_config))) {
12524                         DRM_DEBUG_KMS("Encoder config failure\n");
12525                         goto fail;
12526                 }
12527         }
12528
12529         /* Set default port clock if not overwritten by the encoder. Needs to be
12530          * done afterwards in case the encoder adjusts the mode. */
12531         if (!pipe_config->port_clock)
12532                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12533                         * pipe_config->pixel_multiplier;
12534
12535         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12536         if (ret < 0) {
12537                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12538                 goto fail;
12539         }
12540
12541         if (ret == RETRY) {
12542                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12543                         ret = -EINVAL;
12544                         goto fail;
12545                 }
12546
12547                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12548                 retry = false;
12549                 goto encoder_retry;
12550         }
12551
12552         /* Dithering seems to not pass-through bits correctly when it should, so
12553          * only enable it on 6bpc panels. */
12554         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12555         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12556                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12557
12558 fail:
12559         return ret;
12560 }
12561
12562 static void
12563 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12564 {
12565         struct drm_crtc *crtc;
12566         struct drm_crtc_state *crtc_state;
12567         int i;
12568
12569         /* Double check state. */
12570         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12571                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12572
12573                 /* Update hwmode for vblank functions */
12574                 if (crtc->state->active)
12575                         crtc->hwmode = crtc->state->adjusted_mode;
12576                 else
12577                         crtc->hwmode.crtc_clock = 0;
12578
12579                 /*
12580                  * Update legacy state to satisfy fbc code. This can
12581                  * be removed when fbc uses the atomic state.
12582                  */
12583                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12584                         struct drm_plane_state *plane_state = crtc->primary->state;
12585
12586                         crtc->primary->fb = plane_state->fb;
12587                         crtc->x = plane_state->src_x >> 16;
12588                         crtc->y = plane_state->src_y >> 16;
12589                 }
12590         }
12591 }
12592
12593 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12594 {
12595         int diff;
12596
12597         if (clock1 == clock2)
12598                 return true;
12599
12600         if (!clock1 || !clock2)
12601                 return false;
12602
12603         diff = abs(clock1 - clock2);
12604
12605         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12606                 return true;
12607
12608         return false;
12609 }
12610
12611 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12612         list_for_each_entry((intel_crtc), \
12613                             &(dev)->mode_config.crtc_list, \
12614                             base.head) \
12615                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12616
12617 static bool
12618 intel_compare_m_n(unsigned int m, unsigned int n,
12619                   unsigned int m2, unsigned int n2,
12620                   bool exact)
12621 {
12622         if (m == m2 && n == n2)
12623                 return true;
12624
12625         if (exact || !m || !n || !m2 || !n2)
12626                 return false;
12627
12628         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12629
12630         if (n > n2) {
12631                 while (n > n2) {
12632                         m2 <<= 1;
12633                         n2 <<= 1;
12634                 }
12635         } else if (n < n2) {
12636                 while (n < n2) {
12637                         m <<= 1;
12638                         n <<= 1;
12639                 }
12640         }
12641
12642         if (n != n2)
12643                 return false;
12644
12645         return intel_fuzzy_clock_check(m, m2);
12646 }
12647
12648 static bool
12649 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12650                        struct intel_link_m_n *m2_n2,
12651                        bool adjust)
12652 {
12653         if (m_n->tu == m2_n2->tu &&
12654             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12655                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12656             intel_compare_m_n(m_n->link_m, m_n->link_n,
12657                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12658                 if (adjust)
12659                         *m2_n2 = *m_n;
12660
12661                 return true;
12662         }
12663
12664         return false;
12665 }
12666
12667 static bool
12668 intel_pipe_config_compare(struct drm_device *dev,
12669                           struct intel_crtc_state *current_config,
12670                           struct intel_crtc_state *pipe_config,
12671                           bool adjust)
12672 {
12673         bool ret = true;
12674
12675 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12676         do { \
12677                 if (!adjust) \
12678                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12679                 else \
12680                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12681         } while (0)
12682
12683 #define PIPE_CONF_CHECK_X(name) \
12684         if (current_config->name != pipe_config->name) { \
12685                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12686                           "(expected 0x%08x, found 0x%08x)\n", \
12687                           current_config->name, \
12688                           pipe_config->name); \
12689                 ret = false; \
12690         }
12691
12692 #define PIPE_CONF_CHECK_I(name) \
12693         if (current_config->name != pipe_config->name) { \
12694                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12695                           "(expected %i, found %i)\n", \
12696                           current_config->name, \
12697                           pipe_config->name); \
12698                 ret = false; \
12699         }
12700
12701 #define PIPE_CONF_CHECK_M_N(name) \
12702         if (!intel_compare_link_m_n(&current_config->name, \
12703                                     &pipe_config->name,\
12704                                     adjust)) { \
12705                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12706                           "(expected tu %i gmch %i/%i link %i/%i, " \
12707                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12708                           current_config->name.tu, \
12709                           current_config->name.gmch_m, \
12710                           current_config->name.gmch_n, \
12711                           current_config->name.link_m, \
12712                           current_config->name.link_n, \
12713                           pipe_config->name.tu, \
12714                           pipe_config->name.gmch_m, \
12715                           pipe_config->name.gmch_n, \
12716                           pipe_config->name.link_m, \
12717                           pipe_config->name.link_n); \
12718                 ret = false; \
12719         }
12720
12721 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12722         if (!intel_compare_link_m_n(&current_config->name, \
12723                                     &pipe_config->name, adjust) && \
12724             !intel_compare_link_m_n(&current_config->alt_name, \
12725                                     &pipe_config->name, adjust)) { \
12726                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12727                           "(expected tu %i gmch %i/%i link %i/%i, " \
12728                           "or tu %i gmch %i/%i link %i/%i, " \
12729                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12730                           current_config->name.tu, \
12731                           current_config->name.gmch_m, \
12732                           current_config->name.gmch_n, \
12733                           current_config->name.link_m, \
12734                           current_config->name.link_n, \
12735                           current_config->alt_name.tu, \
12736                           current_config->alt_name.gmch_m, \
12737                           current_config->alt_name.gmch_n, \
12738                           current_config->alt_name.link_m, \
12739                           current_config->alt_name.link_n, \
12740                           pipe_config->name.tu, \
12741                           pipe_config->name.gmch_m, \
12742                           pipe_config->name.gmch_n, \
12743                           pipe_config->name.link_m, \
12744                           pipe_config->name.link_n); \
12745                 ret = false; \
12746         }
12747
12748 /* This is required for BDW+ where there is only one set of registers for
12749  * switching between high and low RR.
12750  * This macro can be used whenever a comparison has to be made between one
12751  * hw state and multiple sw state variables.
12752  */
12753 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12754         if ((current_config->name != pipe_config->name) && \
12755                 (current_config->alt_name != pipe_config->name)) { \
12756                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12757                                   "(expected %i or %i, found %i)\n", \
12758                                   current_config->name, \
12759                                   current_config->alt_name, \
12760                                   pipe_config->name); \
12761                         ret = false; \
12762         }
12763
12764 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12765         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12766                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12767                           "(expected %i, found %i)\n", \
12768                           current_config->name & (mask), \
12769                           pipe_config->name & (mask)); \
12770                 ret = false; \
12771         }
12772
12773 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12774         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12775                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12776                           "(expected %i, found %i)\n", \
12777                           current_config->name, \
12778                           pipe_config->name); \
12779                 ret = false; \
12780         }
12781
12782 #define PIPE_CONF_QUIRK(quirk)  \
12783         ((current_config->quirks | pipe_config->quirks) & (quirk))
12784
12785         PIPE_CONF_CHECK_I(cpu_transcoder);
12786
12787         PIPE_CONF_CHECK_I(has_pch_encoder);
12788         PIPE_CONF_CHECK_I(fdi_lanes);
12789         PIPE_CONF_CHECK_M_N(fdi_m_n);
12790
12791         PIPE_CONF_CHECK_I(has_dp_encoder);
12792         PIPE_CONF_CHECK_I(lane_count);
12793
12794         if (INTEL_INFO(dev)->gen < 8) {
12795                 PIPE_CONF_CHECK_M_N(dp_m_n);
12796
12797                 if (current_config->has_drrs)
12798                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12799         } else
12800                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12801
12802         PIPE_CONF_CHECK_I(has_dsi_encoder);
12803
12804         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12805         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12806         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12807         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12808         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12809         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12810
12811         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12812         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12813         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12814         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12815         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12816         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12817
12818         PIPE_CONF_CHECK_I(pixel_multiplier);
12819         PIPE_CONF_CHECK_I(has_hdmi_sink);
12820         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12821             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12822                 PIPE_CONF_CHECK_I(limited_color_range);
12823         PIPE_CONF_CHECK_I(has_infoframe);
12824
12825         PIPE_CONF_CHECK_I(has_audio);
12826
12827         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12828                               DRM_MODE_FLAG_INTERLACE);
12829
12830         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12831                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12832                                       DRM_MODE_FLAG_PHSYNC);
12833                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12834                                       DRM_MODE_FLAG_NHSYNC);
12835                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12836                                       DRM_MODE_FLAG_PVSYNC);
12837                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12838                                       DRM_MODE_FLAG_NVSYNC);
12839         }
12840
12841         PIPE_CONF_CHECK_X(gmch_pfit.control);
12842         /* pfit ratios are autocomputed by the hw on gen4+ */
12843         if (INTEL_INFO(dev)->gen < 4)
12844                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12845         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12846
12847         if (!adjust) {
12848                 PIPE_CONF_CHECK_I(pipe_src_w);
12849                 PIPE_CONF_CHECK_I(pipe_src_h);
12850
12851                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12852                 if (current_config->pch_pfit.enabled) {
12853                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12854                         PIPE_CONF_CHECK_X(pch_pfit.size);
12855                 }
12856
12857                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12858         }
12859
12860         /* BDW+ don't expose a synchronous way to read the state */
12861         if (IS_HASWELL(dev))
12862                 PIPE_CONF_CHECK_I(ips_enabled);
12863
12864         PIPE_CONF_CHECK_I(double_wide);
12865
12866         PIPE_CONF_CHECK_X(ddi_pll_sel);
12867
12868         PIPE_CONF_CHECK_I(shared_dpll);
12869         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12870         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12871         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12872         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12873         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12874         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12875         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12876         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12877         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12878
12879         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12880                 PIPE_CONF_CHECK_I(pipe_bpp);
12881
12882         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12883         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12884
12885 #undef PIPE_CONF_CHECK_X
12886 #undef PIPE_CONF_CHECK_I
12887 #undef PIPE_CONF_CHECK_I_ALT
12888 #undef PIPE_CONF_CHECK_FLAGS
12889 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12890 #undef PIPE_CONF_QUIRK
12891 #undef INTEL_ERR_OR_DBG_KMS
12892
12893         return ret;
12894 }
12895
12896 static void check_wm_state(struct drm_device *dev)
12897 {
12898         struct drm_i915_private *dev_priv = dev->dev_private;
12899         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12900         struct intel_crtc *intel_crtc;
12901         int plane;
12902
12903         if (INTEL_INFO(dev)->gen < 9)
12904                 return;
12905
12906         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12907         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12908
12909         for_each_intel_crtc(dev, intel_crtc) {
12910                 struct skl_ddb_entry *hw_entry, *sw_entry;
12911                 const enum pipe pipe = intel_crtc->pipe;
12912
12913                 if (!intel_crtc->active)
12914                         continue;
12915
12916                 /* planes */
12917                 for_each_plane(dev_priv, pipe, plane) {
12918                         hw_entry = &hw_ddb.plane[pipe][plane];
12919                         sw_entry = &sw_ddb->plane[pipe][plane];
12920
12921                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12922                                 continue;
12923
12924                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12925                                   "(expected (%u,%u), found (%u,%u))\n",
12926                                   pipe_name(pipe), plane + 1,
12927                                   sw_entry->start, sw_entry->end,
12928                                   hw_entry->start, hw_entry->end);
12929                 }
12930
12931                 /* cursor */
12932                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12933                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12934
12935                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12936                         continue;
12937
12938                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12939                           "(expected (%u,%u), found (%u,%u))\n",
12940                           pipe_name(pipe),
12941                           sw_entry->start, sw_entry->end,
12942                           hw_entry->start, hw_entry->end);
12943         }
12944 }
12945
12946 static void
12947 check_connector_state(struct drm_device *dev,
12948                       struct drm_atomic_state *old_state)
12949 {
12950         struct drm_connector_state *old_conn_state;
12951         struct drm_connector *connector;
12952         int i;
12953
12954         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12955                 struct drm_encoder *encoder = connector->encoder;
12956                 struct drm_connector_state *state = connector->state;
12957
12958                 /* This also checks the encoder/connector hw state with the
12959                  * ->get_hw_state callbacks. */
12960                 intel_connector_check_state(to_intel_connector(connector));
12961
12962                 I915_STATE_WARN(state->best_encoder != encoder,
12963                      "connector's atomic encoder doesn't match legacy encoder\n");
12964         }
12965 }
12966
12967 static void
12968 check_encoder_state(struct drm_device *dev)
12969 {
12970         struct intel_encoder *encoder;
12971         struct intel_connector *connector;
12972
12973         for_each_intel_encoder(dev, encoder) {
12974                 bool enabled = false;
12975                 enum pipe pipe;
12976
12977                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12978                               encoder->base.base.id,
12979                               encoder->base.name);
12980
12981                 for_each_intel_connector(dev, connector) {
12982                         if (connector->base.state->best_encoder != &encoder->base)
12983                                 continue;
12984                         enabled = true;
12985
12986                         I915_STATE_WARN(connector->base.state->crtc !=
12987                                         encoder->base.crtc,
12988                              "connector's crtc doesn't match encoder crtc\n");
12989                 }
12990
12991                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12992                      "encoder's enabled state mismatch "
12993                      "(expected %i, found %i)\n",
12994                      !!encoder->base.crtc, enabled);
12995
12996                 if (!encoder->base.crtc) {
12997                         bool active;
12998
12999                         active = encoder->get_hw_state(encoder, &pipe);
13000                         I915_STATE_WARN(active,
13001                              "encoder detached but still enabled on pipe %c.\n",
13002                              pipe_name(pipe));
13003                 }
13004         }
13005 }
13006
13007 static void
13008 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
13009 {
13010         struct drm_i915_private *dev_priv = dev->dev_private;
13011         struct intel_encoder *encoder;
13012         struct drm_crtc_state *old_crtc_state;
13013         struct drm_crtc *crtc;
13014         int i;
13015
13016         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
13017                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13018                 struct intel_crtc_state *pipe_config, *sw_config;
13019                 bool active;
13020
13021                 if (!needs_modeset(crtc->state) &&
13022                     !to_intel_crtc_state(crtc->state)->update_pipe)
13023                         continue;
13024
13025                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
13026                 pipe_config = to_intel_crtc_state(old_crtc_state);
13027                 memset(pipe_config, 0, sizeof(*pipe_config));
13028                 pipe_config->base.crtc = crtc;
13029                 pipe_config->base.state = old_state;
13030
13031                 DRM_DEBUG_KMS("[CRTC:%d]\n",
13032                               crtc->base.id);
13033
13034                 active = dev_priv->display.get_pipe_config(intel_crtc,
13035                                                            pipe_config);
13036
13037                 /* hw state is inconsistent with the pipe quirk */
13038                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13039                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13040                         active = crtc->state->active;
13041
13042                 I915_STATE_WARN(crtc->state->active != active,
13043                      "crtc active state doesn't match with hw state "
13044                      "(expected %i, found %i)\n", crtc->state->active, active);
13045
13046                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
13047                      "transitional active state does not match atomic hw state "
13048                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
13049
13050                 for_each_encoder_on_crtc(dev, crtc, encoder) {
13051                         enum pipe pipe;
13052
13053                         active = encoder->get_hw_state(encoder, &pipe);
13054                         I915_STATE_WARN(active != crtc->state->active,
13055                                 "[ENCODER:%i] active %i with crtc active %i\n",
13056                                 encoder->base.base.id, active, crtc->state->active);
13057
13058                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13059                                         "Encoder connected to wrong pipe %c\n",
13060                                         pipe_name(pipe));
13061
13062                         if (active)
13063                                 encoder->get_config(encoder, pipe_config);
13064                 }
13065
13066                 if (!crtc->state->active)
13067                         continue;
13068
13069                 sw_config = to_intel_crtc_state(crtc->state);
13070                 if (!intel_pipe_config_compare(dev, sw_config,
13071                                                pipe_config, false)) {
13072                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
13073                         intel_dump_pipe_config(intel_crtc, pipe_config,
13074                                                "[hw state]");
13075                         intel_dump_pipe_config(intel_crtc, sw_config,
13076                                                "[sw state]");
13077                 }
13078         }
13079 }
13080
13081 static void
13082 check_shared_dpll_state(struct drm_device *dev)
13083 {
13084         struct drm_i915_private *dev_priv = dev->dev_private;
13085         struct intel_crtc *crtc;
13086         struct intel_dpll_hw_state dpll_hw_state;
13087         int i;
13088
13089         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13090                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13091                 int enabled_crtcs = 0, active_crtcs = 0;
13092                 bool active;
13093
13094                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13095
13096                 DRM_DEBUG_KMS("%s\n", pll->name);
13097
13098                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13099
13100                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13101                      "more active pll users than references: %i vs %i\n",
13102                      pll->active, hweight32(pll->config.crtc_mask));
13103                 I915_STATE_WARN(pll->active && !pll->on,
13104                      "pll in active use but not on in sw tracking\n");
13105                 I915_STATE_WARN(pll->on && !pll->active,
13106                      "pll in on but not on in use in sw tracking\n");
13107                 I915_STATE_WARN(pll->on != active,
13108                      "pll on state mismatch (expected %i, found %i)\n",
13109                      pll->on, active);
13110
13111                 for_each_intel_crtc(dev, crtc) {
13112                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13113                                 enabled_crtcs++;
13114                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13115                                 active_crtcs++;
13116                 }
13117                 I915_STATE_WARN(pll->active != active_crtcs,
13118                      "pll active crtcs mismatch (expected %i, found %i)\n",
13119                      pll->active, active_crtcs);
13120                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13121                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
13122                      hweight32(pll->config.crtc_mask), enabled_crtcs);
13123
13124                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13125                                        sizeof(dpll_hw_state)),
13126                      "pll hw state mismatch\n");
13127         }
13128 }
13129
13130 static void
13131 intel_modeset_check_state(struct drm_device *dev,
13132                           struct drm_atomic_state *old_state)
13133 {
13134         check_wm_state(dev);
13135         check_connector_state(dev, old_state);
13136         check_encoder_state(dev);
13137         check_crtc_state(dev, old_state);
13138         check_shared_dpll_state(dev);
13139 }
13140
13141 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13142                                      int dotclock)
13143 {
13144         /*
13145          * FDI already provided one idea for the dotclock.
13146          * Yell if the encoder disagrees.
13147          */
13148         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13149              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13150              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13151 }
13152
13153 static void update_scanline_offset(struct intel_crtc *crtc)
13154 {
13155         struct drm_device *dev = crtc->base.dev;
13156
13157         /*
13158          * The scanline counter increments at the leading edge of hsync.
13159          *
13160          * On most platforms it starts counting from vtotal-1 on the
13161          * first active line. That means the scanline counter value is
13162          * always one less than what we would expect. Ie. just after
13163          * start of vblank, which also occurs at start of hsync (on the
13164          * last active line), the scanline counter will read vblank_start-1.
13165          *
13166          * On gen2 the scanline counter starts counting from 1 instead
13167          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13168          * to keep the value positive), instead of adding one.
13169          *
13170          * On HSW+ the behaviour of the scanline counter depends on the output
13171          * type. For DP ports it behaves like most other platforms, but on HDMI
13172          * there's an extra 1 line difference. So we need to add two instead of
13173          * one to the value.
13174          */
13175         if (IS_GEN2(dev)) {
13176                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13177                 int vtotal;
13178
13179                 vtotal = adjusted_mode->crtc_vtotal;
13180                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13181                         vtotal /= 2;
13182
13183                 crtc->scanline_offset = vtotal - 1;
13184         } else if (HAS_DDI(dev) &&
13185                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13186                 crtc->scanline_offset = 2;
13187         } else
13188                 crtc->scanline_offset = 1;
13189 }
13190
13191 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13192 {
13193         struct drm_device *dev = state->dev;
13194         struct drm_i915_private *dev_priv = to_i915(dev);
13195         struct intel_shared_dpll_config *shared_dpll = NULL;
13196         struct intel_crtc *intel_crtc;
13197         struct intel_crtc_state *intel_crtc_state;
13198         struct drm_crtc *crtc;
13199         struct drm_crtc_state *crtc_state;
13200         int i;
13201
13202         if (!dev_priv->display.crtc_compute_clock)
13203                 return;
13204
13205         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13206                 int dpll;
13207
13208                 intel_crtc = to_intel_crtc(crtc);
13209                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13210                 dpll = intel_crtc_state->shared_dpll;
13211
13212                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13213                         continue;
13214
13215                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13216
13217                 if (!shared_dpll)
13218                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13219
13220                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13221         }
13222 }
13223
13224 /*
13225  * This implements the workaround described in the "notes" section of the mode
13226  * set sequence documentation. When going from no pipes or single pipe to
13227  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13228  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13229  */
13230 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13231 {
13232         struct drm_crtc_state *crtc_state;
13233         struct intel_crtc *intel_crtc;
13234         struct drm_crtc *crtc;
13235         struct intel_crtc_state *first_crtc_state = NULL;
13236         struct intel_crtc_state *other_crtc_state = NULL;
13237         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13238         int i;
13239
13240         /* look at all crtc's that are going to be enabled in during modeset */
13241         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13242                 intel_crtc = to_intel_crtc(crtc);
13243
13244                 if (!crtc_state->active || !needs_modeset(crtc_state))
13245                         continue;
13246
13247                 if (first_crtc_state) {
13248                         other_crtc_state = to_intel_crtc_state(crtc_state);
13249                         break;
13250                 } else {
13251                         first_crtc_state = to_intel_crtc_state(crtc_state);
13252                         first_pipe = intel_crtc->pipe;
13253                 }
13254         }
13255
13256         /* No workaround needed? */
13257         if (!first_crtc_state)
13258                 return 0;
13259
13260         /* w/a possibly needed, check how many crtc's are already enabled. */
13261         for_each_intel_crtc(state->dev, intel_crtc) {
13262                 struct intel_crtc_state *pipe_config;
13263
13264                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13265                 if (IS_ERR(pipe_config))
13266                         return PTR_ERR(pipe_config);
13267
13268                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13269
13270                 if (!pipe_config->base.active ||
13271                     needs_modeset(&pipe_config->base))
13272                         continue;
13273
13274                 /* 2 or more enabled crtcs means no need for w/a */
13275                 if (enabled_pipe != INVALID_PIPE)
13276                         return 0;
13277
13278                 enabled_pipe = intel_crtc->pipe;
13279         }
13280
13281         if (enabled_pipe != INVALID_PIPE)
13282                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13283         else if (other_crtc_state)
13284                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13285
13286         return 0;
13287 }
13288
13289 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13290 {
13291         struct drm_crtc *crtc;
13292         struct drm_crtc_state *crtc_state;
13293         int ret = 0;
13294
13295         /* add all active pipes to the state */
13296         for_each_crtc(state->dev, crtc) {
13297                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13298                 if (IS_ERR(crtc_state))
13299                         return PTR_ERR(crtc_state);
13300
13301                 if (!crtc_state->active || needs_modeset(crtc_state))
13302                         continue;
13303
13304                 crtc_state->mode_changed = true;
13305
13306                 ret = drm_atomic_add_affected_connectors(state, crtc);
13307                 if (ret)
13308                         break;
13309
13310                 ret = drm_atomic_add_affected_planes(state, crtc);
13311                 if (ret)
13312                         break;
13313         }
13314
13315         return ret;
13316 }
13317
13318 static int intel_modeset_checks(struct drm_atomic_state *state)
13319 {
13320         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13321         struct drm_i915_private *dev_priv = state->dev->dev_private;
13322         struct drm_crtc *crtc;
13323         struct drm_crtc_state *crtc_state;
13324         int ret = 0, i;
13325
13326         if (!check_digital_port_conflicts(state)) {
13327                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13328                 return -EINVAL;
13329         }
13330
13331         intel_state->modeset = true;
13332         intel_state->active_crtcs = dev_priv->active_crtcs;
13333
13334         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13335                 if (crtc_state->active)
13336                         intel_state->active_crtcs |= 1 << i;
13337                 else
13338                         intel_state->active_crtcs &= ~(1 << i);
13339         }
13340
13341         /*
13342          * See if the config requires any additional preparation, e.g.
13343          * to adjust global state with pipes off.  We need to do this
13344          * here so we can get the modeset_pipe updated config for the new
13345          * mode set on this crtc.  For other crtcs we need to use the
13346          * adjusted_mode bits in the crtc directly.
13347          */
13348         if (dev_priv->display.modeset_calc_cdclk) {
13349                 ret = dev_priv->display.modeset_calc_cdclk(state);
13350
13351                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13352                         ret = intel_modeset_all_pipes(state);
13353
13354                 if (ret < 0)
13355                         return ret;
13356         } else
13357                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13358
13359         intel_modeset_clear_plls(state);
13360
13361         if (IS_HASWELL(dev_priv))
13362                 return haswell_mode_set_planes_workaround(state);
13363
13364         return 0;
13365 }
13366
13367 /*
13368  * Handle calculation of various watermark data at the end of the atomic check
13369  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13370  * handlers to ensure that all derived state has been updated.
13371  */
13372 static void calc_watermark_data(struct drm_atomic_state *state)
13373 {
13374         struct drm_device *dev = state->dev;
13375         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13376         struct drm_crtc *crtc;
13377         struct drm_crtc_state *cstate;
13378         struct drm_plane *plane;
13379         struct drm_plane_state *pstate;
13380
13381         /*
13382          * Calculate watermark configuration details now that derived
13383          * plane/crtc state is all properly updated.
13384          */
13385         drm_for_each_crtc(crtc, dev) {
13386                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13387                         crtc->state;
13388
13389                 if (cstate->active)
13390                         intel_state->wm_config.num_pipes_active++;
13391         }
13392         drm_for_each_legacy_plane(plane, dev) {
13393                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13394                         plane->state;
13395
13396                 if (!to_intel_plane_state(pstate)->visible)
13397                         continue;
13398
13399                 intel_state->wm_config.sprites_enabled = true;
13400                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13401                     pstate->crtc_h != pstate->src_h >> 16)
13402                         intel_state->wm_config.sprites_scaled = true;
13403         }
13404 }
13405
13406 /**
13407  * intel_atomic_check - validate state object
13408  * @dev: drm device
13409  * @state: state to validate
13410  */
13411 static int intel_atomic_check(struct drm_device *dev,
13412                               struct drm_atomic_state *state)
13413 {
13414         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13415         struct drm_crtc *crtc;
13416         struct drm_crtc_state *crtc_state;
13417         int ret, i;
13418         bool any_ms = false;
13419
13420         ret = drm_atomic_helper_check_modeset(dev, state);
13421         if (ret)
13422                 return ret;
13423
13424         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13425                 struct intel_crtc_state *pipe_config =
13426                         to_intel_crtc_state(crtc_state);
13427
13428                 memset(&to_intel_crtc(crtc)->atomic, 0,
13429                        sizeof(struct intel_crtc_atomic_commit));
13430
13431                 /* Catch I915_MODE_FLAG_INHERITED */
13432                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13433                         crtc_state->mode_changed = true;
13434
13435                 if (!crtc_state->enable) {
13436                         if (needs_modeset(crtc_state))
13437                                 any_ms = true;
13438                         continue;
13439                 }
13440
13441                 if (!needs_modeset(crtc_state))
13442                         continue;
13443
13444                 /* FIXME: For only active_changed we shouldn't need to do any
13445                  * state recomputation at all. */
13446
13447                 ret = drm_atomic_add_affected_connectors(state, crtc);
13448                 if (ret)
13449                         return ret;
13450
13451                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13452                 if (ret)
13453                         return ret;
13454
13455                 if (i915.fastboot &&
13456                     intel_pipe_config_compare(state->dev,
13457                                         to_intel_crtc_state(crtc->state),
13458                                         pipe_config, true)) {
13459                         crtc_state->mode_changed = false;
13460                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13461                 }
13462
13463                 if (needs_modeset(crtc_state)) {
13464                         any_ms = true;
13465
13466                         ret = drm_atomic_add_affected_planes(state, crtc);
13467                         if (ret)
13468                                 return ret;
13469                 }
13470
13471                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13472                                        needs_modeset(crtc_state) ?
13473                                        "[modeset]" : "[fastset]");
13474         }
13475
13476         if (any_ms) {
13477                 ret = intel_modeset_checks(state);
13478
13479                 if (ret)
13480                         return ret;
13481         } else
13482                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13483
13484         ret = drm_atomic_helper_check_planes(state->dev, state);
13485         if (ret)
13486                 return ret;
13487
13488         calc_watermark_data(state);
13489
13490         return 0;
13491 }
13492
13493 static int intel_atomic_prepare_commit(struct drm_device *dev,
13494                                        struct drm_atomic_state *state,
13495                                        bool async)
13496 {
13497         struct drm_i915_private *dev_priv = dev->dev_private;
13498         struct drm_plane_state *plane_state;
13499         struct drm_crtc_state *crtc_state;
13500         struct drm_plane *plane;
13501         struct drm_crtc *crtc;
13502         int i, ret;
13503
13504         if (async) {
13505                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13506                 return -EINVAL;
13507         }
13508
13509         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13510                 ret = intel_crtc_wait_for_pending_flips(crtc);
13511                 if (ret)
13512                         return ret;
13513
13514                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13515                         flush_workqueue(dev_priv->wq);
13516         }
13517
13518         ret = mutex_lock_interruptible(&dev->struct_mutex);
13519         if (ret)
13520                 return ret;
13521
13522         ret = drm_atomic_helper_prepare_planes(dev, state);
13523         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13524                 u32 reset_counter;
13525
13526                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13527                 mutex_unlock(&dev->struct_mutex);
13528
13529                 for_each_plane_in_state(state, plane, plane_state, i) {
13530                         struct intel_plane_state *intel_plane_state =
13531                                 to_intel_plane_state(plane_state);
13532
13533                         if (!intel_plane_state->wait_req)
13534                                 continue;
13535
13536                         ret = __i915_wait_request(intel_plane_state->wait_req,
13537                                                   reset_counter, true,
13538                                                   NULL, NULL);
13539
13540                         /* Swallow -EIO errors to allow updates during hw lockup. */
13541                         if (ret == -EIO)
13542                                 ret = 0;
13543
13544                         if (ret)
13545                                 break;
13546                 }
13547
13548                 if (!ret)
13549                         return 0;
13550
13551                 mutex_lock(&dev->struct_mutex);
13552                 drm_atomic_helper_cleanup_planes(dev, state);
13553         }
13554
13555         mutex_unlock(&dev->struct_mutex);
13556         return ret;
13557 }
13558
13559 /**
13560  * intel_atomic_commit - commit validated state object
13561  * @dev: DRM device
13562  * @state: the top-level driver state object
13563  * @async: asynchronous commit
13564  *
13565  * This function commits a top-level state object that has been validated
13566  * with drm_atomic_helper_check().
13567  *
13568  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13569  * we can only handle plane-related operations and do not yet support
13570  * asynchronous commit.
13571  *
13572  * RETURNS
13573  * Zero for success or -errno.
13574  */
13575 static int intel_atomic_commit(struct drm_device *dev,
13576                                struct drm_atomic_state *state,
13577                                bool async)
13578 {
13579         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13580         struct drm_i915_private *dev_priv = dev->dev_private;
13581         struct drm_crtc_state *crtc_state;
13582         struct drm_crtc *crtc;
13583         struct intel_crtc_state *intel_cstate;
13584         int ret = 0, i;
13585         bool hw_check = intel_state->modeset;
13586
13587         ret = intel_atomic_prepare_commit(dev, state, async);
13588         if (ret) {
13589                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13590                 return ret;
13591         }
13592
13593         drm_atomic_helper_swap_state(dev, state);
13594         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13595
13596         if (intel_state->modeset) {
13597                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13598                        sizeof(intel_state->min_pixclk));
13599                 dev_priv->active_crtcs = intel_state->active_crtcs;
13600                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13601         }
13602
13603         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13604                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13605
13606                 if (!needs_modeset(crtc->state))
13607                         continue;
13608
13609                 intel_pre_plane_update(intel_crtc);
13610
13611                 if (crtc_state->active) {
13612                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13613                         dev_priv->display.crtc_disable(crtc);
13614                         intel_crtc->active = false;
13615                         intel_disable_shared_dpll(intel_crtc);
13616
13617                         /*
13618                          * Underruns don't always raise
13619                          * interrupts, so check manually.
13620                          */
13621                         intel_check_cpu_fifo_underruns(dev_priv);
13622                         intel_check_pch_fifo_underruns(dev_priv);
13623
13624                         if (!crtc->state->active)
13625                                 intel_update_watermarks(crtc);
13626                 }
13627         }
13628
13629         /* Only after disabling all output pipelines that will be changed can we
13630          * update the the output configuration. */
13631         intel_modeset_update_crtc_state(state);
13632
13633         if (intel_state->modeset) {
13634                 intel_shared_dpll_commit(state);
13635
13636                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13637                 modeset_update_crtc_power_domains(state);
13638         }
13639
13640         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13641         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13642                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13643                 bool modeset = needs_modeset(crtc->state);
13644                 bool update_pipe = !modeset &&
13645                         to_intel_crtc_state(crtc->state)->update_pipe;
13646                 unsigned long put_domains = 0;
13647
13648                 if (modeset)
13649                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13650
13651                 if (modeset && crtc->state->active) {
13652                         update_scanline_offset(to_intel_crtc(crtc));
13653                         dev_priv->display.crtc_enable(crtc);
13654                 }
13655
13656                 if (update_pipe) {
13657                         put_domains = modeset_get_crtc_power_domains(crtc);
13658
13659                         /* make sure intel_modeset_check_state runs */
13660                         hw_check = true;
13661                 }
13662
13663                 if (!modeset)
13664                         intel_pre_plane_update(intel_crtc);
13665
13666                 if (crtc->state->active &&
13667                     (crtc->state->planes_changed || update_pipe))
13668                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13669
13670                 if (put_domains)
13671                         modeset_put_power_domains(dev_priv, put_domains);
13672
13673                 intel_post_plane_update(intel_crtc);
13674
13675                 if (modeset)
13676                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13677         }
13678
13679         /* FIXME: add subpixel order */
13680
13681         drm_atomic_helper_wait_for_vblanks(dev, state);
13682
13683         /*
13684          * Now that the vblank has passed, we can go ahead and program the
13685          * optimal watermarks on platforms that need two-step watermark
13686          * programming.
13687          *
13688          * TODO: Move this (and other cleanup) to an async worker eventually.
13689          */
13690         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13691                 intel_cstate = to_intel_crtc_state(crtc->state);
13692
13693                 if (dev_priv->display.optimize_watermarks)
13694                         dev_priv->display.optimize_watermarks(intel_cstate);
13695         }
13696
13697         mutex_lock(&dev->struct_mutex);
13698         drm_atomic_helper_cleanup_planes(dev, state);
13699         mutex_unlock(&dev->struct_mutex);
13700
13701         if (hw_check)
13702                 intel_modeset_check_state(dev, state);
13703
13704         drm_atomic_state_free(state);
13705
13706         return 0;
13707 }
13708
13709 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13710 {
13711         struct drm_device *dev = crtc->dev;
13712         struct drm_atomic_state *state;
13713         struct drm_crtc_state *crtc_state;
13714         int ret;
13715
13716         state = drm_atomic_state_alloc(dev);
13717         if (!state) {
13718                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13719                               crtc->base.id);
13720                 return;
13721         }
13722
13723         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13724
13725 retry:
13726         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13727         ret = PTR_ERR_OR_ZERO(crtc_state);
13728         if (!ret) {
13729                 if (!crtc_state->active)
13730                         goto out;
13731
13732                 crtc_state->mode_changed = true;
13733                 ret = drm_atomic_commit(state);
13734         }
13735
13736         if (ret == -EDEADLK) {
13737                 drm_atomic_state_clear(state);
13738                 drm_modeset_backoff(state->acquire_ctx);
13739                 goto retry;
13740         }
13741
13742         if (ret)
13743 out:
13744                 drm_atomic_state_free(state);
13745 }
13746
13747 #undef for_each_intel_crtc_masked
13748
13749 static const struct drm_crtc_funcs intel_crtc_funcs = {
13750         .gamma_set = intel_crtc_gamma_set,
13751         .set_config = drm_atomic_helper_set_config,
13752         .destroy = intel_crtc_destroy,
13753         .page_flip = intel_crtc_page_flip,
13754         .atomic_duplicate_state = intel_crtc_duplicate_state,
13755         .atomic_destroy_state = intel_crtc_destroy_state,
13756 };
13757
13758 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13759                                       struct intel_shared_dpll *pll,
13760                                       struct intel_dpll_hw_state *hw_state)
13761 {
13762         uint32_t val;
13763
13764         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13765                 return false;
13766
13767         val = I915_READ(PCH_DPLL(pll->id));
13768         hw_state->dpll = val;
13769         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13770         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13771
13772         return val & DPLL_VCO_ENABLE;
13773 }
13774
13775 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13776                                   struct intel_shared_dpll *pll)
13777 {
13778         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13779         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13780 }
13781
13782 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13783                                 struct intel_shared_dpll *pll)
13784 {
13785         /* PCH refclock must be enabled first */
13786         ibx_assert_pch_refclk_enabled(dev_priv);
13787
13788         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13789
13790         /* Wait for the clocks to stabilize. */
13791         POSTING_READ(PCH_DPLL(pll->id));
13792         udelay(150);
13793
13794         /* The pixel multiplier can only be updated once the
13795          * DPLL is enabled and the clocks are stable.
13796          *
13797          * So write it again.
13798          */
13799         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13800         POSTING_READ(PCH_DPLL(pll->id));
13801         udelay(200);
13802 }
13803
13804 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13805                                  struct intel_shared_dpll *pll)
13806 {
13807         struct drm_device *dev = dev_priv->dev;
13808         struct intel_crtc *crtc;
13809
13810         /* Make sure no transcoder isn't still depending on us. */
13811         for_each_intel_crtc(dev, crtc) {
13812                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13813                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13814         }
13815
13816         I915_WRITE(PCH_DPLL(pll->id), 0);
13817         POSTING_READ(PCH_DPLL(pll->id));
13818         udelay(200);
13819 }
13820
13821 static char *ibx_pch_dpll_names[] = {
13822         "PCH DPLL A",
13823         "PCH DPLL B",
13824 };
13825
13826 static void ibx_pch_dpll_init(struct drm_device *dev)
13827 {
13828         struct drm_i915_private *dev_priv = dev->dev_private;
13829         int i;
13830
13831         dev_priv->num_shared_dpll = 2;
13832
13833         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13834                 dev_priv->shared_dplls[i].id = i;
13835                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13836                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13837                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13838                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13839                 dev_priv->shared_dplls[i].get_hw_state =
13840                         ibx_pch_dpll_get_hw_state;
13841         }
13842 }
13843
13844 static void intel_shared_dpll_init(struct drm_device *dev)
13845 {
13846         struct drm_i915_private *dev_priv = dev->dev_private;
13847
13848         if (HAS_DDI(dev))
13849                 intel_ddi_pll_init(dev);
13850         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13851                 ibx_pch_dpll_init(dev);
13852         else
13853                 dev_priv->num_shared_dpll = 0;
13854
13855         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13856 }
13857
13858 /**
13859  * intel_prepare_plane_fb - Prepare fb for usage on plane
13860  * @plane: drm plane to prepare for
13861  * @fb: framebuffer to prepare for presentation
13862  *
13863  * Prepares a framebuffer for usage on a display plane.  Generally this
13864  * involves pinning the underlying object and updating the frontbuffer tracking
13865  * bits.  Some older platforms need special physical address handling for
13866  * cursor planes.
13867  *
13868  * Must be called with struct_mutex held.
13869  *
13870  * Returns 0 on success, negative error code on failure.
13871  */
13872 int
13873 intel_prepare_plane_fb(struct drm_plane *plane,
13874                        const struct drm_plane_state *new_state)
13875 {
13876         struct drm_device *dev = plane->dev;
13877         struct drm_framebuffer *fb = new_state->fb;
13878         struct intel_plane *intel_plane = to_intel_plane(plane);
13879         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13880         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13881         int ret = 0;
13882
13883         if (!obj && !old_obj)
13884                 return 0;
13885
13886         if (old_obj) {
13887                 struct drm_crtc_state *crtc_state =
13888                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13889
13890                 /* Big Hammer, we also need to ensure that any pending
13891                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13892                  * current scanout is retired before unpinning the old
13893                  * framebuffer. Note that we rely on userspace rendering
13894                  * into the buffer attached to the pipe they are waiting
13895                  * on. If not, userspace generates a GPU hang with IPEHR
13896                  * point to the MI_WAIT_FOR_EVENT.
13897                  *
13898                  * This should only fail upon a hung GPU, in which case we
13899                  * can safely continue.
13900                  */
13901                 if (needs_modeset(crtc_state))
13902                         ret = i915_gem_object_wait_rendering(old_obj, true);
13903
13904                 /* Swallow -EIO errors to allow updates during hw lockup. */
13905                 if (ret && ret != -EIO)
13906                         return ret;
13907         }
13908
13909         /* For framebuffer backed by dmabuf, wait for fence */
13910         if (obj && obj->base.dma_buf) {
13911                 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13912                                                           false, true,
13913                                                           MAX_SCHEDULE_TIMEOUT);
13914                 if (ret == -ERESTARTSYS)
13915                         return ret;
13916
13917                 WARN_ON(ret < 0);
13918         }
13919
13920         if (!obj) {
13921                 ret = 0;
13922         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13923             INTEL_INFO(dev)->cursor_needs_physical) {
13924                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13925                 ret = i915_gem_object_attach_phys(obj, align);
13926                 if (ret)
13927                         DRM_DEBUG_KMS("failed to attach phys object\n");
13928         } else {
13929                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13930         }
13931
13932         if (ret == 0) {
13933                 if (obj) {
13934                         struct intel_plane_state *plane_state =
13935                                 to_intel_plane_state(new_state);
13936
13937                         i915_gem_request_assign(&plane_state->wait_req,
13938                                                 obj->last_write_req);
13939                 }
13940
13941                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13942         }
13943
13944         return ret;
13945 }
13946
13947 /**
13948  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13949  * @plane: drm plane to clean up for
13950  * @fb: old framebuffer that was on plane
13951  *
13952  * Cleans up a framebuffer that has just been removed from a plane.
13953  *
13954  * Must be called with struct_mutex held.
13955  */
13956 void
13957 intel_cleanup_plane_fb(struct drm_plane *plane,
13958                        const struct drm_plane_state *old_state)
13959 {
13960         struct drm_device *dev = plane->dev;
13961         struct intel_plane *intel_plane = to_intel_plane(plane);
13962         struct intel_plane_state *old_intel_state;
13963         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13964         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13965
13966         old_intel_state = to_intel_plane_state(old_state);
13967
13968         if (!obj && !old_obj)
13969                 return;
13970
13971         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13972             !INTEL_INFO(dev)->cursor_needs_physical))
13973                 intel_unpin_fb_obj(old_state->fb, old_state);
13974
13975         /* prepare_fb aborted? */
13976         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13977             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13978                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13979
13980         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13981
13982 }
13983
13984 int
13985 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13986 {
13987         int max_scale;
13988         struct drm_device *dev;
13989         struct drm_i915_private *dev_priv;
13990         int crtc_clock, cdclk;
13991
13992         if (!intel_crtc || !crtc_state->base.enable)
13993                 return DRM_PLANE_HELPER_NO_SCALING;
13994
13995         dev = intel_crtc->base.dev;
13996         dev_priv = dev->dev_private;
13997         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13998         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13999
14000         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14001                 return DRM_PLANE_HELPER_NO_SCALING;
14002
14003         /*
14004          * skl max scale is lower of:
14005          *    close to 3 but not 3, -1 is for that purpose
14006          *            or
14007          *    cdclk/crtc_clock
14008          */
14009         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14010
14011         return max_scale;
14012 }
14013
14014 static int
14015 intel_check_primary_plane(struct drm_plane *plane,
14016                           struct intel_crtc_state *crtc_state,
14017                           struct intel_plane_state *state)
14018 {
14019         struct drm_crtc *crtc = state->base.crtc;
14020         struct drm_framebuffer *fb = state->base.fb;
14021         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14022         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14023         bool can_position = false;
14024
14025         /* use scaler when colorkey is not required */
14026         if (INTEL_INFO(plane->dev)->gen >= 9 &&
14027             state->ckey.flags == I915_SET_COLORKEY_NONE) {
14028                 min_scale = 1;
14029                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14030                 can_position = true;
14031         }
14032
14033         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14034                                              &state->dst, &state->clip,
14035                                              min_scale, max_scale,
14036                                              can_position, true,
14037                                              &state->visible);
14038 }
14039
14040 static void
14041 intel_commit_primary_plane(struct drm_plane *plane,
14042                            struct intel_plane_state *state)
14043 {
14044         struct drm_crtc *crtc = state->base.crtc;
14045         struct drm_framebuffer *fb = state->base.fb;
14046         struct drm_device *dev = plane->dev;
14047         struct drm_i915_private *dev_priv = dev->dev_private;
14048
14049         crtc = crtc ? crtc : plane->crtc;
14050
14051         dev_priv->display.update_primary_plane(crtc, fb,
14052                                                state->src.x1 >> 16,
14053                                                state->src.y1 >> 16);
14054 }
14055
14056 static void
14057 intel_disable_primary_plane(struct drm_plane *plane,
14058                             struct drm_crtc *crtc)
14059 {
14060         struct drm_device *dev = plane->dev;
14061         struct drm_i915_private *dev_priv = dev->dev_private;
14062
14063         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
14064 }
14065
14066 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14067                                     struct drm_crtc_state *old_crtc_state)
14068 {
14069         struct drm_device *dev = crtc->dev;
14070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14071         struct intel_crtc_state *old_intel_state =
14072                 to_intel_crtc_state(old_crtc_state);
14073         bool modeset = needs_modeset(crtc->state);
14074
14075         /* Perform vblank evasion around commit operation */
14076         intel_pipe_update_start(intel_crtc);
14077
14078         if (modeset)
14079                 return;
14080
14081         if (to_intel_crtc_state(crtc->state)->update_pipe)
14082                 intel_update_pipe_config(intel_crtc, old_intel_state);
14083         else if (INTEL_INFO(dev)->gen >= 9)
14084                 skl_detach_scalers(intel_crtc);
14085 }
14086
14087 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14088                                      struct drm_crtc_state *old_crtc_state)
14089 {
14090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14091
14092         intel_pipe_update_end(intel_crtc);
14093 }
14094
14095 /**
14096  * intel_plane_destroy - destroy a plane
14097  * @plane: plane to destroy
14098  *
14099  * Common destruction function for all types of planes (primary, cursor,
14100  * sprite).
14101  */
14102 void intel_plane_destroy(struct drm_plane *plane)
14103 {
14104         struct intel_plane *intel_plane = to_intel_plane(plane);
14105         drm_plane_cleanup(plane);
14106         kfree(intel_plane);
14107 }
14108
14109 const struct drm_plane_funcs intel_plane_funcs = {
14110         .update_plane = drm_atomic_helper_update_plane,
14111         .disable_plane = drm_atomic_helper_disable_plane,
14112         .destroy = intel_plane_destroy,
14113         .set_property = drm_atomic_helper_plane_set_property,
14114         .atomic_get_property = intel_plane_atomic_get_property,
14115         .atomic_set_property = intel_plane_atomic_set_property,
14116         .atomic_duplicate_state = intel_plane_duplicate_state,
14117         .atomic_destroy_state = intel_plane_destroy_state,
14118
14119 };
14120
14121 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14122                                                     int pipe)
14123 {
14124         struct intel_plane *primary;
14125         struct intel_plane_state *state;
14126         const uint32_t *intel_primary_formats;
14127         unsigned int num_formats;
14128
14129         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14130         if (primary == NULL)
14131                 return NULL;
14132
14133         state = intel_create_plane_state(&primary->base);
14134         if (!state) {
14135                 kfree(primary);
14136                 return NULL;
14137         }
14138         primary->base.state = &state->base;
14139
14140         primary->can_scale = false;
14141         primary->max_downscale = 1;
14142         if (INTEL_INFO(dev)->gen >= 9) {
14143                 primary->can_scale = true;
14144                 state->scaler_id = -1;
14145         }
14146         primary->pipe = pipe;
14147         primary->plane = pipe;
14148         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14149         primary->check_plane = intel_check_primary_plane;
14150         primary->commit_plane = intel_commit_primary_plane;
14151         primary->disable_plane = intel_disable_primary_plane;
14152         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14153                 primary->plane = !pipe;
14154
14155         if (INTEL_INFO(dev)->gen >= 9) {
14156                 intel_primary_formats = skl_primary_formats;
14157                 num_formats = ARRAY_SIZE(skl_primary_formats);
14158         } else if (INTEL_INFO(dev)->gen >= 4) {
14159                 intel_primary_formats = i965_primary_formats;
14160                 num_formats = ARRAY_SIZE(i965_primary_formats);
14161         } else {
14162                 intel_primary_formats = i8xx_primary_formats;
14163                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14164         }
14165
14166         drm_universal_plane_init(dev, &primary->base, 0,
14167                                  &intel_plane_funcs,
14168                                  intel_primary_formats, num_formats,
14169                                  DRM_PLANE_TYPE_PRIMARY);
14170
14171         if (INTEL_INFO(dev)->gen >= 4)
14172                 intel_create_rotation_property(dev, primary);
14173
14174         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14175
14176         return &primary->base;
14177 }
14178
14179 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14180 {
14181         if (!dev->mode_config.rotation_property) {
14182                 unsigned long flags = BIT(DRM_ROTATE_0) |
14183                         BIT(DRM_ROTATE_180);
14184
14185                 if (INTEL_INFO(dev)->gen >= 9)
14186                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14187
14188                 dev->mode_config.rotation_property =
14189                         drm_mode_create_rotation_property(dev, flags);
14190         }
14191         if (dev->mode_config.rotation_property)
14192                 drm_object_attach_property(&plane->base.base,
14193                                 dev->mode_config.rotation_property,
14194                                 plane->base.state->rotation);
14195 }
14196
14197 static int
14198 intel_check_cursor_plane(struct drm_plane *plane,
14199                          struct intel_crtc_state *crtc_state,
14200                          struct intel_plane_state *state)
14201 {
14202         struct drm_crtc *crtc = crtc_state->base.crtc;
14203         struct drm_framebuffer *fb = state->base.fb;
14204         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14205         enum pipe pipe = to_intel_plane(plane)->pipe;
14206         unsigned stride;
14207         int ret;
14208
14209         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14210                                             &state->dst, &state->clip,
14211                                             DRM_PLANE_HELPER_NO_SCALING,
14212                                             DRM_PLANE_HELPER_NO_SCALING,
14213                                             true, true, &state->visible);
14214         if (ret)
14215                 return ret;
14216
14217         /* if we want to turn off the cursor ignore width and height */
14218         if (!obj)
14219                 return 0;
14220
14221         /* Check for which cursor types we support */
14222         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14223                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14224                           state->base.crtc_w, state->base.crtc_h);
14225                 return -EINVAL;
14226         }
14227
14228         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14229         if (obj->base.size < stride * state->base.crtc_h) {
14230                 DRM_DEBUG_KMS("buffer is too small\n");
14231                 return -ENOMEM;
14232         }
14233
14234         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14235                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14236                 return -EINVAL;
14237         }
14238
14239         /*
14240          * There's something wrong with the cursor on CHV pipe C.
14241          * If it straddles the left edge of the screen then
14242          * moving it away from the edge or disabling it often
14243          * results in a pipe underrun, and often that can lead to
14244          * dead pipe (constant underrun reported, and it scans
14245          * out just a solid color). To recover from that, the
14246          * display power well must be turned off and on again.
14247          * Refuse the put the cursor into that compromised position.
14248          */
14249         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14250             state->visible && state->base.crtc_x < 0) {
14251                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14252                 return -EINVAL;
14253         }
14254
14255         return 0;
14256 }
14257
14258 static void
14259 intel_disable_cursor_plane(struct drm_plane *plane,
14260                            struct drm_crtc *crtc)
14261 {
14262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14263
14264         intel_crtc->cursor_addr = 0;
14265         intel_crtc_update_cursor(crtc, NULL);
14266 }
14267
14268 static void
14269 intel_update_cursor_plane(struct drm_plane *plane,
14270                           const struct intel_crtc_state *crtc_state,
14271                           const struct intel_plane_state *state)
14272 {
14273         struct drm_crtc *crtc = crtc_state->base.crtc;
14274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14275         struct drm_device *dev = plane->dev;
14276         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14277         uint32_t addr;
14278
14279         if (!obj)
14280                 addr = 0;
14281         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14282                 addr = i915_gem_obj_ggtt_offset(obj);
14283         else
14284                 addr = obj->phys_handle->busaddr;
14285
14286         intel_crtc->cursor_addr = addr;
14287         intel_crtc_update_cursor(crtc, state);
14288 }
14289
14290 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14291                                                    int pipe)
14292 {
14293         struct intel_plane *cursor;
14294         struct intel_plane_state *state;
14295
14296         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14297         if (cursor == NULL)
14298                 return NULL;
14299
14300         state = intel_create_plane_state(&cursor->base);
14301         if (!state) {
14302                 kfree(cursor);
14303                 return NULL;
14304         }
14305         cursor->base.state = &state->base;
14306
14307         cursor->can_scale = false;
14308         cursor->max_downscale = 1;
14309         cursor->pipe = pipe;
14310         cursor->plane = pipe;
14311         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14312         cursor->check_plane = intel_check_cursor_plane;
14313         cursor->update_plane = intel_update_cursor_plane;
14314         cursor->disable_plane = intel_disable_cursor_plane;
14315
14316         drm_universal_plane_init(dev, &cursor->base, 0,
14317                                  &intel_plane_funcs,
14318                                  intel_cursor_formats,
14319                                  ARRAY_SIZE(intel_cursor_formats),
14320                                  DRM_PLANE_TYPE_CURSOR);
14321
14322         if (INTEL_INFO(dev)->gen >= 4) {
14323                 if (!dev->mode_config.rotation_property)
14324                         dev->mode_config.rotation_property =
14325                                 drm_mode_create_rotation_property(dev,
14326                                                         BIT(DRM_ROTATE_0) |
14327                                                         BIT(DRM_ROTATE_180));
14328                 if (dev->mode_config.rotation_property)
14329                         drm_object_attach_property(&cursor->base.base,
14330                                 dev->mode_config.rotation_property,
14331                                 state->base.rotation);
14332         }
14333
14334         if (INTEL_INFO(dev)->gen >=9)
14335                 state->scaler_id = -1;
14336
14337         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14338
14339         return &cursor->base;
14340 }
14341
14342 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14343         struct intel_crtc_state *crtc_state)
14344 {
14345         int i;
14346         struct intel_scaler *intel_scaler;
14347         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14348
14349         for (i = 0; i < intel_crtc->num_scalers; i++) {
14350                 intel_scaler = &scaler_state->scalers[i];
14351                 intel_scaler->in_use = 0;
14352                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14353         }
14354
14355         scaler_state->scaler_id = -1;
14356 }
14357
14358 static void intel_crtc_init(struct drm_device *dev, int pipe)
14359 {
14360         struct drm_i915_private *dev_priv = dev->dev_private;
14361         struct intel_crtc *intel_crtc;
14362         struct intel_crtc_state *crtc_state = NULL;
14363         struct drm_plane *primary = NULL;
14364         struct drm_plane *cursor = NULL;
14365         int i, ret;
14366
14367         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14368         if (intel_crtc == NULL)
14369                 return;
14370
14371         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14372         if (!crtc_state)
14373                 goto fail;
14374         intel_crtc->config = crtc_state;
14375         intel_crtc->base.state = &crtc_state->base;
14376         crtc_state->base.crtc = &intel_crtc->base;
14377
14378         /* initialize shared scalers */
14379         if (INTEL_INFO(dev)->gen >= 9) {
14380                 if (pipe == PIPE_C)
14381                         intel_crtc->num_scalers = 1;
14382                 else
14383                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14384
14385                 skl_init_scalers(dev, intel_crtc, crtc_state);
14386         }
14387
14388         primary = intel_primary_plane_create(dev, pipe);
14389         if (!primary)
14390                 goto fail;
14391
14392         cursor = intel_cursor_plane_create(dev, pipe);
14393         if (!cursor)
14394                 goto fail;
14395
14396         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14397                                         cursor, &intel_crtc_funcs);
14398         if (ret)
14399                 goto fail;
14400
14401         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14402         for (i = 0; i < 256; i++) {
14403                 intel_crtc->lut_r[i] = i;
14404                 intel_crtc->lut_g[i] = i;
14405                 intel_crtc->lut_b[i] = i;
14406         }
14407
14408         /*
14409          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14410          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14411          */
14412         intel_crtc->pipe = pipe;
14413         intel_crtc->plane = pipe;
14414         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14415                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14416                 intel_crtc->plane = !pipe;
14417         }
14418
14419         intel_crtc->cursor_base = ~0;
14420         intel_crtc->cursor_cntl = ~0;
14421         intel_crtc->cursor_size = ~0;
14422
14423         intel_crtc->wm.cxsr_allowed = true;
14424
14425         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14426                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14427         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14428         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14429
14430         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14431
14432         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14433         return;
14434
14435 fail:
14436         if (primary)
14437                 drm_plane_cleanup(primary);
14438         if (cursor)
14439                 drm_plane_cleanup(cursor);
14440         kfree(crtc_state);
14441         kfree(intel_crtc);
14442 }
14443
14444 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14445 {
14446         struct drm_encoder *encoder = connector->base.encoder;
14447         struct drm_device *dev = connector->base.dev;
14448
14449         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14450
14451         if (!encoder || WARN_ON(!encoder->crtc))
14452                 return INVALID_PIPE;
14453
14454         return to_intel_crtc(encoder->crtc)->pipe;
14455 }
14456
14457 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14458                                 struct drm_file *file)
14459 {
14460         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14461         struct drm_crtc *drmmode_crtc;
14462         struct intel_crtc *crtc;
14463
14464         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14465
14466         if (!drmmode_crtc) {
14467                 DRM_ERROR("no such CRTC id\n");
14468                 return -ENOENT;
14469         }
14470
14471         crtc = to_intel_crtc(drmmode_crtc);
14472         pipe_from_crtc_id->pipe = crtc->pipe;
14473
14474         return 0;
14475 }
14476
14477 static int intel_encoder_clones(struct intel_encoder *encoder)
14478 {
14479         struct drm_device *dev = encoder->base.dev;
14480         struct intel_encoder *source_encoder;
14481         int index_mask = 0;
14482         int entry = 0;
14483
14484         for_each_intel_encoder(dev, source_encoder) {
14485                 if (encoders_cloneable(encoder, source_encoder))
14486                         index_mask |= (1 << entry);
14487
14488                 entry++;
14489         }
14490
14491         return index_mask;
14492 }
14493
14494 static bool has_edp_a(struct drm_device *dev)
14495 {
14496         struct drm_i915_private *dev_priv = dev->dev_private;
14497
14498         if (!IS_MOBILE(dev))
14499                 return false;
14500
14501         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14502                 return false;
14503
14504         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14505                 return false;
14506
14507         return true;
14508 }
14509
14510 static bool intel_crt_present(struct drm_device *dev)
14511 {
14512         struct drm_i915_private *dev_priv = dev->dev_private;
14513
14514         if (INTEL_INFO(dev)->gen >= 9)
14515                 return false;
14516
14517         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14518                 return false;
14519
14520         if (IS_CHERRYVIEW(dev))
14521                 return false;
14522
14523         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14524                 return false;
14525
14526         /* DDI E can't be used if DDI A requires 4 lanes */
14527         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14528                 return false;
14529
14530         if (!dev_priv->vbt.int_crt_support)
14531                 return false;
14532
14533         return true;
14534 }
14535
14536 static void intel_setup_outputs(struct drm_device *dev)
14537 {
14538         struct drm_i915_private *dev_priv = dev->dev_private;
14539         struct intel_encoder *encoder;
14540         bool dpd_is_edp = false;
14541
14542         intel_lvds_init(dev);
14543
14544         if (intel_crt_present(dev))
14545                 intel_crt_init(dev);
14546
14547         if (IS_BROXTON(dev)) {
14548                 /*
14549                  * FIXME: Broxton doesn't support port detection via the
14550                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14551                  * detect the ports.
14552                  */
14553                 intel_ddi_init(dev, PORT_A);
14554                 intel_ddi_init(dev, PORT_B);
14555                 intel_ddi_init(dev, PORT_C);
14556         } else if (HAS_DDI(dev)) {
14557                 int found;
14558
14559                 /*
14560                  * Haswell uses DDI functions to detect digital outputs.
14561                  * On SKL pre-D0 the strap isn't connected, so we assume
14562                  * it's there.
14563                  */
14564                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14565                 /* WaIgnoreDDIAStrap: skl */
14566                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14567                         intel_ddi_init(dev, PORT_A);
14568
14569                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14570                  * register */
14571                 found = I915_READ(SFUSE_STRAP);
14572
14573                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14574                         intel_ddi_init(dev, PORT_B);
14575                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14576                         intel_ddi_init(dev, PORT_C);
14577                 if (found & SFUSE_STRAP_DDID_DETECTED)
14578                         intel_ddi_init(dev, PORT_D);
14579                 /*
14580                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14581                  */
14582                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14583                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14584                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14585                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14586                         intel_ddi_init(dev, PORT_E);
14587
14588         } else if (HAS_PCH_SPLIT(dev)) {
14589                 int found;
14590                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14591
14592                 if (has_edp_a(dev))
14593                         intel_dp_init(dev, DP_A, PORT_A);
14594
14595                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14596                         /* PCH SDVOB multiplex with HDMIB */
14597                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14598                         if (!found)
14599                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14600                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14601                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14602                 }
14603
14604                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14605                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14606
14607                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14608                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14609
14610                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14611                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14612
14613                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14614                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14615         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14616                 /*
14617                  * The DP_DETECTED bit is the latched state of the DDC
14618                  * SDA pin at boot. However since eDP doesn't require DDC
14619                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14620                  * eDP ports may have been muxed to an alternate function.
14621                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14622                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14623                  * detect eDP ports.
14624                  */
14625                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14626                     !intel_dp_is_edp(dev, PORT_B))
14627                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14628                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14629                     intel_dp_is_edp(dev, PORT_B))
14630                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14631
14632                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14633                     !intel_dp_is_edp(dev, PORT_C))
14634                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14635                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14636                     intel_dp_is_edp(dev, PORT_C))
14637                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14638
14639                 if (IS_CHERRYVIEW(dev)) {
14640                         /* eDP not supported on port D, so don't check VBT */
14641                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14642                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14643                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14644                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14645                 }
14646
14647                 intel_dsi_init(dev);
14648         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14649                 bool found = false;
14650
14651                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14652                         DRM_DEBUG_KMS("probing SDVOB\n");
14653                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14654                         if (!found && IS_G4X(dev)) {
14655                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14656                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14657                         }
14658
14659                         if (!found && IS_G4X(dev))
14660                                 intel_dp_init(dev, DP_B, PORT_B);
14661                 }
14662
14663                 /* Before G4X SDVOC doesn't have its own detect register */
14664
14665                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14666                         DRM_DEBUG_KMS("probing SDVOC\n");
14667                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14668                 }
14669
14670                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14671
14672                         if (IS_G4X(dev)) {
14673                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14674                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14675                         }
14676                         if (IS_G4X(dev))
14677                                 intel_dp_init(dev, DP_C, PORT_C);
14678                 }
14679
14680                 if (IS_G4X(dev) &&
14681                     (I915_READ(DP_D) & DP_DETECTED))
14682                         intel_dp_init(dev, DP_D, PORT_D);
14683         } else if (IS_GEN2(dev))
14684                 intel_dvo_init(dev);
14685
14686         if (SUPPORTS_TV(dev))
14687                 intel_tv_init(dev);
14688
14689         intel_psr_init(dev);
14690
14691         for_each_intel_encoder(dev, encoder) {
14692                 encoder->base.possible_crtcs = encoder->crtc_mask;
14693                 encoder->base.possible_clones =
14694                         intel_encoder_clones(encoder);
14695         }
14696
14697         intel_init_pch_refclk(dev);
14698
14699         drm_helper_move_panel_connectors_to_head(dev);
14700 }
14701
14702 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14703 {
14704         struct drm_device *dev = fb->dev;
14705         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14706
14707         drm_framebuffer_cleanup(fb);
14708         mutex_lock(&dev->struct_mutex);
14709         WARN_ON(!intel_fb->obj->framebuffer_references--);
14710         drm_gem_object_unreference(&intel_fb->obj->base);
14711         mutex_unlock(&dev->struct_mutex);
14712         kfree(intel_fb);
14713 }
14714
14715 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14716                                                 struct drm_file *file,
14717                                                 unsigned int *handle)
14718 {
14719         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14720         struct drm_i915_gem_object *obj = intel_fb->obj;
14721
14722         if (obj->userptr.mm) {
14723                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14724                 return -EINVAL;
14725         }
14726
14727         return drm_gem_handle_create(file, &obj->base, handle);
14728 }
14729
14730 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14731                                         struct drm_file *file,
14732                                         unsigned flags, unsigned color,
14733                                         struct drm_clip_rect *clips,
14734                                         unsigned num_clips)
14735 {
14736         struct drm_device *dev = fb->dev;
14737         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14738         struct drm_i915_gem_object *obj = intel_fb->obj;
14739
14740         mutex_lock(&dev->struct_mutex);
14741         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14742         mutex_unlock(&dev->struct_mutex);
14743
14744         return 0;
14745 }
14746
14747 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14748         .destroy = intel_user_framebuffer_destroy,
14749         .create_handle = intel_user_framebuffer_create_handle,
14750         .dirty = intel_user_framebuffer_dirty,
14751 };
14752
14753 static
14754 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14755                          uint32_t pixel_format)
14756 {
14757         u32 gen = INTEL_INFO(dev)->gen;
14758
14759         if (gen >= 9) {
14760                 /* "The stride in bytes must not exceed the of the size of 8K
14761                  *  pixels and 32K bytes."
14762                  */
14763                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14764         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14765                 return 32*1024;
14766         } else if (gen >= 4) {
14767                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14768                         return 16*1024;
14769                 else
14770                         return 32*1024;
14771         } else if (gen >= 3) {
14772                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14773                         return 8*1024;
14774                 else
14775                         return 16*1024;
14776         } else {
14777                 /* XXX DSPC is limited to 4k tiled */
14778                 return 8*1024;
14779         }
14780 }
14781
14782 static int intel_framebuffer_init(struct drm_device *dev,
14783                                   struct intel_framebuffer *intel_fb,
14784                                   struct drm_mode_fb_cmd2 *mode_cmd,
14785                                   struct drm_i915_gem_object *obj)
14786 {
14787         unsigned int aligned_height;
14788         int ret;
14789         u32 pitch_limit, stride_alignment;
14790
14791         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14792
14793         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14794                 /* Enforce that fb modifier and tiling mode match, but only for
14795                  * X-tiled. This is needed for FBC. */
14796                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14797                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14798                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14799                         return -EINVAL;
14800                 }
14801         } else {
14802                 if (obj->tiling_mode == I915_TILING_X)
14803                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14804                 else if (obj->tiling_mode == I915_TILING_Y) {
14805                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14806                         return -EINVAL;
14807                 }
14808         }
14809
14810         /* Passed in modifier sanity checking. */
14811         switch (mode_cmd->modifier[0]) {
14812         case I915_FORMAT_MOD_Y_TILED:
14813         case I915_FORMAT_MOD_Yf_TILED:
14814                 if (INTEL_INFO(dev)->gen < 9) {
14815                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14816                                   mode_cmd->modifier[0]);
14817                         return -EINVAL;
14818                 }
14819         case DRM_FORMAT_MOD_NONE:
14820         case I915_FORMAT_MOD_X_TILED:
14821                 break;
14822         default:
14823                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14824                           mode_cmd->modifier[0]);
14825                 return -EINVAL;
14826         }
14827
14828         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14829                                                      mode_cmd->pixel_format);
14830         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14831                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14832                           mode_cmd->pitches[0], stride_alignment);
14833                 return -EINVAL;
14834         }
14835
14836         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14837                                            mode_cmd->pixel_format);
14838         if (mode_cmd->pitches[0] > pitch_limit) {
14839                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14840                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14841                           "tiled" : "linear",
14842                           mode_cmd->pitches[0], pitch_limit);
14843                 return -EINVAL;
14844         }
14845
14846         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14847             mode_cmd->pitches[0] != obj->stride) {
14848                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14849                           mode_cmd->pitches[0], obj->stride);
14850                 return -EINVAL;
14851         }
14852
14853         /* Reject formats not supported by any plane early. */
14854         switch (mode_cmd->pixel_format) {
14855         case DRM_FORMAT_C8:
14856         case DRM_FORMAT_RGB565:
14857         case DRM_FORMAT_XRGB8888:
14858         case DRM_FORMAT_ARGB8888:
14859                 break;
14860         case DRM_FORMAT_XRGB1555:
14861                 if (INTEL_INFO(dev)->gen > 3) {
14862                         DRM_DEBUG("unsupported pixel format: %s\n",
14863                                   drm_get_format_name(mode_cmd->pixel_format));
14864                         return -EINVAL;
14865                 }
14866                 break;
14867         case DRM_FORMAT_ABGR8888:
14868                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14869                     INTEL_INFO(dev)->gen < 9) {
14870                         DRM_DEBUG("unsupported pixel format: %s\n",
14871                                   drm_get_format_name(mode_cmd->pixel_format));
14872                         return -EINVAL;
14873                 }
14874                 break;
14875         case DRM_FORMAT_XBGR8888:
14876         case DRM_FORMAT_XRGB2101010:
14877         case DRM_FORMAT_XBGR2101010:
14878                 if (INTEL_INFO(dev)->gen < 4) {
14879                         DRM_DEBUG("unsupported pixel format: %s\n",
14880                                   drm_get_format_name(mode_cmd->pixel_format));
14881                         return -EINVAL;
14882                 }
14883                 break;
14884         case DRM_FORMAT_ABGR2101010:
14885                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14886                         DRM_DEBUG("unsupported pixel format: %s\n",
14887                                   drm_get_format_name(mode_cmd->pixel_format));
14888                         return -EINVAL;
14889                 }
14890                 break;
14891         case DRM_FORMAT_YUYV:
14892         case DRM_FORMAT_UYVY:
14893         case DRM_FORMAT_YVYU:
14894         case DRM_FORMAT_VYUY:
14895                 if (INTEL_INFO(dev)->gen < 5) {
14896                         DRM_DEBUG("unsupported pixel format: %s\n",
14897                                   drm_get_format_name(mode_cmd->pixel_format));
14898                         return -EINVAL;
14899                 }
14900                 break;
14901         default:
14902                 DRM_DEBUG("unsupported pixel format: %s\n",
14903                           drm_get_format_name(mode_cmd->pixel_format));
14904                 return -EINVAL;
14905         }
14906
14907         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14908         if (mode_cmd->offsets[0] != 0)
14909                 return -EINVAL;
14910
14911         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14912                                                mode_cmd->pixel_format,
14913                                                mode_cmd->modifier[0]);
14914         /* FIXME drm helper for size checks (especially planar formats)? */
14915         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14916                 return -EINVAL;
14917
14918         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14919         intel_fb->obj = obj;
14920         intel_fb->obj->framebuffer_references++;
14921
14922         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14923         if (ret) {
14924                 DRM_ERROR("framebuffer init failed %d\n", ret);
14925                 return ret;
14926         }
14927
14928         return 0;
14929 }
14930
14931 static struct drm_framebuffer *
14932 intel_user_framebuffer_create(struct drm_device *dev,
14933                               struct drm_file *filp,
14934                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14935 {
14936         struct drm_framebuffer *fb;
14937         struct drm_i915_gem_object *obj;
14938         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14939
14940         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14941                                                 mode_cmd.handles[0]));
14942         if (&obj->base == NULL)
14943                 return ERR_PTR(-ENOENT);
14944
14945         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14946         if (IS_ERR(fb))
14947                 drm_gem_object_unreference_unlocked(&obj->base);
14948
14949         return fb;
14950 }
14951
14952 #ifndef CONFIG_DRM_FBDEV_EMULATION
14953 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14954 {
14955 }
14956 #endif
14957
14958 static const struct drm_mode_config_funcs intel_mode_funcs = {
14959         .fb_create = intel_user_framebuffer_create,
14960         .output_poll_changed = intel_fbdev_output_poll_changed,
14961         .atomic_check = intel_atomic_check,
14962         .atomic_commit = intel_atomic_commit,
14963         .atomic_state_alloc = intel_atomic_state_alloc,
14964         .atomic_state_clear = intel_atomic_state_clear,
14965 };
14966
14967 /* Set up chip specific display functions */
14968 static void intel_init_display(struct drm_device *dev)
14969 {
14970         struct drm_i915_private *dev_priv = dev->dev_private;
14971
14972         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14973                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14974         else if (IS_CHERRYVIEW(dev))
14975                 dev_priv->display.find_dpll = chv_find_best_dpll;
14976         else if (IS_VALLEYVIEW(dev))
14977                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14978         else if (IS_PINEVIEW(dev))
14979                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14980         else
14981                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14982
14983         if (INTEL_INFO(dev)->gen >= 9) {
14984                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14985                 dev_priv->display.get_initial_plane_config =
14986                         skylake_get_initial_plane_config;
14987                 dev_priv->display.crtc_compute_clock =
14988                         haswell_crtc_compute_clock;
14989                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14990                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14991                 dev_priv->display.update_primary_plane =
14992                         skylake_update_primary_plane;
14993         } else if (HAS_DDI(dev)) {
14994                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14995                 dev_priv->display.get_initial_plane_config =
14996                         ironlake_get_initial_plane_config;
14997                 dev_priv->display.crtc_compute_clock =
14998                         haswell_crtc_compute_clock;
14999                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15000                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15001                 dev_priv->display.update_primary_plane =
15002                         ironlake_update_primary_plane;
15003         } else if (HAS_PCH_SPLIT(dev)) {
15004                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15005                 dev_priv->display.get_initial_plane_config =
15006                         ironlake_get_initial_plane_config;
15007                 dev_priv->display.crtc_compute_clock =
15008                         ironlake_crtc_compute_clock;
15009                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15010                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15011                 dev_priv->display.update_primary_plane =
15012                         ironlake_update_primary_plane;
15013         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15014                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15015                 dev_priv->display.get_initial_plane_config =
15016                         i9xx_get_initial_plane_config;
15017                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15018                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15019                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15020                 dev_priv->display.update_primary_plane =
15021                         i9xx_update_primary_plane;
15022         } else {
15023                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15024                 dev_priv->display.get_initial_plane_config =
15025                         i9xx_get_initial_plane_config;
15026                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15027                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15028                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15029                 dev_priv->display.update_primary_plane =
15030                         i9xx_update_primary_plane;
15031         }
15032
15033         /* Returns the core display clock speed */
15034         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15035                 dev_priv->display.get_display_clock_speed =
15036                         skylake_get_display_clock_speed;
15037         else if (IS_BROXTON(dev))
15038                 dev_priv->display.get_display_clock_speed =
15039                         broxton_get_display_clock_speed;
15040         else if (IS_BROADWELL(dev))
15041                 dev_priv->display.get_display_clock_speed =
15042                         broadwell_get_display_clock_speed;
15043         else if (IS_HASWELL(dev))
15044                 dev_priv->display.get_display_clock_speed =
15045                         haswell_get_display_clock_speed;
15046         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15047                 dev_priv->display.get_display_clock_speed =
15048                         valleyview_get_display_clock_speed;
15049         else if (IS_GEN5(dev))
15050                 dev_priv->display.get_display_clock_speed =
15051                         ilk_get_display_clock_speed;
15052         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
15053                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
15054                 dev_priv->display.get_display_clock_speed =
15055                         i945_get_display_clock_speed;
15056         else if (IS_GM45(dev))
15057                 dev_priv->display.get_display_clock_speed =
15058                         gm45_get_display_clock_speed;
15059         else if (IS_CRESTLINE(dev))
15060                 dev_priv->display.get_display_clock_speed =
15061                         i965gm_get_display_clock_speed;
15062         else if (IS_PINEVIEW(dev))
15063                 dev_priv->display.get_display_clock_speed =
15064                         pnv_get_display_clock_speed;
15065         else if (IS_G33(dev) || IS_G4X(dev))
15066                 dev_priv->display.get_display_clock_speed =
15067                         g33_get_display_clock_speed;
15068         else if (IS_I915G(dev))
15069                 dev_priv->display.get_display_clock_speed =
15070                         i915_get_display_clock_speed;
15071         else if (IS_I945GM(dev) || IS_845G(dev))
15072                 dev_priv->display.get_display_clock_speed =
15073                         i9xx_misc_get_display_clock_speed;
15074         else if (IS_I915GM(dev))
15075                 dev_priv->display.get_display_clock_speed =
15076                         i915gm_get_display_clock_speed;
15077         else if (IS_I865G(dev))
15078                 dev_priv->display.get_display_clock_speed =
15079                         i865_get_display_clock_speed;
15080         else if (IS_I85X(dev))
15081                 dev_priv->display.get_display_clock_speed =
15082                         i85x_get_display_clock_speed;
15083         else { /* 830 */
15084                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
15085                 dev_priv->display.get_display_clock_speed =
15086                         i830_get_display_clock_speed;
15087         }
15088
15089         if (IS_GEN5(dev)) {
15090                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15091         } else if (IS_GEN6(dev)) {
15092                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15093         } else if (IS_IVYBRIDGE(dev)) {
15094                 /* FIXME: detect B0+ stepping and use auto training */
15095                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15096         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15097                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15098                 if (IS_BROADWELL(dev)) {
15099                         dev_priv->display.modeset_commit_cdclk =
15100                                 broadwell_modeset_commit_cdclk;
15101                         dev_priv->display.modeset_calc_cdclk =
15102                                 broadwell_modeset_calc_cdclk;
15103                 }
15104         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15105                 dev_priv->display.modeset_commit_cdclk =
15106                         valleyview_modeset_commit_cdclk;
15107                 dev_priv->display.modeset_calc_cdclk =
15108                         valleyview_modeset_calc_cdclk;
15109         } else if (IS_BROXTON(dev)) {
15110                 dev_priv->display.modeset_commit_cdclk =
15111                         broxton_modeset_commit_cdclk;
15112                 dev_priv->display.modeset_calc_cdclk =
15113                         broxton_modeset_calc_cdclk;
15114         }
15115
15116         switch (INTEL_INFO(dev)->gen) {
15117         case 2:
15118                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15119                 break;
15120
15121         case 3:
15122                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15123                 break;
15124
15125         case 4:
15126         case 5:
15127                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15128                 break;
15129
15130         case 6:
15131                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15132                 break;
15133         case 7:
15134         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15135                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15136                 break;
15137         case 9:
15138                 /* Drop through - unsupported since execlist only. */
15139         default:
15140                 /* Default just returns -ENODEV to indicate unsupported */
15141                 dev_priv->display.queue_flip = intel_default_queue_flip;
15142         }
15143
15144         mutex_init(&dev_priv->pps_mutex);
15145 }
15146
15147 /*
15148  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15149  * resume, or other times.  This quirk makes sure that's the case for
15150  * affected systems.
15151  */
15152 static void quirk_pipea_force(struct drm_device *dev)
15153 {
15154         struct drm_i915_private *dev_priv = dev->dev_private;
15155
15156         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15157         DRM_INFO("applying pipe a force quirk\n");
15158 }
15159
15160 static void quirk_pipeb_force(struct drm_device *dev)
15161 {
15162         struct drm_i915_private *dev_priv = dev->dev_private;
15163
15164         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15165         DRM_INFO("applying pipe b force quirk\n");
15166 }
15167
15168 /*
15169  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15170  */
15171 static void quirk_ssc_force_disable(struct drm_device *dev)
15172 {
15173         struct drm_i915_private *dev_priv = dev->dev_private;
15174         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15175         DRM_INFO("applying lvds SSC disable quirk\n");
15176 }
15177
15178 /*
15179  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15180  * brightness value
15181  */
15182 static void quirk_invert_brightness(struct drm_device *dev)
15183 {
15184         struct drm_i915_private *dev_priv = dev->dev_private;
15185         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15186         DRM_INFO("applying inverted panel brightness quirk\n");
15187 }
15188
15189 /* Some VBT's incorrectly indicate no backlight is present */
15190 static void quirk_backlight_present(struct drm_device *dev)
15191 {
15192         struct drm_i915_private *dev_priv = dev->dev_private;
15193         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15194         DRM_INFO("applying backlight present quirk\n");
15195 }
15196
15197 struct intel_quirk {
15198         int device;
15199         int subsystem_vendor;
15200         int subsystem_device;
15201         void (*hook)(struct drm_device *dev);
15202 };
15203
15204 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15205 struct intel_dmi_quirk {
15206         void (*hook)(struct drm_device *dev);
15207         const struct dmi_system_id (*dmi_id_list)[];
15208 };
15209
15210 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15211 {
15212         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15213         return 1;
15214 }
15215
15216 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15217         {
15218                 .dmi_id_list = &(const struct dmi_system_id[]) {
15219                         {
15220                                 .callback = intel_dmi_reverse_brightness,
15221                                 .ident = "NCR Corporation",
15222                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15223                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15224                                 },
15225                         },
15226                         { }  /* terminating entry */
15227                 },
15228                 .hook = quirk_invert_brightness,
15229         },
15230 };
15231
15232 static struct intel_quirk intel_quirks[] = {
15233         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15234         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15235
15236         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15237         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15238
15239         /* 830 needs to leave pipe A & dpll A up */
15240         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15241
15242         /* 830 needs to leave pipe B & dpll B up */
15243         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15244
15245         /* Lenovo U160 cannot use SSC on LVDS */
15246         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15247
15248         /* Sony Vaio Y cannot use SSC on LVDS */
15249         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15250
15251         /* Acer Aspire 5734Z must invert backlight brightness */
15252         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15253
15254         /* Acer/eMachines G725 */
15255         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15256
15257         /* Acer/eMachines e725 */
15258         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15259
15260         /* Acer/Packard Bell NCL20 */
15261         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15262
15263         /* Acer Aspire 4736Z */
15264         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15265
15266         /* Acer Aspire 5336 */
15267         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15268
15269         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15270         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15271
15272         /* Acer C720 Chromebook (Core i3 4005U) */
15273         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15274
15275         /* Apple Macbook 2,1 (Core 2 T7400) */
15276         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15277
15278         /* Apple Macbook 4,1 */
15279         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15280
15281         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15282         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15283
15284         /* HP Chromebook 14 (Celeron 2955U) */
15285         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15286
15287         /* Dell Chromebook 11 */
15288         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15289
15290         /* Dell Chromebook 11 (2015 version) */
15291         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15292 };
15293
15294 static void intel_init_quirks(struct drm_device *dev)
15295 {
15296         struct pci_dev *d = dev->pdev;
15297         int i;
15298
15299         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15300                 struct intel_quirk *q = &intel_quirks[i];
15301
15302                 if (d->device == q->device &&
15303                     (d->subsystem_vendor == q->subsystem_vendor ||
15304                      q->subsystem_vendor == PCI_ANY_ID) &&
15305                     (d->subsystem_device == q->subsystem_device ||
15306                      q->subsystem_device == PCI_ANY_ID))
15307                         q->hook(dev);
15308         }
15309         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15310                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15311                         intel_dmi_quirks[i].hook(dev);
15312         }
15313 }
15314
15315 /* Disable the VGA plane that we never use */
15316 static void i915_disable_vga(struct drm_device *dev)
15317 {
15318         struct drm_i915_private *dev_priv = dev->dev_private;
15319         u8 sr1;
15320         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15321
15322         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15323         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15324         outb(SR01, VGA_SR_INDEX);
15325         sr1 = inb(VGA_SR_DATA);
15326         outb(sr1 | 1<<5, VGA_SR_DATA);
15327         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15328         udelay(300);
15329
15330         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15331         POSTING_READ(vga_reg);
15332 }
15333
15334 void intel_modeset_init_hw(struct drm_device *dev)
15335 {
15336         struct drm_i915_private *dev_priv = dev->dev_private;
15337
15338         intel_update_cdclk(dev);
15339
15340         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15341
15342         intel_prepare_ddi(dev);
15343         intel_init_clock_gating(dev);
15344         intel_enable_gt_powersave(dev);
15345 }
15346
15347 /*
15348  * Calculate what we think the watermarks should be for the state we've read
15349  * out of the hardware and then immediately program those watermarks so that
15350  * we ensure the hardware settings match our internal state.
15351  *
15352  * We can calculate what we think WM's should be by creating a duplicate of the
15353  * current state (which was constructed during hardware readout) and running it
15354  * through the atomic check code to calculate new watermark values in the
15355  * state object.
15356  */
15357 static void sanitize_watermarks(struct drm_device *dev)
15358 {
15359         struct drm_i915_private *dev_priv = to_i915(dev);
15360         struct drm_atomic_state *state;
15361         struct drm_crtc *crtc;
15362         struct drm_crtc_state *cstate;
15363         struct drm_modeset_acquire_ctx ctx;
15364         int ret;
15365         int i;
15366
15367         /* Only supported on platforms that use atomic watermark design */
15368         if (!dev_priv->display.optimize_watermarks)
15369                 return;
15370
15371         /*
15372          * We need to hold connection_mutex before calling duplicate_state so
15373          * that the connector loop is protected.
15374          */
15375         drm_modeset_acquire_init(&ctx, 0);
15376 retry:
15377         ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
15378         if (ret == -EDEADLK) {
15379                 drm_modeset_backoff(&ctx);
15380                 goto retry;
15381         } else if (WARN_ON(ret)) {
15382                 return;
15383         }
15384
15385         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15386         if (WARN_ON(IS_ERR(state)))
15387                 return;
15388
15389         /*
15390          * Hardware readout is the only time we don't want to calculate
15391          * intermediate watermarks (since we don't trust the current
15392          * watermarks).
15393          */
15394         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15395
15396         ret = intel_atomic_check(dev, state);
15397         if (ret) {
15398                 /*
15399                  * If we fail here, it means that the hardware appears to be
15400                  * programmed in a way that shouldn't be possible, given our
15401                  * understanding of watermark requirements.  This might mean a
15402                  * mistake in the hardware readout code or a mistake in the
15403                  * watermark calculations for a given platform.  Raise a WARN
15404                  * so that this is noticeable.
15405                  *
15406                  * If this actually happens, we'll have to just leave the
15407                  * BIOS-programmed watermarks untouched and hope for the best.
15408                  */
15409                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15410                 return;
15411         }
15412
15413         /* Write calculated watermark values back */
15414         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15415         for_each_crtc_in_state(state, crtc, cstate, i) {
15416                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15417
15418                 cs->wm.need_postvbl_update = true;
15419                 dev_priv->display.optimize_watermarks(cs);
15420         }
15421
15422         drm_atomic_state_free(state);
15423         drm_modeset_drop_locks(&ctx);
15424         drm_modeset_acquire_fini(&ctx);
15425 }
15426
15427 void intel_modeset_init(struct drm_device *dev)
15428 {
15429         struct drm_i915_private *dev_priv = dev->dev_private;
15430         int sprite, ret;
15431         enum pipe pipe;
15432         struct intel_crtc *crtc;
15433
15434         drm_mode_config_init(dev);
15435
15436         dev->mode_config.min_width = 0;
15437         dev->mode_config.min_height = 0;
15438
15439         dev->mode_config.preferred_depth = 24;
15440         dev->mode_config.prefer_shadow = 1;
15441
15442         dev->mode_config.allow_fb_modifiers = true;
15443
15444         dev->mode_config.funcs = &intel_mode_funcs;
15445
15446         intel_init_quirks(dev);
15447
15448         intel_init_pm(dev);
15449
15450         if (INTEL_INFO(dev)->num_pipes == 0)
15451                 return;
15452
15453         /*
15454          * There may be no VBT; and if the BIOS enabled SSC we can
15455          * just keep using it to avoid unnecessary flicker.  Whereas if the
15456          * BIOS isn't using it, don't assume it will work even if the VBT
15457          * indicates as much.
15458          */
15459         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15460                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15461                                             DREF_SSC1_ENABLE);
15462
15463                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15464                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15465                                      bios_lvds_use_ssc ? "en" : "dis",
15466                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15467                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15468                 }
15469         }
15470
15471         intel_init_display(dev);
15472         intel_init_audio(dev);
15473
15474         if (IS_GEN2(dev)) {
15475                 dev->mode_config.max_width = 2048;
15476                 dev->mode_config.max_height = 2048;
15477         } else if (IS_GEN3(dev)) {
15478                 dev->mode_config.max_width = 4096;
15479                 dev->mode_config.max_height = 4096;
15480         } else {
15481                 dev->mode_config.max_width = 8192;
15482                 dev->mode_config.max_height = 8192;
15483         }
15484
15485         if (IS_845G(dev) || IS_I865G(dev)) {
15486                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15487                 dev->mode_config.cursor_height = 1023;
15488         } else if (IS_GEN2(dev)) {
15489                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15490                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15491         } else {
15492                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15493                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15494         }
15495
15496         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15497
15498         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15499                       INTEL_INFO(dev)->num_pipes,
15500                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15501
15502         for_each_pipe(dev_priv, pipe) {
15503                 intel_crtc_init(dev, pipe);
15504                 for_each_sprite(dev_priv, pipe, sprite) {
15505                         ret = intel_plane_init(dev, pipe, sprite);
15506                         if (ret)
15507                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15508                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15509                 }
15510         }
15511
15512         intel_update_czclk(dev_priv);
15513         intel_update_cdclk(dev);
15514
15515         intel_shared_dpll_init(dev);
15516
15517         /* Just disable it once at startup */
15518         i915_disable_vga(dev);
15519         intel_setup_outputs(dev);
15520
15521         drm_modeset_lock_all(dev);
15522         intel_modeset_setup_hw_state(dev);
15523         drm_modeset_unlock_all(dev);
15524
15525         for_each_intel_crtc(dev, crtc) {
15526                 struct intel_initial_plane_config plane_config = {};
15527
15528                 if (!crtc->active)
15529                         continue;
15530
15531                 /*
15532                  * Note that reserving the BIOS fb up front prevents us
15533                  * from stuffing other stolen allocations like the ring
15534                  * on top.  This prevents some ugliness at boot time, and
15535                  * can even allow for smooth boot transitions if the BIOS
15536                  * fb is large enough for the active pipe configuration.
15537                  */
15538                 dev_priv->display.get_initial_plane_config(crtc,
15539                                                            &plane_config);
15540
15541                 /*
15542                  * If the fb is shared between multiple heads, we'll
15543                  * just get the first one.
15544                  */
15545                 intel_find_initial_plane_obj(crtc, &plane_config);
15546         }
15547
15548         /*
15549          * Make sure hardware watermarks really match the state we read out.
15550          * Note that we need to do this after reconstructing the BIOS fb's
15551          * since the watermark calculation done here will use pstate->fb.
15552          */
15553         sanitize_watermarks(dev);
15554 }
15555
15556 static void intel_enable_pipe_a(struct drm_device *dev)
15557 {
15558         struct intel_connector *connector;
15559         struct drm_connector *crt = NULL;
15560         struct intel_load_detect_pipe load_detect_temp;
15561         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15562
15563         /* We can't just switch on the pipe A, we need to set things up with a
15564          * proper mode and output configuration. As a gross hack, enable pipe A
15565          * by enabling the load detect pipe once. */
15566         for_each_intel_connector(dev, connector) {
15567                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15568                         crt = &connector->base;
15569                         break;
15570                 }
15571         }
15572
15573         if (!crt)
15574                 return;
15575
15576         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15577                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15578 }
15579
15580 static bool
15581 intel_check_plane_mapping(struct intel_crtc *crtc)
15582 {
15583         struct drm_device *dev = crtc->base.dev;
15584         struct drm_i915_private *dev_priv = dev->dev_private;
15585         u32 val;
15586
15587         if (INTEL_INFO(dev)->num_pipes == 1)
15588                 return true;
15589
15590         val = I915_READ(DSPCNTR(!crtc->plane));
15591
15592         if ((val & DISPLAY_PLANE_ENABLE) &&
15593             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15594                 return false;
15595
15596         return true;
15597 }
15598
15599 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15600 {
15601         struct drm_device *dev = crtc->base.dev;
15602         struct intel_encoder *encoder;
15603
15604         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15605                 return true;
15606
15607         return false;
15608 }
15609
15610 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15611 {
15612         struct drm_device *dev = crtc->base.dev;
15613         struct drm_i915_private *dev_priv = dev->dev_private;
15614         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15615
15616         /* Clear any frame start delays used for debugging left by the BIOS */
15617         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15618
15619         /* restore vblank interrupts to correct state */
15620         drm_crtc_vblank_reset(&crtc->base);
15621         if (crtc->active) {
15622                 struct intel_plane *plane;
15623
15624                 drm_crtc_vblank_on(&crtc->base);
15625
15626                 /* Disable everything but the primary plane */
15627                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15628                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15629                                 continue;
15630
15631                         plane->disable_plane(&plane->base, &crtc->base);
15632                 }
15633         }
15634
15635         /* We need to sanitize the plane -> pipe mapping first because this will
15636          * disable the crtc (and hence change the state) if it is wrong. Note
15637          * that gen4+ has a fixed plane -> pipe mapping.  */
15638         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15639                 bool plane;
15640
15641                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15642                               crtc->base.base.id);
15643
15644                 /* Pipe has the wrong plane attached and the plane is active.
15645                  * Temporarily change the plane mapping and disable everything
15646                  * ...  */
15647                 plane = crtc->plane;
15648                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15649                 crtc->plane = !plane;
15650                 intel_crtc_disable_noatomic(&crtc->base);
15651                 crtc->plane = plane;
15652         }
15653
15654         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15655             crtc->pipe == PIPE_A && !crtc->active) {
15656                 /* BIOS forgot to enable pipe A, this mostly happens after
15657                  * resume. Force-enable the pipe to fix this, the update_dpms
15658                  * call below we restore the pipe to the right state, but leave
15659                  * the required bits on. */
15660                 intel_enable_pipe_a(dev);
15661         }
15662
15663         /* Adjust the state of the output pipe according to whether we
15664          * have active connectors/encoders. */
15665         if (!intel_crtc_has_encoders(crtc))
15666                 intel_crtc_disable_noatomic(&crtc->base);
15667
15668         if (crtc->active != crtc->base.state->active) {
15669                 struct intel_encoder *encoder;
15670
15671                 /* This can happen either due to bugs in the get_hw_state
15672                  * functions or because of calls to intel_crtc_disable_noatomic,
15673                  * or because the pipe is force-enabled due to the
15674                  * pipe A quirk. */
15675                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15676                               crtc->base.base.id,
15677                               crtc->base.state->enable ? "enabled" : "disabled",
15678                               crtc->active ? "enabled" : "disabled");
15679
15680                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15681                 crtc->base.state->active = crtc->active;
15682                 crtc->base.enabled = crtc->active;
15683
15684                 /* Because we only establish the connector -> encoder ->
15685                  * crtc links if something is active, this means the
15686                  * crtc is now deactivated. Break the links. connector
15687                  * -> encoder links are only establish when things are
15688                  *  actually up, hence no need to break them. */
15689                 WARN_ON(crtc->active);
15690
15691                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15692                         encoder->base.crtc = NULL;
15693         }
15694
15695         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15696                 /*
15697                  * We start out with underrun reporting disabled to avoid races.
15698                  * For correct bookkeeping mark this on active crtcs.
15699                  *
15700                  * Also on gmch platforms we dont have any hardware bits to
15701                  * disable the underrun reporting. Which means we need to start
15702                  * out with underrun reporting disabled also on inactive pipes,
15703                  * since otherwise we'll complain about the garbage we read when
15704                  * e.g. coming up after runtime pm.
15705                  *
15706                  * No protection against concurrent access is required - at
15707                  * worst a fifo underrun happens which also sets this to false.
15708                  */
15709                 crtc->cpu_fifo_underrun_disabled = true;
15710                 crtc->pch_fifo_underrun_disabled = true;
15711         }
15712 }
15713
15714 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15715 {
15716         struct intel_connector *connector;
15717         struct drm_device *dev = encoder->base.dev;
15718         bool active = false;
15719
15720         /* We need to check both for a crtc link (meaning that the
15721          * encoder is active and trying to read from a pipe) and the
15722          * pipe itself being active. */
15723         bool has_active_crtc = encoder->base.crtc &&
15724                 to_intel_crtc(encoder->base.crtc)->active;
15725
15726         for_each_intel_connector(dev, connector) {
15727                 if (connector->base.encoder != &encoder->base)
15728                         continue;
15729
15730                 active = true;
15731                 break;
15732         }
15733
15734         if (active && !has_active_crtc) {
15735                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15736                               encoder->base.base.id,
15737                               encoder->base.name);
15738
15739                 /* Connector is active, but has no active pipe. This is
15740                  * fallout from our resume register restoring. Disable
15741                  * the encoder manually again. */
15742                 if (encoder->base.crtc) {
15743                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15744                                       encoder->base.base.id,
15745                                       encoder->base.name);
15746                         encoder->disable(encoder);
15747                         if (encoder->post_disable)
15748                                 encoder->post_disable(encoder);
15749                 }
15750                 encoder->base.crtc = NULL;
15751
15752                 /* Inconsistent output/port/pipe state happens presumably due to
15753                  * a bug in one of the get_hw_state functions. Or someplace else
15754                  * in our code, like the register restore mess on resume. Clamp
15755                  * things to off as a safer default. */
15756                 for_each_intel_connector(dev, connector) {
15757                         if (connector->encoder != encoder)
15758                                 continue;
15759                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15760                         connector->base.encoder = NULL;
15761                 }
15762         }
15763         /* Enabled encoders without active connectors will be fixed in
15764          * the crtc fixup. */
15765 }
15766
15767 void i915_redisable_vga_power_on(struct drm_device *dev)
15768 {
15769         struct drm_i915_private *dev_priv = dev->dev_private;
15770         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15771
15772         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15773                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15774                 i915_disable_vga(dev);
15775         }
15776 }
15777
15778 void i915_redisable_vga(struct drm_device *dev)
15779 {
15780         struct drm_i915_private *dev_priv = dev->dev_private;
15781
15782         /* This function can be called both from intel_modeset_setup_hw_state or
15783          * at a very early point in our resume sequence, where the power well
15784          * structures are not yet restored. Since this function is at a very
15785          * paranoid "someone might have enabled VGA while we were not looking"
15786          * level, just check if the power well is enabled instead of trying to
15787          * follow the "don't touch the power well if we don't need it" policy
15788          * the rest of the driver uses. */
15789         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15790                 return;
15791
15792         i915_redisable_vga_power_on(dev);
15793 }
15794
15795 static bool primary_get_hw_state(struct intel_plane *plane)
15796 {
15797         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15798
15799         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15800 }
15801
15802 /* FIXME read out full plane state for all planes */
15803 static void readout_plane_state(struct intel_crtc *crtc)
15804 {
15805         struct drm_plane *primary = crtc->base.primary;
15806         struct intel_plane_state *plane_state =
15807                 to_intel_plane_state(primary->state);
15808
15809         plane_state->visible = crtc->active &&
15810                 primary_get_hw_state(to_intel_plane(primary));
15811
15812         if (plane_state->visible)
15813                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15814 }
15815
15816 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15817 {
15818         struct drm_i915_private *dev_priv = dev->dev_private;
15819         enum pipe pipe;
15820         struct intel_crtc *crtc;
15821         struct intel_encoder *encoder;
15822         struct intel_connector *connector;
15823         int i;
15824
15825         dev_priv->active_crtcs = 0;
15826
15827         for_each_intel_crtc(dev, crtc) {
15828                 struct intel_crtc_state *crtc_state = crtc->config;
15829                 int pixclk = 0;
15830
15831                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15832                 memset(crtc_state, 0, sizeof(*crtc_state));
15833                 crtc_state->base.crtc = &crtc->base;
15834
15835                 crtc_state->base.active = crtc_state->base.enable =
15836                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15837
15838                 crtc->base.enabled = crtc_state->base.enable;
15839                 crtc->active = crtc_state->base.active;
15840
15841                 if (crtc_state->base.active) {
15842                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15843
15844                         if (IS_BROADWELL(dev_priv)) {
15845                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15846
15847                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15848                                 if (crtc_state->ips_enabled)
15849                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15850                         } else if (IS_VALLEYVIEW(dev_priv) ||
15851                                    IS_CHERRYVIEW(dev_priv) ||
15852                                    IS_BROXTON(dev_priv))
15853                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15854                         else
15855                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15856                 }
15857
15858                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15859
15860                 readout_plane_state(crtc);
15861
15862                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15863                               crtc->base.base.id,
15864                               crtc->active ? "enabled" : "disabled");
15865         }
15866
15867         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15868                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15869
15870                 pll->on = pll->get_hw_state(dev_priv, pll,
15871                                             &pll->config.hw_state);
15872                 pll->active = 0;
15873                 pll->config.crtc_mask = 0;
15874                 for_each_intel_crtc(dev, crtc) {
15875                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15876                                 pll->active++;
15877                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15878                         }
15879                 }
15880
15881                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15882                               pll->name, pll->config.crtc_mask, pll->on);
15883
15884                 if (pll->config.crtc_mask)
15885                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15886         }
15887
15888         for_each_intel_encoder(dev, encoder) {
15889                 pipe = 0;
15890
15891                 if (encoder->get_hw_state(encoder, &pipe)) {
15892                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15893                         encoder->base.crtc = &crtc->base;
15894                         encoder->get_config(encoder, crtc->config);
15895                 } else {
15896                         encoder->base.crtc = NULL;
15897                 }
15898
15899                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15900                               encoder->base.base.id,
15901                               encoder->base.name,
15902                               encoder->base.crtc ? "enabled" : "disabled",
15903                               pipe_name(pipe));
15904         }
15905
15906         for_each_intel_connector(dev, connector) {
15907                 if (connector->get_hw_state(connector)) {
15908                         connector->base.dpms = DRM_MODE_DPMS_ON;
15909                         connector->base.encoder = &connector->encoder->base;
15910                 } else {
15911                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15912                         connector->base.encoder = NULL;
15913                 }
15914                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15915                               connector->base.base.id,
15916                               connector->base.name,
15917                               connector->base.encoder ? "enabled" : "disabled");
15918         }
15919
15920         for_each_intel_crtc(dev, crtc) {
15921                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15922
15923                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15924                 if (crtc->base.state->active) {
15925                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15926                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15927                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15928
15929                         /*
15930                          * The initial mode needs to be set in order to keep
15931                          * the atomic core happy. It wants a valid mode if the
15932                          * crtc's enabled, so we do the above call.
15933                          *
15934                          * At this point some state updated by the connectors
15935                          * in their ->detect() callback has not run yet, so
15936                          * no recalculation can be done yet.
15937                          *
15938                          * Even if we could do a recalculation and modeset
15939                          * right now it would cause a double modeset if
15940                          * fbdev or userspace chooses a different initial mode.
15941                          *
15942                          * If that happens, someone indicated they wanted a
15943                          * mode change, which means it's safe to do a full
15944                          * recalculation.
15945                          */
15946                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15947
15948                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15949                         update_scanline_offset(crtc);
15950                 }
15951         }
15952 }
15953
15954 /* Scan out the current hw modeset state,
15955  * and sanitizes it to the current state
15956  */
15957 static void
15958 intel_modeset_setup_hw_state(struct drm_device *dev)
15959 {
15960         struct drm_i915_private *dev_priv = dev->dev_private;
15961         enum pipe pipe;
15962         struct intel_crtc *crtc;
15963         struct intel_encoder *encoder;
15964         int i;
15965
15966         intel_modeset_readout_hw_state(dev);
15967
15968         /* HW state is read out, now we need to sanitize this mess. */
15969         for_each_intel_encoder(dev, encoder) {
15970                 intel_sanitize_encoder(encoder);
15971         }
15972
15973         for_each_pipe(dev_priv, pipe) {
15974                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15975                 intel_sanitize_crtc(crtc);
15976                 intel_dump_pipe_config(crtc, crtc->config,
15977                                        "[setup_hw_state]");
15978         }
15979
15980         intel_modeset_update_connector_atomic_state(dev);
15981
15982         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15983                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15984
15985                 if (!pll->on || pll->active)
15986                         continue;
15987
15988                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15989
15990                 pll->disable(dev_priv, pll);
15991                 pll->on = false;
15992         }
15993
15994         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15995                 vlv_wm_get_hw_state(dev);
15996         else if (IS_GEN9(dev))
15997                 skl_wm_get_hw_state(dev);
15998         else if (HAS_PCH_SPLIT(dev))
15999                 ilk_wm_get_hw_state(dev);
16000
16001         for_each_intel_crtc(dev, crtc) {
16002                 unsigned long put_domains;
16003
16004                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
16005                 if (WARN_ON(put_domains))
16006                         modeset_put_power_domains(dev_priv, put_domains);
16007         }
16008         intel_display_set_init_power(dev_priv, false);
16009 }
16010
16011 void intel_display_resume(struct drm_device *dev)
16012 {
16013         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
16014         struct intel_connector *conn;
16015         struct intel_plane *plane;
16016         struct drm_crtc *crtc;
16017         int ret;
16018
16019         if (!state)
16020                 return;
16021
16022         state->acquire_ctx = dev->mode_config.acquire_ctx;
16023
16024         /* preserve complete old state, including dpll */
16025         intel_atomic_get_shared_dpll_state(state);
16026
16027         for_each_crtc(dev, crtc) {
16028                 struct drm_crtc_state *crtc_state =
16029                         drm_atomic_get_crtc_state(state, crtc);
16030
16031                 ret = PTR_ERR_OR_ZERO(crtc_state);
16032                 if (ret)
16033                         goto err;
16034
16035                 /* force a restore */
16036                 crtc_state->mode_changed = true;
16037         }
16038
16039         for_each_intel_plane(dev, plane) {
16040                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
16041                 if (ret)
16042                         goto err;
16043         }
16044
16045         for_each_intel_connector(dev, conn) {
16046                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
16047                 if (ret)
16048                         goto err;
16049         }
16050
16051         intel_modeset_setup_hw_state(dev);
16052
16053         i915_redisable_vga(dev);
16054         ret = drm_atomic_commit(state);
16055         if (!ret)
16056                 return;
16057
16058 err:
16059         DRM_ERROR("Restoring old state failed with %i\n", ret);
16060         drm_atomic_state_free(state);
16061 }
16062
16063 void intel_modeset_gem_init(struct drm_device *dev)
16064 {
16065         struct drm_crtc *c;
16066         struct drm_i915_gem_object *obj;
16067         int ret;
16068
16069         mutex_lock(&dev->struct_mutex);
16070         intel_init_gt_powersave(dev);
16071         mutex_unlock(&dev->struct_mutex);
16072
16073         intel_modeset_init_hw(dev);
16074
16075         intel_setup_overlay(dev);
16076
16077         /*
16078          * Make sure any fbs we allocated at startup are properly
16079          * pinned & fenced.  When we do the allocation it's too early
16080          * for this.
16081          */
16082         for_each_crtc(dev, c) {
16083                 obj = intel_fb_obj(c->primary->fb);
16084                 if (obj == NULL)
16085                         continue;
16086
16087                 mutex_lock(&dev->struct_mutex);
16088                 ret = intel_pin_and_fence_fb_obj(c->primary,
16089                                                  c->primary->fb,
16090                                                  c->primary->state);
16091                 mutex_unlock(&dev->struct_mutex);
16092                 if (ret) {
16093                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16094                                   to_intel_crtc(c)->pipe);
16095                         drm_framebuffer_unreference(c->primary->fb);
16096                         c->primary->fb = NULL;
16097                         c->primary->crtc = c->primary->state->crtc = NULL;
16098                         update_state_fb(c->primary);
16099                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16100                 }
16101         }
16102
16103         intel_backlight_register(dev);
16104 }
16105
16106 void intel_connector_unregister(struct intel_connector *intel_connector)
16107 {
16108         struct drm_connector *connector = &intel_connector->base;
16109
16110         intel_panel_destroy_backlight(connector);
16111         drm_connector_unregister(connector);
16112 }
16113
16114 void intel_modeset_cleanup(struct drm_device *dev)
16115 {
16116         struct drm_i915_private *dev_priv = dev->dev_private;
16117         struct intel_connector *connector;
16118
16119         intel_disable_gt_powersave(dev);
16120
16121         intel_backlight_unregister(dev);
16122
16123         /*
16124          * Interrupts and polling as the first thing to avoid creating havoc.
16125          * Too much stuff here (turning of connectors, ...) would
16126          * experience fancy races otherwise.
16127          */
16128         intel_irq_uninstall(dev_priv);
16129
16130         /*
16131          * Due to the hpd irq storm handling the hotplug work can re-arm the
16132          * poll handlers. Hence disable polling after hpd handling is shut down.
16133          */
16134         drm_kms_helper_poll_fini(dev);
16135
16136         intel_unregister_dsm_handler();
16137
16138         intel_fbc_disable(dev_priv);
16139
16140         /* flush any delayed tasks or pending work */
16141         flush_scheduled_work();
16142
16143         /* destroy the backlight and sysfs files before encoders/connectors */
16144         for_each_intel_connector(dev, connector)
16145                 connector->unregister(connector);
16146
16147         drm_mode_config_cleanup(dev);
16148
16149         intel_cleanup_overlay(dev);
16150
16151         mutex_lock(&dev->struct_mutex);
16152         intel_cleanup_gt_powersave(dev);
16153         mutex_unlock(&dev->struct_mutex);
16154 }
16155
16156 /*
16157  * Return which encoder is currently attached for connector.
16158  */
16159 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16160 {
16161         return &intel_attached_encoder(connector)->base;
16162 }
16163
16164 void intel_connector_attach_encoder(struct intel_connector *connector,
16165                                     struct intel_encoder *encoder)
16166 {
16167         connector->encoder = encoder;
16168         drm_mode_connector_attach_encoder(&connector->base,
16169                                           &encoder->base);
16170 }
16171
16172 /*
16173  * set vga decode state - true == enable VGA decode
16174  */
16175 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16176 {
16177         struct drm_i915_private *dev_priv = dev->dev_private;
16178         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16179         u16 gmch_ctrl;
16180
16181         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16182                 DRM_ERROR("failed to read control word\n");
16183                 return -EIO;
16184         }
16185
16186         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16187                 return 0;
16188
16189         if (state)
16190                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16191         else
16192                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16193
16194         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16195                 DRM_ERROR("failed to write control word\n");
16196                 return -EIO;
16197         }
16198
16199         return 0;
16200 }
16201
16202 struct intel_display_error_state {
16203
16204         u32 power_well_driver;
16205
16206         int num_transcoders;
16207
16208         struct intel_cursor_error_state {
16209                 u32 control;
16210                 u32 position;
16211                 u32 base;
16212                 u32 size;
16213         } cursor[I915_MAX_PIPES];
16214
16215         struct intel_pipe_error_state {
16216                 bool power_domain_on;
16217                 u32 source;
16218                 u32 stat;
16219         } pipe[I915_MAX_PIPES];
16220
16221         struct intel_plane_error_state {
16222                 u32 control;
16223                 u32 stride;
16224                 u32 size;
16225                 u32 pos;
16226                 u32 addr;
16227                 u32 surface;
16228                 u32 tile_offset;
16229         } plane[I915_MAX_PIPES];
16230
16231         struct intel_transcoder_error_state {
16232                 bool power_domain_on;
16233                 enum transcoder cpu_transcoder;
16234
16235                 u32 conf;
16236
16237                 u32 htotal;
16238                 u32 hblank;
16239                 u32 hsync;
16240                 u32 vtotal;
16241                 u32 vblank;
16242                 u32 vsync;
16243         } transcoder[4];
16244 };
16245
16246 struct intel_display_error_state *
16247 intel_display_capture_error_state(struct drm_device *dev)
16248 {
16249         struct drm_i915_private *dev_priv = dev->dev_private;
16250         struct intel_display_error_state *error;
16251         int transcoders[] = {
16252                 TRANSCODER_A,
16253                 TRANSCODER_B,
16254                 TRANSCODER_C,
16255                 TRANSCODER_EDP,
16256         };
16257         int i;
16258
16259         if (INTEL_INFO(dev)->num_pipes == 0)
16260                 return NULL;
16261
16262         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16263         if (error == NULL)
16264                 return NULL;
16265
16266         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16267                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16268
16269         for_each_pipe(dev_priv, i) {
16270                 error->pipe[i].power_domain_on =
16271                         __intel_display_power_is_enabled(dev_priv,
16272                                                          POWER_DOMAIN_PIPE(i));
16273                 if (!error->pipe[i].power_domain_on)
16274                         continue;
16275
16276                 error->cursor[i].control = I915_READ(CURCNTR(i));
16277                 error->cursor[i].position = I915_READ(CURPOS(i));
16278                 error->cursor[i].base = I915_READ(CURBASE(i));
16279
16280                 error->plane[i].control = I915_READ(DSPCNTR(i));
16281                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16282                 if (INTEL_INFO(dev)->gen <= 3) {
16283                         error->plane[i].size = I915_READ(DSPSIZE(i));
16284                         error->plane[i].pos = I915_READ(DSPPOS(i));
16285                 }
16286                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16287                         error->plane[i].addr = I915_READ(DSPADDR(i));
16288                 if (INTEL_INFO(dev)->gen >= 4) {
16289                         error->plane[i].surface = I915_READ(DSPSURF(i));
16290                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16291                 }
16292
16293                 error->pipe[i].source = I915_READ(PIPESRC(i));
16294
16295                 if (HAS_GMCH_DISPLAY(dev))
16296                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16297         }
16298
16299         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16300         if (HAS_DDI(dev_priv->dev))
16301                 error->num_transcoders++; /* Account for eDP. */
16302
16303         for (i = 0; i < error->num_transcoders; i++) {
16304                 enum transcoder cpu_transcoder = transcoders[i];
16305
16306                 error->transcoder[i].power_domain_on =
16307                         __intel_display_power_is_enabled(dev_priv,
16308                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16309                 if (!error->transcoder[i].power_domain_on)
16310                         continue;
16311
16312                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16313
16314                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16315                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16316                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16317                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16318                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16319                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16320                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16321         }
16322
16323         return error;
16324 }
16325
16326 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16327
16328 void
16329 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16330                                 struct drm_device *dev,
16331                                 struct intel_display_error_state *error)
16332 {
16333         struct drm_i915_private *dev_priv = dev->dev_private;
16334         int i;
16335
16336         if (!error)
16337                 return;
16338
16339         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16340         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16341                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16342                            error->power_well_driver);
16343         for_each_pipe(dev_priv, i) {
16344                 err_printf(m, "Pipe [%d]:\n", i);
16345                 err_printf(m, "  Power: %s\n",
16346                            error->pipe[i].power_domain_on ? "on" : "off");
16347                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16348                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16349
16350                 err_printf(m, "Plane [%d]:\n", i);
16351                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16352                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16353                 if (INTEL_INFO(dev)->gen <= 3) {
16354                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16355                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16356                 }
16357                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16358                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16359                 if (INTEL_INFO(dev)->gen >= 4) {
16360                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16361                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16362                 }
16363
16364                 err_printf(m, "Cursor [%d]:\n", i);
16365                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16366                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16367                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16368         }
16369
16370         for (i = 0; i < error->num_transcoders; i++) {
16371                 err_printf(m, "CPU transcoder: %c\n",
16372                            transcoder_name(error->transcoder[i].cpu_transcoder));
16373                 err_printf(m, "  Power: %s\n",
16374                            error->transcoder[i].power_domain_on ? "on" : "off");
16375                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16376                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16377                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16378                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16379                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16380                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16381                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16382         }
16383 }
16384
16385 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16386 {
16387         struct intel_crtc *crtc;
16388
16389         for_each_intel_crtc(dev, crtc) {
16390                 struct intel_unpin_work *work;
16391
16392                 spin_lock_irq(&dev->event_lock);
16393
16394                 work = crtc->unpin_work;
16395
16396                 if (work && work->event &&
16397                     work->event->base.file_priv == file) {
16398                         kfree(work->event);
16399                         work->event = NULL;
16400                 }
16401
16402                 spin_unlock_irq(&dev->event_lock);
16403         }
16404 }