drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265
2266         i915_gem_object_pin_fence(obj);
2267
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343
2344         if (plane_config->size == 0)
2345                 return false;
2346
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362         mutex_lock(&dev->struct_mutex);
2363
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409
2410                 if (!i->active)
2411                         continue;
2412
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544
2545         I915_WRITE(reg, dspcntr);
2546
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648
2649         I915_WRITE(reg, dspcntr);
2650
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765         return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct drm_crtc *crtc;
2772
2773         /*
2774          * Flips in the rings have been nuked by the reset,
2775          * so complete all pending flips so that user space
2776          * will get its events and not get stuck.
2777          *
2778          * Also update the base address of all primary
2779          * planes to the the last fb to make sure we're
2780          * showing the correct fb after a reset.
2781          *
2782          * Need to make two loops over the crtcs so that we
2783          * don't try to grab a crtc mutex before the
2784          * pending_flip_queue really got woken up.
2785          */
2786
2787         for_each_crtc(dev, crtc) {
2788                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789                 enum plane plane = intel_crtc->plane;
2790
2791                 intel_prepare_page_flip(dev, plane);
2792                 intel_finish_page_flip_plane(dev, plane);
2793         }
2794
2795         for_each_crtc(dev, crtc) {
2796                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798                 drm_modeset_lock(&crtc->mutex, NULL);
2799                 /*
2800                  * FIXME: Once we have proper support for primary planes (and
2801                  * disabling them without disabling the entire crtc) allow again
2802                  * a NULL crtc->primary->fb.
2803                  */
2804                 if (intel_crtc->active && crtc->primary->fb)
2805                         dev_priv->display.update_primary_plane(crtc,
2806                                                                crtc->primary->fb,
2807                                                                crtc->x,
2808                                                                crtc->y);
2809                 drm_modeset_unlock(&crtc->mutex);
2810         }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818         bool was_interruptible = dev_priv->mm.interruptible;
2819         int ret;
2820
2821         /* Big Hammer, we also need to ensure that any pending
2822          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823          * current scanout is retired before unpinning the old
2824          * framebuffer.
2825          *
2826          * This should only fail upon a hung GPU, in which case we
2827          * can safely continue.
2828          */
2829         dev_priv->mm.interruptible = false;
2830         ret = i915_gem_object_finish_gpu(obj);
2831         dev_priv->mm.interruptible = was_interruptible;
2832
2833         return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841         bool pending;
2842
2843         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845                 return false;
2846
2847         spin_lock_irq(&dev->event_lock);
2848         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849         spin_unlock_irq(&dev->event_lock);
2850
2851         return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->base.dev;
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         const struct drm_display_mode *adjusted_mode;
2859
2860         if (!i915.fastboot)
2861                 return;
2862
2863         /*
2864          * Update pipe size and adjust fitter if needed: the reason for this is
2865          * that in compute_mode_changes we check the native mode (not the pfit
2866          * mode) to see if we can flip rather than do a full mode set. In the
2867          * fastboot case, we'll flip, but if we don't update the pipesrc and
2868          * pfit state, we'll end up with a big fb scanned out into the wrong
2869          * sized surface.
2870          *
2871          * To fix this properly, we need to hoist the checks up into
2872          * compute_mode_changes (or above), check the actual pfit state and
2873          * whether the platform allows pfit disable with pipe active, and only
2874          * then update the pipesrc and pfit state, even on the flip path.
2875          */
2876
2877         adjusted_mode = &crtc->config.adjusted_mode;
2878
2879         I915_WRITE(PIPESRC(crtc->pipe),
2880                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881                    (adjusted_mode->crtc_vdisplay - 1));
2882         if (!crtc->config.pch_pfit.enabled &&
2883             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888         }
2889         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895                     struct drm_framebuffer *fb)
2896 {
2897         struct drm_device *dev = crtc->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900         enum pipe pipe = intel_crtc->pipe;
2901         struct drm_framebuffer *old_fb = crtc->primary->fb;
2902         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903         int ret;
2904
2905         if (intel_crtc_has_pending_flip(crtc)) {
2906                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907                 return -EBUSY;
2908         }
2909
2910         /* no fb bound */
2911         if (!fb) {
2912                 DRM_ERROR("No FB bound\n");
2913                 return 0;
2914         }
2915
2916         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918                           plane_name(intel_crtc->plane),
2919                           INTEL_INFO(dev)->num_pipes);
2920                 return -EINVAL;
2921         }
2922
2923         mutex_lock(&dev->struct_mutex);
2924         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925         if (ret == 0)
2926                 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2928         mutex_unlock(&dev->struct_mutex);
2929         if (ret != 0) {
2930                 DRM_ERROR("pin & fence failed\n");
2931                 return ret;
2932         }
2933
2934         intel_update_pipe_size(intel_crtc);
2935
2936         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2937
2938         if (intel_crtc->active)
2939                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2940
2941         crtc->primary->fb = fb;
2942         crtc->x = x;
2943         crtc->y = y;
2944
2945         if (old_fb) {
2946                 if (intel_crtc->active && old_fb != fb)
2947                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2948                 mutex_lock(&dev->struct_mutex);
2949                 intel_unpin_fb_obj(old_obj);
2950                 mutex_unlock(&dev->struct_mutex);
2951         }
2952
2953         mutex_lock(&dev->struct_mutex);
2954         intel_update_fbc(dev);
2955         mutex_unlock(&dev->struct_mutex);
2956
2957         return 0;
2958 }
2959
2960 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 {
2962         struct drm_device *dev = crtc->dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965         int pipe = intel_crtc->pipe;
2966         u32 reg, temp;
2967
2968         /* enable normal train */
2969         reg = FDI_TX_CTL(pipe);
2970         temp = I915_READ(reg);
2971         if (IS_IVYBRIDGE(dev)) {
2972                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974         } else {
2975                 temp &= ~FDI_LINK_TRAIN_NONE;
2976                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977         }
2978         I915_WRITE(reg, temp);
2979
2980         reg = FDI_RX_CTL(pipe);
2981         temp = I915_READ(reg);
2982         if (HAS_PCH_CPT(dev)) {
2983                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985         } else {
2986                 temp &= ~FDI_LINK_TRAIN_NONE;
2987                 temp |= FDI_LINK_TRAIN_NONE;
2988         }
2989         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991         /* wait one idle pattern time */
2992         POSTING_READ(reg);
2993         udelay(1000);
2994
2995         /* IVB wants error correction enabled */
2996         if (IS_IVYBRIDGE(dev))
2997                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998                            FDI_FE_ERRC_ENABLE);
2999 }
3000
3001 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 {
3003         return crtc->base.enabled && crtc->active &&
3004                 crtc->config.has_pch_encoder;
3005 }
3006
3007 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 {
3009         struct drm_i915_private *dev_priv = dev->dev_private;
3010         struct intel_crtc *pipe_B_crtc =
3011                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012         struct intel_crtc *pipe_C_crtc =
3013                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014         uint32_t temp;
3015
3016         /*
3017          * When everything is off disable fdi C so that we could enable fdi B
3018          * with all lanes. Note that we don't care about enabled pipes without
3019          * an enabled pch encoder.
3020          */
3021         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022             !pipe_has_enabled_pch(pipe_C_crtc)) {
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026                 temp = I915_READ(SOUTH_CHICKEN1);
3027                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029                 I915_WRITE(SOUTH_CHICKEN1, temp);
3030         }
3031 }
3032
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036         struct drm_device *dev = crtc->dev;
3037         struct drm_i915_private *dev_priv = dev->dev_private;
3038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039         int pipe = intel_crtc->pipe;
3040         u32 reg, temp, tries;
3041
3042         /* FDI needs bits from pipe first */
3043         assert_pipe_enabled(dev_priv, pipe);
3044
3045         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046            for train result */
3047         reg = FDI_RX_IMR(pipe);
3048         temp = I915_READ(reg);
3049         temp &= ~FDI_RX_SYMBOL_LOCK;
3050         temp &= ~FDI_RX_BIT_LOCK;
3051         I915_WRITE(reg, temp);
3052         I915_READ(reg);
3053         udelay(150);
3054
3055         /* enable CPU FDI TX and PCH FDI RX */
3056         reg = FDI_TX_CTL(pipe);
3057         temp = I915_READ(reg);
3058         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3060         temp &= ~FDI_LINK_TRAIN_NONE;
3061         temp |= FDI_LINK_TRAIN_PATTERN_1;
3062         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063
3064         reg = FDI_RX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         temp &= ~FDI_LINK_TRAIN_NONE;
3067         temp |= FDI_LINK_TRAIN_PATTERN_1;
3068         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070         POSTING_READ(reg);
3071         udelay(150);
3072
3073         /* Ironlake workaround, enable clock pointer after FDI enable*/
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076                    FDI_RX_PHASE_SYNC_POINTER_EN);
3077
3078         reg = FDI_RX_IIR(pipe);
3079         for (tries = 0; tries < 5; tries++) {
3080                 temp = I915_READ(reg);
3081                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083                 if ((temp & FDI_RX_BIT_LOCK)) {
3084                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3085                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3086                         break;
3087                 }
3088         }
3089         if (tries == 5)
3090                 DRM_ERROR("FDI train 1 fail!\n");
3091
3092         /* Train 2 */
3093         reg = FDI_TX_CTL(pipe);
3094         temp = I915_READ(reg);
3095         temp &= ~FDI_LINK_TRAIN_NONE;
3096         temp |= FDI_LINK_TRAIN_PATTERN_2;
3097         I915_WRITE(reg, temp);
3098
3099         reg = FDI_RX_CTL(pipe);
3100         temp = I915_READ(reg);
3101         temp &= ~FDI_LINK_TRAIN_NONE;
3102         temp |= FDI_LINK_TRAIN_PATTERN_2;
3103         I915_WRITE(reg, temp);
3104
3105         POSTING_READ(reg);
3106         udelay(150);
3107
3108         reg = FDI_RX_IIR(pipe);
3109         for (tries = 0; tries < 5; tries++) {
3110                 temp = I915_READ(reg);
3111                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113                 if (temp & FDI_RX_SYMBOL_LOCK) {
3114                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3115                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3116                         break;
3117                 }
3118         }
3119         if (tries == 5)
3120                 DRM_ERROR("FDI train 2 fail!\n");
3121
3122         DRM_DEBUG_KMS("FDI train done\n");
3123
3124 }
3125
3126 static const int snb_b_fdi_train_param[] = {
3127         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131 };
3132
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 {
3136         struct drm_device *dev = crtc->dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139         int pipe = intel_crtc->pipe;
3140         u32 reg, temp, i, retry;
3141
3142         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143            for train result */
3144         reg = FDI_RX_IMR(pipe);
3145         temp = I915_READ(reg);
3146         temp &= ~FDI_RX_SYMBOL_LOCK;
3147         temp &= ~FDI_RX_BIT_LOCK;
3148         I915_WRITE(reg, temp);
3149
3150         POSTING_READ(reg);
3151         udelay(150);
3152
3153         /* enable CPU FDI TX and PCH FDI RX */
3154         reg = FDI_TX_CTL(pipe);
3155         temp = I915_READ(reg);
3156         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3158         temp &= ~FDI_LINK_TRAIN_NONE;
3159         temp |= FDI_LINK_TRAIN_PATTERN_1;
3160         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161         /* SNB-B */
3162         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3163         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164
3165         I915_WRITE(FDI_RX_MISC(pipe),
3166                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
3168         reg = FDI_RX_CTL(pipe);
3169         temp = I915_READ(reg);
3170         if (HAS_PCH_CPT(dev)) {
3171                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173         } else {
3174                 temp &= ~FDI_LINK_TRAIN_NONE;
3175                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176         }
3177         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179         POSTING_READ(reg);
3180         udelay(150);
3181
3182         for (i = 0; i < 4; i++) {
3183                 reg = FDI_TX_CTL(pipe);
3184                 temp = I915_READ(reg);
3185                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186                 temp |= snb_b_fdi_train_param[i];
3187                 I915_WRITE(reg, temp);
3188
3189                 POSTING_READ(reg);
3190                 udelay(500);
3191
3192                 for (retry = 0; retry < 5; retry++) {
3193                         reg = FDI_RX_IIR(pipe);
3194                         temp = I915_READ(reg);
3195                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196                         if (temp & FDI_RX_BIT_LOCK) {
3197                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199                                 break;
3200                         }
3201                         udelay(50);
3202                 }
3203                 if (retry < 5)
3204                         break;
3205         }
3206         if (i == 4)
3207                 DRM_ERROR("FDI train 1 fail!\n");
3208
3209         /* Train 2 */
3210         reg = FDI_TX_CTL(pipe);
3211         temp = I915_READ(reg);
3212         temp &= ~FDI_LINK_TRAIN_NONE;
3213         temp |= FDI_LINK_TRAIN_PATTERN_2;
3214         if (IS_GEN6(dev)) {
3215                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216                 /* SNB-B */
3217                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218         }
3219         I915_WRITE(reg, temp);
3220
3221         reg = FDI_RX_CTL(pipe);
3222         temp = I915_READ(reg);
3223         if (HAS_PCH_CPT(dev)) {
3224                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226         } else {
3227                 temp &= ~FDI_LINK_TRAIN_NONE;
3228                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229         }
3230         I915_WRITE(reg, temp);
3231
3232         POSTING_READ(reg);
3233         udelay(150);
3234
3235         for (i = 0; i < 4; i++) {
3236                 reg = FDI_TX_CTL(pipe);
3237                 temp = I915_READ(reg);
3238                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239                 temp |= snb_b_fdi_train_param[i];
3240                 I915_WRITE(reg, temp);
3241
3242                 POSTING_READ(reg);
3243                 udelay(500);
3244
3245                 for (retry = 0; retry < 5; retry++) {
3246                         reg = FDI_RX_IIR(pipe);
3247                         temp = I915_READ(reg);
3248                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249                         if (temp & FDI_RX_SYMBOL_LOCK) {
3250                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252                                 break;
3253                         }
3254                         udelay(50);
3255                 }
3256                 if (retry < 5)
3257                         break;
3258         }
3259         if (i == 4)
3260                 DRM_ERROR("FDI train 2 fail!\n");
3261
3262         DRM_DEBUG_KMS("FDI train done.\n");
3263 }
3264
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 {
3268         struct drm_device *dev = crtc->dev;
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271         int pipe = intel_crtc->pipe;
3272         u32 reg, temp, i, j;
3273
3274         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275            for train result */
3276         reg = FDI_RX_IMR(pipe);
3277         temp = I915_READ(reg);
3278         temp &= ~FDI_RX_SYMBOL_LOCK;
3279         temp &= ~FDI_RX_BIT_LOCK;
3280         I915_WRITE(reg, temp);
3281
3282         POSTING_READ(reg);
3283         udelay(150);
3284
3285         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286                       I915_READ(FDI_RX_IIR(pipe)));
3287
3288         /* Try each vswing and preemphasis setting twice before moving on */
3289         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290                 /* disable first in case we need to retry */
3291                 reg = FDI_TX_CTL(pipe);
3292                 temp = I915_READ(reg);
3293                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294                 temp &= ~FDI_TX_ENABLE;
3295                 I915_WRITE(reg, temp);
3296
3297                 reg = FDI_RX_CTL(pipe);
3298                 temp = I915_READ(reg);
3299                 temp &= ~FDI_LINK_TRAIN_AUTO;
3300                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301                 temp &= ~FDI_RX_ENABLE;
3302                 I915_WRITE(reg, temp);
3303
3304                 /* enable CPU FDI TX and PCH FDI RX */
3305                 reg = FDI_TX_CTL(pipe);
3306                 temp = I915_READ(reg);
3307                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3309                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311                 temp |= snb_b_fdi_train_param[j/2];
3312                 temp |= FDI_COMPOSITE_SYNC;
3313                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315                 I915_WRITE(FDI_RX_MISC(pipe),
3316                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318                 reg = FDI_RX_CTL(pipe);
3319                 temp = I915_READ(reg);
3320                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321                 temp |= FDI_COMPOSITE_SYNC;
3322                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324                 POSTING_READ(reg);
3325                 udelay(1); /* should be 0.5us */
3326
3327                 for (i = 0; i < 4; i++) {
3328                         reg = FDI_RX_IIR(pipe);
3329                         temp = I915_READ(reg);
3330                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332                         if (temp & FDI_RX_BIT_LOCK ||
3333                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336                                               i);
3337                                 break;
3338                         }
3339                         udelay(1); /* should be 0.5us */
3340                 }
3341                 if (i == 4) {
3342                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343                         continue;
3344                 }
3345
3346                 /* Train 2 */
3347                 reg = FDI_TX_CTL(pipe);
3348                 temp = I915_READ(reg);
3349                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351                 I915_WRITE(reg, temp);
3352
3353                 reg = FDI_RX_CTL(pipe);
3354                 temp = I915_READ(reg);
3355                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3357                 I915_WRITE(reg, temp);
3358
3359                 POSTING_READ(reg);
3360                 udelay(2); /* should be 1.5us */
3361
3362                 for (i = 0; i < 4; i++) {
3363                         reg = FDI_RX_IIR(pipe);
3364                         temp = I915_READ(reg);
3365                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367                         if (temp & FDI_RX_SYMBOL_LOCK ||
3368                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371                                               i);
3372                                 goto train_done;
3373                         }
3374                         udelay(2); /* should be 1.5us */
3375                 }
3376                 if (i == 4)
3377                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3378         }
3379
3380 train_done:
3381         DRM_DEBUG_KMS("FDI train done.\n");
3382 }
3383
3384 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 {
3386         struct drm_device *dev = intel_crtc->base.dev;
3387         struct drm_i915_private *dev_priv = dev->dev_private;
3388         int pipe = intel_crtc->pipe;
3389         u32 reg, temp;
3390
3391
3392         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393         reg = FDI_RX_CTL(pipe);
3394         temp = I915_READ(reg);
3395         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3397         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400         POSTING_READ(reg);
3401         udelay(200);
3402
3403         /* Switch from Rawclk to PCDclk */
3404         temp = I915_READ(reg);
3405         I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407         POSTING_READ(reg);
3408         udelay(200);
3409
3410         /* Enable CPU FDI TX PLL, always on for Ironlake */
3411         reg = FDI_TX_CTL(pipe);
3412         temp = I915_READ(reg);
3413         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3415
3416                 POSTING_READ(reg);
3417                 udelay(100);
3418         }
3419 }
3420
3421 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 {
3423         struct drm_device *dev = intel_crtc->base.dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         int pipe = intel_crtc->pipe;
3426         u32 reg, temp;
3427
3428         /* Switch from PCDclk to Rawclk */
3429         reg = FDI_RX_CTL(pipe);
3430         temp = I915_READ(reg);
3431         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433         /* Disable CPU FDI TX PLL */
3434         reg = FDI_TX_CTL(pipe);
3435         temp = I915_READ(reg);
3436         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438         POSTING_READ(reg);
3439         udelay(100);
3440
3441         reg = FDI_RX_CTL(pipe);
3442         temp = I915_READ(reg);
3443         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445         /* Wait for the clocks to turn off. */
3446         POSTING_READ(reg);
3447         udelay(100);
3448 }
3449
3450 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 {
3452         struct drm_device *dev = crtc->dev;
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455         int pipe = intel_crtc->pipe;
3456         u32 reg, temp;
3457
3458         /* disable CPU FDI tx and PCH FDI rx */
3459         reg = FDI_TX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462         POSTING_READ(reg);
3463
3464         reg = FDI_RX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         temp &= ~(0x7 << 16);
3467         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470         POSTING_READ(reg);
3471         udelay(100);
3472
3473         /* Ironlake workaround, disable clock pointer after downing FDI */
3474         if (HAS_PCH_IBX(dev))
3475                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476
3477         /* still set train pattern 1 */
3478         reg = FDI_TX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         temp &= ~FDI_LINK_TRAIN_NONE;
3481         temp |= FDI_LINK_TRAIN_PATTERN_1;
3482         I915_WRITE(reg, temp);
3483
3484         reg = FDI_RX_CTL(pipe);
3485         temp = I915_READ(reg);
3486         if (HAS_PCH_CPT(dev)) {
3487                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489         } else {
3490                 temp &= ~FDI_LINK_TRAIN_NONE;
3491                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492         }
3493         /* BPC in FDI rx is consistent with that in PIPECONF */
3494         temp &= ~(0x07 << 16);
3495         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496         I915_WRITE(reg, temp);
3497
3498         POSTING_READ(reg);
3499         udelay(100);
3500 }
3501
3502 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 {
3504         struct intel_crtc *crtc;
3505
3506         /* Note that we don't need to be called with mode_config.lock here
3507          * as our list of CRTC objects is static for the lifetime of the
3508          * device and so cannot disappear as we iterate. Similarly, we can
3509          * happily treat the predicates as racy, atomic checks as userspace
3510          * cannot claim and pin a new fb without at least acquring the
3511          * struct_mutex and so serialising with us.
3512          */
3513         for_each_intel_crtc(dev, crtc) {
3514                 if (atomic_read(&crtc->unpin_work_count) == 0)
3515                         continue;
3516
3517                 if (crtc->unpin_work)
3518                         intel_wait_for_vblank(dev, crtc->pipe);
3519
3520                 return true;
3521         }
3522
3523         return false;
3524 }
3525
3526 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 {
3528         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529         struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531         /* ensure that the unpin work is consistent wrt ->pending. */
3532         smp_rmb();
3533         intel_crtc->unpin_work = NULL;
3534
3535         if (work->event)
3536                 drm_send_vblank_event(intel_crtc->base.dev,
3537                                       intel_crtc->pipe,
3538                                       work->event);
3539
3540         drm_crtc_vblank_put(&intel_crtc->base);
3541
3542         wake_up_all(&dev_priv->pending_flip_queue);
3543         queue_work(dev_priv->wq, &work->work);
3544
3545         trace_i915_flip_complete(intel_crtc->plane,
3546                                  work->pending_flip_obj);
3547 }
3548
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 {
3551         struct drm_device *dev = crtc->dev;
3552         struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3555         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556                                        !intel_crtc_has_pending_flip(crtc),
3557                                        60*HZ) == 0)) {
3558                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560                 spin_lock_irq(&dev->event_lock);
3561                 if (intel_crtc->unpin_work) {
3562                         WARN_ONCE(1, "Removing stuck page flip\n");
3563                         page_flip_completed(intel_crtc);
3564                 }
3565                 spin_unlock_irq(&dev->event_lock);
3566         }
3567
3568         if (crtc->primary->fb) {
3569                 mutex_lock(&dev->struct_mutex);
3570                 intel_finish_fb(crtc->primary->fb);
3571                 mutex_unlock(&dev->struct_mutex);
3572         }
3573 }
3574
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3581         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582         u32 temp;
3583
3584         mutex_lock(&dev_priv->dpio_lock);
3585
3586         /* It is necessary to ungate the pixclk gate prior to programming
3587          * the divisors, and gate it back when it is done.
3588          */
3589         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591         /* Disable SSCCTL */
3592         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3593                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594                                 SBI_SSCCTL_DISABLE,
3595                         SBI_ICLK);
3596
3597         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598         if (clock == 20000) {
3599                 auxdiv = 1;
3600                 divsel = 0x41;
3601                 phaseinc = 0x20;
3602         } else {
3603                 /* The iCLK virtual clock root frequency is in MHz,
3604                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3605                  * divisors, it is necessary to divide one by another, so we
3606                  * convert the virtual clock precision to KHz here for higher
3607                  * precision.
3608                  */
3609                 u32 iclk_virtual_root_freq = 172800 * 1000;
3610                 u32 iclk_pi_range = 64;
3611                 u32 desired_divisor, msb_divisor_value, pi_value;
3612
3613                 desired_divisor = (iclk_virtual_root_freq / clock);
3614                 msb_divisor_value = desired_divisor / iclk_pi_range;
3615                 pi_value = desired_divisor % iclk_pi_range;
3616
3617                 auxdiv = 0;
3618                 divsel = msb_divisor_value - 2;
3619                 phaseinc = pi_value;
3620         }
3621
3622         /* This should not happen with any sane values */
3623         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3629                         clock,
3630                         auxdiv,
3631                         divsel,
3632                         phasedir,
3633                         phaseinc);
3634
3635         /* Program SSCDIVINTPHASE6 */
3636         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3637         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3643         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644
3645         /* Program SSCAUXDIV */
3646         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3647         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3649         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650
3651         /* Enable modulator and associated divider */
3652         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3653         temp &= ~SBI_SSCCTL_DISABLE;
3654         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655
3656         /* Wait for initialization time */
3657         udelay(24);
3658
3659         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660
3661         mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665                                                 enum pipe pch_transcoder)
3666 {
3667         struct drm_device *dev = crtc->base.dev;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3670
3671         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672                    I915_READ(HTOTAL(cpu_transcoder)));
3673         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674                    I915_READ(HBLANK(cpu_transcoder)));
3675         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676                    I915_READ(HSYNC(cpu_transcoder)));
3677
3678         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679                    I915_READ(VTOTAL(cpu_transcoder)));
3680         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681                    I915_READ(VBLANK(cpu_transcoder)));
3682         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683                    I915_READ(VSYNC(cpu_transcoder)));
3684         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686 }
3687
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 {
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         uint32_t temp;
3692
3693         temp = I915_READ(SOUTH_CHICKEN1);
3694         if (temp & FDI_BC_BIFURCATION_SELECT)
3695                 return;
3696
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700         temp |= FDI_BC_BIFURCATION_SELECT;
3701         DRM_DEBUG_KMS("enabling fdi C rx\n");
3702         I915_WRITE(SOUTH_CHICKEN1, temp);
3703         POSTING_READ(SOUTH_CHICKEN1);
3704 }
3705
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 {
3708         struct drm_device *dev = intel_crtc->base.dev;
3709         struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711         switch (intel_crtc->pipe) {
3712         case PIPE_A:
3713                 break;
3714         case PIPE_B:
3715                 if (intel_crtc->config.fdi_lanes > 2)
3716                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717                 else
3718                         cpt_enable_fdi_bc_bifurcation(dev);
3719
3720                 break;
3721         case PIPE_C:
3722                 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724                 break;
3725         default:
3726                 BUG();
3727         }
3728 }
3729
3730 /*
3731  * Enable PCH resources required for PCH ports:
3732  *   - PCH PLLs
3733  *   - FDI training & RX/TX
3734  *   - update transcoder timings
3735  *   - DP transcoding bits
3736  *   - transcoder
3737  */
3738 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 {
3740         struct drm_device *dev = crtc->dev;
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743         int pipe = intel_crtc->pipe;
3744         u32 reg, temp;
3745
3746         assert_pch_transcoder_disabled(dev_priv, pipe);
3747
3748         if (IS_IVYBRIDGE(dev))
3749                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
3751         /* Write the TU size bits before fdi link training, so that error
3752          * detection works. */
3753         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
3756         /* For PCH output, training FDI link */
3757         dev_priv->display.fdi_link_train(crtc);
3758
3759         /* We need to program the right clock selection before writing the pixel
3760          * mutliplier into the DPLL. */
3761         if (HAS_PCH_CPT(dev)) {
3762                 u32 sel;
3763
3764                 temp = I915_READ(PCH_DPLL_SEL);
3765                 temp |= TRANS_DPLL_ENABLE(pipe);
3766                 sel = TRANS_DPLLB_SEL(pipe);
3767                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3768                         temp |= sel;
3769                 else
3770                         temp &= ~sel;
3771                 I915_WRITE(PCH_DPLL_SEL, temp);
3772         }
3773
3774         /* XXX: pch pll's can be enabled any time before we enable the PCH
3775          * transcoder, and we actually should do this to not upset any PCH
3776          * transcoder that already use the clock when we share it.
3777          *
3778          * Note that enable_shared_dpll tries to do the right thing, but
3779          * get_shared_dpll unconditionally resets the pll - we need that to have
3780          * the right LVDS enable sequence. */
3781         intel_enable_shared_dpll(intel_crtc);
3782
3783         /* set transcoder timing, panel must allow it */
3784         assert_panel_unlocked(dev_priv, pipe);
3785         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786
3787         intel_fdi_normal_train(crtc);
3788
3789         /* For PCH DP, enable TRANS_DP_CTL */
3790         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3791                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792                 reg = TRANS_DP_CTL(pipe);
3793                 temp = I915_READ(reg);
3794                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3795                           TRANS_DP_SYNC_MASK |
3796                           TRANS_DP_BPC_MASK);
3797                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798                          TRANS_DP_ENH_FRAMING);
3799                 temp |= bpc << 9; /* same format but at 11:9 */
3800
3801                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3802                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3803                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3804                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805
3806                 switch (intel_trans_dp_port_sel(crtc)) {
3807                 case PCH_DP_B:
3808                         temp |= TRANS_DP_PORT_SEL_B;
3809                         break;
3810                 case PCH_DP_C:
3811                         temp |= TRANS_DP_PORT_SEL_C;
3812                         break;
3813                 case PCH_DP_D:
3814                         temp |= TRANS_DP_PORT_SEL_D;
3815                         break;
3816                 default:
3817                         BUG();
3818                 }
3819
3820                 I915_WRITE(reg, temp);
3821         }
3822
3823         ironlake_enable_pch_transcoder(dev_priv, pipe);
3824 }
3825
3826 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 {
3828         struct drm_device *dev = crtc->dev;
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3832
3833         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834
3835         lpt_program_iclkip(crtc);
3836
3837         /* Set transcoder timing. */
3838         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839
3840         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3841 }
3842
3843 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 {
3845         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3846
3847         if (pll == NULL)
3848                 return;
3849
3850         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3851                 WARN(1, "bad %s crtc mask\n", pll->name);
3852                 return;
3853         }
3854
3855         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856         if (pll->config.crtc_mask == 0) {
3857                 WARN_ON(pll->on);
3858                 WARN_ON(pll->active);
3859         }
3860
3861         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3862 }
3863
3864 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3865 {
3866         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3867         struct intel_shared_dpll *pll;
3868         enum intel_dpll_id i;
3869
3870         if (HAS_PCH_IBX(dev_priv->dev)) {
3871                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872                 i = (enum intel_dpll_id) crtc->pipe;
3873                 pll = &dev_priv->shared_dplls[i];
3874
3875                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876                               crtc->base.base.id, pll->name);
3877
3878                 WARN_ON(pll->new_config->crtc_mask);
3879
3880                 goto found;
3881         }
3882
3883         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3884                 pll = &dev_priv->shared_dplls[i];
3885
3886                 /* Only want to check enabled timings first */
3887                 if (pll->new_config->crtc_mask == 0)
3888                         continue;
3889
3890                 if (memcmp(&crtc->new_config->dpll_hw_state,
3891                            &pll->new_config->hw_state,
3892                            sizeof(pll->new_config->hw_state)) == 0) {
3893                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894                                       crtc->base.base.id, pll->name,
3895                                       pll->new_config->crtc_mask,
3896                                       pll->active);
3897                         goto found;
3898                 }
3899         }
3900
3901         /* Ok no matching timings, maybe there's a free one? */
3902         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3903                 pll = &dev_priv->shared_dplls[i];
3904                 if (pll->new_config->crtc_mask == 0) {
3905                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906                                       crtc->base.base.id, pll->name);
3907                         goto found;
3908                 }
3909         }
3910
3911         return NULL;
3912
3913 found:
3914         if (pll->new_config->crtc_mask == 0)
3915                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3916
3917         crtc->new_config->shared_dpll = i;
3918         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3919                          pipe_name(crtc->pipe));
3920
3921         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3922
3923         return pll;
3924 }
3925
3926 /**
3927  * intel_shared_dpll_start_config - start a new PLL staged config
3928  * @dev_priv: DRM device
3929  * @clear_pipes: mask of pipes that will have their PLLs freed
3930  *
3931  * Starts a new PLL staged config, copying the current config but
3932  * releasing the references of pipes specified in clear_pipes.
3933  */
3934 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3935                                           unsigned clear_pipes)
3936 {
3937         struct intel_shared_dpll *pll;
3938         enum intel_dpll_id i;
3939
3940         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3941                 pll = &dev_priv->shared_dplls[i];
3942
3943                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3944                                           GFP_KERNEL);
3945                 if (!pll->new_config)
3946                         goto cleanup;
3947
3948                 pll->new_config->crtc_mask &= ~clear_pipes;
3949         }
3950
3951         return 0;
3952
3953 cleanup:
3954         while (--i >= 0) {
3955                 pll = &dev_priv->shared_dplls[i];
3956                 kfree(pll->new_config);
3957                 pll->new_config = NULL;
3958         }
3959
3960         return -ENOMEM;
3961 }
3962
3963 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3964 {
3965         struct intel_shared_dpll *pll;
3966         enum intel_dpll_id i;
3967
3968         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3969                 pll = &dev_priv->shared_dplls[i];
3970
3971                 WARN_ON(pll->new_config == &pll->config);
3972
3973                 pll->config = *pll->new_config;
3974                 kfree(pll->new_config);
3975                 pll->new_config = NULL;
3976         }
3977 }
3978
3979 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3980 {
3981         struct intel_shared_dpll *pll;
3982         enum intel_dpll_id i;
3983
3984         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3985                 pll = &dev_priv->shared_dplls[i];
3986
3987                 WARN_ON(pll->new_config == &pll->config);
3988
3989                 kfree(pll->new_config);
3990                 pll->new_config = NULL;
3991         }
3992 }
3993
3994 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3995 {
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997         int dslreg = PIPEDSL(pipe);
3998         u32 temp;
3999
4000         temp = I915_READ(dslreg);
4001         udelay(500);
4002         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4003                 if (wait_for(I915_READ(dslreg) != temp, 5))
4004                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4005         }
4006 }
4007
4008 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4009 {
4010         struct drm_device *dev = crtc->base.dev;
4011         struct drm_i915_private *dev_priv = dev->dev_private;
4012         int pipe = crtc->pipe;
4013
4014         if (crtc->config.pch_pfit.enabled) {
4015                 /* Force use of hard-coded filter coefficients
4016                  * as some pre-programmed values are broken,
4017                  * e.g. x201.
4018                  */
4019                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4020                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4021                                                  PF_PIPE_SEL_IVB(pipe));
4022                 else
4023                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4024                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4025                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4026         }
4027 }
4028
4029 static void intel_enable_planes(struct drm_crtc *crtc)
4030 {
4031         struct drm_device *dev = crtc->dev;
4032         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4033         struct drm_plane *plane;
4034         struct intel_plane *intel_plane;
4035
4036         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4037                 intel_plane = to_intel_plane(plane);
4038                 if (intel_plane->pipe == pipe)
4039                         intel_plane_restore(&intel_plane->base);
4040         }
4041 }
4042
4043 static void intel_disable_planes(struct drm_crtc *crtc)
4044 {
4045         struct drm_device *dev = crtc->dev;
4046         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4047         struct drm_plane *plane;
4048         struct intel_plane *intel_plane;
4049
4050         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4051                 intel_plane = to_intel_plane(plane);
4052                 if (intel_plane->pipe == pipe)
4053                         intel_plane_disable(&intel_plane->base);
4054         }
4055 }
4056
4057 void hsw_enable_ips(struct intel_crtc *crtc)
4058 {
4059         struct drm_device *dev = crtc->base.dev;
4060         struct drm_i915_private *dev_priv = dev->dev_private;
4061
4062         if (!crtc->config.ips_enabled)
4063                 return;
4064
4065         /* We can only enable IPS after we enable a plane and wait for a vblank */
4066         intel_wait_for_vblank(dev, crtc->pipe);
4067
4068         assert_plane_enabled(dev_priv, crtc->plane);
4069         if (IS_BROADWELL(dev)) {
4070                 mutex_lock(&dev_priv->rps.hw_lock);
4071                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4072                 mutex_unlock(&dev_priv->rps.hw_lock);
4073                 /* Quoting Art Runyan: "its not safe to expect any particular
4074                  * value in IPS_CTL bit 31 after enabling IPS through the
4075                  * mailbox." Moreover, the mailbox may return a bogus state,
4076                  * so we need to just enable it and continue on.
4077                  */
4078         } else {
4079                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4080                 /* The bit only becomes 1 in the next vblank, so this wait here
4081                  * is essentially intel_wait_for_vblank. If we don't have this
4082                  * and don't wait for vblanks until the end of crtc_enable, then
4083                  * the HW state readout code will complain that the expected
4084                  * IPS_CTL value is not the one we read. */
4085                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4086                         DRM_ERROR("Timed out waiting for IPS enable\n");
4087         }
4088 }
4089
4090 void hsw_disable_ips(struct intel_crtc *crtc)
4091 {
4092         struct drm_device *dev = crtc->base.dev;
4093         struct drm_i915_private *dev_priv = dev->dev_private;
4094
4095         if (!crtc->config.ips_enabled)
4096                 return;
4097
4098         assert_plane_enabled(dev_priv, crtc->plane);
4099         if (IS_BROADWELL(dev)) {
4100                 mutex_lock(&dev_priv->rps.hw_lock);
4101                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4102                 mutex_unlock(&dev_priv->rps.hw_lock);
4103                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4104                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4105                         DRM_ERROR("Timed out waiting for IPS disable\n");
4106         } else {
4107                 I915_WRITE(IPS_CTL, 0);
4108                 POSTING_READ(IPS_CTL);
4109         }
4110
4111         /* We need to wait for a vblank before we can disable the plane. */
4112         intel_wait_for_vblank(dev, crtc->pipe);
4113 }
4114
4115 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4116 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4117 {
4118         struct drm_device *dev = crtc->dev;
4119         struct drm_i915_private *dev_priv = dev->dev_private;
4120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4121         enum pipe pipe = intel_crtc->pipe;
4122         int palreg = PALETTE(pipe);
4123         int i;
4124         bool reenable_ips = false;
4125
4126         /* The clocks have to be on to load the palette. */
4127         if (!crtc->enabled || !intel_crtc->active)
4128                 return;
4129
4130         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4131                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4132                         assert_dsi_pll_enabled(dev_priv);
4133                 else
4134                         assert_pll_enabled(dev_priv, pipe);
4135         }
4136
4137         /* use legacy palette for Ironlake */
4138         if (!HAS_GMCH_DISPLAY(dev))
4139                 palreg = LGC_PALETTE(pipe);
4140
4141         /* Workaround : Do not read or write the pipe palette/gamma data while
4142          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4143          */
4144         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4145             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4146              GAMMA_MODE_MODE_SPLIT)) {
4147                 hsw_disable_ips(intel_crtc);
4148                 reenable_ips = true;
4149         }
4150
4151         for (i = 0; i < 256; i++) {
4152                 I915_WRITE(palreg + 4 * i,
4153                            (intel_crtc->lut_r[i] << 16) |
4154                            (intel_crtc->lut_g[i] << 8) |
4155                            intel_crtc->lut_b[i]);
4156         }
4157
4158         if (reenable_ips)
4159                 hsw_enable_ips(intel_crtc);
4160 }
4161
4162 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4163 {
4164         if (!enable && intel_crtc->overlay) {
4165                 struct drm_device *dev = intel_crtc->base.dev;
4166                 struct drm_i915_private *dev_priv = dev->dev_private;
4167
4168                 mutex_lock(&dev->struct_mutex);
4169                 dev_priv->mm.interruptible = false;
4170                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4171                 dev_priv->mm.interruptible = true;
4172                 mutex_unlock(&dev->struct_mutex);
4173         }
4174
4175         /* Let userspace switch the overlay on again. In most cases userspace
4176          * has to recompute where to put it anyway.
4177          */
4178 }
4179
4180 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4181 {
4182         struct drm_device *dev = crtc->dev;
4183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184         int pipe = intel_crtc->pipe;
4185
4186         intel_enable_primary_hw_plane(crtc->primary, crtc);
4187         intel_enable_planes(crtc);
4188         intel_crtc_update_cursor(crtc, true);
4189         intel_crtc_dpms_overlay(intel_crtc, true);
4190
4191         hsw_enable_ips(intel_crtc);
4192
4193         mutex_lock(&dev->struct_mutex);
4194         intel_update_fbc(dev);
4195         mutex_unlock(&dev->struct_mutex);
4196
4197         /*
4198          * FIXME: Once we grow proper nuclear flip support out of this we need
4199          * to compute the mask of flip planes precisely. For the time being
4200          * consider this a flip from a NULL plane.
4201          */
4202         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4203 }
4204
4205 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4206 {
4207         struct drm_device *dev = crtc->dev;
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4210         int pipe = intel_crtc->pipe;
4211         int plane = intel_crtc->plane;
4212
4213         intel_crtc_wait_for_pending_flips(crtc);
4214
4215         if (dev_priv->fbc.plane == plane)
4216                 intel_disable_fbc(dev);
4217
4218         hsw_disable_ips(intel_crtc);
4219
4220         intel_crtc_dpms_overlay(intel_crtc, false);
4221         intel_crtc_update_cursor(crtc, false);
4222         intel_disable_planes(crtc);
4223         intel_disable_primary_hw_plane(crtc->primary, crtc);
4224
4225         /*
4226          * FIXME: Once we grow proper nuclear flip support out of this we need
4227          * to compute the mask of flip planes precisely. For the time being
4228          * consider this a flip to a NULL plane.
4229          */
4230         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4231 }
4232
4233 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4234 {
4235         struct drm_device *dev = crtc->dev;
4236         struct drm_i915_private *dev_priv = dev->dev_private;
4237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4238         struct intel_encoder *encoder;
4239         int pipe = intel_crtc->pipe;
4240
4241         WARN_ON(!crtc->enabled);
4242
4243         if (intel_crtc->active)
4244                 return;
4245
4246         if (intel_crtc->config.has_pch_encoder)
4247                 intel_prepare_shared_dpll(intel_crtc);
4248
4249         if (intel_crtc->config.has_dp_encoder)
4250                 intel_dp_set_m_n(intel_crtc);
4251
4252         intel_set_pipe_timings(intel_crtc);
4253
4254         if (intel_crtc->config.has_pch_encoder) {
4255                 intel_cpu_transcoder_set_m_n(intel_crtc,
4256                                      &intel_crtc->config.fdi_m_n, NULL);
4257         }
4258
4259         ironlake_set_pipeconf(crtc);
4260
4261         intel_crtc->active = true;
4262
4263         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4264         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4265
4266         for_each_encoder_on_crtc(dev, crtc, encoder)
4267                 if (encoder->pre_enable)
4268                         encoder->pre_enable(encoder);
4269
4270         if (intel_crtc->config.has_pch_encoder) {
4271                 /* Note: FDI PLL enabling _must_ be done before we enable the
4272                  * cpu pipes, hence this is separate from all the other fdi/pch
4273                  * enabling. */
4274                 ironlake_fdi_pll_enable(intel_crtc);
4275         } else {
4276                 assert_fdi_tx_disabled(dev_priv, pipe);
4277                 assert_fdi_rx_disabled(dev_priv, pipe);
4278         }
4279
4280         ironlake_pfit_enable(intel_crtc);
4281
4282         /*
4283          * On ILK+ LUT must be loaded before the pipe is running but with
4284          * clocks enabled
4285          */
4286         intel_crtc_load_lut(crtc);
4287
4288         intel_update_watermarks(crtc);
4289         intel_enable_pipe(intel_crtc);
4290
4291         if (intel_crtc->config.has_pch_encoder)
4292                 ironlake_pch_enable(crtc);
4293
4294         for_each_encoder_on_crtc(dev, crtc, encoder)
4295                 encoder->enable(encoder);
4296
4297         if (HAS_PCH_CPT(dev))
4298                 cpt_verify_modeset(dev, intel_crtc->pipe);
4299
4300         assert_vblank_disabled(crtc);
4301         drm_crtc_vblank_on(crtc);
4302
4303         intel_crtc_enable_planes(crtc);
4304 }
4305
4306 /* IPS only exists on ULT machines and is tied to pipe A. */
4307 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4308 {
4309         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4310 }
4311
4312 /*
4313  * This implements the workaround described in the "notes" section of the mode
4314  * set sequence documentation. When going from no pipes or single pipe to
4315  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4316  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4317  */
4318 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4319 {
4320         struct drm_device *dev = crtc->base.dev;
4321         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4322
4323         /* We want to get the other_active_crtc only if there's only 1 other
4324          * active crtc. */
4325         for_each_intel_crtc(dev, crtc_it) {
4326                 if (!crtc_it->active || crtc_it == crtc)
4327                         continue;
4328
4329                 if (other_active_crtc)
4330                         return;
4331
4332                 other_active_crtc = crtc_it;
4333         }
4334         if (!other_active_crtc)
4335                 return;
4336
4337         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4338         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4339 }
4340
4341 static void haswell_crtc_enable(struct drm_crtc *crtc)
4342 {
4343         struct drm_device *dev = crtc->dev;
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346         struct intel_encoder *encoder;
4347         int pipe = intel_crtc->pipe;
4348
4349         WARN_ON(!crtc->enabled);
4350
4351         if (intel_crtc->active)
4352                 return;
4353
4354         if (intel_crtc_to_shared_dpll(intel_crtc))
4355                 intel_enable_shared_dpll(intel_crtc);
4356
4357         if (intel_crtc->config.has_dp_encoder)
4358                 intel_dp_set_m_n(intel_crtc);
4359
4360         intel_set_pipe_timings(intel_crtc);
4361
4362         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4363                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4364                            intel_crtc->config.pixel_multiplier - 1);
4365         }
4366
4367         if (intel_crtc->config.has_pch_encoder) {
4368                 intel_cpu_transcoder_set_m_n(intel_crtc,
4369                                      &intel_crtc->config.fdi_m_n, NULL);
4370         }
4371
4372         haswell_set_pipeconf(crtc);
4373
4374         intel_set_pipe_csc(crtc);
4375
4376         intel_crtc->active = true;
4377
4378         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4379         for_each_encoder_on_crtc(dev, crtc, encoder)
4380                 if (encoder->pre_enable)
4381                         encoder->pre_enable(encoder);
4382
4383         if (intel_crtc->config.has_pch_encoder) {
4384                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4385                                                       true);
4386                 dev_priv->display.fdi_link_train(crtc);
4387         }
4388
4389         intel_ddi_enable_pipe_clock(intel_crtc);
4390
4391         ironlake_pfit_enable(intel_crtc);
4392
4393         /*
4394          * On ILK+ LUT must be loaded before the pipe is running but with
4395          * clocks enabled
4396          */
4397         intel_crtc_load_lut(crtc);
4398
4399         intel_ddi_set_pipe_settings(crtc);
4400         intel_ddi_enable_transcoder_func(crtc);
4401
4402         intel_update_watermarks(crtc);
4403         intel_enable_pipe(intel_crtc);
4404
4405         if (intel_crtc->config.has_pch_encoder)
4406                 lpt_pch_enable(crtc);
4407
4408         if (intel_crtc->config.dp_encoder_is_mst)
4409                 intel_ddi_set_vc_payload_alloc(crtc, true);
4410
4411         for_each_encoder_on_crtc(dev, crtc, encoder) {
4412                 encoder->enable(encoder);
4413                 intel_opregion_notify_encoder(encoder, true);
4414         }
4415
4416         assert_vblank_disabled(crtc);
4417         drm_crtc_vblank_on(crtc);
4418
4419         /* If we change the relative order between pipe/planes enabling, we need
4420          * to change the workaround. */
4421         haswell_mode_set_planes_workaround(intel_crtc);
4422         intel_crtc_enable_planes(crtc);
4423 }
4424
4425 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4426 {
4427         struct drm_device *dev = crtc->base.dev;
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429         int pipe = crtc->pipe;
4430
4431         /* To avoid upsetting the power well on haswell only disable the pfit if
4432          * it's in use. The hw state code will make sure we get this right. */
4433         if (crtc->config.pch_pfit.enabled) {
4434                 I915_WRITE(PF_CTL(pipe), 0);
4435                 I915_WRITE(PF_WIN_POS(pipe), 0);
4436                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4437         }
4438 }
4439
4440 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4441 {
4442         struct drm_device *dev = crtc->dev;
4443         struct drm_i915_private *dev_priv = dev->dev_private;
4444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4445         struct intel_encoder *encoder;
4446         int pipe = intel_crtc->pipe;
4447         u32 reg, temp;
4448
4449         if (!intel_crtc->active)
4450                 return;
4451
4452         intel_crtc_disable_planes(crtc);
4453
4454         drm_crtc_vblank_off(crtc);
4455         assert_vblank_disabled(crtc);
4456
4457         for_each_encoder_on_crtc(dev, crtc, encoder)
4458                 encoder->disable(encoder);
4459
4460         if (intel_crtc->config.has_pch_encoder)
4461                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4462
4463         intel_disable_pipe(intel_crtc);
4464
4465         ironlake_pfit_disable(intel_crtc);
4466
4467         for_each_encoder_on_crtc(dev, crtc, encoder)
4468                 if (encoder->post_disable)
4469                         encoder->post_disable(encoder);
4470
4471         if (intel_crtc->config.has_pch_encoder) {
4472                 ironlake_fdi_disable(crtc);
4473
4474                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4475                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4476
4477                 if (HAS_PCH_CPT(dev)) {
4478                         /* disable TRANS_DP_CTL */
4479                         reg = TRANS_DP_CTL(pipe);
4480                         temp = I915_READ(reg);
4481                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4482                                   TRANS_DP_PORT_SEL_MASK);
4483                         temp |= TRANS_DP_PORT_SEL_NONE;
4484                         I915_WRITE(reg, temp);
4485
4486                         /* disable DPLL_SEL */
4487                         temp = I915_READ(PCH_DPLL_SEL);
4488                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4489                         I915_WRITE(PCH_DPLL_SEL, temp);
4490                 }
4491
4492                 /* disable PCH DPLL */
4493                 intel_disable_shared_dpll(intel_crtc);
4494
4495                 ironlake_fdi_pll_disable(intel_crtc);
4496         }
4497
4498         intel_crtc->active = false;
4499         intel_update_watermarks(crtc);
4500
4501         mutex_lock(&dev->struct_mutex);
4502         intel_update_fbc(dev);
4503         mutex_unlock(&dev->struct_mutex);
4504 }
4505
4506 static void haswell_crtc_disable(struct drm_crtc *crtc)
4507 {
4508         struct drm_device *dev = crtc->dev;
4509         struct drm_i915_private *dev_priv = dev->dev_private;
4510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4511         struct intel_encoder *encoder;
4512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4513
4514         if (!intel_crtc->active)
4515                 return;
4516
4517         intel_crtc_disable_planes(crtc);
4518
4519         drm_crtc_vblank_off(crtc);
4520         assert_vblank_disabled(crtc);
4521
4522         for_each_encoder_on_crtc(dev, crtc, encoder) {
4523                 intel_opregion_notify_encoder(encoder, false);
4524                 encoder->disable(encoder);
4525         }
4526
4527         if (intel_crtc->config.has_pch_encoder)
4528                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4529                                                       false);
4530         intel_disable_pipe(intel_crtc);
4531
4532         if (intel_crtc->config.dp_encoder_is_mst)
4533                 intel_ddi_set_vc_payload_alloc(crtc, false);
4534
4535         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4536
4537         ironlake_pfit_disable(intel_crtc);
4538
4539         intel_ddi_disable_pipe_clock(intel_crtc);
4540
4541         if (intel_crtc->config.has_pch_encoder) {
4542                 lpt_disable_pch_transcoder(dev_priv);
4543                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4544                                                       true);
4545                 intel_ddi_fdi_disable(crtc);
4546         }
4547
4548         for_each_encoder_on_crtc(dev, crtc, encoder)
4549                 if (encoder->post_disable)
4550                         encoder->post_disable(encoder);
4551
4552         intel_crtc->active = false;
4553         intel_update_watermarks(crtc);
4554
4555         mutex_lock(&dev->struct_mutex);
4556         intel_update_fbc(dev);
4557         mutex_unlock(&dev->struct_mutex);
4558
4559         if (intel_crtc_to_shared_dpll(intel_crtc))
4560                 intel_disable_shared_dpll(intel_crtc);
4561 }
4562
4563 static void ironlake_crtc_off(struct drm_crtc *crtc)
4564 {
4565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566         intel_put_shared_dpll(intel_crtc);
4567 }
4568
4569
4570 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4571 {
4572         struct drm_device *dev = crtc->base.dev;
4573         struct drm_i915_private *dev_priv = dev->dev_private;
4574         struct intel_crtc_config *pipe_config = &crtc->config;
4575
4576         if (!crtc->config.gmch_pfit.control)
4577                 return;
4578
4579         /*
4580          * The panel fitter should only be adjusted whilst the pipe is disabled,
4581          * according to register description and PRM.
4582          */
4583         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4584         assert_pipe_disabled(dev_priv, crtc->pipe);
4585
4586         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4587         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4588
4589         /* Border color in case we don't scale up to the full screen. Black by
4590          * default, change to something else for debugging. */
4591         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4592 }
4593
4594 static enum intel_display_power_domain port_to_power_domain(enum port port)
4595 {
4596         switch (port) {
4597         case PORT_A:
4598                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4599         case PORT_B:
4600                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4601         case PORT_C:
4602                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4603         case PORT_D:
4604                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4605         default:
4606                 WARN_ON_ONCE(1);
4607                 return POWER_DOMAIN_PORT_OTHER;
4608         }
4609 }
4610
4611 #define for_each_power_domain(domain, mask)                             \
4612         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4613                 if ((1 << (domain)) & (mask))
4614
4615 enum intel_display_power_domain
4616 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4617 {
4618         struct drm_device *dev = intel_encoder->base.dev;
4619         struct intel_digital_port *intel_dig_port;
4620
4621         switch (intel_encoder->type) {
4622         case INTEL_OUTPUT_UNKNOWN:
4623                 /* Only DDI platforms should ever use this output type */
4624                 WARN_ON_ONCE(!HAS_DDI(dev));
4625         case INTEL_OUTPUT_DISPLAYPORT:
4626         case INTEL_OUTPUT_HDMI:
4627         case INTEL_OUTPUT_EDP:
4628                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4629                 return port_to_power_domain(intel_dig_port->port);
4630         case INTEL_OUTPUT_DP_MST:
4631                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4632                 return port_to_power_domain(intel_dig_port->port);
4633         case INTEL_OUTPUT_ANALOG:
4634                 return POWER_DOMAIN_PORT_CRT;
4635         case INTEL_OUTPUT_DSI:
4636                 return POWER_DOMAIN_PORT_DSI;
4637         default:
4638                 return POWER_DOMAIN_PORT_OTHER;
4639         }
4640 }
4641
4642 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4643 {
4644         struct drm_device *dev = crtc->dev;
4645         struct intel_encoder *intel_encoder;
4646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647         enum pipe pipe = intel_crtc->pipe;
4648         unsigned long mask;
4649         enum transcoder transcoder;
4650
4651         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4652
4653         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4654         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4655         if (intel_crtc->config.pch_pfit.enabled ||
4656             intel_crtc->config.pch_pfit.force_thru)
4657                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4658
4659         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4660                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4661
4662         return mask;
4663 }
4664
4665 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4666 {
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4669         struct intel_crtc *crtc;
4670
4671         /*
4672          * First get all needed power domains, then put all unneeded, to avoid
4673          * any unnecessary toggling of the power wells.
4674          */
4675         for_each_intel_crtc(dev, crtc) {
4676                 enum intel_display_power_domain domain;
4677
4678                 if (!crtc->base.enabled)
4679                         continue;
4680
4681                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4682
4683                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4684                         intel_display_power_get(dev_priv, domain);
4685         }
4686
4687         if (dev_priv->display.modeset_global_resources)
4688                 dev_priv->display.modeset_global_resources(dev);
4689
4690         for_each_intel_crtc(dev, crtc) {
4691                 enum intel_display_power_domain domain;
4692
4693                 for_each_power_domain(domain, crtc->enabled_power_domains)
4694                         intel_display_power_put(dev_priv, domain);
4695
4696                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4697         }
4698
4699         intel_display_set_init_power(dev_priv, false);
4700 }
4701
4702 /* returns HPLL frequency in kHz */
4703 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4704 {
4705         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4706
4707         /* Obtain SKU information */
4708         mutex_lock(&dev_priv->dpio_lock);
4709         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4710                 CCK_FUSE_HPLL_FREQ_MASK;
4711         mutex_unlock(&dev_priv->dpio_lock);
4712
4713         return vco_freq[hpll_freq] * 1000;
4714 }
4715
4716 static void vlv_update_cdclk(struct drm_device *dev)
4717 {
4718         struct drm_i915_private *dev_priv = dev->dev_private;
4719
4720         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4721         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4722                          dev_priv->vlv_cdclk_freq);
4723
4724         /*
4725          * Program the gmbus_freq based on the cdclk frequency.
4726          * BSpec erroneously claims we should aim for 4MHz, but
4727          * in fact 1MHz is the correct frequency.
4728          */
4729         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4730 }
4731
4732 /* Adjust CDclk dividers to allow high res or save power if possible */
4733 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4734 {
4735         struct drm_i915_private *dev_priv = dev->dev_private;
4736         u32 val, cmd;
4737
4738         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4739
4740         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4741                 cmd = 2;
4742         else if (cdclk == 266667)
4743                 cmd = 1;
4744         else
4745                 cmd = 0;
4746
4747         mutex_lock(&dev_priv->rps.hw_lock);
4748         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4749         val &= ~DSPFREQGUAR_MASK;
4750         val |= (cmd << DSPFREQGUAR_SHIFT);
4751         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4752         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4753                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4754                      50)) {
4755                 DRM_ERROR("timed out waiting for CDclk change\n");
4756         }
4757         mutex_unlock(&dev_priv->rps.hw_lock);
4758
4759         if (cdclk == 400000) {
4760                 u32 divider;
4761
4762                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4763
4764                 mutex_lock(&dev_priv->dpio_lock);
4765                 /* adjust cdclk divider */
4766                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4767                 val &= ~DISPLAY_FREQUENCY_VALUES;
4768                 val |= divider;
4769                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4770
4771                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4772                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4773                              50))
4774                         DRM_ERROR("timed out waiting for CDclk change\n");
4775                 mutex_unlock(&dev_priv->dpio_lock);
4776         }
4777
4778         mutex_lock(&dev_priv->dpio_lock);
4779         /* adjust self-refresh exit latency value */
4780         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4781         val &= ~0x7f;
4782
4783         /*
4784          * For high bandwidth configs, we set a higher latency in the bunit
4785          * so that the core display fetch happens in time to avoid underruns.
4786          */
4787         if (cdclk == 400000)
4788                 val |= 4500 / 250; /* 4.5 usec */
4789         else
4790                 val |= 3000 / 250; /* 3.0 usec */
4791         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4792         mutex_unlock(&dev_priv->dpio_lock);
4793
4794         vlv_update_cdclk(dev);
4795 }
4796
4797 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4798 {
4799         struct drm_i915_private *dev_priv = dev->dev_private;
4800         u32 val, cmd;
4801
4802         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4803
4804         switch (cdclk) {
4805         case 400000:
4806                 cmd = 3;
4807                 break;
4808         case 333333:
4809         case 320000:
4810                 cmd = 2;
4811                 break;
4812         case 266667:
4813                 cmd = 1;
4814                 break;
4815         case 200000:
4816                 cmd = 0;
4817                 break;
4818         default:
4819                 WARN_ON(1);
4820                 return;
4821         }
4822
4823         mutex_lock(&dev_priv->rps.hw_lock);
4824         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4825         val &= ~DSPFREQGUAR_MASK_CHV;
4826         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4827         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4828         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4829                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4830                      50)) {
4831                 DRM_ERROR("timed out waiting for CDclk change\n");
4832         }
4833         mutex_unlock(&dev_priv->rps.hw_lock);
4834
4835         vlv_update_cdclk(dev);
4836 }
4837
4838 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4839                                  int max_pixclk)
4840 {
4841         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4842
4843         /* FIXME: Punit isn't quite ready yet */
4844         if (IS_CHERRYVIEW(dev_priv->dev))
4845                 return 400000;
4846
4847         /*
4848          * Really only a few cases to deal with, as only 4 CDclks are supported:
4849          *   200MHz
4850          *   267MHz
4851          *   320/333MHz (depends on HPLL freq)
4852          *   400MHz
4853          * So we check to see whether we're above 90% of the lower bin and
4854          * adjust if needed.
4855          *
4856          * We seem to get an unstable or solid color picture at 200MHz.
4857          * Not sure what's wrong. For now use 200MHz only when all pipes
4858          * are off.
4859          */
4860         if (max_pixclk > freq_320*9/10)
4861                 return 400000;
4862         else if (max_pixclk > 266667*9/10)
4863                 return freq_320;
4864         else if (max_pixclk > 0)
4865                 return 266667;
4866         else
4867                 return 200000;
4868 }
4869
4870 /* compute the max pixel clock for new configuration */
4871 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4872 {
4873         struct drm_device *dev = dev_priv->dev;
4874         struct intel_crtc *intel_crtc;
4875         int max_pixclk = 0;
4876
4877         for_each_intel_crtc(dev, intel_crtc) {
4878                 if (intel_crtc->new_enabled)
4879                         max_pixclk = max(max_pixclk,
4880                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4881         }
4882
4883         return max_pixclk;
4884 }
4885
4886 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4887                                             unsigned *prepare_pipes)
4888 {
4889         struct drm_i915_private *dev_priv = dev->dev_private;
4890         struct intel_crtc *intel_crtc;
4891         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4892
4893         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4894             dev_priv->vlv_cdclk_freq)
4895                 return;
4896
4897         /* disable/enable all currently active pipes while we change cdclk */
4898         for_each_intel_crtc(dev, intel_crtc)
4899                 if (intel_crtc->base.enabled)
4900                         *prepare_pipes |= (1 << intel_crtc->pipe);
4901 }
4902
4903 static void valleyview_modeset_global_resources(struct drm_device *dev)
4904 {
4905         struct drm_i915_private *dev_priv = dev->dev_private;
4906         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4907         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4908
4909         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4910                 if (IS_CHERRYVIEW(dev))
4911                         cherryview_set_cdclk(dev, req_cdclk);
4912                 else
4913                         valleyview_set_cdclk(dev, req_cdclk);
4914         }
4915 }
4916
4917 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4918 {
4919         struct drm_device *dev = crtc->dev;
4920         struct drm_i915_private *dev_priv = to_i915(dev);
4921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922         struct intel_encoder *encoder;
4923         int pipe = intel_crtc->pipe;
4924         bool is_dsi;
4925
4926         WARN_ON(!crtc->enabled);
4927
4928         if (intel_crtc->active)
4929                 return;
4930
4931         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4932
4933         if (!is_dsi) {
4934                 if (IS_CHERRYVIEW(dev))
4935                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4936                 else
4937                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4938         }
4939
4940         if (intel_crtc->config.has_dp_encoder)
4941                 intel_dp_set_m_n(intel_crtc);
4942
4943         intel_set_pipe_timings(intel_crtc);
4944
4945         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4946                 struct drm_i915_private *dev_priv = dev->dev_private;
4947
4948                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4949                 I915_WRITE(CHV_CANVAS(pipe), 0);
4950         }
4951
4952         i9xx_set_pipeconf(intel_crtc);
4953
4954         intel_crtc->active = true;
4955
4956         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957
4958         for_each_encoder_on_crtc(dev, crtc, encoder)
4959                 if (encoder->pre_pll_enable)
4960                         encoder->pre_pll_enable(encoder);
4961
4962         if (!is_dsi) {
4963                 if (IS_CHERRYVIEW(dev))
4964                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4965                 else
4966                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4967         }
4968
4969         for_each_encoder_on_crtc(dev, crtc, encoder)
4970                 if (encoder->pre_enable)
4971                         encoder->pre_enable(encoder);
4972
4973         i9xx_pfit_enable(intel_crtc);
4974
4975         intel_crtc_load_lut(crtc);
4976
4977         intel_update_watermarks(crtc);
4978         intel_enable_pipe(intel_crtc);
4979
4980         for_each_encoder_on_crtc(dev, crtc, encoder)
4981                 encoder->enable(encoder);
4982
4983         assert_vblank_disabled(crtc);
4984         drm_crtc_vblank_on(crtc);
4985
4986         intel_crtc_enable_planes(crtc);
4987
4988         /* Underruns don't raise interrupts, so check manually. */
4989         i9xx_check_fifo_underruns(dev_priv);
4990 }
4991
4992 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4993 {
4994         struct drm_device *dev = crtc->base.dev;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996
4997         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4998         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4999 }
5000
5001 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5002 {
5003         struct drm_device *dev = crtc->dev;
5004         struct drm_i915_private *dev_priv = to_i915(dev);
5005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5006         struct intel_encoder *encoder;
5007         int pipe = intel_crtc->pipe;
5008
5009         WARN_ON(!crtc->enabled);
5010
5011         if (intel_crtc->active)
5012                 return;
5013
5014         i9xx_set_pll_dividers(intel_crtc);
5015
5016         if (intel_crtc->config.has_dp_encoder)
5017                 intel_dp_set_m_n(intel_crtc);
5018
5019         intel_set_pipe_timings(intel_crtc);
5020
5021         i9xx_set_pipeconf(intel_crtc);
5022
5023         intel_crtc->active = true;
5024
5025         if (!IS_GEN2(dev))
5026                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5027
5028         for_each_encoder_on_crtc(dev, crtc, encoder)
5029                 if (encoder->pre_enable)
5030                         encoder->pre_enable(encoder);
5031
5032         i9xx_enable_pll(intel_crtc);
5033
5034         i9xx_pfit_enable(intel_crtc);
5035
5036         intel_crtc_load_lut(crtc);
5037
5038         intel_update_watermarks(crtc);
5039         intel_enable_pipe(intel_crtc);
5040
5041         for_each_encoder_on_crtc(dev, crtc, encoder)
5042                 encoder->enable(encoder);
5043
5044         assert_vblank_disabled(crtc);
5045         drm_crtc_vblank_on(crtc);
5046
5047         intel_crtc_enable_planes(crtc);
5048
5049         /*
5050          * Gen2 reports pipe underruns whenever all planes are disabled.
5051          * So don't enable underrun reporting before at least some planes
5052          * are enabled.
5053          * FIXME: Need to fix the logic to work when we turn off all planes
5054          * but leave the pipe running.
5055          */
5056         if (IS_GEN2(dev))
5057                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058
5059         /* Underruns don't raise interrupts, so check manually. */
5060         i9xx_check_fifo_underruns(dev_priv);
5061 }
5062
5063 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5064 {
5065         struct drm_device *dev = crtc->base.dev;
5066         struct drm_i915_private *dev_priv = dev->dev_private;
5067
5068         if (!crtc->config.gmch_pfit.control)
5069                 return;
5070
5071         assert_pipe_disabled(dev_priv, crtc->pipe);
5072
5073         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5074                          I915_READ(PFIT_CONTROL));
5075         I915_WRITE(PFIT_CONTROL, 0);
5076 }
5077
5078 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5079 {
5080         struct drm_device *dev = crtc->dev;
5081         struct drm_i915_private *dev_priv = dev->dev_private;
5082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083         struct intel_encoder *encoder;
5084         int pipe = intel_crtc->pipe;
5085
5086         if (!intel_crtc->active)
5087                 return;
5088
5089         /*
5090          * Gen2 reports pipe underruns whenever all planes are disabled.
5091          * So diasble underrun reporting before all the planes get disabled.
5092          * FIXME: Need to fix the logic to work when we turn off all planes
5093          * but leave the pipe running.
5094          */
5095         if (IS_GEN2(dev))
5096                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5097
5098         /*
5099          * Vblank time updates from the shadow to live plane control register
5100          * are blocked if the memory self-refresh mode is active at that
5101          * moment. So to make sure the plane gets truly disabled, disable
5102          * first the self-refresh mode. The self-refresh enable bit in turn
5103          * will be checked/applied by the HW only at the next frame start
5104          * event which is after the vblank start event, so we need to have a
5105          * wait-for-vblank between disabling the plane and the pipe.
5106          */
5107         intel_set_memory_cxsr(dev_priv, false);
5108         intel_crtc_disable_planes(crtc);
5109
5110         /*
5111          * On gen2 planes are double buffered but the pipe isn't, so we must
5112          * wait for planes to fully turn off before disabling the pipe.
5113          * We also need to wait on all gmch platforms because of the
5114          * self-refresh mode constraint explained above.
5115          */
5116         intel_wait_for_vblank(dev, pipe);
5117
5118         drm_crtc_vblank_off(crtc);
5119         assert_vblank_disabled(crtc);
5120
5121         for_each_encoder_on_crtc(dev, crtc, encoder)
5122                 encoder->disable(encoder);
5123
5124         intel_disable_pipe(intel_crtc);
5125
5126         i9xx_pfit_disable(intel_crtc);
5127
5128         for_each_encoder_on_crtc(dev, crtc, encoder)
5129                 if (encoder->post_disable)
5130                         encoder->post_disable(encoder);
5131
5132         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5133                 if (IS_CHERRYVIEW(dev))
5134                         chv_disable_pll(dev_priv, pipe);
5135                 else if (IS_VALLEYVIEW(dev))
5136                         vlv_disable_pll(dev_priv, pipe);
5137                 else
5138                         i9xx_disable_pll(intel_crtc);
5139         }
5140
5141         if (!IS_GEN2(dev))
5142                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5143
5144         intel_crtc->active = false;
5145         intel_update_watermarks(crtc);
5146
5147         mutex_lock(&dev->struct_mutex);
5148         intel_update_fbc(dev);
5149         mutex_unlock(&dev->struct_mutex);
5150 }
5151
5152 static void i9xx_crtc_off(struct drm_crtc *crtc)
5153 {
5154 }
5155
5156 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5157                                     bool enabled)
5158 {
5159         struct drm_device *dev = crtc->dev;
5160         struct drm_i915_master_private *master_priv;
5161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162         int pipe = intel_crtc->pipe;
5163
5164         if (!dev->primary->master)
5165                 return;
5166
5167         master_priv = dev->primary->master->driver_priv;
5168         if (!master_priv->sarea_priv)
5169                 return;
5170
5171         switch (pipe) {
5172         case 0:
5173                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5174                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5175                 break;
5176         case 1:
5177                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5178                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5179                 break;
5180         default:
5181                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5182                 break;
5183         }
5184 }
5185
5186 /* Master function to enable/disable CRTC and corresponding power wells */
5187 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5188 {
5189         struct drm_device *dev = crtc->dev;
5190         struct drm_i915_private *dev_priv = dev->dev_private;
5191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192         enum intel_display_power_domain domain;
5193         unsigned long domains;
5194
5195         if (enable) {
5196                 if (!intel_crtc->active) {
5197                         domains = get_crtc_power_domains(crtc);
5198                         for_each_power_domain(domain, domains)
5199                                 intel_display_power_get(dev_priv, domain);
5200                         intel_crtc->enabled_power_domains = domains;
5201
5202                         dev_priv->display.crtc_enable(crtc);
5203                 }
5204         } else {
5205                 if (intel_crtc->active) {
5206                         dev_priv->display.crtc_disable(crtc);
5207
5208                         domains = intel_crtc->enabled_power_domains;
5209                         for_each_power_domain(domain, domains)
5210                                 intel_display_power_put(dev_priv, domain);
5211                         intel_crtc->enabled_power_domains = 0;
5212                 }
5213         }
5214 }
5215
5216 /**
5217  * Sets the power management mode of the pipe and plane.
5218  */
5219 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5220 {
5221         struct drm_device *dev = crtc->dev;
5222         struct intel_encoder *intel_encoder;
5223         bool enable = false;
5224
5225         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5226                 enable |= intel_encoder->connectors_active;
5227
5228         intel_crtc_control(crtc, enable);
5229
5230         intel_crtc_update_sarea(crtc, enable);
5231 }
5232
5233 static void intel_crtc_disable(struct drm_crtc *crtc)
5234 {
5235         struct drm_device *dev = crtc->dev;
5236         struct drm_connector *connector;
5237         struct drm_i915_private *dev_priv = dev->dev_private;
5238         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5239         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5240
5241         /* crtc should still be enabled when we disable it. */
5242         WARN_ON(!crtc->enabled);
5243
5244         dev_priv->display.crtc_disable(crtc);
5245         intel_crtc_update_sarea(crtc, false);
5246         dev_priv->display.off(crtc);
5247
5248         if (crtc->primary->fb) {
5249                 mutex_lock(&dev->struct_mutex);
5250                 intel_unpin_fb_obj(old_obj);
5251                 i915_gem_track_fb(old_obj, NULL,
5252                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5253                 mutex_unlock(&dev->struct_mutex);
5254                 crtc->primary->fb = NULL;
5255         }
5256
5257         /* Update computed state. */
5258         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5259                 if (!connector->encoder || !connector->encoder->crtc)
5260                         continue;
5261
5262                 if (connector->encoder->crtc != crtc)
5263                         continue;
5264
5265                 connector->dpms = DRM_MODE_DPMS_OFF;
5266                 to_intel_encoder(connector->encoder)->connectors_active = false;
5267         }
5268 }
5269
5270 void intel_encoder_destroy(struct drm_encoder *encoder)
5271 {
5272         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5273
5274         drm_encoder_cleanup(encoder);
5275         kfree(intel_encoder);
5276 }
5277
5278 /* Simple dpms helper for encoders with just one connector, no cloning and only
5279  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5280  * state of the entire output pipe. */
5281 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5282 {
5283         if (mode == DRM_MODE_DPMS_ON) {
5284                 encoder->connectors_active = true;
5285
5286                 intel_crtc_update_dpms(encoder->base.crtc);
5287         } else {
5288                 encoder->connectors_active = false;
5289
5290                 intel_crtc_update_dpms(encoder->base.crtc);
5291         }
5292 }
5293
5294 /* Cross check the actual hw state with our own modeset state tracking (and it's
5295  * internal consistency). */
5296 static void intel_connector_check_state(struct intel_connector *connector)
5297 {
5298         if (connector->get_hw_state(connector)) {
5299                 struct intel_encoder *encoder = connector->encoder;
5300                 struct drm_crtc *crtc;
5301                 bool encoder_enabled;
5302                 enum pipe pipe;
5303
5304                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5305                               connector->base.base.id,
5306                               connector->base.name);
5307
5308                 /* there is no real hw state for MST connectors */
5309                 if (connector->mst_port)
5310                         return;
5311
5312                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5313                      "wrong connector dpms state\n");
5314                 WARN(connector->base.encoder != &encoder->base,
5315                      "active connector not linked to encoder\n");
5316
5317                 if (encoder) {
5318                         WARN(!encoder->connectors_active,
5319                              "encoder->connectors_active not set\n");
5320
5321                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5322                         WARN(!encoder_enabled, "encoder not enabled\n");
5323                         if (WARN_ON(!encoder->base.crtc))
5324                                 return;
5325
5326                         crtc = encoder->base.crtc;
5327
5328                         WARN(!crtc->enabled, "crtc not enabled\n");
5329                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5330                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5331                              "encoder active on the wrong pipe\n");
5332                 }
5333         }
5334 }
5335
5336 /* Even simpler default implementation, if there's really no special case to
5337  * consider. */
5338 void intel_connector_dpms(struct drm_connector *connector, int mode)
5339 {
5340         /* All the simple cases only support two dpms states. */
5341         if (mode != DRM_MODE_DPMS_ON)
5342                 mode = DRM_MODE_DPMS_OFF;
5343
5344         if (mode == connector->dpms)
5345                 return;
5346
5347         connector->dpms = mode;
5348
5349         /* Only need to change hw state when actually enabled */
5350         if (connector->encoder)
5351                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5352
5353         intel_modeset_check_state(connector->dev);
5354 }
5355
5356 /* Simple connector->get_hw_state implementation for encoders that support only
5357  * one connector and no cloning and hence the encoder state determines the state
5358  * of the connector. */
5359 bool intel_connector_get_hw_state(struct intel_connector *connector)
5360 {
5361         enum pipe pipe = 0;
5362         struct intel_encoder *encoder = connector->encoder;
5363
5364         return encoder->get_hw_state(encoder, &pipe);
5365 }
5366
5367 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5368                                      struct intel_crtc_config *pipe_config)
5369 {
5370         struct drm_i915_private *dev_priv = dev->dev_private;
5371         struct intel_crtc *pipe_B_crtc =
5372                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5373
5374         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375                       pipe_name(pipe), pipe_config->fdi_lanes);
5376         if (pipe_config->fdi_lanes > 4) {
5377                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378                               pipe_name(pipe), pipe_config->fdi_lanes);
5379                 return false;
5380         }
5381
5382         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5383                 if (pipe_config->fdi_lanes > 2) {
5384                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5385                                       pipe_config->fdi_lanes);
5386                         return false;
5387                 } else {
5388                         return true;
5389                 }
5390         }
5391
5392         if (INTEL_INFO(dev)->num_pipes == 2)
5393                 return true;
5394
5395         /* Ivybridge 3 pipe is really complicated */
5396         switch (pipe) {
5397         case PIPE_A:
5398                 return true;
5399         case PIPE_B:
5400                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5401                     pipe_config->fdi_lanes > 2) {
5402                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5403                                       pipe_name(pipe), pipe_config->fdi_lanes);
5404                         return false;
5405                 }
5406                 return true;
5407         case PIPE_C:
5408                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5409                     pipe_B_crtc->config.fdi_lanes <= 2) {
5410                         if (pipe_config->fdi_lanes > 2) {
5411                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412                                               pipe_name(pipe), pipe_config->fdi_lanes);
5413                                 return false;
5414                         }
5415                 } else {
5416                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5417                         return false;
5418                 }
5419                 return true;
5420         default:
5421                 BUG();
5422         }
5423 }
5424
5425 #define RETRY 1
5426 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5427                                        struct intel_crtc_config *pipe_config)
5428 {
5429         struct drm_device *dev = intel_crtc->base.dev;
5430         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5431         int lane, link_bw, fdi_dotclock;
5432         bool setup_ok, needs_recompute = false;
5433
5434 retry:
5435         /* FDI is a binary signal running at ~2.7GHz, encoding
5436          * each output octet as 10 bits. The actual frequency
5437          * is stored as a divider into a 100MHz clock, and the
5438          * mode pixel clock is stored in units of 1KHz.
5439          * Hence the bw of each lane in terms of the mode signal
5440          * is:
5441          */
5442         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5443
5444         fdi_dotclock = adjusted_mode->crtc_clock;
5445
5446         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5447                                            pipe_config->pipe_bpp);
5448
5449         pipe_config->fdi_lanes = lane;
5450
5451         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5452                                link_bw, &pipe_config->fdi_m_n);
5453
5454         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5455                                             intel_crtc->pipe, pipe_config);
5456         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5457                 pipe_config->pipe_bpp -= 2*3;
5458                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5459                               pipe_config->pipe_bpp);
5460                 needs_recompute = true;
5461                 pipe_config->bw_constrained = true;
5462
5463                 goto retry;
5464         }
5465
5466         if (needs_recompute)
5467                 return RETRY;
5468
5469         return setup_ok ? 0 : -EINVAL;
5470 }
5471
5472 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5473                                    struct intel_crtc_config *pipe_config)
5474 {
5475         pipe_config->ips_enabled = i915.enable_ips &&
5476                                    hsw_crtc_supports_ips(crtc) &&
5477                                    pipe_config->pipe_bpp <= 24;
5478 }
5479
5480 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5481                                      struct intel_crtc_config *pipe_config)
5482 {
5483         struct drm_device *dev = crtc->base.dev;
5484         struct drm_i915_private *dev_priv = dev->dev_private;
5485         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5486
5487         /* FIXME should check pixel clock limits on all platforms */
5488         if (INTEL_INFO(dev)->gen < 4) {
5489                 int clock_limit =
5490                         dev_priv->display.get_display_clock_speed(dev);
5491
5492                 /*
5493                  * Enable pixel doubling when the dot clock
5494                  * is > 90% of the (display) core speed.
5495                  *
5496                  * GDG double wide on either pipe,
5497                  * otherwise pipe A only.
5498                  */
5499                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5500                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5501                         clock_limit *= 2;
5502                         pipe_config->double_wide = true;
5503                 }
5504
5505                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5506                         return -EINVAL;
5507         }
5508
5509         /*
5510          * Pipe horizontal size must be even in:
5511          * - DVO ganged mode
5512          * - LVDS dual channel mode
5513          * - Double wide pipe
5514          */
5515         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5516              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5517                 pipe_config->pipe_src_w &= ~1;
5518
5519         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5520          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5521          */
5522         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5523                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5524                 return -EINVAL;
5525
5526         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5527                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5528         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5529                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5530                  * for lvds. */
5531                 pipe_config->pipe_bpp = 8*3;
5532         }
5533
5534         if (HAS_IPS(dev))
5535                 hsw_compute_ips_config(crtc, pipe_config);
5536
5537         if (pipe_config->has_pch_encoder)
5538                 return ironlake_fdi_compute_config(crtc, pipe_config);
5539
5540         return 0;
5541 }
5542
5543 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5544 {
5545         struct drm_i915_private *dev_priv = dev->dev_private;
5546         u32 val;
5547         int divider;
5548
5549         /* FIXME: Punit isn't quite ready yet */
5550         if (IS_CHERRYVIEW(dev))
5551                 return 400000;
5552
5553         if (dev_priv->hpll_freq == 0)
5554                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5555
5556         mutex_lock(&dev_priv->dpio_lock);
5557         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5558         mutex_unlock(&dev_priv->dpio_lock);
5559
5560         divider = val & DISPLAY_FREQUENCY_VALUES;
5561
5562         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5563              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5564              "cdclk change in progress\n");
5565
5566         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5567 }
5568
5569 static int i945_get_display_clock_speed(struct drm_device *dev)
5570 {
5571         return 400000;
5572 }
5573
5574 static int i915_get_display_clock_speed(struct drm_device *dev)
5575 {
5576         return 333000;
5577 }
5578
5579 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5580 {
5581         return 200000;
5582 }
5583
5584 static int pnv_get_display_clock_speed(struct drm_device *dev)
5585 {
5586         u16 gcfgc = 0;
5587
5588         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5589
5590         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5591         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5592                 return 267000;
5593         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5594                 return 333000;
5595         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5596                 return 444000;
5597         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5598                 return 200000;
5599         default:
5600                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5601         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5602                 return 133000;
5603         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5604                 return 167000;
5605         }
5606 }
5607
5608 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5609 {
5610         u16 gcfgc = 0;
5611
5612         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5613
5614         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5615                 return 133000;
5616         else {
5617                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5618                 case GC_DISPLAY_CLOCK_333_MHZ:
5619                         return 333000;
5620                 default:
5621                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5622                         return 190000;
5623                 }
5624         }
5625 }
5626
5627 static int i865_get_display_clock_speed(struct drm_device *dev)
5628 {
5629         return 266000;
5630 }
5631
5632 static int i855_get_display_clock_speed(struct drm_device *dev)
5633 {
5634         u16 hpllcc = 0;
5635         /* Assume that the hardware is in the high speed state.  This
5636          * should be the default.
5637          */
5638         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5639         case GC_CLOCK_133_200:
5640         case GC_CLOCK_100_200:
5641                 return 200000;
5642         case GC_CLOCK_166_250:
5643                 return 250000;
5644         case GC_CLOCK_100_133:
5645                 return 133000;
5646         }
5647
5648         /* Shouldn't happen */
5649         return 0;
5650 }
5651
5652 static int i830_get_display_clock_speed(struct drm_device *dev)
5653 {
5654         return 133000;
5655 }
5656
5657 static void
5658 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5659 {
5660         while (*num > DATA_LINK_M_N_MASK ||
5661                *den > DATA_LINK_M_N_MASK) {
5662                 *num >>= 1;
5663                 *den >>= 1;
5664         }
5665 }
5666
5667 static void compute_m_n(unsigned int m, unsigned int n,
5668                         uint32_t *ret_m, uint32_t *ret_n)
5669 {
5670         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5671         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5672         intel_reduce_m_n_ratio(ret_m, ret_n);
5673 }
5674
5675 void
5676 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5677                        int pixel_clock, int link_clock,
5678                        struct intel_link_m_n *m_n)
5679 {
5680         m_n->tu = 64;
5681
5682         compute_m_n(bits_per_pixel * pixel_clock,
5683                     link_clock * nlanes * 8,
5684                     &m_n->gmch_m, &m_n->gmch_n);
5685
5686         compute_m_n(pixel_clock, link_clock,
5687                     &m_n->link_m, &m_n->link_n);
5688 }
5689
5690 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5691 {
5692         if (i915.panel_use_ssc >= 0)
5693                 return i915.panel_use_ssc != 0;
5694         return dev_priv->vbt.lvds_use_ssc
5695                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5696 }
5697
5698 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5699 {
5700         struct drm_device *dev = crtc->base.dev;
5701         struct drm_i915_private *dev_priv = dev->dev_private;
5702         int refclk;
5703
5704         if (IS_VALLEYVIEW(dev)) {
5705                 refclk = 100000;
5706         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5707             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5708                 refclk = dev_priv->vbt.lvds_ssc_freq;
5709                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5710         } else if (!IS_GEN2(dev)) {
5711                 refclk = 96000;
5712         } else {
5713                 refclk = 48000;
5714         }
5715
5716         return refclk;
5717 }
5718
5719 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5720 {
5721         return (1 << dpll->n) << 16 | dpll->m2;
5722 }
5723
5724 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5725 {
5726         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5727 }
5728
5729 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5730                                      intel_clock_t *reduced_clock)
5731 {
5732         struct drm_device *dev = crtc->base.dev;
5733         u32 fp, fp2 = 0;
5734
5735         if (IS_PINEVIEW(dev)) {
5736                 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5737                 if (reduced_clock)
5738                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5739         } else {
5740                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5741                 if (reduced_clock)
5742                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5743         }
5744
5745         crtc->new_config->dpll_hw_state.fp0 = fp;
5746
5747         crtc->lowfreq_avail = false;
5748         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5749             reduced_clock && i915.powersave) {
5750                 crtc->new_config->dpll_hw_state.fp1 = fp2;
5751                 crtc->lowfreq_avail = true;
5752         } else {
5753                 crtc->new_config->dpll_hw_state.fp1 = fp;
5754         }
5755 }
5756
5757 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5758                 pipe)
5759 {
5760         u32 reg_val;
5761
5762         /*
5763          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5764          * and set it to a reasonable value instead.
5765          */
5766         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5767         reg_val &= 0xffffff00;
5768         reg_val |= 0x00000030;
5769         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5770
5771         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5772         reg_val &= 0x8cffffff;
5773         reg_val = 0x8c000000;
5774         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5775
5776         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5777         reg_val &= 0xffffff00;
5778         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5779
5780         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5781         reg_val &= 0x00ffffff;
5782         reg_val |= 0xb0000000;
5783         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5784 }
5785
5786 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5787                                          struct intel_link_m_n *m_n)
5788 {
5789         struct drm_device *dev = crtc->base.dev;
5790         struct drm_i915_private *dev_priv = dev->dev_private;
5791         int pipe = crtc->pipe;
5792
5793         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5794         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5795         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5796         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5797 }
5798
5799 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5800                                          struct intel_link_m_n *m_n,
5801                                          struct intel_link_m_n *m2_n2)
5802 {
5803         struct drm_device *dev = crtc->base.dev;
5804         struct drm_i915_private *dev_priv = dev->dev_private;
5805         int pipe = crtc->pipe;
5806         enum transcoder transcoder = crtc->config.cpu_transcoder;
5807
5808         if (INTEL_INFO(dev)->gen >= 5) {
5809                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5810                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5811                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5812                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5813                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5814                  * for gen < 8) and if DRRS is supported (to make sure the
5815                  * registers are not unnecessarily accessed).
5816                  */
5817                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5818                         crtc->config.has_drrs) {
5819                         I915_WRITE(PIPE_DATA_M2(transcoder),
5820                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5821                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5822                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5823                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5824                 }
5825         } else {
5826                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5827                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5828                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5829                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5830         }
5831 }
5832
5833 void intel_dp_set_m_n(struct intel_crtc *crtc)
5834 {
5835         if (crtc->config.has_pch_encoder)
5836                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5837         else
5838                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5839                                                    &crtc->config.dp_m2_n2);
5840 }
5841
5842 static void vlv_update_pll(struct intel_crtc *crtc,
5843                            struct intel_crtc_config *pipe_config)
5844 {
5845         u32 dpll, dpll_md;
5846
5847         /*
5848          * Enable DPIO clock input. We should never disable the reference
5849          * clock for pipe B, since VGA hotplug / manual detection depends
5850          * on it.
5851          */
5852         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5853                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5854         /* We should never disable this, set it here for state tracking */
5855         if (crtc->pipe == PIPE_B)
5856                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5857         dpll |= DPLL_VCO_ENABLE;
5858         pipe_config->dpll_hw_state.dpll = dpll;
5859
5860         dpll_md = (pipe_config->pixel_multiplier - 1)
5861                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5862         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5863 }
5864
5865 static void vlv_prepare_pll(struct intel_crtc *crtc,
5866                             const struct intel_crtc_config *pipe_config)
5867 {
5868         struct drm_device *dev = crtc->base.dev;
5869         struct drm_i915_private *dev_priv = dev->dev_private;
5870         int pipe = crtc->pipe;
5871         u32 mdiv;
5872         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5873         u32 coreclk, reg_val;
5874
5875         mutex_lock(&dev_priv->dpio_lock);
5876
5877         bestn = pipe_config->dpll.n;
5878         bestm1 = pipe_config->dpll.m1;
5879         bestm2 = pipe_config->dpll.m2;
5880         bestp1 = pipe_config->dpll.p1;
5881         bestp2 = pipe_config->dpll.p2;
5882
5883         /* See eDP HDMI DPIO driver vbios notes doc */
5884
5885         /* PLL B needs special handling */
5886         if (pipe == PIPE_B)
5887                 vlv_pllb_recal_opamp(dev_priv, pipe);
5888
5889         /* Set up Tx target for periodic Rcomp update */
5890         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5891
5892         /* Disable target IRef on PLL */
5893         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5894         reg_val &= 0x00ffffff;
5895         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5896
5897         /* Disable fast lock */
5898         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5899
5900         /* Set idtafcrecal before PLL is enabled */
5901         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5902         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5903         mdiv |= ((bestn << DPIO_N_SHIFT));
5904         mdiv |= (1 << DPIO_K_SHIFT);
5905
5906         /*
5907          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5908          * but we don't support that).
5909          * Note: don't use the DAC post divider as it seems unstable.
5910          */
5911         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5912         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5913
5914         mdiv |= DPIO_ENABLE_CALIBRATION;
5915         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5916
5917         /* Set HBR and RBR LPF coefficients */
5918         if (pipe_config->port_clock == 162000 ||
5919             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5920             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5921                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5922                                  0x009f0003);
5923         else
5924                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5925                                  0x00d0000f);
5926
5927         if (crtc->config.has_dp_encoder) {
5928                 /* Use SSC source */
5929                 if (pipe == PIPE_A)
5930                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5931                                          0x0df40000);
5932                 else
5933                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5934                                          0x0df70000);
5935         } else { /* HDMI or VGA */
5936                 /* Use bend source */
5937                 if (pipe == PIPE_A)
5938                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5939                                          0x0df70000);
5940                 else
5941                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5942                                          0x0df40000);
5943         }
5944
5945         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5946         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5947         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5948             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5949                 coreclk |= 0x01000000;
5950         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5951
5952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5953         mutex_unlock(&dev_priv->dpio_lock);
5954 }
5955
5956 static void chv_update_pll(struct intel_crtc *crtc,
5957                            struct intel_crtc_config *pipe_config)
5958 {
5959         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5960                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5961                 DPLL_VCO_ENABLE;
5962         if (crtc->pipe != PIPE_A)
5963                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5964
5965         pipe_config->dpll_hw_state.dpll_md =
5966                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5967 }
5968
5969 static void chv_prepare_pll(struct intel_crtc *crtc,
5970                             const struct intel_crtc_config *pipe_config)
5971 {
5972         struct drm_device *dev = crtc->base.dev;
5973         struct drm_i915_private *dev_priv = dev->dev_private;
5974         int pipe = crtc->pipe;
5975         int dpll_reg = DPLL(crtc->pipe);
5976         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5977         u32 loopfilter, intcoeff;
5978         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5979         int refclk;
5980
5981         bestn = pipe_config->dpll.n;
5982         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5983         bestm1 = pipe_config->dpll.m1;
5984         bestm2 = pipe_config->dpll.m2 >> 22;
5985         bestp1 = pipe_config->dpll.p1;
5986         bestp2 = pipe_config->dpll.p2;
5987
5988         /*
5989          * Enable Refclk and SSC
5990          */
5991         I915_WRITE(dpll_reg,
5992                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5993
5994         mutex_lock(&dev_priv->dpio_lock);
5995
5996         /* p1 and p2 divider */
5997         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5998                         5 << DPIO_CHV_S1_DIV_SHIFT |
5999                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6000                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6001                         1 << DPIO_CHV_K_DIV_SHIFT);
6002
6003         /* Feedback post-divider - m2 */
6004         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6005
6006         /* Feedback refclk divider - n and m1 */
6007         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6008                         DPIO_CHV_M1_DIV_BY_2 |
6009                         1 << DPIO_CHV_N_DIV_SHIFT);
6010
6011         /* M2 fraction division */
6012         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6013
6014         /* M2 fraction division enable */
6015         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6016                        DPIO_CHV_FRAC_DIV_EN |
6017                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6018
6019         /* Loop filter */
6020         refclk = i9xx_get_refclk(crtc, 0);
6021         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6022                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6023         if (refclk == 100000)
6024                 intcoeff = 11;
6025         else if (refclk == 38400)
6026                 intcoeff = 10;
6027         else
6028                 intcoeff = 9;
6029         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6030         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6031
6032         /* AFC Recal */
6033         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6034                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6035                         DPIO_AFC_RECAL);
6036
6037         mutex_unlock(&dev_priv->dpio_lock);
6038 }
6039
6040 /**
6041  * vlv_force_pll_on - forcibly enable just the PLL
6042  * @dev_priv: i915 private structure
6043  * @pipe: pipe PLL to enable
6044  * @dpll: PLL configuration
6045  *
6046  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6047  * in cases where we need the PLL enabled even when @pipe is not going to
6048  * be enabled.
6049  */
6050 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6051                       const struct dpll *dpll)
6052 {
6053         struct intel_crtc *crtc =
6054                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6055         struct intel_crtc_config pipe_config = {
6056                 .pixel_multiplier = 1,
6057                 .dpll = *dpll,
6058         };
6059
6060         if (IS_CHERRYVIEW(dev)) {
6061                 chv_update_pll(crtc, &pipe_config);
6062                 chv_prepare_pll(crtc, &pipe_config);
6063                 chv_enable_pll(crtc, &pipe_config);
6064         } else {
6065                 vlv_update_pll(crtc, &pipe_config);
6066                 vlv_prepare_pll(crtc, &pipe_config);
6067                 vlv_enable_pll(crtc, &pipe_config);
6068         }
6069 }
6070
6071 /**
6072  * vlv_force_pll_off - forcibly disable just the PLL
6073  * @dev_priv: i915 private structure
6074  * @pipe: pipe PLL to disable
6075  *
6076  * Disable the PLL for @pipe. To be used in cases where we need
6077  * the PLL enabled even when @pipe is not going to be enabled.
6078  */
6079 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6080 {
6081         if (IS_CHERRYVIEW(dev))
6082                 chv_disable_pll(to_i915(dev), pipe);
6083         else
6084                 vlv_disable_pll(to_i915(dev), pipe);
6085 }
6086
6087 static void i9xx_update_pll(struct intel_crtc *crtc,
6088                             intel_clock_t *reduced_clock,
6089                             int num_connectors)
6090 {
6091         struct drm_device *dev = crtc->base.dev;
6092         struct drm_i915_private *dev_priv = dev->dev_private;
6093         u32 dpll;
6094         bool is_sdvo;
6095         struct dpll *clock = &crtc->new_config->dpll;
6096
6097         i9xx_update_pll_dividers(crtc, reduced_clock);
6098
6099         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6100                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6101
6102         dpll = DPLL_VGA_MODE_DIS;
6103
6104         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6105                 dpll |= DPLLB_MODE_LVDS;
6106         else
6107                 dpll |= DPLLB_MODE_DAC_SERIAL;
6108
6109         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6110                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6111                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6112         }
6113
6114         if (is_sdvo)
6115                 dpll |= DPLL_SDVO_HIGH_SPEED;
6116
6117         if (crtc->new_config->has_dp_encoder)
6118                 dpll |= DPLL_SDVO_HIGH_SPEED;
6119
6120         /* compute bitmask from p1 value */
6121         if (IS_PINEVIEW(dev))
6122                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6123         else {
6124                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6125                 if (IS_G4X(dev) && reduced_clock)
6126                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6127         }
6128         switch (clock->p2) {
6129         case 5:
6130                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6131                 break;
6132         case 7:
6133                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6134                 break;
6135         case 10:
6136                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6137                 break;
6138         case 14:
6139                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6140                 break;
6141         }
6142         if (INTEL_INFO(dev)->gen >= 4)
6143                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6144
6145         if (crtc->new_config->sdvo_tv_clock)
6146                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6147         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6148                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6149                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6150         else
6151                 dpll |= PLL_REF_INPUT_DREFCLK;
6152
6153         dpll |= DPLL_VCO_ENABLE;
6154         crtc->new_config->dpll_hw_state.dpll = dpll;
6155
6156         if (INTEL_INFO(dev)->gen >= 4) {
6157                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6158                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6159                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6160         }
6161 }
6162
6163 static void i8xx_update_pll(struct intel_crtc *crtc,
6164                             intel_clock_t *reduced_clock,
6165                             int num_connectors)
6166 {
6167         struct drm_device *dev = crtc->base.dev;
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169         u32 dpll;
6170         struct dpll *clock = &crtc->new_config->dpll;
6171
6172         i9xx_update_pll_dividers(crtc, reduced_clock);
6173
6174         dpll = DPLL_VGA_MODE_DIS;
6175
6176         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6177                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6178         } else {
6179                 if (clock->p1 == 2)
6180                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6181                 else
6182                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6183                 if (clock->p2 == 4)
6184                         dpll |= PLL_P2_DIVIDE_BY_4;
6185         }
6186
6187         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6188                 dpll |= DPLL_DVO_2X_MODE;
6189
6190         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6191                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6192                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6193         else
6194                 dpll |= PLL_REF_INPUT_DREFCLK;
6195
6196         dpll |= DPLL_VCO_ENABLE;
6197         crtc->new_config->dpll_hw_state.dpll = dpll;
6198 }
6199
6200 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6201 {
6202         struct drm_device *dev = intel_crtc->base.dev;
6203         struct drm_i915_private *dev_priv = dev->dev_private;
6204         enum pipe pipe = intel_crtc->pipe;
6205         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6206         struct drm_display_mode *adjusted_mode =
6207                 &intel_crtc->config.adjusted_mode;
6208         uint32_t crtc_vtotal, crtc_vblank_end;
6209         int vsyncshift = 0;
6210
6211         /* We need to be careful not to changed the adjusted mode, for otherwise
6212          * the hw state checker will get angry at the mismatch. */
6213         crtc_vtotal = adjusted_mode->crtc_vtotal;
6214         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6215
6216         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6217                 /* the chip adds 2 halflines automatically */
6218                 crtc_vtotal -= 1;
6219                 crtc_vblank_end -= 1;
6220
6221                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6222                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6223                 else
6224                         vsyncshift = adjusted_mode->crtc_hsync_start -
6225                                 adjusted_mode->crtc_htotal / 2;
6226                 if (vsyncshift < 0)
6227                         vsyncshift += adjusted_mode->crtc_htotal;
6228         }
6229
6230         if (INTEL_INFO(dev)->gen > 3)
6231                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6232
6233         I915_WRITE(HTOTAL(cpu_transcoder),
6234                    (adjusted_mode->crtc_hdisplay - 1) |
6235                    ((adjusted_mode->crtc_htotal - 1) << 16));
6236         I915_WRITE(HBLANK(cpu_transcoder),
6237                    (adjusted_mode->crtc_hblank_start - 1) |
6238                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6239         I915_WRITE(HSYNC(cpu_transcoder),
6240                    (adjusted_mode->crtc_hsync_start - 1) |
6241                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6242
6243         I915_WRITE(VTOTAL(cpu_transcoder),
6244                    (adjusted_mode->crtc_vdisplay - 1) |
6245                    ((crtc_vtotal - 1) << 16));
6246         I915_WRITE(VBLANK(cpu_transcoder),
6247                    (adjusted_mode->crtc_vblank_start - 1) |
6248                    ((crtc_vblank_end - 1) << 16));
6249         I915_WRITE(VSYNC(cpu_transcoder),
6250                    (adjusted_mode->crtc_vsync_start - 1) |
6251                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6252
6253         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6254          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6255          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6256          * bits. */
6257         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6258             (pipe == PIPE_B || pipe == PIPE_C))
6259                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6260
6261         /* pipesrc controls the size that is scaled from, which should
6262          * always be the user's requested size.
6263          */
6264         I915_WRITE(PIPESRC(pipe),
6265                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6266                    (intel_crtc->config.pipe_src_h - 1));
6267 }
6268
6269 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6270                                    struct intel_crtc_config *pipe_config)
6271 {
6272         struct drm_device *dev = crtc->base.dev;
6273         struct drm_i915_private *dev_priv = dev->dev_private;
6274         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6275         uint32_t tmp;
6276
6277         tmp = I915_READ(HTOTAL(cpu_transcoder));
6278         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6279         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6280         tmp = I915_READ(HBLANK(cpu_transcoder));
6281         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6282         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6283         tmp = I915_READ(HSYNC(cpu_transcoder));
6284         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6285         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6286
6287         tmp = I915_READ(VTOTAL(cpu_transcoder));
6288         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6289         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6290         tmp = I915_READ(VBLANK(cpu_transcoder));
6291         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6292         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6293         tmp = I915_READ(VSYNC(cpu_transcoder));
6294         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6295         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6296
6297         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6298                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6299                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6300                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6301         }
6302
6303         tmp = I915_READ(PIPESRC(crtc->pipe));
6304         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6305         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6306
6307         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6308         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6309 }
6310
6311 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6312                                  struct intel_crtc_config *pipe_config)
6313 {
6314         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6315         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6316         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6317         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6318
6319         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6320         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6321         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6322         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6323
6324         mode->flags = pipe_config->adjusted_mode.flags;
6325
6326         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6327         mode->flags |= pipe_config->adjusted_mode.flags;
6328 }
6329
6330 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6331 {
6332         struct drm_device *dev = intel_crtc->base.dev;
6333         struct drm_i915_private *dev_priv = dev->dev_private;
6334         uint32_t pipeconf;
6335
6336         pipeconf = 0;
6337
6338         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6339             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6340                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6341
6342         if (intel_crtc->config.double_wide)
6343                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6344
6345         /* only g4x and later have fancy bpc/dither controls */
6346         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6347                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6348                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6349                         pipeconf |= PIPECONF_DITHER_EN |
6350                                     PIPECONF_DITHER_TYPE_SP;
6351
6352                 switch (intel_crtc->config.pipe_bpp) {
6353                 case 18:
6354                         pipeconf |= PIPECONF_6BPC;
6355                         break;
6356                 case 24:
6357                         pipeconf |= PIPECONF_8BPC;
6358                         break;
6359                 case 30:
6360                         pipeconf |= PIPECONF_10BPC;
6361                         break;
6362                 default:
6363                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6364                         BUG();
6365                 }
6366         }
6367
6368         if (HAS_PIPE_CXSR(dev)) {
6369                 if (intel_crtc->lowfreq_avail) {
6370                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6371                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6372                 } else {
6373                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6374                 }
6375         }
6376
6377         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6378                 if (INTEL_INFO(dev)->gen < 4 ||
6379                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6380                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6381                 else
6382                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6383         } else
6384                 pipeconf |= PIPECONF_PROGRESSIVE;
6385
6386         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6387                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6388
6389         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6390         POSTING_READ(PIPECONF(intel_crtc->pipe));
6391 }
6392
6393 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6394 {
6395         struct drm_device *dev = crtc->base.dev;
6396         struct drm_i915_private *dev_priv = dev->dev_private;
6397         int refclk, num_connectors = 0;
6398         intel_clock_t clock, reduced_clock;
6399         bool ok, has_reduced_clock = false;
6400         bool is_lvds = false, is_dsi = false;
6401         struct intel_encoder *encoder;
6402         const intel_limit_t *limit;
6403
6404         for_each_intel_encoder(dev, encoder) {
6405                 if (encoder->new_crtc != crtc)
6406                         continue;
6407
6408                 switch (encoder->type) {
6409                 case INTEL_OUTPUT_LVDS:
6410                         is_lvds = true;
6411                         break;
6412                 case INTEL_OUTPUT_DSI:
6413                         is_dsi = true;
6414                         break;
6415                 default:
6416                         break;
6417                 }
6418
6419                 num_connectors++;
6420         }
6421
6422         if (is_dsi)
6423                 return 0;
6424
6425         if (!crtc->new_config->clock_set) {
6426                 refclk = i9xx_get_refclk(crtc, num_connectors);
6427
6428                 /*
6429                  * Returns a set of divisors for the desired target clock with
6430                  * the given refclk, or FALSE.  The returned values represent
6431                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6432                  * 2) / p1 / p2.
6433                  */
6434                 limit = intel_limit(crtc, refclk);
6435                 ok = dev_priv->display.find_dpll(limit, crtc,
6436                                                  crtc->new_config->port_clock,
6437                                                  refclk, NULL, &clock);
6438                 if (!ok) {
6439                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6440                         return -EINVAL;
6441                 }
6442
6443                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6444                         /*
6445                          * Ensure we match the reduced clock's P to the target
6446                          * clock.  If the clocks don't match, we can't switch
6447                          * the display clock by using the FP0/FP1. In such case
6448                          * we will disable the LVDS downclock feature.
6449                          */
6450                         has_reduced_clock =
6451                                 dev_priv->display.find_dpll(limit, crtc,
6452                                                             dev_priv->lvds_downclock,
6453                                                             refclk, &clock,
6454                                                             &reduced_clock);
6455                 }
6456                 /* Compat-code for transition, will disappear. */
6457                 crtc->new_config->dpll.n = clock.n;
6458                 crtc->new_config->dpll.m1 = clock.m1;
6459                 crtc->new_config->dpll.m2 = clock.m2;
6460                 crtc->new_config->dpll.p1 = clock.p1;
6461                 crtc->new_config->dpll.p2 = clock.p2;
6462         }
6463
6464         if (IS_GEN2(dev)) {
6465                 i8xx_update_pll(crtc,
6466                                 has_reduced_clock ? &reduced_clock : NULL,
6467                                 num_connectors);
6468         } else if (IS_CHERRYVIEW(dev)) {
6469                 chv_update_pll(crtc, crtc->new_config);
6470         } else if (IS_VALLEYVIEW(dev)) {
6471                 vlv_update_pll(crtc, crtc->new_config);
6472         } else {
6473                 i9xx_update_pll(crtc,
6474                                 has_reduced_clock ? &reduced_clock : NULL,
6475                                 num_connectors);
6476         }
6477
6478         return 0;
6479 }
6480
6481 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6482                                  struct intel_crtc_config *pipe_config)
6483 {
6484         struct drm_device *dev = crtc->base.dev;
6485         struct drm_i915_private *dev_priv = dev->dev_private;
6486         uint32_t tmp;
6487
6488         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6489                 return;
6490
6491         tmp = I915_READ(PFIT_CONTROL);
6492         if (!(tmp & PFIT_ENABLE))
6493                 return;
6494
6495         /* Check whether the pfit is attached to our pipe. */
6496         if (INTEL_INFO(dev)->gen < 4) {
6497                 if (crtc->pipe != PIPE_B)
6498                         return;
6499         } else {
6500                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6501                         return;
6502         }
6503
6504         pipe_config->gmch_pfit.control = tmp;
6505         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6506         if (INTEL_INFO(dev)->gen < 5)
6507                 pipe_config->gmch_pfit.lvds_border_bits =
6508                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6509 }
6510
6511 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6512                                struct intel_crtc_config *pipe_config)
6513 {
6514         struct drm_device *dev = crtc->base.dev;
6515         struct drm_i915_private *dev_priv = dev->dev_private;
6516         int pipe = pipe_config->cpu_transcoder;
6517         intel_clock_t clock;
6518         u32 mdiv;
6519         int refclk = 100000;
6520
6521         /* In case of MIPI DPLL will not even be used */
6522         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6523                 return;
6524
6525         mutex_lock(&dev_priv->dpio_lock);
6526         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6527         mutex_unlock(&dev_priv->dpio_lock);
6528
6529         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6530         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6531         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6532         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6533         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6534
6535         vlv_clock(refclk, &clock);
6536
6537         /* clock.dot is the fast clock */
6538         pipe_config->port_clock = clock.dot / 5;
6539 }
6540
6541 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6542                                   struct intel_plane_config *plane_config)
6543 {
6544         struct drm_device *dev = crtc->base.dev;
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546         u32 val, base, offset;
6547         int pipe = crtc->pipe, plane = crtc->plane;
6548         int fourcc, pixel_format;
6549         int aligned_height;
6550
6551         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6552         if (!crtc->base.primary->fb) {
6553                 DRM_DEBUG_KMS("failed to alloc fb\n");
6554                 return;
6555         }
6556
6557         val = I915_READ(DSPCNTR(plane));
6558
6559         if (INTEL_INFO(dev)->gen >= 4)
6560                 if (val & DISPPLANE_TILED)
6561                         plane_config->tiled = true;
6562
6563         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6564         fourcc = intel_format_to_fourcc(pixel_format);
6565         crtc->base.primary->fb->pixel_format = fourcc;
6566         crtc->base.primary->fb->bits_per_pixel =
6567                 drm_format_plane_cpp(fourcc, 0) * 8;
6568
6569         if (INTEL_INFO(dev)->gen >= 4) {
6570                 if (plane_config->tiled)
6571                         offset = I915_READ(DSPTILEOFF(plane));
6572                 else
6573                         offset = I915_READ(DSPLINOFF(plane));
6574                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6575         } else {
6576                 base = I915_READ(DSPADDR(plane));
6577         }
6578         plane_config->base = base;
6579
6580         val = I915_READ(PIPESRC(pipe));
6581         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6582         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6583
6584         val = I915_READ(DSPSTRIDE(pipe));
6585         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6586
6587         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6588                                             plane_config->tiled);
6589
6590         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6591                                         aligned_height);
6592
6593         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6594                       pipe, plane, crtc->base.primary->fb->width,
6595                       crtc->base.primary->fb->height,
6596                       crtc->base.primary->fb->bits_per_pixel, base,
6597                       crtc->base.primary->fb->pitches[0],
6598                       plane_config->size);
6599
6600 }
6601
6602 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6603                                struct intel_crtc_config *pipe_config)
6604 {
6605         struct drm_device *dev = crtc->base.dev;
6606         struct drm_i915_private *dev_priv = dev->dev_private;
6607         int pipe = pipe_config->cpu_transcoder;
6608         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6609         intel_clock_t clock;
6610         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6611         int refclk = 100000;
6612
6613         mutex_lock(&dev_priv->dpio_lock);
6614         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6615         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6616         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6617         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6618         mutex_unlock(&dev_priv->dpio_lock);
6619
6620         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6621         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6622         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6623         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6624         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6625
6626         chv_clock(refclk, &clock);
6627
6628         /* clock.dot is the fast clock */
6629         pipe_config->port_clock = clock.dot / 5;
6630 }
6631
6632 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6633                                  struct intel_crtc_config *pipe_config)
6634 {
6635         struct drm_device *dev = crtc->base.dev;
6636         struct drm_i915_private *dev_priv = dev->dev_private;
6637         uint32_t tmp;
6638
6639         if (!intel_display_power_is_enabled(dev_priv,
6640                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6641                 return false;
6642
6643         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6644         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6645
6646         tmp = I915_READ(PIPECONF(crtc->pipe));
6647         if (!(tmp & PIPECONF_ENABLE))
6648                 return false;
6649
6650         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6651                 switch (tmp & PIPECONF_BPC_MASK) {
6652                 case PIPECONF_6BPC:
6653                         pipe_config->pipe_bpp = 18;
6654                         break;
6655                 case PIPECONF_8BPC:
6656                         pipe_config->pipe_bpp = 24;
6657                         break;
6658                 case PIPECONF_10BPC:
6659                         pipe_config->pipe_bpp = 30;
6660                         break;
6661                 default:
6662                         break;
6663                 }
6664         }
6665
6666         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6667                 pipe_config->limited_color_range = true;
6668
6669         if (INTEL_INFO(dev)->gen < 4)
6670                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6671
6672         intel_get_pipe_timings(crtc, pipe_config);
6673
6674         i9xx_get_pfit_config(crtc, pipe_config);
6675
6676         if (INTEL_INFO(dev)->gen >= 4) {
6677                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6678                 pipe_config->pixel_multiplier =
6679                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6680                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6681                 pipe_config->dpll_hw_state.dpll_md = tmp;
6682         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6683                 tmp = I915_READ(DPLL(crtc->pipe));
6684                 pipe_config->pixel_multiplier =
6685                         ((tmp & SDVO_MULTIPLIER_MASK)
6686                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6687         } else {
6688                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6689                  * port and will be fixed up in the encoder->get_config
6690                  * function. */
6691                 pipe_config->pixel_multiplier = 1;
6692         }
6693         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6694         if (!IS_VALLEYVIEW(dev)) {
6695                 /*
6696                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6697                  * on 830. Filter it out here so that we don't
6698                  * report errors due to that.
6699                  */
6700                 if (IS_I830(dev))
6701                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6702
6703                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6704                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6705         } else {
6706                 /* Mask out read-only status bits. */
6707                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6708                                                      DPLL_PORTC_READY_MASK |
6709                                                      DPLL_PORTB_READY_MASK);
6710         }
6711
6712         if (IS_CHERRYVIEW(dev))
6713                 chv_crtc_clock_get(crtc, pipe_config);
6714         else if (IS_VALLEYVIEW(dev))
6715                 vlv_crtc_clock_get(crtc, pipe_config);
6716         else
6717                 i9xx_crtc_clock_get(crtc, pipe_config);
6718
6719         return true;
6720 }
6721
6722 static void ironlake_init_pch_refclk(struct drm_device *dev)
6723 {
6724         struct drm_i915_private *dev_priv = dev->dev_private;
6725         struct intel_encoder *encoder;
6726         u32 val, final;
6727         bool has_lvds = false;
6728         bool has_cpu_edp = false;
6729         bool has_panel = false;
6730         bool has_ck505 = false;
6731         bool can_ssc = false;
6732
6733         /* We need to take the global config into account */
6734         for_each_intel_encoder(dev, encoder) {
6735                 switch (encoder->type) {
6736                 case INTEL_OUTPUT_LVDS:
6737                         has_panel = true;
6738                         has_lvds = true;
6739                         break;
6740                 case INTEL_OUTPUT_EDP:
6741                         has_panel = true;
6742                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6743                                 has_cpu_edp = true;
6744                         break;
6745                 default:
6746                         break;
6747                 }
6748         }
6749
6750         if (HAS_PCH_IBX(dev)) {
6751                 has_ck505 = dev_priv->vbt.display_clock_mode;
6752                 can_ssc = has_ck505;
6753         } else {
6754                 has_ck505 = false;
6755                 can_ssc = true;
6756         }
6757
6758         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6759                       has_panel, has_lvds, has_ck505);
6760
6761         /* Ironlake: try to setup display ref clock before DPLL
6762          * enabling. This is only under driver's control after
6763          * PCH B stepping, previous chipset stepping should be
6764          * ignoring this setting.
6765          */
6766         val = I915_READ(PCH_DREF_CONTROL);
6767
6768         /* As we must carefully and slowly disable/enable each source in turn,
6769          * compute the final state we want first and check if we need to
6770          * make any changes at all.
6771          */
6772         final = val;
6773         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6774         if (has_ck505)
6775                 final |= DREF_NONSPREAD_CK505_ENABLE;
6776         else
6777                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6778
6779         final &= ~DREF_SSC_SOURCE_MASK;
6780         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6781         final &= ~DREF_SSC1_ENABLE;
6782
6783         if (has_panel) {
6784                 final |= DREF_SSC_SOURCE_ENABLE;
6785
6786                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6787                         final |= DREF_SSC1_ENABLE;
6788
6789                 if (has_cpu_edp) {
6790                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6791                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6792                         else
6793                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6794                 } else
6795                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6796         } else {
6797                 final |= DREF_SSC_SOURCE_DISABLE;
6798                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6799         }
6800
6801         if (final == val)
6802                 return;
6803
6804         /* Always enable nonspread source */
6805         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6806
6807         if (has_ck505)
6808                 val |= DREF_NONSPREAD_CK505_ENABLE;
6809         else
6810                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6811
6812         if (has_panel) {
6813                 val &= ~DREF_SSC_SOURCE_MASK;
6814                 val |= DREF_SSC_SOURCE_ENABLE;
6815
6816                 /* SSC must be turned on before enabling the CPU output  */
6817                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6818                         DRM_DEBUG_KMS("Using SSC on panel\n");
6819                         val |= DREF_SSC1_ENABLE;
6820                 } else
6821                         val &= ~DREF_SSC1_ENABLE;
6822
6823                 /* Get SSC going before enabling the outputs */
6824                 I915_WRITE(PCH_DREF_CONTROL, val);
6825                 POSTING_READ(PCH_DREF_CONTROL);
6826                 udelay(200);
6827
6828                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6829
6830                 /* Enable CPU source on CPU attached eDP */
6831                 if (has_cpu_edp) {
6832                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6833                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6834                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6835                         } else
6836                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6837                 } else
6838                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6839
6840                 I915_WRITE(PCH_DREF_CONTROL, val);
6841                 POSTING_READ(PCH_DREF_CONTROL);
6842                 udelay(200);
6843         } else {
6844                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6845
6846                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6847
6848                 /* Turn off CPU output */
6849                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6850
6851                 I915_WRITE(PCH_DREF_CONTROL, val);
6852                 POSTING_READ(PCH_DREF_CONTROL);
6853                 udelay(200);
6854
6855                 /* Turn off the SSC source */
6856                 val &= ~DREF_SSC_SOURCE_MASK;
6857                 val |= DREF_SSC_SOURCE_DISABLE;
6858
6859                 /* Turn off SSC1 */
6860                 val &= ~DREF_SSC1_ENABLE;
6861
6862                 I915_WRITE(PCH_DREF_CONTROL, val);
6863                 POSTING_READ(PCH_DREF_CONTROL);
6864                 udelay(200);
6865         }
6866
6867         BUG_ON(val != final);
6868 }
6869
6870 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6871 {
6872         uint32_t tmp;
6873
6874         tmp = I915_READ(SOUTH_CHICKEN2);
6875         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6876         I915_WRITE(SOUTH_CHICKEN2, tmp);
6877
6878         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6879                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6880                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6881
6882         tmp = I915_READ(SOUTH_CHICKEN2);
6883         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6884         I915_WRITE(SOUTH_CHICKEN2, tmp);
6885
6886         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6887                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6888                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6889 }
6890
6891 /* WaMPhyProgramming:hsw */
6892 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6893 {
6894         uint32_t tmp;
6895
6896         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6897         tmp &= ~(0xFF << 24);
6898         tmp |= (0x12 << 24);
6899         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6900
6901         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6902         tmp |= (1 << 11);
6903         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6904
6905         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6906         tmp |= (1 << 11);
6907         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6908
6909         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6910         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6911         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6912
6913         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6914         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6915         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6916
6917         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6918         tmp &= ~(7 << 13);
6919         tmp |= (5 << 13);
6920         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6921
6922         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6923         tmp &= ~(7 << 13);
6924         tmp |= (5 << 13);
6925         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6926
6927         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6928         tmp &= ~0xFF;
6929         tmp |= 0x1C;
6930         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6931
6932         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6933         tmp &= ~0xFF;
6934         tmp |= 0x1C;
6935         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6936
6937         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6938         tmp &= ~(0xFF << 16);
6939         tmp |= (0x1C << 16);
6940         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6941
6942         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6943         tmp &= ~(0xFF << 16);
6944         tmp |= (0x1C << 16);
6945         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6946
6947         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6948         tmp |= (1 << 27);
6949         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6950
6951         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6952         tmp |= (1 << 27);
6953         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6954
6955         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6956         tmp &= ~(0xF << 28);
6957         tmp |= (4 << 28);
6958         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6959
6960         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6961         tmp &= ~(0xF << 28);
6962         tmp |= (4 << 28);
6963         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6964 }
6965
6966 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6967  * Programming" based on the parameters passed:
6968  * - Sequence to enable CLKOUT_DP
6969  * - Sequence to enable CLKOUT_DP without spread
6970  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6971  */
6972 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6973                                  bool with_fdi)
6974 {
6975         struct drm_i915_private *dev_priv = dev->dev_private;
6976         uint32_t reg, tmp;
6977
6978         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6979                 with_spread = true;
6980         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6981                  with_fdi, "LP PCH doesn't have FDI\n"))
6982                 with_fdi = false;
6983
6984         mutex_lock(&dev_priv->dpio_lock);
6985
6986         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6987         tmp &= ~SBI_SSCCTL_DISABLE;
6988         tmp |= SBI_SSCCTL_PATHALT;
6989         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6990
6991         udelay(24);
6992
6993         if (with_spread) {
6994                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6995                 tmp &= ~SBI_SSCCTL_PATHALT;
6996                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6997
6998                 if (with_fdi) {
6999                         lpt_reset_fdi_mphy(dev_priv);
7000                         lpt_program_fdi_mphy(dev_priv);
7001                 }
7002         }
7003
7004         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7005                SBI_GEN0 : SBI_DBUFF0;
7006         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7007         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7008         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7009
7010         mutex_unlock(&dev_priv->dpio_lock);
7011 }
7012
7013 /* Sequence to disable CLKOUT_DP */
7014 static void lpt_disable_clkout_dp(struct drm_device *dev)
7015 {
7016         struct drm_i915_private *dev_priv = dev->dev_private;
7017         uint32_t reg, tmp;
7018
7019         mutex_lock(&dev_priv->dpio_lock);
7020
7021         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7022                SBI_GEN0 : SBI_DBUFF0;
7023         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7024         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7025         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7026
7027         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7028         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7029                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7030                         tmp |= SBI_SSCCTL_PATHALT;
7031                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7032                         udelay(32);
7033                 }
7034                 tmp |= SBI_SSCCTL_DISABLE;
7035                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7036         }
7037
7038         mutex_unlock(&dev_priv->dpio_lock);
7039 }
7040
7041 static void lpt_init_pch_refclk(struct drm_device *dev)
7042 {
7043         struct intel_encoder *encoder;
7044         bool has_vga = false;
7045
7046         for_each_intel_encoder(dev, encoder) {
7047                 switch (encoder->type) {
7048                 case INTEL_OUTPUT_ANALOG:
7049                         has_vga = true;
7050                         break;
7051                 default:
7052                         break;
7053                 }
7054         }
7055
7056         if (has_vga)
7057                 lpt_enable_clkout_dp(dev, true, true);
7058         else
7059                 lpt_disable_clkout_dp(dev);
7060 }
7061
7062 /*
7063  * Initialize reference clocks when the driver loads
7064  */
7065 void intel_init_pch_refclk(struct drm_device *dev)
7066 {
7067         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7068                 ironlake_init_pch_refclk(dev);
7069         else if (HAS_PCH_LPT(dev))
7070                 lpt_init_pch_refclk(dev);
7071 }
7072
7073 static int ironlake_get_refclk(struct drm_crtc *crtc)
7074 {
7075         struct drm_device *dev = crtc->dev;
7076         struct drm_i915_private *dev_priv = dev->dev_private;
7077         struct intel_encoder *encoder;
7078         int num_connectors = 0;
7079         bool is_lvds = false;
7080
7081         for_each_intel_encoder(dev, encoder) {
7082                 if (encoder->new_crtc != to_intel_crtc(crtc))
7083                         continue;
7084
7085                 switch (encoder->type) {
7086                 case INTEL_OUTPUT_LVDS:
7087                         is_lvds = true;
7088                         break;
7089                 default:
7090                         break;
7091                 }
7092                 num_connectors++;
7093         }
7094
7095         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7096                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7097                               dev_priv->vbt.lvds_ssc_freq);
7098                 return dev_priv->vbt.lvds_ssc_freq;
7099         }
7100
7101         return 120000;
7102 }
7103
7104 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7105 {
7106         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108         int pipe = intel_crtc->pipe;
7109         uint32_t val;
7110
7111         val = 0;
7112
7113         switch (intel_crtc->config.pipe_bpp) {
7114         case 18:
7115                 val |= PIPECONF_6BPC;
7116                 break;
7117         case 24:
7118                 val |= PIPECONF_8BPC;
7119                 break;
7120         case 30:
7121                 val |= PIPECONF_10BPC;
7122                 break;
7123         case 36:
7124                 val |= PIPECONF_12BPC;
7125                 break;
7126         default:
7127                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7128                 BUG();
7129         }
7130
7131         if (intel_crtc->config.dither)
7132                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7133
7134         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7135                 val |= PIPECONF_INTERLACED_ILK;
7136         else
7137                 val |= PIPECONF_PROGRESSIVE;
7138
7139         if (intel_crtc->config.limited_color_range)
7140                 val |= PIPECONF_COLOR_RANGE_SELECT;
7141
7142         I915_WRITE(PIPECONF(pipe), val);
7143         POSTING_READ(PIPECONF(pipe));
7144 }
7145
7146 /*
7147  * Set up the pipe CSC unit.
7148  *
7149  * Currently only full range RGB to limited range RGB conversion
7150  * is supported, but eventually this should handle various
7151  * RGB<->YCbCr scenarios as well.
7152  */
7153 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7154 {
7155         struct drm_device *dev = crtc->dev;
7156         struct drm_i915_private *dev_priv = dev->dev_private;
7157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158         int pipe = intel_crtc->pipe;
7159         uint16_t coeff = 0x7800; /* 1.0 */
7160
7161         /*
7162          * TODO: Check what kind of values actually come out of the pipe
7163          * with these coeff/postoff values and adjust to get the best
7164          * accuracy. Perhaps we even need to take the bpc value into
7165          * consideration.
7166          */
7167
7168         if (intel_crtc->config.limited_color_range)
7169                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7170
7171         /*
7172          * GY/GU and RY/RU should be the other way around according
7173          * to BSpec, but reality doesn't agree. Just set them up in
7174          * a way that results in the correct picture.
7175          */
7176         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7177         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7178
7179         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7180         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7181
7182         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7183         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7184
7185         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7186         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7187         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7188
7189         if (INTEL_INFO(dev)->gen > 6) {
7190                 uint16_t postoff = 0;
7191
7192                 if (intel_crtc->config.limited_color_range)
7193                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7194
7195                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7196                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7197                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7198
7199                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7200         } else {
7201                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7202
7203                 if (intel_crtc->config.limited_color_range)
7204                         mode |= CSC_BLACK_SCREEN_OFFSET;
7205
7206                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7207         }
7208 }
7209
7210 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7211 {
7212         struct drm_device *dev = crtc->dev;
7213         struct drm_i915_private *dev_priv = dev->dev_private;
7214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7215         enum pipe pipe = intel_crtc->pipe;
7216         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7217         uint32_t val;
7218
7219         val = 0;
7220
7221         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7222                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7223
7224         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7225                 val |= PIPECONF_INTERLACED_ILK;
7226         else
7227                 val |= PIPECONF_PROGRESSIVE;
7228
7229         I915_WRITE(PIPECONF(cpu_transcoder), val);
7230         POSTING_READ(PIPECONF(cpu_transcoder));
7231
7232         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7233         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7234
7235         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7236                 val = 0;
7237
7238                 switch (intel_crtc->config.pipe_bpp) {
7239                 case 18:
7240                         val |= PIPEMISC_DITHER_6_BPC;
7241                         break;
7242                 case 24:
7243                         val |= PIPEMISC_DITHER_8_BPC;
7244                         break;
7245                 case 30:
7246                         val |= PIPEMISC_DITHER_10_BPC;
7247                         break;
7248                 case 36:
7249                         val |= PIPEMISC_DITHER_12_BPC;
7250                         break;
7251                 default:
7252                         /* Case prevented by pipe_config_set_bpp. */
7253                         BUG();
7254                 }
7255
7256                 if (intel_crtc->config.dither)
7257                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7258
7259                 I915_WRITE(PIPEMISC(pipe), val);
7260         }
7261 }
7262
7263 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7264                                     intel_clock_t *clock,
7265                                     bool *has_reduced_clock,
7266                                     intel_clock_t *reduced_clock)
7267 {
7268         struct drm_device *dev = crtc->dev;
7269         struct drm_i915_private *dev_priv = dev->dev_private;
7270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7271         int refclk;
7272         const intel_limit_t *limit;
7273         bool ret, is_lvds = false;
7274
7275         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7276
7277         refclk = ironlake_get_refclk(crtc);
7278
7279         /*
7280          * Returns a set of divisors for the desired target clock with the given
7281          * refclk, or FALSE.  The returned values represent the clock equation:
7282          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7283          */
7284         limit = intel_limit(intel_crtc, refclk);
7285         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7286                                           intel_crtc->new_config->port_clock,
7287                                           refclk, NULL, clock);
7288         if (!ret)
7289                 return false;
7290
7291         if (is_lvds && dev_priv->lvds_downclock_avail) {
7292                 /*
7293                  * Ensure we match the reduced clock's P to the target clock.
7294                  * If the clocks don't match, we can't switch the display clock
7295                  * by using the FP0/FP1. In such case we will disable the LVDS
7296                  * downclock feature.
7297                 */
7298                 *has_reduced_clock =
7299                         dev_priv->display.find_dpll(limit, intel_crtc,
7300                                                     dev_priv->lvds_downclock,
7301                                                     refclk, clock,
7302                                                     reduced_clock);
7303         }
7304
7305         return true;
7306 }
7307
7308 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7309 {
7310         /*
7311          * Account for spread spectrum to avoid
7312          * oversubscribing the link. Max center spread
7313          * is 2.5%; use 5% for safety's sake.
7314          */
7315         u32 bps = target_clock * bpp * 21 / 20;
7316         return DIV_ROUND_UP(bps, link_bw * 8);
7317 }
7318
7319 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7320 {
7321         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7322 }
7323
7324 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7325                                       u32 *fp,
7326                                       intel_clock_t *reduced_clock, u32 *fp2)
7327 {
7328         struct drm_crtc *crtc = &intel_crtc->base;
7329         struct drm_device *dev = crtc->dev;
7330         struct drm_i915_private *dev_priv = dev->dev_private;
7331         struct intel_encoder *intel_encoder;
7332         uint32_t dpll;
7333         int factor, num_connectors = 0;
7334         bool is_lvds = false, is_sdvo = false;
7335
7336         for_each_intel_encoder(dev, intel_encoder) {
7337                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7338                         continue;
7339
7340                 switch (intel_encoder->type) {
7341                 case INTEL_OUTPUT_LVDS:
7342                         is_lvds = true;
7343                         break;
7344                 case INTEL_OUTPUT_SDVO:
7345                 case INTEL_OUTPUT_HDMI:
7346                         is_sdvo = true;
7347                         break;
7348                 default:
7349                         break;
7350                 }
7351
7352                 num_connectors++;
7353         }
7354
7355         /* Enable autotuning of the PLL clock (if permissible) */
7356         factor = 21;
7357         if (is_lvds) {
7358                 if ((intel_panel_use_ssc(dev_priv) &&
7359                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7360                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7361                         factor = 25;
7362         } else if (intel_crtc->new_config->sdvo_tv_clock)
7363                 factor = 20;
7364
7365         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7366                 *fp |= FP_CB_TUNE;
7367
7368         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7369                 *fp2 |= FP_CB_TUNE;
7370
7371         dpll = 0;
7372
7373         if (is_lvds)
7374                 dpll |= DPLLB_MODE_LVDS;
7375         else
7376                 dpll |= DPLLB_MODE_DAC_SERIAL;
7377
7378         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7379                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7380
7381         if (is_sdvo)
7382                 dpll |= DPLL_SDVO_HIGH_SPEED;
7383         if (intel_crtc->new_config->has_dp_encoder)
7384                 dpll |= DPLL_SDVO_HIGH_SPEED;
7385
7386         /* compute bitmask from p1 value */
7387         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7388         /* also FPA1 */
7389         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7390
7391         switch (intel_crtc->new_config->dpll.p2) {
7392         case 5:
7393                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7394                 break;
7395         case 7:
7396                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7397                 break;
7398         case 10:
7399                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7400                 break;
7401         case 14:
7402                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7403                 break;
7404         }
7405
7406         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7407                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7408         else
7409                 dpll |= PLL_REF_INPUT_DREFCLK;
7410
7411         return dpll | DPLL_VCO_ENABLE;
7412 }
7413
7414 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7415 {
7416         struct drm_device *dev = crtc->base.dev;
7417         intel_clock_t clock, reduced_clock;
7418         u32 dpll = 0, fp = 0, fp2 = 0;
7419         bool ok, has_reduced_clock = false;
7420         bool is_lvds = false;
7421         struct intel_shared_dpll *pll;
7422
7423         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7424
7425         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7426              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7427
7428         ok = ironlake_compute_clocks(&crtc->base, &clock,
7429                                      &has_reduced_clock, &reduced_clock);
7430         if (!ok && !crtc->new_config->clock_set) {
7431                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7432                 return -EINVAL;
7433         }
7434         /* Compat-code for transition, will disappear. */
7435         if (!crtc->new_config->clock_set) {
7436                 crtc->new_config->dpll.n = clock.n;
7437                 crtc->new_config->dpll.m1 = clock.m1;
7438                 crtc->new_config->dpll.m2 = clock.m2;
7439                 crtc->new_config->dpll.p1 = clock.p1;
7440                 crtc->new_config->dpll.p2 = clock.p2;
7441         }
7442
7443         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7444         if (crtc->new_config->has_pch_encoder) {
7445                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7446                 if (has_reduced_clock)
7447                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7448
7449                 dpll = ironlake_compute_dpll(crtc,
7450                                              &fp, &reduced_clock,
7451                                              has_reduced_clock ? &fp2 : NULL);
7452
7453                 crtc->new_config->dpll_hw_state.dpll = dpll;
7454                 crtc->new_config->dpll_hw_state.fp0 = fp;
7455                 if (has_reduced_clock)
7456                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7457                 else
7458                         crtc->new_config->dpll_hw_state.fp1 = fp;
7459
7460                 pll = intel_get_shared_dpll(crtc);
7461                 if (pll == NULL) {
7462                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7463                                          pipe_name(crtc->pipe));
7464                         return -EINVAL;
7465                 }
7466         }
7467
7468         if (is_lvds && has_reduced_clock && i915.powersave)
7469                 crtc->lowfreq_avail = true;
7470         else
7471                 crtc->lowfreq_avail = false;
7472
7473         return 0;
7474 }
7475
7476 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7477                                          struct intel_link_m_n *m_n)
7478 {
7479         struct drm_device *dev = crtc->base.dev;
7480         struct drm_i915_private *dev_priv = dev->dev_private;
7481         enum pipe pipe = crtc->pipe;
7482
7483         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7484         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7485         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7486                 & ~TU_SIZE_MASK;
7487         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7488         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7489                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7490 }
7491
7492 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7493                                          enum transcoder transcoder,
7494                                          struct intel_link_m_n *m_n,
7495                                          struct intel_link_m_n *m2_n2)
7496 {
7497         struct drm_device *dev = crtc->base.dev;
7498         struct drm_i915_private *dev_priv = dev->dev_private;
7499         enum pipe pipe = crtc->pipe;
7500
7501         if (INTEL_INFO(dev)->gen >= 5) {
7502                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7503                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7504                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7505                         & ~TU_SIZE_MASK;
7506                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7507                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7508                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7509                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7510                  * gen < 8) and if DRRS is supported (to make sure the
7511                  * registers are not unnecessarily read).
7512                  */
7513                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7514                         crtc->config.has_drrs) {
7515                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7516                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7517                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7518                                         & ~TU_SIZE_MASK;
7519                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7520                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7521                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7522                 }
7523         } else {
7524                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7525                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7526                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7527                         & ~TU_SIZE_MASK;
7528                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7529                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7530                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7531         }
7532 }
7533
7534 void intel_dp_get_m_n(struct intel_crtc *crtc,
7535                       struct intel_crtc_config *pipe_config)
7536 {
7537         if (crtc->config.has_pch_encoder)
7538                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7539         else
7540                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7541                                              &pipe_config->dp_m_n,
7542                                              &pipe_config->dp_m2_n2);
7543 }
7544
7545 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7546                                         struct intel_crtc_config *pipe_config)
7547 {
7548         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7549                                      &pipe_config->fdi_m_n, NULL);
7550 }
7551
7552 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7553                                      struct intel_crtc_config *pipe_config)
7554 {
7555         struct drm_device *dev = crtc->base.dev;
7556         struct drm_i915_private *dev_priv = dev->dev_private;
7557         uint32_t tmp;
7558
7559         tmp = I915_READ(PF_CTL(crtc->pipe));
7560
7561         if (tmp & PF_ENABLE) {
7562                 pipe_config->pch_pfit.enabled = true;
7563                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7564                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7565
7566                 /* We currently do not free assignements of panel fitters on
7567                  * ivb/hsw (since we don't use the higher upscaling modes which
7568                  * differentiates them) so just WARN about this case for now. */
7569                 if (IS_GEN7(dev)) {
7570                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7571                                 PF_PIPE_SEL_IVB(crtc->pipe));
7572                 }
7573         }
7574 }
7575
7576 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7577                                       struct intel_plane_config *plane_config)
7578 {
7579         struct drm_device *dev = crtc->base.dev;
7580         struct drm_i915_private *dev_priv = dev->dev_private;
7581         u32 val, base, offset;
7582         int pipe = crtc->pipe, plane = crtc->plane;
7583         int fourcc, pixel_format;
7584         int aligned_height;
7585
7586         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7587         if (!crtc->base.primary->fb) {
7588                 DRM_DEBUG_KMS("failed to alloc fb\n");
7589                 return;
7590         }
7591
7592         val = I915_READ(DSPCNTR(plane));
7593
7594         if (INTEL_INFO(dev)->gen >= 4)
7595                 if (val & DISPPLANE_TILED)
7596                         plane_config->tiled = true;
7597
7598         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7599         fourcc = intel_format_to_fourcc(pixel_format);
7600         crtc->base.primary->fb->pixel_format = fourcc;
7601         crtc->base.primary->fb->bits_per_pixel =
7602                 drm_format_plane_cpp(fourcc, 0) * 8;
7603
7604         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7605         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7606                 offset = I915_READ(DSPOFFSET(plane));
7607         } else {
7608                 if (plane_config->tiled)
7609                         offset = I915_READ(DSPTILEOFF(plane));
7610                 else
7611                         offset = I915_READ(DSPLINOFF(plane));
7612         }
7613         plane_config->base = base;
7614
7615         val = I915_READ(PIPESRC(pipe));
7616         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7617         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7618
7619         val = I915_READ(DSPSTRIDE(pipe));
7620         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7621
7622         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7623                                             plane_config->tiled);
7624
7625         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7626                                         aligned_height);
7627
7628         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7629                       pipe, plane, crtc->base.primary->fb->width,
7630                       crtc->base.primary->fb->height,
7631                       crtc->base.primary->fb->bits_per_pixel, base,
7632                       crtc->base.primary->fb->pitches[0],
7633                       plane_config->size);
7634 }
7635
7636 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7637                                      struct intel_crtc_config *pipe_config)
7638 {
7639         struct drm_device *dev = crtc->base.dev;
7640         struct drm_i915_private *dev_priv = dev->dev_private;
7641         uint32_t tmp;
7642
7643         if (!intel_display_power_is_enabled(dev_priv,
7644                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7645                 return false;
7646
7647         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7648         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7649
7650         tmp = I915_READ(PIPECONF(crtc->pipe));
7651         if (!(tmp & PIPECONF_ENABLE))
7652                 return false;
7653
7654         switch (tmp & PIPECONF_BPC_MASK) {
7655         case PIPECONF_6BPC:
7656                 pipe_config->pipe_bpp = 18;
7657                 break;
7658         case PIPECONF_8BPC:
7659                 pipe_config->pipe_bpp = 24;
7660                 break;
7661         case PIPECONF_10BPC:
7662                 pipe_config->pipe_bpp = 30;
7663                 break;
7664         case PIPECONF_12BPC:
7665                 pipe_config->pipe_bpp = 36;
7666                 break;
7667         default:
7668                 break;
7669         }
7670
7671         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7672                 pipe_config->limited_color_range = true;
7673
7674         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7675                 struct intel_shared_dpll *pll;
7676
7677                 pipe_config->has_pch_encoder = true;
7678
7679                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7680                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7681                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7682
7683                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7684
7685                 if (HAS_PCH_IBX(dev_priv->dev)) {
7686                         pipe_config->shared_dpll =
7687                                 (enum intel_dpll_id) crtc->pipe;
7688                 } else {
7689                         tmp = I915_READ(PCH_DPLL_SEL);
7690                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7691                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7692                         else
7693                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7694                 }
7695
7696                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7697
7698                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7699                                            &pipe_config->dpll_hw_state));
7700
7701                 tmp = pipe_config->dpll_hw_state.dpll;
7702                 pipe_config->pixel_multiplier =
7703                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7704                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7705
7706                 ironlake_pch_clock_get(crtc, pipe_config);
7707         } else {
7708                 pipe_config->pixel_multiplier = 1;
7709         }
7710
7711         intel_get_pipe_timings(crtc, pipe_config);
7712
7713         ironlake_get_pfit_config(crtc, pipe_config);
7714
7715         return true;
7716 }
7717
7718 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7719 {
7720         struct drm_device *dev = dev_priv->dev;
7721         struct intel_crtc *crtc;
7722
7723         for_each_intel_crtc(dev, crtc)
7724                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7725                      pipe_name(crtc->pipe));
7726
7727         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7728         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7729         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7730         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7731         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7732         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7733              "CPU PWM1 enabled\n");
7734         if (IS_HASWELL(dev))
7735                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7736                      "CPU PWM2 enabled\n");
7737         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7738              "PCH PWM1 enabled\n");
7739         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7740              "Utility pin enabled\n");
7741         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7742
7743         /*
7744          * In theory we can still leave IRQs enabled, as long as only the HPD
7745          * interrupts remain enabled. We used to check for that, but since it's
7746          * gen-specific and since we only disable LCPLL after we fully disable
7747          * the interrupts, the check below should be enough.
7748          */
7749         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7750 }
7751
7752 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7753 {
7754         struct drm_device *dev = dev_priv->dev;
7755
7756         if (IS_HASWELL(dev))
7757                 return I915_READ(D_COMP_HSW);
7758         else
7759                 return I915_READ(D_COMP_BDW);
7760 }
7761
7762 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7763 {
7764         struct drm_device *dev = dev_priv->dev;
7765
7766         if (IS_HASWELL(dev)) {
7767                 mutex_lock(&dev_priv->rps.hw_lock);
7768                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7769                                             val))
7770                         DRM_ERROR("Failed to write to D_COMP\n");
7771                 mutex_unlock(&dev_priv->rps.hw_lock);
7772         } else {
7773                 I915_WRITE(D_COMP_BDW, val);
7774                 POSTING_READ(D_COMP_BDW);
7775         }
7776 }
7777
7778 /*
7779  * This function implements pieces of two sequences from BSpec:
7780  * - Sequence for display software to disable LCPLL
7781  * - Sequence for display software to allow package C8+
7782  * The steps implemented here are just the steps that actually touch the LCPLL
7783  * register. Callers should take care of disabling all the display engine
7784  * functions, doing the mode unset, fixing interrupts, etc.
7785  */
7786 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7787                               bool switch_to_fclk, bool allow_power_down)
7788 {
7789         uint32_t val;
7790
7791         assert_can_disable_lcpll(dev_priv);
7792
7793         val = I915_READ(LCPLL_CTL);
7794
7795         if (switch_to_fclk) {
7796                 val |= LCPLL_CD_SOURCE_FCLK;
7797                 I915_WRITE(LCPLL_CTL, val);
7798
7799                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7800                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7801                         DRM_ERROR("Switching to FCLK failed\n");
7802
7803                 val = I915_READ(LCPLL_CTL);
7804         }
7805
7806         val |= LCPLL_PLL_DISABLE;
7807         I915_WRITE(LCPLL_CTL, val);
7808         POSTING_READ(LCPLL_CTL);
7809
7810         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7811                 DRM_ERROR("LCPLL still locked\n");
7812
7813         val = hsw_read_dcomp(dev_priv);
7814         val |= D_COMP_COMP_DISABLE;
7815         hsw_write_dcomp(dev_priv, val);
7816         ndelay(100);
7817
7818         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7819                      1))
7820                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7821
7822         if (allow_power_down) {
7823                 val = I915_READ(LCPLL_CTL);
7824                 val |= LCPLL_POWER_DOWN_ALLOW;
7825                 I915_WRITE(LCPLL_CTL, val);
7826                 POSTING_READ(LCPLL_CTL);
7827         }
7828 }
7829
7830 /*
7831  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7832  * source.
7833  */
7834 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7835 {
7836         uint32_t val;
7837
7838         val = I915_READ(LCPLL_CTL);
7839
7840         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7841                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7842                 return;
7843
7844         /*
7845          * Make sure we're not on PC8 state before disabling PC8, otherwise
7846          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7847          *
7848          * The other problem is that hsw_restore_lcpll() is called as part of
7849          * the runtime PM resume sequence, so we can't just call
7850          * gen6_gt_force_wake_get() because that function calls
7851          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7852          * while we are on the resume sequence. So to solve this problem we have
7853          * to call special forcewake code that doesn't touch runtime PM and
7854          * doesn't enable the forcewake delayed work.
7855          */
7856         spin_lock_irq(&dev_priv->uncore.lock);
7857         if (dev_priv->uncore.forcewake_count++ == 0)
7858                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7859         spin_unlock_irq(&dev_priv->uncore.lock);
7860
7861         if (val & LCPLL_POWER_DOWN_ALLOW) {
7862                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7863                 I915_WRITE(LCPLL_CTL, val);
7864                 POSTING_READ(LCPLL_CTL);
7865         }
7866
7867         val = hsw_read_dcomp(dev_priv);
7868         val |= D_COMP_COMP_FORCE;
7869         val &= ~D_COMP_COMP_DISABLE;
7870         hsw_write_dcomp(dev_priv, val);
7871
7872         val = I915_READ(LCPLL_CTL);
7873         val &= ~LCPLL_PLL_DISABLE;
7874         I915_WRITE(LCPLL_CTL, val);
7875
7876         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7877                 DRM_ERROR("LCPLL not locked yet\n");
7878
7879         if (val & LCPLL_CD_SOURCE_FCLK) {
7880                 val = I915_READ(LCPLL_CTL);
7881                 val &= ~LCPLL_CD_SOURCE_FCLK;
7882                 I915_WRITE(LCPLL_CTL, val);
7883
7884                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7885                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7886                         DRM_ERROR("Switching back to LCPLL failed\n");
7887         }
7888
7889         /* See the big comment above. */
7890         spin_lock_irq(&dev_priv->uncore.lock);
7891         if (--dev_priv->uncore.forcewake_count == 0)
7892                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7893         spin_unlock_irq(&dev_priv->uncore.lock);
7894 }
7895
7896 /*
7897  * Package states C8 and deeper are really deep PC states that can only be
7898  * reached when all the devices on the system allow it, so even if the graphics
7899  * device allows PC8+, it doesn't mean the system will actually get to these
7900  * states. Our driver only allows PC8+ when going into runtime PM.
7901  *
7902  * The requirements for PC8+ are that all the outputs are disabled, the power
7903  * well is disabled and most interrupts are disabled, and these are also
7904  * requirements for runtime PM. When these conditions are met, we manually do
7905  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7906  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7907  * hang the machine.
7908  *
7909  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7910  * the state of some registers, so when we come back from PC8+ we need to
7911  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7912  * need to take care of the registers kept by RC6. Notice that this happens even
7913  * if we don't put the device in PCI D3 state (which is what currently happens
7914  * because of the runtime PM support).
7915  *
7916  * For more, read "Display Sequences for Package C8" on the hardware
7917  * documentation.
7918  */
7919 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7920 {
7921         struct drm_device *dev = dev_priv->dev;
7922         uint32_t val;
7923
7924         DRM_DEBUG_KMS("Enabling package C8+\n");
7925
7926         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7927                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7928                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7929                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7930         }
7931
7932         lpt_disable_clkout_dp(dev);
7933         hsw_disable_lcpll(dev_priv, true, true);
7934 }
7935
7936 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7937 {
7938         struct drm_device *dev = dev_priv->dev;
7939         uint32_t val;
7940
7941         DRM_DEBUG_KMS("Disabling package C8+\n");
7942
7943         hsw_restore_lcpll(dev_priv);
7944         lpt_init_pch_refclk(dev);
7945
7946         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7947                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7948                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7949                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7950         }
7951
7952         intel_prepare_ddi(dev);
7953 }
7954
7955 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7956 {
7957         if (!intel_ddi_pll_select(crtc))
7958                 return -EINVAL;
7959
7960         crtc->lowfreq_avail = false;
7961
7962         return 0;
7963 }
7964
7965 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7966                                 enum port port,
7967                                 struct intel_crtc_config *pipe_config)
7968 {
7969         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7970
7971         switch (pipe_config->ddi_pll_sel) {
7972         case PORT_CLK_SEL_WRPLL1:
7973                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7974                 break;
7975         case PORT_CLK_SEL_WRPLL2:
7976                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7977                 break;
7978         }
7979 }
7980
7981 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7982                                        struct intel_crtc_config *pipe_config)
7983 {
7984         struct drm_device *dev = crtc->base.dev;
7985         struct drm_i915_private *dev_priv = dev->dev_private;
7986         struct intel_shared_dpll *pll;
7987         enum port port;
7988         uint32_t tmp;
7989
7990         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7991
7992         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7993
7994         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7995
7996         if (pipe_config->shared_dpll >= 0) {
7997                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7998
7999                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8000                                            &pipe_config->dpll_hw_state));
8001         }
8002
8003         /*
8004          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8005          * DDI E. So just check whether this pipe is wired to DDI E and whether
8006          * the PCH transcoder is on.
8007          */
8008         if (INTEL_INFO(dev)->gen < 9 &&
8009             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8010                 pipe_config->has_pch_encoder = true;
8011
8012                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8013                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8014                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8015
8016                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8017         }
8018 }
8019
8020 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8021                                     struct intel_crtc_config *pipe_config)
8022 {
8023         struct drm_device *dev = crtc->base.dev;
8024         struct drm_i915_private *dev_priv = dev->dev_private;
8025         enum intel_display_power_domain pfit_domain;
8026         uint32_t tmp;
8027
8028         if (!intel_display_power_is_enabled(dev_priv,
8029                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8030                 return false;
8031
8032         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8033         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8034
8035         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8036         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8037                 enum pipe trans_edp_pipe;
8038                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8039                 default:
8040                         WARN(1, "unknown pipe linked to edp transcoder\n");
8041                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8042                 case TRANS_DDI_EDP_INPUT_A_ON:
8043                         trans_edp_pipe = PIPE_A;
8044                         break;
8045                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8046                         trans_edp_pipe = PIPE_B;
8047                         break;
8048                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8049                         trans_edp_pipe = PIPE_C;
8050                         break;
8051                 }
8052
8053                 if (trans_edp_pipe == crtc->pipe)
8054                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8055         }
8056
8057         if (!intel_display_power_is_enabled(dev_priv,
8058                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8059                 return false;
8060
8061         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8062         if (!(tmp & PIPECONF_ENABLE))
8063                 return false;
8064
8065         haswell_get_ddi_port_state(crtc, pipe_config);
8066
8067         intel_get_pipe_timings(crtc, pipe_config);
8068
8069         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8070         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8071                 ironlake_get_pfit_config(crtc, pipe_config);
8072
8073         if (IS_HASWELL(dev))
8074                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8075                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8076
8077         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8078                 pipe_config->pixel_multiplier =
8079                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8080         } else {
8081                 pipe_config->pixel_multiplier = 1;
8082         }
8083
8084         return true;
8085 }
8086
8087 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8088 {
8089         struct drm_device *dev = crtc->dev;
8090         struct drm_i915_private *dev_priv = dev->dev_private;
8091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8092         uint32_t cntl = 0, size = 0;
8093
8094         if (base) {
8095                 unsigned int width = intel_crtc->cursor_width;
8096                 unsigned int height = intel_crtc->cursor_height;
8097                 unsigned int stride = roundup_pow_of_two(width) * 4;
8098
8099                 switch (stride) {
8100                 default:
8101                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8102                                   width, stride);
8103                         stride = 256;
8104                         /* fallthrough */
8105                 case 256:
8106                 case 512:
8107                 case 1024:
8108                 case 2048:
8109                         break;
8110                 }
8111
8112                 cntl |= CURSOR_ENABLE |
8113                         CURSOR_GAMMA_ENABLE |
8114                         CURSOR_FORMAT_ARGB |
8115                         CURSOR_STRIDE(stride);
8116
8117                 size = (height << 12) | width;
8118         }
8119
8120         if (intel_crtc->cursor_cntl != 0 &&
8121             (intel_crtc->cursor_base != base ||
8122              intel_crtc->cursor_size != size ||
8123              intel_crtc->cursor_cntl != cntl)) {
8124                 /* On these chipsets we can only modify the base/size/stride
8125                  * whilst the cursor is disabled.
8126                  */
8127                 I915_WRITE(_CURACNTR, 0);
8128                 POSTING_READ(_CURACNTR);
8129                 intel_crtc->cursor_cntl = 0;
8130         }
8131
8132         if (intel_crtc->cursor_base != base) {
8133                 I915_WRITE(_CURABASE, base);
8134                 intel_crtc->cursor_base = base;
8135         }
8136
8137         if (intel_crtc->cursor_size != size) {
8138                 I915_WRITE(CURSIZE, size);
8139                 intel_crtc->cursor_size = size;
8140         }
8141
8142         if (intel_crtc->cursor_cntl != cntl) {
8143                 I915_WRITE(_CURACNTR, cntl);
8144                 POSTING_READ(_CURACNTR);
8145                 intel_crtc->cursor_cntl = cntl;
8146         }
8147 }
8148
8149 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8150 {
8151         struct drm_device *dev = crtc->dev;
8152         struct drm_i915_private *dev_priv = dev->dev_private;
8153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8154         int pipe = intel_crtc->pipe;
8155         uint32_t cntl;
8156
8157         cntl = 0;
8158         if (base) {
8159                 cntl = MCURSOR_GAMMA_ENABLE;
8160                 switch (intel_crtc->cursor_width) {
8161                         case 64:
8162                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8163                                 break;
8164                         case 128:
8165                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8166                                 break;
8167                         case 256:
8168                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8169                                 break;
8170                         default:
8171                                 WARN_ON(1);
8172                                 return;
8173                 }
8174                 cntl |= pipe << 28; /* Connect to correct pipe */
8175
8176                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8177                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8178         }
8179
8180         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8181                 cntl |= CURSOR_ROTATE_180;
8182
8183         if (intel_crtc->cursor_cntl != cntl) {
8184                 I915_WRITE(CURCNTR(pipe), cntl);
8185                 POSTING_READ(CURCNTR(pipe));
8186                 intel_crtc->cursor_cntl = cntl;
8187         }
8188
8189         /* and commit changes on next vblank */
8190         I915_WRITE(CURBASE(pipe), base);
8191         POSTING_READ(CURBASE(pipe));
8192
8193         intel_crtc->cursor_base = base;
8194 }
8195
8196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8197 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8198                                      bool on)
8199 {
8200         struct drm_device *dev = crtc->dev;
8201         struct drm_i915_private *dev_priv = dev->dev_private;
8202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8203         int pipe = intel_crtc->pipe;
8204         int x = crtc->cursor_x;
8205         int y = crtc->cursor_y;
8206         u32 base = 0, pos = 0;
8207
8208         if (on)
8209                 base = intel_crtc->cursor_addr;
8210
8211         if (x >= intel_crtc->config.pipe_src_w)
8212                 base = 0;
8213
8214         if (y >= intel_crtc->config.pipe_src_h)
8215                 base = 0;
8216
8217         if (x < 0) {
8218                 if (x + intel_crtc->cursor_width <= 0)
8219                         base = 0;
8220
8221                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8222                 x = -x;
8223         }
8224         pos |= x << CURSOR_X_SHIFT;
8225
8226         if (y < 0) {
8227                 if (y + intel_crtc->cursor_height <= 0)
8228                         base = 0;
8229
8230                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8231                 y = -y;
8232         }
8233         pos |= y << CURSOR_Y_SHIFT;
8234
8235         if (base == 0 && intel_crtc->cursor_base == 0)
8236                 return;
8237
8238         I915_WRITE(CURPOS(pipe), pos);
8239
8240         /* ILK+ do this automagically */
8241         if (HAS_GMCH_DISPLAY(dev) &&
8242                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8243                 base += (intel_crtc->cursor_height *
8244                         intel_crtc->cursor_width - 1) * 4;
8245         }
8246
8247         if (IS_845G(dev) || IS_I865G(dev))
8248                 i845_update_cursor(crtc, base);
8249         else
8250                 i9xx_update_cursor(crtc, base);
8251 }
8252
8253 static bool cursor_size_ok(struct drm_device *dev,
8254                            uint32_t width, uint32_t height)
8255 {
8256         if (width == 0 || height == 0)
8257                 return false;
8258
8259         /*
8260          * 845g/865g are special in that they are only limited by
8261          * the width of their cursors, the height is arbitrary up to
8262          * the precision of the register. Everything else requires
8263          * square cursors, limited to a few power-of-two sizes.
8264          */
8265         if (IS_845G(dev) || IS_I865G(dev)) {
8266                 if ((width & 63) != 0)
8267                         return false;
8268
8269                 if (width > (IS_845G(dev) ? 64 : 512))
8270                         return false;
8271
8272                 if (height > 1023)
8273                         return false;
8274         } else {
8275                 switch (width | height) {
8276                 case 256:
8277                 case 128:
8278                         if (IS_GEN2(dev))
8279                                 return false;
8280                 case 64:
8281                         break;
8282                 default:
8283                         return false;
8284                 }
8285         }
8286
8287         return true;
8288 }
8289
8290 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8291                                      struct drm_i915_gem_object *obj,
8292                                      uint32_t width, uint32_t height)
8293 {
8294         struct drm_device *dev = crtc->dev;
8295         struct drm_i915_private *dev_priv = dev->dev_private;
8296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8297         enum pipe pipe = intel_crtc->pipe;
8298         unsigned old_width;
8299         uint32_t addr;
8300         int ret;
8301
8302         /* if we want to turn off the cursor ignore width and height */
8303         if (!obj) {
8304                 DRM_DEBUG_KMS("cursor off\n");
8305                 addr = 0;
8306                 mutex_lock(&dev->struct_mutex);
8307                 goto finish;
8308         }
8309
8310         /* we only need to pin inside GTT if cursor is non-phy */
8311         mutex_lock(&dev->struct_mutex);
8312         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8313                 unsigned alignment;
8314
8315                 /*
8316                  * Global gtt pte registers are special registers which actually
8317                  * forward writes to a chunk of system memory. Which means that
8318                  * there is no risk that the register values disappear as soon
8319                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8320                  * only the pin/unpin/fence and not more.
8321                  */
8322                 intel_runtime_pm_get(dev_priv);
8323
8324                 /* Note that the w/a also requires 2 PTE of padding following
8325                  * the bo. We currently fill all unused PTE with the shadow
8326                  * page and so we should always have valid PTE following the
8327                  * cursor preventing the VT-d warning.
8328                  */
8329                 alignment = 0;
8330                 if (need_vtd_wa(dev))
8331                         alignment = 64*1024;
8332
8333                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8334                 if (ret) {
8335                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8336                         intel_runtime_pm_put(dev_priv);
8337                         goto fail_locked;
8338                 }
8339
8340                 ret = i915_gem_object_put_fence(obj);
8341                 if (ret) {
8342                         DRM_DEBUG_KMS("failed to release fence for cursor");
8343                         intel_runtime_pm_put(dev_priv);
8344                         goto fail_unpin;
8345                 }
8346
8347                 addr = i915_gem_obj_ggtt_offset(obj);
8348
8349                 intel_runtime_pm_put(dev_priv);
8350         } else {
8351                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8352                 ret = i915_gem_object_attach_phys(obj, align);
8353                 if (ret) {
8354                         DRM_DEBUG_KMS("failed to attach phys object\n");
8355                         goto fail_locked;
8356                 }
8357                 addr = obj->phys_handle->busaddr;
8358         }
8359
8360  finish:
8361         if (intel_crtc->cursor_bo) {
8362                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8363                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8364         }
8365
8366         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8367                           INTEL_FRONTBUFFER_CURSOR(pipe));
8368         mutex_unlock(&dev->struct_mutex);
8369
8370         old_width = intel_crtc->cursor_width;
8371
8372         intel_crtc->cursor_addr = addr;
8373         intel_crtc->cursor_bo = obj;
8374         intel_crtc->cursor_width = width;
8375         intel_crtc->cursor_height = height;
8376
8377         if (intel_crtc->active) {
8378                 if (old_width != width)
8379                         intel_update_watermarks(crtc);
8380                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8381
8382                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8383         }
8384
8385         return 0;
8386 fail_unpin:
8387         i915_gem_object_unpin_from_display_plane(obj);
8388 fail_locked:
8389         mutex_unlock(&dev->struct_mutex);
8390         return ret;
8391 }
8392
8393 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8394                                  u16 *blue, uint32_t start, uint32_t size)
8395 {
8396         int end = (start + size > 256) ? 256 : start + size, i;
8397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8398
8399         for (i = start; i < end; i++) {
8400                 intel_crtc->lut_r[i] = red[i] >> 8;
8401                 intel_crtc->lut_g[i] = green[i] >> 8;
8402                 intel_crtc->lut_b[i] = blue[i] >> 8;
8403         }
8404
8405         intel_crtc_load_lut(crtc);
8406 }
8407
8408 /* VESA 640x480x72Hz mode to set on the pipe */
8409 static struct drm_display_mode load_detect_mode = {
8410         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8411                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8412 };
8413
8414 struct drm_framebuffer *
8415 __intel_framebuffer_create(struct drm_device *dev,
8416                            struct drm_mode_fb_cmd2 *mode_cmd,
8417                            struct drm_i915_gem_object *obj)
8418 {
8419         struct intel_framebuffer *intel_fb;
8420         int ret;
8421
8422         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8423         if (!intel_fb) {
8424                 drm_gem_object_unreference(&obj->base);
8425                 return ERR_PTR(-ENOMEM);
8426         }
8427
8428         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8429         if (ret)
8430                 goto err;
8431
8432         return &intel_fb->base;
8433 err:
8434         drm_gem_object_unreference(&obj->base);
8435         kfree(intel_fb);
8436
8437         return ERR_PTR(ret);
8438 }
8439
8440 static struct drm_framebuffer *
8441 intel_framebuffer_create(struct drm_device *dev,
8442                          struct drm_mode_fb_cmd2 *mode_cmd,
8443                          struct drm_i915_gem_object *obj)
8444 {
8445         struct drm_framebuffer *fb;
8446         int ret;
8447
8448         ret = i915_mutex_lock_interruptible(dev);
8449         if (ret)
8450                 return ERR_PTR(ret);
8451         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8452         mutex_unlock(&dev->struct_mutex);
8453
8454         return fb;
8455 }
8456
8457 static u32
8458 intel_framebuffer_pitch_for_width(int width, int bpp)
8459 {
8460         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8461         return ALIGN(pitch, 64);
8462 }
8463
8464 static u32
8465 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8466 {
8467         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8468         return PAGE_ALIGN(pitch * mode->vdisplay);
8469 }
8470
8471 static struct drm_framebuffer *
8472 intel_framebuffer_create_for_mode(struct drm_device *dev,
8473                                   struct drm_display_mode *mode,
8474                                   int depth, int bpp)
8475 {
8476         struct drm_i915_gem_object *obj;
8477         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8478
8479         obj = i915_gem_alloc_object(dev,
8480                                     intel_framebuffer_size_for_mode(mode, bpp));
8481         if (obj == NULL)
8482                 return ERR_PTR(-ENOMEM);
8483
8484         mode_cmd.width = mode->hdisplay;
8485         mode_cmd.height = mode->vdisplay;
8486         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8487                                                                 bpp);
8488         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8489
8490         return intel_framebuffer_create(dev, &mode_cmd, obj);
8491 }
8492
8493 static struct drm_framebuffer *
8494 mode_fits_in_fbdev(struct drm_device *dev,
8495                    struct drm_display_mode *mode)
8496 {
8497 #ifdef CONFIG_DRM_I915_FBDEV
8498         struct drm_i915_private *dev_priv = dev->dev_private;
8499         struct drm_i915_gem_object *obj;
8500         struct drm_framebuffer *fb;
8501
8502         if (!dev_priv->fbdev)
8503                 return NULL;
8504
8505         if (!dev_priv->fbdev->fb)
8506                 return NULL;
8507
8508         obj = dev_priv->fbdev->fb->obj;
8509         BUG_ON(!obj);
8510
8511         fb = &dev_priv->fbdev->fb->base;
8512         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8513                                                                fb->bits_per_pixel))
8514                 return NULL;
8515
8516         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8517                 return NULL;
8518
8519         return fb;
8520 #else
8521         return NULL;
8522 #endif
8523 }
8524
8525 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8526                                 struct drm_display_mode *mode,
8527                                 struct intel_load_detect_pipe *old,
8528                                 struct drm_modeset_acquire_ctx *ctx)
8529 {
8530         struct intel_crtc *intel_crtc;
8531         struct intel_encoder *intel_encoder =
8532                 intel_attached_encoder(connector);
8533         struct drm_crtc *possible_crtc;
8534         struct drm_encoder *encoder = &intel_encoder->base;
8535         struct drm_crtc *crtc = NULL;
8536         struct drm_device *dev = encoder->dev;
8537         struct drm_framebuffer *fb;
8538         struct drm_mode_config *config = &dev->mode_config;
8539         int ret, i = -1;
8540
8541         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8542                       connector->base.id, connector->name,
8543                       encoder->base.id, encoder->name);
8544
8545 retry:
8546         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8547         if (ret)
8548                 goto fail_unlock;
8549
8550         /*
8551          * Algorithm gets a little messy:
8552          *
8553          *   - if the connector already has an assigned crtc, use it (but make
8554          *     sure it's on first)
8555          *
8556          *   - try to find the first unused crtc that can drive this connector,
8557          *     and use that if we find one
8558          */
8559
8560         /* See if we already have a CRTC for this connector */
8561         if (encoder->crtc) {
8562                 crtc = encoder->crtc;
8563
8564                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8565                 if (ret)
8566                         goto fail_unlock;
8567
8568                 old->dpms_mode = connector->dpms;
8569                 old->load_detect_temp = false;
8570
8571                 /* Make sure the crtc and connector are running */
8572                 if (connector->dpms != DRM_MODE_DPMS_ON)
8573                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8574
8575                 return true;
8576         }
8577
8578         /* Find an unused one (if possible) */
8579         for_each_crtc(dev, possible_crtc) {
8580                 i++;
8581                 if (!(encoder->possible_crtcs & (1 << i)))
8582                         continue;
8583                 if (possible_crtc->enabled)
8584                         continue;
8585                 /* This can occur when applying the pipe A quirk on resume. */
8586                 if (to_intel_crtc(possible_crtc)->new_enabled)
8587                         continue;
8588
8589                 crtc = possible_crtc;
8590                 break;
8591         }
8592
8593         /*
8594          * If we didn't find an unused CRTC, don't use any.
8595          */
8596         if (!crtc) {
8597                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8598                 goto fail_unlock;
8599         }
8600
8601         ret = drm_modeset_lock(&crtc->mutex, ctx);
8602         if (ret)
8603                 goto fail_unlock;
8604         intel_encoder->new_crtc = to_intel_crtc(crtc);
8605         to_intel_connector(connector)->new_encoder = intel_encoder;
8606
8607         intel_crtc = to_intel_crtc(crtc);
8608         intel_crtc->new_enabled = true;
8609         intel_crtc->new_config = &intel_crtc->config;
8610         old->dpms_mode = connector->dpms;
8611         old->load_detect_temp = true;
8612         old->release_fb = NULL;
8613
8614         if (!mode)
8615                 mode = &load_detect_mode;
8616
8617         /* We need a framebuffer large enough to accommodate all accesses
8618          * that the plane may generate whilst we perform load detection.
8619          * We can not rely on the fbcon either being present (we get called
8620          * during its initialisation to detect all boot displays, or it may
8621          * not even exist) or that it is large enough to satisfy the
8622          * requested mode.
8623          */
8624         fb = mode_fits_in_fbdev(dev, mode);
8625         if (fb == NULL) {
8626                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8627                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8628                 old->release_fb = fb;
8629         } else
8630                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8631         if (IS_ERR(fb)) {
8632                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8633                 goto fail;
8634         }
8635
8636         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8637                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8638                 if (old->release_fb)
8639                         old->release_fb->funcs->destroy(old->release_fb);
8640                 goto fail;
8641         }
8642
8643         /* let the connector get through one full cycle before testing */
8644         intel_wait_for_vblank(dev, intel_crtc->pipe);
8645         return true;
8646
8647  fail:
8648         intel_crtc->new_enabled = crtc->enabled;
8649         if (intel_crtc->new_enabled)
8650                 intel_crtc->new_config = &intel_crtc->config;
8651         else
8652                 intel_crtc->new_config = NULL;
8653 fail_unlock:
8654         if (ret == -EDEADLK) {
8655                 drm_modeset_backoff(ctx);
8656                 goto retry;
8657         }
8658
8659         return false;
8660 }
8661
8662 void intel_release_load_detect_pipe(struct drm_connector *connector,
8663                                     struct intel_load_detect_pipe *old)
8664 {
8665         struct intel_encoder *intel_encoder =
8666                 intel_attached_encoder(connector);
8667         struct drm_encoder *encoder = &intel_encoder->base;
8668         struct drm_crtc *crtc = encoder->crtc;
8669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8670
8671         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8672                       connector->base.id, connector->name,
8673                       encoder->base.id, encoder->name);
8674
8675         if (old->load_detect_temp) {
8676                 to_intel_connector(connector)->new_encoder = NULL;
8677                 intel_encoder->new_crtc = NULL;
8678                 intel_crtc->new_enabled = false;
8679                 intel_crtc->new_config = NULL;
8680                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8681
8682                 if (old->release_fb) {
8683                         drm_framebuffer_unregister_private(old->release_fb);
8684                         drm_framebuffer_unreference(old->release_fb);
8685                 }
8686
8687                 return;
8688         }
8689
8690         /* Switch crtc and encoder back off if necessary */
8691         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8692                 connector->funcs->dpms(connector, old->dpms_mode);
8693 }
8694
8695 static int i9xx_pll_refclk(struct drm_device *dev,
8696                            const struct intel_crtc_config *pipe_config)
8697 {
8698         struct drm_i915_private *dev_priv = dev->dev_private;
8699         u32 dpll = pipe_config->dpll_hw_state.dpll;
8700
8701         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8702                 return dev_priv->vbt.lvds_ssc_freq;
8703         else if (HAS_PCH_SPLIT(dev))
8704                 return 120000;
8705         else if (!IS_GEN2(dev))
8706                 return 96000;
8707         else
8708                 return 48000;
8709 }
8710
8711 /* Returns the clock of the currently programmed mode of the given pipe. */
8712 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8713                                 struct intel_crtc_config *pipe_config)
8714 {
8715         struct drm_device *dev = crtc->base.dev;
8716         struct drm_i915_private *dev_priv = dev->dev_private;
8717         int pipe = pipe_config->cpu_transcoder;
8718         u32 dpll = pipe_config->dpll_hw_state.dpll;
8719         u32 fp;
8720         intel_clock_t clock;
8721         int refclk = i9xx_pll_refclk(dev, pipe_config);
8722
8723         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8724                 fp = pipe_config->dpll_hw_state.fp0;
8725         else
8726                 fp = pipe_config->dpll_hw_state.fp1;
8727
8728         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8729         if (IS_PINEVIEW(dev)) {
8730                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8731                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8732         } else {
8733                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8734                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8735         }
8736
8737         if (!IS_GEN2(dev)) {
8738                 if (IS_PINEVIEW(dev))
8739                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8740                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8741                 else
8742                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8743                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8744
8745                 switch (dpll & DPLL_MODE_MASK) {
8746                 case DPLLB_MODE_DAC_SERIAL:
8747                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8748                                 5 : 10;
8749                         break;
8750                 case DPLLB_MODE_LVDS:
8751                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8752                                 7 : 14;
8753                         break;
8754                 default:
8755                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8756                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8757                         return;
8758                 }
8759
8760                 if (IS_PINEVIEW(dev))
8761                         pineview_clock(refclk, &clock);
8762                 else
8763                         i9xx_clock(refclk, &clock);
8764         } else {
8765                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8766                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8767
8768                 if (is_lvds) {
8769                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8770                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8771
8772                         if (lvds & LVDS_CLKB_POWER_UP)
8773                                 clock.p2 = 7;
8774                         else
8775                                 clock.p2 = 14;
8776                 } else {
8777                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8778                                 clock.p1 = 2;
8779                         else {
8780                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8781                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8782                         }
8783                         if (dpll & PLL_P2_DIVIDE_BY_4)
8784                                 clock.p2 = 4;
8785                         else
8786                                 clock.p2 = 2;
8787                 }
8788
8789                 i9xx_clock(refclk, &clock);
8790         }
8791
8792         /*
8793          * This value includes pixel_multiplier. We will use
8794          * port_clock to compute adjusted_mode.crtc_clock in the
8795          * encoder's get_config() function.
8796          */
8797         pipe_config->port_clock = clock.dot;
8798 }
8799
8800 int intel_dotclock_calculate(int link_freq,
8801                              const struct intel_link_m_n *m_n)
8802 {
8803         /*
8804          * The calculation for the data clock is:
8805          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8806          * But we want to avoid losing precison if possible, so:
8807          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8808          *
8809          * and the link clock is simpler:
8810          * link_clock = (m * link_clock) / n
8811          */
8812
8813         if (!m_n->link_n)
8814                 return 0;
8815
8816         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8817 }
8818
8819 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8820                                    struct intel_crtc_config *pipe_config)
8821 {
8822         struct drm_device *dev = crtc->base.dev;
8823
8824         /* read out port_clock from the DPLL */
8825         i9xx_crtc_clock_get(crtc, pipe_config);
8826
8827         /*
8828          * This value does not include pixel_multiplier.
8829          * We will check that port_clock and adjusted_mode.crtc_clock
8830          * agree once we know their relationship in the encoder's
8831          * get_config() function.
8832          */
8833         pipe_config->adjusted_mode.crtc_clock =
8834                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8835                                          &pipe_config->fdi_m_n);
8836 }
8837
8838 /** Returns the currently programmed mode of the given pipe. */
8839 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8840                                              struct drm_crtc *crtc)
8841 {
8842         struct drm_i915_private *dev_priv = dev->dev_private;
8843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8844         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8845         struct drm_display_mode *mode;
8846         struct intel_crtc_config pipe_config;
8847         int htot = I915_READ(HTOTAL(cpu_transcoder));
8848         int hsync = I915_READ(HSYNC(cpu_transcoder));
8849         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8850         int vsync = I915_READ(VSYNC(cpu_transcoder));
8851         enum pipe pipe = intel_crtc->pipe;
8852
8853         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8854         if (!mode)
8855                 return NULL;
8856
8857         /*
8858          * Construct a pipe_config sufficient for getting the clock info
8859          * back out of crtc_clock_get.
8860          *
8861          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8862          * to use a real value here instead.
8863          */
8864         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8865         pipe_config.pixel_multiplier = 1;
8866         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8867         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8868         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8869         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8870
8871         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8872         mode->hdisplay = (htot & 0xffff) + 1;
8873         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8874         mode->hsync_start = (hsync & 0xffff) + 1;
8875         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8876         mode->vdisplay = (vtot & 0xffff) + 1;
8877         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8878         mode->vsync_start = (vsync & 0xffff) + 1;
8879         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8880
8881         drm_mode_set_name(mode);
8882
8883         return mode;
8884 }
8885
8886 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8887 {
8888         struct drm_device *dev = crtc->dev;
8889         struct drm_i915_private *dev_priv = dev->dev_private;
8890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8891
8892         if (!HAS_GMCH_DISPLAY(dev))
8893                 return;
8894
8895         if (!dev_priv->lvds_downclock_avail)
8896                 return;
8897
8898         /*
8899          * Since this is called by a timer, we should never get here in
8900          * the manual case.
8901          */
8902         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8903                 int pipe = intel_crtc->pipe;
8904                 int dpll_reg = DPLL(pipe);
8905                 int dpll;
8906
8907                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8908
8909                 assert_panel_unlocked(dev_priv, pipe);
8910
8911                 dpll = I915_READ(dpll_reg);
8912                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8913                 I915_WRITE(dpll_reg, dpll);
8914                 intel_wait_for_vblank(dev, pipe);
8915                 dpll = I915_READ(dpll_reg);
8916                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8917                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8918         }
8919
8920 }
8921
8922 void intel_mark_busy(struct drm_device *dev)
8923 {
8924         struct drm_i915_private *dev_priv = dev->dev_private;
8925
8926         if (dev_priv->mm.busy)
8927                 return;
8928
8929         intel_runtime_pm_get(dev_priv);
8930         i915_update_gfx_val(dev_priv);
8931         dev_priv->mm.busy = true;
8932 }
8933
8934 void intel_mark_idle(struct drm_device *dev)
8935 {
8936         struct drm_i915_private *dev_priv = dev->dev_private;
8937         struct drm_crtc *crtc;
8938
8939         if (!dev_priv->mm.busy)
8940                 return;
8941
8942         dev_priv->mm.busy = false;
8943
8944         if (!i915.powersave)
8945                 goto out;
8946
8947         for_each_crtc(dev, crtc) {
8948                 if (!crtc->primary->fb)
8949                         continue;
8950
8951                 intel_decrease_pllclock(crtc);
8952         }
8953
8954         if (INTEL_INFO(dev)->gen >= 6)
8955                 gen6_rps_idle(dev->dev_private);
8956
8957 out:
8958         intel_runtime_pm_put(dev_priv);
8959 }
8960
8961 static void intel_crtc_destroy(struct drm_crtc *crtc)
8962 {
8963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8964         struct drm_device *dev = crtc->dev;
8965         struct intel_unpin_work *work;
8966
8967         spin_lock_irq(&dev->event_lock);
8968         work = intel_crtc->unpin_work;
8969         intel_crtc->unpin_work = NULL;
8970         spin_unlock_irq(&dev->event_lock);
8971
8972         if (work) {
8973                 cancel_work_sync(&work->work);
8974                 kfree(work);
8975         }
8976
8977         drm_crtc_cleanup(crtc);
8978
8979         kfree(intel_crtc);
8980 }
8981
8982 static void intel_unpin_work_fn(struct work_struct *__work)
8983 {
8984         struct intel_unpin_work *work =
8985                 container_of(__work, struct intel_unpin_work, work);
8986         struct drm_device *dev = work->crtc->dev;
8987         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8988
8989         mutex_lock(&dev->struct_mutex);
8990         intel_unpin_fb_obj(work->old_fb_obj);
8991         drm_gem_object_unreference(&work->pending_flip_obj->base);
8992         drm_gem_object_unreference(&work->old_fb_obj->base);
8993
8994         intel_update_fbc(dev);
8995         mutex_unlock(&dev->struct_mutex);
8996
8997         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8998
8999         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9000         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9001
9002         kfree(work);
9003 }
9004
9005 static void do_intel_finish_page_flip(struct drm_device *dev,
9006                                       struct drm_crtc *crtc)
9007 {
9008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9009         struct intel_unpin_work *work;
9010         unsigned long flags;
9011
9012         /* Ignore early vblank irqs */
9013         if (intel_crtc == NULL)
9014                 return;
9015
9016         /*
9017          * This is called both by irq handlers and the reset code (to complete
9018          * lost pageflips) so needs the full irqsave spinlocks.
9019          */
9020         spin_lock_irqsave(&dev->event_lock, flags);
9021         work = intel_crtc->unpin_work;
9022
9023         /* Ensure we don't miss a work->pending update ... */
9024         smp_rmb();
9025
9026         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9027                 spin_unlock_irqrestore(&dev->event_lock, flags);
9028                 return;
9029         }
9030
9031         page_flip_completed(intel_crtc);
9032
9033         spin_unlock_irqrestore(&dev->event_lock, flags);
9034 }
9035
9036 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9037 {
9038         struct drm_i915_private *dev_priv = dev->dev_private;
9039         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9040
9041         do_intel_finish_page_flip(dev, crtc);
9042 }
9043
9044 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9045 {
9046         struct drm_i915_private *dev_priv = dev->dev_private;
9047         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9048
9049         do_intel_finish_page_flip(dev, crtc);
9050 }
9051
9052 /* Is 'a' after or equal to 'b'? */
9053 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9054 {
9055         return !((a - b) & 0x80000000);
9056 }
9057
9058 static bool page_flip_finished(struct intel_crtc *crtc)
9059 {
9060         struct drm_device *dev = crtc->base.dev;
9061         struct drm_i915_private *dev_priv = dev->dev_private;
9062
9063         /*
9064          * The relevant registers doen't exist on pre-ctg.
9065          * As the flip done interrupt doesn't trigger for mmio
9066          * flips on gmch platforms, a flip count check isn't
9067          * really needed there. But since ctg has the registers,
9068          * include it in the check anyway.
9069          */
9070         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9071                 return true;
9072
9073         /*
9074          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9075          * used the same base address. In that case the mmio flip might
9076          * have completed, but the CS hasn't even executed the flip yet.
9077          *
9078          * A flip count check isn't enough as the CS might have updated
9079          * the base address just after start of vblank, but before we
9080          * managed to process the interrupt. This means we'd complete the
9081          * CS flip too soon.
9082          *
9083          * Combining both checks should get us a good enough result. It may
9084          * still happen that the CS flip has been executed, but has not
9085          * yet actually completed. But in case the base address is the same
9086          * anyway, we don't really care.
9087          */
9088         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9089                 crtc->unpin_work->gtt_offset &&
9090                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9091                                     crtc->unpin_work->flip_count);
9092 }
9093
9094 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9095 {
9096         struct drm_i915_private *dev_priv = dev->dev_private;
9097         struct intel_crtc *intel_crtc =
9098                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9099         unsigned long flags;
9100
9101
9102         /*
9103          * This is called both by irq handlers and the reset code (to complete
9104          * lost pageflips) so needs the full irqsave spinlocks.
9105          *
9106          * NB: An MMIO update of the plane base pointer will also
9107          * generate a page-flip completion irq, i.e. every modeset
9108          * is also accompanied by a spurious intel_prepare_page_flip().
9109          */
9110         spin_lock_irqsave(&dev->event_lock, flags);
9111         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9112                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9113         spin_unlock_irqrestore(&dev->event_lock, flags);
9114 }
9115
9116 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9117 {
9118         /* Ensure that the work item is consistent when activating it ... */
9119         smp_wmb();
9120         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9121         /* and that it is marked active as soon as the irq could fire. */
9122         smp_wmb();
9123 }
9124
9125 static int intel_gen2_queue_flip(struct drm_device *dev,
9126                                  struct drm_crtc *crtc,
9127                                  struct drm_framebuffer *fb,
9128                                  struct drm_i915_gem_object *obj,
9129                                  struct intel_engine_cs *ring,
9130                                  uint32_t flags)
9131 {
9132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9133         u32 flip_mask;
9134         int ret;
9135
9136         ret = intel_ring_begin(ring, 6);
9137         if (ret)
9138                 return ret;
9139
9140         /* Can't queue multiple flips, so wait for the previous
9141          * one to finish before executing the next.
9142          */
9143         if (intel_crtc->plane)
9144                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9145         else
9146                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9147         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9148         intel_ring_emit(ring, MI_NOOP);
9149         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9150                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9151         intel_ring_emit(ring, fb->pitches[0]);
9152         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9153         intel_ring_emit(ring, 0); /* aux display base address, unused */
9154
9155         intel_mark_page_flip_active(intel_crtc);
9156         __intel_ring_advance(ring);
9157         return 0;
9158 }
9159
9160 static int intel_gen3_queue_flip(struct drm_device *dev,
9161                                  struct drm_crtc *crtc,
9162                                  struct drm_framebuffer *fb,
9163                                  struct drm_i915_gem_object *obj,
9164                                  struct intel_engine_cs *ring,
9165                                  uint32_t flags)
9166 {
9167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9168         u32 flip_mask;
9169         int ret;
9170
9171         ret = intel_ring_begin(ring, 6);
9172         if (ret)
9173                 return ret;
9174
9175         if (intel_crtc->plane)
9176                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9177         else
9178                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9179         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9180         intel_ring_emit(ring, MI_NOOP);
9181         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9182                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9183         intel_ring_emit(ring, fb->pitches[0]);
9184         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9185         intel_ring_emit(ring, MI_NOOP);
9186
9187         intel_mark_page_flip_active(intel_crtc);
9188         __intel_ring_advance(ring);
9189         return 0;
9190 }
9191
9192 static int intel_gen4_queue_flip(struct drm_device *dev,
9193                                  struct drm_crtc *crtc,
9194                                  struct drm_framebuffer *fb,
9195                                  struct drm_i915_gem_object *obj,
9196                                  struct intel_engine_cs *ring,
9197                                  uint32_t flags)
9198 {
9199         struct drm_i915_private *dev_priv = dev->dev_private;
9200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9201         uint32_t pf, pipesrc;
9202         int ret;
9203
9204         ret = intel_ring_begin(ring, 4);
9205         if (ret)
9206                 return ret;
9207
9208         /* i965+ uses the linear or tiled offsets from the
9209          * Display Registers (which do not change across a page-flip)
9210          * so we need only reprogram the base address.
9211          */
9212         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9213                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9214         intel_ring_emit(ring, fb->pitches[0]);
9215         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9216                         obj->tiling_mode);
9217
9218         /* XXX Enabling the panel-fitter across page-flip is so far
9219          * untested on non-native modes, so ignore it for now.
9220          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9221          */
9222         pf = 0;
9223         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9224         intel_ring_emit(ring, pf | pipesrc);
9225
9226         intel_mark_page_flip_active(intel_crtc);
9227         __intel_ring_advance(ring);
9228         return 0;
9229 }
9230
9231 static int intel_gen6_queue_flip(struct drm_device *dev,
9232                                  struct drm_crtc *crtc,
9233                                  struct drm_framebuffer *fb,
9234                                  struct drm_i915_gem_object *obj,
9235                                  struct intel_engine_cs *ring,
9236                                  uint32_t flags)
9237 {
9238         struct drm_i915_private *dev_priv = dev->dev_private;
9239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9240         uint32_t pf, pipesrc;
9241         int ret;
9242
9243         ret = intel_ring_begin(ring, 4);
9244         if (ret)
9245                 return ret;
9246
9247         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9248                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9249         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9250         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9251
9252         /* Contrary to the suggestions in the documentation,
9253          * "Enable Panel Fitter" does not seem to be required when page
9254          * flipping with a non-native mode, and worse causes a normal
9255          * modeset to fail.
9256          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9257          */
9258         pf = 0;
9259         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9260         intel_ring_emit(ring, pf | pipesrc);
9261
9262         intel_mark_page_flip_active(intel_crtc);
9263         __intel_ring_advance(ring);
9264         return 0;
9265 }
9266
9267 static int intel_gen7_queue_flip(struct drm_device *dev,
9268                                  struct drm_crtc *crtc,
9269                                  struct drm_framebuffer *fb,
9270                                  struct drm_i915_gem_object *obj,
9271                                  struct intel_engine_cs *ring,
9272                                  uint32_t flags)
9273 {
9274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9275         uint32_t plane_bit = 0;
9276         int len, ret;
9277
9278         switch (intel_crtc->plane) {
9279         case PLANE_A:
9280                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9281                 break;
9282         case PLANE_B:
9283                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9284                 break;
9285         case PLANE_C:
9286                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9287                 break;
9288         default:
9289                 WARN_ONCE(1, "unknown plane in flip command\n");
9290                 return -ENODEV;
9291         }
9292
9293         len = 4;
9294         if (ring->id == RCS) {
9295                 len += 6;
9296                 /*
9297                  * On Gen 8, SRM is now taking an extra dword to accommodate
9298                  * 48bits addresses, and we need a NOOP for the batch size to
9299                  * stay even.
9300                  */
9301                 if (IS_GEN8(dev))
9302                         len += 2;
9303         }
9304
9305         /*
9306          * BSpec MI_DISPLAY_FLIP for IVB:
9307          * "The full packet must be contained within the same cache line."
9308          *
9309          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9310          * cacheline, if we ever start emitting more commands before
9311          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9312          * then do the cacheline alignment, and finally emit the
9313          * MI_DISPLAY_FLIP.
9314          */
9315         ret = intel_ring_cacheline_align(ring);
9316         if (ret)
9317                 return ret;
9318
9319         ret = intel_ring_begin(ring, len);
9320         if (ret)
9321                 return ret;
9322
9323         /* Unmask the flip-done completion message. Note that the bspec says that
9324          * we should do this for both the BCS and RCS, and that we must not unmask
9325          * more than one flip event at any time (or ensure that one flip message
9326          * can be sent by waiting for flip-done prior to queueing new flips).
9327          * Experimentation says that BCS works despite DERRMR masking all
9328          * flip-done completion events and that unmasking all planes at once
9329          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9330          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9331          */
9332         if (ring->id == RCS) {
9333                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9334                 intel_ring_emit(ring, DERRMR);
9335                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9336                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9337                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9338                 if (IS_GEN8(dev))
9339                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9340                                               MI_SRM_LRM_GLOBAL_GTT);
9341                 else
9342                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9343                                               MI_SRM_LRM_GLOBAL_GTT);
9344                 intel_ring_emit(ring, DERRMR);
9345                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9346                 if (IS_GEN8(dev)) {
9347                         intel_ring_emit(ring, 0);
9348                         intel_ring_emit(ring, MI_NOOP);
9349                 }
9350         }
9351
9352         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9353         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9354         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9355         intel_ring_emit(ring, (MI_NOOP));
9356
9357         intel_mark_page_flip_active(intel_crtc);
9358         __intel_ring_advance(ring);
9359         return 0;
9360 }
9361
9362 static bool use_mmio_flip(struct intel_engine_cs *ring,
9363                           struct drm_i915_gem_object *obj)
9364 {
9365         /*
9366          * This is not being used for older platforms, because
9367          * non-availability of flip done interrupt forces us to use
9368          * CS flips. Older platforms derive flip done using some clever
9369          * tricks involving the flip_pending status bits and vblank irqs.
9370          * So using MMIO flips there would disrupt this mechanism.
9371          */
9372
9373         if (ring == NULL)
9374                 return true;
9375
9376         if (INTEL_INFO(ring->dev)->gen < 5)
9377                 return false;
9378
9379         if (i915.use_mmio_flip < 0)
9380                 return false;
9381         else if (i915.use_mmio_flip > 0)
9382                 return true;
9383         else if (i915.enable_execlists)
9384                 return true;
9385         else
9386                 return ring != obj->ring;
9387 }
9388
9389 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9390 {
9391         struct drm_device *dev = intel_crtc->base.dev;
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         struct intel_framebuffer *intel_fb =
9394                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9395         struct drm_i915_gem_object *obj = intel_fb->obj;
9396         bool atomic_update;
9397         u32 start_vbl_count;
9398         u32 dspcntr;
9399         u32 reg;
9400
9401         intel_mark_page_flip_active(intel_crtc);
9402
9403         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9404
9405         reg = DSPCNTR(intel_crtc->plane);
9406         dspcntr = I915_READ(reg);
9407
9408         if (obj->tiling_mode != I915_TILING_NONE)
9409                 dspcntr |= DISPPLANE_TILED;
9410         else
9411                 dspcntr &= ~DISPPLANE_TILED;
9412
9413         I915_WRITE(reg, dspcntr);
9414
9415         I915_WRITE(DSPSURF(intel_crtc->plane),
9416                    intel_crtc->unpin_work->gtt_offset);
9417         POSTING_READ(DSPSURF(intel_crtc->plane));
9418
9419         if (atomic_update)
9420                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9421 }
9422
9423 static void intel_mmio_flip_work_func(struct work_struct *work)
9424 {
9425         struct intel_crtc *intel_crtc =
9426                 container_of(work, struct intel_crtc, mmio_flip.work);
9427         struct intel_engine_cs *ring;
9428         uint32_t seqno;
9429
9430         seqno = intel_crtc->mmio_flip.seqno;
9431         ring = intel_crtc->mmio_flip.ring;
9432
9433         if (seqno)
9434                 WARN_ON(__i915_wait_seqno(ring, seqno,
9435                                           intel_crtc->reset_counter,
9436                                           false, NULL, NULL) != 0);
9437
9438         intel_do_mmio_flip(intel_crtc);
9439 }
9440
9441 static int intel_queue_mmio_flip(struct drm_device *dev,
9442                                  struct drm_crtc *crtc,
9443                                  struct drm_framebuffer *fb,
9444                                  struct drm_i915_gem_object *obj,
9445                                  struct intel_engine_cs *ring,
9446                                  uint32_t flags)
9447 {
9448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9449
9450         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9451         intel_crtc->mmio_flip.ring = obj->ring;
9452
9453         schedule_work(&intel_crtc->mmio_flip.work);
9454
9455         return 0;
9456 }
9457
9458 static int intel_default_queue_flip(struct drm_device *dev,
9459                                     struct drm_crtc *crtc,
9460                                     struct drm_framebuffer *fb,
9461                                     struct drm_i915_gem_object *obj,
9462                                     struct intel_engine_cs *ring,
9463                                     uint32_t flags)
9464 {
9465         return -ENODEV;
9466 }
9467
9468 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9469                                          struct drm_crtc *crtc)
9470 {
9471         struct drm_i915_private *dev_priv = dev->dev_private;
9472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9473         struct intel_unpin_work *work = intel_crtc->unpin_work;
9474         u32 addr;
9475
9476         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9477                 return true;
9478
9479         if (!work->enable_stall_check)
9480                 return false;
9481
9482         if (work->flip_ready_vblank == 0) {
9483                 if (work->flip_queued_ring &&
9484                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9485                                        work->flip_queued_seqno))
9486                         return false;
9487
9488                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9489         }
9490
9491         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9492                 return false;
9493
9494         /* Potential stall - if we see that the flip has happened,
9495          * assume a missed interrupt. */
9496         if (INTEL_INFO(dev)->gen >= 4)
9497                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9498         else
9499                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9500
9501         /* There is a potential issue here with a false positive after a flip
9502          * to the same address. We could address this by checking for a
9503          * non-incrementing frame counter.
9504          */
9505         return addr == work->gtt_offset;
9506 }
9507
9508 void intel_check_page_flip(struct drm_device *dev, int pipe)
9509 {
9510         struct drm_i915_private *dev_priv = dev->dev_private;
9511         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9513
9514         WARN_ON(!in_irq());
9515
9516         if (crtc == NULL)
9517                 return;
9518
9519         spin_lock(&dev->event_lock);
9520         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9521                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9522                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9523                 page_flip_completed(intel_crtc);
9524         }
9525         spin_unlock(&dev->event_lock);
9526 }
9527
9528 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9529                                 struct drm_framebuffer *fb,
9530                                 struct drm_pending_vblank_event *event,
9531                                 uint32_t page_flip_flags)
9532 {
9533         struct drm_device *dev = crtc->dev;
9534         struct drm_i915_private *dev_priv = dev->dev_private;
9535         struct drm_framebuffer *old_fb = crtc->primary->fb;
9536         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9538         enum pipe pipe = intel_crtc->pipe;
9539         struct intel_unpin_work *work;
9540         struct intel_engine_cs *ring;
9541         int ret;
9542
9543         /*
9544          * drm_mode_page_flip_ioctl() should already catch this, but double
9545          * check to be safe.  In the future we may enable pageflipping from
9546          * a disabled primary plane.
9547          */
9548         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9549                 return -EBUSY;
9550
9551         /* Can't change pixel format via MI display flips. */
9552         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9553                 return -EINVAL;
9554
9555         /*
9556          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9557          * Note that pitch changes could also affect these register.
9558          */
9559         if (INTEL_INFO(dev)->gen > 3 &&
9560             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9561              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9562                 return -EINVAL;
9563
9564         if (i915_terminally_wedged(&dev_priv->gpu_error))
9565                 goto out_hang;
9566
9567         work = kzalloc(sizeof(*work), GFP_KERNEL);
9568         if (work == NULL)
9569                 return -ENOMEM;
9570
9571         work->event = event;
9572         work->crtc = crtc;
9573         work->old_fb_obj = intel_fb_obj(old_fb);
9574         INIT_WORK(&work->work, intel_unpin_work_fn);
9575
9576         ret = drm_crtc_vblank_get(crtc);
9577         if (ret)
9578                 goto free_work;
9579
9580         /* We borrow the event spin lock for protecting unpin_work */
9581         spin_lock_irq(&dev->event_lock);
9582         if (intel_crtc->unpin_work) {
9583                 /* Before declaring the flip queue wedged, check if
9584                  * the hardware completed the operation behind our backs.
9585                  */
9586                 if (__intel_pageflip_stall_check(dev, crtc)) {
9587                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9588                         page_flip_completed(intel_crtc);
9589                 } else {
9590                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9591                         spin_unlock_irq(&dev->event_lock);
9592
9593                         drm_crtc_vblank_put(crtc);
9594                         kfree(work);
9595                         return -EBUSY;
9596                 }
9597         }
9598         intel_crtc->unpin_work = work;
9599         spin_unlock_irq(&dev->event_lock);
9600
9601         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9602                 flush_workqueue(dev_priv->wq);
9603
9604         ret = i915_mutex_lock_interruptible(dev);
9605         if (ret)
9606                 goto cleanup;
9607
9608         /* Reference the objects for the scheduled work. */
9609         drm_gem_object_reference(&work->old_fb_obj->base);
9610         drm_gem_object_reference(&obj->base);
9611
9612         crtc->primary->fb = fb;
9613
9614         work->pending_flip_obj = obj;
9615
9616         atomic_inc(&intel_crtc->unpin_work_count);
9617         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9618
9619         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9620                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9621
9622         if (IS_VALLEYVIEW(dev)) {
9623                 ring = &dev_priv->ring[BCS];
9624                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9625                         /* vlv: DISPLAY_FLIP fails to change tiling */
9626                         ring = NULL;
9627         } else if (IS_IVYBRIDGE(dev)) {
9628                 ring = &dev_priv->ring[BCS];
9629         } else if (INTEL_INFO(dev)->gen >= 7) {
9630                 ring = obj->ring;
9631                 if (ring == NULL || ring->id != RCS)
9632                         ring = &dev_priv->ring[BCS];
9633         } else {
9634                 ring = &dev_priv->ring[RCS];
9635         }
9636
9637         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9638         if (ret)
9639                 goto cleanup_pending;
9640
9641         work->gtt_offset =
9642                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9643
9644         if (use_mmio_flip(ring, obj)) {
9645                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9646                                             page_flip_flags);
9647                 if (ret)
9648                         goto cleanup_unpin;
9649
9650                 work->flip_queued_seqno = obj->last_write_seqno;
9651                 work->flip_queued_ring = obj->ring;
9652         } else {
9653                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9654                                                    page_flip_flags);
9655                 if (ret)
9656                         goto cleanup_unpin;
9657
9658                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9659                 work->flip_queued_ring = ring;
9660         }
9661
9662         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9663         work->enable_stall_check = true;
9664
9665         i915_gem_track_fb(work->old_fb_obj, obj,
9666                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9667
9668         intel_disable_fbc(dev);
9669         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9670         mutex_unlock(&dev->struct_mutex);
9671
9672         trace_i915_flip_request(intel_crtc->plane, obj);
9673
9674         return 0;
9675
9676 cleanup_unpin:
9677         intel_unpin_fb_obj(obj);
9678 cleanup_pending:
9679         atomic_dec(&intel_crtc->unpin_work_count);
9680         crtc->primary->fb = old_fb;
9681         drm_gem_object_unreference(&work->old_fb_obj->base);
9682         drm_gem_object_unreference(&obj->base);
9683         mutex_unlock(&dev->struct_mutex);
9684
9685 cleanup:
9686         spin_lock_irq(&dev->event_lock);
9687         intel_crtc->unpin_work = NULL;
9688         spin_unlock_irq(&dev->event_lock);
9689
9690         drm_crtc_vblank_put(crtc);
9691 free_work:
9692         kfree(work);
9693
9694         if (ret == -EIO) {
9695 out_hang:
9696                 intel_crtc_wait_for_pending_flips(crtc);
9697                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9698                 if (ret == 0 && event) {
9699                         spin_lock_irq(&dev->event_lock);
9700                         drm_send_vblank_event(dev, pipe, event);
9701                         spin_unlock_irq(&dev->event_lock);
9702                 }
9703         }
9704         return ret;
9705 }
9706
9707 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9708         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9709         .load_lut = intel_crtc_load_lut,
9710 };
9711
9712 /**
9713  * intel_modeset_update_staged_output_state
9714  *
9715  * Updates the staged output configuration state, e.g. after we've read out the
9716  * current hw state.
9717  */
9718 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9719 {
9720         struct intel_crtc *crtc;
9721         struct intel_encoder *encoder;
9722         struct intel_connector *connector;
9723
9724         list_for_each_entry(connector, &dev->mode_config.connector_list,
9725                             base.head) {
9726                 connector->new_encoder =
9727                         to_intel_encoder(connector->base.encoder);
9728         }
9729
9730         for_each_intel_encoder(dev, encoder) {
9731                 encoder->new_crtc =
9732                         to_intel_crtc(encoder->base.crtc);
9733         }
9734
9735         for_each_intel_crtc(dev, crtc) {
9736                 crtc->new_enabled = crtc->base.enabled;
9737
9738                 if (crtc->new_enabled)
9739                         crtc->new_config = &crtc->config;
9740                 else
9741                         crtc->new_config = NULL;
9742         }
9743 }
9744
9745 /**
9746  * intel_modeset_commit_output_state
9747  *
9748  * This function copies the stage display pipe configuration to the real one.
9749  */
9750 static void intel_modeset_commit_output_state(struct drm_device *dev)
9751 {
9752         struct intel_crtc *crtc;
9753         struct intel_encoder *encoder;
9754         struct intel_connector *connector;
9755
9756         list_for_each_entry(connector, &dev->mode_config.connector_list,
9757                             base.head) {
9758                 connector->base.encoder = &connector->new_encoder->base;
9759         }
9760
9761         for_each_intel_encoder(dev, encoder) {
9762                 encoder->base.crtc = &encoder->new_crtc->base;
9763         }
9764
9765         for_each_intel_crtc(dev, crtc) {
9766                 crtc->base.enabled = crtc->new_enabled;
9767         }
9768 }
9769
9770 static void
9771 connected_sink_compute_bpp(struct intel_connector *connector,
9772                            struct intel_crtc_config *pipe_config)
9773 {
9774         int bpp = pipe_config->pipe_bpp;
9775
9776         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9777                 connector->base.base.id,
9778                 connector->base.name);
9779
9780         /* Don't use an invalid EDID bpc value */
9781         if (connector->base.display_info.bpc &&
9782             connector->base.display_info.bpc * 3 < bpp) {
9783                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9784                               bpp, connector->base.display_info.bpc*3);
9785                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9786         }
9787
9788         /* Clamp bpp to 8 on screens without EDID 1.4 */
9789         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9790                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9791                               bpp);
9792                 pipe_config->pipe_bpp = 24;
9793         }
9794 }
9795
9796 static int
9797 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9798                           struct drm_framebuffer *fb,
9799                           struct intel_crtc_config *pipe_config)
9800 {
9801         struct drm_device *dev = crtc->base.dev;
9802         struct intel_connector *connector;
9803         int bpp;
9804
9805         switch (fb->pixel_format) {
9806         case DRM_FORMAT_C8:
9807                 bpp = 8*3; /* since we go through a colormap */
9808                 break;
9809         case DRM_FORMAT_XRGB1555:
9810         case DRM_FORMAT_ARGB1555:
9811                 /* checked in intel_framebuffer_init already */
9812                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9813                         return -EINVAL;
9814         case DRM_FORMAT_RGB565:
9815                 bpp = 6*3; /* min is 18bpp */
9816                 break;
9817         case DRM_FORMAT_XBGR8888:
9818         case DRM_FORMAT_ABGR8888:
9819                 /* checked in intel_framebuffer_init already */
9820                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9821                         return -EINVAL;
9822         case DRM_FORMAT_XRGB8888:
9823         case DRM_FORMAT_ARGB8888:
9824                 bpp = 8*3;
9825                 break;
9826         case DRM_FORMAT_XRGB2101010:
9827         case DRM_FORMAT_ARGB2101010:
9828         case DRM_FORMAT_XBGR2101010:
9829         case DRM_FORMAT_ABGR2101010:
9830                 /* checked in intel_framebuffer_init already */
9831                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9832                         return -EINVAL;
9833                 bpp = 10*3;
9834                 break;
9835         /* TODO: gen4+ supports 16 bpc floating point, too. */
9836         default:
9837                 DRM_DEBUG_KMS("unsupported depth\n");
9838                 return -EINVAL;
9839         }
9840
9841         pipe_config->pipe_bpp = bpp;
9842
9843         /* Clamp display bpp to EDID value */
9844         list_for_each_entry(connector, &dev->mode_config.connector_list,
9845                             base.head) {
9846                 if (!connector->new_encoder ||
9847                     connector->new_encoder->new_crtc != crtc)
9848                         continue;
9849
9850                 connected_sink_compute_bpp(connector, pipe_config);
9851         }
9852
9853         return bpp;
9854 }
9855
9856 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9857 {
9858         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9859                         "type: 0x%x flags: 0x%x\n",
9860                 mode->crtc_clock,
9861                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9862                 mode->crtc_hsync_end, mode->crtc_htotal,
9863                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9864                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9865 }
9866
9867 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9868                                    struct intel_crtc_config *pipe_config,
9869                                    const char *context)
9870 {
9871         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9872                       context, pipe_name(crtc->pipe));
9873
9874         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9875         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9876                       pipe_config->pipe_bpp, pipe_config->dither);
9877         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9878                       pipe_config->has_pch_encoder,
9879                       pipe_config->fdi_lanes,
9880                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9881                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9882                       pipe_config->fdi_m_n.tu);
9883         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9884                       pipe_config->has_dp_encoder,
9885                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9886                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9887                       pipe_config->dp_m_n.tu);
9888
9889         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9890                       pipe_config->has_dp_encoder,
9891                       pipe_config->dp_m2_n2.gmch_m,
9892                       pipe_config->dp_m2_n2.gmch_n,
9893                       pipe_config->dp_m2_n2.link_m,
9894                       pipe_config->dp_m2_n2.link_n,
9895                       pipe_config->dp_m2_n2.tu);
9896
9897         DRM_DEBUG_KMS("requested mode:\n");
9898         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9899         DRM_DEBUG_KMS("adjusted mode:\n");
9900         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9901         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9902         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9903         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9904                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9905         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9906                       pipe_config->gmch_pfit.control,
9907                       pipe_config->gmch_pfit.pgm_ratios,
9908                       pipe_config->gmch_pfit.lvds_border_bits);
9909         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9910                       pipe_config->pch_pfit.pos,
9911                       pipe_config->pch_pfit.size,
9912                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9913         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9914         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9915 }
9916
9917 static bool encoders_cloneable(const struct intel_encoder *a,
9918                                const struct intel_encoder *b)
9919 {
9920         /* masks could be asymmetric, so check both ways */
9921         return a == b || (a->cloneable & (1 << b->type) &&
9922                           b->cloneable & (1 << a->type));
9923 }
9924
9925 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9926                                          struct intel_encoder *encoder)
9927 {
9928         struct drm_device *dev = crtc->base.dev;
9929         struct intel_encoder *source_encoder;
9930
9931         for_each_intel_encoder(dev, source_encoder) {
9932                 if (source_encoder->new_crtc != crtc)
9933                         continue;
9934
9935                 if (!encoders_cloneable(encoder, source_encoder))
9936                         return false;
9937         }
9938
9939         return true;
9940 }
9941
9942 static bool check_encoder_cloning(struct intel_crtc *crtc)
9943 {
9944         struct drm_device *dev = crtc->base.dev;
9945         struct intel_encoder *encoder;
9946
9947         for_each_intel_encoder(dev, encoder) {
9948                 if (encoder->new_crtc != crtc)
9949                         continue;
9950
9951                 if (!check_single_encoder_cloning(crtc, encoder))
9952                         return false;
9953         }
9954
9955         return true;
9956 }
9957
9958 static struct intel_crtc_config *
9959 intel_modeset_pipe_config(struct drm_crtc *crtc,
9960                           struct drm_framebuffer *fb,
9961                           struct drm_display_mode *mode)
9962 {
9963         struct drm_device *dev = crtc->dev;
9964         struct intel_encoder *encoder;
9965         struct intel_crtc_config *pipe_config;
9966         int plane_bpp, ret = -EINVAL;
9967         bool retry = true;
9968
9969         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9970                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9971                 return ERR_PTR(-EINVAL);
9972         }
9973
9974         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9975         if (!pipe_config)
9976                 return ERR_PTR(-ENOMEM);
9977
9978         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9979         drm_mode_copy(&pipe_config->requested_mode, mode);
9980
9981         pipe_config->cpu_transcoder =
9982                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9983         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9984
9985         /*
9986          * Sanitize sync polarity flags based on requested ones. If neither
9987          * positive or negative polarity is requested, treat this as meaning
9988          * negative polarity.
9989          */
9990         if (!(pipe_config->adjusted_mode.flags &
9991               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9992                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9993
9994         if (!(pipe_config->adjusted_mode.flags &
9995               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9996                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9997
9998         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9999          * plane pixel format and any sink constraints into account. Returns the
10000          * source plane bpp so that dithering can be selected on mismatches
10001          * after encoders and crtc also have had their say. */
10002         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10003                                               fb, pipe_config);
10004         if (plane_bpp < 0)
10005                 goto fail;
10006
10007         /*
10008          * Determine the real pipe dimensions. Note that stereo modes can
10009          * increase the actual pipe size due to the frame doubling and
10010          * insertion of additional space for blanks between the frame. This
10011          * is stored in the crtc timings. We use the requested mode to do this
10012          * computation to clearly distinguish it from the adjusted mode, which
10013          * can be changed by the connectors in the below retry loop.
10014          */
10015         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10016         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10017         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10018
10019 encoder_retry:
10020         /* Ensure the port clock defaults are reset when retrying. */
10021         pipe_config->port_clock = 0;
10022         pipe_config->pixel_multiplier = 1;
10023
10024         /* Fill in default crtc timings, allow encoders to overwrite them. */
10025         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10026
10027         /* Pass our mode to the connectors and the CRTC to give them a chance to
10028          * adjust it according to limitations or connector properties, and also
10029          * a chance to reject the mode entirely.
10030          */
10031         for_each_intel_encoder(dev, encoder) {
10032
10033                 if (&encoder->new_crtc->base != crtc)
10034                         continue;
10035
10036                 if (!(encoder->compute_config(encoder, pipe_config))) {
10037                         DRM_DEBUG_KMS("Encoder config failure\n");
10038                         goto fail;
10039                 }
10040         }
10041
10042         /* Set default port clock if not overwritten by the encoder. Needs to be
10043          * done afterwards in case the encoder adjusts the mode. */
10044         if (!pipe_config->port_clock)
10045                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10046                         * pipe_config->pixel_multiplier;
10047
10048         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10049         if (ret < 0) {
10050                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10051                 goto fail;
10052         }
10053
10054         if (ret == RETRY) {
10055                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10056                         ret = -EINVAL;
10057                         goto fail;
10058                 }
10059
10060                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10061                 retry = false;
10062                 goto encoder_retry;
10063         }
10064
10065         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10066         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10067                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10068
10069         return pipe_config;
10070 fail:
10071         kfree(pipe_config);
10072         return ERR_PTR(ret);
10073 }
10074
10075 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10076  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10077 static void
10078 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10079                              unsigned *prepare_pipes, unsigned *disable_pipes)
10080 {
10081         struct intel_crtc *intel_crtc;
10082         struct drm_device *dev = crtc->dev;
10083         struct intel_encoder *encoder;
10084         struct intel_connector *connector;
10085         struct drm_crtc *tmp_crtc;
10086
10087         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10088
10089         /* Check which crtcs have changed outputs connected to them, these need
10090          * to be part of the prepare_pipes mask. We don't (yet) support global
10091          * modeset across multiple crtcs, so modeset_pipes will only have one
10092          * bit set at most. */
10093         list_for_each_entry(connector, &dev->mode_config.connector_list,
10094                             base.head) {
10095                 if (connector->base.encoder == &connector->new_encoder->base)
10096                         continue;
10097
10098                 if (connector->base.encoder) {
10099                         tmp_crtc = connector->base.encoder->crtc;
10100
10101                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10102                 }
10103
10104                 if (connector->new_encoder)
10105                         *prepare_pipes |=
10106                                 1 << connector->new_encoder->new_crtc->pipe;
10107         }
10108
10109         for_each_intel_encoder(dev, encoder) {
10110                 if (encoder->base.crtc == &encoder->new_crtc->base)
10111                         continue;
10112
10113                 if (encoder->base.crtc) {
10114                         tmp_crtc = encoder->base.crtc;
10115
10116                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10117                 }
10118
10119                 if (encoder->new_crtc)
10120                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10121         }
10122
10123         /* Check for pipes that will be enabled/disabled ... */
10124         for_each_intel_crtc(dev, intel_crtc) {
10125                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10126                         continue;
10127
10128                 if (!intel_crtc->new_enabled)
10129                         *disable_pipes |= 1 << intel_crtc->pipe;
10130                 else
10131                         *prepare_pipes |= 1 << intel_crtc->pipe;
10132         }
10133
10134
10135         /* set_mode is also used to update properties on life display pipes. */
10136         intel_crtc = to_intel_crtc(crtc);
10137         if (intel_crtc->new_enabled)
10138                 *prepare_pipes |= 1 << intel_crtc->pipe;
10139
10140         /*
10141          * For simplicity do a full modeset on any pipe where the output routing
10142          * changed. We could be more clever, but that would require us to be
10143          * more careful with calling the relevant encoder->mode_set functions.
10144          */
10145         if (*prepare_pipes)
10146                 *modeset_pipes = *prepare_pipes;
10147
10148         /* ... and mask these out. */
10149         *modeset_pipes &= ~(*disable_pipes);
10150         *prepare_pipes &= ~(*disable_pipes);
10151
10152         /*
10153          * HACK: We don't (yet) fully support global modesets. intel_set_config
10154          * obies this rule, but the modeset restore mode of
10155          * intel_modeset_setup_hw_state does not.
10156          */
10157         *modeset_pipes &= 1 << intel_crtc->pipe;
10158         *prepare_pipes &= 1 << intel_crtc->pipe;
10159
10160         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10161                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10162 }
10163
10164 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10165 {
10166         struct drm_encoder *encoder;
10167         struct drm_device *dev = crtc->dev;
10168
10169         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10170                 if (encoder->crtc == crtc)
10171                         return true;
10172
10173         return false;
10174 }
10175
10176 static void
10177 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10178 {
10179         struct drm_i915_private *dev_priv = dev->dev_private;
10180         struct intel_encoder *intel_encoder;
10181         struct intel_crtc *intel_crtc;
10182         struct drm_connector *connector;
10183
10184         intel_shared_dpll_commit(dev_priv);
10185
10186         for_each_intel_encoder(dev, intel_encoder) {
10187                 if (!intel_encoder->base.crtc)
10188                         continue;
10189
10190                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10191
10192                 if (prepare_pipes & (1 << intel_crtc->pipe))
10193                         intel_encoder->connectors_active = false;
10194         }
10195
10196         intel_modeset_commit_output_state(dev);
10197
10198         /* Double check state. */
10199         for_each_intel_crtc(dev, intel_crtc) {
10200                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10201                 WARN_ON(intel_crtc->new_config &&
10202                         intel_crtc->new_config != &intel_crtc->config);
10203                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10204         }
10205
10206         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10207                 if (!connector->encoder || !connector->encoder->crtc)
10208                         continue;
10209
10210                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10211
10212                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10213                         struct drm_property *dpms_property =
10214                                 dev->mode_config.dpms_property;
10215
10216                         connector->dpms = DRM_MODE_DPMS_ON;
10217                         drm_object_property_set_value(&connector->base,
10218                                                          dpms_property,
10219                                                          DRM_MODE_DPMS_ON);
10220
10221                         intel_encoder = to_intel_encoder(connector->encoder);
10222                         intel_encoder->connectors_active = true;
10223                 }
10224         }
10225
10226 }
10227
10228 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10229 {
10230         int diff;
10231
10232         if (clock1 == clock2)
10233                 return true;
10234
10235         if (!clock1 || !clock2)
10236                 return false;
10237
10238         diff = abs(clock1 - clock2);
10239
10240         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10241                 return true;
10242
10243         return false;
10244 }
10245
10246 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10247         list_for_each_entry((intel_crtc), \
10248                             &(dev)->mode_config.crtc_list, \
10249                             base.head) \
10250                 if (mask & (1 <<(intel_crtc)->pipe))
10251
10252 static bool
10253 intel_pipe_config_compare(struct drm_device *dev,
10254                           struct intel_crtc_config *current_config,
10255                           struct intel_crtc_config *pipe_config)
10256 {
10257 #define PIPE_CONF_CHECK_X(name) \
10258         if (current_config->name != pipe_config->name) { \
10259                 DRM_ERROR("mismatch in " #name " " \
10260                           "(expected 0x%08x, found 0x%08x)\n", \
10261                           current_config->name, \
10262                           pipe_config->name); \
10263                 return false; \
10264         }
10265
10266 #define PIPE_CONF_CHECK_I(name) \
10267         if (current_config->name != pipe_config->name) { \
10268                 DRM_ERROR("mismatch in " #name " " \
10269                           "(expected %i, found %i)\n", \
10270                           current_config->name, \
10271                           pipe_config->name); \
10272                 return false; \
10273         }
10274
10275 /* This is required for BDW+ where there is only one set of registers for
10276  * switching between high and low RR.
10277  * This macro can be used whenever a comparison has to be made between one
10278  * hw state and multiple sw state variables.
10279  */
10280 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10281         if ((current_config->name != pipe_config->name) && \
10282                 (current_config->alt_name != pipe_config->name)) { \
10283                         DRM_ERROR("mismatch in " #name " " \
10284                                   "(expected %i or %i, found %i)\n", \
10285                                   current_config->name, \
10286                                   current_config->alt_name, \
10287                                   pipe_config->name); \
10288                         return false; \
10289         }
10290
10291 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10292         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10293                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10294                           "(expected %i, found %i)\n", \
10295                           current_config->name & (mask), \
10296                           pipe_config->name & (mask)); \
10297                 return false; \
10298         }
10299
10300 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10301         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10302                 DRM_ERROR("mismatch in " #name " " \
10303                           "(expected %i, found %i)\n", \
10304                           current_config->name, \
10305                           pipe_config->name); \
10306                 return false; \
10307         }
10308
10309 #define PIPE_CONF_QUIRK(quirk)  \
10310         ((current_config->quirks | pipe_config->quirks) & (quirk))
10311
10312         PIPE_CONF_CHECK_I(cpu_transcoder);
10313
10314         PIPE_CONF_CHECK_I(has_pch_encoder);
10315         PIPE_CONF_CHECK_I(fdi_lanes);
10316         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10317         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10318         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10319         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10320         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10321
10322         PIPE_CONF_CHECK_I(has_dp_encoder);
10323
10324         if (INTEL_INFO(dev)->gen < 8) {
10325                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10326                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10327                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10328                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10329                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10330
10331                 if (current_config->has_drrs) {
10332                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10333                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10334                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10335                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10336                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10337                 }
10338         } else {
10339                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10340                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10341                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10342                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10343                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10344         }
10345
10346         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10347         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10348         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10349         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10350         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10351         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10352
10353         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10354         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10355         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10356         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10357         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10358         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10359
10360         PIPE_CONF_CHECK_I(pixel_multiplier);
10361         PIPE_CONF_CHECK_I(has_hdmi_sink);
10362         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10363             IS_VALLEYVIEW(dev))
10364                 PIPE_CONF_CHECK_I(limited_color_range);
10365
10366         PIPE_CONF_CHECK_I(has_audio);
10367
10368         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10369                               DRM_MODE_FLAG_INTERLACE);
10370
10371         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10372                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10373                                       DRM_MODE_FLAG_PHSYNC);
10374                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10375                                       DRM_MODE_FLAG_NHSYNC);
10376                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10377                                       DRM_MODE_FLAG_PVSYNC);
10378                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10379                                       DRM_MODE_FLAG_NVSYNC);
10380         }
10381
10382         PIPE_CONF_CHECK_I(pipe_src_w);
10383         PIPE_CONF_CHECK_I(pipe_src_h);
10384
10385         /*
10386          * FIXME: BIOS likes to set up a cloned config with lvds+external
10387          * screen. Since we don't yet re-compute the pipe config when moving
10388          * just the lvds port away to another pipe the sw tracking won't match.
10389          *
10390          * Proper atomic modesets with recomputed global state will fix this.
10391          * Until then just don't check gmch state for inherited modes.
10392          */
10393         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10394                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10395                 /* pfit ratios are autocomputed by the hw on gen4+ */
10396                 if (INTEL_INFO(dev)->gen < 4)
10397                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10398                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10399         }
10400
10401         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10402         if (current_config->pch_pfit.enabled) {
10403                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10404                 PIPE_CONF_CHECK_I(pch_pfit.size);
10405         }
10406
10407         /* BDW+ don't expose a synchronous way to read the state */
10408         if (IS_HASWELL(dev))
10409                 PIPE_CONF_CHECK_I(ips_enabled);
10410
10411         PIPE_CONF_CHECK_I(double_wide);
10412
10413         PIPE_CONF_CHECK_X(ddi_pll_sel);
10414
10415         PIPE_CONF_CHECK_I(shared_dpll);
10416         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10417         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10418         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10419         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10420         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10421
10422         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10423                 PIPE_CONF_CHECK_I(pipe_bpp);
10424
10425         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10426         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10427
10428 #undef PIPE_CONF_CHECK_X
10429 #undef PIPE_CONF_CHECK_I
10430 #undef PIPE_CONF_CHECK_I_ALT
10431 #undef PIPE_CONF_CHECK_FLAGS
10432 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10433 #undef PIPE_CONF_QUIRK
10434
10435         return true;
10436 }
10437
10438 static void check_wm_state(struct drm_device *dev)
10439 {
10440         struct drm_i915_private *dev_priv = dev->dev_private;
10441         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10442         struct intel_crtc *intel_crtc;
10443         int plane;
10444
10445         if (INTEL_INFO(dev)->gen < 9)
10446                 return;
10447
10448         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10449         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10450
10451         for_each_intel_crtc(dev, intel_crtc) {
10452                 struct skl_ddb_entry *hw_entry, *sw_entry;
10453                 const enum pipe pipe = intel_crtc->pipe;
10454
10455                 if (!intel_crtc->active)
10456                         continue;
10457
10458                 /* planes */
10459                 for_each_plane(pipe, plane) {
10460                         hw_entry = &hw_ddb.plane[pipe][plane];
10461                         sw_entry = &sw_ddb->plane[pipe][plane];
10462
10463                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10464                                 continue;
10465
10466                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10467                                   "(expected (%u,%u), found (%u,%u))\n",
10468                                   pipe_name(pipe), plane + 1,
10469                                   sw_entry->start, sw_entry->end,
10470                                   hw_entry->start, hw_entry->end);
10471                 }
10472
10473                 /* cursor */
10474                 hw_entry = &hw_ddb.cursor[pipe];
10475                 sw_entry = &sw_ddb->cursor[pipe];
10476
10477                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10478                         continue;
10479
10480                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10481                           "(expected (%u,%u), found (%u,%u))\n",
10482                           pipe_name(pipe),
10483                           sw_entry->start, sw_entry->end,
10484                           hw_entry->start, hw_entry->end);
10485         }
10486 }
10487
10488 static void
10489 check_connector_state(struct drm_device *dev)
10490 {
10491         struct intel_connector *connector;
10492
10493         list_for_each_entry(connector, &dev->mode_config.connector_list,
10494                             base.head) {
10495                 /* This also checks the encoder/connector hw state with the
10496                  * ->get_hw_state callbacks. */
10497                 intel_connector_check_state(connector);
10498
10499                 WARN(&connector->new_encoder->base != connector->base.encoder,
10500                      "connector's staged encoder doesn't match current encoder\n");
10501         }
10502 }
10503
10504 static void
10505 check_encoder_state(struct drm_device *dev)
10506 {
10507         struct intel_encoder *encoder;
10508         struct intel_connector *connector;
10509
10510         for_each_intel_encoder(dev, encoder) {
10511                 bool enabled = false;
10512                 bool active = false;
10513                 enum pipe pipe, tracked_pipe;
10514
10515                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10516                               encoder->base.base.id,
10517                               encoder->base.name);
10518
10519                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10520                      "encoder's stage crtc doesn't match current crtc\n");
10521                 WARN(encoder->connectors_active && !encoder->base.crtc,
10522                      "encoder's active_connectors set, but no crtc\n");
10523
10524                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10525                                     base.head) {
10526                         if (connector->base.encoder != &encoder->base)
10527                                 continue;
10528                         enabled = true;
10529                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10530                                 active = true;
10531                 }
10532                 /*
10533                  * for MST connectors if we unplug the connector is gone
10534                  * away but the encoder is still connected to a crtc
10535                  * until a modeset happens in response to the hotplug.
10536                  */
10537                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10538                         continue;
10539
10540                 WARN(!!encoder->base.crtc != enabled,
10541                      "encoder's enabled state mismatch "
10542                      "(expected %i, found %i)\n",
10543                      !!encoder->base.crtc, enabled);
10544                 WARN(active && !encoder->base.crtc,
10545                      "active encoder with no crtc\n");
10546
10547                 WARN(encoder->connectors_active != active,
10548                      "encoder's computed active state doesn't match tracked active state "
10549                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10550
10551                 active = encoder->get_hw_state(encoder, &pipe);
10552                 WARN(active != encoder->connectors_active,
10553                      "encoder's hw state doesn't match sw tracking "
10554                      "(expected %i, found %i)\n",
10555                      encoder->connectors_active, active);
10556
10557                 if (!encoder->base.crtc)
10558                         continue;
10559
10560                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10561                 WARN(active && pipe != tracked_pipe,
10562                      "active encoder's pipe doesn't match"
10563                      "(expected %i, found %i)\n",
10564                      tracked_pipe, pipe);
10565
10566         }
10567 }
10568
10569 static void
10570 check_crtc_state(struct drm_device *dev)
10571 {
10572         struct drm_i915_private *dev_priv = dev->dev_private;
10573         struct intel_crtc *crtc;
10574         struct intel_encoder *encoder;
10575         struct intel_crtc_config pipe_config;
10576
10577         for_each_intel_crtc(dev, crtc) {
10578                 bool enabled = false;
10579                 bool active = false;
10580
10581                 memset(&pipe_config, 0, sizeof(pipe_config));
10582
10583                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10584                               crtc->base.base.id);
10585
10586                 WARN(crtc->active && !crtc->base.enabled,
10587                      "active crtc, but not enabled in sw tracking\n");
10588
10589                 for_each_intel_encoder(dev, encoder) {
10590                         if (encoder->base.crtc != &crtc->base)
10591                                 continue;
10592                         enabled = true;
10593                         if (encoder->connectors_active)
10594                                 active = true;
10595                 }
10596
10597                 WARN(active != crtc->active,
10598                      "crtc's computed active state doesn't match tracked active state "
10599                      "(expected %i, found %i)\n", active, crtc->active);
10600                 WARN(enabled != crtc->base.enabled,
10601                      "crtc's computed enabled state doesn't match tracked enabled state "
10602                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10603
10604                 active = dev_priv->display.get_pipe_config(crtc,
10605                                                            &pipe_config);
10606
10607                 /* hw state is inconsistent with the pipe quirk */
10608                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10609                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10610                         active = crtc->active;
10611
10612                 for_each_intel_encoder(dev, encoder) {
10613                         enum pipe pipe;
10614                         if (encoder->base.crtc != &crtc->base)
10615                                 continue;
10616                         if (encoder->get_hw_state(encoder, &pipe))
10617                                 encoder->get_config(encoder, &pipe_config);
10618                 }
10619
10620                 WARN(crtc->active != active,
10621                      "crtc active state doesn't match with hw state "
10622                      "(expected %i, found %i)\n", crtc->active, active);
10623
10624                 if (active &&
10625                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10626                         WARN(1, "pipe state doesn't match!\n");
10627                         intel_dump_pipe_config(crtc, &pipe_config,
10628                                                "[hw state]");
10629                         intel_dump_pipe_config(crtc, &crtc->config,
10630                                                "[sw state]");
10631                 }
10632         }
10633 }
10634
10635 static void
10636 check_shared_dpll_state(struct drm_device *dev)
10637 {
10638         struct drm_i915_private *dev_priv = dev->dev_private;
10639         struct intel_crtc *crtc;
10640         struct intel_dpll_hw_state dpll_hw_state;
10641         int i;
10642
10643         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10644                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10645                 int enabled_crtcs = 0, active_crtcs = 0;
10646                 bool active;
10647
10648                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10649
10650                 DRM_DEBUG_KMS("%s\n", pll->name);
10651
10652                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10653
10654                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10655                      "more active pll users than references: %i vs %i\n",
10656                      pll->active, hweight32(pll->config.crtc_mask));
10657                 WARN(pll->active && !pll->on,
10658                      "pll in active use but not on in sw tracking\n");
10659                 WARN(pll->on && !pll->active,
10660                      "pll in on but not on in use in sw tracking\n");
10661                 WARN(pll->on != active,
10662                      "pll on state mismatch (expected %i, found %i)\n",
10663                      pll->on, active);
10664
10665                 for_each_intel_crtc(dev, crtc) {
10666                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10667                                 enabled_crtcs++;
10668                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10669                                 active_crtcs++;
10670                 }
10671                 WARN(pll->active != active_crtcs,
10672                      "pll active crtcs mismatch (expected %i, found %i)\n",
10673                      pll->active, active_crtcs);
10674                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10675                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10676                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10677
10678                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10679                                        sizeof(dpll_hw_state)),
10680                      "pll hw state mismatch\n");
10681         }
10682 }
10683
10684 void
10685 intel_modeset_check_state(struct drm_device *dev)
10686 {
10687         check_wm_state(dev);
10688         check_connector_state(dev);
10689         check_encoder_state(dev);
10690         check_crtc_state(dev);
10691         check_shared_dpll_state(dev);
10692 }
10693
10694 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10695                                      int dotclock)
10696 {
10697         /*
10698          * FDI already provided one idea for the dotclock.
10699          * Yell if the encoder disagrees.
10700          */
10701         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10702              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10703              pipe_config->adjusted_mode.crtc_clock, dotclock);
10704 }
10705
10706 static void update_scanline_offset(struct intel_crtc *crtc)
10707 {
10708         struct drm_device *dev = crtc->base.dev;
10709
10710         /*
10711          * The scanline counter increments at the leading edge of hsync.
10712          *
10713          * On most platforms it starts counting from vtotal-1 on the
10714          * first active line. That means the scanline counter value is
10715          * always one less than what we would expect. Ie. just after
10716          * start of vblank, which also occurs at start of hsync (on the
10717          * last active line), the scanline counter will read vblank_start-1.
10718          *
10719          * On gen2 the scanline counter starts counting from 1 instead
10720          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10721          * to keep the value positive), instead of adding one.
10722          *
10723          * On HSW+ the behaviour of the scanline counter depends on the output
10724          * type. For DP ports it behaves like most other platforms, but on HDMI
10725          * there's an extra 1 line difference. So we need to add two instead of
10726          * one to the value.
10727          */
10728         if (IS_GEN2(dev)) {
10729                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10730                 int vtotal;
10731
10732                 vtotal = mode->crtc_vtotal;
10733                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10734                         vtotal /= 2;
10735
10736                 crtc->scanline_offset = vtotal - 1;
10737         } else if (HAS_DDI(dev) &&
10738                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10739                 crtc->scanline_offset = 2;
10740         } else
10741                 crtc->scanline_offset = 1;
10742 }
10743
10744 static int __intel_set_mode(struct drm_crtc *crtc,
10745                             struct drm_display_mode *mode,
10746                             int x, int y, struct drm_framebuffer *fb)
10747 {
10748         struct drm_device *dev = crtc->dev;
10749         struct drm_i915_private *dev_priv = dev->dev_private;
10750         struct drm_display_mode *saved_mode;
10751         struct intel_crtc_config *pipe_config = NULL;
10752         struct intel_crtc *intel_crtc;
10753         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10754         int ret = 0;
10755
10756         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10757         if (!saved_mode)
10758                 return -ENOMEM;
10759
10760         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10761                                      &prepare_pipes, &disable_pipes);
10762
10763         *saved_mode = crtc->mode;
10764
10765         /* Hack: Because we don't (yet) support global modeset on multiple
10766          * crtcs, we don't keep track of the new mode for more than one crtc.
10767          * Hence simply check whether any bit is set in modeset_pipes in all the
10768          * pieces of code that are not yet converted to deal with mutliple crtcs
10769          * changing their mode at the same time. */
10770         if (modeset_pipes) {
10771                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10772                 if (IS_ERR(pipe_config)) {
10773                         ret = PTR_ERR(pipe_config);
10774                         pipe_config = NULL;
10775
10776                         goto out;
10777                 }
10778                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10779                                        "[modeset]");
10780                 to_intel_crtc(crtc)->new_config = pipe_config;
10781         }
10782
10783         /*
10784          * See if the config requires any additional preparation, e.g.
10785          * to adjust global state with pipes off.  We need to do this
10786          * here so we can get the modeset_pipe updated config for the new
10787          * mode set on this crtc.  For other crtcs we need to use the
10788          * adjusted_mode bits in the crtc directly.
10789          */
10790         if (IS_VALLEYVIEW(dev)) {
10791                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10792
10793                 /* may have added more to prepare_pipes than we should */
10794                 prepare_pipes &= ~disable_pipes;
10795         }
10796
10797         if (dev_priv->display.crtc_compute_clock) {
10798                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10799
10800                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10801                 if (ret)
10802                         goto done;
10803
10804                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10805                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10806                         if (ret) {
10807                                 intel_shared_dpll_abort_config(dev_priv);
10808                                 goto done;
10809                         }
10810                 }
10811         }
10812
10813         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10814                 intel_crtc_disable(&intel_crtc->base);
10815
10816         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10817                 if (intel_crtc->base.enabled)
10818                         dev_priv->display.crtc_disable(&intel_crtc->base);
10819         }
10820
10821         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10822          * to set it here already despite that we pass it down the callchain.
10823          */
10824         if (modeset_pipes) {
10825                 crtc->mode = *mode;
10826                 /* mode_set/enable/disable functions rely on a correct pipe
10827                  * config. */
10828                 to_intel_crtc(crtc)->config = *pipe_config;
10829                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10830
10831                 /*
10832                  * Calculate and store various constants which
10833                  * are later needed by vblank and swap-completion
10834                  * timestamping. They are derived from true hwmode.
10835                  */
10836                 drm_calc_timestamping_constants(crtc,
10837                                                 &pipe_config->adjusted_mode);
10838         }
10839
10840         /* Only after disabling all output pipelines that will be changed can we
10841          * update the the output configuration. */
10842         intel_modeset_update_state(dev, prepare_pipes);
10843
10844         modeset_update_crtc_power_domains(dev);
10845
10846         /* Set up the DPLL and any encoders state that needs to adjust or depend
10847          * on the DPLL.
10848          */
10849         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10850                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10851                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10852                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10853
10854                 mutex_lock(&dev->struct_mutex);
10855                 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
10856                 if (ret != 0) {
10857                         DRM_ERROR("pin & fence failed\n");
10858                         mutex_unlock(&dev->struct_mutex);
10859                         goto done;
10860                 }
10861                 if (old_fb)
10862                         intel_unpin_fb_obj(old_obj);
10863                 i915_gem_track_fb(old_obj, obj,
10864                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10865                 mutex_unlock(&dev->struct_mutex);
10866
10867                 crtc->primary->fb = fb;
10868                 crtc->x = x;
10869                 crtc->y = y;
10870         }
10871
10872         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10873         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10874                 update_scanline_offset(intel_crtc);
10875
10876                 dev_priv->display.crtc_enable(&intel_crtc->base);
10877         }
10878
10879         /* FIXME: add subpixel order */
10880 done:
10881         if (ret && crtc->enabled)
10882                 crtc->mode = *saved_mode;
10883
10884 out:
10885         kfree(pipe_config);
10886         kfree(saved_mode);
10887         return ret;
10888 }
10889
10890 static int intel_set_mode(struct drm_crtc *crtc,
10891                           struct drm_display_mode *mode,
10892                           int x, int y, struct drm_framebuffer *fb)
10893 {
10894         int ret;
10895
10896         ret = __intel_set_mode(crtc, mode, x, y, fb);
10897
10898         if (ret == 0)
10899                 intel_modeset_check_state(crtc->dev);
10900
10901         return ret;
10902 }
10903
10904 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10905 {
10906         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10907 }
10908
10909 #undef for_each_intel_crtc_masked
10910
10911 static void intel_set_config_free(struct intel_set_config *config)
10912 {
10913         if (!config)
10914                 return;
10915
10916         kfree(config->save_connector_encoders);
10917         kfree(config->save_encoder_crtcs);
10918         kfree(config->save_crtc_enabled);
10919         kfree(config);
10920 }
10921
10922 static int intel_set_config_save_state(struct drm_device *dev,
10923                                        struct intel_set_config *config)
10924 {
10925         struct drm_crtc *crtc;
10926         struct drm_encoder *encoder;
10927         struct drm_connector *connector;
10928         int count;
10929
10930         config->save_crtc_enabled =
10931                 kcalloc(dev->mode_config.num_crtc,
10932                         sizeof(bool), GFP_KERNEL);
10933         if (!config->save_crtc_enabled)
10934                 return -ENOMEM;
10935
10936         config->save_encoder_crtcs =
10937                 kcalloc(dev->mode_config.num_encoder,
10938                         sizeof(struct drm_crtc *), GFP_KERNEL);
10939         if (!config->save_encoder_crtcs)
10940                 return -ENOMEM;
10941
10942         config->save_connector_encoders =
10943                 kcalloc(dev->mode_config.num_connector,
10944                         sizeof(struct drm_encoder *), GFP_KERNEL);
10945         if (!config->save_connector_encoders)
10946                 return -ENOMEM;
10947
10948         /* Copy data. Note that driver private data is not affected.
10949          * Should anything bad happen only the expected state is
10950          * restored, not the drivers personal bookkeeping.
10951          */
10952         count = 0;
10953         for_each_crtc(dev, crtc) {
10954                 config->save_crtc_enabled[count++] = crtc->enabled;
10955         }
10956
10957         count = 0;
10958         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10959                 config->save_encoder_crtcs[count++] = encoder->crtc;
10960         }
10961
10962         count = 0;
10963         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10964                 config->save_connector_encoders[count++] = connector->encoder;
10965         }
10966
10967         return 0;
10968 }
10969
10970 static void intel_set_config_restore_state(struct drm_device *dev,
10971                                            struct intel_set_config *config)
10972 {
10973         struct intel_crtc *crtc;
10974         struct intel_encoder *encoder;
10975         struct intel_connector *connector;
10976         int count;
10977
10978         count = 0;
10979         for_each_intel_crtc(dev, crtc) {
10980                 crtc->new_enabled = config->save_crtc_enabled[count++];
10981
10982                 if (crtc->new_enabled)
10983                         crtc->new_config = &crtc->config;
10984                 else
10985                         crtc->new_config = NULL;
10986         }
10987
10988         count = 0;
10989         for_each_intel_encoder(dev, encoder) {
10990                 encoder->new_crtc =
10991                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10992         }
10993
10994         count = 0;
10995         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10996                 connector->new_encoder =
10997                         to_intel_encoder(config->save_connector_encoders[count++]);
10998         }
10999 }
11000
11001 static bool
11002 is_crtc_connector_off(struct drm_mode_set *set)
11003 {
11004         int i;
11005
11006         if (set->num_connectors == 0)
11007                 return false;
11008
11009         if (WARN_ON(set->connectors == NULL))
11010                 return false;
11011
11012         for (i = 0; i < set->num_connectors; i++)
11013                 if (set->connectors[i]->encoder &&
11014                     set->connectors[i]->encoder->crtc == set->crtc &&
11015                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11016                         return true;
11017
11018         return false;
11019 }
11020
11021 static void
11022 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11023                                       struct intel_set_config *config)
11024 {
11025
11026         /* We should be able to check here if the fb has the same properties
11027          * and then just flip_or_move it */
11028         if (is_crtc_connector_off(set)) {
11029                 config->mode_changed = true;
11030         } else if (set->crtc->primary->fb != set->fb) {
11031                 /*
11032                  * If we have no fb, we can only flip as long as the crtc is
11033                  * active, otherwise we need a full mode set.  The crtc may
11034                  * be active if we've only disabled the primary plane, or
11035                  * in fastboot situations.
11036                  */
11037                 if (set->crtc->primary->fb == NULL) {
11038                         struct intel_crtc *intel_crtc =
11039                                 to_intel_crtc(set->crtc);
11040
11041                         if (intel_crtc->active) {
11042                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11043                                 config->fb_changed = true;
11044                         } else {
11045                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11046                                 config->mode_changed = true;
11047                         }
11048                 } else if (set->fb == NULL) {
11049                         config->mode_changed = true;
11050                 } else if (set->fb->pixel_format !=
11051                            set->crtc->primary->fb->pixel_format) {
11052                         config->mode_changed = true;
11053                 } else {
11054                         config->fb_changed = true;
11055                 }
11056         }
11057
11058         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11059                 config->fb_changed = true;
11060
11061         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11062                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11063                 drm_mode_debug_printmodeline(&set->crtc->mode);
11064                 drm_mode_debug_printmodeline(set->mode);
11065                 config->mode_changed = true;
11066         }
11067
11068         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11069                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11070 }
11071
11072 static int
11073 intel_modeset_stage_output_state(struct drm_device *dev,
11074                                  struct drm_mode_set *set,
11075                                  struct intel_set_config *config)
11076 {
11077         struct intel_connector *connector;
11078         struct intel_encoder *encoder;
11079         struct intel_crtc *crtc;
11080         int ro;
11081
11082         /* The upper layers ensure that we either disable a crtc or have a list
11083          * of connectors. For paranoia, double-check this. */
11084         WARN_ON(!set->fb && (set->num_connectors != 0));
11085         WARN_ON(set->fb && (set->num_connectors == 0));
11086
11087         list_for_each_entry(connector, &dev->mode_config.connector_list,
11088                             base.head) {
11089                 /* Otherwise traverse passed in connector list and get encoders
11090                  * for them. */
11091                 for (ro = 0; ro < set->num_connectors; ro++) {
11092                         if (set->connectors[ro] == &connector->base) {
11093                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11094                                 break;
11095                         }
11096                 }
11097
11098                 /* If we disable the crtc, disable all its connectors. Also, if
11099                  * the connector is on the changing crtc but not on the new
11100                  * connector list, disable it. */
11101                 if ((!set->fb || ro == set->num_connectors) &&
11102                     connector->base.encoder &&
11103                     connector->base.encoder->crtc == set->crtc) {
11104                         connector->new_encoder = NULL;
11105
11106                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11107                                 connector->base.base.id,
11108                                 connector->base.name);
11109                 }
11110
11111
11112                 if (&connector->new_encoder->base != connector->base.encoder) {
11113                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11114                         config->mode_changed = true;
11115                 }
11116         }
11117         /* connector->new_encoder is now updated for all connectors. */
11118
11119         /* Update crtc of enabled connectors. */
11120         list_for_each_entry(connector, &dev->mode_config.connector_list,
11121                             base.head) {
11122                 struct drm_crtc *new_crtc;
11123
11124                 if (!connector->new_encoder)
11125                         continue;
11126
11127                 new_crtc = connector->new_encoder->base.crtc;
11128
11129                 for (ro = 0; ro < set->num_connectors; ro++) {
11130                         if (set->connectors[ro] == &connector->base)
11131                                 new_crtc = set->crtc;
11132                 }
11133
11134                 /* Make sure the new CRTC will work with the encoder */
11135                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11136                                          new_crtc)) {
11137                         return -EINVAL;
11138                 }
11139                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11140
11141                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11142                         connector->base.base.id,
11143                         connector->base.name,
11144                         new_crtc->base.id);
11145         }
11146
11147         /* Check for any encoders that needs to be disabled. */
11148         for_each_intel_encoder(dev, encoder) {
11149                 int num_connectors = 0;
11150                 list_for_each_entry(connector,
11151                                     &dev->mode_config.connector_list,
11152                                     base.head) {
11153                         if (connector->new_encoder == encoder) {
11154                                 WARN_ON(!connector->new_encoder->new_crtc);
11155                                 num_connectors++;
11156                         }
11157                 }
11158
11159                 if (num_connectors == 0)
11160                         encoder->new_crtc = NULL;
11161                 else if (num_connectors > 1)
11162                         return -EINVAL;
11163
11164                 /* Only now check for crtc changes so we don't miss encoders
11165                  * that will be disabled. */
11166                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11167                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11168                         config->mode_changed = true;
11169                 }
11170         }
11171         /* Now we've also updated encoder->new_crtc for all encoders. */
11172         list_for_each_entry(connector, &dev->mode_config.connector_list,
11173                             base.head) {
11174                 if (connector->new_encoder)
11175                         if (connector->new_encoder != connector->encoder)
11176                                 connector->encoder = connector->new_encoder;
11177         }
11178         for_each_intel_crtc(dev, crtc) {
11179                 crtc->new_enabled = false;
11180
11181                 for_each_intel_encoder(dev, encoder) {
11182                         if (encoder->new_crtc == crtc) {
11183                                 crtc->new_enabled = true;
11184                                 break;
11185                         }
11186                 }
11187
11188                 if (crtc->new_enabled != crtc->base.enabled) {
11189                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11190                                       crtc->new_enabled ? "en" : "dis");
11191                         config->mode_changed = true;
11192                 }
11193
11194                 if (crtc->new_enabled)
11195                         crtc->new_config = &crtc->config;
11196                 else
11197                         crtc->new_config = NULL;
11198         }
11199
11200         return 0;
11201 }
11202
11203 static void disable_crtc_nofb(struct intel_crtc *crtc)
11204 {
11205         struct drm_device *dev = crtc->base.dev;
11206         struct intel_encoder *encoder;
11207         struct intel_connector *connector;
11208
11209         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11210                       pipe_name(crtc->pipe));
11211
11212         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11213                 if (connector->new_encoder &&
11214                     connector->new_encoder->new_crtc == crtc)
11215                         connector->new_encoder = NULL;
11216         }
11217
11218         for_each_intel_encoder(dev, encoder) {
11219                 if (encoder->new_crtc == crtc)
11220                         encoder->new_crtc = NULL;
11221         }
11222
11223         crtc->new_enabled = false;
11224         crtc->new_config = NULL;
11225 }
11226
11227 static int intel_crtc_set_config(struct drm_mode_set *set)
11228 {
11229         struct drm_device *dev;
11230         struct drm_mode_set save_set;
11231         struct intel_set_config *config;
11232         int ret;
11233
11234         BUG_ON(!set);
11235         BUG_ON(!set->crtc);
11236         BUG_ON(!set->crtc->helper_private);
11237
11238         /* Enforce sane interface api - has been abused by the fb helper. */
11239         BUG_ON(!set->mode && set->fb);
11240         BUG_ON(set->fb && set->num_connectors == 0);
11241
11242         if (set->fb) {
11243                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11244                                 set->crtc->base.id, set->fb->base.id,
11245                                 (int)set->num_connectors, set->x, set->y);
11246         } else {
11247                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11248         }
11249
11250         dev = set->crtc->dev;
11251
11252         ret = -ENOMEM;
11253         config = kzalloc(sizeof(*config), GFP_KERNEL);
11254         if (!config)
11255                 goto out_config;
11256
11257         ret = intel_set_config_save_state(dev, config);
11258         if (ret)
11259                 goto out_config;
11260
11261         save_set.crtc = set->crtc;
11262         save_set.mode = &set->crtc->mode;
11263         save_set.x = set->crtc->x;
11264         save_set.y = set->crtc->y;
11265         save_set.fb = set->crtc->primary->fb;
11266
11267         /* Compute whether we need a full modeset, only an fb base update or no
11268          * change at all. In the future we might also check whether only the
11269          * mode changed, e.g. for LVDS where we only change the panel fitter in
11270          * such cases. */
11271         intel_set_config_compute_mode_changes(set, config);
11272
11273         ret = intel_modeset_stage_output_state(dev, set, config);
11274         if (ret)
11275                 goto fail;
11276
11277         if (config->mode_changed) {
11278                 ret = intel_set_mode(set->crtc, set->mode,
11279                                      set->x, set->y, set->fb);
11280         } else if (config->fb_changed) {
11281                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11282
11283                 intel_crtc_wait_for_pending_flips(set->crtc);
11284
11285                 ret = intel_pipe_set_base(set->crtc,
11286                                           set->x, set->y, set->fb);
11287
11288                 /*
11289                  * We need to make sure the primary plane is re-enabled if it
11290                  * has previously been turned off.
11291                  */
11292                 if (!intel_crtc->primary_enabled && ret == 0) {
11293                         WARN_ON(!intel_crtc->active);
11294                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11295                 }
11296
11297                 /*
11298                  * In the fastboot case this may be our only check of the
11299                  * state after boot.  It would be better to only do it on
11300                  * the first update, but we don't have a nice way of doing that
11301                  * (and really, set_config isn't used much for high freq page
11302                  * flipping, so increasing its cost here shouldn't be a big
11303                  * deal).
11304                  */
11305                 if (i915.fastboot && ret == 0)
11306                         intel_modeset_check_state(set->crtc->dev);
11307         }
11308
11309         if (ret) {
11310                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11311                               set->crtc->base.id, ret);
11312 fail:
11313                 intel_set_config_restore_state(dev, config);
11314
11315                 /*
11316                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11317                  * force the pipe off to avoid oopsing in the modeset code
11318                  * due to fb==NULL. This should only happen during boot since
11319                  * we don't yet reconstruct the FB from the hardware state.
11320                  */
11321                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11322                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11323
11324                 /* Try to restore the config */
11325                 if (config->mode_changed &&
11326                     intel_set_mode(save_set.crtc, save_set.mode,
11327                                    save_set.x, save_set.y, save_set.fb))
11328                         DRM_ERROR("failed to restore config after modeset failure\n");
11329         }
11330
11331 out_config:
11332         intel_set_config_free(config);
11333         return ret;
11334 }
11335
11336 static const struct drm_crtc_funcs intel_crtc_funcs = {
11337         .gamma_set = intel_crtc_gamma_set,
11338         .set_config = intel_crtc_set_config,
11339         .destroy = intel_crtc_destroy,
11340         .page_flip = intel_crtc_page_flip,
11341 };
11342
11343 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11344                                       struct intel_shared_dpll *pll,
11345                                       struct intel_dpll_hw_state *hw_state)
11346 {
11347         uint32_t val;
11348
11349         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11350                 return false;
11351
11352         val = I915_READ(PCH_DPLL(pll->id));
11353         hw_state->dpll = val;
11354         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11355         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11356
11357         return val & DPLL_VCO_ENABLE;
11358 }
11359
11360 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11361                                   struct intel_shared_dpll *pll)
11362 {
11363         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11364         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11365 }
11366
11367 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11368                                 struct intel_shared_dpll *pll)
11369 {
11370         /* PCH refclock must be enabled first */
11371         ibx_assert_pch_refclk_enabled(dev_priv);
11372
11373         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11374
11375         /* Wait for the clocks to stabilize. */
11376         POSTING_READ(PCH_DPLL(pll->id));
11377         udelay(150);
11378
11379         /* The pixel multiplier can only be updated once the
11380          * DPLL is enabled and the clocks are stable.
11381          *
11382          * So write it again.
11383          */
11384         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11385         POSTING_READ(PCH_DPLL(pll->id));
11386         udelay(200);
11387 }
11388
11389 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11390                                  struct intel_shared_dpll *pll)
11391 {
11392         struct drm_device *dev = dev_priv->dev;
11393         struct intel_crtc *crtc;
11394
11395         /* Make sure no transcoder isn't still depending on us. */
11396         for_each_intel_crtc(dev, crtc) {
11397                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11398                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11399         }
11400
11401         I915_WRITE(PCH_DPLL(pll->id), 0);
11402         POSTING_READ(PCH_DPLL(pll->id));
11403         udelay(200);
11404 }
11405
11406 static char *ibx_pch_dpll_names[] = {
11407         "PCH DPLL A",
11408         "PCH DPLL B",
11409 };
11410
11411 static void ibx_pch_dpll_init(struct drm_device *dev)
11412 {
11413         struct drm_i915_private *dev_priv = dev->dev_private;
11414         int i;
11415
11416         dev_priv->num_shared_dpll = 2;
11417
11418         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11419                 dev_priv->shared_dplls[i].id = i;
11420                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11421                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11422                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11423                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11424                 dev_priv->shared_dplls[i].get_hw_state =
11425                         ibx_pch_dpll_get_hw_state;
11426         }
11427 }
11428
11429 static void intel_shared_dpll_init(struct drm_device *dev)
11430 {
11431         struct drm_i915_private *dev_priv = dev->dev_private;
11432
11433         if (HAS_DDI(dev))
11434                 intel_ddi_pll_init(dev);
11435         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11436                 ibx_pch_dpll_init(dev);
11437         else
11438                 dev_priv->num_shared_dpll = 0;
11439
11440         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11441 }
11442
11443 static int
11444 intel_primary_plane_disable(struct drm_plane *plane)
11445 {
11446         struct drm_device *dev = plane->dev;
11447         struct intel_crtc *intel_crtc;
11448
11449         if (!plane->fb)
11450                 return 0;
11451
11452         BUG_ON(!plane->crtc);
11453
11454         intel_crtc = to_intel_crtc(plane->crtc);
11455
11456         /*
11457          * Even though we checked plane->fb above, it's still possible that
11458          * the primary plane has been implicitly disabled because the crtc
11459          * coordinates given weren't visible, or because we detected
11460          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11461          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11462          * In either case, we need to unpin the FB and let the fb pointer get
11463          * updated, but otherwise we don't need to touch the hardware.
11464          */
11465         if (!intel_crtc->primary_enabled)
11466                 goto disable_unpin;
11467
11468         intel_crtc_wait_for_pending_flips(plane->crtc);
11469         intel_disable_primary_hw_plane(plane, plane->crtc);
11470
11471 disable_unpin:
11472         mutex_lock(&dev->struct_mutex);
11473         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11474                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11475         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11476         mutex_unlock(&dev->struct_mutex);
11477         plane->fb = NULL;
11478
11479         return 0;
11480 }
11481
11482 static int
11483 intel_check_primary_plane(struct drm_plane *plane,
11484                           struct intel_plane_state *state)
11485 {
11486         struct drm_crtc *crtc = state->crtc;
11487         struct drm_framebuffer *fb = state->fb;
11488         struct drm_rect *dest = &state->dst;
11489         struct drm_rect *src = &state->src;
11490         const struct drm_rect *clip = &state->clip;
11491
11492         return drm_plane_helper_check_update(plane, crtc, fb,
11493                                              src, dest, clip,
11494                                              DRM_PLANE_HELPER_NO_SCALING,
11495                                              DRM_PLANE_HELPER_NO_SCALING,
11496                                              false, true, &state->visible);
11497 }
11498
11499 static int
11500 intel_prepare_primary_plane(struct drm_plane *plane,
11501                             struct intel_plane_state *state)
11502 {
11503         struct drm_crtc *crtc = state->crtc;
11504         struct drm_framebuffer *fb = state->fb;
11505         struct drm_device *dev = crtc->dev;
11506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11507         enum pipe pipe = intel_crtc->pipe;
11508         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11509         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11510         int ret;
11511
11512         intel_crtc_wait_for_pending_flips(crtc);
11513
11514         if (intel_crtc_has_pending_flip(crtc)) {
11515                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11516                 return -EBUSY;
11517         }
11518
11519         if (old_obj != obj) {
11520                 mutex_lock(&dev->struct_mutex);
11521                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11522                 if (ret == 0)
11523                         i915_gem_track_fb(old_obj, obj,
11524                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11525                 mutex_unlock(&dev->struct_mutex);
11526                 if (ret != 0) {
11527                         DRM_DEBUG_KMS("pin & fence failed\n");
11528                         return ret;
11529                 }
11530         }
11531
11532         return 0;
11533 }
11534
11535 static void
11536 intel_commit_primary_plane(struct drm_plane *plane,
11537                            struct intel_plane_state *state)
11538 {
11539         struct drm_crtc *crtc = state->crtc;
11540         struct drm_framebuffer *fb = state->fb;
11541         struct drm_device *dev = crtc->dev;
11542         struct drm_i915_private *dev_priv = dev->dev_private;
11543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11544         enum pipe pipe = intel_crtc->pipe;
11545         struct drm_framebuffer *old_fb = plane->fb;
11546         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11547         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11548         struct intel_plane *intel_plane = to_intel_plane(plane);
11549         struct drm_rect *src = &state->src;
11550
11551         crtc->primary->fb = fb;
11552         crtc->x = src->x1;
11553         crtc->y = src->y1;
11554
11555         intel_plane->crtc_x = state->orig_dst.x1;
11556         intel_plane->crtc_y = state->orig_dst.y1;
11557         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11558         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11559         intel_plane->src_x = state->orig_src.x1;
11560         intel_plane->src_y = state->orig_src.y1;
11561         intel_plane->src_w = drm_rect_width(&state->orig_src);
11562         intel_plane->src_h = drm_rect_height(&state->orig_src);
11563         intel_plane->obj = obj;
11564
11565         if (intel_crtc->active) {
11566                 /*
11567                  * FBC does not work on some platforms for rotated
11568                  * planes, so disable it when rotation is not 0 and
11569                  * update it when rotation is set back to 0.
11570                  *
11571                  * FIXME: This is redundant with the fbc update done in
11572                  * the primary plane enable function except that that
11573                  * one is done too late. We eventually need to unify
11574                  * this.
11575                  */
11576                 if (intel_crtc->primary_enabled &&
11577                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11578                     dev_priv->fbc.plane == intel_crtc->plane &&
11579                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11580                         intel_disable_fbc(dev);
11581                 }
11582
11583                 if (state->visible) {
11584                         bool was_enabled = intel_crtc->primary_enabled;
11585
11586                         /* FIXME: kill this fastboot hack */
11587                         intel_update_pipe_size(intel_crtc);
11588
11589                         intel_crtc->primary_enabled = true;
11590
11591                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11592                                         crtc->x, crtc->y);
11593
11594                         /*
11595                          * BDW signals flip done immediately if the plane
11596                          * is disabled, even if the plane enable is already
11597                          * armed to occur at the next vblank :(
11598                          */
11599                         if (IS_BROADWELL(dev) && !was_enabled)
11600                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11601                 } else {
11602                         /*
11603                          * If clipping results in a non-visible primary plane,
11604                          * we'll disable the primary plane.  Note that this is
11605                          * a bit different than what happens if userspace
11606                          * explicitly disables the plane by passing fb=0
11607                          * because plane->fb still gets set and pinned.
11608                          */
11609                         intel_disable_primary_hw_plane(plane, crtc);
11610                 }
11611
11612                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11613
11614                 mutex_lock(&dev->struct_mutex);
11615                 intel_update_fbc(dev);
11616                 mutex_unlock(&dev->struct_mutex);
11617         }
11618
11619         if (old_fb && old_fb != fb) {
11620                 if (intel_crtc->active)
11621                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11622
11623                 mutex_lock(&dev->struct_mutex);
11624                 intel_unpin_fb_obj(old_obj);
11625                 mutex_unlock(&dev->struct_mutex);
11626         }
11627 }
11628
11629 static int
11630 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11631                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11632                              unsigned int crtc_w, unsigned int crtc_h,
11633                              uint32_t src_x, uint32_t src_y,
11634                              uint32_t src_w, uint32_t src_h)
11635 {
11636         struct intel_plane_state state;
11637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11638         int ret;
11639
11640         state.crtc = crtc;
11641         state.fb = fb;
11642
11643         /* sample coordinates in 16.16 fixed point */
11644         state.src.x1 = src_x;
11645         state.src.x2 = src_x + src_w;
11646         state.src.y1 = src_y;
11647         state.src.y2 = src_y + src_h;
11648
11649         /* integer pixels */
11650         state.dst.x1 = crtc_x;
11651         state.dst.x2 = crtc_x + crtc_w;
11652         state.dst.y1 = crtc_y;
11653         state.dst.y2 = crtc_y + crtc_h;
11654
11655         state.clip.x1 = 0;
11656         state.clip.y1 = 0;
11657         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11658         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11659
11660         state.orig_src = state.src;
11661         state.orig_dst = state.dst;
11662
11663         ret = intel_check_primary_plane(plane, &state);
11664         if (ret)
11665                 return ret;
11666
11667         ret = intel_prepare_primary_plane(plane, &state);
11668         if (ret)
11669                 return ret;
11670
11671         intel_commit_primary_plane(plane, &state);
11672
11673         return 0;
11674 }
11675
11676 /* Common destruction function for both primary and cursor planes */
11677 static void intel_plane_destroy(struct drm_plane *plane)
11678 {
11679         struct intel_plane *intel_plane = to_intel_plane(plane);
11680         drm_plane_cleanup(plane);
11681         kfree(intel_plane);
11682 }
11683
11684 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11685         .update_plane = intel_primary_plane_setplane,
11686         .disable_plane = intel_primary_plane_disable,
11687         .destroy = intel_plane_destroy,
11688         .set_property = intel_plane_set_property
11689 };
11690
11691 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11692                                                     int pipe)
11693 {
11694         struct intel_plane *primary;
11695         const uint32_t *intel_primary_formats;
11696         int num_formats;
11697
11698         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11699         if (primary == NULL)
11700                 return NULL;
11701
11702         primary->can_scale = false;
11703         primary->max_downscale = 1;
11704         primary->pipe = pipe;
11705         primary->plane = pipe;
11706         primary->rotation = BIT(DRM_ROTATE_0);
11707         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11708                 primary->plane = !pipe;
11709
11710         if (INTEL_INFO(dev)->gen <= 3) {
11711                 intel_primary_formats = intel_primary_formats_gen2;
11712                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11713         } else {
11714                 intel_primary_formats = intel_primary_formats_gen4;
11715                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11716         }
11717
11718         drm_universal_plane_init(dev, &primary->base, 0,
11719                                  &intel_primary_plane_funcs,
11720                                  intel_primary_formats, num_formats,
11721                                  DRM_PLANE_TYPE_PRIMARY);
11722
11723         if (INTEL_INFO(dev)->gen >= 4) {
11724                 if (!dev->mode_config.rotation_property)
11725                         dev->mode_config.rotation_property =
11726                                 drm_mode_create_rotation_property(dev,
11727                                                         BIT(DRM_ROTATE_0) |
11728                                                         BIT(DRM_ROTATE_180));
11729                 if (dev->mode_config.rotation_property)
11730                         drm_object_attach_property(&primary->base.base,
11731                                 dev->mode_config.rotation_property,
11732                                 primary->rotation);
11733         }
11734
11735         return &primary->base;
11736 }
11737
11738 static int
11739 intel_cursor_plane_disable(struct drm_plane *plane)
11740 {
11741         if (!plane->fb)
11742                 return 0;
11743
11744         BUG_ON(!plane->crtc);
11745
11746         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11747 }
11748
11749 static int
11750 intel_check_cursor_plane(struct drm_plane *plane,
11751                          struct intel_plane_state *state)
11752 {
11753         struct drm_crtc *crtc = state->crtc;
11754         struct drm_device *dev = crtc->dev;
11755         struct drm_framebuffer *fb = state->fb;
11756         struct drm_rect *dest = &state->dst;
11757         struct drm_rect *src = &state->src;
11758         const struct drm_rect *clip = &state->clip;
11759         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11760         int crtc_w, crtc_h;
11761         unsigned stride;
11762         int ret;
11763
11764         ret = drm_plane_helper_check_update(plane, crtc, fb,
11765                                             src, dest, clip,
11766                                             DRM_PLANE_HELPER_NO_SCALING,
11767                                             DRM_PLANE_HELPER_NO_SCALING,
11768                                             true, true, &state->visible);
11769         if (ret)
11770                 return ret;
11771
11772
11773         /* if we want to turn off the cursor ignore width and height */
11774         if (!obj)
11775                 return 0;
11776
11777         /* Check for which cursor types we support */
11778         crtc_w = drm_rect_width(&state->orig_dst);
11779         crtc_h = drm_rect_height(&state->orig_dst);
11780         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11781                 DRM_DEBUG("Cursor dimension not supported\n");
11782                 return -EINVAL;
11783         }
11784
11785         stride = roundup_pow_of_two(crtc_w) * 4;
11786         if (obj->base.size < stride * crtc_h) {
11787                 DRM_DEBUG_KMS("buffer is too small\n");
11788                 return -ENOMEM;
11789         }
11790
11791         if (fb == crtc->cursor->fb)
11792                 return 0;
11793
11794         /* we only need to pin inside GTT if cursor is non-phy */
11795         mutex_lock(&dev->struct_mutex);
11796         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11797                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11798                 ret = -EINVAL;
11799         }
11800         mutex_unlock(&dev->struct_mutex);
11801
11802         return ret;
11803 }
11804
11805 static int
11806 intel_commit_cursor_plane(struct drm_plane *plane,
11807                           struct intel_plane_state *state)
11808 {
11809         struct drm_crtc *crtc = state->crtc;
11810         struct drm_framebuffer *fb = state->fb;
11811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11812         struct intel_plane *intel_plane = to_intel_plane(plane);
11813         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11814         struct drm_i915_gem_object *obj = intel_fb->obj;
11815         int crtc_w, crtc_h;
11816
11817         crtc->cursor_x = state->orig_dst.x1;
11818         crtc->cursor_y = state->orig_dst.y1;
11819
11820         intel_plane->crtc_x = state->orig_dst.x1;
11821         intel_plane->crtc_y = state->orig_dst.y1;
11822         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11823         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11824         intel_plane->src_x = state->orig_src.x1;
11825         intel_plane->src_y = state->orig_src.y1;
11826         intel_plane->src_w = drm_rect_width(&state->orig_src);
11827         intel_plane->src_h = drm_rect_height(&state->orig_src);
11828         intel_plane->obj = obj;
11829
11830         if (fb != crtc->cursor->fb) {
11831                 crtc_w = drm_rect_width(&state->orig_dst);
11832                 crtc_h = drm_rect_height(&state->orig_dst);
11833                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11834         } else {
11835                 intel_crtc_update_cursor(crtc, state->visible);
11836
11837                 intel_frontbuffer_flip(crtc->dev,
11838                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11839
11840                 return 0;
11841         }
11842 }
11843
11844 static int
11845 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11846                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11847                           unsigned int crtc_w, unsigned int crtc_h,
11848                           uint32_t src_x, uint32_t src_y,
11849                           uint32_t src_w, uint32_t src_h)
11850 {
11851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11852         struct intel_plane_state state;
11853         int ret;
11854
11855         state.crtc = crtc;
11856         state.fb = fb;
11857
11858         /* sample coordinates in 16.16 fixed point */
11859         state.src.x1 = src_x;
11860         state.src.x2 = src_x + src_w;
11861         state.src.y1 = src_y;
11862         state.src.y2 = src_y + src_h;
11863
11864         /* integer pixels */
11865         state.dst.x1 = crtc_x;
11866         state.dst.x2 = crtc_x + crtc_w;
11867         state.dst.y1 = crtc_y;
11868         state.dst.y2 = crtc_y + crtc_h;
11869
11870         state.clip.x1 = 0;
11871         state.clip.y1 = 0;
11872         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11873         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11874
11875         state.orig_src = state.src;
11876         state.orig_dst = state.dst;
11877
11878         ret = intel_check_cursor_plane(plane, &state);
11879         if (ret)
11880                 return ret;
11881
11882         return intel_commit_cursor_plane(plane, &state);
11883 }
11884
11885 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11886         .update_plane = intel_cursor_plane_update,
11887         .disable_plane = intel_cursor_plane_disable,
11888         .destroy = intel_plane_destroy,
11889         .set_property = intel_plane_set_property,
11890 };
11891
11892 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11893                                                    int pipe)
11894 {
11895         struct intel_plane *cursor;
11896
11897         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11898         if (cursor == NULL)
11899                 return NULL;
11900
11901         cursor->can_scale = false;
11902         cursor->max_downscale = 1;
11903         cursor->pipe = pipe;
11904         cursor->plane = pipe;
11905         cursor->rotation = BIT(DRM_ROTATE_0);
11906
11907         drm_universal_plane_init(dev, &cursor->base, 0,
11908                                  &intel_cursor_plane_funcs,
11909                                  intel_cursor_formats,
11910                                  ARRAY_SIZE(intel_cursor_formats),
11911                                  DRM_PLANE_TYPE_CURSOR);
11912
11913         if (INTEL_INFO(dev)->gen >= 4) {
11914                 if (!dev->mode_config.rotation_property)
11915                         dev->mode_config.rotation_property =
11916                                 drm_mode_create_rotation_property(dev,
11917                                                         BIT(DRM_ROTATE_0) |
11918                                                         BIT(DRM_ROTATE_180));
11919                 if (dev->mode_config.rotation_property)
11920                         drm_object_attach_property(&cursor->base.base,
11921                                 dev->mode_config.rotation_property,
11922                                 cursor->rotation);
11923         }
11924
11925         return &cursor->base;
11926 }
11927
11928 static void intel_crtc_init(struct drm_device *dev, int pipe)
11929 {
11930         struct drm_i915_private *dev_priv = dev->dev_private;
11931         struct intel_crtc *intel_crtc;
11932         struct drm_plane *primary = NULL;
11933         struct drm_plane *cursor = NULL;
11934         int i, ret;
11935
11936         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11937         if (intel_crtc == NULL)
11938                 return;
11939
11940         primary = intel_primary_plane_create(dev, pipe);
11941         if (!primary)
11942                 goto fail;
11943
11944         cursor = intel_cursor_plane_create(dev, pipe);
11945         if (!cursor)
11946                 goto fail;
11947
11948         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11949                                         cursor, &intel_crtc_funcs);
11950         if (ret)
11951                 goto fail;
11952
11953         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11954         for (i = 0; i < 256; i++) {
11955                 intel_crtc->lut_r[i] = i;
11956                 intel_crtc->lut_g[i] = i;
11957                 intel_crtc->lut_b[i] = i;
11958         }
11959
11960         /*
11961          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11962          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11963          */
11964         intel_crtc->pipe = pipe;
11965         intel_crtc->plane = pipe;
11966         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11967                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11968                 intel_crtc->plane = !pipe;
11969         }
11970
11971         intel_crtc->cursor_base = ~0;
11972         intel_crtc->cursor_cntl = ~0;
11973         intel_crtc->cursor_size = ~0;
11974
11975         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11976                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11977         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11978         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11979
11980         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
11981
11982         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11983
11984         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11985         return;
11986
11987 fail:
11988         if (primary)
11989                 drm_plane_cleanup(primary);
11990         if (cursor)
11991                 drm_plane_cleanup(cursor);
11992         kfree(intel_crtc);
11993 }
11994
11995 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11996 {
11997         struct drm_encoder *encoder = connector->base.encoder;
11998         struct drm_device *dev = connector->base.dev;
11999
12000         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12001
12002         if (!encoder)
12003                 return INVALID_PIPE;
12004
12005         return to_intel_crtc(encoder->crtc)->pipe;
12006 }
12007
12008 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12009                                 struct drm_file *file)
12010 {
12011         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12012         struct drm_crtc *drmmode_crtc;
12013         struct intel_crtc *crtc;
12014
12015         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12016                 return -ENODEV;
12017
12018         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12019
12020         if (!drmmode_crtc) {
12021                 DRM_ERROR("no such CRTC id\n");
12022                 return -ENOENT;
12023         }
12024
12025         crtc = to_intel_crtc(drmmode_crtc);
12026         pipe_from_crtc_id->pipe = crtc->pipe;
12027
12028         return 0;
12029 }
12030
12031 static int intel_encoder_clones(struct intel_encoder *encoder)
12032 {
12033         struct drm_device *dev = encoder->base.dev;
12034         struct intel_encoder *source_encoder;
12035         int index_mask = 0;
12036         int entry = 0;
12037
12038         for_each_intel_encoder(dev, source_encoder) {
12039                 if (encoders_cloneable(encoder, source_encoder))
12040                         index_mask |= (1 << entry);
12041
12042                 entry++;
12043         }
12044
12045         return index_mask;
12046 }
12047
12048 static bool has_edp_a(struct drm_device *dev)
12049 {
12050         struct drm_i915_private *dev_priv = dev->dev_private;
12051
12052         if (!IS_MOBILE(dev))
12053                 return false;
12054
12055         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12056                 return false;
12057
12058         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12059                 return false;
12060
12061         return true;
12062 }
12063
12064 const char *intel_output_name(int output)
12065 {
12066         static const char *names[] = {
12067                 [INTEL_OUTPUT_UNUSED] = "Unused",
12068                 [INTEL_OUTPUT_ANALOG] = "Analog",
12069                 [INTEL_OUTPUT_DVO] = "DVO",
12070                 [INTEL_OUTPUT_SDVO] = "SDVO",
12071                 [INTEL_OUTPUT_LVDS] = "LVDS",
12072                 [INTEL_OUTPUT_TVOUT] = "TV",
12073                 [INTEL_OUTPUT_HDMI] = "HDMI",
12074                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12075                 [INTEL_OUTPUT_EDP] = "eDP",
12076                 [INTEL_OUTPUT_DSI] = "DSI",
12077                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12078         };
12079
12080         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12081                 return "Invalid";
12082
12083         return names[output];
12084 }
12085
12086 static bool intel_crt_present(struct drm_device *dev)
12087 {
12088         struct drm_i915_private *dev_priv = dev->dev_private;
12089
12090         if (INTEL_INFO(dev)->gen >= 9)
12091                 return false;
12092
12093         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12094                 return false;
12095
12096         if (IS_CHERRYVIEW(dev))
12097                 return false;
12098
12099         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12100                 return false;
12101
12102         return true;
12103 }
12104
12105 static void intel_setup_outputs(struct drm_device *dev)
12106 {
12107         struct drm_i915_private *dev_priv = dev->dev_private;
12108         struct intel_encoder *encoder;
12109         bool dpd_is_edp = false;
12110
12111         intel_lvds_init(dev);
12112
12113         if (intel_crt_present(dev))
12114                 intel_crt_init(dev);
12115
12116         if (HAS_DDI(dev)) {
12117                 int found;
12118
12119                 /* Haswell uses DDI functions to detect digital outputs */
12120                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12121                 /* DDI A only supports eDP */
12122                 if (found)
12123                         intel_ddi_init(dev, PORT_A);
12124
12125                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12126                  * register */
12127                 found = I915_READ(SFUSE_STRAP);
12128
12129                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12130                         intel_ddi_init(dev, PORT_B);
12131                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12132                         intel_ddi_init(dev, PORT_C);
12133                 if (found & SFUSE_STRAP_DDID_DETECTED)
12134                         intel_ddi_init(dev, PORT_D);
12135         } else if (HAS_PCH_SPLIT(dev)) {
12136                 int found;
12137                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12138
12139                 if (has_edp_a(dev))
12140                         intel_dp_init(dev, DP_A, PORT_A);
12141
12142                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12143                         /* PCH SDVOB multiplex with HDMIB */
12144                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12145                         if (!found)
12146                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12147                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12148                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12149                 }
12150
12151                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12152                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12153
12154                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12155                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12156
12157                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12158                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12159
12160                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12161                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12162         } else if (IS_VALLEYVIEW(dev)) {
12163                 /*
12164                  * The DP_DETECTED bit is the latched state of the DDC
12165                  * SDA pin at boot. However since eDP doesn't require DDC
12166                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12167                  * eDP ports may have been muxed to an alternate function.
12168                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12169                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12170                  * detect eDP ports.
12171                  */
12172                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12173                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12174                                         PORT_B);
12175                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12176                     intel_dp_is_edp(dev, PORT_B))
12177                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12178
12179                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12180                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12181                                         PORT_C);
12182                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12183                     intel_dp_is_edp(dev, PORT_C))
12184                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12185
12186                 if (IS_CHERRYVIEW(dev)) {
12187                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12188                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12189                                                 PORT_D);
12190                         /* eDP not supported on port D, so don't check VBT */
12191                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12192                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12193                 }
12194
12195                 intel_dsi_init(dev);
12196         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12197                 bool found = false;
12198
12199                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12200                         DRM_DEBUG_KMS("probing SDVOB\n");
12201                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12202                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12203                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12204                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12205                         }
12206
12207                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12208                                 intel_dp_init(dev, DP_B, PORT_B);
12209                 }
12210
12211                 /* Before G4X SDVOC doesn't have its own detect register */
12212
12213                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12214                         DRM_DEBUG_KMS("probing SDVOC\n");
12215                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12216                 }
12217
12218                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12219
12220                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12221                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12222                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12223                         }
12224                         if (SUPPORTS_INTEGRATED_DP(dev))
12225                                 intel_dp_init(dev, DP_C, PORT_C);
12226                 }
12227
12228                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12229                     (I915_READ(DP_D) & DP_DETECTED))
12230                         intel_dp_init(dev, DP_D, PORT_D);
12231         } else if (IS_GEN2(dev))
12232                 intel_dvo_init(dev);
12233
12234         if (SUPPORTS_TV(dev))
12235                 intel_tv_init(dev);
12236
12237         intel_edp_psr_init(dev);
12238
12239         for_each_intel_encoder(dev, encoder) {
12240                 encoder->base.possible_crtcs = encoder->crtc_mask;
12241                 encoder->base.possible_clones =
12242                         intel_encoder_clones(encoder);
12243         }
12244
12245         intel_init_pch_refclk(dev);
12246
12247         drm_helper_move_panel_connectors_to_head(dev);
12248 }
12249
12250 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12251 {
12252         struct drm_device *dev = fb->dev;
12253         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12254
12255         drm_framebuffer_cleanup(fb);
12256         mutex_lock(&dev->struct_mutex);
12257         WARN_ON(!intel_fb->obj->framebuffer_references--);
12258         drm_gem_object_unreference(&intel_fb->obj->base);
12259         mutex_unlock(&dev->struct_mutex);
12260         kfree(intel_fb);
12261 }
12262
12263 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12264                                                 struct drm_file *file,
12265                                                 unsigned int *handle)
12266 {
12267         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12268         struct drm_i915_gem_object *obj = intel_fb->obj;
12269
12270         return drm_gem_handle_create(file, &obj->base, handle);
12271 }
12272
12273 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12274         .destroy = intel_user_framebuffer_destroy,
12275         .create_handle = intel_user_framebuffer_create_handle,
12276 };
12277
12278 static int intel_framebuffer_init(struct drm_device *dev,
12279                                   struct intel_framebuffer *intel_fb,
12280                                   struct drm_mode_fb_cmd2 *mode_cmd,
12281                                   struct drm_i915_gem_object *obj)
12282 {
12283         int aligned_height;
12284         int pitch_limit;
12285         int ret;
12286
12287         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12288
12289         if (obj->tiling_mode == I915_TILING_Y) {
12290                 DRM_DEBUG("hardware does not support tiling Y\n");
12291                 return -EINVAL;
12292         }
12293
12294         if (mode_cmd->pitches[0] & 63) {
12295                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12296                           mode_cmd->pitches[0]);
12297                 return -EINVAL;
12298         }
12299
12300         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12301                 pitch_limit = 32*1024;
12302         } else if (INTEL_INFO(dev)->gen >= 4) {
12303                 if (obj->tiling_mode)
12304                         pitch_limit = 16*1024;
12305                 else
12306                         pitch_limit = 32*1024;
12307         } else if (INTEL_INFO(dev)->gen >= 3) {
12308                 if (obj->tiling_mode)
12309                         pitch_limit = 8*1024;
12310                 else
12311                         pitch_limit = 16*1024;
12312         } else
12313                 /* XXX DSPC is limited to 4k tiled */
12314                 pitch_limit = 8*1024;
12315
12316         if (mode_cmd->pitches[0] > pitch_limit) {
12317                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12318                           obj->tiling_mode ? "tiled" : "linear",
12319                           mode_cmd->pitches[0], pitch_limit);
12320                 return -EINVAL;
12321         }
12322
12323         if (obj->tiling_mode != I915_TILING_NONE &&
12324             mode_cmd->pitches[0] != obj->stride) {
12325                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12326                           mode_cmd->pitches[0], obj->stride);
12327                 return -EINVAL;
12328         }
12329
12330         /* Reject formats not supported by any plane early. */
12331         switch (mode_cmd->pixel_format) {
12332         case DRM_FORMAT_C8:
12333         case DRM_FORMAT_RGB565:
12334         case DRM_FORMAT_XRGB8888:
12335         case DRM_FORMAT_ARGB8888:
12336                 break;
12337         case DRM_FORMAT_XRGB1555:
12338         case DRM_FORMAT_ARGB1555:
12339                 if (INTEL_INFO(dev)->gen > 3) {
12340                         DRM_DEBUG("unsupported pixel format: %s\n",
12341                                   drm_get_format_name(mode_cmd->pixel_format));
12342                         return -EINVAL;
12343                 }
12344                 break;
12345         case DRM_FORMAT_XBGR8888:
12346         case DRM_FORMAT_ABGR8888:
12347         case DRM_FORMAT_XRGB2101010:
12348         case DRM_FORMAT_ARGB2101010:
12349         case DRM_FORMAT_XBGR2101010:
12350         case DRM_FORMAT_ABGR2101010:
12351                 if (INTEL_INFO(dev)->gen < 4) {
12352                         DRM_DEBUG("unsupported pixel format: %s\n",
12353                                   drm_get_format_name(mode_cmd->pixel_format));
12354                         return -EINVAL;
12355                 }
12356                 break;
12357         case DRM_FORMAT_YUYV:
12358         case DRM_FORMAT_UYVY:
12359         case DRM_FORMAT_YVYU:
12360         case DRM_FORMAT_VYUY:
12361                 if (INTEL_INFO(dev)->gen < 5) {
12362                         DRM_DEBUG("unsupported pixel format: %s\n",
12363                                   drm_get_format_name(mode_cmd->pixel_format));
12364                         return -EINVAL;
12365                 }
12366                 break;
12367         default:
12368                 DRM_DEBUG("unsupported pixel format: %s\n",
12369                           drm_get_format_name(mode_cmd->pixel_format));
12370                 return -EINVAL;
12371         }
12372
12373         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12374         if (mode_cmd->offsets[0] != 0)
12375                 return -EINVAL;
12376
12377         aligned_height = intel_align_height(dev, mode_cmd->height,
12378                                             obj->tiling_mode);
12379         /* FIXME drm helper for size checks (especially planar formats)? */
12380         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12381                 return -EINVAL;
12382
12383         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12384         intel_fb->obj = obj;
12385         intel_fb->obj->framebuffer_references++;
12386
12387         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12388         if (ret) {
12389                 DRM_ERROR("framebuffer init failed %d\n", ret);
12390                 return ret;
12391         }
12392
12393         return 0;
12394 }
12395
12396 static struct drm_framebuffer *
12397 intel_user_framebuffer_create(struct drm_device *dev,
12398                               struct drm_file *filp,
12399                               struct drm_mode_fb_cmd2 *mode_cmd)
12400 {
12401         struct drm_i915_gem_object *obj;
12402
12403         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12404                                                 mode_cmd->handles[0]));
12405         if (&obj->base == NULL)
12406                 return ERR_PTR(-ENOENT);
12407
12408         return intel_framebuffer_create(dev, mode_cmd, obj);
12409 }
12410
12411 #ifndef CONFIG_DRM_I915_FBDEV
12412 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12413 {
12414 }
12415 #endif
12416
12417 static const struct drm_mode_config_funcs intel_mode_funcs = {
12418         .fb_create = intel_user_framebuffer_create,
12419         .output_poll_changed = intel_fbdev_output_poll_changed,
12420 };
12421
12422 /* Set up chip specific display functions */
12423 static void intel_init_display(struct drm_device *dev)
12424 {
12425         struct drm_i915_private *dev_priv = dev->dev_private;
12426
12427         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12428                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12429         else if (IS_CHERRYVIEW(dev))
12430                 dev_priv->display.find_dpll = chv_find_best_dpll;
12431         else if (IS_VALLEYVIEW(dev))
12432                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12433         else if (IS_PINEVIEW(dev))
12434                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12435         else
12436                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12437
12438         if (HAS_DDI(dev)) {
12439                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12440                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12441                 dev_priv->display.crtc_compute_clock =
12442                         haswell_crtc_compute_clock;
12443                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12444                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12445                 dev_priv->display.off = ironlake_crtc_off;
12446                 if (INTEL_INFO(dev)->gen >= 9)
12447                         dev_priv->display.update_primary_plane =
12448                                 skylake_update_primary_plane;
12449                 else
12450                         dev_priv->display.update_primary_plane =
12451                                 ironlake_update_primary_plane;
12452         } else if (HAS_PCH_SPLIT(dev)) {
12453                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12454                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12455                 dev_priv->display.crtc_compute_clock =
12456                         ironlake_crtc_compute_clock;
12457                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12458                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12459                 dev_priv->display.off = ironlake_crtc_off;
12460                 dev_priv->display.update_primary_plane =
12461                         ironlake_update_primary_plane;
12462         } else if (IS_VALLEYVIEW(dev)) {
12463                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12464                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12465                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12466                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12467                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12468                 dev_priv->display.off = i9xx_crtc_off;
12469                 dev_priv->display.update_primary_plane =
12470                         i9xx_update_primary_plane;
12471         } else {
12472                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12473                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12474                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12475                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12476                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12477                 dev_priv->display.off = i9xx_crtc_off;
12478                 dev_priv->display.update_primary_plane =
12479                         i9xx_update_primary_plane;
12480         }
12481
12482         /* Returns the core display clock speed */
12483         if (IS_VALLEYVIEW(dev))
12484                 dev_priv->display.get_display_clock_speed =
12485                         valleyview_get_display_clock_speed;
12486         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12487                 dev_priv->display.get_display_clock_speed =
12488                         i945_get_display_clock_speed;
12489         else if (IS_I915G(dev))
12490                 dev_priv->display.get_display_clock_speed =
12491                         i915_get_display_clock_speed;
12492         else if (IS_I945GM(dev) || IS_845G(dev))
12493                 dev_priv->display.get_display_clock_speed =
12494                         i9xx_misc_get_display_clock_speed;
12495         else if (IS_PINEVIEW(dev))
12496                 dev_priv->display.get_display_clock_speed =
12497                         pnv_get_display_clock_speed;
12498         else if (IS_I915GM(dev))
12499                 dev_priv->display.get_display_clock_speed =
12500                         i915gm_get_display_clock_speed;
12501         else if (IS_I865G(dev))
12502                 dev_priv->display.get_display_clock_speed =
12503                         i865_get_display_clock_speed;
12504         else if (IS_I85X(dev))
12505                 dev_priv->display.get_display_clock_speed =
12506                         i855_get_display_clock_speed;
12507         else /* 852, 830 */
12508                 dev_priv->display.get_display_clock_speed =
12509                         i830_get_display_clock_speed;
12510
12511         if (IS_GEN5(dev)) {
12512                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12513         } else if (IS_GEN6(dev)) {
12514                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12515         } else if (IS_IVYBRIDGE(dev)) {
12516                 /* FIXME: detect B0+ stepping and use auto training */
12517                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12518                 dev_priv->display.modeset_global_resources =
12519                         ivb_modeset_global_resources;
12520         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12521                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12522         } else if (IS_VALLEYVIEW(dev)) {
12523                 dev_priv->display.modeset_global_resources =
12524                         valleyview_modeset_global_resources;
12525         }
12526
12527         /* Default just returns -ENODEV to indicate unsupported */
12528         dev_priv->display.queue_flip = intel_default_queue_flip;
12529
12530         switch (INTEL_INFO(dev)->gen) {
12531         case 2:
12532                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12533                 break;
12534
12535         case 3:
12536                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12537                 break;
12538
12539         case 4:
12540         case 5:
12541                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12542                 break;
12543
12544         case 6:
12545                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12546                 break;
12547         case 7:
12548         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12549                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12550                 break;
12551         }
12552
12553         intel_panel_init_backlight_funcs(dev);
12554
12555         mutex_init(&dev_priv->pps_mutex);
12556 }
12557
12558 /*
12559  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12560  * resume, or other times.  This quirk makes sure that's the case for
12561  * affected systems.
12562  */
12563 static void quirk_pipea_force(struct drm_device *dev)
12564 {
12565         struct drm_i915_private *dev_priv = dev->dev_private;
12566
12567         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12568         DRM_INFO("applying pipe a force quirk\n");
12569 }
12570
12571 static void quirk_pipeb_force(struct drm_device *dev)
12572 {
12573         struct drm_i915_private *dev_priv = dev->dev_private;
12574
12575         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12576         DRM_INFO("applying pipe b force quirk\n");
12577 }
12578
12579 /*
12580  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12581  */
12582 static void quirk_ssc_force_disable(struct drm_device *dev)
12583 {
12584         struct drm_i915_private *dev_priv = dev->dev_private;
12585         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12586         DRM_INFO("applying lvds SSC disable quirk\n");
12587 }
12588
12589 /*
12590  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12591  * brightness value
12592  */
12593 static void quirk_invert_brightness(struct drm_device *dev)
12594 {
12595         struct drm_i915_private *dev_priv = dev->dev_private;
12596         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12597         DRM_INFO("applying inverted panel brightness quirk\n");
12598 }
12599
12600 /* Some VBT's incorrectly indicate no backlight is present */
12601 static void quirk_backlight_present(struct drm_device *dev)
12602 {
12603         struct drm_i915_private *dev_priv = dev->dev_private;
12604         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12605         DRM_INFO("applying backlight present quirk\n");
12606 }
12607
12608 struct intel_quirk {
12609         int device;
12610         int subsystem_vendor;
12611         int subsystem_device;
12612         void (*hook)(struct drm_device *dev);
12613 };
12614
12615 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12616 struct intel_dmi_quirk {
12617         void (*hook)(struct drm_device *dev);
12618         const struct dmi_system_id (*dmi_id_list)[];
12619 };
12620
12621 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12622 {
12623         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12624         return 1;
12625 }
12626
12627 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12628         {
12629                 .dmi_id_list = &(const struct dmi_system_id[]) {
12630                         {
12631                                 .callback = intel_dmi_reverse_brightness,
12632                                 .ident = "NCR Corporation",
12633                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12634                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12635                                 },
12636                         },
12637                         { }  /* terminating entry */
12638                 },
12639                 .hook = quirk_invert_brightness,
12640         },
12641 };
12642
12643 static struct intel_quirk intel_quirks[] = {
12644         /* HP Mini needs pipe A force quirk (LP: #322104) */
12645         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12646
12647         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12648         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12649
12650         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12651         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12652
12653         /* 830 needs to leave pipe A & dpll A up */
12654         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12655
12656         /* 830 needs to leave pipe B & dpll B up */
12657         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12658
12659         /* Lenovo U160 cannot use SSC on LVDS */
12660         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12661
12662         /* Sony Vaio Y cannot use SSC on LVDS */
12663         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12664
12665         /* Acer Aspire 5734Z must invert backlight brightness */
12666         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12667
12668         /* Acer/eMachines G725 */
12669         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12670
12671         /* Acer/eMachines e725 */
12672         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12673
12674         /* Acer/Packard Bell NCL20 */
12675         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12676
12677         /* Acer Aspire 4736Z */
12678         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12679
12680         /* Acer Aspire 5336 */
12681         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12682
12683         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12684         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12685
12686         /* Acer C720 Chromebook (Core i3 4005U) */
12687         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12688
12689         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12690         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12691
12692         /* HP Chromebook 14 (Celeron 2955U) */
12693         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12694 };
12695
12696 static void intel_init_quirks(struct drm_device *dev)
12697 {
12698         struct pci_dev *d = dev->pdev;
12699         int i;
12700
12701         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12702                 struct intel_quirk *q = &intel_quirks[i];
12703
12704                 if (d->device == q->device &&
12705                     (d->subsystem_vendor == q->subsystem_vendor ||
12706                      q->subsystem_vendor == PCI_ANY_ID) &&
12707                     (d->subsystem_device == q->subsystem_device ||
12708                      q->subsystem_device == PCI_ANY_ID))
12709                         q->hook(dev);
12710         }
12711         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12712                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12713                         intel_dmi_quirks[i].hook(dev);
12714         }
12715 }
12716
12717 /* Disable the VGA plane that we never use */
12718 static void i915_disable_vga(struct drm_device *dev)
12719 {
12720         struct drm_i915_private *dev_priv = dev->dev_private;
12721         u8 sr1;
12722         u32 vga_reg = i915_vgacntrl_reg(dev);
12723
12724         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12725         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12726         outb(SR01, VGA_SR_INDEX);
12727         sr1 = inb(VGA_SR_DATA);
12728         outb(sr1 | 1<<5, VGA_SR_DATA);
12729         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12730         udelay(300);
12731
12732         /*
12733          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12734          * from S3 without preserving (some of?) the other bits.
12735          */
12736         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12737         POSTING_READ(vga_reg);
12738 }
12739
12740 void intel_modeset_init_hw(struct drm_device *dev)
12741 {
12742         intel_prepare_ddi(dev);
12743
12744         if (IS_VALLEYVIEW(dev))
12745                 vlv_update_cdclk(dev);
12746
12747         intel_init_clock_gating(dev);
12748
12749         intel_enable_gt_powersave(dev);
12750 }
12751
12752 void intel_modeset_init(struct drm_device *dev)
12753 {
12754         struct drm_i915_private *dev_priv = dev->dev_private;
12755         int sprite, ret;
12756         enum pipe pipe;
12757         struct intel_crtc *crtc;
12758
12759         drm_mode_config_init(dev);
12760
12761         dev->mode_config.min_width = 0;
12762         dev->mode_config.min_height = 0;
12763
12764         dev->mode_config.preferred_depth = 24;
12765         dev->mode_config.prefer_shadow = 1;
12766
12767         dev->mode_config.funcs = &intel_mode_funcs;
12768
12769         intel_init_quirks(dev);
12770
12771         intel_init_pm(dev);
12772
12773         if (INTEL_INFO(dev)->num_pipes == 0)
12774                 return;
12775
12776         intel_init_display(dev);
12777         intel_init_audio(dev);
12778
12779         if (IS_GEN2(dev)) {
12780                 dev->mode_config.max_width = 2048;
12781                 dev->mode_config.max_height = 2048;
12782         } else if (IS_GEN3(dev)) {
12783                 dev->mode_config.max_width = 4096;
12784                 dev->mode_config.max_height = 4096;
12785         } else {
12786                 dev->mode_config.max_width = 8192;
12787                 dev->mode_config.max_height = 8192;
12788         }
12789
12790         if (IS_845G(dev) || IS_I865G(dev)) {
12791                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12792                 dev->mode_config.cursor_height = 1023;
12793         } else if (IS_GEN2(dev)) {
12794                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12795                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12796         } else {
12797                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12798                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12799         }
12800
12801         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12802
12803         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12804                       INTEL_INFO(dev)->num_pipes,
12805                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12806
12807         for_each_pipe(dev_priv, pipe) {
12808                 intel_crtc_init(dev, pipe);
12809                 for_each_sprite(pipe, sprite) {
12810                         ret = intel_plane_init(dev, pipe, sprite);
12811                         if (ret)
12812                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12813                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12814                 }
12815         }
12816
12817         intel_init_dpio(dev);
12818
12819         intel_shared_dpll_init(dev);
12820
12821         /* save the BIOS value before clobbering it */
12822         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12823         /* Just disable it once at startup */
12824         i915_disable_vga(dev);
12825         intel_setup_outputs(dev);
12826
12827         /* Just in case the BIOS is doing something questionable. */
12828         intel_disable_fbc(dev);
12829
12830         drm_modeset_lock_all(dev);
12831         intel_modeset_setup_hw_state(dev, false);
12832         drm_modeset_unlock_all(dev);
12833
12834         for_each_intel_crtc(dev, crtc) {
12835                 if (!crtc->active)
12836                         continue;
12837
12838                 /*
12839                  * Note that reserving the BIOS fb up front prevents us
12840                  * from stuffing other stolen allocations like the ring
12841                  * on top.  This prevents some ugliness at boot time, and
12842                  * can even allow for smooth boot transitions if the BIOS
12843                  * fb is large enough for the active pipe configuration.
12844                  */
12845                 if (dev_priv->display.get_plane_config) {
12846                         dev_priv->display.get_plane_config(crtc,
12847                                                            &crtc->plane_config);
12848                         /*
12849                          * If the fb is shared between multiple heads, we'll
12850                          * just get the first one.
12851                          */
12852                         intel_find_plane_obj(crtc, &crtc->plane_config);
12853                 }
12854         }
12855 }
12856
12857 static void intel_enable_pipe_a(struct drm_device *dev)
12858 {
12859         struct intel_connector *connector;
12860         struct drm_connector *crt = NULL;
12861         struct intel_load_detect_pipe load_detect_temp;
12862         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12863
12864         /* We can't just switch on the pipe A, we need to set things up with a
12865          * proper mode and output configuration. As a gross hack, enable pipe A
12866          * by enabling the load detect pipe once. */
12867         list_for_each_entry(connector,
12868                             &dev->mode_config.connector_list,
12869                             base.head) {
12870                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12871                         crt = &connector->base;
12872                         break;
12873                 }
12874         }
12875
12876         if (!crt)
12877                 return;
12878
12879         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12880                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12881 }
12882
12883 static bool
12884 intel_check_plane_mapping(struct intel_crtc *crtc)
12885 {
12886         struct drm_device *dev = crtc->base.dev;
12887         struct drm_i915_private *dev_priv = dev->dev_private;
12888         u32 reg, val;
12889
12890         if (INTEL_INFO(dev)->num_pipes == 1)
12891                 return true;
12892
12893         reg = DSPCNTR(!crtc->plane);
12894         val = I915_READ(reg);
12895
12896         if ((val & DISPLAY_PLANE_ENABLE) &&
12897             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12898                 return false;
12899
12900         return true;
12901 }
12902
12903 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12904 {
12905         struct drm_device *dev = crtc->base.dev;
12906         struct drm_i915_private *dev_priv = dev->dev_private;
12907         u32 reg;
12908
12909         /* Clear any frame start delays used for debugging left by the BIOS */
12910         reg = PIPECONF(crtc->config.cpu_transcoder);
12911         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12912
12913         /* restore vblank interrupts to correct state */
12914         if (crtc->active) {
12915                 update_scanline_offset(crtc);
12916                 drm_vblank_on(dev, crtc->pipe);
12917         } else
12918                 drm_vblank_off(dev, crtc->pipe);
12919
12920         /* We need to sanitize the plane -> pipe mapping first because this will
12921          * disable the crtc (and hence change the state) if it is wrong. Note
12922          * that gen4+ has a fixed plane -> pipe mapping.  */
12923         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12924                 struct intel_connector *connector;
12925                 bool plane;
12926
12927                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12928                               crtc->base.base.id);
12929
12930                 /* Pipe has the wrong plane attached and the plane is active.
12931                  * Temporarily change the plane mapping and disable everything
12932                  * ...  */
12933                 plane = crtc->plane;
12934                 crtc->plane = !plane;
12935                 crtc->primary_enabled = true;
12936                 dev_priv->display.crtc_disable(&crtc->base);
12937                 crtc->plane = plane;
12938
12939                 /* ... and break all links. */
12940                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12941                                     base.head) {
12942                         if (connector->encoder->base.crtc != &crtc->base)
12943                                 continue;
12944
12945                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12946                         connector->base.encoder = NULL;
12947                 }
12948                 /* multiple connectors may have the same encoder:
12949                  *  handle them and break crtc link separately */
12950                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12951                                     base.head)
12952                         if (connector->encoder->base.crtc == &crtc->base) {
12953                                 connector->encoder->base.crtc = NULL;
12954                                 connector->encoder->connectors_active = false;
12955                         }
12956
12957                 WARN_ON(crtc->active);
12958                 crtc->base.enabled = false;
12959         }
12960
12961         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12962             crtc->pipe == PIPE_A && !crtc->active) {
12963                 /* BIOS forgot to enable pipe A, this mostly happens after
12964                  * resume. Force-enable the pipe to fix this, the update_dpms
12965                  * call below we restore the pipe to the right state, but leave
12966                  * the required bits on. */
12967                 intel_enable_pipe_a(dev);
12968         }
12969
12970         /* Adjust the state of the output pipe according to whether we
12971          * have active connectors/encoders. */
12972         intel_crtc_update_dpms(&crtc->base);
12973
12974         if (crtc->active != crtc->base.enabled) {
12975                 struct intel_encoder *encoder;
12976
12977                 /* This can happen either due to bugs in the get_hw_state
12978                  * functions or because the pipe is force-enabled due to the
12979                  * pipe A quirk. */
12980                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12981                               crtc->base.base.id,
12982                               crtc->base.enabled ? "enabled" : "disabled",
12983                               crtc->active ? "enabled" : "disabled");
12984
12985                 crtc->base.enabled = crtc->active;
12986
12987                 /* Because we only establish the connector -> encoder ->
12988                  * crtc links if something is active, this means the
12989                  * crtc is now deactivated. Break the links. connector
12990                  * -> encoder links are only establish when things are
12991                  *  actually up, hence no need to break them. */
12992                 WARN_ON(crtc->active);
12993
12994                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12995                         WARN_ON(encoder->connectors_active);
12996                         encoder->base.crtc = NULL;
12997                 }
12998         }
12999
13000         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13001                 /*
13002                  * We start out with underrun reporting disabled to avoid races.
13003                  * For correct bookkeeping mark this on active crtcs.
13004                  *
13005                  * Also on gmch platforms we dont have any hardware bits to
13006                  * disable the underrun reporting. Which means we need to start
13007                  * out with underrun reporting disabled also on inactive pipes,
13008                  * since otherwise we'll complain about the garbage we read when
13009                  * e.g. coming up after runtime pm.
13010                  *
13011                  * No protection against concurrent access is required - at
13012                  * worst a fifo underrun happens which also sets this to false.
13013                  */
13014                 crtc->cpu_fifo_underrun_disabled = true;
13015                 crtc->pch_fifo_underrun_disabled = true;
13016         }
13017 }
13018
13019 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13020 {
13021         struct intel_connector *connector;
13022         struct drm_device *dev = encoder->base.dev;
13023
13024         /* We need to check both for a crtc link (meaning that the
13025          * encoder is active and trying to read from a pipe) and the
13026          * pipe itself being active. */
13027         bool has_active_crtc = encoder->base.crtc &&
13028                 to_intel_crtc(encoder->base.crtc)->active;
13029
13030         if (encoder->connectors_active && !has_active_crtc) {
13031                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13032                               encoder->base.base.id,
13033                               encoder->base.name);
13034
13035                 /* Connector is active, but has no active pipe. This is
13036                  * fallout from our resume register restoring. Disable
13037                  * the encoder manually again. */
13038                 if (encoder->base.crtc) {
13039                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13040                                       encoder->base.base.id,
13041                                       encoder->base.name);
13042                         encoder->disable(encoder);
13043                         if (encoder->post_disable)
13044                                 encoder->post_disable(encoder);
13045                 }
13046                 encoder->base.crtc = NULL;
13047                 encoder->connectors_active = false;
13048
13049                 /* Inconsistent output/port/pipe state happens presumably due to
13050                  * a bug in one of the get_hw_state functions. Or someplace else
13051                  * in our code, like the register restore mess on resume. Clamp
13052                  * things to off as a safer default. */
13053                 list_for_each_entry(connector,
13054                                     &dev->mode_config.connector_list,
13055                                     base.head) {
13056                         if (connector->encoder != encoder)
13057                                 continue;
13058                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13059                         connector->base.encoder = NULL;
13060                 }
13061         }
13062         /* Enabled encoders without active connectors will be fixed in
13063          * the crtc fixup. */
13064 }
13065
13066 void i915_redisable_vga_power_on(struct drm_device *dev)
13067 {
13068         struct drm_i915_private *dev_priv = dev->dev_private;
13069         u32 vga_reg = i915_vgacntrl_reg(dev);
13070
13071         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13072                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13073                 i915_disable_vga(dev);
13074         }
13075 }
13076
13077 void i915_redisable_vga(struct drm_device *dev)
13078 {
13079         struct drm_i915_private *dev_priv = dev->dev_private;
13080
13081         /* This function can be called both from intel_modeset_setup_hw_state or
13082          * at a very early point in our resume sequence, where the power well
13083          * structures are not yet restored. Since this function is at a very
13084          * paranoid "someone might have enabled VGA while we were not looking"
13085          * level, just check if the power well is enabled instead of trying to
13086          * follow the "don't touch the power well if we don't need it" policy
13087          * the rest of the driver uses. */
13088         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13089                 return;
13090
13091         i915_redisable_vga_power_on(dev);
13092 }
13093
13094 static bool primary_get_hw_state(struct intel_crtc *crtc)
13095 {
13096         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13097
13098         if (!crtc->active)
13099                 return false;
13100
13101         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13102 }
13103
13104 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13105 {
13106         struct drm_i915_private *dev_priv = dev->dev_private;
13107         enum pipe pipe;
13108         struct intel_crtc *crtc;
13109         struct intel_encoder *encoder;
13110         struct intel_connector *connector;
13111         int i;
13112
13113         for_each_intel_crtc(dev, crtc) {
13114                 memset(&crtc->config, 0, sizeof(crtc->config));
13115
13116                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13117
13118                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13119                                                                  &crtc->config);
13120
13121                 crtc->base.enabled = crtc->active;
13122                 crtc->primary_enabled = primary_get_hw_state(crtc);
13123
13124                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13125                               crtc->base.base.id,
13126                               crtc->active ? "enabled" : "disabled");
13127         }
13128
13129         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13130                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13131
13132                 pll->on = pll->get_hw_state(dev_priv, pll,
13133                                             &pll->config.hw_state);
13134                 pll->active = 0;
13135                 pll->config.crtc_mask = 0;
13136                 for_each_intel_crtc(dev, crtc) {
13137                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13138                                 pll->active++;
13139                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13140                         }
13141                 }
13142
13143                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13144                               pll->name, pll->config.crtc_mask, pll->on);
13145
13146                 if (pll->config.crtc_mask)
13147                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13148         }
13149
13150         for_each_intel_encoder(dev, encoder) {
13151                 pipe = 0;
13152
13153                 if (encoder->get_hw_state(encoder, &pipe)) {
13154                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13155                         encoder->base.crtc = &crtc->base;
13156                         encoder->get_config(encoder, &crtc->config);
13157                 } else {
13158                         encoder->base.crtc = NULL;
13159                 }
13160
13161                 encoder->connectors_active = false;
13162                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13163                               encoder->base.base.id,
13164                               encoder->base.name,
13165                               encoder->base.crtc ? "enabled" : "disabled",
13166                               pipe_name(pipe));
13167         }
13168
13169         list_for_each_entry(connector, &dev->mode_config.connector_list,
13170                             base.head) {
13171                 if (connector->get_hw_state(connector)) {
13172                         connector->base.dpms = DRM_MODE_DPMS_ON;
13173                         connector->encoder->connectors_active = true;
13174                         connector->base.encoder = &connector->encoder->base;
13175                 } else {
13176                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13177                         connector->base.encoder = NULL;
13178                 }
13179                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13180                               connector->base.base.id,
13181                               connector->base.name,
13182                               connector->base.encoder ? "enabled" : "disabled");
13183         }
13184 }
13185
13186 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13187  * and i915 state tracking structures. */
13188 void intel_modeset_setup_hw_state(struct drm_device *dev,
13189                                   bool force_restore)
13190 {
13191         struct drm_i915_private *dev_priv = dev->dev_private;
13192         enum pipe pipe;
13193         struct intel_crtc *crtc;
13194         struct intel_encoder *encoder;
13195         int i;
13196
13197         intel_modeset_readout_hw_state(dev);
13198
13199         /*
13200          * Now that we have the config, copy it to each CRTC struct
13201          * Note that this could go away if we move to using crtc_config
13202          * checking everywhere.
13203          */
13204         for_each_intel_crtc(dev, crtc) {
13205                 if (crtc->active && i915.fastboot) {
13206                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13207                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13208                                       crtc->base.base.id);
13209                         drm_mode_debug_printmodeline(&crtc->base.mode);
13210                 }
13211         }
13212
13213         /* HW state is read out, now we need to sanitize this mess. */
13214         for_each_intel_encoder(dev, encoder) {
13215                 intel_sanitize_encoder(encoder);
13216         }
13217
13218         for_each_pipe(dev_priv, pipe) {
13219                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13220                 intel_sanitize_crtc(crtc);
13221                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13222         }
13223
13224         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13225                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13226
13227                 if (!pll->on || pll->active)
13228                         continue;
13229
13230                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13231
13232                 pll->disable(dev_priv, pll);
13233                 pll->on = false;
13234         }
13235
13236         if (IS_GEN9(dev))
13237                 skl_wm_get_hw_state(dev);
13238         else if (HAS_PCH_SPLIT(dev))
13239                 ilk_wm_get_hw_state(dev);
13240
13241         if (force_restore) {
13242                 i915_redisable_vga(dev);
13243
13244                 /*
13245                  * We need to use raw interfaces for restoring state to avoid
13246                  * checking (bogus) intermediate states.
13247                  */
13248                 for_each_pipe(dev_priv, pipe) {
13249                         struct drm_crtc *crtc =
13250                                 dev_priv->pipe_to_crtc_mapping[pipe];
13251
13252                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13253                                          crtc->primary->fb);
13254                 }
13255         } else {
13256                 intel_modeset_update_staged_output_state(dev);
13257         }
13258
13259         intel_modeset_check_state(dev);
13260 }
13261
13262 void intel_modeset_gem_init(struct drm_device *dev)
13263 {
13264         struct drm_crtc *c;
13265         struct drm_i915_gem_object *obj;
13266
13267         mutex_lock(&dev->struct_mutex);
13268         intel_init_gt_powersave(dev);
13269         mutex_unlock(&dev->struct_mutex);
13270
13271         intel_modeset_init_hw(dev);
13272
13273         intel_setup_overlay(dev);
13274
13275         /*
13276          * Make sure any fbs we allocated at startup are properly
13277          * pinned & fenced.  When we do the allocation it's too early
13278          * for this.
13279          */
13280         mutex_lock(&dev->struct_mutex);
13281         for_each_crtc(dev, c) {
13282                 obj = intel_fb_obj(c->primary->fb);
13283                 if (obj == NULL)
13284                         continue;
13285
13286                 if (intel_pin_and_fence_fb_obj(c->primary,
13287                                                c->primary->fb,
13288                                                NULL)) {
13289                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13290                                   to_intel_crtc(c)->pipe);
13291                         drm_framebuffer_unreference(c->primary->fb);
13292                         c->primary->fb = NULL;
13293                 }
13294         }
13295         mutex_unlock(&dev->struct_mutex);
13296 }
13297
13298 void intel_connector_unregister(struct intel_connector *intel_connector)
13299 {
13300         struct drm_connector *connector = &intel_connector->base;
13301
13302         intel_panel_destroy_backlight(connector);
13303         drm_connector_unregister(connector);
13304 }
13305
13306 void intel_modeset_cleanup(struct drm_device *dev)
13307 {
13308         struct drm_i915_private *dev_priv = dev->dev_private;
13309         struct drm_connector *connector;
13310
13311         /*
13312          * Interrupts and polling as the first thing to avoid creating havoc.
13313          * Too much stuff here (turning of rps, connectors, ...) would
13314          * experience fancy races otherwise.
13315          */
13316         intel_irq_uninstall(dev_priv);
13317
13318         /*
13319          * Due to the hpd irq storm handling the hotplug work can re-arm the
13320          * poll handlers. Hence disable polling after hpd handling is shut down.
13321          */
13322         drm_kms_helper_poll_fini(dev);
13323
13324         mutex_lock(&dev->struct_mutex);
13325
13326         intel_unregister_dsm_handler();
13327
13328         intel_disable_fbc(dev);
13329
13330         intel_disable_gt_powersave(dev);
13331
13332         ironlake_teardown_rc6(dev);
13333
13334         mutex_unlock(&dev->struct_mutex);
13335
13336         /* flush any delayed tasks or pending work */
13337         flush_scheduled_work();
13338
13339         /* destroy the backlight and sysfs files before encoders/connectors */
13340         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13341                 struct intel_connector *intel_connector;
13342
13343                 intel_connector = to_intel_connector(connector);
13344                 intel_connector->unregister(intel_connector);
13345         }
13346
13347         drm_mode_config_cleanup(dev);
13348
13349         intel_cleanup_overlay(dev);
13350
13351         mutex_lock(&dev->struct_mutex);
13352         intel_cleanup_gt_powersave(dev);
13353         mutex_unlock(&dev->struct_mutex);
13354 }
13355
13356 /*
13357  * Return which encoder is currently attached for connector.
13358  */
13359 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13360 {
13361         return &intel_attached_encoder(connector)->base;
13362 }
13363
13364 void intel_connector_attach_encoder(struct intel_connector *connector,
13365                                     struct intel_encoder *encoder)
13366 {
13367         connector->encoder = encoder;
13368         drm_mode_connector_attach_encoder(&connector->base,
13369                                           &encoder->base);
13370 }
13371
13372 /*
13373  * set vga decode state - true == enable VGA decode
13374  */
13375 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13376 {
13377         struct drm_i915_private *dev_priv = dev->dev_private;
13378         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13379         u16 gmch_ctrl;
13380
13381         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13382                 DRM_ERROR("failed to read control word\n");
13383                 return -EIO;
13384         }
13385
13386         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13387                 return 0;
13388
13389         if (state)
13390                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13391         else
13392                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13393
13394         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13395                 DRM_ERROR("failed to write control word\n");
13396                 return -EIO;
13397         }
13398
13399         return 0;
13400 }
13401
13402 struct intel_display_error_state {
13403
13404         u32 power_well_driver;
13405
13406         int num_transcoders;
13407
13408         struct intel_cursor_error_state {
13409                 u32 control;
13410                 u32 position;
13411                 u32 base;
13412                 u32 size;
13413         } cursor[I915_MAX_PIPES];
13414
13415         struct intel_pipe_error_state {
13416                 bool power_domain_on;
13417                 u32 source;
13418                 u32 stat;
13419         } pipe[I915_MAX_PIPES];
13420
13421         struct intel_plane_error_state {
13422                 u32 control;
13423                 u32 stride;
13424                 u32 size;
13425                 u32 pos;
13426                 u32 addr;
13427                 u32 surface;
13428                 u32 tile_offset;
13429         } plane[I915_MAX_PIPES];
13430
13431         struct intel_transcoder_error_state {
13432                 bool power_domain_on;
13433                 enum transcoder cpu_transcoder;
13434
13435                 u32 conf;
13436
13437                 u32 htotal;
13438                 u32 hblank;
13439                 u32 hsync;
13440                 u32 vtotal;
13441                 u32 vblank;
13442                 u32 vsync;
13443         } transcoder[4];
13444 };
13445
13446 struct intel_display_error_state *
13447 intel_display_capture_error_state(struct drm_device *dev)
13448 {
13449         struct drm_i915_private *dev_priv = dev->dev_private;
13450         struct intel_display_error_state *error;
13451         int transcoders[] = {
13452                 TRANSCODER_A,
13453                 TRANSCODER_B,
13454                 TRANSCODER_C,
13455                 TRANSCODER_EDP,
13456         };
13457         int i;
13458
13459         if (INTEL_INFO(dev)->num_pipes == 0)
13460                 return NULL;
13461
13462         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13463         if (error == NULL)
13464                 return NULL;
13465
13466         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13467                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13468
13469         for_each_pipe(dev_priv, i) {
13470                 error->pipe[i].power_domain_on =
13471                         __intel_display_power_is_enabled(dev_priv,
13472                                                          POWER_DOMAIN_PIPE(i));
13473                 if (!error->pipe[i].power_domain_on)
13474                         continue;
13475
13476                 error->cursor[i].control = I915_READ(CURCNTR(i));
13477                 error->cursor[i].position = I915_READ(CURPOS(i));
13478                 error->cursor[i].base = I915_READ(CURBASE(i));
13479
13480                 error->plane[i].control = I915_READ(DSPCNTR(i));
13481                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13482                 if (INTEL_INFO(dev)->gen <= 3) {
13483                         error->plane[i].size = I915_READ(DSPSIZE(i));
13484                         error->plane[i].pos = I915_READ(DSPPOS(i));
13485                 }
13486                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13487                         error->plane[i].addr = I915_READ(DSPADDR(i));
13488                 if (INTEL_INFO(dev)->gen >= 4) {
13489                         error->plane[i].surface = I915_READ(DSPSURF(i));
13490                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13491                 }
13492
13493                 error->pipe[i].source = I915_READ(PIPESRC(i));
13494
13495                 if (HAS_GMCH_DISPLAY(dev))
13496                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13497         }
13498
13499         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13500         if (HAS_DDI(dev_priv->dev))
13501                 error->num_transcoders++; /* Account for eDP. */
13502
13503         for (i = 0; i < error->num_transcoders; i++) {
13504                 enum transcoder cpu_transcoder = transcoders[i];
13505
13506                 error->transcoder[i].power_domain_on =
13507                         __intel_display_power_is_enabled(dev_priv,
13508                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13509                 if (!error->transcoder[i].power_domain_on)
13510                         continue;
13511
13512                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13513
13514                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13515                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13516                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13517                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13518                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13519                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13520                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13521         }
13522
13523         return error;
13524 }
13525
13526 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13527
13528 void
13529 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13530                                 struct drm_device *dev,
13531                                 struct intel_display_error_state *error)
13532 {
13533         struct drm_i915_private *dev_priv = dev->dev_private;
13534         int i;
13535
13536         if (!error)
13537                 return;
13538
13539         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13540         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13541                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13542                            error->power_well_driver);
13543         for_each_pipe(dev_priv, i) {
13544                 err_printf(m, "Pipe [%d]:\n", i);
13545                 err_printf(m, "  Power: %s\n",
13546                            error->pipe[i].power_domain_on ? "on" : "off");
13547                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13548                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13549
13550                 err_printf(m, "Plane [%d]:\n", i);
13551                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13552                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13553                 if (INTEL_INFO(dev)->gen <= 3) {
13554                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13555                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13556                 }
13557                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13558                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13559                 if (INTEL_INFO(dev)->gen >= 4) {
13560                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13561                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13562                 }
13563
13564                 err_printf(m, "Cursor [%d]:\n", i);
13565                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13566                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13567                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13568         }
13569
13570         for (i = 0; i < error->num_transcoders; i++) {
13571                 err_printf(m, "CPU transcoder: %c\n",
13572                            transcoder_name(error->transcoder[i].cpu_transcoder));
13573                 err_printf(m, "  Power: %s\n",
13574                            error->transcoder[i].power_domain_on ? "on" : "off");
13575                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13576                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13577                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13578                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13579                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13580                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13581                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13582         }
13583 }
13584
13585 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13586 {
13587         struct intel_crtc *crtc;
13588
13589         for_each_intel_crtc(dev, crtc) {
13590                 struct intel_unpin_work *work;
13591
13592                 spin_lock_irq(&dev->event_lock);
13593
13594                 work = crtc->unpin_work;
13595
13596                 if (work && work->event &&
13597                     work->event->base.file_priv == file) {
13598                         kfree(work->event);
13599                         work->event = NULL;
13600                 }
13601
13602                 spin_unlock_irq(&dev->event_lock);
13603         }
13604 }