drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 static int
 173 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 174 {
 175         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 176 }
 177
 178 static int
 179 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 180 {
 181         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 182                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 183 }
 184
 185 static int
 186 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 187 {
 188         uint32_t clkcfg;
 189
 190         /* hrawclock is 1/4 the FSB frequency */
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100000;
 195         case CLKCFG_FSB_533:
 196                 return 133333;
 197         case CLKCFG_FSB_667:
 198                 return 166667;
 199         case CLKCFG_FSB_800:
 200                 return 200000;
 201         case CLKCFG_FSB_1067:
 202                 return 266667;
 203         case CLKCFG_FSB_1333:
 204                 return 333333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400000;
 209         default:
 210                 return 133333;
 211         }
 212 }
 213
 214 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (HAS_PCH_SPLIT(dev_priv))
 217                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 218         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 219                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 220         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 221                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 222         else
 223                 return; /* no rawclk on other platforms, or no need to know it */
 224
 225         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 226 }
 227
 228 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 229 {
 230         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 231                 return;
 232
 233         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 234                                                       CCK_CZ_CLOCK_CONTROL);
 235
 236         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 237 }
 238
 239 static inline u32 /* units of 100MHz */
 240 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 241                     const struct intel_crtc_state *pipe_config)
 242 {
 243         if (HAS_DDI(dev_priv))
 244                 return pipe_config->port_clock; /* SPLL */
 245         else if (IS_GEN5(dev_priv))
 246                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 247         else
 248                 return 270000;
 249 }
 250
 251 static const intel_limit_t intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const intel_limit_t intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const intel_limit_t intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const intel_limit_t intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const intel_limit_t intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const intel_limit_t intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const intel_limit_t intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const intel_limit_t intel_limits_pineview_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const intel_limit_t intel_limits_ironlake_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const intel_limit_t intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const intel_limit_t intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const intel_limit_t intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 static bool
 517 needs_modeset(struct drm_crtc_state *state)
 518 {
 519         return drm_atomic_crtc_needs_modeset(state);
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe is of the specified type
 524  */
 525 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 526 {
 527         struct drm_device *dev = crtc->base.dev;
 528         struct intel_encoder *encoder;
 529
 530         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 531                 if (encoder->type == type)
 532                         return true;
 533
 534         return false;
 535 }
 536
 537 /**
 538  * Returns whether any output on the specified pipe will have the specified
 539  * type after a staged modeset is complete, i.e., the same as
 540  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 541  * encoder->crtc.
 542  */
 543 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 544                                       int type)
 545 {
 546         struct drm_atomic_state *state = crtc_state->base.state;
 547         struct drm_connector *connector;
 548         struct drm_connector_state *connector_state;
 549         struct intel_encoder *encoder;
 550         int i, num_connectors = 0;
 551
 552         for_each_connector_in_state(state, connector, connector_state, i) {
 553                 if (connector_state->crtc != crtc_state->base.crtc)
 554                         continue;
 555
 556                 num_connectors++;
 557
 558                 encoder = to_intel_encoder(connector_state->best_encoder);
 559                 if (encoder->type == type)
 560                         return true;
 561         }
 562
 563         WARN_ON(num_connectors == 0);
 564
 565         return false;
 566 }
 567
 568 static const intel_limit_t *
 569 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 570 {
 571         struct drm_device *dev = crtc_state->base.crtc->dev;
 572         const intel_limit_t *limit;
 573
 574         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 575                 if (intel_is_dual_link_lvds(dev)) {
 576                         if (refclk == 100000)
 577                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 578                         else
 579                                 limit = &intel_limits_ironlake_dual_lvds;
 580                 } else {
 581                         if (refclk == 100000)
 582                                 limit = &intel_limits_ironlake_single_lvds_100m;
 583                         else
 584                                 limit = &intel_limits_ironlake_single_lvds;
 585                 }
 586         } else
 587                 limit = &intel_limits_ironlake_dac;
 588
 589         return limit;
 590 }
 591
 592 static const intel_limit_t *
 593 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 594 {
 595         struct drm_device *dev = crtc_state->base.crtc->dev;
 596         const intel_limit_t *limit;
 597
 598         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 599                 if (intel_is_dual_link_lvds(dev))
 600                         limit = &intel_limits_g4x_dual_channel_lvds;
 601                 else
 602                         limit = &intel_limits_g4x_single_channel_lvds;
 603         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 604                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 605                 limit = &intel_limits_g4x_hdmi;
 606         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 607                 limit = &intel_limits_g4x_sdvo;
 608         } else /* The option is for other outputs */
 609                 limit = &intel_limits_i9xx_sdvo;
 610
 611         return limit;
 612 }
 613
 614 static const intel_limit_t *
 615 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 616 {
 617         struct drm_device *dev = crtc_state->base.crtc->dev;
 618         const intel_limit_t *limit;
 619
 620         if (IS_BROXTON(dev))
 621                 limit = &intel_limits_bxt;
 622         else if (HAS_PCH_SPLIT(dev))
 623                 limit = intel_ironlake_limit(crtc_state, refclk);
 624         else if (IS_G4X(dev)) {
 625                 limit = intel_g4x_limit(crtc_state);
 626         } else if (IS_PINEVIEW(dev)) {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_pineview_lvds;
 629                 else
 630                         limit = &intel_limits_pineview_sdvo;
 631         } else if (IS_CHERRYVIEW(dev)) {
 632                 limit = &intel_limits_chv;
 633         } else if (IS_VALLEYVIEW(dev)) {
 634                 limit = &intel_limits_vlv;
 635         } else if (!IS_GEN2(dev)) {
 636                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 637                         limit = &intel_limits_i9xx_lvds;
 638                 else
 639                         limit = &intel_limits_i9xx_sdvo;
 640         } else {
 641                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 642                         limit = &intel_limits_i8xx_lvds;
 643                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 644                         limit = &intel_limits_i8xx_dvo;
 645                 else
 646                         limit = &intel_limits_i8xx_dac;
 647         }
 648         return limit;
 649 }
 650
 651 /*
 652  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 653  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 654  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 655  * The helpers' return value is the rate of the clock that is fed to the
 656  * display engine's pipe which can be the above fast dot clock rate or a
 657  * divided-down version of it.
 658  */
 659 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 660 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 661 {
 662         clock->m = clock->m2 + 2;
 663         clock->p = clock->p1 * clock->p2;
 664         if (WARN_ON(clock->n == 0 || clock->p == 0))
 665                 return 0;
 666         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 667         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 668
 669         return clock->dot;
 670 }
 671
 672 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 673 {
 674         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 675 }
 676
 677 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 678 {
 679         clock->m = i9xx_dpll_compute_m(clock);
 680         clock->p = clock->p1 * clock->p2;
 681         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 682                 return 0;
 683         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 684         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 685
 686         return clock->dot;
 687 }
 688
 689 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 690 {
 691         clock->m = clock->m1 * clock->m2;
 692         clock->p = clock->p1 * clock->p2;
 693         if (WARN_ON(clock->n == 0 || clock->p == 0))
 694                 return 0;
 695         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 696         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 697
 698         return clock->dot / 5;
 699 }
 700
 701 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 702 {
 703         clock->m = clock->m1 * clock->m2;
 704         clock->p = clock->p1 * clock->p2;
 705         if (WARN_ON(clock->n == 0 || clock->p == 0))
 706                 return 0;
 707         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 708                         clock->n << 22);
 709         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 710
 711         return clock->dot / 5;
 712 }
 713
 714 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 715 /**
 716  * Returns whether the given set of divisors are valid for a given refclk with
 717  * the given connectors.
 718  */
 719
 720 static bool intel_PLL_is_valid(struct drm_device *dev,
 721                                const intel_limit_t *limit,
 722                                const intel_clock_t *clock)
 723 {
 724         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 725                 INTELPllInvalid("n out of range\n");
 726         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 727                 INTELPllInvalid("p1 out of range\n");
 728         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 729                 INTELPllInvalid("m2 out of range\n");
 730         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 731                 INTELPllInvalid("m1 out of range\n");
 732
 733         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 734             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 735                 if (clock->m1 <= clock->m2)
 736                         INTELPllInvalid("m1 <= m2\n");
 737
 738         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 739                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 740                         INTELPllInvalid("p out of range\n");
 741                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 742                         INTELPllInvalid("m out of range\n");
 743         }
 744
 745         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 746                 INTELPllInvalid("vco out of range\n");
 747         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 748          * connector, etc., rather than just a single range.
 749          */
 750         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 751                 INTELPllInvalid("dot out of range\n");
 752
 753         return true;
 754 }
 755
 756 static int
 757 i9xx_select_p2_div(const intel_limit_t *limit,
 758                    const struct intel_crtc_state *crtc_state,
 759                    int target)
 760 {
 761         struct drm_device *dev = crtc_state->base.crtc->dev;
 762
 763         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 764                 /*
 765                  * For LVDS just rely on its current settings for dual-channel.
 766                  * We haven't figured out how to reliably set up different
 767                  * single/dual channel state, if we even can.
 768                  */
 769                 if (intel_is_dual_link_lvds(dev))
 770                         return limit->p2.p2_fast;
 771                 else
 772                         return limit->p2.p2_slow;
 773         } else {
 774                 if (target < limit->p2.dot_limit)
 775                         return limit->p2.p2_slow;
 776                 else
 777                         return limit->p2.p2_fast;
 778         }
 779 }
 780
 781 static bool
 782 i9xx_find_best_dpll(const intel_limit_t *limit,
 783                     struct intel_crtc_state *crtc_state,
 784                     int target, int refclk, intel_clock_t *match_clock,
 785                     intel_clock_t *best_clock)
 786 {
 787         struct drm_device *dev = crtc_state->base.crtc->dev;
 788         intel_clock_t clock;
 789         int err = target;
 790
 791         memset(best_clock, 0, sizeof(*best_clock));
 792
 793         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 794
 795         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 796              clock.m1++) {
 797                 for (clock.m2 = limit->m2.min;
 798                      clock.m2 <= limit->m2.max; clock.m2++) {
 799                         if (clock.m2 >= clock.m1)
 800                                 break;
 801                         for (clock.n = limit->n.min;
 802                              clock.n <= limit->n.max; clock.n++) {
 803                                 for (clock.p1 = limit->p1.min;
 804                                         clock.p1 <= limit->p1.max; clock.p1++) {
 805                                         int this_err;
 806
 807                                         i9xx_calc_dpll_params(refclk, &clock);
 808                                         if (!intel_PLL_is_valid(dev, limit,
 809                                                                 &clock))
 810                                                 continue;
 811                                         if (match_clock &&
 812                                             clock.p != match_clock->p)
 813                                                 continue;
 814
 815                                         this_err = abs(clock.dot - target);
 816                                         if (this_err < err) {
 817                                                 *best_clock = clock;
 818                                                 err = this_err;
 819                                         }
 820                                 }
 821                         }
 822                 }
 823         }
 824
 825         return (err != target);
 826 }
 827
 828 static bool
 829 pnv_find_best_dpll(const intel_limit_t *limit,
 830                    struct intel_crtc_state *crtc_state,
 831                    int target, int refclk, intel_clock_t *match_clock,
 832                    intel_clock_t *best_clock)
 833 {
 834         struct drm_device *dev = crtc_state->base.crtc->dev;
 835         intel_clock_t clock;
 836         int err = target;
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         for (clock.n = limit->n.min;
 847                              clock.n <= limit->n.max; clock.n++) {
 848                                 for (clock.p1 = limit->p1.min;
 849                                         clock.p1 <= limit->p1.max; clock.p1++) {
 850                                         int this_err;
 851
 852                                         pnv_calc_dpll_params(refclk, &clock);
 853                                         if (!intel_PLL_is_valid(dev, limit,
 854                                                                 &clock))
 855                                                 continue;
 856                                         if (match_clock &&
 857                                             clock.p != match_clock->p)
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 g4x_find_best_dpll(const intel_limit_t *limit,
 875                    struct intel_crtc_state *crtc_state,
 876                    int target, int refclk, intel_clock_t *match_clock,
 877                    intel_clock_t *best_clock)
 878 {
 879         struct drm_device *dev = crtc_state->base.crtc->dev;
 880         intel_clock_t clock;
 881         int max_n;
 882         bool found = false;
 883         /* approximately equals target * 0.00585 */
 884         int err_most = (target >> 8) + (target >> 9);
 885
 886         memset(best_clock, 0, sizeof(*best_clock));
 887
 888         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 889
 890         max_n = limit->n.max;
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 893                 /* based on hardware requirement, prefere larger m1,m2 */
 894                 for (clock.m1 = limit->m1.max;
 895                      clock.m1 >= limit->m1.min; clock.m1--) {
 896                         for (clock.m2 = limit->m2.max;
 897                              clock.m2 >= limit->m2.min; clock.m2--) {
 898                                 for (clock.p1 = limit->p1.max;
 899                                      clock.p1 >= limit->p1.min; clock.p1--) {
 900                                         int this_err;
 901
 902                                         i9xx_calc_dpll_params(refclk, &clock);
 903                                         if (!intel_PLL_is_valid(dev, limit,
 904                                                                 &clock))
 905                                                 continue;
 906
 907                                         this_err = abs(clock.dot - target);
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918         return found;
 919 }
 920
 921 /*
 922  * Check if the calculated PLL configuration is more optimal compared to the
 923  * best configuration and error found so far. Return the calculated error.
 924  */
 925 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 926                                const intel_clock_t *calculated_clock,
 927                                const intel_clock_t *best_clock,
 928                                unsigned int best_error_ppm,
 929                                unsigned int *error_ppm)
 930 {
 931         /*
 932          * For CHV ignore the error and consider only the P value.
 933          * Prefer a bigger P value based on HW requirements.
 934          */
 935         if (IS_CHERRYVIEW(dev)) {
 936                 *error_ppm = 0;
 937
 938                 return calculated_clock->p > best_clock->p;
 939         }
 940
 941         if (WARN_ON_ONCE(!target_freq))
 942                 return false;
 943
 944         *error_ppm = div_u64(1000000ULL *
 945                                 abs(target_freq - calculated_clock->dot),
 946                              target_freq);
 947         /*
 948          * Prefer a better P value over a better (smaller) error if the error
 949          * is small. Ensure this preference for future configurations too by
 950          * setting the error to 0.
 951          */
 952         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 953                 *error_ppm = 0;
 954
 955                 return true;
 956         }
 957
 958         return *error_ppm + 10 < best_error_ppm;
 959 }
 960
 961 static bool
 962 vlv_find_best_dpll(const intel_limit_t *limit,
 963                    struct intel_crtc_state *crtc_state,
 964                    int target, int refclk, intel_clock_t *match_clock,
 965                    intel_clock_t *best_clock)
 966 {
 967         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 968         struct drm_device *dev = crtc->base.dev;
 969         intel_clock_t clock;
 970         unsigned int bestppm = 1000000;
 971         /* min update 19.2 MHz */
 972         int max_n = min(limit->n.max, refclk / 19200);
 973         bool found = false;
 974
 975         target *= 5; /* fast clock */
 976
 977         memset(best_clock, 0, sizeof(*best_clock));
 978
 979         /* based on hardware requirement, prefer smaller n to precision */
 980         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 981                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 982                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 983                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 984                                 clock.p = clock.p1 * clock.p2;
 985                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 986                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 987                                         unsigned int ppm;
 988
 989                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 990                                                                      refclk * clock.m1);
 991
 992                                         vlv_calc_dpll_params(refclk, &clock);
 993
 994                                         if (!intel_PLL_is_valid(dev, limit,
 995                                                                 &clock))
 996                                                 continue;
 997
 998                                         if (!vlv_PLL_is_optimal(dev, target,
 999                                                                 &clock,
1000                                                                 best_clock,
1001                                                                 bestppm, &ppm))
1002                                                 continue;
1003
1004                                         *best_clock = clock;
1005                                         bestppm = ppm;
1006                                         found = true;
1007                                 }
1008                         }
1009                 }
1010         }
1011
1012         return found;
1013 }
1014
1015 static bool
1016 chv_find_best_dpll(const intel_limit_t *limit,
1017                    struct intel_crtc_state *crtc_state,
1018                    int target, int refclk, intel_clock_t *match_clock,
1019                    intel_clock_t *best_clock)
1020 {
1021         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1022         struct drm_device *dev = crtc->base.dev;
1023         unsigned int best_error_ppm;
1024         intel_clock_t clock;
1025         uint64_t m2;
1026         int found = false;
1027
1028         memset(best_clock, 0, sizeof(*best_clock));
1029         best_error_ppm = 1000000;
1030
1031         /*
1032          * Based on hardware doc, the n always set to 1, and m1 always
1033          * set to 2.  If requires to support 200Mhz refclk, we need to
1034          * revisit this because n may not 1 anymore.
1035          */
1036         clock.n = 1, clock.m1 = 2;
1037         target *= 5;    /* fast clock */
1038
1039         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1040                 for (clock.p2 = limit->p2.p2_fast;
1041                                 clock.p2 >= limit->p2.p2_slow;
1042                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1043                         unsigned int error_ppm;
1044
1045                         clock.p = clock.p1 * clock.p2;
1046
1047                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1048                                         clock.n) << 22, refclk * clock.m1);
1049
1050                         if (m2 > INT_MAX/clock.m1)
1051                                 continue;
1052
1053                         clock.m2 = m2;
1054
1055                         chv_calc_dpll_params(refclk, &clock);
1056
1057                         if (!intel_PLL_is_valid(dev, limit, &clock))
1058                                 continue;
1059
1060                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1061                                                 best_error_ppm, &error_ppm))
1062                                 continue;
1063
1064                         *best_clock = clock;
1065                         best_error_ppm = error_ppm;
1066                         found = true;
1067                 }
1068         }
1069
1070         return found;
1071 }
1072
1073 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1074                         intel_clock_t *best_clock)
1075 {
1076         int refclk = i9xx_get_refclk(crtc_state, 0);
1077
1078         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1079                                   target_clock, refclk, NULL, best_clock);
1080 }
1081
1082 bool intel_crtc_active(struct drm_crtc *crtc)
1083 {
1084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1085
1086         /* Be paranoid as we can arrive here with only partial
1087          * state retrieved from the hardware during setup.
1088          *
1089          * We can ditch the adjusted_mode.crtc_clock check as soon
1090          * as Haswell has gained clock readout/fastboot support.
1091          *
1092          * We can ditch the crtc->primary->fb check as soon as we can
1093          * properly reconstruct framebuffers.
1094          *
1095          * FIXME: The intel_crtc->active here should be switched to
1096          * crtc->state->active once we have proper CRTC states wired up
1097          * for atomic.
1098          */
1099         return intel_crtc->active && crtc->primary->state->fb &&
1100                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1101 }
1102
1103 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1104                                              enum pipe pipe)
1105 {
1106         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1108
1109         return intel_crtc->config->cpu_transcoder;
1110 }
1111
1112 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         i915_reg_t reg = PIPEDSL(pipe);
1116         u32 line1, line2;
1117         u32 line_mask;
1118
1119         if (IS_GEN2(dev))
1120                 line_mask = DSL_LINEMASK_GEN2;
1121         else
1122                 line_mask = DSL_LINEMASK_GEN3;
1123
1124         line1 = I915_READ(reg) & line_mask;
1125         msleep(5);
1126         line2 = I915_READ(reg) & line_mask;
1127
1128         return line1 == line2;
1129 }
1130
1131 /*
1132  * intel_wait_for_pipe_off - wait for pipe to turn off
1133  * @crtc: crtc whose pipe to wait for
1134  *
1135  * After disabling a pipe, we can't wait for vblank in the usual way,
1136  * spinning on the vblank interrupt status bit, since we won't actually
1137  * see an interrupt when the pipe is disabled.
1138  *
1139  * On Gen4 and above:
1140  *   wait for the pipe register state bit to turn off
1141  *
1142  * Otherwise:
1143  *   wait for the display line value to settle (it usually
1144  *   ends up stopping at the start of the next frame).
1145  *
1146  */
1147 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1148 {
1149         struct drm_device *dev = crtc->base.dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1152         enum pipe pipe = crtc->pipe;
1153
1154         if (INTEL_INFO(dev)->gen >= 4) {
1155                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1156
1157                 /* Wait for the Pipe State to go off */
1158                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1159                              100))
1160                         WARN(1, "pipe_off wait timed out\n");
1161         } else {
1162                 /* Wait for the display line to settle */
1163                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1164                         WARN(1, "pipe_off wait timed out\n");
1165         }
1166 }
1167
1168 /* Only for pre-ILK configs */
1169 void assert_pll(struct drm_i915_private *dev_priv,
1170                 enum pipe pipe, bool state)
1171 {
1172         u32 val;
1173         bool cur_state;
1174
1175         val = I915_READ(DPLL(pipe));
1176         cur_state = !!(val & DPLL_VCO_ENABLE);
1177         I915_STATE_WARN(cur_state != state,
1178              "PLL state assertion failure (expected %s, current %s)\n",
1179                         onoff(state), onoff(cur_state));
1180 }
1181
1182 /* XXX: the dsi pll is shared between MIPI DSI ports */
1183 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1184 {
1185         u32 val;
1186         bool cur_state;
1187
1188         mutex_lock(&dev_priv->sb_lock);
1189         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1190         mutex_unlock(&dev_priv->sb_lock);
1191
1192         cur_state = val & DSI_PLL_VCO_EN;
1193         I915_STATE_WARN(cur_state != state,
1194              "DSI PLL state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1198 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1199
1200 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1201                           enum pipe pipe, bool state)
1202 {
1203         bool cur_state;
1204         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205                                                                       pipe);
1206
1207         if (HAS_DDI(dev_priv->dev)) {
1208                 /* DDI does not have a specific FDI_TX register */
1209                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1210                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1211         } else {
1212                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1213                 cur_state = !!(val & FDI_TX_ENABLE);
1214         }
1215         I915_STATE_WARN(cur_state != state,
1216              "FDI TX state assertion failure (expected %s, current %s)\n",
1217                         onoff(state), onoff(cur_state));
1218 }
1219 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1220 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1221
1222 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1223                           enum pipe pipe, bool state)
1224 {
1225         u32 val;
1226         bool cur_state;
1227
1228         val = I915_READ(FDI_RX_CTL(pipe));
1229         cur_state = !!(val & FDI_RX_ENABLE);
1230         I915_STATE_WARN(cur_state != state,
1231              "FDI RX state assertion failure (expected %s, current %s)\n",
1232                         onoff(state), onoff(cur_state));
1233 }
1234 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1235 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1236
1237 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1238                                       enum pipe pipe)
1239 {
1240         u32 val;
1241
1242         /* ILK FDI PLL is always enabled */
1243         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1244                 return;
1245
1246         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1247         if (HAS_DDI(dev_priv->dev))
1248                 return;
1249
1250         val = I915_READ(FDI_TX_CTL(pipe));
1251         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1252 }
1253
1254 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1255                        enum pipe pipe, bool state)
1256 {
1257         u32 val;
1258         bool cur_state;
1259
1260         val = I915_READ(FDI_RX_CTL(pipe));
1261         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1262         I915_STATE_WARN(cur_state != state,
1263              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1264                         onoff(state), onoff(cur_state));
1265 }
1266
1267 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1268                            enum pipe pipe)
1269 {
1270         struct drm_device *dev = dev_priv->dev;
1271         i915_reg_t pp_reg;
1272         u32 val;
1273         enum pipe panel_pipe = PIPE_A;
1274         bool locked = true;
1275
1276         if (WARN_ON(HAS_DDI(dev)))
1277                 return;
1278
1279         if (HAS_PCH_SPLIT(dev)) {
1280                 u32 port_sel;
1281
1282                 pp_reg = PCH_PP_CONTROL;
1283                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284
1285                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1286                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1287                         panel_pipe = PIPE_B;
1288                 /* XXX: else fix for eDP */
1289         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1290                 /* presumably write lock depends on pipe, not port select */
1291                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1292                 panel_pipe = pipe;
1293         } else {
1294                 pp_reg = PP_CONTROL;
1295                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1296                         panel_pipe = PIPE_B;
1297         }
1298
1299         val = I915_READ(pp_reg);
1300         if (!(val & PANEL_POWER_ON) ||
1301             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1302                 locked = false;
1303
1304         I915_STATE_WARN(panel_pipe == pipe && locked,
1305              "panel assertion failure, pipe %c regs locked\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static void assert_cursor(struct drm_i915_private *dev_priv,
1310                           enum pipe pipe, bool state)
1311 {
1312         struct drm_device *dev = dev_priv->dev;
1313         bool cur_state;
1314
1315         if (IS_845G(dev) || IS_I865G(dev))
1316                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1317         else
1318                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1319
1320         I915_STATE_WARN(cur_state != state,
1321              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1322                         pipe_name(pipe), onoff(state), onoff(cur_state));
1323 }
1324 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1325 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326
1327 void assert_pipe(struct drm_i915_private *dev_priv,
1328                  enum pipe pipe, bool state)
1329 {
1330         bool cur_state;
1331         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1332                                                                       pipe);
1333         enum intel_display_power_domain power_domain;
1334
1335         /* if we need the pipe quirk it must be always on */
1336         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338                 state = true;
1339
1340         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1341         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1342                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1343                 cur_state = !!(val & PIPECONF_ENABLE);
1344
1345                 intel_display_power_put(dev_priv, power_domain);
1346         } else {
1347                 cur_state = false;
1348         }
1349
1350         I915_STATE_WARN(cur_state != state,
1351              "pipe %c assertion failure (expected %s, current %s)\n",
1352                         pipe_name(pipe), onoff(state), onoff(cur_state));
1353 }
1354
1355 static void assert_plane(struct drm_i915_private *dev_priv,
1356                          enum plane plane, bool state)
1357 {
1358         u32 val;
1359         bool cur_state;
1360
1361         val = I915_READ(DSPCNTR(plane));
1362         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1363         I915_STATE_WARN(cur_state != state,
1364              "plane %c assertion failure (expected %s, current %s)\n",
1365                         plane_name(plane), onoff(state), onoff(cur_state));
1366 }
1367
1368 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1369 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1370
1371 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe)
1373 {
1374         struct drm_device *dev = dev_priv->dev;
1375         int i;
1376
1377         /* Primary planes are fixed to pipes on gen4+ */
1378         if (INTEL_INFO(dev)->gen >= 4) {
1379                 u32 val = I915_READ(DSPCNTR(pipe));
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 u32 val = I915_READ(DSPCNTR(i));
1389                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390                         DISPPLANE_SEL_PIPE_SHIFT;
1391                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393                      plane_name(i), pipe_name(pipe));
1394         }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398                                     enum pipe pipe)
1399 {
1400         struct drm_device *dev = dev_priv->dev;
1401         int sprite;
1402
1403         if (INTEL_INFO(dev)->gen >= 9) {
1404                 for_each_sprite(dev_priv, pipe, sprite) {
1405                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1406                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1407                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1408                              sprite, pipe_name(pipe));
1409                 }
1410         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1411                 for_each_sprite(dev_priv, pipe, sprite) {
1412                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1413                         I915_STATE_WARN(val & SP_ENABLE,
1414                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415                              sprite_name(pipe, sprite), pipe_name(pipe));
1416                 }
1417         } else if (INTEL_INFO(dev)->gen >= 7) {
1418                 u32 val = I915_READ(SPRCTL(pipe));
1419                 I915_STATE_WARN(val & SPRITE_ENABLE,
1420                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1421                      plane_name(pipe), pipe_name(pipe));
1422         } else if (INTEL_INFO(dev)->gen >= 5) {
1423                 u32 val = I915_READ(DVSCNTR(pipe));
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1437                                     enum pipe pipe)
1438 {
1439         u32 val;
1440         bool enabled;
1441
1442         val = I915_READ(PCH_TRANSCONF(pipe));
1443         enabled = !!(val & TRANS_ENABLE);
1444         I915_STATE_WARN(enabled,
1445              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1446              pipe_name(pipe));
1447 }
1448
1449 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1450                             enum pipe pipe, u32 port_sel, u32 val)
1451 {
1452         if ((val & DP_PORT_EN) == 0)
1453                 return false;
1454
1455         if (HAS_PCH_CPT(dev_priv->dev)) {
1456                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1457                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1458                         return false;
1459         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1460                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1461                         return false;
1462         } else {
1463                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1464                         return false;
1465         }
1466         return true;
1467 }
1468
1469 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1470                               enum pipe pipe, u32 val)
1471 {
1472         if ((val & SDVO_ENABLE) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1477                         return false;
1478         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1479                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1480                         return false;
1481         } else {
1482                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1483                         return false;
1484         }
1485         return true;
1486 }
1487
1488 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1489                               enum pipe pipe, u32 val)
1490 {
1491         if ((val & LVDS_PORT_EN) == 0)
1492                 return false;
1493
1494         if (HAS_PCH_CPT(dev_priv->dev)) {
1495                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & ADPA_DAC_ENABLE) == 0)
1508                 return false;
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511                         return false;
1512         } else {
1513                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1514                         return false;
1515         }
1516         return true;
1517 }
1518
1519 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1520                                    enum pipe pipe, i915_reg_t reg,
1521                                    u32 port_sel)
1522 {
1523         u32 val = I915_READ(reg);
1524         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1525              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1526              i915_mmio_reg_offset(reg), pipe_name(pipe));
1527
1528         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1529              && (val & DP_PIPEB_SELECT),
1530              "IBX PCH dp port still using transcoder B\n");
1531 }
1532
1533 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1534                                      enum pipe pipe, i915_reg_t reg)
1535 {
1536         u32 val = I915_READ(reg);
1537         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1538              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1539              i915_mmio_reg_offset(reg), pipe_name(pipe));
1540
1541         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1542              && (val & SDVO_PIPE_B_SELECT),
1543              "IBX PCH hdmi port still using transcoder B\n");
1544 }
1545
1546 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1547                                       enum pipe pipe)
1548 {
1549         u32 val;
1550
1551         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1552         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1553         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1554
1555         val = I915_READ(PCH_ADPA);
1556         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1557              "PCH VGA enabled on transcoder %c, should be disabled\n",
1558              pipe_name(pipe));
1559
1560         val = I915_READ(PCH_LVDS);
1561         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1562              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1563              pipe_name(pipe));
1564
1565         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1566         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1567         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1568 }
1569
1570 static void vlv_enable_pll(struct intel_crtc *crtc,
1571                            const struct intel_crtc_state *pipe_config)
1572 {
1573         struct drm_device *dev = crtc->base.dev;
1574         struct drm_i915_private *dev_priv = dev->dev_private;
1575         i915_reg_t reg = DPLL(crtc->pipe);
1576         u32 dpll = pipe_config->dpll_hw_state.dpll;
1577
1578         assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580         /* PLL is protected by panel, make sure we can write it */
1581         if (IS_MOBILE(dev_priv->dev))
1582                 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584         I915_WRITE(reg, dpll);
1585         POSTING_READ(reg);
1586         udelay(150);
1587
1588         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1589                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1590
1591         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1592         POSTING_READ(DPLL_MD(crtc->pipe));
1593
1594         /* We do this three times for luck */
1595         I915_WRITE(reg, dpll);
1596         POSTING_READ(reg);
1597         udelay(150); /* wait for warmup */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604 }
1605
1606 static void chv_enable_pll(struct intel_crtc *crtc,
1607                            const struct intel_crtc_state *pipe_config)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int pipe = crtc->pipe;
1612         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1613         u32 tmp;
1614
1615         assert_pipe_disabled(dev_priv, crtc->pipe);
1616
1617         mutex_lock(&dev_priv->sb_lock);
1618
1619         /* Enable back the 10bit clock to display controller */
1620         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1621         tmp |= DPIO_DCLKP_EN;
1622         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1623
1624         mutex_unlock(&dev_priv->sb_lock);
1625
1626         /*
1627          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1628          */
1629         udelay(1);
1630
1631         /* Enable PLL */
1632         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1633
1634         /* Check PLL is locked */
1635         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1636                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1637
1638         /* not sure when this should be written */
1639         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640         POSTING_READ(DPLL_MD(pipe));
1641 }
1642
1643 static int intel_num_dvo_pipes(struct drm_device *dev)
1644 {
1645         struct intel_crtc *crtc;
1646         int count = 0;
1647
1648         for_each_intel_crtc(dev, crtc)
1649                 count += crtc->base.state->active &&
1650                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1651
1652         return count;
1653 }
1654
1655 static void i9xx_enable_pll(struct intel_crtc *crtc)
1656 {
1657         struct drm_device *dev = crtc->base.dev;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659         i915_reg_t reg = DPLL(crtc->pipe);
1660         u32 dpll = crtc->config->dpll_hw_state.dpll;
1661
1662         assert_pipe_disabled(dev_priv, crtc->pipe);
1663
1664         /* No really, not for ILK+ */
1665         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1666
1667         /* PLL is protected by panel, make sure we can write it */
1668         if (IS_MOBILE(dev) && !IS_I830(dev))
1669                 assert_panel_unlocked(dev_priv, crtc->pipe);
1670
1671         /* Enable DVO 2x clock on both PLLs if necessary */
1672         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1673                 /*
1674                  * It appears to be important that we don't enable this
1675                  * for the current pipe before otherwise configuring the
1676                  * PLL. No idea how this should be handled if multiple
1677                  * DVO outputs are enabled simultaneosly.
1678                  */
1679                 dpll |= DPLL_DVO_2X_MODE;
1680                 I915_WRITE(DPLL(!crtc->pipe),
1681                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1682         }
1683
1684         /*
1685          * Apparently we need to have VGA mode enabled prior to changing
1686          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1687          * dividers, even though the register value does change.
1688          */
1689         I915_WRITE(reg, 0);
1690
1691         I915_WRITE(reg, dpll);
1692
1693         /* Wait for the clocks to stabilize. */
1694         POSTING_READ(reg);
1695         udelay(150);
1696
1697         if (INTEL_INFO(dev)->gen >= 4) {
1698                 I915_WRITE(DPLL_MD(crtc->pipe),
1699                            crtc->config->dpll_hw_state.dpll_md);
1700         } else {
1701                 /* The pixel multiplier can only be updated once the
1702                  * DPLL is enabled and the clocks are stable.
1703                  *
1704                  * So write it again.
1705                  */
1706                 I915_WRITE(reg, dpll);
1707         }
1708
1709         /* We do this three times for luck */
1710         I915_WRITE(reg, dpll);
1711         POSTING_READ(reg);
1712         udelay(150); /* wait for warmup */
1713         I915_WRITE(reg, dpll);
1714         POSTING_READ(reg);
1715         udelay(150); /* wait for warmup */
1716         I915_WRITE(reg, dpll);
1717         POSTING_READ(reg);
1718         udelay(150); /* wait for warmup */
1719 }
1720
1721 /**
1722  * i9xx_disable_pll - disable a PLL
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe PLL to disable
1725  *
1726  * Disable the PLL for @pipe, making sure the pipe is off first.
1727  *
1728  * Note!  This is for pre-ILK only.
1729  */
1730 static void i9xx_disable_pll(struct intel_crtc *crtc)
1731 {
1732         struct drm_device *dev = crtc->base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         enum pipe pipe = crtc->pipe;
1735
1736         /* Disable DVO 2x clock on both PLLs if necessary */
1737         if (IS_I830(dev) &&
1738             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1739             !intel_num_dvo_pipes(dev)) {
1740                 I915_WRITE(DPLL(PIPE_B),
1741                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1742                 I915_WRITE(DPLL(PIPE_A),
1743                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1744         }
1745
1746         /* Don't disable pipe or pipe PLLs if needed */
1747         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1748             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1749                 return;
1750
1751         /* Make sure the pipe isn't still relying on us */
1752         assert_pipe_disabled(dev_priv, pipe);
1753
1754         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1755         POSTING_READ(DPLL(pipe));
1756 }
1757
1758 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1759 {
1760         u32 val;
1761
1762         /* Make sure the pipe isn't still relying on us */
1763         assert_pipe_disabled(dev_priv, pipe);
1764
1765         /*
1766          * Leave integrated clock source and reference clock enabled for pipe B.
1767          * The latter is needed for VGA hotplug / manual detection.
1768          */
1769         val = DPLL_VGA_MODE_DIS;
1770         if (pipe == PIPE_B)
1771                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1772         I915_WRITE(DPLL(pipe), val);
1773         POSTING_READ(DPLL(pipe));
1774
1775 }
1776
1777 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1778 {
1779         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1780         u32 val;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         /* Set PLL en = 0 */
1786         val = DPLL_SSC_REF_CLK_CHV |
1787                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1788         if (pipe != PIPE_A)
1789                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1790         I915_WRITE(DPLL(pipe), val);
1791         POSTING_READ(DPLL(pipe));
1792
1793         mutex_lock(&dev_priv->sb_lock);
1794
1795         /* Disable 10bit clock to display controller */
1796         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1797         val &= ~DPIO_DCLKP_EN;
1798         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1799
1800         mutex_unlock(&dev_priv->sb_lock);
1801 }
1802
1803 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1804                          struct intel_digital_port *dport,
1805                          unsigned int expected_mask)
1806 {
1807         u32 port_mask;
1808         i915_reg_t dpll_reg;
1809
1810         switch (dport->port) {
1811         case PORT_B:
1812                 port_mask = DPLL_PORTB_READY_MASK;
1813                 dpll_reg = DPLL(0);
1814                 break;
1815         case PORT_C:
1816                 port_mask = DPLL_PORTC_READY_MASK;
1817                 dpll_reg = DPLL(0);
1818                 expected_mask <<= 4;
1819                 break;
1820         case PORT_D:
1821                 port_mask = DPLL_PORTD_READY_MASK;
1822                 dpll_reg = DPIO_PHY_STATUS;
1823                 break;
1824         default:
1825                 BUG();
1826         }
1827
1828         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1829                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1830                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1831 }
1832
1833 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834                                            enum pipe pipe)
1835 {
1836         struct drm_device *dev = dev_priv->dev;
1837         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839         i915_reg_t reg;
1840         uint32_t val, pipeconf_val;
1841
1842         /* PCH only available on ILK+ */
1843         BUG_ON(!HAS_PCH_SPLIT(dev));
1844
1845         /* Make sure PCH DPLL is enabled */
1846         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1847
1848         /* FDI must be feeding us bits for PCH ports */
1849         assert_fdi_tx_enabled(dev_priv, pipe);
1850         assert_fdi_rx_enabled(dev_priv, pipe);
1851
1852         if (HAS_PCH_CPT(dev)) {
1853                 /* Workaround: Set the timing override bit before enabling the
1854                  * pch transcoder. */
1855                 reg = TRANS_CHICKEN2(pipe);
1856                 val = I915_READ(reg);
1857                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858                 I915_WRITE(reg, val);
1859         }
1860
1861         reg = PCH_TRANSCONF(pipe);
1862         val = I915_READ(reg);
1863         pipeconf_val = I915_READ(PIPECONF(pipe));
1864
1865         if (HAS_PCH_IBX(dev_priv->dev)) {
1866                 /*
1867                  * Make the BPC in transcoder be consistent with
1868                  * that in pipeconf reg. For HDMI we must use 8bpc
1869                  * here for both 8bpc and 12bpc.
1870                  */
1871                 val &= ~PIPECONF_BPC_MASK;
1872                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1873                         val |= PIPECONF_8BPC;
1874                 else
1875                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1876         }
1877
1878         val &= ~TRANS_INTERLACE_MASK;
1879         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1880                 if (HAS_PCH_IBX(dev_priv->dev) &&
1881                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1882                         val |= TRANS_LEGACY_INTERLACED_ILK;
1883                 else
1884                         val |= TRANS_INTERLACED;
1885         else
1886                 val |= TRANS_PROGRESSIVE;
1887
1888         I915_WRITE(reg, val | TRANS_ENABLE);
1889         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1890                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1891 }
1892
1893 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1894                                       enum transcoder cpu_transcoder)
1895 {
1896         u32 val, pipeconf_val;
1897
1898         /* PCH only available on ILK+ */
1899         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1900
1901         /* FDI must be feeding us bits for PCH ports */
1902         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1903         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1904
1905         /* Workaround: set timing override bit. */
1906         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1907         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1908         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1909
1910         val = TRANS_ENABLE;
1911         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1912
1913         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1914             PIPECONF_INTERLACED_ILK)
1915                 val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(LPT_TRANSCONF, val);
1920         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("Failed to enable PCH transcoder\n");
1922 }
1923
1924 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                             enum pipe pipe)
1926 {
1927         struct drm_device *dev = dev_priv->dev;
1928         i915_reg_t reg;
1929         uint32_t val;
1930
1931         /* FDI relies on the transcoder */
1932         assert_fdi_tx_disabled(dev_priv, pipe);
1933         assert_fdi_rx_disabled(dev_priv, pipe);
1934
1935         /* Ports must be off as well */
1936         assert_pch_ports_disabled(dev_priv, pipe);
1937
1938         reg = PCH_TRANSCONF(pipe);
1939         val = I915_READ(reg);
1940         val &= ~TRANS_ENABLE;
1941         I915_WRITE(reg, val);
1942         /* wait for PCH transcoder off, transcoder state */
1943         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1944                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1945
1946         if (HAS_PCH_CPT(dev)) {
1947                 /* Workaround: Clear the timing override chicken bit again. */
1948                 reg = TRANS_CHICKEN2(pipe);
1949                 val = I915_READ(reg);
1950                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951                 I915_WRITE(reg, val);
1952         }
1953 }
1954
1955 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1956 {
1957         u32 val;
1958
1959         val = I915_READ(LPT_TRANSCONF);
1960         val &= ~TRANS_ENABLE;
1961         I915_WRITE(LPT_TRANSCONF, val);
1962         /* wait for PCH transcoder off, transcoder state */
1963         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1964                 DRM_ERROR("Failed to disable PCH transcoder\n");
1965
1966         /* Workaround: clear timing override bit. */
1967         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1968         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1969         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1970 }
1971
1972 /**
1973  * intel_enable_pipe - enable a pipe, asserting requirements
1974  * @crtc: crtc responsible for the pipe
1975  *
1976  * Enable @crtc's pipe, making sure that various hardware specific requirements
1977  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1978  */
1979 static void intel_enable_pipe(struct intel_crtc *crtc)
1980 {
1981         struct drm_device *dev = crtc->base.dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         enum pipe pipe = crtc->pipe;
1984         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1985         enum pipe pch_transcoder;
1986         i915_reg_t reg;
1987         u32 val;
1988
1989         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1990
1991         assert_planes_disabled(dev_priv, pipe);
1992         assert_cursor_disabled(dev_priv, pipe);
1993         assert_sprites_disabled(dev_priv, pipe);
1994
1995         if (HAS_PCH_LPT(dev_priv->dev))
1996                 pch_transcoder = TRANSCODER_A;
1997         else
1998                 pch_transcoder = pipe;
1999
2000         /*
2001          * A pipe without a PLL won't actually be able to drive bits from
2002          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2003          * need the check.
2004          */
2005         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2006                 if (crtc->config->has_dsi_encoder)
2007                         assert_dsi_pll_enabled(dev_priv);
2008                 else
2009                         assert_pll_enabled(dev_priv, pipe);
2010         else {
2011                 if (crtc->config->has_pch_encoder) {
2012                         /* if driving the PCH, we need FDI enabled */
2013                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2014                         assert_fdi_tx_pll_enabled(dev_priv,
2015                                                   (enum pipe) cpu_transcoder);
2016                 }
2017                 /* FIXME: assert CPU port conditions for SNB+ */
2018         }
2019
2020         reg = PIPECONF(cpu_transcoder);
2021         val = I915_READ(reg);
2022         if (val & PIPECONF_ENABLE) {
2023                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2024                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2025                 return;
2026         }
2027
2028         I915_WRITE(reg, val | PIPECONF_ENABLE);
2029         POSTING_READ(reg);
2030
2031         /*
2032          * Until the pipe starts DSL will read as 0, which would cause
2033          * an apparent vblank timestamp jump, which messes up also the
2034          * frame count when it's derived from the timestamps. So let's
2035          * wait for the pipe to start properly before we call
2036          * drm_crtc_vblank_on()
2037          */
2038         if (dev->max_vblank_count == 0 &&
2039             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2040                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2041 }
2042
2043 /**
2044  * intel_disable_pipe - disable a pipe, asserting requirements
2045  * @crtc: crtc whose pipes is to be disabled
2046  *
2047  * Disable the pipe of @crtc, making sure that various hardware
2048  * specific requirements are met, if applicable, e.g. plane
2049  * disabled, panel fitter off, etc.
2050  *
2051  * Will wait until the pipe has shut down before returning.
2052  */
2053 static void intel_disable_pipe(struct intel_crtc *crtc)
2054 {
2055         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2056         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2057         enum pipe pipe = crtc->pipe;
2058         i915_reg_t reg;
2059         u32 val;
2060
2061         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2062
2063         /*
2064          * Make sure planes won't keep trying to pump pixels to us,
2065          * or we might hang the display.
2066          */
2067         assert_planes_disabled(dev_priv, pipe);
2068         assert_cursor_disabled(dev_priv, pipe);
2069         assert_sprites_disabled(dev_priv, pipe);
2070
2071         reg = PIPECONF(cpu_transcoder);
2072         val = I915_READ(reg);
2073         if ((val & PIPECONF_ENABLE) == 0)
2074                 return;
2075
2076         /*
2077          * Double wide has implications for planes
2078          * so best keep it disabled when not needed.
2079          */
2080         if (crtc->config->double_wide)
2081                 val &= ~PIPECONF_DOUBLE_WIDE;
2082
2083         /* Don't disable pipe or pipe PLLs if needed */
2084         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2085             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2086                 val &= ~PIPECONF_ENABLE;
2087
2088         I915_WRITE(reg, val);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 intel_wait_for_pipe_off(crtc);
2091 }
2092
2093 static bool need_vtd_wa(struct drm_device *dev)
2094 {
2095 #ifdef CONFIG_INTEL_IOMMU
2096         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2097                 return true;
2098 #endif
2099         return false;
2100 }
2101
2102 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2103 {
2104         return IS_GEN2(dev_priv) ? 2048 : 4096;
2105 }
2106
2107 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2108                                            uint64_t fb_modifier, unsigned int cpp)
2109 {
2110         switch (fb_modifier) {
2111         case DRM_FORMAT_MOD_NONE:
2112                 return cpp;
2113         case I915_FORMAT_MOD_X_TILED:
2114                 if (IS_GEN2(dev_priv))
2115                         return 128;
2116                 else
2117                         return 512;
2118         case I915_FORMAT_MOD_Y_TILED:
2119                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2120                         return 128;
2121                 else
2122                         return 512;
2123         case I915_FORMAT_MOD_Yf_TILED:
2124                 switch (cpp) {
2125                 case 1:
2126                         return 64;
2127                 case 2:
2128                 case 4:
2129                         return 128;
2130                 case 8:
2131                 case 16:
2132                         return 256;
2133                 default:
2134                         MISSING_CASE(cpp);
2135                         return cpp;
2136                 }
2137                 break;
2138         default:
2139                 MISSING_CASE(fb_modifier);
2140                 return cpp;
2141         }
2142 }
2143
2144 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2145                                uint64_t fb_modifier, unsigned int cpp)
2146 {
2147         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2148                 return 1;
2149         else
2150                 return intel_tile_size(dev_priv) /
2151                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2152 }
2153
2154 /* Return the tile dimensions in pixel units */
2155 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2156                             unsigned int *tile_width,
2157                             unsigned int *tile_height,
2158                             uint64_t fb_modifier,
2159                             unsigned int cpp)
2160 {
2161         unsigned int tile_width_bytes =
2162                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2163
2164         *tile_width = tile_width_bytes / cpp;
2165         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2166 }
2167
2168 unsigned int
2169 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2170                       uint32_t pixel_format, uint64_t fb_modifier)
2171 {
2172         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2173         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2174
2175         return ALIGN(height, tile_height);
2176 }
2177
2178 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2179 {
2180         unsigned int size = 0;
2181         int i;
2182
2183         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2184                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2185
2186         return size;
2187 }
2188
2189 static void
2190 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2191                         const struct drm_framebuffer *fb,
2192                         unsigned int rotation)
2193 {
2194         if (intel_rotation_90_or_270(rotation)) {
2195                 *view = i915_ggtt_view_rotated;
2196                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2197         } else {
2198                 *view = i915_ggtt_view_normal;
2199         }
2200 }
2201
2202 static void
2203 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2204                    struct drm_framebuffer *fb)
2205 {
2206         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2207         unsigned int tile_size, tile_width, tile_height, cpp;
2208
2209         tile_size = intel_tile_size(dev_priv);
2210
2211         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2212         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2213                         fb->modifier[0], cpp);
2214
2215         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2216         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2217
2218         if (info->pixel_format == DRM_FORMAT_NV12) {
2219                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2220                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2221                                 fb->modifier[1], cpp);
2222
2223                 info->uv_offset = fb->offsets[1];
2224                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2225                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2226         }
2227 }
2228
2229 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2230 {
2231         if (INTEL_INFO(dev_priv)->gen >= 9)
2232                 return 256 * 1024;
2233         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2234                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2235                 return 128 * 1024;
2236         else if (INTEL_INFO(dev_priv)->gen >= 4)
2237                 return 4 * 1024;
2238         else
2239                 return 0;
2240 }
2241
2242 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2243                                          uint64_t fb_modifier)
2244 {
2245         switch (fb_modifier) {
2246         case DRM_FORMAT_MOD_NONE:
2247                 return intel_linear_alignment(dev_priv);
2248         case I915_FORMAT_MOD_X_TILED:
2249                 if (INTEL_INFO(dev_priv)->gen >= 9)
2250                         return 256 * 1024;
2251                 return 0;
2252         case I915_FORMAT_MOD_Y_TILED:
2253         case I915_FORMAT_MOD_Yf_TILED:
2254                 return 1 * 1024 * 1024;
2255         default:
2256                 MISSING_CASE(fb_modifier);
2257                 return 0;
2258         }
2259 }
2260
2261 int
2262 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2263                            unsigned int rotation)
2264 {
2265         struct drm_device *dev = fb->dev;
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2268         struct i915_ggtt_view view;
2269         u32 alignment;
2270         int ret;
2271
2272         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2273
2274         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2275
2276         intel_fill_fb_ggtt_view(&view, fb, rotation);
2277
2278         /* Note that the w/a also requires 64 PTE of padding following the
2279          * bo. We currently fill all unused PTE with the shadow page and so
2280          * we should always have valid PTE following the scanout preventing
2281          * the VT-d warning.
2282          */
2283         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2284                 alignment = 256 * 1024;
2285
2286         /*
2287          * Global gtt pte registers are special registers which actually forward
2288          * writes to a chunk of system memory. Which means that there is no risk
2289          * that the register values disappear as soon as we call
2290          * intel_runtime_pm_put(), so it is correct to wrap only the
2291          * pin/unpin/fence and not more.
2292          */
2293         intel_runtime_pm_get(dev_priv);
2294
2295         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2296                                                    &view);
2297         if (ret)
2298                 goto err_pm;
2299
2300         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2301          * fence, whereas 965+ only requires a fence if using
2302          * framebuffer compression.  For simplicity, we always install
2303          * a fence as the cost is not that onerous.
2304          */
2305         if (view.type == I915_GGTT_VIEW_NORMAL) {
2306                 ret = i915_gem_object_get_fence(obj);
2307                 if (ret == -EDEADLK) {
2308                         /*
2309                          * -EDEADLK means there are no free fences
2310                          * no pending flips.
2311                          *
2312                          * This is propagated to atomic, but it uses
2313                          * -EDEADLK to force a locking recovery, so
2314                          * change the returned error to -EBUSY.
2315                          */
2316                         ret = -EBUSY;
2317                         goto err_unpin;
2318                 } else if (ret)
2319                         goto err_unpin;
2320
2321                 i915_gem_object_pin_fence(obj);
2322         }
2323
2324         intel_runtime_pm_put(dev_priv);
2325         return 0;
2326
2327 err_unpin:
2328         i915_gem_object_unpin_from_display_plane(obj, &view);
2329 err_pm:
2330         intel_runtime_pm_put(dev_priv);
2331         return ret;
2332 }
2333
2334 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2335 {
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338
2339         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2340
2341         intel_fill_fb_ggtt_view(&view, fb, rotation);
2342
2343         if (view.type == I915_GGTT_VIEW_NORMAL)
2344                 i915_gem_object_unpin_fence(obj);
2345
2346         i915_gem_object_unpin_from_display_plane(obj, &view);
2347 }
2348
2349 /*
2350  * Adjust the tile offset by moving the difference into
2351  * the x/y offsets.
2352  *
2353  * Input tile dimensions and pitch must already be
2354  * rotated to match x and y, and in pixel units.
2355  */
2356 static u32 intel_adjust_tile_offset(int *x, int *y,
2357                                     unsigned int tile_width,
2358                                     unsigned int tile_height,
2359                                     unsigned int tile_size,
2360                                     unsigned int pitch_tiles,
2361                                     u32 old_offset,
2362                                     u32 new_offset)
2363 {
2364         unsigned int tiles;
2365
2366         WARN_ON(old_offset & (tile_size - 1));
2367         WARN_ON(new_offset & (tile_size - 1));
2368         WARN_ON(new_offset > old_offset);
2369
2370         tiles = (old_offset - new_offset) / tile_size;
2371
2372         *y += tiles / pitch_tiles * tile_height;
2373         *x += tiles % pitch_tiles * tile_width;
2374
2375         return new_offset;
2376 }
2377
2378 /*
2379  * Computes the linear offset to the base tile and adjusts
2380  * x, y. bytes per pixel is assumed to be a power-of-two.
2381  *
2382  * In the 90/270 rotated case, x and y are assumed
2383  * to be already rotated to match the rotated GTT view, and
2384  * pitch is the tile_height aligned framebuffer height.
2385  */
2386 u32 intel_compute_tile_offset(int *x, int *y,
2387                               const struct drm_framebuffer *fb, int plane,
2388                               unsigned int pitch,
2389                               unsigned int rotation)
2390 {
2391         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2392         uint64_t fb_modifier = fb->modifier[plane];
2393         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2394         u32 offset, offset_aligned, alignment;
2395
2396         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2397         if (alignment)
2398                 alignment--;
2399
2400         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2401                 unsigned int tile_size, tile_width, tile_height;
2402                 unsigned int tile_rows, tiles, pitch_tiles;
2403
2404                 tile_size = intel_tile_size(dev_priv);
2405                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2406                                 fb_modifier, cpp);
2407
2408                 if (intel_rotation_90_or_270(rotation)) {
2409                         pitch_tiles = pitch / tile_height;
2410                         swap(tile_width, tile_height);
2411                 } else {
2412                         pitch_tiles = pitch / (tile_width * cpp);
2413                 }
2414
2415                 tile_rows = *y / tile_height;
2416                 *y %= tile_height;
2417
2418                 tiles = *x / tile_width;
2419                 *x %= tile_width;
2420
2421                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2422                 offset_aligned = offset & ~alignment;
2423
2424                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2425                                          tile_size, pitch_tiles,
2426                                          offset, offset_aligned);
2427         } else {
2428                 offset = *y * pitch + *x * cpp;
2429                 offset_aligned = offset & ~alignment;
2430
2431                 *y = (offset & alignment) / pitch;
2432                 *x = ((offset & alignment) - *y * pitch) / cpp;
2433         }
2434
2435         return offset_aligned;
2436 }
2437
2438 static int i9xx_format_to_fourcc(int format)
2439 {
2440         switch (format) {
2441         case DISPPLANE_8BPP:
2442                 return DRM_FORMAT_C8;
2443         case DISPPLANE_BGRX555:
2444                 return DRM_FORMAT_XRGB1555;
2445         case DISPPLANE_BGRX565:
2446                 return DRM_FORMAT_RGB565;
2447         default:
2448         case DISPPLANE_BGRX888:
2449                 return DRM_FORMAT_XRGB8888;
2450         case DISPPLANE_RGBX888:
2451                 return DRM_FORMAT_XBGR8888;
2452         case DISPPLANE_BGRX101010:
2453                 return DRM_FORMAT_XRGB2101010;
2454         case DISPPLANE_RGBX101010:
2455                 return DRM_FORMAT_XBGR2101010;
2456         }
2457 }
2458
2459 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2460 {
2461         switch (format) {
2462         case PLANE_CTL_FORMAT_RGB_565:
2463                 return DRM_FORMAT_RGB565;
2464         default:
2465         case PLANE_CTL_FORMAT_XRGB_8888:
2466                 if (rgb_order) {
2467                         if (alpha)
2468                                 return DRM_FORMAT_ABGR8888;
2469                         else
2470                                 return DRM_FORMAT_XBGR8888;
2471                 } else {
2472                         if (alpha)
2473                                 return DRM_FORMAT_ARGB8888;
2474                         else
2475                                 return DRM_FORMAT_XRGB8888;
2476                 }
2477         case PLANE_CTL_FORMAT_XRGB_2101010:
2478                 if (rgb_order)
2479                         return DRM_FORMAT_XBGR2101010;
2480                 else
2481                         return DRM_FORMAT_XRGB2101010;
2482         }
2483 }
2484
2485 static bool
2486 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2487                               struct intel_initial_plane_config *plane_config)
2488 {
2489         struct drm_device *dev = crtc->base.dev;
2490         struct drm_i915_private *dev_priv = to_i915(dev);
2491         struct drm_i915_gem_object *obj = NULL;
2492         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2493         struct drm_framebuffer *fb = &plane_config->fb->base;
2494         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2495         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2496                                     PAGE_SIZE);
2497
2498         size_aligned -= base_aligned;
2499
2500         if (plane_config->size == 0)
2501                 return false;
2502
2503         /* If the FB is too big, just don't use it since fbdev is not very
2504          * important and we should probably use that space with FBC or other
2505          * features. */
2506         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2507                 return false;
2508
2509         mutex_lock(&dev->struct_mutex);
2510
2511         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2512                                                              base_aligned,
2513                                                              base_aligned,
2514                                                              size_aligned);
2515         if (!obj) {
2516                 mutex_unlock(&dev->struct_mutex);
2517                 return false;
2518         }
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2532                                    &mode_cmd, obj)) {
2533                 DRM_DEBUG_KMS("intel fb init failed\n");
2534                 goto out_unref_obj;
2535         }
2536
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2574         struct intel_plane *intel_plane = to_intel_plane(primary);
2575         struct intel_plane_state *intel_state =
2576                 to_intel_plane_state(plane_state);
2577         struct drm_framebuffer *fb;
2578
2579         if (!plane_config->fb)
2580                 return;
2581
2582         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2583                 fb = &plane_config->fb->base;
2584                 goto valid_fb;
2585         }
2586
2587         kfree(plane_config->fb);
2588
2589         /*
2590          * Failed to alloc the obj, check to see if we should share
2591          * an fb with another CRTC instead
2592          */
2593         for_each_crtc(dev, c) {
2594                 i = to_intel_crtc(c);
2595
2596                 if (c == &intel_crtc->base)
2597                         continue;
2598
2599                 if (!i->active)
2600                         continue;
2601
2602                 fb = c->primary->fb;
2603                 if (!fb)
2604                         continue;
2605
2606                 obj = intel_fb_obj(fb);
2607                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2608                         drm_framebuffer_reference(fb);
2609                         goto valid_fb;
2610                 }
2611         }
2612
2613         /*
2614          * We've failed to reconstruct the BIOS FB.  Current display state
2615          * indicates that the primary plane is visible, but has a NULL FB,
2616          * which will lead to problems later if we don't fix it up.  The
2617          * simplest solution is to just disable the primary plane now and
2618          * pretend the BIOS never had it enabled.
2619          */
2620         to_intel_plane_state(plane_state)->visible = false;
2621         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2623         intel_plane->disable_plane(primary, &intel_crtc->base);
2624
2625         return;
2626
2627 valid_fb:
2628         plane_state->src_x = 0;
2629         plane_state->src_y = 0;
2630         plane_state->src_w = fb->width << 16;
2631         plane_state->src_h = fb->height << 16;
2632
2633         plane_state->crtc_x = 0;
2634         plane_state->crtc_y = 0;
2635         plane_state->crtc_w = fb->width;
2636         plane_state->crtc_h = fb->height;
2637
2638         intel_state->src.x1 = plane_state->src_x;
2639         intel_state->src.y1 = plane_state->src_y;
2640         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2641         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2642         intel_state->dst.x1 = plane_state->crtc_x;
2643         intel_state->dst.y1 = plane_state->crtc_y;
2644         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2645         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2646
2647         obj = intel_fb_obj(fb);
2648         if (obj->tiling_mode != I915_TILING_NONE)
2649                 dev_priv->preserve_bios_swizzle = true;
2650
2651         drm_framebuffer_reference(fb);
2652         primary->fb = primary->state->fb = fb;
2653         primary->crtc = primary->state->crtc = &intel_crtc->base;
2654         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_plane *primary,
2659                                       const struct intel_crtc_state *crtc_state,
2660                                       const struct intel_plane_state *plane_state)
2661 {
2662         struct drm_device *dev = primary->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2665         struct drm_framebuffer *fb = plane_state->base.fb;
2666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2667         int plane = intel_crtc->plane;
2668         u32 linear_offset;
2669         u32 dspcntr;
2670         i915_reg_t reg = DSPCNTR(plane);
2671         unsigned int rotation = plane_state->base.rotation;
2672         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2673         int x = plane_state->src.x1 >> 16;
2674         int y = plane_state->src.y1 >> 16;
2675
2676         dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678         dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680         if (INTEL_INFO(dev)->gen < 4) {
2681                 if (intel_crtc->pipe == PIPE_B)
2682                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684                 /* pipesrc and dspsize control the size that is scaled from,
2685                  * which should always be the user's requested size.
2686                  */
2687                 I915_WRITE(DSPSIZE(plane),
2688                            ((crtc_state->pipe_src_h - 1) << 16) |
2689                            (crtc_state->pipe_src_w - 1));
2690                 I915_WRITE(DSPPOS(plane), 0);
2691         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692                 I915_WRITE(PRIMSIZE(plane),
2693                            ((crtc_state->pipe_src_h - 1) << 16) |
2694                            (crtc_state->pipe_src_w - 1));
2695                 I915_WRITE(PRIMPOS(plane), 0);
2696                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697         }
2698
2699         switch (fb->pixel_format) {
2700         case DRM_FORMAT_C8:
2701                 dspcntr |= DISPPLANE_8BPP;
2702                 break;
2703         case DRM_FORMAT_XRGB1555:
2704                 dspcntr |= DISPPLANE_BGRX555;
2705                 break;
2706         case DRM_FORMAT_RGB565:
2707                 dspcntr |= DISPPLANE_BGRX565;
2708                 break;
2709         case DRM_FORMAT_XRGB8888:
2710                 dspcntr |= DISPPLANE_BGRX888;
2711                 break;
2712         case DRM_FORMAT_XBGR8888:
2713                 dspcntr |= DISPPLANE_RGBX888;
2714                 break;
2715         case DRM_FORMAT_XRGB2101010:
2716                 dspcntr |= DISPPLANE_BGRX101010;
2717                 break;
2718         case DRM_FORMAT_XBGR2101010:
2719                 dspcntr |= DISPPLANE_RGBX101010;
2720                 break;
2721         default:
2722                 BUG();
2723         }
2724
2725         if (INTEL_INFO(dev)->gen >= 4 &&
2726             obj->tiling_mode != I915_TILING_NONE)
2727                 dspcntr |= DISPPLANE_TILED;
2728
2729         if (IS_G4X(dev))
2730                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732         linear_offset = y * fb->pitches[0] + x * cpp;
2733
2734         if (INTEL_INFO(dev)->gen >= 4) {
2735                 intel_crtc->dspaddr_offset =
2736                         intel_compute_tile_offset(&x, &y, fb, 0,
2737                                                   fb->pitches[0], rotation);
2738                 linear_offset -= intel_crtc->dspaddr_offset;
2739         } else {
2740                 intel_crtc->dspaddr_offset = linear_offset;
2741         }
2742
2743         if (rotation == BIT(DRM_ROTATE_180)) {
2744                 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746                 x += (crtc_state->pipe_src_w - 1);
2747                 y += (crtc_state->pipe_src_h - 1);
2748
2749                 /* Finding the last pixel of the last line of the display
2750                 data and adding to linear_offset*/
2751                 linear_offset +=
2752                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2753                         (crtc_state->pipe_src_w - 1) * cpp;
2754         }
2755
2756         intel_crtc->adjusted_x = x;
2757         intel_crtc->adjusted_y = y;
2758
2759         I915_WRITE(reg, dspcntr);
2760
2761         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2762         if (INTEL_INFO(dev)->gen >= 4) {
2763                 I915_WRITE(DSPSURF(plane),
2764                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2766                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767         } else
2768                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769         POSTING_READ(reg);
2770 }
2771
2772 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2773                                        struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int plane = intel_crtc->plane;
2779
2780         I915_WRITE(DSPCNTR(plane), 0);
2781         if (INTEL_INFO(dev_priv)->gen >= 4)
2782                 I915_WRITE(DSPSURF(plane), 0);
2783         else
2784                 I915_WRITE(DSPADDR(plane), 0);
2785         POSTING_READ(DSPCNTR(plane));
2786 }
2787
2788 static void ironlake_update_primary_plane(struct drm_plane *primary,
2789                                           const struct intel_crtc_state *crtc_state,
2790                                           const struct intel_plane_state *plane_state)
2791 {
2792         struct drm_device *dev = primary->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2795         struct drm_framebuffer *fb = plane_state->base.fb;
2796         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2797         int plane = intel_crtc->plane;
2798         u32 linear_offset;
2799         u32 dspcntr;
2800         i915_reg_t reg = DSPCNTR(plane);
2801         unsigned int rotation = plane_state->base.rotation;
2802         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2803         int x = plane_state->src.x1 >> 16;
2804         int y = plane_state->src.y1 >> 16;
2805
2806         dspcntr = DISPPLANE_GAMMA_ENABLE;
2807         dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812         switch (fb->pixel_format) {
2813         case DRM_FORMAT_C8:
2814                 dspcntr |= DISPPLANE_8BPP;
2815                 break;
2816         case DRM_FORMAT_RGB565:
2817                 dspcntr |= DISPPLANE_BGRX565;
2818                 break;
2819         case DRM_FORMAT_XRGB8888:
2820                 dspcntr |= DISPPLANE_BGRX888;
2821                 break;
2822         case DRM_FORMAT_XBGR8888:
2823                 dspcntr |= DISPPLANE_RGBX888;
2824                 break;
2825         case DRM_FORMAT_XRGB2101010:
2826                 dspcntr |= DISPPLANE_BGRX101010;
2827                 break;
2828         case DRM_FORMAT_XBGR2101010:
2829                 dspcntr |= DISPPLANE_RGBX101010;
2830                 break;
2831         default:
2832                 BUG();
2833         }
2834
2835         if (obj->tiling_mode != I915_TILING_NONE)
2836                 dspcntr |= DISPPLANE_TILED;
2837
2838         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2839                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2840
2841         linear_offset = y * fb->pitches[0] + x * cpp;
2842         intel_crtc->dspaddr_offset =
2843                 intel_compute_tile_offset(&x, &y, fb, 0,
2844                                           fb->pitches[0], rotation);
2845         linear_offset -= intel_crtc->dspaddr_offset;
2846         if (rotation == BIT(DRM_ROTATE_180)) {
2847                 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850                         x += (crtc_state->pipe_src_w - 1);
2851                         y += (crtc_state->pipe_src_h - 1);
2852
2853                         /* Finding the last pixel of the last line of the display
2854                         data and adding to linear_offset*/
2855                         linear_offset +=
2856                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2857                                 (crtc_state->pipe_src_w - 1) * cpp;
2858                 }
2859         }
2860
2861         intel_crtc->adjusted_x = x;
2862         intel_crtc->adjusted_y = y;
2863
2864         I915_WRITE(reg, dspcntr);
2865
2866         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867         I915_WRITE(DSPSURF(plane),
2868                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871         } else {
2872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874         }
2875         POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2879                               uint64_t fb_modifier, uint32_t pixel_format)
2880 {
2881         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2882                 return 64;
2883         } else {
2884                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2885
2886                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2887         }
2888 }
2889
2890 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2891                            struct drm_i915_gem_object *obj,
2892                            unsigned int plane)
2893 {
2894         struct i915_ggtt_view view;
2895         struct i915_vma *vma;
2896         u64 offset;
2897
2898         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2899                                 intel_plane->base.state->rotation);
2900
2901         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2902         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2903                 view.type))
2904                 return -1;
2905
2906         offset = vma->node.start;
2907
2908         if (plane == 1) {
2909                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2910                           PAGE_SIZE;
2911         }
2912
2913         WARN_ON(upper_32_bits(offset));
2914
2915         return lower_32_bits(offset);
2916 }
2917
2918 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 {
2920         struct drm_device *dev = intel_crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922
2923         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2925         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2926 }
2927
2928 /*
2929  * This function detaches (aka. unbinds) unused scalers in hardware
2930  */
2931 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 {
2933         struct intel_crtc_scaler_state *scaler_state;
2934         int i;
2935
2936         scaler_state = &intel_crtc->config->scaler_state;
2937
2938         /* loop through and disable scalers that aren't in use */
2939         for (i = 0; i < intel_crtc->num_scalers; i++) {
2940                 if (!scaler_state->scalers[i].in_use)
2941                         skl_detach_scaler(intel_crtc, i);
2942         }
2943 }
2944
2945 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 {
2947         switch (pixel_format) {
2948         case DRM_FORMAT_C8:
2949                 return PLANE_CTL_FORMAT_INDEXED;
2950         case DRM_FORMAT_RGB565:
2951                 return PLANE_CTL_FORMAT_RGB_565;
2952         case DRM_FORMAT_XBGR8888:
2953                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2954         case DRM_FORMAT_XRGB8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888;
2956         /*
2957          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2958          * to be already pre-multiplied. We need to add a knob (or a different
2959          * DRM_FORMAT) for user-space to configure that.
2960          */
2961         case DRM_FORMAT_ABGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2963                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2964         case DRM_FORMAT_ARGB8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888 |
2966                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2967         case DRM_FORMAT_XRGB2101010:
2968                 return PLANE_CTL_FORMAT_XRGB_2101010;
2969         case DRM_FORMAT_XBGR2101010:
2970                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2971         case DRM_FORMAT_YUYV:
2972                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2973         case DRM_FORMAT_YVYU:
2974                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2975         case DRM_FORMAT_UYVY:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2977         case DRM_FORMAT_VYUY:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979         default:
2980                 MISSING_CASE(pixel_format);
2981         }
2982
2983         return 0;
2984 }
2985
2986 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 {
2988         switch (fb_modifier) {
2989         case DRM_FORMAT_MOD_NONE:
2990                 break;
2991         case I915_FORMAT_MOD_X_TILED:
2992                 return PLANE_CTL_TILED_X;
2993         case I915_FORMAT_MOD_Y_TILED:
2994                 return PLANE_CTL_TILED_Y;
2995         case I915_FORMAT_MOD_Yf_TILED:
2996                 return PLANE_CTL_TILED_YF;
2997         default:
2998                 MISSING_CASE(fb_modifier);
2999         }
3000
3001         return 0;
3002 }
3003
3004 u32 skl_plane_ctl_rotation(unsigned int rotation)
3005 {
3006         switch (rotation) {
3007         case BIT(DRM_ROTATE_0):
3008                 break;
3009         /*
3010          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3011          * while i915 HW rotation is clockwise, thats why this swapping.
3012          */
3013         case BIT(DRM_ROTATE_90):
3014                 return PLANE_CTL_ROTATE_270;
3015         case BIT(DRM_ROTATE_180):
3016                 return PLANE_CTL_ROTATE_180;
3017         case BIT(DRM_ROTATE_270):
3018                 return PLANE_CTL_ROTATE_90;
3019         default:
3020                 MISSING_CASE(rotation);
3021         }
3022
3023         return 0;
3024 }
3025
3026 static void skylake_update_primary_plane(struct drm_plane *plane,
3027                                          const struct intel_crtc_state *crtc_state,
3028                                          const struct intel_plane_state *plane_state)
3029 {
3030         struct drm_device *dev = plane->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3033         struct drm_framebuffer *fb = plane_state->base.fb;
3034         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3035         int pipe = intel_crtc->pipe;
3036         u32 plane_ctl, stride_div, stride;
3037         u32 tile_height, plane_offset, plane_size;
3038         unsigned int rotation = plane_state->base.rotation;
3039         int x_offset, y_offset;
3040         u32 surf_addr;
3041         int scaler_id = plane_state->scaler_id;
3042         int src_x = plane_state->src.x1 >> 16;
3043         int src_y = plane_state->src.y1 >> 16;
3044         int src_w = drm_rect_width(&plane_state->src) >> 16;
3045         int src_h = drm_rect_height(&plane_state->src) >> 16;
3046         int dst_x = plane_state->dst.x1;
3047         int dst_y = plane_state->dst.y1;
3048         int dst_w = drm_rect_width(&plane_state->dst);
3049         int dst_h = drm_rect_height(&plane_state->dst);
3050
3051         plane_ctl = PLANE_CTL_ENABLE |
3052                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3053                     PLANE_CTL_PIPE_CSC_ENABLE;
3054
3055         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3056         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3057         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3058         plane_ctl |= skl_plane_ctl_rotation(rotation);
3059
3060         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3061                                                fb->pixel_format);
3062         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3063
3064         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3065
3066         if (intel_rotation_90_or_270(rotation)) {
3067                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3068
3069                 /* stride = Surface height in tiles */
3070                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3071                 stride = DIV_ROUND_UP(fb->height, tile_height);
3072                 x_offset = stride * tile_height - src_y - src_h;
3073                 y_offset = src_x;
3074                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3075         } else {
3076                 stride = fb->pitches[0] / stride_div;
3077                 x_offset = src_x;
3078                 y_offset = src_y;
3079                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3080         }
3081         plane_offset = y_offset << 16 | x_offset;
3082
3083         intel_crtc->adjusted_x = x_offset;
3084         intel_crtc->adjusted_y = y_offset;
3085
3086         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3087         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3088         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3089         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3090
3091         if (scaler_id >= 0) {
3092                 uint32_t ps_ctrl = 0;
3093
3094                 WARN_ON(!dst_w || !dst_h);
3095                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3096                         crtc_state->scaler_state.scalers[scaler_id].mode;
3097                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3098                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3099                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3100                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3101                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3102         } else {
3103                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3104         }
3105
3106         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3107
3108         POSTING_READ(PLANE_SURF(pipe, 0));
3109 }
3110
3111 static void skylake_disable_primary_plane(struct drm_plane *primary,
3112                                           struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int pipe = to_intel_crtc(crtc)->pipe;
3117
3118         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3119         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3120         POSTING_READ(PLANE_SURF(pipe, 0));
3121 }
3122
3123 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3124 static int
3125 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3126                            int x, int y, enum mode_set_atomic state)
3127 {
3128         /* Support for kgdboc is disabled, this needs a major rework. */
3129         DRM_ERROR("legacy panic handler not supported any more.\n");
3130
3131         return -ENODEV;
3132 }
3133
3134 static void intel_complete_page_flips(struct drm_device *dev)
3135 {
3136         struct drm_crtc *crtc;
3137
3138         for_each_crtc(dev, crtc) {
3139                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3140                 enum plane plane = intel_crtc->plane;
3141
3142                 intel_prepare_page_flip(dev, plane);
3143                 intel_finish_page_flip_plane(dev, plane);
3144         }
3145 }
3146
3147 static void intel_update_primary_planes(struct drm_device *dev)
3148 {
3149         struct drm_crtc *crtc;
3150
3151         for_each_crtc(dev, crtc) {
3152                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3153                 struct intel_plane_state *plane_state;
3154
3155                 drm_modeset_lock_crtc(crtc, &plane->base);
3156                 plane_state = to_intel_plane_state(plane->base.state);
3157
3158                 if (plane_state->visible)
3159                         plane->update_plane(&plane->base,
3160                                             to_intel_crtc_state(crtc->state),
3161                                             plane_state);
3162
3163                 drm_modeset_unlock_crtc(crtc);
3164         }
3165 }
3166
3167 void intel_prepare_reset(struct drm_device *dev)
3168 {
3169         /* no reset support for gen2 */
3170         if (IS_GEN2(dev))
3171                 return;
3172
3173         /* reset doesn't touch the display */
3174         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3175                 return;
3176
3177         drm_modeset_lock_all(dev);
3178         /*
3179          * Disabling the crtcs gracefully seems nicer. Also the
3180          * g33 docs say we should at least disable all the planes.
3181          */
3182         intel_display_suspend(dev);
3183 }
3184
3185 void intel_finish_reset(struct drm_device *dev)
3186 {
3187         struct drm_i915_private *dev_priv = to_i915(dev);
3188
3189         /*
3190          * Flips in the rings will be nuked by the reset,
3191          * so complete all pending flips so that user space
3192          * will get its events and not get stuck.
3193          */
3194         intel_complete_page_flips(dev);
3195
3196         /* no reset support for gen2 */
3197         if (IS_GEN2(dev))
3198                 return;
3199
3200         /* reset doesn't touch the display */
3201         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3202                 /*
3203                  * Flips in the rings have been nuked by the reset,
3204                  * so update the base address of all primary
3205                  * planes to the the last fb to make sure we're
3206                  * showing the correct fb after a reset.
3207                  *
3208                  * FIXME: Atomic will make this obsolete since we won't schedule
3209                  * CS-based flips (which might get lost in gpu resets) any more.
3210                  */
3211                 intel_update_primary_planes(dev);
3212                 return;
3213         }
3214
3215         /*
3216          * The display has been reset as well,
3217          * so need a full re-initialization.
3218          */
3219         intel_runtime_pm_disable_interrupts(dev_priv);
3220         intel_runtime_pm_enable_interrupts(dev_priv);
3221
3222         intel_modeset_init_hw(dev);
3223
3224         spin_lock_irq(&dev_priv->irq_lock);
3225         if (dev_priv->display.hpd_irq_setup)
3226                 dev_priv->display.hpd_irq_setup(dev);
3227         spin_unlock_irq(&dev_priv->irq_lock);
3228
3229         intel_display_resume(dev);
3230
3231         intel_hpd_init(dev_priv);
3232
3233         drm_modeset_unlock_all(dev);
3234 }
3235
3236 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         bool pending;
3242
3243         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3244             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3245                 return false;
3246
3247         spin_lock_irq(&dev->event_lock);
3248         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3249         spin_unlock_irq(&dev->event_lock);
3250
3251         return pending;
3252 }
3253
3254 static void intel_update_pipe_config(struct intel_crtc *crtc,
3255                                      struct intel_crtc_state *old_crtc_state)
3256 {
3257         struct drm_device *dev = crtc->base.dev;
3258         struct drm_i915_private *dev_priv = dev->dev_private;
3259         struct intel_crtc_state *pipe_config =
3260                 to_intel_crtc_state(crtc->base.state);
3261
3262         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3263         crtc->base.mode = crtc->base.state->mode;
3264
3265         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3266                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3267                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3268
3269         if (HAS_DDI(dev))
3270                 intel_set_pipe_csc(&crtc->base);
3271
3272         /*
3273          * Update pipe size and adjust fitter if needed: the reason for this is
3274          * that in compute_mode_changes we check the native mode (not the pfit
3275          * mode) to see if we can flip rather than do a full mode set. In the
3276          * fastboot case, we'll flip, but if we don't update the pipesrc and
3277          * pfit state, we'll end up with a big fb scanned out into the wrong
3278          * sized surface.
3279          */
3280
3281         I915_WRITE(PIPESRC(crtc->pipe),
3282                    ((pipe_config->pipe_src_w - 1) << 16) |
3283                    (pipe_config->pipe_src_h - 1));
3284
3285         /* on skylake this is done by detaching scalers */
3286         if (INTEL_INFO(dev)->gen >= 9) {
3287                 skl_detach_scalers(crtc);
3288
3289                 if (pipe_config->pch_pfit.enabled)
3290                         skylake_pfit_enable(crtc);
3291         } else if (HAS_PCH_SPLIT(dev)) {
3292                 if (pipe_config->pch_pfit.enabled)
3293                         ironlake_pfit_enable(crtc);
3294                 else if (old_crtc_state->pch_pfit.enabled)
3295                         ironlake_pfit_disable(crtc, true);
3296         }
3297 }
3298
3299 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3300 {
3301         struct drm_device *dev = crtc->dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304         int pipe = intel_crtc->pipe;
3305         i915_reg_t reg;
3306         u32 temp;
3307
3308         /* enable normal train */
3309         reg = FDI_TX_CTL(pipe);
3310         temp = I915_READ(reg);
3311         if (IS_IVYBRIDGE(dev)) {
3312                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3313                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3314         } else {
3315                 temp &= ~FDI_LINK_TRAIN_NONE;
3316                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3317         }
3318         I915_WRITE(reg, temp);
3319
3320         reg = FDI_RX_CTL(pipe);
3321         temp = I915_READ(reg);
3322         if (HAS_PCH_CPT(dev)) {
3323                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3324                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3325         } else {
3326                 temp &= ~FDI_LINK_TRAIN_NONE;
3327                 temp |= FDI_LINK_TRAIN_NONE;
3328         }
3329         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3330
3331         /* wait one idle pattern time */
3332         POSTING_READ(reg);
3333         udelay(1000);
3334
3335         /* IVB wants error correction enabled */
3336         if (IS_IVYBRIDGE(dev))
3337                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3338                            FDI_FE_ERRC_ENABLE);
3339 }
3340
3341 /* The FDI link training functions for ILK/Ibexpeak. */
3342 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3343 {
3344         struct drm_device *dev = crtc->dev;
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347         int pipe = intel_crtc->pipe;
3348         i915_reg_t reg;
3349         u32 temp, tries;
3350
3351         /* FDI needs bits from pipe first */
3352         assert_pipe_enabled(dev_priv, pipe);
3353
3354         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3355            for train result */
3356         reg = FDI_RX_IMR(pipe);
3357         temp = I915_READ(reg);
3358         temp &= ~FDI_RX_SYMBOL_LOCK;
3359         temp &= ~FDI_RX_BIT_LOCK;
3360         I915_WRITE(reg, temp);
3361         I915_READ(reg);
3362         udelay(150);
3363
3364         /* enable CPU FDI TX and PCH FDI RX */
3365         reg = FDI_TX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3368         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_1;
3371         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3372
3373         reg = FDI_RX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         temp &= ~FDI_LINK_TRAIN_NONE;
3376         temp |= FDI_LINK_TRAIN_PATTERN_1;
3377         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379         POSTING_READ(reg);
3380         udelay(150);
3381
3382         /* Ironlake workaround, enable clock pointer after FDI enable*/
3383         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3384         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3385                    FDI_RX_PHASE_SYNC_POINTER_EN);
3386
3387         reg = FDI_RX_IIR(pipe);
3388         for (tries = 0; tries < 5; tries++) {
3389                 temp = I915_READ(reg);
3390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391
3392                 if ((temp & FDI_RX_BIT_LOCK)) {
3393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3395                         break;
3396                 }
3397         }
3398         if (tries == 5)
3399                 DRM_ERROR("FDI train 1 fail!\n");
3400
3401         /* Train 2 */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_2;
3406         I915_WRITE(reg, temp);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_LINK_TRAIN_NONE;
3411         temp |= FDI_LINK_TRAIN_PATTERN_2;
3412         I915_WRITE(reg, temp);
3413
3414         POSTING_READ(reg);
3415         udelay(150);
3416
3417         reg = FDI_RX_IIR(pipe);
3418         for (tries = 0; tries < 5; tries++) {
3419                 temp = I915_READ(reg);
3420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422                 if (temp & FDI_RX_SYMBOL_LOCK) {
3423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3425                         break;
3426                 }
3427         }
3428         if (tries == 5)
3429                 DRM_ERROR("FDI train 2 fail!\n");
3430
3431         DRM_DEBUG_KMS("FDI train done\n");
3432
3433 }
3434
3435 static const int snb_b_fdi_train_param[] = {
3436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3440 };
3441
3442 /* The FDI link training functions for SNB/Cougarpoint. */
3443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_private *dev_priv = dev->dev_private;
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449         i915_reg_t reg;
3450         u32 temp, i, retry;
3451
3452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453            for train result */
3454         reg = FDI_RX_IMR(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_RX_SYMBOL_LOCK;
3457         temp &= ~FDI_RX_BIT_LOCK;
3458         I915_WRITE(reg, temp);
3459
3460         POSTING_READ(reg);
3461         udelay(150);
3462
3463         /* enable CPU FDI TX and PCH FDI RX */
3464         reg = FDI_TX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3467         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3468         temp &= ~FDI_LINK_TRAIN_NONE;
3469         temp |= FDI_LINK_TRAIN_PATTERN_1;
3470         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471         /* SNB-B */
3472         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3473         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3474
3475         I915_WRITE(FDI_RX_MISC(pipe),
3476                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3477
3478         reg = FDI_RX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         if (HAS_PCH_CPT(dev)) {
3481                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3482                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483         } else {
3484                 temp &= ~FDI_LINK_TRAIN_NONE;
3485                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486         }
3487         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3488
3489         POSTING_READ(reg);
3490         udelay(150);
3491
3492         for (i = 0; i < 4; i++) {
3493                 reg = FDI_TX_CTL(pipe);
3494                 temp = I915_READ(reg);
3495                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3496                 temp |= snb_b_fdi_train_param[i];
3497                 I915_WRITE(reg, temp);
3498
3499                 POSTING_READ(reg);
3500                 udelay(500);
3501
3502                 for (retry = 0; retry < 5; retry++) {
3503                         reg = FDI_RX_IIR(pipe);
3504                         temp = I915_READ(reg);
3505                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3506                         if (temp & FDI_RX_BIT_LOCK) {
3507                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3508                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3509                                 break;
3510                         }
3511                         udelay(50);
3512                 }
3513                 if (retry < 5)
3514                         break;
3515         }
3516         if (i == 4)
3517                 DRM_ERROR("FDI train 1 fail!\n");
3518
3519         /* Train 2 */
3520         reg = FDI_TX_CTL(pipe);
3521         temp = I915_READ(reg);
3522         temp &= ~FDI_LINK_TRAIN_NONE;
3523         temp |= FDI_LINK_TRAIN_PATTERN_2;
3524         if (IS_GEN6(dev)) {
3525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526                 /* SNB-B */
3527                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3528         }
3529         I915_WRITE(reg, temp);
3530
3531         reg = FDI_RX_CTL(pipe);
3532         temp = I915_READ(reg);
3533         if (HAS_PCH_CPT(dev)) {
3534                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3536         } else {
3537                 temp &= ~FDI_LINK_TRAIN_NONE;
3538                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3539         }
3540         I915_WRITE(reg, temp);
3541
3542         POSTING_READ(reg);
3543         udelay(150);
3544
3545         for (i = 0; i < 4; i++) {
3546                 reg = FDI_TX_CTL(pipe);
3547                 temp = I915_READ(reg);
3548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549                 temp |= snb_b_fdi_train_param[i];
3550                 I915_WRITE(reg, temp);
3551
3552                 POSTING_READ(reg);
3553                 udelay(500);
3554
3555                 for (retry = 0; retry < 5; retry++) {
3556                         reg = FDI_RX_IIR(pipe);
3557                         temp = I915_READ(reg);
3558                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3559                         if (temp & FDI_RX_SYMBOL_LOCK) {
3560                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3561                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3562                                 break;
3563                         }
3564                         udelay(50);
3565                 }
3566                 if (retry < 5)
3567                         break;
3568         }
3569         if (i == 4)
3570                 DRM_ERROR("FDI train 2 fail!\n");
3571
3572         DRM_DEBUG_KMS("FDI train done.\n");
3573 }
3574
3575 /* Manual link training for Ivy Bridge A0 parts */
3576 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581         int pipe = intel_crtc->pipe;
3582         i915_reg_t reg;
3583         u32 temp, i, j;
3584
3585         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3586            for train result */
3587         reg = FDI_RX_IMR(pipe);
3588         temp = I915_READ(reg);
3589         temp &= ~FDI_RX_SYMBOL_LOCK;
3590         temp &= ~FDI_RX_BIT_LOCK;
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3597                       I915_READ(FDI_RX_IIR(pipe)));
3598
3599         /* Try each vswing and preemphasis setting twice before moving on */
3600         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3601                 /* disable first in case we need to retry */
3602                 reg = FDI_TX_CTL(pipe);
3603                 temp = I915_READ(reg);
3604                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3605                 temp &= ~FDI_TX_ENABLE;
3606                 I915_WRITE(reg, temp);
3607
3608                 reg = FDI_RX_CTL(pipe);
3609                 temp = I915_READ(reg);
3610                 temp &= ~FDI_LINK_TRAIN_AUTO;
3611                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3612                 temp &= ~FDI_RX_ENABLE;
3613                 I915_WRITE(reg, temp);
3614
3615                 /* enable CPU FDI TX and PCH FDI RX */
3616                 reg = FDI_TX_CTL(pipe);
3617                 temp = I915_READ(reg);
3618                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3619                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3620                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3622                 temp |= snb_b_fdi_train_param[j/2];
3623                 temp |= FDI_COMPOSITE_SYNC;
3624                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3625
3626                 I915_WRITE(FDI_RX_MISC(pipe),
3627                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3628
3629                 reg = FDI_RX_CTL(pipe);
3630                 temp = I915_READ(reg);
3631                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3632                 temp |= FDI_COMPOSITE_SYNC;
3633                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3634
3635                 POSTING_READ(reg);
3636                 udelay(1); /* should be 0.5us */
3637
3638                 for (i = 0; i < 4; i++) {
3639                         reg = FDI_RX_IIR(pipe);
3640                         temp = I915_READ(reg);
3641                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3642
3643                         if (temp & FDI_RX_BIT_LOCK ||
3644                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3645                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3646                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3647                                               i);
3648                                 break;
3649                         }
3650                         udelay(1); /* should be 0.5us */
3651                 }
3652                 if (i == 4) {
3653                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3654                         continue;
3655                 }
3656
3657                 /* Train 2 */
3658                 reg = FDI_TX_CTL(pipe);
3659                 temp = I915_READ(reg);
3660                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3661                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3662                 I915_WRITE(reg, temp);
3663
3664                 reg = FDI_RX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3667                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3668                 I915_WRITE(reg, temp);
3669
3670                 POSTING_READ(reg);
3671                 udelay(2); /* should be 1.5us */
3672
3673                 for (i = 0; i < 4; i++) {
3674                         reg = FDI_RX_IIR(pipe);
3675                         temp = I915_READ(reg);
3676                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678                         if (temp & FDI_RX_SYMBOL_LOCK ||
3679                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3680                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3681                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3682                                               i);
3683                                 goto train_done;
3684                         }
3685                         udelay(2); /* should be 1.5us */
3686                 }
3687                 if (i == 4)
3688                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3689         }
3690
3691 train_done:
3692         DRM_DEBUG_KMS("FDI train done.\n");
3693 }
3694
3695 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3696 {
3697         struct drm_device *dev = intel_crtc->base.dev;
3698         struct drm_i915_private *dev_priv = dev->dev_private;
3699         int pipe = intel_crtc->pipe;
3700         i915_reg_t reg;
3701         u32 temp;
3702
3703         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3704         reg = FDI_RX_CTL(pipe);
3705         temp = I915_READ(reg);
3706         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3707         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3708         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3709         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3710
3711         POSTING_READ(reg);
3712         udelay(200);
3713
3714         /* Switch from Rawclk to PCDclk */
3715         temp = I915_READ(reg);
3716         I915_WRITE(reg, temp | FDI_PCDCLK);
3717
3718         POSTING_READ(reg);
3719         udelay(200);
3720
3721         /* Enable CPU FDI TX PLL, always on for Ironlake */
3722         reg = FDI_TX_CTL(pipe);
3723         temp = I915_READ(reg);
3724         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3725                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3726
3727                 POSTING_READ(reg);
3728                 udelay(100);
3729         }
3730 }
3731
3732 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3733 {
3734         struct drm_device *dev = intel_crtc->base.dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         int pipe = intel_crtc->pipe;
3737         i915_reg_t reg;
3738         u32 temp;
3739
3740         /* Switch from PCDclk to Rawclk */
3741         reg = FDI_RX_CTL(pipe);
3742         temp = I915_READ(reg);
3743         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3744
3745         /* Disable CPU FDI TX PLL */
3746         reg = FDI_TX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3749
3750         POSTING_READ(reg);
3751         udelay(100);
3752
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3756
3757         /* Wait for the clocks to turn off. */
3758         POSTING_READ(reg);
3759         udelay(100);
3760 }
3761
3762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         int pipe = intel_crtc->pipe;
3768         i915_reg_t reg;
3769         u32 temp;
3770
3771         /* disable CPU FDI tx and PCH FDI rx */
3772         reg = FDI_TX_CTL(pipe);
3773         temp = I915_READ(reg);
3774         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3775         POSTING_READ(reg);
3776
3777         reg = FDI_RX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~(0x7 << 16);
3780         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3781         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3782
3783         POSTING_READ(reg);
3784         udelay(100);
3785
3786         /* Ironlake workaround, disable clock pointer after downing FDI */
3787         if (HAS_PCH_IBX(dev))
3788                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3789
3790         /* still set train pattern 1 */
3791         reg = FDI_TX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         temp &= ~FDI_LINK_TRAIN_NONE;
3794         temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         I915_WRITE(reg, temp);
3796
3797         reg = FDI_RX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         if (HAS_PCH_CPT(dev)) {
3800                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3801                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3802         } else {
3803                 temp &= ~FDI_LINK_TRAIN_NONE;
3804                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3805         }
3806         /* BPC in FDI rx is consistent with that in PIPECONF */
3807         temp &= ~(0x07 << 16);
3808         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3809         I915_WRITE(reg, temp);
3810
3811         POSTING_READ(reg);
3812         udelay(100);
3813 }
3814
3815 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3816 {
3817         struct intel_crtc *crtc;
3818
3819         /* Note that we don't need to be called with mode_config.lock here
3820          * as our list of CRTC objects is static for the lifetime of the
3821          * device and so cannot disappear as we iterate. Similarly, we can
3822          * happily treat the predicates as racy, atomic checks as userspace
3823          * cannot claim and pin a new fb without at least acquring the
3824          * struct_mutex and so serialising with us.
3825          */
3826         for_each_intel_crtc(dev, crtc) {
3827                 if (atomic_read(&crtc->unpin_work_count) == 0)
3828                         continue;
3829
3830                 if (crtc->unpin_work)
3831                         intel_wait_for_vblank(dev, crtc->pipe);
3832
3833                 return true;
3834         }
3835
3836         return false;
3837 }
3838
3839 static void page_flip_completed(struct intel_crtc *intel_crtc)
3840 {
3841         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3842         struct intel_unpin_work *work = intel_crtc->unpin_work;
3843
3844         /* ensure that the unpin work is consistent wrt ->pending. */
3845         smp_rmb();
3846         intel_crtc->unpin_work = NULL;
3847
3848         if (work->event)
3849                 drm_send_vblank_event(intel_crtc->base.dev,
3850                                       intel_crtc->pipe,
3851                                       work->event);
3852
3853         drm_crtc_vblank_put(&intel_crtc->base);
3854
3855         wake_up_all(&dev_priv->pending_flip_queue);
3856         queue_work(dev_priv->wq, &work->work);
3857
3858         trace_i915_flip_complete(intel_crtc->plane,
3859                                  work->pending_flip_obj);
3860 }
3861
3862 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3863 {
3864         struct drm_device *dev = crtc->dev;
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         long ret;
3867
3868         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3869
3870         ret = wait_event_interruptible_timeout(
3871                                         dev_priv->pending_flip_queue,
3872                                         !intel_crtc_has_pending_flip(crtc),
3873                                         60*HZ);
3874
3875         if (ret < 0)
3876                 return ret;
3877
3878         if (ret == 0) {
3879                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880
3881                 spin_lock_irq(&dev->event_lock);
3882                 if (intel_crtc->unpin_work) {
3883                         WARN_ONCE(1, "Removing stuck page flip\n");
3884                         page_flip_completed(intel_crtc);
3885                 }
3886                 spin_unlock_irq(&dev->event_lock);
3887         }
3888
3889         return 0;
3890 }
3891
3892 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3893 {
3894         u32 temp;
3895
3896         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3897
3898         mutex_lock(&dev_priv->sb_lock);
3899
3900         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3901         temp |= SBI_SSCCTL_DISABLE;
3902         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3903
3904         mutex_unlock(&dev_priv->sb_lock);
3905 }
3906
3907 /* Program iCLKIP clock to the desired frequency */
3908 static void lpt_program_iclkip(struct drm_crtc *crtc)
3909 {
3910         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3911         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3912         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3913         u32 temp;
3914
3915         lpt_disable_iclkip(dev_priv);
3916
3917         /* The iCLK virtual clock root frequency is in MHz,
3918          * but the adjusted_mode->crtc_clock in in KHz. To get the
3919          * divisors, it is necessary to divide one by another, so we
3920          * convert the virtual clock precision to KHz here for higher
3921          * precision.
3922          */
3923         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3924                 u32 iclk_virtual_root_freq = 172800 * 1000;
3925                 u32 iclk_pi_range = 64;
3926                 u32 desired_divisor;
3927
3928                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3929                                                     clock << auxdiv);
3930                 divsel = (desired_divisor / iclk_pi_range) - 2;
3931                 phaseinc = desired_divisor % iclk_pi_range;
3932
3933                 /*
3934                  * Near 20MHz is a corner case which is
3935                  * out of range for the 7-bit divisor
3936                  */
3937                 if (divsel <= 0x7f)
3938                         break;
3939         }
3940
3941         /* This should not happen with any sane values */
3942         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3943                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3944         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3945                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3946
3947         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3948                         clock,
3949                         auxdiv,
3950                         divsel,
3951                         phasedir,
3952                         phaseinc);
3953
3954         mutex_lock(&dev_priv->sb_lock);
3955
3956         /* Program SSCDIVINTPHASE6 */
3957         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3958         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3959         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3960         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3961         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3962         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3963         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3964         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3965
3966         /* Program SSCAUXDIV */
3967         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3968         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3969         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3970         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3971
3972         /* Enable modulator and associated divider */
3973         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3974         temp &= ~SBI_SSCCTL_DISABLE;
3975         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3976
3977         mutex_unlock(&dev_priv->sb_lock);
3978
3979         /* Wait for initialization time */
3980         udelay(24);
3981
3982         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3983 }
3984
3985 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3986 {
3987         u32 divsel, phaseinc, auxdiv;
3988         u32 iclk_virtual_root_freq = 172800 * 1000;
3989         u32 iclk_pi_range = 64;
3990         u32 desired_divisor;
3991         u32 temp;
3992
3993         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3994                 return 0;
3995
3996         mutex_lock(&dev_priv->sb_lock);
3997
3998         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999         if (temp & SBI_SSCCTL_DISABLE) {
4000                 mutex_unlock(&dev_priv->sb_lock);
4001                 return 0;
4002         }
4003
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4006                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4007         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4008                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4009
4010         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4011         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4012                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4013
4014         mutex_unlock(&dev_priv->sb_lock);
4015
4016         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4017
4018         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4019                                  desired_divisor << auxdiv);
4020 }
4021
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023                                                 enum pipe pch_transcoder)
4024 {
4025         struct drm_device *dev = crtc->base.dev;
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028
4029         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030                    I915_READ(HTOTAL(cpu_transcoder)));
4031         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032                    I915_READ(HBLANK(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034                    I915_READ(HSYNC(cpu_transcoder)));
4035
4036         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037                    I915_READ(VTOTAL(cpu_transcoder)));
4038         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039                    I915_READ(VBLANK(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041                    I915_READ(VSYNC(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044 }
4045
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         uint32_t temp;
4050
4051         temp = I915_READ(SOUTH_CHICKEN1);
4052         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4053                 return;
4054
4055         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
4058         temp &= ~FDI_BC_BIFURCATION_SELECT;
4059         if (enable)
4060                 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4063         I915_WRITE(SOUTH_CHICKEN1, temp);
4064         POSTING_READ(SOUTH_CHICKEN1);
4065 }
4066
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 {
4069         struct drm_device *dev = intel_crtc->base.dev;
4070
4071         switch (intel_crtc->pipe) {
4072         case PIPE_A:
4073                 break;
4074         case PIPE_B:
4075                 if (intel_crtc->config->fdi_lanes > 2)
4076                         cpt_set_fdi_bc_bifurcation(dev, false);
4077                 else
4078                         cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080                 break;
4081         case PIPE_C:
4082                 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084                 break;
4085         default:
4086                 BUG();
4087         }
4088 }
4089
4090 /* Return which DP Port should be selected for Transcoder DP control */
4091 static enum port
4092 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4093 {
4094         struct drm_device *dev = crtc->dev;
4095         struct intel_encoder *encoder;
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder) {
4098                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4099                     encoder->type == INTEL_OUTPUT_EDP)
4100                         return enc_to_dig_port(&encoder->base)->port;
4101         }
4102
4103         return -1;
4104 }
4105
4106 /*
4107  * Enable PCH resources required for PCH ports:
4108  *   - PCH PLLs
4109  *   - FDI training & RX/TX
4110  *   - update transcoder timings
4111  *   - DP transcoding bits
4112  *   - transcoder
4113  */
4114 static void ironlake_pch_enable(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120         u32 temp;
4121
4122         assert_pch_transcoder_disabled(dev_priv, pipe);
4123
4124         if (IS_IVYBRIDGE(dev))
4125                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4126
4127         /* Write the TU size bits before fdi link training, so that error
4128          * detection works. */
4129         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4130                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4131
4132         /*
4133          * Sometimes spurious CPU pipe underruns happen during FDI
4134          * training, at least with VGA+HDMI cloning. Suppress them.
4135          */
4136         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4137
4138         /* For PCH output, training FDI link */
4139         dev_priv->display.fdi_link_train(crtc);
4140
4141         /* We need to program the right clock selection before writing the pixel
4142          * mutliplier into the DPLL. */
4143         if (HAS_PCH_CPT(dev)) {
4144                 u32 sel;
4145
4146                 temp = I915_READ(PCH_DPLL_SEL);
4147                 temp |= TRANS_DPLL_ENABLE(pipe);
4148                 sel = TRANS_DPLLB_SEL(pipe);
4149                 if (intel_crtc->config->shared_dpll ==
4150                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4151                         temp |= sel;
4152                 else
4153                         temp &= ~sel;
4154                 I915_WRITE(PCH_DPLL_SEL, temp);
4155         }
4156
4157         /* XXX: pch pll's can be enabled any time before we enable the PCH
4158          * transcoder, and we actually should do this to not upset any PCH
4159          * transcoder that already use the clock when we share it.
4160          *
4161          * Note that enable_shared_dpll tries to do the right thing, but
4162          * get_shared_dpll unconditionally resets the pll - we need that to have
4163          * the right LVDS enable sequence. */
4164         intel_enable_shared_dpll(intel_crtc);
4165
4166         /* set transcoder timing, panel must allow it */
4167         assert_panel_unlocked(dev_priv, pipe);
4168         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4169
4170         intel_fdi_normal_train(crtc);
4171
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173
4174         /* For PCH DP, enable TRANS_DP_CTL */
4175         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4176                 const struct drm_display_mode *adjusted_mode =
4177                         &intel_crtc->config->base.adjusted_mode;
4178                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4179                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4180                 temp = I915_READ(reg);
4181                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4182                           TRANS_DP_SYNC_MASK |
4183                           TRANS_DP_BPC_MASK);
4184                 temp |= TRANS_DP_OUTPUT_ENABLE;
4185                 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4188                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4190                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192                 switch (intel_trans_dp_port_sel(crtc)) {
4193                 case PORT_B:
4194                         temp |= TRANS_DP_PORT_SEL_B;
4195                         break;
4196                 case PORT_C:
4197                         temp |= TRANS_DP_PORT_SEL_C;
4198                         break;
4199                 case PORT_D:
4200                         temp |= TRANS_DP_PORT_SEL_D;
4201                         break;
4202                 default:
4203                         BUG();
4204                 }
4205
4206                 I915_WRITE(reg, temp);
4207         }
4208
4209         ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221         lpt_program_iclkip(crtc);
4222
4223         /* Set transcoder timing. */
4224         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4230 {
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         i915_reg_t dslreg = PIPEDSL(pipe);
4233         u32 temp;
4234
4235         temp = I915_READ(dslreg);
4236         udelay(500);
4237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4238                 if (wait_for(I915_READ(dslreg) != temp, 5))
4239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4240         }
4241 }
4242
4243 static int
4244 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4245                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4246                   int src_w, int src_h, int dst_w, int dst_h)
4247 {
4248         struct intel_crtc_scaler_state *scaler_state =
4249                 &crtc_state->scaler_state;
4250         struct intel_crtc *intel_crtc =
4251                 to_intel_crtc(crtc_state->base.crtc);
4252         int need_scaling;
4253
4254         need_scaling = intel_rotation_90_or_270(rotation) ?
4255                 (src_h != dst_w || src_w != dst_h):
4256                 (src_w != dst_w || src_h != dst_h);
4257
4258         /*
4259          * if plane is being disabled or scaler is no more required or force detach
4260          *  - free scaler binded to this plane/crtc
4261          *  - in order to do this, update crtc->scaler_usage
4262          *
4263          * Here scaler state in crtc_state is set free so that
4264          * scaler can be assigned to other user. Actual register
4265          * update to free the scaler is done in plane/panel-fit programming.
4266          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4267          */
4268         if (force_detach || !need_scaling) {
4269                 if (*scaler_id >= 0) {
4270                         scaler_state->scaler_users &= ~(1 << scaler_user);
4271                         scaler_state->scalers[*scaler_id].in_use = 0;
4272
4273                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4274                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4275                                 intel_crtc->pipe, scaler_user, *scaler_id,
4276                                 scaler_state->scaler_users);
4277                         *scaler_id = -1;
4278                 }
4279                 return 0;
4280         }
4281
4282         /* range checks */
4283         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4284                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4285
4286                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4287                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4288                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4289                         "size is out of scaler range\n",
4290                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4291                 return -EINVAL;
4292         }
4293
4294         /* mark this plane as a scaler user in crtc_state */
4295         scaler_state->scaler_users |= (1 << scaler_user);
4296         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4297                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4298                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4299                 scaler_state->scaler_users);
4300
4301         return 0;
4302 }
4303
4304 /**
4305  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4306  *
4307  * @state: crtc's scaler state
4308  *
4309  * Return
4310  *     0 - scaler_usage updated successfully
4311  *    error - requested scaling cannot be supported or other error condition
4312  */
4313 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4314 {
4315         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4316         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4317
4318         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4319                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4320
4321         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4322                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4323                 state->pipe_src_w, state->pipe_src_h,
4324                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4325 }
4326
4327 /**
4328  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4329  *
4330  * @state: crtc's scaler state
4331  * @plane_state: atomic plane state to update
4332  *
4333  * Return
4334  *     0 - scaler_usage updated successfully
4335  *    error - requested scaling cannot be supported or other error condition
4336  */
4337 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4338                                    struct intel_plane_state *plane_state)
4339 {
4340
4341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4342         struct intel_plane *intel_plane =
4343                 to_intel_plane(plane_state->base.plane);
4344         struct drm_framebuffer *fb = plane_state->base.fb;
4345         int ret;
4346
4347         bool force_detach = !fb || !plane_state->visible;
4348
4349         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4350                       intel_plane->base.base.id, intel_crtc->pipe,
4351                       drm_plane_index(&intel_plane->base));
4352
4353         ret = skl_update_scaler(crtc_state, force_detach,
4354                                 drm_plane_index(&intel_plane->base),
4355                                 &plane_state->scaler_id,
4356                                 plane_state->base.rotation,
4357                                 drm_rect_width(&plane_state->src) >> 16,
4358                                 drm_rect_height(&plane_state->src) >> 16,
4359                                 drm_rect_width(&plane_state->dst),
4360                                 drm_rect_height(&plane_state->dst));
4361
4362         if (ret || plane_state->scaler_id < 0)
4363                 return ret;
4364
4365         /* check colorkey */
4366         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4367                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4368                               intel_plane->base.base.id);
4369                 return -EINVAL;
4370         }
4371
4372         /* Check src format */
4373         switch (fb->pixel_format) {
4374         case DRM_FORMAT_RGB565:
4375         case DRM_FORMAT_XBGR8888:
4376         case DRM_FORMAT_XRGB8888:
4377         case DRM_FORMAT_ABGR8888:
4378         case DRM_FORMAT_ARGB8888:
4379         case DRM_FORMAT_XRGB2101010:
4380         case DRM_FORMAT_XBGR2101010:
4381         case DRM_FORMAT_YUYV:
4382         case DRM_FORMAT_YVYU:
4383         case DRM_FORMAT_UYVY:
4384         case DRM_FORMAT_VYUY:
4385                 break;
4386         default:
4387                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4388                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4389                 return -EINVAL;
4390         }
4391
4392         return 0;
4393 }
4394
4395 static void skylake_scaler_disable(struct intel_crtc *crtc)
4396 {
4397         int i;
4398
4399         for (i = 0; i < crtc->num_scalers; i++)
4400                 skl_detach_scaler(crtc, i);
4401 }
4402
4403 static void skylake_pfit_enable(struct intel_crtc *crtc)
4404 {
4405         struct drm_device *dev = crtc->base.dev;
4406         struct drm_i915_private *dev_priv = dev->dev_private;
4407         int pipe = crtc->pipe;
4408         struct intel_crtc_scaler_state *scaler_state =
4409                 &crtc->config->scaler_state;
4410
4411         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4412
4413         if (crtc->config->pch_pfit.enabled) {
4414                 int id;
4415
4416                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4417                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4418                         return;
4419                 }
4420
4421                 id = scaler_state->scaler_id;
4422                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4423                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4424                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4425                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4426
4427                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4428         }
4429 }
4430
4431 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4432 {
4433         struct drm_device *dev = crtc->base.dev;
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         int pipe = crtc->pipe;
4436
4437         if (crtc->config->pch_pfit.enabled) {
4438                 /* Force use of hard-coded filter coefficients
4439                  * as some pre-programmed values are broken,
4440                  * e.g. x201.
4441                  */
4442                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4443                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4444                                                  PF_PIPE_SEL_IVB(pipe));
4445                 else
4446                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4447                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4448                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4449         }
4450 }
4451
4452 void hsw_enable_ips(struct intel_crtc *crtc)
4453 {
4454         struct drm_device *dev = crtc->base.dev;
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457         if (!crtc->config->ips_enabled)
4458                 return;
4459
4460         /* We can only enable IPS after we enable a plane and wait for a vblank */
4461         intel_wait_for_vblank(dev, crtc->pipe);
4462
4463         assert_plane_enabled(dev_priv, crtc->plane);
4464         if (IS_BROADWELL(dev)) {
4465                 mutex_lock(&dev_priv->rps.hw_lock);
4466                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4467                 mutex_unlock(&dev_priv->rps.hw_lock);
4468                 /* Quoting Art Runyan: "its not safe to expect any particular
4469                  * value in IPS_CTL bit 31 after enabling IPS through the
4470                  * mailbox." Moreover, the mailbox may return a bogus state,
4471                  * so we need to just enable it and continue on.
4472                  */
4473         } else {
4474                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4475                 /* The bit only becomes 1 in the next vblank, so this wait here
4476                  * is essentially intel_wait_for_vblank. If we don't have this
4477                  * and don't wait for vblanks until the end of crtc_enable, then
4478                  * the HW state readout code will complain that the expected
4479                  * IPS_CTL value is not the one we read. */
4480                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4481                         DRM_ERROR("Timed out waiting for IPS enable\n");
4482         }
4483 }
4484
4485 void hsw_disable_ips(struct intel_crtc *crtc)
4486 {
4487         struct drm_device *dev = crtc->base.dev;
4488         struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490         if (!crtc->config->ips_enabled)
4491                 return;
4492
4493         assert_plane_enabled(dev_priv, crtc->plane);
4494         if (IS_BROADWELL(dev)) {
4495                 mutex_lock(&dev_priv->rps.hw_lock);
4496                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4497                 mutex_unlock(&dev_priv->rps.hw_lock);
4498                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4499                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4500                         DRM_ERROR("Timed out waiting for IPS disable\n");
4501         } else {
4502                 I915_WRITE(IPS_CTL, 0);
4503                 POSTING_READ(IPS_CTL);
4504         }
4505
4506         /* We need to wait for a vblank before we can disable the plane. */
4507         intel_wait_for_vblank(dev, crtc->pipe);
4508 }
4509
4510 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4511 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516         enum pipe pipe = intel_crtc->pipe;
4517         int i;
4518         bool reenable_ips = false;
4519
4520         /* The clocks have to be on to load the palette. */
4521         if (!crtc->state->active)
4522                 return;
4523
4524         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4525                 if (intel_crtc->config->has_dsi_encoder)
4526                         assert_dsi_pll_enabled(dev_priv);
4527                 else
4528                         assert_pll_enabled(dev_priv, pipe);
4529         }
4530
4531         /* Workaround : Do not read or write the pipe palette/gamma data while
4532          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4533          */
4534         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4535             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4536              GAMMA_MODE_MODE_SPLIT)) {
4537                 hsw_disable_ips(intel_crtc);
4538                 reenable_ips = true;
4539         }
4540
4541         for (i = 0; i < 256; i++) {
4542                 i915_reg_t palreg;
4543
4544                 if (HAS_GMCH_DISPLAY(dev))
4545                         palreg = PALETTE(pipe, i);
4546                 else
4547                         palreg = LGC_PALETTE(pipe, i);
4548
4549                 I915_WRITE(palreg,
4550                            (intel_crtc->lut_r[i] << 16) |
4551                            (intel_crtc->lut_g[i] << 8) |
4552                            intel_crtc->lut_b[i]);
4553         }
4554
4555         if (reenable_ips)
4556                 hsw_enable_ips(intel_crtc);
4557 }
4558
4559 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4560 {
4561         if (intel_crtc->overlay) {
4562                 struct drm_device *dev = intel_crtc->base.dev;
4563                 struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565                 mutex_lock(&dev->struct_mutex);
4566                 dev_priv->mm.interruptible = false;
4567                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4568                 dev_priv->mm.interruptible = true;
4569                 mutex_unlock(&dev->struct_mutex);
4570         }
4571
4572         /* Let userspace switch the overlay on again. In most cases userspace
4573          * has to recompute where to put it anyway.
4574          */
4575 }
4576
4577 /**
4578  * intel_post_enable_primary - Perform operations after enabling primary plane
4579  * @crtc: the CRTC whose primary plane was just enabled
4580  *
4581  * Performs potentially sleeping operations that must be done after the primary
4582  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4583  * called due to an explicit primary plane update, or due to an implicit
4584  * re-enable that is caused when a sprite plane is updated to no longer
4585  * completely hide the primary plane.
4586  */
4587 static void
4588 intel_post_enable_primary(struct drm_crtc *crtc)
4589 {
4590         struct drm_device *dev = crtc->dev;
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         int pipe = intel_crtc->pipe;
4594
4595         /*
4596          * FIXME IPS should be fine as long as one plane is
4597          * enabled, but in practice it seems to have problems
4598          * when going from primary only to sprite only and vice
4599          * versa.
4600          */
4601         hsw_enable_ips(intel_crtc);
4602
4603         /*
4604          * Gen2 reports pipe underruns whenever all planes are disabled.
4605          * So don't enable underrun reporting before at least some planes
4606          * are enabled.
4607          * FIXME: Need to fix the logic to work when we turn off all planes
4608          * but leave the pipe running.
4609          */
4610         if (IS_GEN2(dev))
4611                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4612
4613         /* Underruns don't always raise interrupts, so check manually. */
4614         intel_check_cpu_fifo_underruns(dev_priv);
4615         intel_check_pch_fifo_underruns(dev_priv);
4616 }
4617
4618 /* FIXME move all this to pre_plane_update() with proper state tracking */
4619 static void
4620 intel_pre_disable_primary(struct drm_crtc *crtc)
4621 {
4622         struct drm_device *dev = crtc->dev;
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4625         int pipe = intel_crtc->pipe;
4626
4627         /*
4628          * Gen2 reports pipe underruns whenever all planes are disabled.
4629          * So diasble underrun reporting before all the planes get disabled.
4630          * FIXME: Need to fix the logic to work when we turn off all planes
4631          * but leave the pipe running.
4632          */
4633         if (IS_GEN2(dev))
4634                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4635
4636         /*
4637          * FIXME IPS should be fine as long as one plane is
4638          * enabled, but in practice it seems to have problems
4639          * when going from primary only to sprite only and vice
4640          * versa.
4641          */
4642         hsw_disable_ips(intel_crtc);
4643 }
4644
4645 /* FIXME get rid of this and use pre_plane_update */
4646 static void
4647 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4648 {
4649         struct drm_device *dev = crtc->dev;
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4652         int pipe = intel_crtc->pipe;
4653
4654         intel_pre_disable_primary(crtc);
4655
4656         /*
4657          * Vblank time updates from the shadow to live plane control register
4658          * are blocked if the memory self-refresh mode is active at that
4659          * moment. So to make sure the plane gets truly disabled, disable
4660          * first the self-refresh mode. The self-refresh enable bit in turn
4661          * will be checked/applied by the HW only at the next frame start
4662          * event which is after the vblank start event, so we need to have a
4663          * wait-for-vblank between disabling the plane and the pipe.
4664          */
4665         if (HAS_GMCH_DISPLAY(dev)) {
4666                 intel_set_memory_cxsr(dev_priv, false);
4667                 dev_priv->wm.vlv.cxsr = false;
4668                 intel_wait_for_vblank(dev, pipe);
4669         }
4670 }
4671
4672 static void intel_post_plane_update(struct intel_crtc *crtc)
4673 {
4674         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4675         struct intel_crtc_state *pipe_config =
4676                 to_intel_crtc_state(crtc->base.state);
4677         struct drm_device *dev = crtc->base.dev;
4678
4679         intel_frontbuffer_flip(dev, atomic->fb_bits);
4680
4681         crtc->wm.cxsr_allowed = true;
4682
4683         if (pipe_config->update_wm_post && pipe_config->base.active)
4684                 intel_update_watermarks(&crtc->base);
4685
4686         if (atomic->update_fbc)
4687                 intel_fbc_post_update(crtc);
4688
4689         if (atomic->post_enable_primary)
4690                 intel_post_enable_primary(&crtc->base);
4691
4692         memset(atomic, 0, sizeof(*atomic));
4693 }
4694
4695 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4696 {
4697         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4698         struct drm_device *dev = crtc->base.dev;
4699         struct drm_i915_private *dev_priv = dev->dev_private;
4700         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4701         struct intel_crtc_state *pipe_config =
4702                 to_intel_crtc_state(crtc->base.state);
4703         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4704         struct drm_plane *primary = crtc->base.primary;
4705         struct drm_plane_state *old_pri_state =
4706                 drm_atomic_get_existing_plane_state(old_state, primary);
4707         bool modeset = needs_modeset(&pipe_config->base);
4708
4709         if (atomic->update_fbc)
4710                 intel_fbc_pre_update(crtc);
4711
4712         if (old_pri_state) {
4713                 struct intel_plane_state *primary_state =
4714                         to_intel_plane_state(primary->state);
4715                 struct intel_plane_state *old_primary_state =
4716                         to_intel_plane_state(old_pri_state);
4717
4718                 if (old_primary_state->visible &&
4719                     (modeset || !primary_state->visible))
4720                         intel_pre_disable_primary(&crtc->base);
4721         }
4722
4723         if (pipe_config->disable_cxsr) {
4724                 crtc->wm.cxsr_allowed = false;
4725
4726                 /*
4727                  * Vblank time updates from the shadow to live plane control register
4728                  * are blocked if the memory self-refresh mode is active at that
4729                  * moment. So to make sure the plane gets truly disabled, disable
4730                  * first the self-refresh mode. The self-refresh enable bit in turn
4731                  * will be checked/applied by the HW only at the next frame start
4732                  * event which is after the vblank start event, so we need to have a
4733                  * wait-for-vblank between disabling the plane and the pipe.
4734                  */
4735                 if (old_crtc_state->base.active) {
4736                         intel_set_memory_cxsr(dev_priv, false);
4737                         dev_priv->wm.vlv.cxsr = false;
4738                         intel_wait_for_vblank(dev, crtc->pipe);
4739                 }
4740         }
4741
4742         /*
4743          * IVB workaround: must disable low power watermarks for at least
4744          * one frame before enabling scaling.  LP watermarks can be re-enabled
4745          * when scaling is disabled.
4746          *
4747          * WaCxSRDisabledForSpriteScaling:ivb
4748          */
4749         if (pipe_config->disable_lp_wm) {
4750                 ilk_disable_lp_wm(dev);
4751                 intel_wait_for_vblank(dev, crtc->pipe);
4752         }
4753
4754         /*
4755          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4756          * watermark programming here.
4757          */
4758         if (needs_modeset(&pipe_config->base))
4759                 return;
4760
4761         /*
4762          * For platforms that support atomic watermarks, program the
4763          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4764          * will be the intermediate values that are safe for both pre- and
4765          * post- vblank; when vblank happens, the 'active' values will be set
4766          * to the final 'target' values and we'll do this again to get the
4767          * optimal watermarks.  For gen9+ platforms, the values we program here
4768          * will be the final target values which will get automatically latched
4769          * at vblank time; no further programming will be necessary.
4770          *
4771          * If a platform hasn't been transitioned to atomic watermarks yet,
4772          * we'll continue to update watermarks the old way, if flags tell
4773          * us to.
4774          */
4775         if (dev_priv->display.initial_watermarks != NULL)
4776                 dev_priv->display.initial_watermarks(pipe_config);
4777         else if (pipe_config->update_wm_pre)
4778                 intel_update_watermarks(&crtc->base);
4779 }
4780
4781 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4782 {
4783         struct drm_device *dev = crtc->dev;
4784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4785         struct drm_plane *p;
4786         int pipe = intel_crtc->pipe;
4787
4788         intel_crtc_dpms_overlay_disable(intel_crtc);
4789
4790         drm_for_each_plane_mask(p, dev, plane_mask)
4791                 to_intel_plane(p)->disable_plane(p, crtc);
4792
4793         /*
4794          * FIXME: Once we grow proper nuclear flip support out of this we need
4795          * to compute the mask of flip planes precisely. For the time being
4796          * consider this a flip to a NULL plane.
4797          */
4798         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4799 }
4800
4801 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4802 {
4803         struct drm_device *dev = crtc->dev;
4804         struct drm_i915_private *dev_priv = dev->dev_private;
4805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806         struct intel_encoder *encoder;
4807         int pipe = intel_crtc->pipe;
4808
4809         if (WARN_ON(intel_crtc->active))
4810                 return;
4811
4812         if (intel_crtc->config->has_pch_encoder)
4813                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4814
4815         if (intel_crtc->config->has_pch_encoder)
4816                 intel_prepare_shared_dpll(intel_crtc);
4817
4818         if (intel_crtc->config->has_dp_encoder)
4819                 intel_dp_set_m_n(intel_crtc, M1_N1);
4820
4821         intel_set_pipe_timings(intel_crtc);
4822
4823         if (intel_crtc->config->has_pch_encoder) {
4824                 intel_cpu_transcoder_set_m_n(intel_crtc,
4825                                      &intel_crtc->config->fdi_m_n, NULL);
4826         }
4827
4828         ironlake_set_pipeconf(crtc);
4829
4830         intel_crtc->active = true;
4831
4832         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4833
4834         for_each_encoder_on_crtc(dev, crtc, encoder)
4835                 if (encoder->pre_enable)
4836                         encoder->pre_enable(encoder);
4837
4838         if (intel_crtc->config->has_pch_encoder) {
4839                 /* Note: FDI PLL enabling _must_ be done before we enable the
4840                  * cpu pipes, hence this is separate from all the other fdi/pch
4841                  * enabling. */
4842                 ironlake_fdi_pll_enable(intel_crtc);
4843         } else {
4844                 assert_fdi_tx_disabled(dev_priv, pipe);
4845                 assert_fdi_rx_disabled(dev_priv, pipe);
4846         }
4847
4848         ironlake_pfit_enable(intel_crtc);
4849
4850         /*
4851          * On ILK+ LUT must be loaded before the pipe is running but with
4852          * clocks enabled
4853          */
4854         intel_crtc_load_lut(crtc);
4855
4856         if (dev_priv->display.initial_watermarks != NULL)
4857                 dev_priv->display.initial_watermarks(intel_crtc->config);
4858         intel_enable_pipe(intel_crtc);
4859
4860         if (intel_crtc->config->has_pch_encoder)
4861                 ironlake_pch_enable(crtc);
4862
4863         assert_vblank_disabled(crtc);
4864         drm_crtc_vblank_on(crtc);
4865
4866         for_each_encoder_on_crtc(dev, crtc, encoder)
4867                 encoder->enable(encoder);
4868
4869         if (HAS_PCH_CPT(dev))
4870                 cpt_verify_modeset(dev, intel_crtc->pipe);
4871
4872         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4873         if (intel_crtc->config->has_pch_encoder)
4874                 intel_wait_for_vblank(dev, pipe);
4875         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4876 }
4877
4878 /* IPS only exists on ULT machines and is tied to pipe A. */
4879 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4880 {
4881         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4882 }
4883
4884 static void haswell_crtc_enable(struct drm_crtc *crtc)
4885 {
4886         struct drm_device *dev = crtc->dev;
4887         struct drm_i915_private *dev_priv = dev->dev_private;
4888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4889         struct intel_encoder *encoder;
4890         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4891         struct intel_crtc_state *pipe_config =
4892                 to_intel_crtc_state(crtc->state);
4893
4894         if (WARN_ON(intel_crtc->active))
4895                 return;
4896
4897         if (intel_crtc->config->has_pch_encoder)
4898                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4899                                                       false);
4900
4901         if (intel_crtc->config->shared_dpll)
4902                 intel_enable_shared_dpll(intel_crtc);
4903
4904         if (intel_crtc->config->has_dp_encoder)
4905                 intel_dp_set_m_n(intel_crtc, M1_N1);
4906
4907         intel_set_pipe_timings(intel_crtc);
4908
4909         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4910                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4911                            intel_crtc->config->pixel_multiplier - 1);
4912         }
4913
4914         if (intel_crtc->config->has_pch_encoder) {
4915                 intel_cpu_transcoder_set_m_n(intel_crtc,
4916                                      &intel_crtc->config->fdi_m_n, NULL);
4917         }
4918
4919         haswell_set_pipeconf(crtc);
4920
4921         intel_set_pipe_csc(crtc);
4922
4923         intel_crtc->active = true;
4924
4925         if (intel_crtc->config->has_pch_encoder)
4926                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4927         else
4928                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4929
4930         for_each_encoder_on_crtc(dev, crtc, encoder) {
4931                 if (encoder->pre_enable)
4932                         encoder->pre_enable(encoder);
4933         }
4934
4935         if (intel_crtc->config->has_pch_encoder)
4936                 dev_priv->display.fdi_link_train(crtc);
4937
4938         if (!intel_crtc->config->has_dsi_encoder)
4939                 intel_ddi_enable_pipe_clock(intel_crtc);
4940
4941         if (INTEL_INFO(dev)->gen >= 9)
4942                 skylake_pfit_enable(intel_crtc);
4943         else
4944                 ironlake_pfit_enable(intel_crtc);
4945
4946         /*
4947          * On ILK+ LUT must be loaded before the pipe is running but with
4948          * clocks enabled
4949          */
4950         intel_crtc_load_lut(crtc);
4951
4952         intel_ddi_set_pipe_settings(crtc);
4953         if (!intel_crtc->config->has_dsi_encoder)
4954                 intel_ddi_enable_transcoder_func(crtc);
4955
4956         if (dev_priv->display.initial_watermarks != NULL)
4957                 dev_priv->display.initial_watermarks(pipe_config);
4958         else
4959                 intel_update_watermarks(crtc);
4960         intel_enable_pipe(intel_crtc);
4961
4962         if (intel_crtc->config->has_pch_encoder)
4963                 lpt_pch_enable(crtc);
4964
4965         if (intel_crtc->config->dp_encoder_is_mst)
4966                 intel_ddi_set_vc_payload_alloc(crtc, true);
4967
4968         assert_vblank_disabled(crtc);
4969         drm_crtc_vblank_on(crtc);
4970
4971         for_each_encoder_on_crtc(dev, crtc, encoder) {
4972                 encoder->enable(encoder);
4973                 intel_opregion_notify_encoder(encoder, true);
4974         }
4975
4976         if (intel_crtc->config->has_pch_encoder) {
4977                 intel_wait_for_vblank(dev, pipe);
4978                 intel_wait_for_vblank(dev, pipe);
4979                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4980                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4981                                                       true);
4982         }
4983
4984         /* If we change the relative order between pipe/planes enabling, we need
4985          * to change the workaround. */
4986         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4987         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4988                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4989                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990         }
4991 }
4992
4993 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4994 {
4995         struct drm_device *dev = crtc->base.dev;
4996         struct drm_i915_private *dev_priv = dev->dev_private;
4997         int pipe = crtc->pipe;
4998
4999         /* To avoid upsetting the power well on haswell only disable the pfit if
5000          * it's in use. The hw state code will make sure we get this right. */
5001         if (force || crtc->config->pch_pfit.enabled) {
5002                 I915_WRITE(PF_CTL(pipe), 0);
5003                 I915_WRITE(PF_WIN_POS(pipe), 0);
5004                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5005         }
5006 }
5007
5008 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5009 {
5010         struct drm_device *dev = crtc->dev;
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5013         struct intel_encoder *encoder;
5014         int pipe = intel_crtc->pipe;
5015
5016         if (intel_crtc->config->has_pch_encoder)
5017                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5018
5019         for_each_encoder_on_crtc(dev, crtc, encoder)
5020                 encoder->disable(encoder);
5021
5022         drm_crtc_vblank_off(crtc);
5023         assert_vblank_disabled(crtc);
5024
5025         /*
5026          * Sometimes spurious CPU pipe underruns happen when the
5027          * pipe is already disabled, but FDI RX/TX is still enabled.
5028          * Happens at least with VGA+HDMI cloning. Suppress them.
5029          */
5030         if (intel_crtc->config->has_pch_encoder)
5031                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5032
5033         intel_disable_pipe(intel_crtc);
5034
5035         ironlake_pfit_disable(intel_crtc, false);
5036
5037         if (intel_crtc->config->has_pch_encoder) {
5038                 ironlake_fdi_disable(crtc);
5039                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5040         }
5041
5042         for_each_encoder_on_crtc(dev, crtc, encoder)
5043                 if (encoder->post_disable)
5044                         encoder->post_disable(encoder);
5045
5046         if (intel_crtc->config->has_pch_encoder) {
5047                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5048
5049                 if (HAS_PCH_CPT(dev)) {
5050                         i915_reg_t reg;
5051                         u32 temp;
5052
5053                         /* disable TRANS_DP_CTL */
5054                         reg = TRANS_DP_CTL(pipe);
5055                         temp = I915_READ(reg);
5056                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5057                                   TRANS_DP_PORT_SEL_MASK);
5058                         temp |= TRANS_DP_PORT_SEL_NONE;
5059                         I915_WRITE(reg, temp);
5060
5061                         /* disable DPLL_SEL */
5062                         temp = I915_READ(PCH_DPLL_SEL);
5063                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5064                         I915_WRITE(PCH_DPLL_SEL, temp);
5065                 }
5066
5067                 ironlake_fdi_pll_disable(intel_crtc);
5068         }
5069
5070         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5071 }
5072
5073 static void haswell_crtc_disable(struct drm_crtc *crtc)
5074 {
5075         struct drm_device *dev = crtc->dev;
5076         struct drm_i915_private *dev_priv = dev->dev_private;
5077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5078         struct intel_encoder *encoder;
5079         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5080
5081         if (intel_crtc->config->has_pch_encoder)
5082                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5083                                                       false);
5084
5085         for_each_encoder_on_crtc(dev, crtc, encoder) {
5086                 intel_opregion_notify_encoder(encoder, false);
5087                 encoder->disable(encoder);
5088         }
5089
5090         drm_crtc_vblank_off(crtc);
5091         assert_vblank_disabled(crtc);
5092
5093         intel_disable_pipe(intel_crtc);
5094
5095         if (intel_crtc->config->dp_encoder_is_mst)
5096                 intel_ddi_set_vc_payload_alloc(crtc, false);
5097
5098         if (!intel_crtc->config->has_dsi_encoder)
5099                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5100
5101         if (INTEL_INFO(dev)->gen >= 9)
5102                 skylake_scaler_disable(intel_crtc);
5103         else
5104                 ironlake_pfit_disable(intel_crtc, false);
5105
5106         if (!intel_crtc->config->has_dsi_encoder)
5107                 intel_ddi_disable_pipe_clock(intel_crtc);
5108
5109         for_each_encoder_on_crtc(dev, crtc, encoder)
5110                 if (encoder->post_disable)
5111                         encoder->post_disable(encoder);
5112
5113         if (intel_crtc->config->has_pch_encoder) {
5114                 lpt_disable_pch_transcoder(dev_priv);
5115                 lpt_disable_iclkip(dev_priv);
5116                 intel_ddi_fdi_disable(crtc);
5117
5118                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5119                                                       true);
5120         }
5121 }
5122
5123 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5124 {
5125         struct drm_device *dev = crtc->base.dev;
5126         struct drm_i915_private *dev_priv = dev->dev_private;
5127         struct intel_crtc_state *pipe_config = crtc->config;
5128
5129         if (!pipe_config->gmch_pfit.control)
5130                 return;
5131
5132         /*
5133          * The panel fitter should only be adjusted whilst the pipe is disabled,
5134          * according to register description and PRM.
5135          */
5136         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5137         assert_pipe_disabled(dev_priv, crtc->pipe);
5138
5139         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5140         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5141
5142         /* Border color in case we don't scale up to the full screen. Black by
5143          * default, change to something else for debugging. */
5144         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5145 }
5146
5147 static enum intel_display_power_domain port_to_power_domain(enum port port)
5148 {
5149         switch (port) {
5150         case PORT_A:
5151                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5152         case PORT_B:
5153                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5154         case PORT_C:
5155                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5156         case PORT_D:
5157                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5158         case PORT_E:
5159                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5160         default:
5161                 MISSING_CASE(port);
5162                 return POWER_DOMAIN_PORT_OTHER;
5163         }
5164 }
5165
5166 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5167 {
5168         switch (port) {
5169         case PORT_A:
5170                 return POWER_DOMAIN_AUX_A;
5171         case PORT_B:
5172                 return POWER_DOMAIN_AUX_B;
5173         case PORT_C:
5174                 return POWER_DOMAIN_AUX_C;
5175         case PORT_D:
5176                 return POWER_DOMAIN_AUX_D;
5177         case PORT_E:
5178                 /* FIXME: Check VBT for actual wiring of PORT E */
5179                 return POWER_DOMAIN_AUX_D;
5180         default:
5181                 MISSING_CASE(port);
5182                 return POWER_DOMAIN_AUX_A;
5183         }
5184 }
5185
5186 enum intel_display_power_domain
5187 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5188 {
5189         struct drm_device *dev = intel_encoder->base.dev;
5190         struct intel_digital_port *intel_dig_port;
5191
5192         switch (intel_encoder->type) {
5193         case INTEL_OUTPUT_UNKNOWN:
5194                 /* Only DDI platforms should ever use this output type */
5195                 WARN_ON_ONCE(!HAS_DDI(dev));
5196         case INTEL_OUTPUT_DISPLAYPORT:
5197         case INTEL_OUTPUT_HDMI:
5198         case INTEL_OUTPUT_EDP:
5199                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5200                 return port_to_power_domain(intel_dig_port->port);
5201         case INTEL_OUTPUT_DP_MST:
5202                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5203                 return port_to_power_domain(intel_dig_port->port);
5204         case INTEL_OUTPUT_ANALOG:
5205                 return POWER_DOMAIN_PORT_CRT;
5206         case INTEL_OUTPUT_DSI:
5207                 return POWER_DOMAIN_PORT_DSI;
5208         default:
5209                 return POWER_DOMAIN_PORT_OTHER;
5210         }
5211 }
5212
5213 enum intel_display_power_domain
5214 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5215 {
5216         struct drm_device *dev = intel_encoder->base.dev;
5217         struct intel_digital_port *intel_dig_port;
5218
5219         switch (intel_encoder->type) {
5220         case INTEL_OUTPUT_UNKNOWN:
5221         case INTEL_OUTPUT_HDMI:
5222                 /*
5223                  * Only DDI platforms should ever use these output types.
5224                  * We can get here after the HDMI detect code has already set
5225                  * the type of the shared encoder. Since we can't be sure
5226                  * what's the status of the given connectors, play safe and
5227                  * run the DP detection too.
5228                  */
5229                 WARN_ON_ONCE(!HAS_DDI(dev));
5230         case INTEL_OUTPUT_DISPLAYPORT:
5231         case INTEL_OUTPUT_EDP:
5232                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5233                 return port_to_aux_power_domain(intel_dig_port->port);
5234         case INTEL_OUTPUT_DP_MST:
5235                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5236                 return port_to_aux_power_domain(intel_dig_port->port);
5237         default:
5238                 MISSING_CASE(intel_encoder->type);
5239                 return POWER_DOMAIN_AUX_A;
5240         }
5241 }
5242
5243 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5244                                             struct intel_crtc_state *crtc_state)
5245 {
5246         struct drm_device *dev = crtc->dev;
5247         struct drm_encoder *encoder;
5248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249         enum pipe pipe = intel_crtc->pipe;
5250         unsigned long mask;
5251         enum transcoder transcoder = crtc_state->cpu_transcoder;
5252
5253         if (!crtc_state->base.active)
5254                 return 0;
5255
5256         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5257         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5258         if (crtc_state->pch_pfit.enabled ||
5259             crtc_state->pch_pfit.force_thru)
5260                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5261
5262         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5263                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5264
5265                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5266         }
5267
5268         return mask;
5269 }
5270
5271 static unsigned long
5272 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5273                                struct intel_crtc_state *crtc_state)
5274 {
5275         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5277         enum intel_display_power_domain domain;
5278         unsigned long domains, new_domains, old_domains;
5279
5280         old_domains = intel_crtc->enabled_power_domains;
5281         intel_crtc->enabled_power_domains = new_domains =
5282                 get_crtc_power_domains(crtc, crtc_state);
5283
5284         domains = new_domains & ~old_domains;
5285
5286         for_each_power_domain(domain, domains)
5287                 intel_display_power_get(dev_priv, domain);
5288
5289         return old_domains & ~new_domains;
5290 }
5291
5292 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5293                                       unsigned long domains)
5294 {
5295         enum intel_display_power_domain domain;
5296
5297         for_each_power_domain(domain, domains)
5298                 intel_display_power_put(dev_priv, domain);
5299 }
5300
5301 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5302 {
5303         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5304
5305         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5306             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5307                 return max_cdclk_freq;
5308         else if (IS_CHERRYVIEW(dev_priv))
5309                 return max_cdclk_freq*95/100;
5310         else if (INTEL_INFO(dev_priv)->gen < 4)
5311                 return 2*max_cdclk_freq*90/100;
5312         else
5313                 return max_cdclk_freq*90/100;
5314 }
5315
5316 static void intel_update_max_cdclk(struct drm_device *dev)
5317 {
5318         struct drm_i915_private *dev_priv = dev->dev_private;
5319
5320         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5321                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5322
5323                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5324                         dev_priv->max_cdclk_freq = 675000;
5325                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5326                         dev_priv->max_cdclk_freq = 540000;
5327                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5328                         dev_priv->max_cdclk_freq = 450000;
5329                 else
5330                         dev_priv->max_cdclk_freq = 337500;
5331         } else if (IS_BROADWELL(dev))  {
5332                 /*
5333                  * FIXME with extra cooling we can allow
5334                  * 540 MHz for ULX and 675 Mhz for ULT.
5335                  * How can we know if extra cooling is
5336                  * available? PCI ID, VTB, something else?
5337                  */
5338                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5339                         dev_priv->max_cdclk_freq = 450000;
5340                 else if (IS_BDW_ULX(dev))
5341                         dev_priv->max_cdclk_freq = 450000;
5342                 else if (IS_BDW_ULT(dev))
5343                         dev_priv->max_cdclk_freq = 540000;
5344                 else
5345                         dev_priv->max_cdclk_freq = 675000;
5346         } else if (IS_CHERRYVIEW(dev)) {
5347                 dev_priv->max_cdclk_freq = 320000;
5348         } else if (IS_VALLEYVIEW(dev)) {
5349                 dev_priv->max_cdclk_freq = 400000;
5350         } else {
5351                 /* otherwise assume cdclk is fixed */
5352                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5353         }
5354
5355         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5356
5357         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5358                          dev_priv->max_cdclk_freq);
5359
5360         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5361                          dev_priv->max_dotclk_freq);
5362 }
5363
5364 static void intel_update_cdclk(struct drm_device *dev)
5365 {
5366         struct drm_i915_private *dev_priv = dev->dev_private;
5367
5368         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5369         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5370                          dev_priv->cdclk_freq);
5371
5372         /*
5373          * Program the gmbus_freq based on the cdclk frequency.
5374          * BSpec erroneously claims we should aim for 4MHz, but
5375          * in fact 1MHz is the correct frequency.
5376          */
5377         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5378                 /*
5379                  * Program the gmbus_freq based on the cdclk frequency.
5380                  * BSpec erroneously claims we should aim for 4MHz, but
5381                  * in fact 1MHz is the correct frequency.
5382                  */
5383                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5384         }
5385
5386         if (dev_priv->max_cdclk_freq == 0)
5387                 intel_update_max_cdclk(dev);
5388 }
5389
5390 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5391 {
5392         struct drm_i915_private *dev_priv = dev->dev_private;
5393         uint32_t divider;
5394         uint32_t ratio;
5395         uint32_t current_freq;
5396         int ret;
5397
5398         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5399         switch (frequency) {
5400         case 144000:
5401                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5402                 ratio = BXT_DE_PLL_RATIO(60);
5403                 break;
5404         case 288000:
5405                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5406                 ratio = BXT_DE_PLL_RATIO(60);
5407                 break;
5408         case 384000:
5409                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5410                 ratio = BXT_DE_PLL_RATIO(60);
5411                 break;
5412         case 576000:
5413                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5414                 ratio = BXT_DE_PLL_RATIO(60);
5415                 break;
5416         case 624000:
5417                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5418                 ratio = BXT_DE_PLL_RATIO(65);
5419                 break;
5420         case 19200:
5421                 /*
5422                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5423                  * to suppress GCC warning.
5424                  */
5425                 ratio = 0;
5426                 divider = 0;
5427                 break;
5428         default:
5429                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5430
5431                 return;
5432         }
5433
5434         mutex_lock(&dev_priv->rps.hw_lock);
5435         /* Inform power controller of upcoming frequency change */
5436         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5437                                       0x80000000);
5438         mutex_unlock(&dev_priv->rps.hw_lock);
5439
5440         if (ret) {
5441                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5442                           ret, frequency);
5443                 return;
5444         }
5445
5446         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5447         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5448         current_freq = current_freq * 500 + 1000;
5449
5450         /*
5451          * DE PLL has to be disabled when
5452          * - setting to 19.2MHz (bypass, PLL isn't used)
5453          * - before setting to 624MHz (PLL needs toggling)
5454          * - before setting to any frequency from 624MHz (PLL needs toggling)
5455          */
5456         if (frequency == 19200 || frequency == 624000 ||
5457             current_freq == 624000) {
5458                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5459                 /* Timeout 200us */
5460                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5461                              1))
5462                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5463         }
5464
5465         if (frequency != 19200) {
5466                 uint32_t val;
5467
5468                 val = I915_READ(BXT_DE_PLL_CTL);
5469                 val &= ~BXT_DE_PLL_RATIO_MASK;
5470                 val |= ratio;
5471                 I915_WRITE(BXT_DE_PLL_CTL, val);
5472
5473                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5474                 /* Timeout 200us */
5475                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5476                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5477
5478                 val = I915_READ(CDCLK_CTL);
5479                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5480                 val |= divider;
5481                 /*
5482                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5483                  * enable otherwise.
5484                  */
5485                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5486                 if (frequency >= 500000)
5487                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5488
5489                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5490                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5491                 val |= (frequency - 1000) / 500;
5492                 I915_WRITE(CDCLK_CTL, val);
5493         }
5494
5495         mutex_lock(&dev_priv->rps.hw_lock);
5496         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5497                                       DIV_ROUND_UP(frequency, 25000));
5498         mutex_unlock(&dev_priv->rps.hw_lock);
5499
5500         if (ret) {
5501                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5502                           ret, frequency);
5503                 return;
5504         }
5505
5506         intel_update_cdclk(dev);
5507 }
5508
5509 void broxton_init_cdclk(struct drm_device *dev)
5510 {
5511         struct drm_i915_private *dev_priv = dev->dev_private;
5512         uint32_t val;
5513
5514         /*
5515          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5516          * or else the reset will hang because there is no PCH to respond.
5517          * Move the handshake programming to initialization sequence.
5518          * Previously was left up to BIOS.
5519          */
5520         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5521         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5522         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5523
5524         /* Enable PG1 for cdclk */
5525         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5526
5527         /* check if cd clock is enabled */
5528         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5529                 DRM_DEBUG_KMS("Display already initialized\n");
5530                 return;
5531         }
5532
5533         /*
5534          * FIXME:
5535          * - The initial CDCLK needs to be read from VBT.
5536          *   Need to make this change after VBT has changes for BXT.
5537          * - check if setting the max (or any) cdclk freq is really necessary
5538          *   here, it belongs to modeset time
5539          */
5540         broxton_set_cdclk(dev, 624000);
5541
5542         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5543         POSTING_READ(DBUF_CTL);
5544
5545         udelay(10);
5546
5547         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5548                 DRM_ERROR("DBuf power enable timeout!\n");
5549 }
5550
5551 void broxton_uninit_cdclk(struct drm_device *dev)
5552 {
5553         struct drm_i915_private *dev_priv = dev->dev_private;
5554
5555         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5556         POSTING_READ(DBUF_CTL);
5557
5558         udelay(10);
5559
5560         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5561                 DRM_ERROR("DBuf power disable timeout!\n");
5562
5563         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5564         broxton_set_cdclk(dev, 19200);
5565
5566         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5567 }
5568
5569 static const struct skl_cdclk_entry {
5570         unsigned int freq;
5571         unsigned int vco;
5572 } skl_cdclk_frequencies[] = {
5573         { .freq = 308570, .vco = 8640 },
5574         { .freq = 337500, .vco = 8100 },
5575         { .freq = 432000, .vco = 8640 },
5576         { .freq = 450000, .vco = 8100 },
5577         { .freq = 540000, .vco = 8100 },
5578         { .freq = 617140, .vco = 8640 },
5579         { .freq = 675000, .vco = 8100 },
5580 };
5581
5582 static unsigned int skl_cdclk_decimal(unsigned int freq)
5583 {
5584         return (freq - 1000) / 500;
5585 }
5586
5587 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5588 {
5589         unsigned int i;
5590
5591         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5592                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5593
5594                 if (e->freq == freq)
5595                         return e->vco;
5596         }
5597
5598         return 8100;
5599 }
5600
5601 static void
5602 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5603 {
5604         unsigned int min_freq;
5605         u32 val;
5606
5607         /* select the minimum CDCLK before enabling DPLL 0 */
5608         val = I915_READ(CDCLK_CTL);
5609         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5610         val |= CDCLK_FREQ_337_308;
5611
5612         if (required_vco == 8640)
5613                 min_freq = 308570;
5614         else
5615                 min_freq = 337500;
5616
5617         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5618
5619         I915_WRITE(CDCLK_CTL, val);
5620         POSTING_READ(CDCLK_CTL);
5621
5622         /*
5623          * We always enable DPLL0 with the lowest link rate possible, but still
5624          * taking into account the VCO required to operate the eDP panel at the
5625          * desired frequency. The usual DP link rates operate with a VCO of
5626          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5627          * The modeset code is responsible for the selection of the exact link
5628          * rate later on, with the constraint of choosing a frequency that
5629          * works with required_vco.
5630          */
5631         val = I915_READ(DPLL_CTRL1);
5632
5633         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5634                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5635         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5636         if (required_vco == 8640)
5637                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5638                                             SKL_DPLL0);
5639         else
5640                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5641                                             SKL_DPLL0);
5642
5643         I915_WRITE(DPLL_CTRL1, val);
5644         POSTING_READ(DPLL_CTRL1);
5645
5646         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5647
5648         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5649                 DRM_ERROR("DPLL0 not locked\n");
5650 }
5651
5652 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5653 {
5654         int ret;
5655         u32 val;
5656
5657         /* inform PCU we want to change CDCLK */
5658         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5659         mutex_lock(&dev_priv->rps.hw_lock);
5660         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5661         mutex_unlock(&dev_priv->rps.hw_lock);
5662
5663         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5664 }
5665
5666 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5667 {
5668         unsigned int i;
5669
5670         for (i = 0; i < 15; i++) {
5671                 if (skl_cdclk_pcu_ready(dev_priv))
5672                         return true;
5673                 udelay(10);
5674         }
5675
5676         return false;
5677 }
5678
5679 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5680 {
5681         struct drm_device *dev = dev_priv->dev;
5682         u32 freq_select, pcu_ack;
5683
5684         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5685
5686         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5687                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5688                 return;
5689         }
5690
5691         /* set CDCLK_CTL */
5692         switch(freq) {
5693         case 450000:
5694         case 432000:
5695                 freq_select = CDCLK_FREQ_450_432;
5696                 pcu_ack = 1;
5697                 break;
5698         case 540000:
5699                 freq_select = CDCLK_FREQ_540;
5700                 pcu_ack = 2;
5701                 break;
5702         case 308570:
5703         case 337500:
5704         default:
5705                 freq_select = CDCLK_FREQ_337_308;
5706                 pcu_ack = 0;
5707                 break;
5708         case 617140:
5709         case 675000:
5710                 freq_select = CDCLK_FREQ_675_617;
5711                 pcu_ack = 3;
5712                 break;
5713         }
5714
5715         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5716         POSTING_READ(CDCLK_CTL);
5717
5718         /* inform PCU of the change */
5719         mutex_lock(&dev_priv->rps.hw_lock);
5720         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5721         mutex_unlock(&dev_priv->rps.hw_lock);
5722
5723         intel_update_cdclk(dev);
5724 }
5725
5726 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5727 {
5728         /* disable DBUF power */
5729         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5730         POSTING_READ(DBUF_CTL);
5731
5732         udelay(10);
5733
5734         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5735                 DRM_ERROR("DBuf power disable timeout\n");
5736
5737         /* disable DPLL0 */
5738         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5739         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5740                 DRM_ERROR("Couldn't disable DPLL0\n");
5741 }
5742
5743 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5744 {
5745         unsigned int required_vco;
5746
5747         /* DPLL0 not enabled (happens on early BIOS versions) */
5748         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5749                 /* enable DPLL0 */
5750                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5751                 skl_dpll0_enable(dev_priv, required_vco);
5752         }
5753
5754         /* set CDCLK to the frequency the BIOS chose */
5755         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5756
5757         /* enable DBUF power */
5758         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5759         POSTING_READ(DBUF_CTL);
5760
5761         udelay(10);
5762
5763         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5764                 DRM_ERROR("DBuf power enable timeout\n");
5765 }
5766
5767 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5768 {
5769         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5770         uint32_t cdctl = I915_READ(CDCLK_CTL);
5771         int freq = dev_priv->skl_boot_cdclk;
5772
5773         /*
5774          * check if the pre-os intialized the display
5775          * There is SWF18 scratchpad register defined which is set by the
5776          * pre-os which can be used by the OS drivers to check the status
5777          */
5778         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5779                 goto sanitize;
5780
5781         /* Is PLL enabled and locked ? */
5782         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5783                 goto sanitize;
5784
5785         /* DPLL okay; verify the cdclock
5786          *
5787          * Noticed in some instances that the freq selection is correct but
5788          * decimal part is programmed wrong from BIOS where pre-os does not
5789          * enable display. Verify the same as well.
5790          */
5791         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5792                 /* All well; nothing to sanitize */
5793                 return false;
5794 sanitize:
5795         /*
5796          * As of now initialize with max cdclk till
5797          * we get dynamic cdclk support
5798          * */
5799         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5800         skl_init_cdclk(dev_priv);
5801
5802         /* we did have to sanitize */
5803         return true;
5804 }
5805
5806 /* Adjust CDclk dividers to allow high res or save power if possible */
5807 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5808 {
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810         u32 val, cmd;
5811
5812         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5813                                         != dev_priv->cdclk_freq);
5814
5815         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5816                 cmd = 2;
5817         else if (cdclk == 266667)
5818                 cmd = 1;
5819         else
5820                 cmd = 0;
5821
5822         mutex_lock(&dev_priv->rps.hw_lock);
5823         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5824         val &= ~DSPFREQGUAR_MASK;
5825         val |= (cmd << DSPFREQGUAR_SHIFT);
5826         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5827         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5828                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5829                      50)) {
5830                 DRM_ERROR("timed out waiting for CDclk change\n");
5831         }
5832         mutex_unlock(&dev_priv->rps.hw_lock);
5833
5834         mutex_lock(&dev_priv->sb_lock);
5835
5836         if (cdclk == 400000) {
5837                 u32 divider;
5838
5839                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5840
5841                 /* adjust cdclk divider */
5842                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5843                 val &= ~CCK_FREQUENCY_VALUES;
5844                 val |= divider;
5845                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5846
5847                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5848                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5849                              50))
5850                         DRM_ERROR("timed out waiting for CDclk change\n");
5851         }
5852
5853         /* adjust self-refresh exit latency value */
5854         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5855         val &= ~0x7f;
5856
5857         /*
5858          * For high bandwidth configs, we set a higher latency in the bunit
5859          * so that the core display fetch happens in time to avoid underruns.
5860          */
5861         if (cdclk == 400000)
5862                 val |= 4500 / 250; /* 4.5 usec */
5863         else
5864                 val |= 3000 / 250; /* 3.0 usec */
5865         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5866
5867         mutex_unlock(&dev_priv->sb_lock);
5868
5869         intel_update_cdclk(dev);
5870 }
5871
5872 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5873 {
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         u32 val, cmd;
5876
5877         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5878                                                 != dev_priv->cdclk_freq);
5879
5880         switch (cdclk) {
5881         case 333333:
5882         case 320000:
5883         case 266667:
5884         case 200000:
5885                 break;
5886         default:
5887                 MISSING_CASE(cdclk);
5888                 return;
5889         }
5890
5891         /*
5892          * Specs are full of misinformation, but testing on actual
5893          * hardware has shown that we just need to write the desired
5894          * CCK divider into the Punit register.
5895          */
5896         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5897
5898         mutex_lock(&dev_priv->rps.hw_lock);
5899         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5900         val &= ~DSPFREQGUAR_MASK_CHV;
5901         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5902         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5903         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5904                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5905                      50)) {
5906                 DRM_ERROR("timed out waiting for CDclk change\n");
5907         }
5908         mutex_unlock(&dev_priv->rps.hw_lock);
5909
5910         intel_update_cdclk(dev);
5911 }
5912
5913 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5914                                  int max_pixclk)
5915 {
5916         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5917         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5918
5919         /*
5920          * Really only a few cases to deal with, as only 4 CDclks are supported:
5921          *   200MHz
5922          *   267MHz
5923          *   320/333MHz (depends on HPLL freq)
5924          *   400MHz (VLV only)
5925          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5926          * of the lower bin and adjust if needed.
5927          *
5928          * We seem to get an unstable or solid color picture at 200MHz.
5929          * Not sure what's wrong. For now use 200MHz only when all pipes
5930          * are off.
5931          */
5932         if (!IS_CHERRYVIEW(dev_priv) &&
5933             max_pixclk > freq_320*limit/100)
5934                 return 400000;
5935         else if (max_pixclk > 266667*limit/100)
5936                 return freq_320;
5937         else if (max_pixclk > 0)
5938                 return 266667;
5939         else
5940                 return 200000;
5941 }
5942
5943 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5944                               int max_pixclk)
5945 {
5946         /*
5947          * FIXME:
5948          * - remove the guardband, it's not needed on BXT
5949          * - set 19.2MHz bypass frequency if there are no active pipes
5950          */
5951         if (max_pixclk > 576000*9/10)
5952                 return 624000;
5953         else if (max_pixclk > 384000*9/10)
5954                 return 576000;
5955         else if (max_pixclk > 288000*9/10)
5956                 return 384000;
5957         else if (max_pixclk > 144000*9/10)
5958                 return 288000;
5959         else
5960                 return 144000;
5961 }
5962
5963 /* Compute the max pixel clock for new configuration. */
5964 static int intel_mode_max_pixclk(struct drm_device *dev,
5965                                  struct drm_atomic_state *state)
5966 {
5967         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5968         struct drm_i915_private *dev_priv = dev->dev_private;
5969         struct drm_crtc *crtc;
5970         struct drm_crtc_state *crtc_state;
5971         unsigned max_pixclk = 0, i;
5972         enum pipe pipe;
5973
5974         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5975                sizeof(intel_state->min_pixclk));
5976
5977         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5978                 int pixclk = 0;
5979
5980                 if (crtc_state->enable)
5981                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5982
5983                 intel_state->min_pixclk[i] = pixclk;
5984         }
5985
5986         for_each_pipe(dev_priv, pipe)
5987                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5988
5989         return max_pixclk;
5990 }
5991
5992 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5993 {
5994         struct drm_device *dev = state->dev;
5995         struct drm_i915_private *dev_priv = dev->dev_private;
5996         int max_pixclk = intel_mode_max_pixclk(dev, state);
5997         struct intel_atomic_state *intel_state =
5998                 to_intel_atomic_state(state);
5999
6000         if (max_pixclk < 0)
6001                 return max_pixclk;
6002
6003         intel_state->cdclk = intel_state->dev_cdclk =
6004                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6005
6006         if (!intel_state->active_crtcs)
6007                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6008
6009         return 0;
6010 }
6011
6012 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6013 {
6014         struct drm_device *dev = state->dev;
6015         struct drm_i915_private *dev_priv = dev->dev_private;
6016         int max_pixclk = intel_mode_max_pixclk(dev, state);
6017         struct intel_atomic_state *intel_state =
6018                 to_intel_atomic_state(state);
6019
6020         if (max_pixclk < 0)
6021                 return max_pixclk;
6022
6023         intel_state->cdclk = intel_state->dev_cdclk =
6024                 broxton_calc_cdclk(dev_priv, max_pixclk);
6025
6026         if (!intel_state->active_crtcs)
6027                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6028
6029         return 0;
6030 }
6031
6032 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6033 {
6034         unsigned int credits, default_credits;
6035
6036         if (IS_CHERRYVIEW(dev_priv))
6037                 default_credits = PFI_CREDIT(12);
6038         else
6039                 default_credits = PFI_CREDIT(8);
6040
6041         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6042                 /* CHV suggested value is 31 or 63 */
6043                 if (IS_CHERRYVIEW(dev_priv))
6044                         credits = PFI_CREDIT_63;
6045                 else
6046                         credits = PFI_CREDIT(15);
6047         } else {
6048                 credits = default_credits;
6049         }
6050
6051         /*
6052          * WA - write default credits before re-programming
6053          * FIXME: should we also set the resend bit here?
6054          */
6055         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6056                    default_credits);
6057
6058         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6059                    credits | PFI_CREDIT_RESEND);
6060
6061         /*
6062          * FIXME is this guaranteed to clear
6063          * immediately or should we poll for it?
6064          */
6065         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6066 }
6067
6068 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6069 {
6070         struct drm_device *dev = old_state->dev;
6071         struct drm_i915_private *dev_priv = dev->dev_private;
6072         struct intel_atomic_state *old_intel_state =
6073                 to_intel_atomic_state(old_state);
6074         unsigned req_cdclk = old_intel_state->dev_cdclk;
6075
6076         /*
6077          * FIXME: We can end up here with all power domains off, yet
6078          * with a CDCLK frequency other than the minimum. To account
6079          * for this take the PIPE-A power domain, which covers the HW
6080          * blocks needed for the following programming. This can be
6081          * removed once it's guaranteed that we get here either with
6082          * the minimum CDCLK set, or the required power domains
6083          * enabled.
6084          */
6085         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6086
6087         if (IS_CHERRYVIEW(dev))
6088                 cherryview_set_cdclk(dev, req_cdclk);
6089         else
6090                 valleyview_set_cdclk(dev, req_cdclk);
6091
6092         vlv_program_pfi_credits(dev_priv);
6093
6094         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6095 }
6096
6097 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6098 {
6099         struct drm_device *dev = crtc->dev;
6100         struct drm_i915_private *dev_priv = to_i915(dev);
6101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102         struct intel_encoder *encoder;
6103         int pipe = intel_crtc->pipe;
6104
6105         if (WARN_ON(intel_crtc->active))
6106                 return;
6107
6108         if (intel_crtc->config->has_dp_encoder)
6109                 intel_dp_set_m_n(intel_crtc, M1_N1);
6110
6111         intel_set_pipe_timings(intel_crtc);
6112
6113         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6114                 struct drm_i915_private *dev_priv = dev->dev_private;
6115
6116                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6117                 I915_WRITE(CHV_CANVAS(pipe), 0);
6118         }
6119
6120         i9xx_set_pipeconf(intel_crtc);
6121
6122         intel_crtc->active = true;
6123
6124         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6125
6126         for_each_encoder_on_crtc(dev, crtc, encoder)
6127                 if (encoder->pre_pll_enable)
6128                         encoder->pre_pll_enable(encoder);
6129
6130         if (!intel_crtc->config->has_dsi_encoder) {
6131                 if (IS_CHERRYVIEW(dev)) {
6132                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6133                         chv_enable_pll(intel_crtc, intel_crtc->config);
6134                 } else {
6135                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6136                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6137                 }
6138         }
6139
6140         for_each_encoder_on_crtc(dev, crtc, encoder)
6141                 if (encoder->pre_enable)
6142                         encoder->pre_enable(encoder);
6143
6144         i9xx_pfit_enable(intel_crtc);
6145
6146         intel_crtc_load_lut(crtc);
6147
6148         intel_update_watermarks(crtc);
6149         intel_enable_pipe(intel_crtc);
6150
6151         assert_vblank_disabled(crtc);
6152         drm_crtc_vblank_on(crtc);
6153
6154         for_each_encoder_on_crtc(dev, crtc, encoder)
6155                 encoder->enable(encoder);
6156 }
6157
6158 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6159 {
6160         struct drm_device *dev = crtc->base.dev;
6161         struct drm_i915_private *dev_priv = dev->dev_private;
6162
6163         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6164         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6165 }
6166
6167 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6168 {
6169         struct drm_device *dev = crtc->dev;
6170         struct drm_i915_private *dev_priv = to_i915(dev);
6171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6172         struct intel_encoder *encoder;
6173         int pipe = intel_crtc->pipe;
6174
6175         if (WARN_ON(intel_crtc->active))
6176                 return;
6177
6178         i9xx_set_pll_dividers(intel_crtc);
6179
6180         if (intel_crtc->config->has_dp_encoder)
6181                 intel_dp_set_m_n(intel_crtc, M1_N1);
6182
6183         intel_set_pipe_timings(intel_crtc);
6184
6185         i9xx_set_pipeconf(intel_crtc);
6186
6187         intel_crtc->active = true;
6188
6189         if (!IS_GEN2(dev))
6190                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6191
6192         for_each_encoder_on_crtc(dev, crtc, encoder)
6193                 if (encoder->pre_enable)
6194                         encoder->pre_enable(encoder);
6195
6196         i9xx_enable_pll(intel_crtc);
6197
6198         i9xx_pfit_enable(intel_crtc);
6199
6200         intel_crtc_load_lut(crtc);
6201
6202         intel_update_watermarks(crtc);
6203         intel_enable_pipe(intel_crtc);
6204
6205         assert_vblank_disabled(crtc);
6206         drm_crtc_vblank_on(crtc);
6207
6208         for_each_encoder_on_crtc(dev, crtc, encoder)
6209                 encoder->enable(encoder);
6210 }
6211
6212 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6213 {
6214         struct drm_device *dev = crtc->base.dev;
6215         struct drm_i915_private *dev_priv = dev->dev_private;
6216
6217         if (!crtc->config->gmch_pfit.control)
6218                 return;
6219
6220         assert_pipe_disabled(dev_priv, crtc->pipe);
6221
6222         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6223                          I915_READ(PFIT_CONTROL));
6224         I915_WRITE(PFIT_CONTROL, 0);
6225 }
6226
6227 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6228 {
6229         struct drm_device *dev = crtc->dev;
6230         struct drm_i915_private *dev_priv = dev->dev_private;
6231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6232         struct intel_encoder *encoder;
6233         int pipe = intel_crtc->pipe;
6234
6235         /*
6236          * On gen2 planes are double buffered but the pipe isn't, so we must
6237          * wait for planes to fully turn off before disabling the pipe.
6238          * We also need to wait on all gmch platforms because of the
6239          * self-refresh mode constraint explained above.
6240          */
6241         intel_wait_for_vblank(dev, pipe);
6242
6243         for_each_encoder_on_crtc(dev, crtc, encoder)
6244                 encoder->disable(encoder);
6245
6246         drm_crtc_vblank_off(crtc);
6247         assert_vblank_disabled(crtc);
6248
6249         intel_disable_pipe(intel_crtc);
6250
6251         i9xx_pfit_disable(intel_crtc);
6252
6253         for_each_encoder_on_crtc(dev, crtc, encoder)
6254                 if (encoder->post_disable)
6255                         encoder->post_disable(encoder);
6256
6257         if (!intel_crtc->config->has_dsi_encoder) {
6258                 if (IS_CHERRYVIEW(dev))
6259                         chv_disable_pll(dev_priv, pipe);
6260                 else if (IS_VALLEYVIEW(dev))
6261                         vlv_disable_pll(dev_priv, pipe);
6262                 else
6263                         i9xx_disable_pll(intel_crtc);
6264         }
6265
6266         for_each_encoder_on_crtc(dev, crtc, encoder)
6267                 if (encoder->post_pll_disable)
6268                         encoder->post_pll_disable(encoder);
6269
6270         if (!IS_GEN2(dev))
6271                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6272 }
6273
6274 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6275 {
6276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6277         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6278         enum intel_display_power_domain domain;
6279         unsigned long domains;
6280
6281         if (!intel_crtc->active)
6282                 return;
6283
6284         if (to_intel_plane_state(crtc->primary->state)->visible) {
6285                 WARN_ON(intel_crtc->unpin_work);
6286
6287                 intel_pre_disable_primary_noatomic(crtc);
6288
6289                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6290                 to_intel_plane_state(crtc->primary->state)->visible = false;
6291         }
6292
6293         dev_priv->display.crtc_disable(crtc);
6294         intel_crtc->active = false;
6295         intel_fbc_disable(intel_crtc);
6296         intel_update_watermarks(crtc);
6297         intel_disable_shared_dpll(intel_crtc);
6298
6299         domains = intel_crtc->enabled_power_domains;
6300         for_each_power_domain(domain, domains)
6301                 intel_display_power_put(dev_priv, domain);
6302         intel_crtc->enabled_power_domains = 0;
6303
6304         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6305         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6306 }
6307
6308 /*
6309  * turn all crtc's off, but do not adjust state
6310  * This has to be paired with a call to intel_modeset_setup_hw_state.
6311  */
6312 int intel_display_suspend(struct drm_device *dev)
6313 {
6314         struct drm_i915_private *dev_priv = to_i915(dev);
6315         struct drm_atomic_state *state;
6316         int ret;
6317
6318         state = drm_atomic_helper_suspend(dev);
6319         ret = PTR_ERR_OR_ZERO(state);
6320         if (ret)
6321                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6322         else
6323                 dev_priv->modeset_restore_state = state;
6324         return ret;
6325 }
6326
6327 void intel_encoder_destroy(struct drm_encoder *encoder)
6328 {
6329         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6330
6331         drm_encoder_cleanup(encoder);
6332         kfree(intel_encoder);
6333 }
6334
6335 /* Cross check the actual hw state with our own modeset state tracking (and it's
6336  * internal consistency). */
6337 static void intel_connector_check_state(struct intel_connector *connector)
6338 {
6339         struct drm_crtc *crtc = connector->base.state->crtc;
6340
6341         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6342                       connector->base.base.id,
6343                       connector->base.name);
6344
6345         if (connector->get_hw_state(connector)) {
6346                 struct intel_encoder *encoder = connector->encoder;
6347                 struct drm_connector_state *conn_state = connector->base.state;
6348
6349                 I915_STATE_WARN(!crtc,
6350                          "connector enabled without attached crtc\n");
6351
6352                 if (!crtc)
6353                         return;
6354
6355                 I915_STATE_WARN(!crtc->state->active,
6356                       "connector is active, but attached crtc isn't\n");
6357
6358                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6359                         return;
6360
6361                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6362                         "atomic encoder doesn't match attached encoder\n");
6363
6364                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6365                         "attached encoder crtc differs from connector crtc\n");
6366         } else {
6367                 I915_STATE_WARN(crtc && crtc->state->active,
6368                         "attached crtc is active, but connector isn't\n");
6369                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6370                         "best encoder set without crtc!\n");
6371         }
6372 }
6373
6374 int intel_connector_init(struct intel_connector *connector)
6375 {
6376         drm_atomic_helper_connector_reset(&connector->base);
6377
6378         if (!connector->base.state)
6379                 return -ENOMEM;
6380
6381         return 0;
6382 }
6383
6384 struct intel_connector *intel_connector_alloc(void)
6385 {
6386         struct intel_connector *connector;
6387
6388         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6389         if (!connector)
6390                 return NULL;
6391
6392         if (intel_connector_init(connector) < 0) {
6393                 kfree(connector);
6394                 return NULL;
6395         }
6396
6397         return connector;
6398 }
6399
6400 /* Simple connector->get_hw_state implementation for encoders that support only
6401  * one connector and no cloning and hence the encoder state determines the state
6402  * of the connector. */
6403 bool intel_connector_get_hw_state(struct intel_connector *connector)
6404 {
6405         enum pipe pipe = 0;
6406         struct intel_encoder *encoder = connector->encoder;
6407
6408         return encoder->get_hw_state(encoder, &pipe);
6409 }
6410
6411 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6412 {
6413         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6414                 return crtc_state->fdi_lanes;
6415
6416         return 0;
6417 }
6418
6419 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6420                                      struct intel_crtc_state *pipe_config)
6421 {
6422         struct drm_atomic_state *state = pipe_config->base.state;
6423         struct intel_crtc *other_crtc;
6424         struct intel_crtc_state *other_crtc_state;
6425
6426         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6427                       pipe_name(pipe), pipe_config->fdi_lanes);
6428         if (pipe_config->fdi_lanes > 4) {
6429                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6430                               pipe_name(pipe), pipe_config->fdi_lanes);
6431                 return -EINVAL;
6432         }
6433
6434         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6435                 if (pipe_config->fdi_lanes > 2) {
6436                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6437                                       pipe_config->fdi_lanes);
6438                         return -EINVAL;
6439                 } else {
6440                         return 0;
6441                 }
6442         }
6443
6444         if (INTEL_INFO(dev)->num_pipes == 2)
6445                 return 0;
6446
6447         /* Ivybridge 3 pipe is really complicated */
6448         switch (pipe) {
6449         case PIPE_A:
6450                 return 0;
6451         case PIPE_B:
6452                 if (pipe_config->fdi_lanes <= 2)
6453                         return 0;
6454
6455                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6456                 other_crtc_state =
6457                         intel_atomic_get_crtc_state(state, other_crtc);
6458                 if (IS_ERR(other_crtc_state))
6459                         return PTR_ERR(other_crtc_state);
6460
6461                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6462                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6463                                       pipe_name(pipe), pipe_config->fdi_lanes);
6464                         return -EINVAL;
6465                 }
6466                 return 0;
6467         case PIPE_C:
6468                 if (pipe_config->fdi_lanes > 2) {
6469                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6470                                       pipe_name(pipe), pipe_config->fdi_lanes);
6471                         return -EINVAL;
6472                 }
6473
6474                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6475                 other_crtc_state =
6476                         intel_atomic_get_crtc_state(state, other_crtc);
6477                 if (IS_ERR(other_crtc_state))
6478                         return PTR_ERR(other_crtc_state);
6479
6480                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6481                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6482                         return -EINVAL;
6483                 }
6484                 return 0;
6485         default:
6486                 BUG();
6487         }
6488 }
6489
6490 #define RETRY 1
6491 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6492                                        struct intel_crtc_state *pipe_config)
6493 {
6494         struct drm_device *dev = intel_crtc->base.dev;
6495         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6496         int lane, link_bw, fdi_dotclock, ret;
6497         bool needs_recompute = false;
6498
6499 retry:
6500         /* FDI is a binary signal running at ~2.7GHz, encoding
6501          * each output octet as 10 bits. The actual frequency
6502          * is stored as a divider into a 100MHz clock, and the
6503          * mode pixel clock is stored in units of 1KHz.
6504          * Hence the bw of each lane in terms of the mode signal
6505          * is:
6506          */
6507         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6508
6509         fdi_dotclock = adjusted_mode->crtc_clock;
6510
6511         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6512                                            pipe_config->pipe_bpp);
6513
6514         pipe_config->fdi_lanes = lane;
6515
6516         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6517                                link_bw, &pipe_config->fdi_m_n);
6518
6519         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6520         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6521                 pipe_config->pipe_bpp -= 2*3;
6522                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6523                               pipe_config->pipe_bpp);
6524                 needs_recompute = true;
6525                 pipe_config->bw_constrained = true;
6526
6527                 goto retry;
6528         }
6529
6530         if (needs_recompute)
6531                 return RETRY;
6532
6533         return ret;
6534 }
6535
6536 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6537                                      struct intel_crtc_state *pipe_config)
6538 {
6539         if (pipe_config->pipe_bpp > 24)
6540                 return false;
6541
6542         /* HSW can handle pixel rate up to cdclk? */
6543         if (IS_HASWELL(dev_priv->dev))
6544                 return true;
6545
6546         /*
6547          * We compare against max which means we must take
6548          * the increased cdclk requirement into account when
6549          * calculating the new cdclk.
6550          *
6551          * Should measure whether using a lower cdclk w/o IPS
6552          */
6553         return ilk_pipe_pixel_rate(pipe_config) <=
6554                 dev_priv->max_cdclk_freq * 95 / 100;
6555 }
6556
6557 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6558                                    struct intel_crtc_state *pipe_config)
6559 {
6560         struct drm_device *dev = crtc->base.dev;
6561         struct drm_i915_private *dev_priv = dev->dev_private;
6562
6563         pipe_config->ips_enabled = i915.enable_ips &&
6564                 hsw_crtc_supports_ips(crtc) &&
6565                 pipe_config_supports_ips(dev_priv, pipe_config);
6566 }
6567
6568 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6569 {
6570         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6571
6572         /* GDG double wide on either pipe, otherwise pipe A only */
6573         return INTEL_INFO(dev_priv)->gen < 4 &&
6574                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6575 }
6576
6577 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6578                                      struct intel_crtc_state *pipe_config)
6579 {
6580         struct drm_device *dev = crtc->base.dev;
6581         struct drm_i915_private *dev_priv = dev->dev_private;
6582         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6583
6584         /* FIXME should check pixel clock limits on all platforms */
6585         if (INTEL_INFO(dev)->gen < 4) {
6586                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6587
6588                 /*
6589                  * Enable double wide mode when the dot clock
6590                  * is > 90% of the (display) core speed.
6591                  */
6592                 if (intel_crtc_supports_double_wide(crtc) &&
6593                     adjusted_mode->crtc_clock > clock_limit) {
6594                         clock_limit *= 2;
6595                         pipe_config->double_wide = true;
6596                 }
6597
6598                 if (adjusted_mode->crtc_clock > clock_limit) {
6599                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6600                                       adjusted_mode->crtc_clock, clock_limit,
6601                                       yesno(pipe_config->double_wide));
6602                         return -EINVAL;
6603                 }
6604         }
6605
6606         /*
6607          * Pipe horizontal size must be even in:
6608          * - DVO ganged mode
6609          * - LVDS dual channel mode
6610          * - Double wide pipe
6611          */
6612         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6613              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6614                 pipe_config->pipe_src_w &= ~1;
6615
6616         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6617          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6618          */
6619         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6620                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6621                 return -EINVAL;
6622
6623         if (HAS_IPS(dev))
6624                 hsw_compute_ips_config(crtc, pipe_config);
6625
6626         if (pipe_config->has_pch_encoder)
6627                 return ironlake_fdi_compute_config(crtc, pipe_config);
6628
6629         return 0;
6630 }
6631
6632 static int skylake_get_display_clock_speed(struct drm_device *dev)
6633 {
6634         struct drm_i915_private *dev_priv = to_i915(dev);
6635         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6636         uint32_t cdctl = I915_READ(CDCLK_CTL);
6637         uint32_t linkrate;
6638
6639         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6640                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6641
6642         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6643                 return 540000;
6644
6645         linkrate = (I915_READ(DPLL_CTRL1) &
6646                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6647
6648         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6649             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6650                 /* vco 8640 */
6651                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6652                 case CDCLK_FREQ_450_432:
6653                         return 432000;
6654                 case CDCLK_FREQ_337_308:
6655                         return 308570;
6656                 case CDCLK_FREQ_675_617:
6657                         return 617140;
6658                 default:
6659                         WARN(1, "Unknown cd freq selection\n");
6660                 }
6661         } else {
6662                 /* vco 8100 */
6663                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6664                 case CDCLK_FREQ_450_432:
6665                         return 450000;
6666                 case CDCLK_FREQ_337_308:
6667                         return 337500;
6668                 case CDCLK_FREQ_675_617:
6669                         return 675000;
6670                 default:
6671                         WARN(1, "Unknown cd freq selection\n");
6672                 }
6673         }
6674
6675         /* error case, do as if DPLL0 isn't enabled */
6676         return 24000;
6677 }
6678
6679 static int broxton_get_display_clock_speed(struct drm_device *dev)
6680 {
6681         struct drm_i915_private *dev_priv = to_i915(dev);
6682         uint32_t cdctl = I915_READ(CDCLK_CTL);
6683         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6684         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6685         int cdclk;
6686
6687         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6688                 return 19200;
6689
6690         cdclk = 19200 * pll_ratio / 2;
6691
6692         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6693         case BXT_CDCLK_CD2X_DIV_SEL_1:
6694                 return cdclk;  /* 576MHz or 624MHz */
6695         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6696                 return cdclk * 2 / 3; /* 384MHz */
6697         case BXT_CDCLK_CD2X_DIV_SEL_2:
6698                 return cdclk / 2; /* 288MHz */
6699         case BXT_CDCLK_CD2X_DIV_SEL_4:
6700                 return cdclk / 4; /* 144MHz */
6701         }
6702
6703         /* error case, do as if DE PLL isn't enabled */
6704         return 19200;
6705 }
6706
6707 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6708 {
6709         struct drm_i915_private *dev_priv = dev->dev_private;
6710         uint32_t lcpll = I915_READ(LCPLL_CTL);
6711         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6712
6713         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6714                 return 800000;
6715         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6716                 return 450000;
6717         else if (freq == LCPLL_CLK_FREQ_450)
6718                 return 450000;
6719         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6720                 return 540000;
6721         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6722                 return 337500;
6723         else
6724                 return 675000;
6725 }
6726
6727 static int haswell_get_display_clock_speed(struct drm_device *dev)
6728 {
6729         struct drm_i915_private *dev_priv = dev->dev_private;
6730         uint32_t lcpll = I915_READ(LCPLL_CTL);
6731         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6732
6733         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6734                 return 800000;
6735         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6736                 return 450000;
6737         else if (freq == LCPLL_CLK_FREQ_450)
6738                 return 450000;
6739         else if (IS_HSW_ULT(dev))
6740                 return 337500;
6741         else
6742                 return 540000;
6743 }
6744
6745 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6746 {
6747         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6748                                       CCK_DISPLAY_CLOCK_CONTROL);
6749 }
6750
6751 static int ilk_get_display_clock_speed(struct drm_device *dev)
6752 {
6753         return 450000;
6754 }
6755
6756 static int i945_get_display_clock_speed(struct drm_device *dev)
6757 {
6758         return 400000;
6759 }
6760
6761 static int i915_get_display_clock_speed(struct drm_device *dev)
6762 {
6763         return 333333;
6764 }
6765
6766 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         return 200000;
6769 }
6770
6771 static int pnv_get_display_clock_speed(struct drm_device *dev)
6772 {
6773         u16 gcfgc = 0;
6774
6775         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6776
6777         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6778         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6779                 return 266667;
6780         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6781                 return 333333;
6782         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6783                 return 444444;
6784         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6785                 return 200000;
6786         default:
6787                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6788         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6789                 return 133333;
6790         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6791                 return 166667;
6792         }
6793 }
6794
6795 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6796 {
6797         u16 gcfgc = 0;
6798
6799         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6800
6801         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6802                 return 133333;
6803         else {
6804                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6805                 case GC_DISPLAY_CLOCK_333_MHZ:
6806                         return 333333;
6807                 default:
6808                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6809                         return 190000;
6810                 }
6811         }
6812 }
6813
6814 static int i865_get_display_clock_speed(struct drm_device *dev)
6815 {
6816         return 266667;
6817 }
6818
6819 static int i85x_get_display_clock_speed(struct drm_device *dev)
6820 {
6821         u16 hpllcc = 0;
6822
6823         /*
6824          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6825          * encoding is different :(
6826          * FIXME is this the right way to detect 852GM/852GMV?
6827          */
6828         if (dev->pdev->revision == 0x1)
6829                 return 133333;
6830
6831         pci_bus_read_config_word(dev->pdev->bus,
6832                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6833
6834         /* Assume that the hardware is in the high speed state.  This
6835          * should be the default.
6836          */
6837         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6838         case GC_CLOCK_133_200:
6839         case GC_CLOCK_133_200_2:
6840         case GC_CLOCK_100_200:
6841                 return 200000;
6842         case GC_CLOCK_166_250:
6843                 return 250000;
6844         case GC_CLOCK_100_133:
6845                 return 133333;
6846         case GC_CLOCK_133_266:
6847         case GC_CLOCK_133_266_2:
6848         case GC_CLOCK_166_266:
6849                 return 266667;
6850         }
6851
6852         /* Shouldn't happen */
6853         return 0;
6854 }
6855
6856 static int i830_get_display_clock_speed(struct drm_device *dev)
6857 {
6858         return 133333;
6859 }
6860
6861 static unsigned int intel_hpll_vco(struct drm_device *dev)
6862 {
6863         struct drm_i915_private *dev_priv = dev->dev_private;
6864         static const unsigned int blb_vco[8] = {
6865                 [0] = 3200000,
6866                 [1] = 4000000,
6867                 [2] = 5333333,
6868                 [3] = 4800000,
6869                 [4] = 6400000,
6870         };
6871         static const unsigned int pnv_vco[8] = {
6872                 [0] = 3200000,
6873                 [1] = 4000000,
6874                 [2] = 5333333,
6875                 [3] = 4800000,
6876                 [4] = 2666667,
6877         };
6878         static const unsigned int cl_vco[8] = {
6879                 [0] = 3200000,
6880                 [1] = 4000000,
6881                 [2] = 5333333,
6882                 [3] = 6400000,
6883                 [4] = 3333333,
6884                 [5] = 3566667,
6885                 [6] = 4266667,
6886         };
6887         static const unsigned int elk_vco[8] = {
6888                 [0] = 3200000,
6889                 [1] = 4000000,
6890                 [2] = 5333333,
6891                 [3] = 4800000,
6892         };
6893         static const unsigned int ctg_vco[8] = {
6894                 [0] = 3200000,
6895                 [1] = 4000000,
6896                 [2] = 5333333,
6897                 [3] = 6400000,
6898                 [4] = 2666667,
6899                 [5] = 4266667,
6900         };
6901         const unsigned int *vco_table;
6902         unsigned int vco;
6903         uint8_t tmp = 0;
6904
6905         /* FIXME other chipsets? */
6906         if (IS_GM45(dev))
6907                 vco_table = ctg_vco;
6908         else if (IS_G4X(dev))
6909                 vco_table = elk_vco;
6910         else if (IS_CRESTLINE(dev))
6911                 vco_table = cl_vco;
6912         else if (IS_PINEVIEW(dev))
6913                 vco_table = pnv_vco;
6914         else if (IS_G33(dev))
6915                 vco_table = blb_vco;
6916         else
6917                 return 0;
6918
6919         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6920
6921         vco = vco_table[tmp & 0x7];
6922         if (vco == 0)
6923                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6924         else
6925                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6926
6927         return vco;
6928 }
6929
6930 static int gm45_get_display_clock_speed(struct drm_device *dev)
6931 {
6932         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6933         uint16_t tmp = 0;
6934
6935         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6936
6937         cdclk_sel = (tmp >> 12) & 0x1;
6938
6939         switch (vco) {
6940         case 2666667:
6941         case 4000000:
6942         case 5333333:
6943                 return cdclk_sel ? 333333 : 222222;
6944         case 3200000:
6945                 return cdclk_sel ? 320000 : 228571;
6946         default:
6947                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6948                 return 222222;
6949         }
6950 }
6951
6952 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6953 {
6954         static const uint8_t div_3200[] = { 16, 10,  8 };
6955         static const uint8_t div_4000[] = { 20, 12, 10 };
6956         static const uint8_t div_5333[] = { 24, 16, 14 };
6957         const uint8_t *div_table;
6958         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6959         uint16_t tmp = 0;
6960
6961         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6962
6963         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6964
6965         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6966                 goto fail;
6967
6968         switch (vco) {
6969         case 3200000:
6970                 div_table = div_3200;
6971                 break;
6972         case 4000000:
6973                 div_table = div_4000;
6974                 break;
6975         case 5333333:
6976                 div_table = div_5333;
6977                 break;
6978         default:
6979                 goto fail;
6980         }
6981
6982         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6983
6984 fail:
6985         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6986         return 200000;
6987 }
6988
6989 static int g33_get_display_clock_speed(struct drm_device *dev)
6990 {
6991         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6992         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6993         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6994         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6995         const uint8_t *div_table;
6996         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6997         uint16_t tmp = 0;
6998
6999         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7000
7001         cdclk_sel = (tmp >> 4) & 0x7;
7002
7003         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7004                 goto fail;
7005
7006         switch (vco) {
7007         case 3200000:
7008                 div_table = div_3200;
7009                 break;
7010         case 4000000:
7011                 div_table = div_4000;
7012                 break;
7013         case 4800000:
7014                 div_table = div_4800;
7015                 break;
7016         case 5333333:
7017                 div_table = div_5333;
7018                 break;
7019         default:
7020                 goto fail;
7021         }
7022
7023         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7024
7025 fail:
7026         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7027         return 190476;
7028 }
7029
7030 static void
7031 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7032 {
7033         while (*num > DATA_LINK_M_N_MASK ||
7034                *den > DATA_LINK_M_N_MASK) {
7035                 *num >>= 1;
7036                 *den >>= 1;
7037         }
7038 }
7039
7040 static void compute_m_n(unsigned int m, unsigned int n,
7041                         uint32_t *ret_m, uint32_t *ret_n)
7042 {
7043         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7044         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7045         intel_reduce_m_n_ratio(ret_m, ret_n);
7046 }
7047
7048 void
7049 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7050                        int pixel_clock, int link_clock,
7051                        struct intel_link_m_n *m_n)
7052 {
7053         m_n->tu = 64;
7054
7055         compute_m_n(bits_per_pixel * pixel_clock,
7056                     link_clock * nlanes * 8,
7057                     &m_n->gmch_m, &m_n->gmch_n);
7058
7059         compute_m_n(pixel_clock, link_clock,
7060                     &m_n->link_m, &m_n->link_n);
7061 }
7062
7063 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7064 {
7065         if (i915.panel_use_ssc >= 0)
7066                 return i915.panel_use_ssc != 0;
7067         return dev_priv->vbt.lvds_use_ssc
7068                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7069 }
7070
7071 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7072                            int num_connectors)
7073 {
7074         struct drm_device *dev = crtc_state->base.crtc->dev;
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076         int refclk;
7077
7078         WARN_ON(!crtc_state->base.state);
7079
7080         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7081                 refclk = 100000;
7082         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7083             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7084                 refclk = dev_priv->vbt.lvds_ssc_freq;
7085                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7086         } else if (!IS_GEN2(dev)) {
7087                 refclk = 96000;
7088         } else {
7089                 refclk = 48000;
7090         }
7091
7092         return refclk;
7093 }
7094
7095 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7096 {
7097         return (1 << dpll->n) << 16 | dpll->m2;
7098 }
7099
7100 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7101 {
7102         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7103 }
7104
7105 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7106                                      struct intel_crtc_state *crtc_state,
7107                                      intel_clock_t *reduced_clock)
7108 {
7109         struct drm_device *dev = crtc->base.dev;
7110         u32 fp, fp2 = 0;
7111
7112         if (IS_PINEVIEW(dev)) {
7113                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7114                 if (reduced_clock)
7115                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7116         } else {
7117                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7118                 if (reduced_clock)
7119                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7120         }
7121
7122         crtc_state->dpll_hw_state.fp0 = fp;
7123
7124         crtc->lowfreq_avail = false;
7125         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7126             reduced_clock) {
7127                 crtc_state->dpll_hw_state.fp1 = fp2;
7128                 crtc->lowfreq_avail = true;
7129         } else {
7130                 crtc_state->dpll_hw_state.fp1 = fp;
7131         }
7132 }
7133
7134 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7135                 pipe)
7136 {
7137         u32 reg_val;
7138
7139         /*
7140          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7141          * and set it to a reasonable value instead.
7142          */
7143         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7144         reg_val &= 0xffffff00;
7145         reg_val |= 0x00000030;
7146         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7147
7148         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7149         reg_val &= 0x8cffffff;
7150         reg_val = 0x8c000000;
7151         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7152
7153         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7154         reg_val &= 0xffffff00;
7155         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7156
7157         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7158         reg_val &= 0x00ffffff;
7159         reg_val |= 0xb0000000;
7160         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7161 }
7162
7163 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7164                                          struct intel_link_m_n *m_n)
7165 {
7166         struct drm_device *dev = crtc->base.dev;
7167         struct drm_i915_private *dev_priv = dev->dev_private;
7168         int pipe = crtc->pipe;
7169
7170         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7171         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7172         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7173         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7174 }
7175
7176 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7177                                          struct intel_link_m_n *m_n,
7178                                          struct intel_link_m_n *m2_n2)
7179 {
7180         struct drm_device *dev = crtc->base.dev;
7181         struct drm_i915_private *dev_priv = dev->dev_private;
7182         int pipe = crtc->pipe;
7183         enum transcoder transcoder = crtc->config->cpu_transcoder;
7184
7185         if (INTEL_INFO(dev)->gen >= 5) {
7186                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7187                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7188                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7189                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7190                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7191                  * for gen < 8) and if DRRS is supported (to make sure the
7192                  * registers are not unnecessarily accessed).
7193                  */
7194                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7195                         crtc->config->has_drrs) {
7196                         I915_WRITE(PIPE_DATA_M2(transcoder),
7197                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7198                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7199                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7200                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7201                 }
7202         } else {
7203                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7204                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7205                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7206                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7207         }
7208 }
7209
7210 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7211 {
7212         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7213
7214         if (m_n == M1_N1) {
7215                 dp_m_n = &crtc->config->dp_m_n;
7216                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7217         } else if (m_n == M2_N2) {
7218
7219                 /*
7220                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7221                  * needs to be programmed into M1_N1.
7222                  */
7223                 dp_m_n = &crtc->config->dp_m2_n2;
7224         } else {
7225                 DRM_ERROR("Unsupported divider value\n");
7226                 return;
7227         }
7228
7229         if (crtc->config->has_pch_encoder)
7230                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7231         else
7232                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7233 }
7234
7235 static void vlv_compute_dpll(struct intel_crtc *crtc,
7236                              struct intel_crtc_state *pipe_config)
7237 {
7238         u32 dpll, dpll_md;
7239
7240         /*
7241          * Enable DPIO clock input. We should never disable the reference
7242          * clock for pipe B, since VGA hotplug / manual detection depends
7243          * on it.
7244          */
7245         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7246                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7247         /* We should never disable this, set it here for state tracking */
7248         if (crtc->pipe == PIPE_B)
7249                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7250         dpll |= DPLL_VCO_ENABLE;
7251         pipe_config->dpll_hw_state.dpll = dpll;
7252
7253         dpll_md = (pipe_config->pixel_multiplier - 1)
7254                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7255         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7256 }
7257
7258 static void vlv_prepare_pll(struct intel_crtc *crtc,
7259                             const struct intel_crtc_state *pipe_config)
7260 {
7261         struct drm_device *dev = crtc->base.dev;
7262         struct drm_i915_private *dev_priv = dev->dev_private;
7263         int pipe = crtc->pipe;
7264         u32 mdiv;
7265         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7266         u32 coreclk, reg_val;
7267
7268         mutex_lock(&dev_priv->sb_lock);
7269
7270         bestn = pipe_config->dpll.n;
7271         bestm1 = pipe_config->dpll.m1;
7272         bestm2 = pipe_config->dpll.m2;
7273         bestp1 = pipe_config->dpll.p1;
7274         bestp2 = pipe_config->dpll.p2;
7275
7276         /* See eDP HDMI DPIO driver vbios notes doc */
7277
7278         /* PLL B needs special handling */
7279         if (pipe == PIPE_B)
7280                 vlv_pllb_recal_opamp(dev_priv, pipe);
7281
7282         /* Set up Tx target for periodic Rcomp update */
7283         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7284
7285         /* Disable target IRef on PLL */
7286         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7287         reg_val &= 0x00ffffff;
7288         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7289
7290         /* Disable fast lock */
7291         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7292
7293         /* Set idtafcrecal before PLL is enabled */
7294         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7295         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7296         mdiv |= ((bestn << DPIO_N_SHIFT));
7297         mdiv |= (1 << DPIO_K_SHIFT);
7298
7299         /*
7300          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7301          * but we don't support that).
7302          * Note: don't use the DAC post divider as it seems unstable.
7303          */
7304         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7305         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7306
7307         mdiv |= DPIO_ENABLE_CALIBRATION;
7308         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7309
7310         /* Set HBR and RBR LPF coefficients */
7311         if (pipe_config->port_clock == 162000 ||
7312             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7313             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7314                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7315                                  0x009f0003);
7316         else
7317                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7318                                  0x00d0000f);
7319
7320         if (pipe_config->has_dp_encoder) {
7321                 /* Use SSC source */
7322                 if (pipe == PIPE_A)
7323                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7324                                          0x0df40000);
7325                 else
7326                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7327                                          0x0df70000);
7328         } else { /* HDMI or VGA */
7329                 /* Use bend source */
7330                 if (pipe == PIPE_A)
7331                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7332                                          0x0df70000);
7333                 else
7334                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7335                                          0x0df40000);
7336         }
7337
7338         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7339         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7341             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7342                 coreclk |= 0x01000000;
7343         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7344
7345         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7346         mutex_unlock(&dev_priv->sb_lock);
7347 }
7348
7349 static void chv_compute_dpll(struct intel_crtc *crtc,
7350                              struct intel_crtc_state *pipe_config)
7351 {
7352         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7353                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7354                 DPLL_VCO_ENABLE;
7355         if (crtc->pipe != PIPE_A)
7356                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7357
7358         pipe_config->dpll_hw_state.dpll_md =
7359                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7360 }
7361
7362 static void chv_prepare_pll(struct intel_crtc *crtc,
7363                             const struct intel_crtc_state *pipe_config)
7364 {
7365         struct drm_device *dev = crtc->base.dev;
7366         struct drm_i915_private *dev_priv = dev->dev_private;
7367         int pipe = crtc->pipe;
7368         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7369         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7370         u32 loopfilter, tribuf_calcntr;
7371         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7372         u32 dpio_val;
7373         int vco;
7374
7375         bestn = pipe_config->dpll.n;
7376         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7377         bestm1 = pipe_config->dpll.m1;
7378         bestm2 = pipe_config->dpll.m2 >> 22;
7379         bestp1 = pipe_config->dpll.p1;
7380         bestp2 = pipe_config->dpll.p2;
7381         vco = pipe_config->dpll.vco;
7382         dpio_val = 0;
7383         loopfilter = 0;
7384
7385         /*
7386          * Enable Refclk and SSC
7387          */
7388         I915_WRITE(dpll_reg,
7389                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7390
7391         mutex_lock(&dev_priv->sb_lock);
7392
7393         /* p1 and p2 divider */
7394         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7395                         5 << DPIO_CHV_S1_DIV_SHIFT |
7396                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7397                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7398                         1 << DPIO_CHV_K_DIV_SHIFT);
7399
7400         /* Feedback post-divider - m2 */
7401         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7402
7403         /* Feedback refclk divider - n and m1 */
7404         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7405                         DPIO_CHV_M1_DIV_BY_2 |
7406                         1 << DPIO_CHV_N_DIV_SHIFT);
7407
7408         /* M2 fraction division */
7409         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7410
7411         /* M2 fraction division enable */
7412         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7413         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7414         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7415         if (bestm2_frac)
7416                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7417         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7418
7419         /* Program digital lock detect threshold */
7420         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7421         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7422                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7423         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7424         if (!bestm2_frac)
7425                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7426         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7427
7428         /* Loop filter */
7429         if (vco == 5400000) {
7430                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7431                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7432                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433                 tribuf_calcntr = 0x9;
7434         } else if (vco <= 6200000) {
7435                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7436                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7437                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7438                 tribuf_calcntr = 0x9;
7439         } else if (vco <= 6480000) {
7440                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7441                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7442                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7443                 tribuf_calcntr = 0x8;
7444         } else {
7445                 /* Not supported. Apply the same limits as in the max case */
7446                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7447                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7448                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7449                 tribuf_calcntr = 0;
7450         }
7451         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7452
7453         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7454         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7455         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7456         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7457
7458         /* AFC Recal */
7459         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7460                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7461                         DPIO_AFC_RECAL);
7462
7463         mutex_unlock(&dev_priv->sb_lock);
7464 }
7465
7466 /**
7467  * vlv_force_pll_on - forcibly enable just the PLL
7468  * @dev_priv: i915 private structure
7469  * @pipe: pipe PLL to enable
7470  * @dpll: PLL configuration
7471  *
7472  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7473  * in cases where we need the PLL enabled even when @pipe is not going to
7474  * be enabled.
7475  */
7476 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7477                      const struct dpll *dpll)
7478 {
7479         struct intel_crtc *crtc =
7480                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7481         struct intel_crtc_state *pipe_config;
7482
7483         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7484         if (!pipe_config)
7485                 return -ENOMEM;
7486
7487         pipe_config->base.crtc = &crtc->base;
7488         pipe_config->pixel_multiplier = 1;
7489         pipe_config->dpll = *dpll;
7490
7491         if (IS_CHERRYVIEW(dev)) {
7492                 chv_compute_dpll(crtc, pipe_config);
7493                 chv_prepare_pll(crtc, pipe_config);
7494                 chv_enable_pll(crtc, pipe_config);
7495         } else {
7496                 vlv_compute_dpll(crtc, pipe_config);
7497                 vlv_prepare_pll(crtc, pipe_config);
7498                 vlv_enable_pll(crtc, pipe_config);
7499         }
7500
7501         kfree(pipe_config);
7502
7503         return 0;
7504 }
7505
7506 /**
7507  * vlv_force_pll_off - forcibly disable just the PLL
7508  * @dev_priv: i915 private structure
7509  * @pipe: pipe PLL to disable
7510  *
7511  * Disable the PLL for @pipe. To be used in cases where we need
7512  * the PLL enabled even when @pipe is not going to be enabled.
7513  */
7514 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7515 {
7516         if (IS_CHERRYVIEW(dev))
7517                 chv_disable_pll(to_i915(dev), pipe);
7518         else
7519                 vlv_disable_pll(to_i915(dev), pipe);
7520 }
7521
7522 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7523                               struct intel_crtc_state *crtc_state,
7524                               intel_clock_t *reduced_clock,
7525                               int num_connectors)
7526 {
7527         struct drm_device *dev = crtc->base.dev;
7528         struct drm_i915_private *dev_priv = dev->dev_private;
7529         u32 dpll;
7530         bool is_sdvo;
7531         struct dpll *clock = &crtc_state->dpll;
7532
7533         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7534
7535         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7536                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7537
7538         dpll = DPLL_VGA_MODE_DIS;
7539
7540         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7541                 dpll |= DPLLB_MODE_LVDS;
7542         else
7543                 dpll |= DPLLB_MODE_DAC_SERIAL;
7544
7545         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7546                 dpll |= (crtc_state->pixel_multiplier - 1)
7547                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7548         }
7549
7550         if (is_sdvo)
7551                 dpll |= DPLL_SDVO_HIGH_SPEED;
7552
7553         if (crtc_state->has_dp_encoder)
7554                 dpll |= DPLL_SDVO_HIGH_SPEED;
7555
7556         /* compute bitmask from p1 value */
7557         if (IS_PINEVIEW(dev))
7558                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7559         else {
7560                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7561                 if (IS_G4X(dev) && reduced_clock)
7562                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7563         }
7564         switch (clock->p2) {
7565         case 5:
7566                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7567                 break;
7568         case 7:
7569                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7570                 break;
7571         case 10:
7572                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7573                 break;
7574         case 14:
7575                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7576                 break;
7577         }
7578         if (INTEL_INFO(dev)->gen >= 4)
7579                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7580
7581         if (crtc_state->sdvo_tv_clock)
7582                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7583         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7584                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7585                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7586         else
7587                 dpll |= PLL_REF_INPUT_DREFCLK;
7588
7589         dpll |= DPLL_VCO_ENABLE;
7590         crtc_state->dpll_hw_state.dpll = dpll;
7591
7592         if (INTEL_INFO(dev)->gen >= 4) {
7593                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7594                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7595                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7596         }
7597 }
7598
7599 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7600                               struct intel_crtc_state *crtc_state,
7601                               intel_clock_t *reduced_clock,
7602                               int num_connectors)
7603 {
7604         struct drm_device *dev = crtc->base.dev;
7605         struct drm_i915_private *dev_priv = dev->dev_private;
7606         u32 dpll;
7607         struct dpll *clock = &crtc_state->dpll;
7608
7609         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7610
7611         dpll = DPLL_VGA_MODE_DIS;
7612
7613         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7614                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7615         } else {
7616                 if (clock->p1 == 2)
7617                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7618                 else
7619                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7620                 if (clock->p2 == 4)
7621                         dpll |= PLL_P2_DIVIDE_BY_4;
7622         }
7623
7624         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7625                 dpll |= DPLL_DVO_2X_MODE;
7626
7627         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7628                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7629                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7630         else
7631                 dpll |= PLL_REF_INPUT_DREFCLK;
7632
7633         dpll |= DPLL_VCO_ENABLE;
7634         crtc_state->dpll_hw_state.dpll = dpll;
7635 }
7636
7637 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7638 {
7639         struct drm_device *dev = intel_crtc->base.dev;
7640         struct drm_i915_private *dev_priv = dev->dev_private;
7641         enum pipe pipe = intel_crtc->pipe;
7642         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7643         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7644         uint32_t crtc_vtotal, crtc_vblank_end;
7645         int vsyncshift = 0;
7646
7647         /* We need to be careful not to changed the adjusted mode, for otherwise
7648          * the hw state checker will get angry at the mismatch. */
7649         crtc_vtotal = adjusted_mode->crtc_vtotal;
7650         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7651
7652         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7653                 /* the chip adds 2 halflines automatically */
7654                 crtc_vtotal -= 1;
7655                 crtc_vblank_end -= 1;
7656
7657                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7658                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7659                 else
7660                         vsyncshift = adjusted_mode->crtc_hsync_start -
7661                                 adjusted_mode->crtc_htotal / 2;
7662                 if (vsyncshift < 0)
7663                         vsyncshift += adjusted_mode->crtc_htotal;
7664         }
7665
7666         if (INTEL_INFO(dev)->gen > 3)
7667                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7668
7669         I915_WRITE(HTOTAL(cpu_transcoder),
7670                    (adjusted_mode->crtc_hdisplay - 1) |
7671                    ((adjusted_mode->crtc_htotal - 1) << 16));
7672         I915_WRITE(HBLANK(cpu_transcoder),
7673                    (adjusted_mode->crtc_hblank_start - 1) |
7674                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7675         I915_WRITE(HSYNC(cpu_transcoder),
7676                    (adjusted_mode->crtc_hsync_start - 1) |
7677                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7678
7679         I915_WRITE(VTOTAL(cpu_transcoder),
7680                    (adjusted_mode->crtc_vdisplay - 1) |
7681                    ((crtc_vtotal - 1) << 16));
7682         I915_WRITE(VBLANK(cpu_transcoder),
7683                    (adjusted_mode->crtc_vblank_start - 1) |
7684                    ((crtc_vblank_end - 1) << 16));
7685         I915_WRITE(VSYNC(cpu_transcoder),
7686                    (adjusted_mode->crtc_vsync_start - 1) |
7687                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7688
7689         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7690          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7691          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7692          * bits. */
7693         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7694             (pipe == PIPE_B || pipe == PIPE_C))
7695                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7696
7697         /* pipesrc controls the size that is scaled from, which should
7698          * always be the user's requested size.
7699          */
7700         I915_WRITE(PIPESRC(pipe),
7701                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7702                    (intel_crtc->config->pipe_src_h - 1));
7703 }
7704
7705 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7706                                    struct intel_crtc_state *pipe_config)
7707 {
7708         struct drm_device *dev = crtc->base.dev;
7709         struct drm_i915_private *dev_priv = dev->dev_private;
7710         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7711         uint32_t tmp;
7712
7713         tmp = I915_READ(HTOTAL(cpu_transcoder));
7714         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7715         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7716         tmp = I915_READ(HBLANK(cpu_transcoder));
7717         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7718         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7719         tmp = I915_READ(HSYNC(cpu_transcoder));
7720         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7721         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7722
7723         tmp = I915_READ(VTOTAL(cpu_transcoder));
7724         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7725         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7726         tmp = I915_READ(VBLANK(cpu_transcoder));
7727         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7728         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7729         tmp = I915_READ(VSYNC(cpu_transcoder));
7730         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7731         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7732
7733         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7734                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7735                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7736                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7737         }
7738
7739         tmp = I915_READ(PIPESRC(crtc->pipe));
7740         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7741         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7742
7743         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7744         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7745 }
7746
7747 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7748                                  struct intel_crtc_state *pipe_config)
7749 {
7750         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7751         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7752         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7753         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7754
7755         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7756         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7757         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7758         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7759
7760         mode->flags = pipe_config->base.adjusted_mode.flags;
7761         mode->type = DRM_MODE_TYPE_DRIVER;
7762
7763         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7764         mode->flags |= pipe_config->base.adjusted_mode.flags;
7765
7766         mode->hsync = drm_mode_hsync(mode);
7767         mode->vrefresh = drm_mode_vrefresh(mode);
7768         drm_mode_set_name(mode);
7769 }
7770
7771 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7772 {
7773         struct drm_device *dev = intel_crtc->base.dev;
7774         struct drm_i915_private *dev_priv = dev->dev_private;
7775         uint32_t pipeconf;
7776
7777         pipeconf = 0;
7778
7779         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7780             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7781                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7782
7783         if (intel_crtc->config->double_wide)
7784                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7785
7786         /* only g4x and later have fancy bpc/dither controls */
7787         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7788                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7789                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7790                         pipeconf |= PIPECONF_DITHER_EN |
7791                                     PIPECONF_DITHER_TYPE_SP;
7792
7793                 switch (intel_crtc->config->pipe_bpp) {
7794                 case 18:
7795                         pipeconf |= PIPECONF_6BPC;
7796                         break;
7797                 case 24:
7798                         pipeconf |= PIPECONF_8BPC;
7799                         break;
7800                 case 30:
7801                         pipeconf |= PIPECONF_10BPC;
7802                         break;
7803                 default:
7804                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7805                         BUG();
7806                 }
7807         }
7808
7809         if (HAS_PIPE_CXSR(dev)) {
7810                 if (intel_crtc->lowfreq_avail) {
7811                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7812                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7813                 } else {
7814                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7815                 }
7816         }
7817
7818         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7819                 if (INTEL_INFO(dev)->gen < 4 ||
7820                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7821                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7822                 else
7823                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7824         } else
7825                 pipeconf |= PIPECONF_PROGRESSIVE;
7826
7827         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7828              intel_crtc->config->limited_color_range)
7829                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7830
7831         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7832         POSTING_READ(PIPECONF(intel_crtc->pipe));
7833 }
7834
7835 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7836                                    struct intel_crtc_state *crtc_state)
7837 {
7838         struct drm_device *dev = crtc->base.dev;
7839         struct drm_i915_private *dev_priv = dev->dev_private;
7840         int refclk, num_connectors = 0;
7841         intel_clock_t clock;
7842         bool ok;
7843         const intel_limit_t *limit;
7844         struct drm_atomic_state *state = crtc_state->base.state;
7845         struct drm_connector *connector;
7846         struct drm_connector_state *connector_state;
7847         int i;
7848
7849         memset(&crtc_state->dpll_hw_state, 0,
7850                sizeof(crtc_state->dpll_hw_state));
7851
7852         if (crtc_state->has_dsi_encoder)
7853                 return 0;
7854
7855         for_each_connector_in_state(state, connector, connector_state, i) {
7856                 if (connector_state->crtc == &crtc->base)
7857                         num_connectors++;
7858         }
7859
7860         if (!crtc_state->clock_set) {
7861                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7862
7863                 /*
7864                  * Returns a set of divisors for the desired target clock with
7865                  * the given refclk, or FALSE.  The returned values represent
7866                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7867                  * 2) / p1 / p2.
7868                  */
7869                 limit = intel_limit(crtc_state, refclk);
7870                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7871                                                  crtc_state->port_clock,
7872                                                  refclk, NULL, &clock);
7873                 if (!ok) {
7874                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7875                         return -EINVAL;
7876                 }
7877
7878                 /* Compat-code for transition, will disappear. */
7879                 crtc_state->dpll.n = clock.n;
7880                 crtc_state->dpll.m1 = clock.m1;
7881                 crtc_state->dpll.m2 = clock.m2;
7882                 crtc_state->dpll.p1 = clock.p1;
7883                 crtc_state->dpll.p2 = clock.p2;
7884         }
7885
7886         if (IS_GEN2(dev)) {
7887                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7888                                   num_connectors);
7889         } else if (IS_CHERRYVIEW(dev)) {
7890                 chv_compute_dpll(crtc, crtc_state);
7891         } else if (IS_VALLEYVIEW(dev)) {
7892                 vlv_compute_dpll(crtc, crtc_state);
7893         } else {
7894                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7895                                   num_connectors);
7896         }
7897
7898         return 0;
7899 }
7900
7901 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7902                                  struct intel_crtc_state *pipe_config)
7903 {
7904         struct drm_device *dev = crtc->base.dev;
7905         struct drm_i915_private *dev_priv = dev->dev_private;
7906         uint32_t tmp;
7907
7908         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7909                 return;
7910
7911         tmp = I915_READ(PFIT_CONTROL);
7912         if (!(tmp & PFIT_ENABLE))
7913                 return;
7914
7915         /* Check whether the pfit is attached to our pipe. */
7916         if (INTEL_INFO(dev)->gen < 4) {
7917                 if (crtc->pipe != PIPE_B)
7918                         return;
7919         } else {
7920                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7921                         return;
7922         }
7923
7924         pipe_config->gmch_pfit.control = tmp;
7925         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7926         if (INTEL_INFO(dev)->gen < 5)
7927                 pipe_config->gmch_pfit.lvds_border_bits =
7928                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7929 }
7930
7931 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7932                                struct intel_crtc_state *pipe_config)
7933 {
7934         struct drm_device *dev = crtc->base.dev;
7935         struct drm_i915_private *dev_priv = dev->dev_private;
7936         int pipe = pipe_config->cpu_transcoder;
7937         intel_clock_t clock;
7938         u32 mdiv;
7939         int refclk = 100000;
7940
7941         /* In case of MIPI DPLL will not even be used */
7942         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7943                 return;
7944
7945         mutex_lock(&dev_priv->sb_lock);
7946         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7947         mutex_unlock(&dev_priv->sb_lock);
7948
7949         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7950         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7951         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7952         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7953         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7954
7955         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7956 }
7957
7958 static void
7959 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7960                               struct intel_initial_plane_config *plane_config)
7961 {
7962         struct drm_device *dev = crtc->base.dev;
7963         struct drm_i915_private *dev_priv = dev->dev_private;
7964         u32 val, base, offset;
7965         int pipe = crtc->pipe, plane = crtc->plane;
7966         int fourcc, pixel_format;
7967         unsigned int aligned_height;
7968         struct drm_framebuffer *fb;
7969         struct intel_framebuffer *intel_fb;
7970
7971         val = I915_READ(DSPCNTR(plane));
7972         if (!(val & DISPLAY_PLANE_ENABLE))
7973                 return;
7974
7975         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7976         if (!intel_fb) {
7977                 DRM_DEBUG_KMS("failed to alloc fb\n");
7978                 return;
7979         }
7980
7981         fb = &intel_fb->base;
7982
7983         if (INTEL_INFO(dev)->gen >= 4) {
7984                 if (val & DISPPLANE_TILED) {
7985                         plane_config->tiling = I915_TILING_X;
7986                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7987                 }
7988         }
7989
7990         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7991         fourcc = i9xx_format_to_fourcc(pixel_format);
7992         fb->pixel_format = fourcc;
7993         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7994
7995         if (INTEL_INFO(dev)->gen >= 4) {
7996                 if (plane_config->tiling)
7997                         offset = I915_READ(DSPTILEOFF(plane));
7998                 else
7999                         offset = I915_READ(DSPLINOFF(plane));
8000                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8001         } else {
8002                 base = I915_READ(DSPADDR(plane));
8003         }
8004         plane_config->base = base;
8005
8006         val = I915_READ(PIPESRC(pipe));
8007         fb->width = ((val >> 16) & 0xfff) + 1;
8008         fb->height = ((val >> 0) & 0xfff) + 1;
8009
8010         val = I915_READ(DSPSTRIDE(pipe));
8011         fb->pitches[0] = val & 0xffffffc0;
8012
8013         aligned_height = intel_fb_align_height(dev, fb->height,
8014                                                fb->pixel_format,
8015                                                fb->modifier[0]);
8016
8017         plane_config->size = fb->pitches[0] * aligned_height;
8018
8019         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8020                       pipe_name(pipe), plane, fb->width, fb->height,
8021                       fb->bits_per_pixel, base, fb->pitches[0],
8022                       plane_config->size);
8023
8024         plane_config->fb = intel_fb;
8025 }
8026
8027 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8028                                struct intel_crtc_state *pipe_config)
8029 {
8030         struct drm_device *dev = crtc->base.dev;
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032         int pipe = pipe_config->cpu_transcoder;
8033         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8034         intel_clock_t clock;
8035         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8036         int refclk = 100000;
8037
8038         mutex_lock(&dev_priv->sb_lock);
8039         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8040         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8041         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8042         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8043         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8044         mutex_unlock(&dev_priv->sb_lock);
8045
8046         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8047         clock.m2 = (pll_dw0 & 0xff) << 22;
8048         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8049                 clock.m2 |= pll_dw2 & 0x3fffff;
8050         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8051         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8052         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8053
8054         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8055 }
8056
8057 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8058                                  struct intel_crtc_state *pipe_config)
8059 {
8060         struct drm_device *dev = crtc->base.dev;
8061         struct drm_i915_private *dev_priv = dev->dev_private;
8062         enum intel_display_power_domain power_domain;
8063         uint32_t tmp;
8064         bool ret;
8065
8066         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8067         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8068                 return false;
8069
8070         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8071         pipe_config->shared_dpll = NULL;
8072
8073         ret = false;
8074
8075         tmp = I915_READ(PIPECONF(crtc->pipe));
8076         if (!(tmp & PIPECONF_ENABLE))
8077                 goto out;
8078
8079         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8080                 switch (tmp & PIPECONF_BPC_MASK) {
8081                 case PIPECONF_6BPC:
8082                         pipe_config->pipe_bpp = 18;
8083                         break;
8084                 case PIPECONF_8BPC:
8085                         pipe_config->pipe_bpp = 24;
8086                         break;
8087                 case PIPECONF_10BPC:
8088                         pipe_config->pipe_bpp = 30;
8089                         break;
8090                 default:
8091                         break;
8092                 }
8093         }
8094
8095         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8096             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8097                 pipe_config->limited_color_range = true;
8098
8099         if (INTEL_INFO(dev)->gen < 4)
8100                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8101
8102         intel_get_pipe_timings(crtc, pipe_config);
8103
8104         i9xx_get_pfit_config(crtc, pipe_config);
8105
8106         if (INTEL_INFO(dev)->gen >= 4) {
8107                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8108                 pipe_config->pixel_multiplier =
8109                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8110                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8111                 pipe_config->dpll_hw_state.dpll_md = tmp;
8112         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8113                 tmp = I915_READ(DPLL(crtc->pipe));
8114                 pipe_config->pixel_multiplier =
8115                         ((tmp & SDVO_MULTIPLIER_MASK)
8116                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8117         } else {
8118                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8119                  * port and will be fixed up in the encoder->get_config
8120                  * function. */
8121                 pipe_config->pixel_multiplier = 1;
8122         }
8123         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8124         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8125                 /*
8126                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8127                  * on 830. Filter it out here so that we don't
8128                  * report errors due to that.
8129                  */
8130                 if (IS_I830(dev))
8131                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8132
8133                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8134                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8135         } else {
8136                 /* Mask out read-only status bits. */
8137                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8138                                                      DPLL_PORTC_READY_MASK |
8139                                                      DPLL_PORTB_READY_MASK);
8140         }
8141
8142         if (IS_CHERRYVIEW(dev))
8143                 chv_crtc_clock_get(crtc, pipe_config);
8144         else if (IS_VALLEYVIEW(dev))
8145                 vlv_crtc_clock_get(crtc, pipe_config);
8146         else
8147                 i9xx_crtc_clock_get(crtc, pipe_config);
8148
8149         /*
8150          * Normally the dotclock is filled in by the encoder .get_config()
8151          * but in case the pipe is enabled w/o any ports we need a sane
8152          * default.
8153          */
8154         pipe_config->base.adjusted_mode.crtc_clock =
8155                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8156
8157         ret = true;
8158
8159 out:
8160         intel_display_power_put(dev_priv, power_domain);
8161
8162         return ret;
8163 }
8164
8165 static void ironlake_init_pch_refclk(struct drm_device *dev)
8166 {
8167         struct drm_i915_private *dev_priv = dev->dev_private;
8168         struct intel_encoder *encoder;
8169         u32 val, final;
8170         bool has_lvds = false;
8171         bool has_cpu_edp = false;
8172         bool has_panel = false;
8173         bool has_ck505 = false;
8174         bool can_ssc = false;
8175
8176         /* We need to take the global config into account */
8177         for_each_intel_encoder(dev, encoder) {
8178                 switch (encoder->type) {
8179                 case INTEL_OUTPUT_LVDS:
8180                         has_panel = true;
8181                         has_lvds = true;
8182                         break;
8183                 case INTEL_OUTPUT_EDP:
8184                         has_panel = true;
8185                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8186                                 has_cpu_edp = true;
8187                         break;
8188                 default:
8189                         break;
8190                 }
8191         }
8192
8193         if (HAS_PCH_IBX(dev)) {
8194                 has_ck505 = dev_priv->vbt.display_clock_mode;
8195                 can_ssc = has_ck505;
8196         } else {
8197                 has_ck505 = false;
8198                 can_ssc = true;
8199         }
8200
8201         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8202                       has_panel, has_lvds, has_ck505);
8203
8204         /* Ironlake: try to setup display ref clock before DPLL
8205          * enabling. This is only under driver's control after
8206          * PCH B stepping, previous chipset stepping should be
8207          * ignoring this setting.
8208          */
8209         val = I915_READ(PCH_DREF_CONTROL);
8210
8211         /* As we must carefully and slowly disable/enable each source in turn,
8212          * compute the final state we want first and check if we need to
8213          * make any changes at all.
8214          */
8215         final = val;
8216         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8217         if (has_ck505)
8218                 final |= DREF_NONSPREAD_CK505_ENABLE;
8219         else
8220                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8221
8222         final &= ~DREF_SSC_SOURCE_MASK;
8223         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8224         final &= ~DREF_SSC1_ENABLE;
8225
8226         if (has_panel) {
8227                 final |= DREF_SSC_SOURCE_ENABLE;
8228
8229                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8230                         final |= DREF_SSC1_ENABLE;
8231
8232                 if (has_cpu_edp) {
8233                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8234                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8235                         else
8236                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8237                 } else
8238                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8239         } else {
8240                 final |= DREF_SSC_SOURCE_DISABLE;
8241                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8242         }
8243
8244         if (final == val)
8245                 return;
8246
8247         /* Always enable nonspread source */
8248         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8249
8250         if (has_ck505)
8251                 val |= DREF_NONSPREAD_CK505_ENABLE;
8252         else
8253                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8254
8255         if (has_panel) {
8256                 val &= ~DREF_SSC_SOURCE_MASK;
8257                 val |= DREF_SSC_SOURCE_ENABLE;
8258
8259                 /* SSC must be turned on before enabling the CPU output  */
8260                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8261                         DRM_DEBUG_KMS("Using SSC on panel\n");
8262                         val |= DREF_SSC1_ENABLE;
8263                 } else
8264                         val &= ~DREF_SSC1_ENABLE;
8265
8266                 /* Get SSC going before enabling the outputs */
8267                 I915_WRITE(PCH_DREF_CONTROL, val);
8268                 POSTING_READ(PCH_DREF_CONTROL);
8269                 udelay(200);
8270
8271                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8272
8273                 /* Enable CPU source on CPU attached eDP */
8274                 if (has_cpu_edp) {
8275                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8276                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8277                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8278                         } else
8279                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8280                 } else
8281                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8282
8283                 I915_WRITE(PCH_DREF_CONTROL, val);
8284                 POSTING_READ(PCH_DREF_CONTROL);
8285                 udelay(200);
8286         } else {
8287                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8288
8289                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8290
8291                 /* Turn off CPU output */
8292                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8293
8294                 I915_WRITE(PCH_DREF_CONTROL, val);
8295                 POSTING_READ(PCH_DREF_CONTROL);
8296                 udelay(200);
8297
8298                 /* Turn off the SSC source */
8299                 val &= ~DREF_SSC_SOURCE_MASK;
8300                 val |= DREF_SSC_SOURCE_DISABLE;
8301
8302                 /* Turn off SSC1 */
8303                 val &= ~DREF_SSC1_ENABLE;
8304
8305                 I915_WRITE(PCH_DREF_CONTROL, val);
8306                 POSTING_READ(PCH_DREF_CONTROL);
8307                 udelay(200);
8308         }
8309
8310         BUG_ON(val != final);
8311 }
8312
8313 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8314 {
8315         uint32_t tmp;
8316
8317         tmp = I915_READ(SOUTH_CHICKEN2);
8318         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8319         I915_WRITE(SOUTH_CHICKEN2, tmp);
8320
8321         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8322                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8323                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8324
8325         tmp = I915_READ(SOUTH_CHICKEN2);
8326         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8327         I915_WRITE(SOUTH_CHICKEN2, tmp);
8328
8329         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8330                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8331                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8332 }
8333
8334 /* WaMPhyProgramming:hsw */
8335 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8336 {
8337         uint32_t tmp;
8338
8339         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8340         tmp &= ~(0xFF << 24);
8341         tmp |= (0x12 << 24);
8342         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8343
8344         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8345         tmp |= (1 << 11);
8346         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8347
8348         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8349         tmp |= (1 << 11);
8350         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8351
8352         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8353         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8354         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8355
8356         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8357         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8358         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8359
8360         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8361         tmp &= ~(7 << 13);
8362         tmp |= (5 << 13);
8363         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8364
8365         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8366         tmp &= ~(7 << 13);
8367         tmp |= (5 << 13);
8368         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8369
8370         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8371         tmp &= ~0xFF;
8372         tmp |= 0x1C;
8373         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8374
8375         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8376         tmp &= ~0xFF;
8377         tmp |= 0x1C;
8378         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8379
8380         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8381         tmp &= ~(0xFF << 16);
8382         tmp |= (0x1C << 16);
8383         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8384
8385         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8386         tmp &= ~(0xFF << 16);
8387         tmp |= (0x1C << 16);
8388         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8389
8390         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8391         tmp |= (1 << 27);
8392         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8393
8394         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8395         tmp |= (1 << 27);
8396         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8397
8398         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8399         tmp &= ~(0xF << 28);
8400         tmp |= (4 << 28);
8401         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8402
8403         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8404         tmp &= ~(0xF << 28);
8405         tmp |= (4 << 28);
8406         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8407 }
8408
8409 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8410  * Programming" based on the parameters passed:
8411  * - Sequence to enable CLKOUT_DP
8412  * - Sequence to enable CLKOUT_DP without spread
8413  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8414  */
8415 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8416                                  bool with_fdi)
8417 {
8418         struct drm_i915_private *dev_priv = dev->dev_private;
8419         uint32_t reg, tmp;
8420
8421         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8422                 with_spread = true;
8423         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8424                 with_fdi = false;
8425
8426         mutex_lock(&dev_priv->sb_lock);
8427
8428         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8429         tmp &= ~SBI_SSCCTL_DISABLE;
8430         tmp |= SBI_SSCCTL_PATHALT;
8431         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8432
8433         udelay(24);
8434
8435         if (with_spread) {
8436                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8437                 tmp &= ~SBI_SSCCTL_PATHALT;
8438                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8439
8440                 if (with_fdi) {
8441                         lpt_reset_fdi_mphy(dev_priv);
8442                         lpt_program_fdi_mphy(dev_priv);
8443                 }
8444         }
8445
8446         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8447         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8448         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8449         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8450
8451         mutex_unlock(&dev_priv->sb_lock);
8452 }
8453
8454 /* Sequence to disable CLKOUT_DP */
8455 static void lpt_disable_clkout_dp(struct drm_device *dev)
8456 {
8457         struct drm_i915_private *dev_priv = dev->dev_private;
8458         uint32_t reg, tmp;
8459
8460         mutex_lock(&dev_priv->sb_lock);
8461
8462         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8463         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8464         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8465         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8466
8467         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8468         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8469                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8470                         tmp |= SBI_SSCCTL_PATHALT;
8471                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8472                         udelay(32);
8473                 }
8474                 tmp |= SBI_SSCCTL_DISABLE;
8475                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8476         }
8477
8478         mutex_unlock(&dev_priv->sb_lock);
8479 }
8480
8481 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8482
8483 static const uint16_t sscdivintphase[] = {
8484         [BEND_IDX( 50)] = 0x3B23,
8485         [BEND_IDX( 45)] = 0x3B23,
8486         [BEND_IDX( 40)] = 0x3C23,
8487         [BEND_IDX( 35)] = 0x3C23,
8488         [BEND_IDX( 30)] = 0x3D23,
8489         [BEND_IDX( 25)] = 0x3D23,
8490         [BEND_IDX( 20)] = 0x3E23,
8491         [BEND_IDX( 15)] = 0x3E23,
8492         [BEND_IDX( 10)] = 0x3F23,
8493         [BEND_IDX(  5)] = 0x3F23,
8494         [BEND_IDX(  0)] = 0x0025,
8495         [BEND_IDX( -5)] = 0x0025,
8496         [BEND_IDX(-10)] = 0x0125,
8497         [BEND_IDX(-15)] = 0x0125,
8498         [BEND_IDX(-20)] = 0x0225,
8499         [BEND_IDX(-25)] = 0x0225,
8500         [BEND_IDX(-30)] = 0x0325,
8501         [BEND_IDX(-35)] = 0x0325,
8502         [BEND_IDX(-40)] = 0x0425,
8503         [BEND_IDX(-45)] = 0x0425,
8504         [BEND_IDX(-50)] = 0x0525,
8505 };
8506
8507 /*
8508  * Bend CLKOUT_DP
8509  * steps -50 to 50 inclusive, in steps of 5
8510  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8511  * change in clock period = -(steps / 10) * 5.787 ps
8512  */
8513 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8514 {
8515         uint32_t tmp;
8516         int idx = BEND_IDX(steps);
8517
8518         if (WARN_ON(steps % 5 != 0))
8519                 return;
8520
8521         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8522                 return;
8523
8524         mutex_lock(&dev_priv->sb_lock);
8525
8526         if (steps % 10 != 0)
8527                 tmp = 0xAAAAAAAB;
8528         else
8529                 tmp = 0x00000000;
8530         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8531
8532         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8533         tmp &= 0xffff0000;
8534         tmp |= sscdivintphase[idx];
8535         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8536
8537         mutex_unlock(&dev_priv->sb_lock);
8538 }
8539
8540 #undef BEND_IDX
8541
8542 static void lpt_init_pch_refclk(struct drm_device *dev)
8543 {
8544         struct intel_encoder *encoder;
8545         bool has_vga = false;
8546
8547         for_each_intel_encoder(dev, encoder) {
8548                 switch (encoder->type) {
8549                 case INTEL_OUTPUT_ANALOG:
8550                         has_vga = true;
8551                         break;
8552                 default:
8553                         break;
8554                 }
8555         }
8556
8557         if (has_vga) {
8558                 lpt_bend_clkout_dp(to_i915(dev), 0);
8559                 lpt_enable_clkout_dp(dev, true, true);
8560         } else {
8561                 lpt_disable_clkout_dp(dev);
8562         }
8563 }
8564
8565 /*
8566  * Initialize reference clocks when the driver loads
8567  */
8568 void intel_init_pch_refclk(struct drm_device *dev)
8569 {
8570         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8571                 ironlake_init_pch_refclk(dev);
8572         else if (HAS_PCH_LPT(dev))
8573                 lpt_init_pch_refclk(dev);
8574 }
8575
8576 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8577 {
8578         struct drm_device *dev = crtc_state->base.crtc->dev;
8579         struct drm_i915_private *dev_priv = dev->dev_private;
8580         struct drm_atomic_state *state = crtc_state->base.state;
8581         struct drm_connector *connector;
8582         struct drm_connector_state *connector_state;
8583         struct intel_encoder *encoder;
8584         int num_connectors = 0, i;
8585         bool is_lvds = false;
8586
8587         for_each_connector_in_state(state, connector, connector_state, i) {
8588                 if (connector_state->crtc != crtc_state->base.crtc)
8589                         continue;
8590
8591                 encoder = to_intel_encoder(connector_state->best_encoder);
8592
8593                 switch (encoder->type) {
8594                 case INTEL_OUTPUT_LVDS:
8595                         is_lvds = true;
8596                         break;
8597                 default:
8598                         break;
8599                 }
8600                 num_connectors++;
8601         }
8602
8603         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8604                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8605                               dev_priv->vbt.lvds_ssc_freq);
8606                 return dev_priv->vbt.lvds_ssc_freq;
8607         }
8608
8609         return 120000;
8610 }
8611
8612 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8613 {
8614         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8616         int pipe = intel_crtc->pipe;
8617         uint32_t val;
8618
8619         val = 0;
8620
8621         switch (intel_crtc->config->pipe_bpp) {
8622         case 18:
8623                 val |= PIPECONF_6BPC;
8624                 break;
8625         case 24:
8626                 val |= PIPECONF_8BPC;
8627                 break;
8628         case 30:
8629                 val |= PIPECONF_10BPC;
8630                 break;
8631         case 36:
8632                 val |= PIPECONF_12BPC;
8633                 break;
8634         default:
8635                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8636                 BUG();
8637         }
8638
8639         if (intel_crtc->config->dither)
8640                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8641
8642         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8643                 val |= PIPECONF_INTERLACED_ILK;
8644         else
8645                 val |= PIPECONF_PROGRESSIVE;
8646
8647         if (intel_crtc->config->limited_color_range)
8648                 val |= PIPECONF_COLOR_RANGE_SELECT;
8649
8650         I915_WRITE(PIPECONF(pipe), val);
8651         POSTING_READ(PIPECONF(pipe));
8652 }
8653
8654 /*
8655  * Set up the pipe CSC unit.
8656  *
8657  * Currently only full range RGB to limited range RGB conversion
8658  * is supported, but eventually this should handle various
8659  * RGB<->YCbCr scenarios as well.
8660  */
8661 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8662 {
8663         struct drm_device *dev = crtc->dev;
8664         struct drm_i915_private *dev_priv = dev->dev_private;
8665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666         int pipe = intel_crtc->pipe;
8667         uint16_t coeff = 0x7800; /* 1.0 */
8668
8669         /*
8670          * TODO: Check what kind of values actually come out of the pipe
8671          * with these coeff/postoff values and adjust to get the best
8672          * accuracy. Perhaps we even need to take the bpc value into
8673          * consideration.
8674          */
8675
8676         if (intel_crtc->config->limited_color_range)
8677                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8678
8679         /*
8680          * GY/GU and RY/RU should be the other way around according
8681          * to BSpec, but reality doesn't agree. Just set them up in
8682          * a way that results in the correct picture.
8683          */
8684         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8685         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8686
8687         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8688         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8689
8690         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8691         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8692
8693         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8694         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8695         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8696
8697         if (INTEL_INFO(dev)->gen > 6) {
8698                 uint16_t postoff = 0;
8699
8700                 if (intel_crtc->config->limited_color_range)
8701                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8702
8703                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8704                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8705                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8706
8707                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8708         } else {
8709                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8710
8711                 if (intel_crtc->config->limited_color_range)
8712                         mode |= CSC_BLACK_SCREEN_OFFSET;
8713
8714                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8715         }
8716 }
8717
8718 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8719 {
8720         struct drm_device *dev = crtc->dev;
8721         struct drm_i915_private *dev_priv = dev->dev_private;
8722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8723         enum pipe pipe = intel_crtc->pipe;
8724         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8725         uint32_t val;
8726
8727         val = 0;
8728
8729         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8730                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8731
8732         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8733                 val |= PIPECONF_INTERLACED_ILK;
8734         else
8735                 val |= PIPECONF_PROGRESSIVE;
8736
8737         I915_WRITE(PIPECONF(cpu_transcoder), val);
8738         POSTING_READ(PIPECONF(cpu_transcoder));
8739
8740         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8741         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8742
8743         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8744                 val = 0;
8745
8746                 switch (intel_crtc->config->pipe_bpp) {
8747                 case 18:
8748                         val |= PIPEMISC_DITHER_6_BPC;
8749                         break;
8750                 case 24:
8751                         val |= PIPEMISC_DITHER_8_BPC;
8752                         break;
8753                 case 30:
8754                         val |= PIPEMISC_DITHER_10_BPC;
8755                         break;
8756                 case 36:
8757                         val |= PIPEMISC_DITHER_12_BPC;
8758                         break;
8759                 default:
8760                         /* Case prevented by pipe_config_set_bpp. */
8761                         BUG();
8762                 }
8763
8764                 if (intel_crtc->config->dither)
8765                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8766
8767                 I915_WRITE(PIPEMISC(pipe), val);
8768         }
8769 }
8770
8771 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8772                                     struct intel_crtc_state *crtc_state,
8773                                     intel_clock_t *clock,
8774                                     bool *has_reduced_clock,
8775                                     intel_clock_t *reduced_clock)
8776 {
8777         struct drm_device *dev = crtc->dev;
8778         struct drm_i915_private *dev_priv = dev->dev_private;
8779         int refclk;
8780         const intel_limit_t *limit;
8781         bool ret;
8782
8783         refclk = ironlake_get_refclk(crtc_state);
8784
8785         /*
8786          * Returns a set of divisors for the desired target clock with the given
8787          * refclk, or FALSE.  The returned values represent the clock equation:
8788          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8789          */
8790         limit = intel_limit(crtc_state, refclk);
8791         ret = dev_priv->display.find_dpll(limit, crtc_state,
8792                                           crtc_state->port_clock,
8793                                           refclk, NULL, clock);
8794         if (!ret)
8795                 return false;
8796
8797         return true;
8798 }
8799
8800 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8801 {
8802         /*
8803          * Account for spread spectrum to avoid
8804          * oversubscribing the link. Max center spread
8805          * is 2.5%; use 5% for safety's sake.
8806          */
8807         u32 bps = target_clock * bpp * 21 / 20;
8808         return DIV_ROUND_UP(bps, link_bw * 8);
8809 }
8810
8811 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8812 {
8813         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8814 }
8815
8816 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8817                                       struct intel_crtc_state *crtc_state,
8818                                       u32 *fp,
8819                                       intel_clock_t *reduced_clock, u32 *fp2)
8820 {
8821         struct drm_crtc *crtc = &intel_crtc->base;
8822         struct drm_device *dev = crtc->dev;
8823         struct drm_i915_private *dev_priv = dev->dev_private;
8824         struct drm_atomic_state *state = crtc_state->base.state;
8825         struct drm_connector *connector;
8826         struct drm_connector_state *connector_state;
8827         struct intel_encoder *encoder;
8828         uint32_t dpll;
8829         int factor, num_connectors = 0, i;
8830         bool is_lvds = false, is_sdvo = false;
8831
8832         for_each_connector_in_state(state, connector, connector_state, i) {
8833                 if (connector_state->crtc != crtc_state->base.crtc)
8834                         continue;
8835
8836                 encoder = to_intel_encoder(connector_state->best_encoder);
8837
8838                 switch (encoder->type) {
8839                 case INTEL_OUTPUT_LVDS:
8840                         is_lvds = true;
8841                         break;
8842                 case INTEL_OUTPUT_SDVO:
8843                 case INTEL_OUTPUT_HDMI:
8844                         is_sdvo = true;
8845                         break;
8846                 default:
8847                         break;
8848                 }
8849
8850                 num_connectors++;
8851         }
8852
8853         /* Enable autotuning of the PLL clock (if permissible) */
8854         factor = 21;
8855         if (is_lvds) {
8856                 if ((intel_panel_use_ssc(dev_priv) &&
8857                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8858                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8859                         factor = 25;
8860         } else if (crtc_state->sdvo_tv_clock)
8861                 factor = 20;
8862
8863         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8864                 *fp |= FP_CB_TUNE;
8865
8866         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8867                 *fp2 |= FP_CB_TUNE;
8868
8869         dpll = 0;
8870
8871         if (is_lvds)
8872                 dpll |= DPLLB_MODE_LVDS;
8873         else
8874                 dpll |= DPLLB_MODE_DAC_SERIAL;
8875
8876         dpll |= (crtc_state->pixel_multiplier - 1)
8877                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8878
8879         if (is_sdvo)
8880                 dpll |= DPLL_SDVO_HIGH_SPEED;
8881         if (crtc_state->has_dp_encoder)
8882                 dpll |= DPLL_SDVO_HIGH_SPEED;
8883
8884         /* compute bitmask from p1 value */
8885         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8886         /* also FPA1 */
8887         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8888
8889         switch (crtc_state->dpll.p2) {
8890         case 5:
8891                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8892                 break;
8893         case 7:
8894                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8895                 break;
8896         case 10:
8897                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8898                 break;
8899         case 14:
8900                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8901                 break;
8902         }
8903
8904         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8905                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8906         else
8907                 dpll |= PLL_REF_INPUT_DREFCLK;
8908
8909         return dpll | DPLL_VCO_ENABLE;
8910 }
8911
8912 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8913                                        struct intel_crtc_state *crtc_state)
8914 {
8915         struct drm_device *dev = crtc->base.dev;
8916         intel_clock_t clock, reduced_clock;
8917         u32 dpll = 0, fp = 0, fp2 = 0;
8918         bool ok, has_reduced_clock = false;
8919         bool is_lvds = false;
8920         struct intel_shared_dpll *pll;
8921
8922         memset(&crtc_state->dpll_hw_state, 0,
8923                sizeof(crtc_state->dpll_hw_state));
8924
8925         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8926
8927         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8928              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8929
8930         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8931                                      &has_reduced_clock, &reduced_clock);
8932         if (!ok && !crtc_state->clock_set) {
8933                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8934                 return -EINVAL;
8935         }
8936         /* Compat-code for transition, will disappear. */
8937         if (!crtc_state->clock_set) {
8938                 crtc_state->dpll.n = clock.n;
8939                 crtc_state->dpll.m1 = clock.m1;
8940                 crtc_state->dpll.m2 = clock.m2;
8941                 crtc_state->dpll.p1 = clock.p1;
8942                 crtc_state->dpll.p2 = clock.p2;
8943         }
8944
8945         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8946         if (crtc_state->has_pch_encoder) {
8947                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8948                 if (has_reduced_clock)
8949                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8950
8951                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8952                                              &fp, &reduced_clock,
8953                                              has_reduced_clock ? &fp2 : NULL);
8954
8955                 crtc_state->dpll_hw_state.dpll = dpll;
8956                 crtc_state->dpll_hw_state.fp0 = fp;
8957                 if (has_reduced_clock)
8958                         crtc_state->dpll_hw_state.fp1 = fp2;
8959                 else
8960                         crtc_state->dpll_hw_state.fp1 = fp;
8961
8962                 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8963                 if (pll == NULL) {
8964                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8965                                          pipe_name(crtc->pipe));
8966                         return -EINVAL;
8967                 }
8968         }
8969
8970         if (is_lvds && has_reduced_clock)
8971                 crtc->lowfreq_avail = true;
8972         else
8973                 crtc->lowfreq_avail = false;
8974
8975         return 0;
8976 }
8977
8978 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8979                                          struct intel_link_m_n *m_n)
8980 {
8981         struct drm_device *dev = crtc->base.dev;
8982         struct drm_i915_private *dev_priv = dev->dev_private;
8983         enum pipe pipe = crtc->pipe;
8984
8985         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8986         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8987         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8988                 & ~TU_SIZE_MASK;
8989         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8990         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8991                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8992 }
8993
8994 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8995                                          enum transcoder transcoder,
8996                                          struct intel_link_m_n *m_n,
8997                                          struct intel_link_m_n *m2_n2)
8998 {
8999         struct drm_device *dev = crtc->base.dev;
9000         struct drm_i915_private *dev_priv = dev->dev_private;
9001         enum pipe pipe = crtc->pipe;
9002
9003         if (INTEL_INFO(dev)->gen >= 5) {
9004                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9005                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9006                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9007                         & ~TU_SIZE_MASK;
9008                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9009                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9010                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9011                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9012                  * gen < 8) and if DRRS is supported (to make sure the
9013                  * registers are not unnecessarily read).
9014                  */
9015                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9016                         crtc->config->has_drrs) {
9017                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9018                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9019                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9020                                         & ~TU_SIZE_MASK;
9021                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9022                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9023                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9024                 }
9025         } else {
9026                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9027                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9028                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9029                         & ~TU_SIZE_MASK;
9030                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9031                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9032                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9033         }
9034 }
9035
9036 void intel_dp_get_m_n(struct intel_crtc *crtc,
9037                       struct intel_crtc_state *pipe_config)
9038 {
9039         if (pipe_config->has_pch_encoder)
9040                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9041         else
9042                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9043                                              &pipe_config->dp_m_n,
9044                                              &pipe_config->dp_m2_n2);
9045 }
9046
9047 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9048                                         struct intel_crtc_state *pipe_config)
9049 {
9050         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9051                                      &pipe_config->fdi_m_n, NULL);
9052 }
9053
9054 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9055                                     struct intel_crtc_state *pipe_config)
9056 {
9057         struct drm_device *dev = crtc->base.dev;
9058         struct drm_i915_private *dev_priv = dev->dev_private;
9059         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9060         uint32_t ps_ctrl = 0;
9061         int id = -1;
9062         int i;
9063
9064         /* find scaler attached to this pipe */
9065         for (i = 0; i < crtc->num_scalers; i++) {
9066                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9067                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9068                         id = i;
9069                         pipe_config->pch_pfit.enabled = true;
9070                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9071                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9072                         break;
9073                 }
9074         }
9075
9076         scaler_state->scaler_id = id;
9077         if (id >= 0) {
9078                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9079         } else {
9080                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9081         }
9082 }
9083
9084 static void
9085 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9086                                  struct intel_initial_plane_config *plane_config)
9087 {
9088         struct drm_device *dev = crtc->base.dev;
9089         struct drm_i915_private *dev_priv = dev->dev_private;
9090         u32 val, base, offset, stride_mult, tiling;
9091         int pipe = crtc->pipe;
9092         int fourcc, pixel_format;
9093         unsigned int aligned_height;
9094         struct drm_framebuffer *fb;
9095         struct intel_framebuffer *intel_fb;
9096
9097         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9098         if (!intel_fb) {
9099                 DRM_DEBUG_KMS("failed to alloc fb\n");
9100                 return;
9101         }
9102
9103         fb = &intel_fb->base;
9104
9105         val = I915_READ(PLANE_CTL(pipe, 0));
9106         if (!(val & PLANE_CTL_ENABLE))
9107                 goto error;
9108
9109         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9110         fourcc = skl_format_to_fourcc(pixel_format,
9111                                       val & PLANE_CTL_ORDER_RGBX,
9112                                       val & PLANE_CTL_ALPHA_MASK);
9113         fb->pixel_format = fourcc;
9114         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9115
9116         tiling = val & PLANE_CTL_TILED_MASK;
9117         switch (tiling) {
9118         case PLANE_CTL_TILED_LINEAR:
9119                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9120                 break;
9121         case PLANE_CTL_TILED_X:
9122                 plane_config->tiling = I915_TILING_X;
9123                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9124                 break;
9125         case PLANE_CTL_TILED_Y:
9126                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9127                 break;
9128         case PLANE_CTL_TILED_YF:
9129                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9130                 break;
9131         default:
9132                 MISSING_CASE(tiling);
9133                 goto error;
9134         }
9135
9136         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9137         plane_config->base = base;
9138
9139         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9140
9141         val = I915_READ(PLANE_SIZE(pipe, 0));
9142         fb->height = ((val >> 16) & 0xfff) + 1;
9143         fb->width = ((val >> 0) & 0x1fff) + 1;
9144
9145         val = I915_READ(PLANE_STRIDE(pipe, 0));
9146         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9147                                                 fb->pixel_format);
9148         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9149
9150         aligned_height = intel_fb_align_height(dev, fb->height,
9151                                                fb->pixel_format,
9152                                                fb->modifier[0]);
9153
9154         plane_config->size = fb->pitches[0] * aligned_height;
9155
9156         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9157                       pipe_name(pipe), fb->width, fb->height,
9158                       fb->bits_per_pixel, base, fb->pitches[0],
9159                       plane_config->size);
9160
9161         plane_config->fb = intel_fb;
9162         return;
9163
9164 error:
9165         kfree(fb);
9166 }
9167
9168 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9169                                      struct intel_crtc_state *pipe_config)
9170 {
9171         struct drm_device *dev = crtc->base.dev;
9172         struct drm_i915_private *dev_priv = dev->dev_private;
9173         uint32_t tmp;
9174
9175         tmp = I915_READ(PF_CTL(crtc->pipe));
9176
9177         if (tmp & PF_ENABLE) {
9178                 pipe_config->pch_pfit.enabled = true;
9179                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9180                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9181
9182                 /* We currently do not free assignements of panel fitters on
9183                  * ivb/hsw (since we don't use the higher upscaling modes which
9184                  * differentiates them) so just WARN about this case for now. */
9185                 if (IS_GEN7(dev)) {
9186                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9187                                 PF_PIPE_SEL_IVB(crtc->pipe));
9188                 }
9189         }
9190 }
9191
9192 static void
9193 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9194                                   struct intel_initial_plane_config *plane_config)
9195 {
9196         struct drm_device *dev = crtc->base.dev;
9197         struct drm_i915_private *dev_priv = dev->dev_private;
9198         u32 val, base, offset;
9199         int pipe = crtc->pipe;
9200         int fourcc, pixel_format;
9201         unsigned int aligned_height;
9202         struct drm_framebuffer *fb;
9203         struct intel_framebuffer *intel_fb;
9204
9205         val = I915_READ(DSPCNTR(pipe));
9206         if (!(val & DISPLAY_PLANE_ENABLE))
9207                 return;
9208
9209         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9210         if (!intel_fb) {
9211                 DRM_DEBUG_KMS("failed to alloc fb\n");
9212                 return;
9213         }
9214
9215         fb = &intel_fb->base;
9216
9217         if (INTEL_INFO(dev)->gen >= 4) {
9218                 if (val & DISPPLANE_TILED) {
9219                         plane_config->tiling = I915_TILING_X;
9220                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9221                 }
9222         }
9223
9224         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9225         fourcc = i9xx_format_to_fourcc(pixel_format);
9226         fb->pixel_format = fourcc;
9227         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9228
9229         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9230         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9231                 offset = I915_READ(DSPOFFSET(pipe));
9232         } else {
9233                 if (plane_config->tiling)
9234                         offset = I915_READ(DSPTILEOFF(pipe));
9235                 else
9236                         offset = I915_READ(DSPLINOFF(pipe));
9237         }
9238         plane_config->base = base;
9239
9240         val = I915_READ(PIPESRC(pipe));
9241         fb->width = ((val >> 16) & 0xfff) + 1;
9242         fb->height = ((val >> 0) & 0xfff) + 1;
9243
9244         val = I915_READ(DSPSTRIDE(pipe));
9245         fb->pitches[0] = val & 0xffffffc0;
9246
9247         aligned_height = intel_fb_align_height(dev, fb->height,
9248                                                fb->pixel_format,
9249                                                fb->modifier[0]);
9250
9251         plane_config->size = fb->pitches[0] * aligned_height;
9252
9253         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9254                       pipe_name(pipe), fb->width, fb->height,
9255                       fb->bits_per_pixel, base, fb->pitches[0],
9256                       plane_config->size);
9257
9258         plane_config->fb = intel_fb;
9259 }
9260
9261 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9262                                      struct intel_crtc_state *pipe_config)
9263 {
9264         struct drm_device *dev = crtc->base.dev;
9265         struct drm_i915_private *dev_priv = dev->dev_private;
9266         enum intel_display_power_domain power_domain;
9267         uint32_t tmp;
9268         bool ret;
9269
9270         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9271         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9272                 return false;
9273
9274         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9275         pipe_config->shared_dpll = NULL;
9276
9277         ret = false;
9278         tmp = I915_READ(PIPECONF(crtc->pipe));
9279         if (!(tmp & PIPECONF_ENABLE))
9280                 goto out;
9281
9282         switch (tmp & PIPECONF_BPC_MASK) {
9283         case PIPECONF_6BPC:
9284                 pipe_config->pipe_bpp = 18;
9285                 break;
9286         case PIPECONF_8BPC:
9287                 pipe_config->pipe_bpp = 24;
9288                 break;
9289         case PIPECONF_10BPC:
9290                 pipe_config->pipe_bpp = 30;
9291                 break;
9292         case PIPECONF_12BPC:
9293                 pipe_config->pipe_bpp = 36;
9294                 break;
9295         default:
9296                 break;
9297         }
9298
9299         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9300                 pipe_config->limited_color_range = true;
9301
9302         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9303                 struct intel_shared_dpll *pll;
9304                 enum intel_dpll_id pll_id;
9305
9306                 pipe_config->has_pch_encoder = true;
9307
9308                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9309                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9310                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9311
9312                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9313
9314                 if (HAS_PCH_IBX(dev_priv->dev)) {
9315                         pll_id = (enum intel_dpll_id) crtc->pipe;
9316                 } else {
9317                         tmp = I915_READ(PCH_DPLL_SEL);
9318                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9319                                 pll_id = DPLL_ID_PCH_PLL_B;
9320                         else
9321                                 pll_id= DPLL_ID_PCH_PLL_A;
9322                 }
9323
9324                 pipe_config->shared_dpll =
9325                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9326                 pll = pipe_config->shared_dpll;
9327
9328                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9329                                                  &pipe_config->dpll_hw_state));
9330
9331                 tmp = pipe_config->dpll_hw_state.dpll;
9332                 pipe_config->pixel_multiplier =
9333                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9334                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9335
9336                 ironlake_pch_clock_get(crtc, pipe_config);
9337         } else {
9338                 pipe_config->pixel_multiplier = 1;
9339         }
9340
9341         intel_get_pipe_timings(crtc, pipe_config);
9342
9343         ironlake_get_pfit_config(crtc, pipe_config);
9344
9345         ret = true;
9346
9347 out:
9348         intel_display_power_put(dev_priv, power_domain);
9349
9350         return ret;
9351 }
9352
9353 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9354 {
9355         struct drm_device *dev = dev_priv->dev;
9356         struct intel_crtc *crtc;
9357
9358         for_each_intel_crtc(dev, crtc)
9359                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9360                      pipe_name(crtc->pipe));
9361
9362         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9363         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9364         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9365         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9366         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9367         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9368              "CPU PWM1 enabled\n");
9369         if (IS_HASWELL(dev))
9370                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9371                      "CPU PWM2 enabled\n");
9372         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9373              "PCH PWM1 enabled\n");
9374         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9375              "Utility pin enabled\n");
9376         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9377
9378         /*
9379          * In theory we can still leave IRQs enabled, as long as only the HPD
9380          * interrupts remain enabled. We used to check for that, but since it's
9381          * gen-specific and since we only disable LCPLL after we fully disable
9382          * the interrupts, the check below should be enough.
9383          */
9384         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9385 }
9386
9387 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9388 {
9389         struct drm_device *dev = dev_priv->dev;
9390
9391         if (IS_HASWELL(dev))
9392                 return I915_READ(D_COMP_HSW);
9393         else
9394                 return I915_READ(D_COMP_BDW);
9395 }
9396
9397 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9398 {
9399         struct drm_device *dev = dev_priv->dev;
9400
9401         if (IS_HASWELL(dev)) {
9402                 mutex_lock(&dev_priv->rps.hw_lock);
9403                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9404                                             val))
9405                         DRM_ERROR("Failed to write to D_COMP\n");
9406                 mutex_unlock(&dev_priv->rps.hw_lock);
9407         } else {
9408                 I915_WRITE(D_COMP_BDW, val);
9409                 POSTING_READ(D_COMP_BDW);
9410         }
9411 }
9412
9413 /*
9414  * This function implements pieces of two sequences from BSpec:
9415  * - Sequence for display software to disable LCPLL
9416  * - Sequence for display software to allow package C8+
9417  * The steps implemented here are just the steps that actually touch the LCPLL
9418  * register. Callers should take care of disabling all the display engine
9419  * functions, doing the mode unset, fixing interrupts, etc.
9420  */
9421 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9422                               bool switch_to_fclk, bool allow_power_down)
9423 {
9424         uint32_t val;
9425
9426         assert_can_disable_lcpll(dev_priv);
9427
9428         val = I915_READ(LCPLL_CTL);
9429
9430         if (switch_to_fclk) {
9431                 val |= LCPLL_CD_SOURCE_FCLK;
9432                 I915_WRITE(LCPLL_CTL, val);
9433
9434                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9435                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9436                         DRM_ERROR("Switching to FCLK failed\n");
9437
9438                 val = I915_READ(LCPLL_CTL);
9439         }
9440
9441         val |= LCPLL_PLL_DISABLE;
9442         I915_WRITE(LCPLL_CTL, val);
9443         POSTING_READ(LCPLL_CTL);
9444
9445         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9446                 DRM_ERROR("LCPLL still locked\n");
9447
9448         val = hsw_read_dcomp(dev_priv);
9449         val |= D_COMP_COMP_DISABLE;
9450         hsw_write_dcomp(dev_priv, val);
9451         ndelay(100);
9452
9453         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9454                      1))
9455                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9456
9457         if (allow_power_down) {
9458                 val = I915_READ(LCPLL_CTL);
9459                 val |= LCPLL_POWER_DOWN_ALLOW;
9460                 I915_WRITE(LCPLL_CTL, val);
9461                 POSTING_READ(LCPLL_CTL);
9462         }
9463 }
9464
9465 /*
9466  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9467  * source.
9468  */
9469 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9470 {
9471         uint32_t val;
9472
9473         val = I915_READ(LCPLL_CTL);
9474
9475         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9476                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9477                 return;
9478
9479         /*
9480          * Make sure we're not on PC8 state before disabling PC8, otherwise
9481          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9482          */
9483         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9484
9485         if (val & LCPLL_POWER_DOWN_ALLOW) {
9486                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9487                 I915_WRITE(LCPLL_CTL, val);
9488                 POSTING_READ(LCPLL_CTL);
9489         }
9490
9491         val = hsw_read_dcomp(dev_priv);
9492         val |= D_COMP_COMP_FORCE;
9493         val &= ~D_COMP_COMP_DISABLE;
9494         hsw_write_dcomp(dev_priv, val);
9495
9496         val = I915_READ(LCPLL_CTL);
9497         val &= ~LCPLL_PLL_DISABLE;
9498         I915_WRITE(LCPLL_CTL, val);
9499
9500         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9501                 DRM_ERROR("LCPLL not locked yet\n");
9502
9503         if (val & LCPLL_CD_SOURCE_FCLK) {
9504                 val = I915_READ(LCPLL_CTL);
9505                 val &= ~LCPLL_CD_SOURCE_FCLK;
9506                 I915_WRITE(LCPLL_CTL, val);
9507
9508                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9509                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9510                         DRM_ERROR("Switching back to LCPLL failed\n");
9511         }
9512
9513         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9514         intel_update_cdclk(dev_priv->dev);
9515 }
9516
9517 /*
9518  * Package states C8 and deeper are really deep PC states that can only be
9519  * reached when all the devices on the system allow it, so even if the graphics
9520  * device allows PC8+, it doesn't mean the system will actually get to these
9521  * states. Our driver only allows PC8+ when going into runtime PM.
9522  *
9523  * The requirements for PC8+ are that all the outputs are disabled, the power
9524  * well is disabled and most interrupts are disabled, and these are also
9525  * requirements for runtime PM. When these conditions are met, we manually do
9526  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9527  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9528  * hang the machine.
9529  *
9530  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9531  * the state of some registers, so when we come back from PC8+ we need to
9532  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9533  * need to take care of the registers kept by RC6. Notice that this happens even
9534  * if we don't put the device in PCI D3 state (which is what currently happens
9535  * because of the runtime PM support).
9536  *
9537  * For more, read "Display Sequences for Package C8" on the hardware
9538  * documentation.
9539  */
9540 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9541 {
9542         struct drm_device *dev = dev_priv->dev;
9543         uint32_t val;
9544
9545         DRM_DEBUG_KMS("Enabling package C8+\n");
9546
9547         if (HAS_PCH_LPT_LP(dev)) {
9548                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9549                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9550                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9551         }
9552
9553         lpt_disable_clkout_dp(dev);
9554         hsw_disable_lcpll(dev_priv, true, true);
9555 }
9556
9557 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9558 {
9559         struct drm_device *dev = dev_priv->dev;
9560         uint32_t val;
9561
9562         DRM_DEBUG_KMS("Disabling package C8+\n");
9563
9564         hsw_restore_lcpll(dev_priv);
9565         lpt_init_pch_refclk(dev);
9566
9567         if (HAS_PCH_LPT_LP(dev)) {
9568                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9569                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9570                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9571         }
9572 }
9573
9574 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9575 {
9576         struct drm_device *dev = old_state->dev;
9577         struct intel_atomic_state *old_intel_state =
9578                 to_intel_atomic_state(old_state);
9579         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9580
9581         broxton_set_cdclk(dev, req_cdclk);
9582 }
9583
9584 /* compute the max rate for new configuration */
9585 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9586 {
9587         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9588         struct drm_i915_private *dev_priv = state->dev->dev_private;
9589         struct drm_crtc *crtc;
9590         struct drm_crtc_state *cstate;
9591         struct intel_crtc_state *crtc_state;
9592         unsigned max_pixel_rate = 0, i;
9593         enum pipe pipe;
9594
9595         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9596                sizeof(intel_state->min_pixclk));
9597
9598         for_each_crtc_in_state(state, crtc, cstate, i) {
9599                 int pixel_rate;
9600
9601                 crtc_state = to_intel_crtc_state(cstate);
9602                 if (!crtc_state->base.enable) {
9603                         intel_state->min_pixclk[i] = 0;
9604                         continue;
9605                 }
9606
9607                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9608
9609                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9610                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9611                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9612
9613                 intel_state->min_pixclk[i] = pixel_rate;
9614         }
9615
9616         for_each_pipe(dev_priv, pipe)
9617                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9618
9619         return max_pixel_rate;
9620 }
9621
9622 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9623 {
9624         struct drm_i915_private *dev_priv = dev->dev_private;
9625         uint32_t val, data;
9626         int ret;
9627
9628         if (WARN((I915_READ(LCPLL_CTL) &
9629                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9630                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9631                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9632                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9633                  "trying to change cdclk frequency with cdclk not enabled\n"))
9634                 return;
9635
9636         mutex_lock(&dev_priv->rps.hw_lock);
9637         ret = sandybridge_pcode_write(dev_priv,
9638                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9639         mutex_unlock(&dev_priv->rps.hw_lock);
9640         if (ret) {
9641                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9642                 return;
9643         }
9644
9645         val = I915_READ(LCPLL_CTL);
9646         val |= LCPLL_CD_SOURCE_FCLK;
9647         I915_WRITE(LCPLL_CTL, val);
9648
9649         if (wait_for_us(I915_READ(LCPLL_CTL) &
9650                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9651                 DRM_ERROR("Switching to FCLK failed\n");
9652
9653         val = I915_READ(LCPLL_CTL);
9654         val &= ~LCPLL_CLK_FREQ_MASK;
9655
9656         switch (cdclk) {
9657         case 450000:
9658                 val |= LCPLL_CLK_FREQ_450;
9659                 data = 0;
9660                 break;
9661         case 540000:
9662                 val |= LCPLL_CLK_FREQ_54O_BDW;
9663                 data = 1;
9664                 break;
9665         case 337500:
9666                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9667                 data = 2;
9668                 break;
9669         case 675000:
9670                 val |= LCPLL_CLK_FREQ_675_BDW;
9671                 data = 3;
9672                 break;
9673         default:
9674                 WARN(1, "invalid cdclk frequency\n");
9675                 return;
9676         }
9677
9678         I915_WRITE(LCPLL_CTL, val);
9679
9680         val = I915_READ(LCPLL_CTL);
9681         val &= ~LCPLL_CD_SOURCE_FCLK;
9682         I915_WRITE(LCPLL_CTL, val);
9683
9684         if (wait_for_us((I915_READ(LCPLL_CTL) &
9685                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9686                 DRM_ERROR("Switching back to LCPLL failed\n");
9687
9688         mutex_lock(&dev_priv->rps.hw_lock);
9689         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9690         mutex_unlock(&dev_priv->rps.hw_lock);
9691
9692         intel_update_cdclk(dev);
9693
9694         WARN(cdclk != dev_priv->cdclk_freq,
9695              "cdclk requested %d kHz but got %d kHz\n",
9696              cdclk, dev_priv->cdclk_freq);
9697 }
9698
9699 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9700 {
9701         struct drm_i915_private *dev_priv = to_i915(state->dev);
9702         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9703         int max_pixclk = ilk_max_pixel_rate(state);
9704         int cdclk;
9705
9706         /*
9707          * FIXME should also account for plane ratio
9708          * once 64bpp pixel formats are supported.
9709          */
9710         if (max_pixclk > 540000)
9711                 cdclk = 675000;
9712         else if (max_pixclk > 450000)
9713                 cdclk = 540000;
9714         else if (max_pixclk > 337500)
9715                 cdclk = 450000;
9716         else
9717                 cdclk = 337500;
9718
9719         if (cdclk > dev_priv->max_cdclk_freq) {
9720                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9721                               cdclk, dev_priv->max_cdclk_freq);
9722                 return -EINVAL;
9723         }
9724
9725         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9726         if (!intel_state->active_crtcs)
9727                 intel_state->dev_cdclk = 337500;
9728
9729         return 0;
9730 }
9731
9732 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9733 {
9734         struct drm_device *dev = old_state->dev;
9735         struct intel_atomic_state *old_intel_state =
9736                 to_intel_atomic_state(old_state);
9737         unsigned req_cdclk = old_intel_state->dev_cdclk;
9738
9739         broadwell_set_cdclk(dev, req_cdclk);
9740 }
9741
9742 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9743                                       struct intel_crtc_state *crtc_state)
9744 {
9745         struct intel_encoder *intel_encoder =
9746                 intel_ddi_get_crtc_new_encoder(crtc_state);
9747
9748         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9749                 if (!intel_ddi_pll_select(crtc, crtc_state))
9750                         return -EINVAL;
9751         }
9752
9753         crtc->lowfreq_avail = false;
9754
9755         return 0;
9756 }
9757
9758 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9759                                 enum port port,
9760                                 struct intel_crtc_state *pipe_config)
9761 {
9762         enum intel_dpll_id id;
9763
9764         switch (port) {
9765         case PORT_A:
9766                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9767                 id = DPLL_ID_SKL_DPLL1;
9768                 break;
9769         case PORT_B:
9770                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9771                 id = DPLL_ID_SKL_DPLL2;
9772                 break;
9773         case PORT_C:
9774                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9775                 id = DPLL_ID_SKL_DPLL3;
9776                 break;
9777         default:
9778                 DRM_ERROR("Incorrect port type\n");
9779                 return;
9780         }
9781
9782         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9783 }
9784
9785 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9786                                 enum port port,
9787                                 struct intel_crtc_state *pipe_config)
9788 {
9789         enum intel_dpll_id id;
9790         u32 temp;
9791
9792         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9793         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9794
9795         switch (pipe_config->ddi_pll_sel) {
9796         case SKL_DPLL0:
9797                 id = DPLL_ID_SKL_DPLL0;
9798                 break;
9799         case SKL_DPLL1:
9800                 id = DPLL_ID_SKL_DPLL1;
9801                 break;
9802         case SKL_DPLL2:
9803                 id = DPLL_ID_SKL_DPLL2;
9804                 break;
9805         case SKL_DPLL3:
9806                 id = DPLL_ID_SKL_DPLL3;
9807                 break;
9808         default:
9809                 MISSING_CASE(pipe_config->ddi_pll_sel);
9810                 return;
9811         }
9812
9813         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9814 }
9815
9816 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9817                                 enum port port,
9818                                 struct intel_crtc_state *pipe_config)
9819 {
9820         enum intel_dpll_id id;
9821
9822         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9823
9824         switch (pipe_config->ddi_pll_sel) {
9825         case PORT_CLK_SEL_WRPLL1:
9826                 id = DPLL_ID_WRPLL1;
9827                 break;
9828         case PORT_CLK_SEL_WRPLL2:
9829                 id = DPLL_ID_WRPLL2;
9830                 break;
9831         case PORT_CLK_SEL_SPLL:
9832                 id = DPLL_ID_SPLL;
9833                 break;
9834         case PORT_CLK_SEL_LCPLL_810:
9835                 id = DPLL_ID_LCPLL_810;
9836                 break;
9837         case PORT_CLK_SEL_LCPLL_1350:
9838                 id = DPLL_ID_LCPLL_1350;
9839                 break;
9840         case PORT_CLK_SEL_LCPLL_2700:
9841                 id = DPLL_ID_LCPLL_2700;
9842                 break;
9843         default:
9844                 MISSING_CASE(pipe_config->ddi_pll_sel);
9845                 /* fall through */
9846         case PORT_CLK_SEL_NONE:
9847                 return;
9848         }
9849
9850         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9851 }
9852
9853 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9854                                        struct intel_crtc_state *pipe_config)
9855 {
9856         struct drm_device *dev = crtc->base.dev;
9857         struct drm_i915_private *dev_priv = dev->dev_private;
9858         struct intel_shared_dpll *pll;
9859         enum port port;
9860         uint32_t tmp;
9861
9862         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9863
9864         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9865
9866         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9867                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9868         else if (IS_BROXTON(dev))
9869                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9870         else
9871                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9872
9873         pll = pipe_config->shared_dpll;
9874         if (pll) {
9875                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9876                                                  &pipe_config->dpll_hw_state));
9877         }
9878
9879         /*
9880          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9881          * DDI E. So just check whether this pipe is wired to DDI E and whether
9882          * the PCH transcoder is on.
9883          */
9884         if (INTEL_INFO(dev)->gen < 9 &&
9885             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9886                 pipe_config->has_pch_encoder = true;
9887
9888                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9889                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9890                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9891
9892                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9893         }
9894 }
9895
9896 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9897                                     struct intel_crtc_state *pipe_config)
9898 {
9899         struct drm_device *dev = crtc->base.dev;
9900         struct drm_i915_private *dev_priv = dev->dev_private;
9901         enum intel_display_power_domain power_domain;
9902         unsigned long power_domain_mask;
9903         uint32_t tmp;
9904         bool ret;
9905
9906         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9907         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9908                 return false;
9909         power_domain_mask = BIT(power_domain);
9910
9911         ret = false;
9912
9913         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9914         pipe_config->shared_dpll = NULL;
9915
9916         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9917         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9918                 enum pipe trans_edp_pipe;
9919                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9920                 default:
9921                         WARN(1, "unknown pipe linked to edp transcoder\n");
9922                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9923                 case TRANS_DDI_EDP_INPUT_A_ON:
9924                         trans_edp_pipe = PIPE_A;
9925                         break;
9926                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9927                         trans_edp_pipe = PIPE_B;
9928                         break;
9929                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9930                         trans_edp_pipe = PIPE_C;
9931                         break;
9932                 }
9933
9934                 if (trans_edp_pipe == crtc->pipe)
9935                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9936         }
9937
9938         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9939         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9940                 goto out;
9941         power_domain_mask |= BIT(power_domain);
9942
9943         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9944         if (!(tmp & PIPECONF_ENABLE))
9945                 goto out;
9946
9947         haswell_get_ddi_port_state(crtc, pipe_config);
9948
9949         intel_get_pipe_timings(crtc, pipe_config);
9950
9951         if (INTEL_INFO(dev)->gen >= 9) {
9952                 skl_init_scalers(dev, crtc, pipe_config);
9953         }
9954
9955         if (INTEL_INFO(dev)->gen >= 9) {
9956                 pipe_config->scaler_state.scaler_id = -1;
9957                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9958         }
9959
9960         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9961         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9962                 power_domain_mask |= BIT(power_domain);
9963                 if (INTEL_INFO(dev)->gen >= 9)
9964                         skylake_get_pfit_config(crtc, pipe_config);
9965                 else
9966                         ironlake_get_pfit_config(crtc, pipe_config);
9967         }
9968
9969         if (IS_HASWELL(dev))
9970                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9971                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9972
9973         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9974                 pipe_config->pixel_multiplier =
9975                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9976         } else {
9977                 pipe_config->pixel_multiplier = 1;
9978         }
9979
9980         ret = true;
9981
9982 out:
9983         for_each_power_domain(power_domain, power_domain_mask)
9984                 intel_display_power_put(dev_priv, power_domain);
9985
9986         return ret;
9987 }
9988
9989 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9990                                const struct intel_plane_state *plane_state)
9991 {
9992         struct drm_device *dev = crtc->dev;
9993         struct drm_i915_private *dev_priv = dev->dev_private;
9994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9995         uint32_t cntl = 0, size = 0;
9996
9997         if (plane_state && plane_state->visible) {
9998                 unsigned int width = plane_state->base.crtc_w;
9999                 unsigned int height = plane_state->base.crtc_h;
10000                 unsigned int stride = roundup_pow_of_two(width) * 4;
10001
10002                 switch (stride) {
10003                 default:
10004                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10005                                   width, stride);
10006                         stride = 256;
10007                         /* fallthrough */
10008                 case 256:
10009                 case 512:
10010                 case 1024:
10011                 case 2048:
10012                         break;
10013                 }
10014
10015                 cntl |= CURSOR_ENABLE |
10016                         CURSOR_GAMMA_ENABLE |
10017                         CURSOR_FORMAT_ARGB |
10018                         CURSOR_STRIDE(stride);
10019
10020                 size = (height << 12) | width;
10021         }
10022
10023         if (intel_crtc->cursor_cntl != 0 &&
10024             (intel_crtc->cursor_base != base ||
10025              intel_crtc->cursor_size != size ||
10026              intel_crtc->cursor_cntl != cntl)) {
10027                 /* On these chipsets we can only modify the base/size/stride
10028                  * whilst the cursor is disabled.
10029                  */
10030                 I915_WRITE(CURCNTR(PIPE_A), 0);
10031                 POSTING_READ(CURCNTR(PIPE_A));
10032                 intel_crtc->cursor_cntl = 0;
10033         }
10034
10035         if (intel_crtc->cursor_base != base) {
10036                 I915_WRITE(CURBASE(PIPE_A), base);
10037                 intel_crtc->cursor_base = base;
10038         }
10039
10040         if (intel_crtc->cursor_size != size) {
10041                 I915_WRITE(CURSIZE, size);
10042                 intel_crtc->cursor_size = size;
10043         }
10044
10045         if (intel_crtc->cursor_cntl != cntl) {
10046                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10047                 POSTING_READ(CURCNTR(PIPE_A));
10048                 intel_crtc->cursor_cntl = cntl;
10049         }
10050 }
10051
10052 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10053                                const struct intel_plane_state *plane_state)
10054 {
10055         struct drm_device *dev = crtc->dev;
10056         struct drm_i915_private *dev_priv = dev->dev_private;
10057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10058         int pipe = intel_crtc->pipe;
10059         uint32_t cntl = 0;
10060
10061         if (plane_state && plane_state->visible) {
10062                 cntl = MCURSOR_GAMMA_ENABLE;
10063                 switch (plane_state->base.crtc_w) {
10064                         case 64:
10065                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10066                                 break;
10067                         case 128:
10068                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10069                                 break;
10070                         case 256:
10071                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10072                                 break;
10073                         default:
10074                                 MISSING_CASE(plane_state->base.crtc_w);
10075                                 return;
10076                 }
10077                 cntl |= pipe << 28; /* Connect to correct pipe */
10078
10079                 if (HAS_DDI(dev))
10080                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10081
10082                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10083                         cntl |= CURSOR_ROTATE_180;
10084         }
10085
10086         if (intel_crtc->cursor_cntl != cntl) {
10087                 I915_WRITE(CURCNTR(pipe), cntl);
10088                 POSTING_READ(CURCNTR(pipe));
10089                 intel_crtc->cursor_cntl = cntl;
10090         }
10091
10092         /* and commit changes on next vblank */
10093         I915_WRITE(CURBASE(pipe), base);
10094         POSTING_READ(CURBASE(pipe));
10095
10096         intel_crtc->cursor_base = base;
10097 }
10098
10099 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10100 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10101                                      const struct intel_plane_state *plane_state)
10102 {
10103         struct drm_device *dev = crtc->dev;
10104         struct drm_i915_private *dev_priv = dev->dev_private;
10105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10106         int pipe = intel_crtc->pipe;
10107         u32 base = intel_crtc->cursor_addr;
10108         u32 pos = 0;
10109
10110         if (plane_state) {
10111                 int x = plane_state->base.crtc_x;
10112                 int y = plane_state->base.crtc_y;
10113
10114                 if (x < 0) {
10115                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10116                         x = -x;
10117                 }
10118                 pos |= x << CURSOR_X_SHIFT;
10119
10120                 if (y < 0) {
10121                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10122                         y = -y;
10123                 }
10124                 pos |= y << CURSOR_Y_SHIFT;
10125
10126                 /* ILK+ do this automagically */
10127                 if (HAS_GMCH_DISPLAY(dev) &&
10128                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10129                         base += (plane_state->base.crtc_h *
10130                                  plane_state->base.crtc_w - 1) * 4;
10131                 }
10132         }
10133
10134         I915_WRITE(CURPOS(pipe), pos);
10135
10136         if (IS_845G(dev) || IS_I865G(dev))
10137                 i845_update_cursor(crtc, base, plane_state);
10138         else
10139                 i9xx_update_cursor(crtc, base, plane_state);
10140 }
10141
10142 static bool cursor_size_ok(struct drm_device *dev,
10143                            uint32_t width, uint32_t height)
10144 {
10145         if (width == 0 || height == 0)
10146                 return false;
10147
10148         /*
10149          * 845g/865g are special in that they are only limited by
10150          * the width of their cursors, the height is arbitrary up to
10151          * the precision of the register. Everything else requires
10152          * square cursors, limited to a few power-of-two sizes.
10153          */
10154         if (IS_845G(dev) || IS_I865G(dev)) {
10155                 if ((width & 63) != 0)
10156                         return false;
10157
10158                 if (width > (IS_845G(dev) ? 64 : 512))
10159                         return false;
10160
10161                 if (height > 1023)
10162                         return false;
10163         } else {
10164                 switch (width | height) {
10165                 case 256:
10166                 case 128:
10167                         if (IS_GEN2(dev))
10168                                 return false;
10169                 case 64:
10170                         break;
10171                 default:
10172                         return false;
10173                 }
10174         }
10175
10176         return true;
10177 }
10178
10179 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10180                                  u16 *blue, uint32_t start, uint32_t size)
10181 {
10182         int end = (start + size > 256) ? 256 : start + size, i;
10183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10184
10185         for (i = start; i < end; i++) {
10186                 intel_crtc->lut_r[i] = red[i] >> 8;
10187                 intel_crtc->lut_g[i] = green[i] >> 8;
10188                 intel_crtc->lut_b[i] = blue[i] >> 8;
10189         }
10190
10191         intel_crtc_load_lut(crtc);
10192 }
10193
10194 /* VESA 640x480x72Hz mode to set on the pipe */
10195 static struct drm_display_mode load_detect_mode = {
10196         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10197                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10198 };
10199
10200 struct drm_framebuffer *
10201 __intel_framebuffer_create(struct drm_device *dev,
10202                            struct drm_mode_fb_cmd2 *mode_cmd,
10203                            struct drm_i915_gem_object *obj)
10204 {
10205         struct intel_framebuffer *intel_fb;
10206         int ret;
10207
10208         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10209         if (!intel_fb)
10210                 return ERR_PTR(-ENOMEM);
10211
10212         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10213         if (ret)
10214                 goto err;
10215
10216         return &intel_fb->base;
10217
10218 err:
10219         kfree(intel_fb);
10220         return ERR_PTR(ret);
10221 }
10222
10223 static struct drm_framebuffer *
10224 intel_framebuffer_create(struct drm_device *dev,
10225                          struct drm_mode_fb_cmd2 *mode_cmd,
10226                          struct drm_i915_gem_object *obj)
10227 {
10228         struct drm_framebuffer *fb;
10229         int ret;
10230
10231         ret = i915_mutex_lock_interruptible(dev);
10232         if (ret)
10233                 return ERR_PTR(ret);
10234         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10235         mutex_unlock(&dev->struct_mutex);
10236
10237         return fb;
10238 }
10239
10240 static u32
10241 intel_framebuffer_pitch_for_width(int width, int bpp)
10242 {
10243         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10244         return ALIGN(pitch, 64);
10245 }
10246
10247 static u32
10248 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10249 {
10250         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10251         return PAGE_ALIGN(pitch * mode->vdisplay);
10252 }
10253
10254 static struct drm_framebuffer *
10255 intel_framebuffer_create_for_mode(struct drm_device *dev,
10256                                   struct drm_display_mode *mode,
10257                                   int depth, int bpp)
10258 {
10259         struct drm_framebuffer *fb;
10260         struct drm_i915_gem_object *obj;
10261         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10262
10263         obj = i915_gem_alloc_object(dev,
10264                                     intel_framebuffer_size_for_mode(mode, bpp));
10265         if (obj == NULL)
10266                 return ERR_PTR(-ENOMEM);
10267
10268         mode_cmd.width = mode->hdisplay;
10269         mode_cmd.height = mode->vdisplay;
10270         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10271                                                                 bpp);
10272         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10273
10274         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10275         if (IS_ERR(fb))
10276                 drm_gem_object_unreference_unlocked(&obj->base);
10277
10278         return fb;
10279 }
10280
10281 static struct drm_framebuffer *
10282 mode_fits_in_fbdev(struct drm_device *dev,
10283                    struct drm_display_mode *mode)
10284 {
10285 #ifdef CONFIG_DRM_FBDEV_EMULATION
10286         struct drm_i915_private *dev_priv = dev->dev_private;
10287         struct drm_i915_gem_object *obj;
10288         struct drm_framebuffer *fb;
10289
10290         if (!dev_priv->fbdev)
10291                 return NULL;
10292
10293         if (!dev_priv->fbdev->fb)
10294                 return NULL;
10295
10296         obj = dev_priv->fbdev->fb->obj;
10297         BUG_ON(!obj);
10298
10299         fb = &dev_priv->fbdev->fb->base;
10300         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10301                                                                fb->bits_per_pixel))
10302                 return NULL;
10303
10304         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10305                 return NULL;
10306
10307         drm_framebuffer_reference(fb);
10308         return fb;
10309 #else
10310         return NULL;
10311 #endif
10312 }
10313
10314 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10315                                            struct drm_crtc *crtc,
10316                                            struct drm_display_mode *mode,
10317                                            struct drm_framebuffer *fb,
10318                                            int x, int y)
10319 {
10320         struct drm_plane_state *plane_state;
10321         int hdisplay, vdisplay;
10322         int ret;
10323
10324         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10325         if (IS_ERR(plane_state))
10326                 return PTR_ERR(plane_state);
10327
10328         if (mode)
10329                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10330         else
10331                 hdisplay = vdisplay = 0;
10332
10333         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10334         if (ret)
10335                 return ret;
10336         drm_atomic_set_fb_for_plane(plane_state, fb);
10337         plane_state->crtc_x = 0;
10338         plane_state->crtc_y = 0;
10339         plane_state->crtc_w = hdisplay;
10340         plane_state->crtc_h = vdisplay;
10341         plane_state->src_x = x << 16;
10342         plane_state->src_y = y << 16;
10343         plane_state->src_w = hdisplay << 16;
10344         plane_state->src_h = vdisplay << 16;
10345
10346         return 0;
10347 }
10348
10349 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10350                                 struct drm_display_mode *mode,
10351                                 struct intel_load_detect_pipe *old,
10352                                 struct drm_modeset_acquire_ctx *ctx)
10353 {
10354         struct intel_crtc *intel_crtc;
10355         struct intel_encoder *intel_encoder =
10356                 intel_attached_encoder(connector);
10357         struct drm_crtc *possible_crtc;
10358         struct drm_encoder *encoder = &intel_encoder->base;
10359         struct drm_crtc *crtc = NULL;
10360         struct drm_device *dev = encoder->dev;
10361         struct drm_framebuffer *fb;
10362         struct drm_mode_config *config = &dev->mode_config;
10363         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10364         struct drm_connector_state *connector_state;
10365         struct intel_crtc_state *crtc_state;
10366         int ret, i = -1;
10367
10368         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10369                       connector->base.id, connector->name,
10370                       encoder->base.id, encoder->name);
10371
10372         old->restore_state = NULL;
10373
10374 retry:
10375         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10376         if (ret)
10377                 goto fail;
10378
10379         /*
10380          * Algorithm gets a little messy:
10381          *
10382          *   - if the connector already has an assigned crtc, use it (but make
10383          *     sure it's on first)
10384          *
10385          *   - try to find the first unused crtc that can drive this connector,
10386          *     and use that if we find one
10387          */
10388
10389         /* See if we already have a CRTC for this connector */
10390         if (connector->state->crtc) {
10391                 crtc = connector->state->crtc;
10392
10393                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10394                 if (ret)
10395                         goto fail;
10396
10397                 /* Make sure the crtc and connector are running */
10398                 goto found;
10399         }
10400
10401         /* Find an unused one (if possible) */
10402         for_each_crtc(dev, possible_crtc) {
10403                 i++;
10404                 if (!(encoder->possible_crtcs & (1 << i)))
10405                         continue;
10406
10407                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10408                 if (ret)
10409                         goto fail;
10410
10411                 if (possible_crtc->state->enable) {
10412                         drm_modeset_unlock(&possible_crtc->mutex);
10413                         continue;
10414                 }
10415
10416                 crtc = possible_crtc;
10417                 break;
10418         }
10419
10420         /*
10421          * If we didn't find an unused CRTC, don't use any.
10422          */
10423         if (!crtc) {
10424                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10425                 goto fail;
10426         }
10427
10428 found:
10429         intel_crtc = to_intel_crtc(crtc);
10430
10431         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10432         if (ret)
10433                 goto fail;
10434
10435         state = drm_atomic_state_alloc(dev);
10436         restore_state = drm_atomic_state_alloc(dev);
10437         if (!state || !restore_state) {
10438                 ret = -ENOMEM;
10439                 goto fail;
10440         }
10441
10442         state->acquire_ctx = ctx;
10443         restore_state->acquire_ctx = ctx;
10444
10445         connector_state = drm_atomic_get_connector_state(state, connector);
10446         if (IS_ERR(connector_state)) {
10447                 ret = PTR_ERR(connector_state);
10448                 goto fail;
10449         }
10450
10451         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10452         if (ret)
10453                 goto fail;
10454
10455         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10456         if (IS_ERR(crtc_state)) {
10457                 ret = PTR_ERR(crtc_state);
10458                 goto fail;
10459         }
10460
10461         crtc_state->base.active = crtc_state->base.enable = true;
10462
10463         if (!mode)
10464                 mode = &load_detect_mode;
10465
10466         /* We need a framebuffer large enough to accommodate all accesses
10467          * that the plane may generate whilst we perform load detection.
10468          * We can not rely on the fbcon either being present (we get called
10469          * during its initialisation to detect all boot displays, or it may
10470          * not even exist) or that it is large enough to satisfy the
10471          * requested mode.
10472          */
10473         fb = mode_fits_in_fbdev(dev, mode);
10474         if (fb == NULL) {
10475                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10476                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10477         } else
10478                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10479         if (IS_ERR(fb)) {
10480                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10481                 goto fail;
10482         }
10483
10484         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10485         if (ret)
10486                 goto fail;
10487
10488         drm_framebuffer_unreference(fb);
10489
10490         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10491         if (ret)
10492                 goto fail;
10493
10494         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10495         if (!ret)
10496                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10497         if (!ret)
10498                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10499         if (ret) {
10500                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10501                 goto fail;
10502         }
10503
10504         ret = drm_atomic_commit(state);
10505         if (ret) {
10506                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10507                 goto fail;
10508         }
10509
10510         old->restore_state = restore_state;
10511
10512         /* let the connector get through one full cycle before testing */
10513         intel_wait_for_vblank(dev, intel_crtc->pipe);
10514         return true;
10515
10516 fail:
10517         drm_atomic_state_free(state);
10518         drm_atomic_state_free(restore_state);
10519         restore_state = state = NULL;
10520
10521         if (ret == -EDEADLK) {
10522                 drm_modeset_backoff(ctx);
10523                 goto retry;
10524         }
10525
10526         return false;
10527 }
10528
10529 void intel_release_load_detect_pipe(struct drm_connector *connector,
10530                                     struct intel_load_detect_pipe *old,
10531                                     struct drm_modeset_acquire_ctx *ctx)
10532 {
10533         struct intel_encoder *intel_encoder =
10534                 intel_attached_encoder(connector);
10535         struct drm_encoder *encoder = &intel_encoder->base;
10536         struct drm_atomic_state *state = old->restore_state;
10537         int ret;
10538
10539         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10540                       connector->base.id, connector->name,
10541                       encoder->base.id, encoder->name);
10542
10543         if (!state)
10544                 return;
10545
10546         ret = drm_atomic_commit(state);
10547         if (ret) {
10548                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10549                 drm_atomic_state_free(state);
10550         }
10551 }
10552
10553 static int i9xx_pll_refclk(struct drm_device *dev,
10554                            const struct intel_crtc_state *pipe_config)
10555 {
10556         struct drm_i915_private *dev_priv = dev->dev_private;
10557         u32 dpll = pipe_config->dpll_hw_state.dpll;
10558
10559         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10560                 return dev_priv->vbt.lvds_ssc_freq;
10561         else if (HAS_PCH_SPLIT(dev))
10562                 return 120000;
10563         else if (!IS_GEN2(dev))
10564                 return 96000;
10565         else
10566                 return 48000;
10567 }
10568
10569 /* Returns the clock of the currently programmed mode of the given pipe. */
10570 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10571                                 struct intel_crtc_state *pipe_config)
10572 {
10573         struct drm_device *dev = crtc->base.dev;
10574         struct drm_i915_private *dev_priv = dev->dev_private;
10575         int pipe = pipe_config->cpu_transcoder;
10576         u32 dpll = pipe_config->dpll_hw_state.dpll;
10577         u32 fp;
10578         intel_clock_t clock;
10579         int port_clock;
10580         int refclk = i9xx_pll_refclk(dev, pipe_config);
10581
10582         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10583                 fp = pipe_config->dpll_hw_state.fp0;
10584         else
10585                 fp = pipe_config->dpll_hw_state.fp1;
10586
10587         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10588         if (IS_PINEVIEW(dev)) {
10589                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10590                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10591         } else {
10592                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10593                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10594         }
10595
10596         if (!IS_GEN2(dev)) {
10597                 if (IS_PINEVIEW(dev))
10598                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10599                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10600                 else
10601                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10602                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10603
10604                 switch (dpll & DPLL_MODE_MASK) {
10605                 case DPLLB_MODE_DAC_SERIAL:
10606                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10607                                 5 : 10;
10608                         break;
10609                 case DPLLB_MODE_LVDS:
10610                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10611                                 7 : 14;
10612                         break;
10613                 default:
10614                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10615                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10616                         return;
10617                 }
10618
10619                 if (IS_PINEVIEW(dev))
10620                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10621                 else
10622                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10623         } else {
10624                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10625                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10626
10627                 if (is_lvds) {
10628                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10629                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10630
10631                         if (lvds & LVDS_CLKB_POWER_UP)
10632                                 clock.p2 = 7;
10633                         else
10634                                 clock.p2 = 14;
10635                 } else {
10636                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10637                                 clock.p1 = 2;
10638                         else {
10639                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10640                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10641                         }
10642                         if (dpll & PLL_P2_DIVIDE_BY_4)
10643                                 clock.p2 = 4;
10644                         else
10645                                 clock.p2 = 2;
10646                 }
10647
10648                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10649         }
10650
10651         /*
10652          * This value includes pixel_multiplier. We will use
10653          * port_clock to compute adjusted_mode.crtc_clock in the
10654          * encoder's get_config() function.
10655          */
10656         pipe_config->port_clock = port_clock;
10657 }
10658
10659 int intel_dotclock_calculate(int link_freq,
10660                              const struct intel_link_m_n *m_n)
10661 {
10662         /*
10663          * The calculation for the data clock is:
10664          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10665          * But we want to avoid losing precison if possible, so:
10666          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10667          *
10668          * and the link clock is simpler:
10669          * link_clock = (m * link_clock) / n
10670          */
10671
10672         if (!m_n->link_n)
10673                 return 0;
10674
10675         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10676 }
10677
10678 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10679                                    struct intel_crtc_state *pipe_config)
10680 {
10681         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10682
10683         /* read out port_clock from the DPLL */
10684         i9xx_crtc_clock_get(crtc, pipe_config);
10685
10686         /*
10687          * In case there is an active pipe without active ports,
10688          * we may need some idea for the dotclock anyway.
10689          * Calculate one based on the FDI configuration.
10690          */
10691         pipe_config->base.adjusted_mode.crtc_clock =
10692                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10693                                          &pipe_config->fdi_m_n);
10694 }
10695
10696 /** Returns the currently programmed mode of the given pipe. */
10697 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10698                                              struct drm_crtc *crtc)
10699 {
10700         struct drm_i915_private *dev_priv = dev->dev_private;
10701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10703         struct drm_display_mode *mode;
10704         struct intel_crtc_state *pipe_config;
10705         int htot = I915_READ(HTOTAL(cpu_transcoder));
10706         int hsync = I915_READ(HSYNC(cpu_transcoder));
10707         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10708         int vsync = I915_READ(VSYNC(cpu_transcoder));
10709         enum pipe pipe = intel_crtc->pipe;
10710
10711         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10712         if (!mode)
10713                 return NULL;
10714
10715         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10716         if (!pipe_config) {
10717                 kfree(mode);
10718                 return NULL;
10719         }
10720
10721         /*
10722          * Construct a pipe_config sufficient for getting the clock info
10723          * back out of crtc_clock_get.
10724          *
10725          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10726          * to use a real value here instead.
10727          */
10728         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10729         pipe_config->pixel_multiplier = 1;
10730         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10731         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10732         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10733         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10734
10735         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10736         mode->hdisplay = (htot & 0xffff) + 1;
10737         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10738         mode->hsync_start = (hsync & 0xffff) + 1;
10739         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10740         mode->vdisplay = (vtot & 0xffff) + 1;
10741         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10742         mode->vsync_start = (vsync & 0xffff) + 1;
10743         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10744
10745         drm_mode_set_name(mode);
10746
10747         kfree(pipe_config);
10748
10749         return mode;
10750 }
10751
10752 void intel_mark_busy(struct drm_device *dev)
10753 {
10754         struct drm_i915_private *dev_priv = dev->dev_private;
10755
10756         if (dev_priv->mm.busy)
10757                 return;
10758
10759         intel_runtime_pm_get(dev_priv);
10760         i915_update_gfx_val(dev_priv);
10761         if (INTEL_INFO(dev)->gen >= 6)
10762                 gen6_rps_busy(dev_priv);
10763         dev_priv->mm.busy = true;
10764 }
10765
10766 void intel_mark_idle(struct drm_device *dev)
10767 {
10768         struct drm_i915_private *dev_priv = dev->dev_private;
10769
10770         if (!dev_priv->mm.busy)
10771                 return;
10772
10773         dev_priv->mm.busy = false;
10774
10775         if (INTEL_INFO(dev)->gen >= 6)
10776                 gen6_rps_idle(dev->dev_private);
10777
10778         intel_runtime_pm_put(dev_priv);
10779 }
10780
10781 static void intel_crtc_destroy(struct drm_crtc *crtc)
10782 {
10783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10784         struct drm_device *dev = crtc->dev;
10785         struct intel_unpin_work *work;
10786
10787         spin_lock_irq(&dev->event_lock);
10788         work = intel_crtc->unpin_work;
10789         intel_crtc->unpin_work = NULL;
10790         spin_unlock_irq(&dev->event_lock);
10791
10792         if (work) {
10793                 cancel_work_sync(&work->work);
10794                 kfree(work);
10795         }
10796
10797         drm_crtc_cleanup(crtc);
10798
10799         kfree(intel_crtc);
10800 }
10801
10802 static void intel_unpin_work_fn(struct work_struct *__work)
10803 {
10804         struct intel_unpin_work *work =
10805                 container_of(__work, struct intel_unpin_work, work);
10806         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10807         struct drm_device *dev = crtc->base.dev;
10808         struct drm_plane *primary = crtc->base.primary;
10809
10810         mutex_lock(&dev->struct_mutex);
10811         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10812         drm_gem_object_unreference(&work->pending_flip_obj->base);
10813
10814         if (work->flip_queued_req)
10815                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10816         mutex_unlock(&dev->struct_mutex);
10817
10818         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10819         intel_fbc_post_update(crtc);
10820         drm_framebuffer_unreference(work->old_fb);
10821
10822         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10823         atomic_dec(&crtc->unpin_work_count);
10824
10825         kfree(work);
10826 }
10827
10828 static void do_intel_finish_page_flip(struct drm_device *dev,
10829                                       struct drm_crtc *crtc)
10830 {
10831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10832         struct intel_unpin_work *work;
10833         unsigned long flags;
10834
10835         /* Ignore early vblank irqs */
10836         if (intel_crtc == NULL)
10837                 return;
10838
10839         /*
10840          * This is called both by irq handlers and the reset code (to complete
10841          * lost pageflips) so needs the full irqsave spinlocks.
10842          */
10843         spin_lock_irqsave(&dev->event_lock, flags);
10844         work = intel_crtc->unpin_work;
10845
10846         /* Ensure we don't miss a work->pending update ... */
10847         smp_rmb();
10848
10849         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10850                 spin_unlock_irqrestore(&dev->event_lock, flags);
10851                 return;
10852         }
10853
10854         page_flip_completed(intel_crtc);
10855
10856         spin_unlock_irqrestore(&dev->event_lock, flags);
10857 }
10858
10859 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10860 {
10861         struct drm_i915_private *dev_priv = dev->dev_private;
10862         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10863
10864         do_intel_finish_page_flip(dev, crtc);
10865 }
10866
10867 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10868 {
10869         struct drm_i915_private *dev_priv = dev->dev_private;
10870         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10871
10872         do_intel_finish_page_flip(dev, crtc);
10873 }
10874
10875 /* Is 'a' after or equal to 'b'? */
10876 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10877 {
10878         return !((a - b) & 0x80000000);
10879 }
10880
10881 static bool page_flip_finished(struct intel_crtc *crtc)
10882 {
10883         struct drm_device *dev = crtc->base.dev;
10884         struct drm_i915_private *dev_priv = dev->dev_private;
10885
10886         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10887             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10888                 return true;
10889
10890         /*
10891          * The relevant registers doen't exist on pre-ctg.
10892          * As the flip done interrupt doesn't trigger for mmio
10893          * flips on gmch platforms, a flip count check isn't
10894          * really needed there. But since ctg has the registers,
10895          * include it in the check anyway.
10896          */
10897         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10898                 return true;
10899
10900         /*
10901          * BDW signals flip done immediately if the plane
10902          * is disabled, even if the plane enable is already
10903          * armed to occur at the next vblank :(
10904          */
10905
10906         /*
10907          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10908          * used the same base address. In that case the mmio flip might
10909          * have completed, but the CS hasn't even executed the flip yet.
10910          *
10911          * A flip count check isn't enough as the CS might have updated
10912          * the base address just after start of vblank, but before we
10913          * managed to process the interrupt. This means we'd complete the
10914          * CS flip too soon.
10915          *
10916          * Combining both checks should get us a good enough result. It may
10917          * still happen that the CS flip has been executed, but has not
10918          * yet actually completed. But in case the base address is the same
10919          * anyway, we don't really care.
10920          */
10921         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10922                 crtc->unpin_work->gtt_offset &&
10923                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10924                                     crtc->unpin_work->flip_count);
10925 }
10926
10927 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10928 {
10929         struct drm_i915_private *dev_priv = dev->dev_private;
10930         struct intel_crtc *intel_crtc =
10931                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10932         unsigned long flags;
10933
10934
10935         /*
10936          * This is called both by irq handlers and the reset code (to complete
10937          * lost pageflips) so needs the full irqsave spinlocks.
10938          *
10939          * NB: An MMIO update of the plane base pointer will also
10940          * generate a page-flip completion irq, i.e. every modeset
10941          * is also accompanied by a spurious intel_prepare_page_flip().
10942          */
10943         spin_lock_irqsave(&dev->event_lock, flags);
10944         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10945                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10946         spin_unlock_irqrestore(&dev->event_lock, flags);
10947 }
10948
10949 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10950 {
10951         /* Ensure that the work item is consistent when activating it ... */
10952         smp_wmb();
10953         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10954         /* and that it is marked active as soon as the irq could fire. */
10955         smp_wmb();
10956 }
10957
10958 static int intel_gen2_queue_flip(struct drm_device *dev,
10959                                  struct drm_crtc *crtc,
10960                                  struct drm_framebuffer *fb,
10961                                  struct drm_i915_gem_object *obj,
10962                                  struct drm_i915_gem_request *req,
10963                                  uint32_t flags)
10964 {
10965         struct intel_engine_cs *ring = req->ring;
10966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10967         u32 flip_mask;
10968         int ret;
10969
10970         ret = intel_ring_begin(req, 6);
10971         if (ret)
10972                 return ret;
10973
10974         /* Can't queue multiple flips, so wait for the previous
10975          * one to finish before executing the next.
10976          */
10977         if (intel_crtc->plane)
10978                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10979         else
10980                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10981         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10982         intel_ring_emit(ring, MI_NOOP);
10983         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10984                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10985         intel_ring_emit(ring, fb->pitches[0]);
10986         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10987         intel_ring_emit(ring, 0); /* aux display base address, unused */
10988
10989         intel_mark_page_flip_active(intel_crtc->unpin_work);
10990         return 0;
10991 }
10992
10993 static int intel_gen3_queue_flip(struct drm_device *dev,
10994                                  struct drm_crtc *crtc,
10995                                  struct drm_framebuffer *fb,
10996                                  struct drm_i915_gem_object *obj,
10997                                  struct drm_i915_gem_request *req,
10998                                  uint32_t flags)
10999 {
11000         struct intel_engine_cs *ring = req->ring;
11001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11002         u32 flip_mask;
11003         int ret;
11004
11005         ret = intel_ring_begin(req, 6);
11006         if (ret)
11007                 return ret;
11008
11009         if (intel_crtc->plane)
11010                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11011         else
11012                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11013         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11014         intel_ring_emit(ring, MI_NOOP);
11015         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11016                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11017         intel_ring_emit(ring, fb->pitches[0]);
11018         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11019         intel_ring_emit(ring, MI_NOOP);
11020
11021         intel_mark_page_flip_active(intel_crtc->unpin_work);
11022         return 0;
11023 }
11024
11025 static int intel_gen4_queue_flip(struct drm_device *dev,
11026                                  struct drm_crtc *crtc,
11027                                  struct drm_framebuffer *fb,
11028                                  struct drm_i915_gem_object *obj,
11029                                  struct drm_i915_gem_request *req,
11030                                  uint32_t flags)
11031 {
11032         struct intel_engine_cs *ring = req->ring;
11033         struct drm_i915_private *dev_priv = dev->dev_private;
11034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11035         uint32_t pf, pipesrc;
11036         int ret;
11037
11038         ret = intel_ring_begin(req, 4);
11039         if (ret)
11040                 return ret;
11041
11042         /* i965+ uses the linear or tiled offsets from the
11043          * Display Registers (which do not change across a page-flip)
11044          * so we need only reprogram the base address.
11045          */
11046         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11047                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11048         intel_ring_emit(ring, fb->pitches[0]);
11049         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11050                         obj->tiling_mode);
11051
11052         /* XXX Enabling the panel-fitter across page-flip is so far
11053          * untested on non-native modes, so ignore it for now.
11054          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11055          */
11056         pf = 0;
11057         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11058         intel_ring_emit(ring, pf | pipesrc);
11059
11060         intel_mark_page_flip_active(intel_crtc->unpin_work);
11061         return 0;
11062 }
11063
11064 static int intel_gen6_queue_flip(struct drm_device *dev,
11065                                  struct drm_crtc *crtc,
11066                                  struct drm_framebuffer *fb,
11067                                  struct drm_i915_gem_object *obj,
11068                                  struct drm_i915_gem_request *req,
11069                                  uint32_t flags)
11070 {
11071         struct intel_engine_cs *ring = req->ring;
11072         struct drm_i915_private *dev_priv = dev->dev_private;
11073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11074         uint32_t pf, pipesrc;
11075         int ret;
11076
11077         ret = intel_ring_begin(req, 4);
11078         if (ret)
11079                 return ret;
11080
11081         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11082                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11083         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11084         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11085
11086         /* Contrary to the suggestions in the documentation,
11087          * "Enable Panel Fitter" does not seem to be required when page
11088          * flipping with a non-native mode, and worse causes a normal
11089          * modeset to fail.
11090          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11091          */
11092         pf = 0;
11093         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11094         intel_ring_emit(ring, pf | pipesrc);
11095
11096         intel_mark_page_flip_active(intel_crtc->unpin_work);
11097         return 0;
11098 }
11099
11100 static int intel_gen7_queue_flip(struct drm_device *dev,
11101                                  struct drm_crtc *crtc,
11102                                  struct drm_framebuffer *fb,
11103                                  struct drm_i915_gem_object *obj,
11104                                  struct drm_i915_gem_request *req,
11105                                  uint32_t flags)
11106 {
11107         struct intel_engine_cs *ring = req->ring;
11108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11109         uint32_t plane_bit = 0;
11110         int len, ret;
11111
11112         switch (intel_crtc->plane) {
11113         case PLANE_A:
11114                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11115                 break;
11116         case PLANE_B:
11117                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11118                 break;
11119         case PLANE_C:
11120                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11121                 break;
11122         default:
11123                 WARN_ONCE(1, "unknown plane in flip command\n");
11124                 return -ENODEV;
11125         }
11126
11127         len = 4;
11128         if (ring->id == RCS) {
11129                 len += 6;
11130                 /*
11131                  * On Gen 8, SRM is now taking an extra dword to accommodate
11132                  * 48bits addresses, and we need a NOOP for the batch size to
11133                  * stay even.
11134                  */
11135                 if (IS_GEN8(dev))
11136                         len += 2;
11137         }
11138
11139         /*
11140          * BSpec MI_DISPLAY_FLIP for IVB:
11141          * "The full packet must be contained within the same cache line."
11142          *
11143          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11144          * cacheline, if we ever start emitting more commands before
11145          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11146          * then do the cacheline alignment, and finally emit the
11147          * MI_DISPLAY_FLIP.
11148          */
11149         ret = intel_ring_cacheline_align(req);
11150         if (ret)
11151                 return ret;
11152
11153         ret = intel_ring_begin(req, len);
11154         if (ret)
11155                 return ret;
11156
11157         /* Unmask the flip-done completion message. Note that the bspec says that
11158          * we should do this for both the BCS and RCS, and that we must not unmask
11159          * more than one flip event at any time (or ensure that one flip message
11160          * can be sent by waiting for flip-done prior to queueing new flips).
11161          * Experimentation says that BCS works despite DERRMR masking all
11162          * flip-done completion events and that unmasking all planes at once
11163          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11164          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11165          */
11166         if (ring->id == RCS) {
11167                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11168                 intel_ring_emit_reg(ring, DERRMR);
11169                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11170                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11171                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11172                 if (IS_GEN8(dev))
11173                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11174                                               MI_SRM_LRM_GLOBAL_GTT);
11175                 else
11176                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11177                                               MI_SRM_LRM_GLOBAL_GTT);
11178                 intel_ring_emit_reg(ring, DERRMR);
11179                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11180                 if (IS_GEN8(dev)) {
11181                         intel_ring_emit(ring, 0);
11182                         intel_ring_emit(ring, MI_NOOP);
11183                 }
11184         }
11185
11186         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11187         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11188         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11189         intel_ring_emit(ring, (MI_NOOP));
11190
11191         intel_mark_page_flip_active(intel_crtc->unpin_work);
11192         return 0;
11193 }
11194
11195 static bool use_mmio_flip(struct intel_engine_cs *ring,
11196                           struct drm_i915_gem_object *obj)
11197 {
11198         /*
11199          * This is not being used for older platforms, because
11200          * non-availability of flip done interrupt forces us to use
11201          * CS flips. Older platforms derive flip done using some clever
11202          * tricks involving the flip_pending status bits and vblank irqs.
11203          * So using MMIO flips there would disrupt this mechanism.
11204          */
11205
11206         if (ring == NULL)
11207                 return true;
11208
11209         if (INTEL_INFO(ring->dev)->gen < 5)
11210                 return false;
11211
11212         if (i915.use_mmio_flip < 0)
11213                 return false;
11214         else if (i915.use_mmio_flip > 0)
11215                 return true;
11216         else if (i915.enable_execlists)
11217                 return true;
11218         else if (obj->base.dma_buf &&
11219                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11220                                                        false))
11221                 return true;
11222         else
11223                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11224 }
11225
11226 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11227                              unsigned int rotation,
11228                              struct intel_unpin_work *work)
11229 {
11230         struct drm_device *dev = intel_crtc->base.dev;
11231         struct drm_i915_private *dev_priv = dev->dev_private;
11232         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11233         const enum pipe pipe = intel_crtc->pipe;
11234         u32 ctl, stride, tile_height;
11235
11236         ctl = I915_READ(PLANE_CTL(pipe, 0));
11237         ctl &= ~PLANE_CTL_TILED_MASK;
11238         switch (fb->modifier[0]) {
11239         case DRM_FORMAT_MOD_NONE:
11240                 break;
11241         case I915_FORMAT_MOD_X_TILED:
11242                 ctl |= PLANE_CTL_TILED_X;
11243                 break;
11244         case I915_FORMAT_MOD_Y_TILED:
11245                 ctl |= PLANE_CTL_TILED_Y;
11246                 break;
11247         case I915_FORMAT_MOD_Yf_TILED:
11248                 ctl |= PLANE_CTL_TILED_YF;
11249                 break;
11250         default:
11251                 MISSING_CASE(fb->modifier[0]);
11252         }
11253
11254         /*
11255          * The stride is either expressed as a multiple of 64 bytes chunks for
11256          * linear buffers or in number of tiles for tiled buffers.
11257          */
11258         if (intel_rotation_90_or_270(rotation)) {
11259                 /* stride = Surface height in tiles */
11260                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11261                 stride = DIV_ROUND_UP(fb->height, tile_height);
11262         } else {
11263                 stride = fb->pitches[0] /
11264                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11265                                                   fb->pixel_format);
11266         }
11267
11268         /*
11269          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11270          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11271          */
11272         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11273         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11274
11275         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11276         POSTING_READ(PLANE_SURF(pipe, 0));
11277 }
11278
11279 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11280                              struct intel_unpin_work *work)
11281 {
11282         struct drm_device *dev = intel_crtc->base.dev;
11283         struct drm_i915_private *dev_priv = dev->dev_private;
11284         struct intel_framebuffer *intel_fb =
11285                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11286         struct drm_i915_gem_object *obj = intel_fb->obj;
11287         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11288         u32 dspcntr;
11289
11290         dspcntr = I915_READ(reg);
11291
11292         if (obj->tiling_mode != I915_TILING_NONE)
11293                 dspcntr |= DISPPLANE_TILED;
11294         else
11295                 dspcntr &= ~DISPPLANE_TILED;
11296
11297         I915_WRITE(reg, dspcntr);
11298
11299         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11300         POSTING_READ(DSPSURF(intel_crtc->plane));
11301 }
11302
11303 /*
11304  * XXX: This is the temporary way to update the plane registers until we get
11305  * around to using the usual plane update functions for MMIO flips
11306  */
11307 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11308 {
11309         struct intel_crtc *crtc = mmio_flip->crtc;
11310         struct intel_unpin_work *work;
11311
11312         spin_lock_irq(&crtc->base.dev->event_lock);
11313         work = crtc->unpin_work;
11314         spin_unlock_irq(&crtc->base.dev->event_lock);
11315         if (work == NULL)
11316                 return;
11317
11318         intel_mark_page_flip_active(work);
11319
11320         intel_pipe_update_start(crtc);
11321
11322         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11323                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11324         else
11325                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11326                 ilk_do_mmio_flip(crtc, work);
11327
11328         intel_pipe_update_end(crtc);
11329 }
11330
11331 static void intel_mmio_flip_work_func(struct work_struct *work)
11332 {
11333         struct intel_mmio_flip *mmio_flip =
11334                 container_of(work, struct intel_mmio_flip, work);
11335         struct intel_framebuffer *intel_fb =
11336                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11337         struct drm_i915_gem_object *obj = intel_fb->obj;
11338
11339         if (mmio_flip->req) {
11340                 WARN_ON(__i915_wait_request(mmio_flip->req,
11341                                             mmio_flip->crtc->reset_counter,
11342                                             false, NULL,
11343                                             &mmio_flip->i915->rps.mmioflips));
11344                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11345         }
11346
11347         /* For framebuffer backed by dmabuf, wait for fence */
11348         if (obj->base.dma_buf)
11349                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11350                                                             false, false,
11351                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11352
11353         intel_do_mmio_flip(mmio_flip);
11354         kfree(mmio_flip);
11355 }
11356
11357 static int intel_queue_mmio_flip(struct drm_device *dev,
11358                                  struct drm_crtc *crtc,
11359                                  struct drm_i915_gem_object *obj)
11360 {
11361         struct intel_mmio_flip *mmio_flip;
11362
11363         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11364         if (mmio_flip == NULL)
11365                 return -ENOMEM;
11366
11367         mmio_flip->i915 = to_i915(dev);
11368         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11369         mmio_flip->crtc = to_intel_crtc(crtc);
11370         mmio_flip->rotation = crtc->primary->state->rotation;
11371
11372         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11373         schedule_work(&mmio_flip->work);
11374
11375         return 0;
11376 }
11377
11378 static int intel_default_queue_flip(struct drm_device *dev,
11379                                     struct drm_crtc *crtc,
11380                                     struct drm_framebuffer *fb,
11381                                     struct drm_i915_gem_object *obj,
11382                                     struct drm_i915_gem_request *req,
11383                                     uint32_t flags)
11384 {
11385         return -ENODEV;
11386 }
11387
11388 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11389                                          struct drm_crtc *crtc)
11390 {
11391         struct drm_i915_private *dev_priv = dev->dev_private;
11392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11393         struct intel_unpin_work *work = intel_crtc->unpin_work;
11394         u32 addr;
11395
11396         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11397                 return true;
11398
11399         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11400                 return false;
11401
11402         if (!work->enable_stall_check)
11403                 return false;
11404
11405         if (work->flip_ready_vblank == 0) {
11406                 if (work->flip_queued_req &&
11407                     !i915_gem_request_completed(work->flip_queued_req, true))
11408                         return false;
11409
11410                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11411         }
11412
11413         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11414                 return false;
11415
11416         /* Potential stall - if we see that the flip has happened,
11417          * assume a missed interrupt. */
11418         if (INTEL_INFO(dev)->gen >= 4)
11419                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11420         else
11421                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11422
11423         /* There is a potential issue here with a false positive after a flip
11424          * to the same address. We could address this by checking for a
11425          * non-incrementing frame counter.
11426          */
11427         return addr == work->gtt_offset;
11428 }
11429
11430 void intel_check_page_flip(struct drm_device *dev, int pipe)
11431 {
11432         struct drm_i915_private *dev_priv = dev->dev_private;
11433         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11435         struct intel_unpin_work *work;
11436
11437         WARN_ON(!in_interrupt());
11438
11439         if (crtc == NULL)
11440                 return;
11441
11442         spin_lock(&dev->event_lock);
11443         work = intel_crtc->unpin_work;
11444         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11445                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11446                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11447                 page_flip_completed(intel_crtc);
11448                 work = NULL;
11449         }
11450         if (work != NULL &&
11451             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11452                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11453         spin_unlock(&dev->event_lock);
11454 }
11455
11456 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11457                                 struct drm_framebuffer *fb,
11458                                 struct drm_pending_vblank_event *event,
11459                                 uint32_t page_flip_flags)
11460 {
11461         struct drm_device *dev = crtc->dev;
11462         struct drm_i915_private *dev_priv = dev->dev_private;
11463         struct drm_framebuffer *old_fb = crtc->primary->fb;
11464         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11466         struct drm_plane *primary = crtc->primary;
11467         enum pipe pipe = intel_crtc->pipe;
11468         struct intel_unpin_work *work;
11469         struct intel_engine_cs *ring;
11470         bool mmio_flip;
11471         struct drm_i915_gem_request *request = NULL;
11472         int ret;
11473
11474         /*
11475          * drm_mode_page_flip_ioctl() should already catch this, but double
11476          * check to be safe.  In the future we may enable pageflipping from
11477          * a disabled primary plane.
11478          */
11479         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11480                 return -EBUSY;
11481
11482         /* Can't change pixel format via MI display flips. */
11483         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11484                 return -EINVAL;
11485
11486         /*
11487          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11488          * Note that pitch changes could also affect these register.
11489          */
11490         if (INTEL_INFO(dev)->gen > 3 &&
11491             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11492              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11493                 return -EINVAL;
11494
11495         if (i915_terminally_wedged(&dev_priv->gpu_error))
11496                 goto out_hang;
11497
11498         work = kzalloc(sizeof(*work), GFP_KERNEL);
11499         if (work == NULL)
11500                 return -ENOMEM;
11501
11502         work->event = event;
11503         work->crtc = crtc;
11504         work->old_fb = old_fb;
11505         INIT_WORK(&work->work, intel_unpin_work_fn);
11506
11507         ret = drm_crtc_vblank_get(crtc);
11508         if (ret)
11509                 goto free_work;
11510
11511         /* We borrow the event spin lock for protecting unpin_work */
11512         spin_lock_irq(&dev->event_lock);
11513         if (intel_crtc->unpin_work) {
11514                 /* Before declaring the flip queue wedged, check if
11515                  * the hardware completed the operation behind our backs.
11516                  */
11517                 if (__intel_pageflip_stall_check(dev, crtc)) {
11518                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11519                         page_flip_completed(intel_crtc);
11520                 } else {
11521                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11522                         spin_unlock_irq(&dev->event_lock);
11523
11524                         drm_crtc_vblank_put(crtc);
11525                         kfree(work);
11526                         return -EBUSY;
11527                 }
11528         }
11529         intel_crtc->unpin_work = work;
11530         spin_unlock_irq(&dev->event_lock);
11531
11532         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11533                 flush_workqueue(dev_priv->wq);
11534
11535         /* Reference the objects for the scheduled work. */
11536         drm_framebuffer_reference(work->old_fb);
11537         drm_gem_object_reference(&obj->base);
11538
11539         crtc->primary->fb = fb;
11540         update_state_fb(crtc->primary);
11541         intel_fbc_pre_update(intel_crtc);
11542
11543         work->pending_flip_obj = obj;
11544
11545         ret = i915_mutex_lock_interruptible(dev);
11546         if (ret)
11547                 goto cleanup;
11548
11549         atomic_inc(&intel_crtc->unpin_work_count);
11550         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11551
11552         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11553                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11554
11555         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11556                 ring = &dev_priv->ring[BCS];
11557                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11558                         /* vlv: DISPLAY_FLIP fails to change tiling */
11559                         ring = NULL;
11560         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11561                 ring = &dev_priv->ring[BCS];
11562         } else if (INTEL_INFO(dev)->gen >= 7) {
11563                 ring = i915_gem_request_get_ring(obj->last_write_req);
11564                 if (ring == NULL || ring->id != RCS)
11565                         ring = &dev_priv->ring[BCS];
11566         } else {
11567                 ring = &dev_priv->ring[RCS];
11568         }
11569
11570         mmio_flip = use_mmio_flip(ring, obj);
11571
11572         /* When using CS flips, we want to emit semaphores between rings.
11573          * However, when using mmio flips we will create a task to do the
11574          * synchronisation, so all we want here is to pin the framebuffer
11575          * into the display plane and skip any waits.
11576          */
11577         if (!mmio_flip) {
11578                 ret = i915_gem_object_sync(obj, ring, &request);
11579                 if (ret)
11580                         goto cleanup_pending;
11581         }
11582
11583         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11584         if (ret)
11585                 goto cleanup_pending;
11586
11587         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11588                                                   obj, 0);
11589         work->gtt_offset += intel_crtc->dspaddr_offset;
11590
11591         if (mmio_flip) {
11592                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11593                 if (ret)
11594                         goto cleanup_unpin;
11595
11596                 i915_gem_request_assign(&work->flip_queued_req,
11597                                         obj->last_write_req);
11598         } else {
11599                 if (!request) {
11600                         request = i915_gem_request_alloc(ring, NULL);
11601                         if (IS_ERR(request)) {
11602                                 ret = PTR_ERR(request);
11603                                 goto cleanup_unpin;
11604                         }
11605                 }
11606
11607                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11608                                                    page_flip_flags);
11609                 if (ret)
11610                         goto cleanup_unpin;
11611
11612                 i915_gem_request_assign(&work->flip_queued_req, request);
11613         }
11614
11615         if (request)
11616                 i915_add_request_no_flush(request);
11617
11618         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11619         work->enable_stall_check = true;
11620
11621         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11622                           to_intel_plane(primary)->frontbuffer_bit);
11623         mutex_unlock(&dev->struct_mutex);
11624
11625         intel_frontbuffer_flip_prepare(dev,
11626                                        to_intel_plane(primary)->frontbuffer_bit);
11627
11628         trace_i915_flip_request(intel_crtc->plane, obj);
11629
11630         return 0;
11631
11632 cleanup_unpin:
11633         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11634 cleanup_pending:
11635         if (!IS_ERR_OR_NULL(request))
11636                 i915_gem_request_cancel(request);
11637         atomic_dec(&intel_crtc->unpin_work_count);
11638         mutex_unlock(&dev->struct_mutex);
11639 cleanup:
11640         crtc->primary->fb = old_fb;
11641         update_state_fb(crtc->primary);
11642
11643         drm_gem_object_unreference_unlocked(&obj->base);
11644         drm_framebuffer_unreference(work->old_fb);
11645
11646         spin_lock_irq(&dev->event_lock);
11647         intel_crtc->unpin_work = NULL;
11648         spin_unlock_irq(&dev->event_lock);
11649
11650         drm_crtc_vblank_put(crtc);
11651 free_work:
11652         kfree(work);
11653
11654         if (ret == -EIO) {
11655                 struct drm_atomic_state *state;
11656                 struct drm_plane_state *plane_state;
11657
11658 out_hang:
11659                 state = drm_atomic_state_alloc(dev);
11660                 if (!state)
11661                         return -ENOMEM;
11662                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11663
11664 retry:
11665                 plane_state = drm_atomic_get_plane_state(state, primary);
11666                 ret = PTR_ERR_OR_ZERO(plane_state);
11667                 if (!ret) {
11668                         drm_atomic_set_fb_for_plane(plane_state, fb);
11669
11670                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11671                         if (!ret)
11672                                 ret = drm_atomic_commit(state);
11673                 }
11674
11675                 if (ret == -EDEADLK) {
11676                         drm_modeset_backoff(state->acquire_ctx);
11677                         drm_atomic_state_clear(state);
11678                         goto retry;
11679                 }
11680
11681                 if (ret)
11682                         drm_atomic_state_free(state);
11683
11684                 if (ret == 0 && event) {
11685                         spin_lock_irq(&dev->event_lock);
11686                         drm_send_vblank_event(dev, pipe, event);
11687                         spin_unlock_irq(&dev->event_lock);
11688                 }
11689         }
11690         return ret;
11691 }
11692
11693
11694 /**
11695  * intel_wm_need_update - Check whether watermarks need updating
11696  * @plane: drm plane
11697  * @state: new plane state
11698  *
11699  * Check current plane state versus the new one to determine whether
11700  * watermarks need to be recalculated.
11701  *
11702  * Returns true or false.
11703  */
11704 static bool intel_wm_need_update(struct drm_plane *plane,
11705                                  struct drm_plane_state *state)
11706 {
11707         struct intel_plane_state *new = to_intel_plane_state(state);
11708         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11709
11710         /* Update watermarks on tiling or size changes. */
11711         if (new->visible != cur->visible)
11712                 return true;
11713
11714         if (!cur->base.fb || !new->base.fb)
11715                 return false;
11716
11717         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11718             cur->base.rotation != new->base.rotation ||
11719             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11720             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11721             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11722             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11723                 return true;
11724
11725         return false;
11726 }
11727
11728 static bool needs_scaling(struct intel_plane_state *state)
11729 {
11730         int src_w = drm_rect_width(&state->src) >> 16;
11731         int src_h = drm_rect_height(&state->src) >> 16;
11732         int dst_w = drm_rect_width(&state->dst);
11733         int dst_h = drm_rect_height(&state->dst);
11734
11735         return (src_w != dst_w || src_h != dst_h);
11736 }
11737
11738 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11739                                     struct drm_plane_state *plane_state)
11740 {
11741         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11742         struct drm_crtc *crtc = crtc_state->crtc;
11743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11744         struct drm_plane *plane = plane_state->plane;
11745         struct drm_device *dev = crtc->dev;
11746         struct drm_i915_private *dev_priv = to_i915(dev);
11747         struct intel_plane_state *old_plane_state =
11748                 to_intel_plane_state(plane->state);
11749         int idx = intel_crtc->base.base.id, ret;
11750         bool mode_changed = needs_modeset(crtc_state);
11751         bool was_crtc_enabled = crtc->state->active;
11752         bool is_crtc_enabled = crtc_state->active;
11753         bool turn_off, turn_on, visible, was_visible;
11754         struct drm_framebuffer *fb = plane_state->fb;
11755
11756         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11757             plane->type != DRM_PLANE_TYPE_CURSOR) {
11758                 ret = skl_update_scaler_plane(
11759                         to_intel_crtc_state(crtc_state),
11760                         to_intel_plane_state(plane_state));
11761                 if (ret)
11762                         return ret;
11763         }
11764
11765         was_visible = old_plane_state->visible;
11766         visible = to_intel_plane_state(plane_state)->visible;
11767
11768         if (!was_crtc_enabled && WARN_ON(was_visible))
11769                 was_visible = false;
11770
11771         /*
11772          * Visibility is calculated as if the crtc was on, but
11773          * after scaler setup everything depends on it being off
11774          * when the crtc isn't active.
11775          */
11776         if (!is_crtc_enabled)
11777                 to_intel_plane_state(plane_state)->visible = visible = false;
11778
11779         if (!was_visible && !visible)
11780                 return 0;
11781
11782         if (fb != old_plane_state->base.fb)
11783                 pipe_config->fb_changed = true;
11784
11785         turn_off = was_visible && (!visible || mode_changed);
11786         turn_on = visible && (!was_visible || mode_changed);
11787
11788         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11789                          plane->base.id, fb ? fb->base.id : -1);
11790
11791         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11792                          plane->base.id, was_visible, visible,
11793                          turn_off, turn_on, mode_changed);
11794
11795         if (turn_on) {
11796                 pipe_config->update_wm_pre = true;
11797
11798                 /* must disable cxsr around plane enable/disable */
11799                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11800                         pipe_config->disable_cxsr = true;
11801         } else if (turn_off) {
11802                 pipe_config->update_wm_post = true;
11803
11804                 /* must disable cxsr around plane enable/disable */
11805                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11806                         pipe_config->disable_cxsr = true;
11807         } else if (intel_wm_need_update(plane, plane_state)) {
11808                 /* FIXME bollocks */
11809                 pipe_config->update_wm_pre = true;
11810                 pipe_config->update_wm_post = true;
11811         }
11812
11813         /* Pre-gen9 platforms need two-step watermark updates */
11814         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11815             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11816                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11817
11818         if (visible || was_visible)
11819                 intel_crtc->atomic.fb_bits |=
11820                         to_intel_plane(plane)->frontbuffer_bit;
11821
11822         switch (plane->type) {
11823         case DRM_PLANE_TYPE_PRIMARY:
11824                 intel_crtc->atomic.post_enable_primary = turn_on;
11825                 intel_crtc->atomic.update_fbc = true;
11826
11827                 break;
11828         case DRM_PLANE_TYPE_CURSOR:
11829                 break;
11830         case DRM_PLANE_TYPE_OVERLAY:
11831                 /*
11832                  * WaCxSRDisabledForSpriteScaling:ivb
11833                  *
11834                  * cstate->update_wm was already set above, so this flag will
11835                  * take effect when we commit and program watermarks.
11836                  */
11837                 if (IS_IVYBRIDGE(dev) &&
11838                     needs_scaling(to_intel_plane_state(plane_state)) &&
11839                     !needs_scaling(old_plane_state))
11840                         pipe_config->disable_lp_wm = true;
11841
11842                 break;
11843         }
11844         return 0;
11845 }
11846
11847 static bool encoders_cloneable(const struct intel_encoder *a,
11848                                const struct intel_encoder *b)
11849 {
11850         /* masks could be asymmetric, so check both ways */
11851         return a == b || (a->cloneable & (1 << b->type) &&
11852                           b->cloneable & (1 << a->type));
11853 }
11854
11855 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11856                                          struct intel_crtc *crtc,
11857                                          struct intel_encoder *encoder)
11858 {
11859         struct intel_encoder *source_encoder;
11860         struct drm_connector *connector;
11861         struct drm_connector_state *connector_state;
11862         int i;
11863
11864         for_each_connector_in_state(state, connector, connector_state, i) {
11865                 if (connector_state->crtc != &crtc->base)
11866                         continue;
11867
11868                 source_encoder =
11869                         to_intel_encoder(connector_state->best_encoder);
11870                 if (!encoders_cloneable(encoder, source_encoder))
11871                         return false;
11872         }
11873
11874         return true;
11875 }
11876
11877 static bool check_encoder_cloning(struct drm_atomic_state *state,
11878                                   struct intel_crtc *crtc)
11879 {
11880         struct intel_encoder *encoder;
11881         struct drm_connector *connector;
11882         struct drm_connector_state *connector_state;
11883         int i;
11884
11885         for_each_connector_in_state(state, connector, connector_state, i) {
11886                 if (connector_state->crtc != &crtc->base)
11887                         continue;
11888
11889                 encoder = to_intel_encoder(connector_state->best_encoder);
11890                 if (!check_single_encoder_cloning(state, crtc, encoder))
11891                         return false;
11892         }
11893
11894         return true;
11895 }
11896
11897 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11898                                    struct drm_crtc_state *crtc_state)
11899 {
11900         struct drm_device *dev = crtc->dev;
11901         struct drm_i915_private *dev_priv = dev->dev_private;
11902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11903         struct intel_crtc_state *pipe_config =
11904                 to_intel_crtc_state(crtc_state);
11905         struct drm_atomic_state *state = crtc_state->state;
11906         int ret;
11907         bool mode_changed = needs_modeset(crtc_state);
11908
11909         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11910                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11911                 return -EINVAL;
11912         }
11913
11914         if (mode_changed && !crtc_state->active)
11915                 pipe_config->update_wm_post = true;
11916
11917         if (mode_changed && crtc_state->enable &&
11918             dev_priv->display.crtc_compute_clock &&
11919             !WARN_ON(pipe_config->shared_dpll)) {
11920                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11921                                                            pipe_config);
11922                 if (ret)
11923                         return ret;
11924         }
11925
11926         ret = 0;
11927         if (dev_priv->display.compute_pipe_wm) {
11928                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11929                 if (ret) {
11930                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11931                         return ret;
11932                 }
11933         }
11934
11935         if (dev_priv->display.compute_intermediate_wm &&
11936             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11937                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11938                         return 0;
11939
11940                 /*
11941                  * Calculate 'intermediate' watermarks that satisfy both the
11942                  * old state and the new state.  We can program these
11943                  * immediately.
11944                  */
11945                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11946                                                                 intel_crtc,
11947                                                                 pipe_config);
11948                 if (ret) {
11949                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11950                         return ret;
11951                 }
11952         }
11953
11954         if (INTEL_INFO(dev)->gen >= 9) {
11955                 if (mode_changed)
11956                         ret = skl_update_scaler_crtc(pipe_config);
11957
11958                 if (!ret)
11959                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11960                                                          pipe_config);
11961         }
11962
11963         return ret;
11964 }
11965
11966 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11967         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11968         .load_lut = intel_crtc_load_lut,
11969         .atomic_begin = intel_begin_crtc_commit,
11970         .atomic_flush = intel_finish_crtc_commit,
11971         .atomic_check = intel_crtc_atomic_check,
11972 };
11973
11974 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11975 {
11976         struct intel_connector *connector;
11977
11978         for_each_intel_connector(dev, connector) {
11979                 if (connector->base.encoder) {
11980                         connector->base.state->best_encoder =
11981                                 connector->base.encoder;
11982                         connector->base.state->crtc =
11983                                 connector->base.encoder->crtc;
11984                 } else {
11985                         connector->base.state->best_encoder = NULL;
11986                         connector->base.state->crtc = NULL;
11987                 }
11988         }
11989 }
11990
11991 static void
11992 connected_sink_compute_bpp(struct intel_connector *connector,
11993                            struct intel_crtc_state *pipe_config)
11994 {
11995         int bpp = pipe_config->pipe_bpp;
11996
11997         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11998                 connector->base.base.id,
11999                 connector->base.name);
12000
12001         /* Don't use an invalid EDID bpc value */
12002         if (connector->base.display_info.bpc &&
12003             connector->base.display_info.bpc * 3 < bpp) {
12004                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12005                               bpp, connector->base.display_info.bpc*3);
12006                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12007         }
12008
12009         /* Clamp bpp to default limit on screens without EDID 1.4 */
12010         if (connector->base.display_info.bpc == 0) {
12011                 int type = connector->base.connector_type;
12012                 int clamp_bpp = 24;
12013
12014                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12015                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12016                     type == DRM_MODE_CONNECTOR_eDP)
12017                         clamp_bpp = 18;
12018
12019                 if (bpp > clamp_bpp) {
12020                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12021                                       bpp, clamp_bpp);
12022                         pipe_config->pipe_bpp = clamp_bpp;
12023                 }
12024         }
12025 }
12026
12027 static int
12028 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12029                           struct intel_crtc_state *pipe_config)
12030 {
12031         struct drm_device *dev = crtc->base.dev;
12032         struct drm_atomic_state *state;
12033         struct drm_connector *connector;
12034         struct drm_connector_state *connector_state;
12035         int bpp, i;
12036
12037         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12038                 bpp = 10*3;
12039         else if (INTEL_INFO(dev)->gen >= 5)
12040                 bpp = 12*3;
12041         else
12042                 bpp = 8*3;
12043
12044
12045         pipe_config->pipe_bpp = bpp;
12046
12047         state = pipe_config->base.state;
12048
12049         /* Clamp display bpp to EDID value */
12050         for_each_connector_in_state(state, connector, connector_state, i) {
12051                 if (connector_state->crtc != &crtc->base)
12052                         continue;
12053
12054                 connected_sink_compute_bpp(to_intel_connector(connector),
12055                                            pipe_config);
12056         }
12057
12058         return bpp;
12059 }
12060
12061 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12062 {
12063         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12064                         "type: 0x%x flags: 0x%x\n",
12065                 mode->crtc_clock,
12066                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12067                 mode->crtc_hsync_end, mode->crtc_htotal,
12068                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12069                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12070 }
12071
12072 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12073                                    struct intel_crtc_state *pipe_config,
12074                                    const char *context)
12075 {
12076         struct drm_device *dev = crtc->base.dev;
12077         struct drm_plane *plane;
12078         struct intel_plane *intel_plane;
12079         struct intel_plane_state *state;
12080         struct drm_framebuffer *fb;
12081
12082         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12083                       context, pipe_config, pipe_name(crtc->pipe));
12084
12085         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12086         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12087                       pipe_config->pipe_bpp, pipe_config->dither);
12088         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12089                       pipe_config->has_pch_encoder,
12090                       pipe_config->fdi_lanes,
12091                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12092                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12093                       pipe_config->fdi_m_n.tu);
12094         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12095                       pipe_config->has_dp_encoder,
12096                       pipe_config->lane_count,
12097                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12098                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12099                       pipe_config->dp_m_n.tu);
12100
12101         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12102                       pipe_config->has_dp_encoder,
12103                       pipe_config->lane_count,
12104                       pipe_config->dp_m2_n2.gmch_m,
12105                       pipe_config->dp_m2_n2.gmch_n,
12106                       pipe_config->dp_m2_n2.link_m,
12107                       pipe_config->dp_m2_n2.link_n,
12108                       pipe_config->dp_m2_n2.tu);
12109
12110         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12111                       pipe_config->has_audio,
12112                       pipe_config->has_infoframe);
12113
12114         DRM_DEBUG_KMS("requested mode:\n");
12115         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12116         DRM_DEBUG_KMS("adjusted mode:\n");
12117         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12118         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12119         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12120         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12121                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12122         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12123                       crtc->num_scalers,
12124                       pipe_config->scaler_state.scaler_users,
12125                       pipe_config->scaler_state.scaler_id);
12126         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12127                       pipe_config->gmch_pfit.control,
12128                       pipe_config->gmch_pfit.pgm_ratios,
12129                       pipe_config->gmch_pfit.lvds_border_bits);
12130         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12131                       pipe_config->pch_pfit.pos,
12132                       pipe_config->pch_pfit.size,
12133                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12134         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12135         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12136
12137         if (IS_BROXTON(dev)) {
12138                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12139                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12140                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12141                               pipe_config->ddi_pll_sel,
12142                               pipe_config->dpll_hw_state.ebb0,
12143                               pipe_config->dpll_hw_state.ebb4,
12144                               pipe_config->dpll_hw_state.pll0,
12145                               pipe_config->dpll_hw_state.pll1,
12146                               pipe_config->dpll_hw_state.pll2,
12147                               pipe_config->dpll_hw_state.pll3,
12148                               pipe_config->dpll_hw_state.pll6,
12149                               pipe_config->dpll_hw_state.pll8,
12150                               pipe_config->dpll_hw_state.pll9,
12151                               pipe_config->dpll_hw_state.pll10,
12152                               pipe_config->dpll_hw_state.pcsdw12);
12153         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12154                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12155                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12156                               pipe_config->ddi_pll_sel,
12157                               pipe_config->dpll_hw_state.ctrl1,
12158                               pipe_config->dpll_hw_state.cfgcr1,
12159                               pipe_config->dpll_hw_state.cfgcr2);
12160         } else if (HAS_DDI(dev)) {
12161                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12162                               pipe_config->ddi_pll_sel,
12163                               pipe_config->dpll_hw_state.wrpll,
12164                               pipe_config->dpll_hw_state.spll);
12165         } else {
12166                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12167                               "fp0: 0x%x, fp1: 0x%x\n",
12168                               pipe_config->dpll_hw_state.dpll,
12169                               pipe_config->dpll_hw_state.dpll_md,
12170                               pipe_config->dpll_hw_state.fp0,
12171                               pipe_config->dpll_hw_state.fp1);
12172         }
12173
12174         DRM_DEBUG_KMS("planes on this crtc\n");
12175         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12176                 intel_plane = to_intel_plane(plane);
12177                 if (intel_plane->pipe != crtc->pipe)
12178                         continue;
12179
12180                 state = to_intel_plane_state(plane->state);
12181                 fb = state->base.fb;
12182                 if (!fb) {
12183                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12184                                 "disabled, scaler_id = %d\n",
12185                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12186                                 plane->base.id, intel_plane->pipe,
12187                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12188                                 drm_plane_index(plane), state->scaler_id);
12189                         continue;
12190                 }
12191
12192                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12193                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12194                         plane->base.id, intel_plane->pipe,
12195                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12196                         drm_plane_index(plane));
12197                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12198                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12199                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12200                         state->scaler_id,
12201                         state->src.x1 >> 16, state->src.y1 >> 16,
12202                         drm_rect_width(&state->src) >> 16,
12203                         drm_rect_height(&state->src) >> 16,
12204                         state->dst.x1, state->dst.y1,
12205                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12206         }
12207 }
12208
12209 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12210 {
12211         struct drm_device *dev = state->dev;
12212         struct drm_connector *connector;
12213         unsigned int used_ports = 0;
12214
12215         /*
12216          * Walk the connector list instead of the encoder
12217          * list to detect the problem on ddi platforms
12218          * where there's just one encoder per digital port.
12219          */
12220         drm_for_each_connector(connector, dev) {
12221                 struct drm_connector_state *connector_state;
12222                 struct intel_encoder *encoder;
12223
12224                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12225                 if (!connector_state)
12226                         connector_state = connector->state;
12227
12228                 if (!connector_state->best_encoder)
12229                         continue;
12230
12231                 encoder = to_intel_encoder(connector_state->best_encoder);
12232
12233                 WARN_ON(!connector_state->crtc);
12234
12235                 switch (encoder->type) {
12236                         unsigned int port_mask;
12237                 case INTEL_OUTPUT_UNKNOWN:
12238                         if (WARN_ON(!HAS_DDI(dev)))
12239                                 break;
12240                 case INTEL_OUTPUT_DISPLAYPORT:
12241                 case INTEL_OUTPUT_HDMI:
12242                 case INTEL_OUTPUT_EDP:
12243                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12244
12245                         /* the same port mustn't appear more than once */
12246                         if (used_ports & port_mask)
12247                                 return false;
12248
12249                         used_ports |= port_mask;
12250                 default:
12251                         break;
12252                 }
12253         }
12254
12255         return true;
12256 }
12257
12258 static void
12259 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12260 {
12261         struct drm_crtc_state tmp_state;
12262         struct intel_crtc_scaler_state scaler_state;
12263         struct intel_dpll_hw_state dpll_hw_state;
12264         struct intel_shared_dpll *shared_dpll;
12265         uint32_t ddi_pll_sel;
12266         bool force_thru;
12267
12268         /* FIXME: before the switch to atomic started, a new pipe_config was
12269          * kzalloc'd. Code that depends on any field being zero should be
12270          * fixed, so that the crtc_state can be safely duplicated. For now,
12271          * only fields that are know to not cause problems are preserved. */
12272
12273         tmp_state = crtc_state->base;
12274         scaler_state = crtc_state->scaler_state;
12275         shared_dpll = crtc_state->shared_dpll;
12276         dpll_hw_state = crtc_state->dpll_hw_state;
12277         ddi_pll_sel = crtc_state->ddi_pll_sel;
12278         force_thru = crtc_state->pch_pfit.force_thru;
12279
12280         memset(crtc_state, 0, sizeof *crtc_state);
12281
12282         crtc_state->base = tmp_state;
12283         crtc_state->scaler_state = scaler_state;
12284         crtc_state->shared_dpll = shared_dpll;
12285         crtc_state->dpll_hw_state = dpll_hw_state;
12286         crtc_state->ddi_pll_sel = ddi_pll_sel;
12287         crtc_state->pch_pfit.force_thru = force_thru;
12288 }
12289
12290 static int
12291 intel_modeset_pipe_config(struct drm_crtc *crtc,
12292                           struct intel_crtc_state *pipe_config)
12293 {
12294         struct drm_atomic_state *state = pipe_config->base.state;
12295         struct intel_encoder *encoder;
12296         struct drm_connector *connector;
12297         struct drm_connector_state *connector_state;
12298         int base_bpp, ret = -EINVAL;
12299         int i;
12300         bool retry = true;
12301
12302         clear_intel_crtc_state(pipe_config);
12303
12304         pipe_config->cpu_transcoder =
12305                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12306
12307         /*
12308          * Sanitize sync polarity flags based on requested ones. If neither
12309          * positive or negative polarity is requested, treat this as meaning
12310          * negative polarity.
12311          */
12312         if (!(pipe_config->base.adjusted_mode.flags &
12313               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12314                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12315
12316         if (!(pipe_config->base.adjusted_mode.flags &
12317               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12318                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12319
12320         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12321                                              pipe_config);
12322         if (base_bpp < 0)
12323                 goto fail;
12324
12325         /*
12326          * Determine the real pipe dimensions. Note that stereo modes can
12327          * increase the actual pipe size due to the frame doubling and
12328          * insertion of additional space for blanks between the frame. This
12329          * is stored in the crtc timings. We use the requested mode to do this
12330          * computation to clearly distinguish it from the adjusted mode, which
12331          * can be changed by the connectors in the below retry loop.
12332          */
12333         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12334                                &pipe_config->pipe_src_w,
12335                                &pipe_config->pipe_src_h);
12336
12337 encoder_retry:
12338         /* Ensure the port clock defaults are reset when retrying. */
12339         pipe_config->port_clock = 0;
12340         pipe_config->pixel_multiplier = 1;
12341
12342         /* Fill in default crtc timings, allow encoders to overwrite them. */
12343         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12344                               CRTC_STEREO_DOUBLE);
12345
12346         /* Pass our mode to the connectors and the CRTC to give them a chance to
12347          * adjust it according to limitations or connector properties, and also
12348          * a chance to reject the mode entirely.
12349          */
12350         for_each_connector_in_state(state, connector, connector_state, i) {
12351                 if (connector_state->crtc != crtc)
12352                         continue;
12353
12354                 encoder = to_intel_encoder(connector_state->best_encoder);
12355
12356                 if (!(encoder->compute_config(encoder, pipe_config))) {
12357                         DRM_DEBUG_KMS("Encoder config failure\n");
12358                         goto fail;
12359                 }
12360         }
12361
12362         /* Set default port clock if not overwritten by the encoder. Needs to be
12363          * done afterwards in case the encoder adjusts the mode. */
12364         if (!pipe_config->port_clock)
12365                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12366                         * pipe_config->pixel_multiplier;
12367
12368         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12369         if (ret < 0) {
12370                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12371                 goto fail;
12372         }
12373
12374         if (ret == RETRY) {
12375                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12376                         ret = -EINVAL;
12377                         goto fail;
12378                 }
12379
12380                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12381                 retry = false;
12382                 goto encoder_retry;
12383         }
12384
12385         /* Dithering seems to not pass-through bits correctly when it should, so
12386          * only enable it on 6bpc panels. */
12387         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12388         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12389                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12390
12391 fail:
12392         return ret;
12393 }
12394
12395 static void
12396 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12397 {
12398         struct drm_crtc *crtc;
12399         struct drm_crtc_state *crtc_state;
12400         int i;
12401
12402         /* Double check state. */
12403         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12404                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12405
12406                 /* Update hwmode for vblank functions */
12407                 if (crtc->state->active)
12408                         crtc->hwmode = crtc->state->adjusted_mode;
12409                 else
12410                         crtc->hwmode.crtc_clock = 0;
12411
12412                 /*
12413                  * Update legacy state to satisfy fbc code. This can
12414                  * be removed when fbc uses the atomic state.
12415                  */
12416                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12417                         struct drm_plane_state *plane_state = crtc->primary->state;
12418
12419                         crtc->primary->fb = plane_state->fb;
12420                         crtc->x = plane_state->src_x >> 16;
12421                         crtc->y = plane_state->src_y >> 16;
12422                 }
12423         }
12424 }
12425
12426 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12427 {
12428         int diff;
12429
12430         if (clock1 == clock2)
12431                 return true;
12432
12433         if (!clock1 || !clock2)
12434                 return false;
12435
12436         diff = abs(clock1 - clock2);
12437
12438         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12439                 return true;
12440
12441         return false;
12442 }
12443
12444 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12445         list_for_each_entry((intel_crtc), \
12446                             &(dev)->mode_config.crtc_list, \
12447                             base.head) \
12448                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12449
12450 static bool
12451 intel_compare_m_n(unsigned int m, unsigned int n,
12452                   unsigned int m2, unsigned int n2,
12453                   bool exact)
12454 {
12455         if (m == m2 && n == n2)
12456                 return true;
12457
12458         if (exact || !m || !n || !m2 || !n2)
12459                 return false;
12460
12461         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12462
12463         if (n > n2) {
12464                 while (n > n2) {
12465                         m2 <<= 1;
12466                         n2 <<= 1;
12467                 }
12468         } else if (n < n2) {
12469                 while (n < n2) {
12470                         m <<= 1;
12471                         n <<= 1;
12472                 }
12473         }
12474
12475         if (n != n2)
12476                 return false;
12477
12478         return intel_fuzzy_clock_check(m, m2);
12479 }
12480
12481 static bool
12482 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12483                        struct intel_link_m_n *m2_n2,
12484                        bool adjust)
12485 {
12486         if (m_n->tu == m2_n2->tu &&
12487             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12488                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12489             intel_compare_m_n(m_n->link_m, m_n->link_n,
12490                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12491                 if (adjust)
12492                         *m2_n2 = *m_n;
12493
12494                 return true;
12495         }
12496
12497         return false;
12498 }
12499
12500 static bool
12501 intel_pipe_config_compare(struct drm_device *dev,
12502                           struct intel_crtc_state *current_config,
12503                           struct intel_crtc_state *pipe_config,
12504                           bool adjust)
12505 {
12506         bool ret = true;
12507
12508 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12509         do { \
12510                 if (!adjust) \
12511                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12512                 else \
12513                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12514         } while (0)
12515
12516 #define PIPE_CONF_CHECK_X(name) \
12517         if (current_config->name != pipe_config->name) { \
12518                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12519                           "(expected 0x%08x, found 0x%08x)\n", \
12520                           current_config->name, \
12521                           pipe_config->name); \
12522                 ret = false; \
12523         }
12524
12525 #define PIPE_CONF_CHECK_I(name) \
12526         if (current_config->name != pipe_config->name) { \
12527                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12528                           "(expected %i, found %i)\n", \
12529                           current_config->name, \
12530                           pipe_config->name); \
12531                 ret = false; \
12532         }
12533
12534 #define PIPE_CONF_CHECK_P(name) \
12535         if (current_config->name != pipe_config->name) { \
12536                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12537                           "(expected %p, found %p)\n", \
12538                           current_config->name, \
12539                           pipe_config->name); \
12540                 ret = false; \
12541         }
12542
12543 #define PIPE_CONF_CHECK_M_N(name) \
12544         if (!intel_compare_link_m_n(&current_config->name, \
12545                                     &pipe_config->name,\
12546                                     adjust)) { \
12547                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12548                           "(expected tu %i gmch %i/%i link %i/%i, " \
12549                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12550                           current_config->name.tu, \
12551                           current_config->name.gmch_m, \
12552                           current_config->name.gmch_n, \
12553                           current_config->name.link_m, \
12554                           current_config->name.link_n, \
12555                           pipe_config->name.tu, \
12556                           pipe_config->name.gmch_m, \
12557                           pipe_config->name.gmch_n, \
12558                           pipe_config->name.link_m, \
12559                           pipe_config->name.link_n); \
12560                 ret = false; \
12561         }
12562
12563 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12564         if (!intel_compare_link_m_n(&current_config->name, \
12565                                     &pipe_config->name, adjust) && \
12566             !intel_compare_link_m_n(&current_config->alt_name, \
12567                                     &pipe_config->name, adjust)) { \
12568                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12569                           "(expected tu %i gmch %i/%i link %i/%i, " \
12570                           "or tu %i gmch %i/%i link %i/%i, " \
12571                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12572                           current_config->name.tu, \
12573                           current_config->name.gmch_m, \
12574                           current_config->name.gmch_n, \
12575                           current_config->name.link_m, \
12576                           current_config->name.link_n, \
12577                           current_config->alt_name.tu, \
12578                           current_config->alt_name.gmch_m, \
12579                           current_config->alt_name.gmch_n, \
12580                           current_config->alt_name.link_m, \
12581                           current_config->alt_name.link_n, \
12582                           pipe_config->name.tu, \
12583                           pipe_config->name.gmch_m, \
12584                           pipe_config->name.gmch_n, \
12585                           pipe_config->name.link_m, \
12586                           pipe_config->name.link_n); \
12587                 ret = false; \
12588         }
12589
12590 /* This is required for BDW+ where there is only one set of registers for
12591  * switching between high and low RR.
12592  * This macro can be used whenever a comparison has to be made between one
12593  * hw state and multiple sw state variables.
12594  */
12595 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12596         if ((current_config->name != pipe_config->name) && \
12597                 (current_config->alt_name != pipe_config->name)) { \
12598                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12599                                   "(expected %i or %i, found %i)\n", \
12600                                   current_config->name, \
12601                                   current_config->alt_name, \
12602                                   pipe_config->name); \
12603                         ret = false; \
12604         }
12605
12606 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12607         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12608                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12609                           "(expected %i, found %i)\n", \
12610                           current_config->name & (mask), \
12611                           pipe_config->name & (mask)); \
12612                 ret = false; \
12613         }
12614
12615 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12616         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12617                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12618                           "(expected %i, found %i)\n", \
12619                           current_config->name, \
12620                           pipe_config->name); \
12621                 ret = false; \
12622         }
12623
12624 #define PIPE_CONF_QUIRK(quirk)  \
12625         ((current_config->quirks | pipe_config->quirks) & (quirk))
12626
12627         PIPE_CONF_CHECK_I(cpu_transcoder);
12628
12629         PIPE_CONF_CHECK_I(has_pch_encoder);
12630         PIPE_CONF_CHECK_I(fdi_lanes);
12631         PIPE_CONF_CHECK_M_N(fdi_m_n);
12632
12633         PIPE_CONF_CHECK_I(has_dp_encoder);
12634         PIPE_CONF_CHECK_I(lane_count);
12635
12636         if (INTEL_INFO(dev)->gen < 8) {
12637                 PIPE_CONF_CHECK_M_N(dp_m_n);
12638
12639                 if (current_config->has_drrs)
12640                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12641         } else
12642                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12643
12644         PIPE_CONF_CHECK_I(has_dsi_encoder);
12645
12646         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12647         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12648         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12649         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12650         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12651         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12652
12653         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12654         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12655         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12656         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12657         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12658         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12659
12660         PIPE_CONF_CHECK_I(pixel_multiplier);
12661         PIPE_CONF_CHECK_I(has_hdmi_sink);
12662         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12663             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12664                 PIPE_CONF_CHECK_I(limited_color_range);
12665         PIPE_CONF_CHECK_I(has_infoframe);
12666
12667         PIPE_CONF_CHECK_I(has_audio);
12668
12669         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12670                               DRM_MODE_FLAG_INTERLACE);
12671
12672         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12673                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12674                                       DRM_MODE_FLAG_PHSYNC);
12675                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12676                                       DRM_MODE_FLAG_NHSYNC);
12677                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12678                                       DRM_MODE_FLAG_PVSYNC);
12679                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12680                                       DRM_MODE_FLAG_NVSYNC);
12681         }
12682
12683         PIPE_CONF_CHECK_X(gmch_pfit.control);
12684         /* pfit ratios are autocomputed by the hw on gen4+ */
12685         if (INTEL_INFO(dev)->gen < 4)
12686                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12687         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12688
12689         if (!adjust) {
12690                 PIPE_CONF_CHECK_I(pipe_src_w);
12691                 PIPE_CONF_CHECK_I(pipe_src_h);
12692
12693                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12694                 if (current_config->pch_pfit.enabled) {
12695                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12696                         PIPE_CONF_CHECK_X(pch_pfit.size);
12697                 }
12698
12699                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12700         }
12701
12702         /* BDW+ don't expose a synchronous way to read the state */
12703         if (IS_HASWELL(dev))
12704                 PIPE_CONF_CHECK_I(ips_enabled);
12705
12706         PIPE_CONF_CHECK_I(double_wide);
12707
12708         PIPE_CONF_CHECK_X(ddi_pll_sel);
12709
12710         PIPE_CONF_CHECK_P(shared_dpll);
12711         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12712         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12713         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12714         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12715         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12716         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12717         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12718         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12719         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12720
12721         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12722                 PIPE_CONF_CHECK_I(pipe_bpp);
12723
12724         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12725         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12726
12727 #undef PIPE_CONF_CHECK_X
12728 #undef PIPE_CONF_CHECK_I
12729 #undef PIPE_CONF_CHECK_P
12730 #undef PIPE_CONF_CHECK_I_ALT
12731 #undef PIPE_CONF_CHECK_FLAGS
12732 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12733 #undef PIPE_CONF_QUIRK
12734 #undef INTEL_ERR_OR_DBG_KMS
12735
12736         return ret;
12737 }
12738
12739 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12740                                            const struct intel_crtc_state *pipe_config)
12741 {
12742         if (pipe_config->has_pch_encoder) {
12743                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12744                                                             &pipe_config->fdi_m_n);
12745                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12746
12747                 /*
12748                  * FDI already provided one idea for the dotclock.
12749                  * Yell if the encoder disagrees.
12750                  */
12751                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12752                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12753                      fdi_dotclock, dotclock);
12754         }
12755 }
12756
12757 static void check_wm_state(struct drm_device *dev)
12758 {
12759         struct drm_i915_private *dev_priv = dev->dev_private;
12760         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12761         struct intel_crtc *intel_crtc;
12762         int plane;
12763
12764         if (INTEL_INFO(dev)->gen < 9)
12765                 return;
12766
12767         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12768         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12769
12770         for_each_intel_crtc(dev, intel_crtc) {
12771                 struct skl_ddb_entry *hw_entry, *sw_entry;
12772                 const enum pipe pipe = intel_crtc->pipe;
12773
12774                 if (!intel_crtc->active)
12775                         continue;
12776
12777                 /* planes */
12778                 for_each_plane(dev_priv, pipe, plane) {
12779                         hw_entry = &hw_ddb.plane[pipe][plane];
12780                         sw_entry = &sw_ddb->plane[pipe][plane];
12781
12782                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12783                                 continue;
12784
12785                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12786                                   "(expected (%u,%u), found (%u,%u))\n",
12787                                   pipe_name(pipe), plane + 1,
12788                                   sw_entry->start, sw_entry->end,
12789                                   hw_entry->start, hw_entry->end);
12790                 }
12791
12792                 /* cursor */
12793                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12794                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12795
12796                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12797                         continue;
12798
12799                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12800                           "(expected (%u,%u), found (%u,%u))\n",
12801                           pipe_name(pipe),
12802                           sw_entry->start, sw_entry->end,
12803                           hw_entry->start, hw_entry->end);
12804         }
12805 }
12806
12807 static void
12808 check_connector_state(struct drm_device *dev,
12809                       struct drm_atomic_state *old_state)
12810 {
12811         struct drm_connector_state *old_conn_state;
12812         struct drm_connector *connector;
12813         int i;
12814
12815         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12816                 struct drm_encoder *encoder = connector->encoder;
12817                 struct drm_connector_state *state = connector->state;
12818
12819                 /* This also checks the encoder/connector hw state with the
12820                  * ->get_hw_state callbacks. */
12821                 intel_connector_check_state(to_intel_connector(connector));
12822
12823                 I915_STATE_WARN(state->best_encoder != encoder,
12824                      "connector's atomic encoder doesn't match legacy encoder\n");
12825         }
12826 }
12827
12828 static void
12829 check_encoder_state(struct drm_device *dev)
12830 {
12831         struct intel_encoder *encoder;
12832         struct intel_connector *connector;
12833
12834         for_each_intel_encoder(dev, encoder) {
12835                 bool enabled = false;
12836                 enum pipe pipe;
12837
12838                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12839                               encoder->base.base.id,
12840                               encoder->base.name);
12841
12842                 for_each_intel_connector(dev, connector) {
12843                         if (connector->base.state->best_encoder != &encoder->base)
12844                                 continue;
12845                         enabled = true;
12846
12847                         I915_STATE_WARN(connector->base.state->crtc !=
12848                                         encoder->base.crtc,
12849                              "connector's crtc doesn't match encoder crtc\n");
12850                 }
12851
12852                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12853                      "encoder's enabled state mismatch "
12854                      "(expected %i, found %i)\n",
12855                      !!encoder->base.crtc, enabled);
12856
12857                 if (!encoder->base.crtc) {
12858                         bool active;
12859
12860                         active = encoder->get_hw_state(encoder, &pipe);
12861                         I915_STATE_WARN(active,
12862                              "encoder detached but still enabled on pipe %c.\n",
12863                              pipe_name(pipe));
12864                 }
12865         }
12866 }
12867
12868 static void
12869 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12870 {
12871         struct drm_i915_private *dev_priv = dev->dev_private;
12872         struct intel_encoder *encoder;
12873         struct drm_crtc_state *old_crtc_state;
12874         struct drm_crtc *crtc;
12875         int i;
12876
12877         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12878                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12879                 struct intel_crtc_state *pipe_config, *sw_config;
12880                 bool active;
12881
12882                 if (!needs_modeset(crtc->state) &&
12883                     !to_intel_crtc_state(crtc->state)->update_pipe)
12884                         continue;
12885
12886                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12887                 pipe_config = to_intel_crtc_state(old_crtc_state);
12888                 memset(pipe_config, 0, sizeof(*pipe_config));
12889                 pipe_config->base.crtc = crtc;
12890                 pipe_config->base.state = old_state;
12891
12892                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12893                               crtc->base.id);
12894
12895                 active = dev_priv->display.get_pipe_config(intel_crtc,
12896                                                            pipe_config);
12897
12898                 /* hw state is inconsistent with the pipe quirk */
12899                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12900                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12901                         active = crtc->state->active;
12902
12903                 I915_STATE_WARN(crtc->state->active != active,
12904                      "crtc active state doesn't match with hw state "
12905                      "(expected %i, found %i)\n", crtc->state->active, active);
12906
12907                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12908                      "transitional active state does not match atomic hw state "
12909                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12910
12911                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12912                         enum pipe pipe;
12913
12914                         active = encoder->get_hw_state(encoder, &pipe);
12915                         I915_STATE_WARN(active != crtc->state->active,
12916                                 "[ENCODER:%i] active %i with crtc active %i\n",
12917                                 encoder->base.base.id, active, crtc->state->active);
12918
12919                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12920                                         "Encoder connected to wrong pipe %c\n",
12921                                         pipe_name(pipe));
12922
12923                         if (active)
12924                                 encoder->get_config(encoder, pipe_config);
12925                 }
12926
12927                 if (!crtc->state->active)
12928                         continue;
12929
12930                 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12931
12932                 sw_config = to_intel_crtc_state(crtc->state);
12933                 if (!intel_pipe_config_compare(dev, sw_config,
12934                                                pipe_config, false)) {
12935                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12936                         intel_dump_pipe_config(intel_crtc, pipe_config,
12937                                                "[hw state]");
12938                         intel_dump_pipe_config(intel_crtc, sw_config,
12939                                                "[sw state]");
12940                 }
12941         }
12942 }
12943
12944 static void
12945 check_shared_dpll_state(struct drm_device *dev)
12946 {
12947         struct drm_i915_private *dev_priv = dev->dev_private;
12948         struct intel_crtc *crtc;
12949         struct intel_dpll_hw_state dpll_hw_state;
12950         int i;
12951
12952         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12953                 struct intel_shared_dpll *pll =
12954                         intel_get_shared_dpll_by_id(dev_priv, i);
12955                 int enabled_crtcs = 0, active_crtcs = 0;
12956                 bool active;
12957
12958                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12959
12960                 DRM_DEBUG_KMS("%s\n", pll->name);
12961
12962                 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12963
12964                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12965                      "more active pll users than references: %i vs %i\n",
12966                      pll->active, hweight32(pll->config.crtc_mask));
12967                 I915_STATE_WARN(pll->active && !pll->on,
12968                      "pll in active use but not on in sw tracking\n");
12969
12970                 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12971                         I915_STATE_WARN(pll->on && !pll->active,
12972                              "pll in on but not on in use in sw tracking\n");
12973                         I915_STATE_WARN(pll->on != active,
12974                              "pll on state mismatch (expected %i, found %i)\n",
12975                              pll->on, active);
12976                 }
12977
12978                 for_each_intel_crtc(dev, crtc) {
12979                         if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12980                                 enabled_crtcs++;
12981                         if (crtc->active && crtc->config->shared_dpll == pll)
12982                                 active_crtcs++;
12983                 }
12984                 I915_STATE_WARN(pll->active != active_crtcs,
12985                      "pll active crtcs mismatch (expected %i, found %i)\n",
12986                      pll->active, active_crtcs);
12987                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12988                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12989                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12990
12991                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12992                                        sizeof(dpll_hw_state)),
12993                      "pll hw state mismatch\n");
12994         }
12995 }
12996
12997 static void
12998 intel_modeset_check_state(struct drm_device *dev,
12999                           struct drm_atomic_state *old_state)
13000 {
13001         check_wm_state(dev);
13002         check_connector_state(dev, old_state);
13003         check_encoder_state(dev);
13004         check_crtc_state(dev, old_state);
13005         check_shared_dpll_state(dev);
13006 }
13007
13008 static void update_scanline_offset(struct intel_crtc *crtc)
13009 {
13010         struct drm_device *dev = crtc->base.dev;
13011
13012         /*
13013          * The scanline counter increments at the leading edge of hsync.
13014          *
13015          * On most platforms it starts counting from vtotal-1 on the
13016          * first active line. That means the scanline counter value is
13017          * always one less than what we would expect. Ie. just after
13018          * start of vblank, which also occurs at start of hsync (on the
13019          * last active line), the scanline counter will read vblank_start-1.
13020          *
13021          * On gen2 the scanline counter starts counting from 1 instead
13022          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13023          * to keep the value positive), instead of adding one.
13024          *
13025          * On HSW+ the behaviour of the scanline counter depends on the output
13026          * type. For DP ports it behaves like most other platforms, but on HDMI
13027          * there's an extra 1 line difference. So we need to add two instead of
13028          * one to the value.
13029          */
13030         if (IS_GEN2(dev)) {
13031                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13032                 int vtotal;
13033
13034                 vtotal = adjusted_mode->crtc_vtotal;
13035                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13036                         vtotal /= 2;
13037
13038                 crtc->scanline_offset = vtotal - 1;
13039         } else if (HAS_DDI(dev) &&
13040                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13041                 crtc->scanline_offset = 2;
13042         } else
13043                 crtc->scanline_offset = 1;
13044 }
13045
13046 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13047 {
13048         struct drm_device *dev = state->dev;
13049         struct drm_i915_private *dev_priv = to_i915(dev);
13050         struct intel_shared_dpll_config *shared_dpll = NULL;
13051         struct drm_crtc *crtc;
13052         struct drm_crtc_state *crtc_state;
13053         int i;
13054
13055         if (!dev_priv->display.crtc_compute_clock)
13056                 return;
13057
13058         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13059                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13060                 struct intel_shared_dpll *old_dpll =
13061                         to_intel_crtc_state(crtc->state)->shared_dpll;
13062
13063                 if (!needs_modeset(crtc_state))
13064                         continue;
13065
13066                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13067
13068                 if (!old_dpll)
13069                         continue;
13070
13071                 if (!shared_dpll)
13072                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13073
13074                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13075         }
13076 }
13077
13078 /*
13079  * This implements the workaround described in the "notes" section of the mode
13080  * set sequence documentation. When going from no pipes or single pipe to
13081  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13082  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13083  */
13084 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13085 {
13086         struct drm_crtc_state *crtc_state;
13087         struct intel_crtc *intel_crtc;
13088         struct drm_crtc *crtc;
13089         struct intel_crtc_state *first_crtc_state = NULL;
13090         struct intel_crtc_state *other_crtc_state = NULL;
13091         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13092         int i;
13093
13094         /* look at all crtc's that are going to be enabled in during modeset */
13095         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13096                 intel_crtc = to_intel_crtc(crtc);
13097
13098                 if (!crtc_state->active || !needs_modeset(crtc_state))
13099                         continue;
13100
13101                 if (first_crtc_state) {
13102                         other_crtc_state = to_intel_crtc_state(crtc_state);
13103                         break;
13104                 } else {
13105                         first_crtc_state = to_intel_crtc_state(crtc_state);
13106                         first_pipe = intel_crtc->pipe;
13107                 }
13108         }
13109
13110         /* No workaround needed? */
13111         if (!first_crtc_state)
13112                 return 0;
13113
13114         /* w/a possibly needed, check how many crtc's are already enabled. */
13115         for_each_intel_crtc(state->dev, intel_crtc) {
13116                 struct intel_crtc_state *pipe_config;
13117
13118                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13119                 if (IS_ERR(pipe_config))
13120                         return PTR_ERR(pipe_config);
13121
13122                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13123
13124                 if (!pipe_config->base.active ||
13125                     needs_modeset(&pipe_config->base))
13126                         continue;
13127
13128                 /* 2 or more enabled crtcs means no need for w/a */
13129                 if (enabled_pipe != INVALID_PIPE)
13130                         return 0;
13131
13132                 enabled_pipe = intel_crtc->pipe;
13133         }
13134
13135         if (enabled_pipe != INVALID_PIPE)
13136                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13137         else if (other_crtc_state)
13138                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13139
13140         return 0;
13141 }
13142
13143 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13144 {
13145         struct drm_crtc *crtc;
13146         struct drm_crtc_state *crtc_state;
13147         int ret = 0;
13148
13149         /* add all active pipes to the state */
13150         for_each_crtc(state->dev, crtc) {
13151                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13152                 if (IS_ERR(crtc_state))
13153                         return PTR_ERR(crtc_state);
13154
13155                 if (!crtc_state->active || needs_modeset(crtc_state))
13156                         continue;
13157
13158                 crtc_state->mode_changed = true;
13159
13160                 ret = drm_atomic_add_affected_connectors(state, crtc);
13161                 if (ret)
13162                         break;
13163
13164                 ret = drm_atomic_add_affected_planes(state, crtc);
13165                 if (ret)
13166                         break;
13167         }
13168
13169         return ret;
13170 }
13171
13172 static int intel_modeset_checks(struct drm_atomic_state *state)
13173 {
13174         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13175         struct drm_i915_private *dev_priv = state->dev->dev_private;
13176         struct drm_crtc *crtc;
13177         struct drm_crtc_state *crtc_state;
13178         int ret = 0, i;
13179
13180         if (!check_digital_port_conflicts(state)) {
13181                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13182                 return -EINVAL;
13183         }
13184
13185         intel_state->modeset = true;
13186         intel_state->active_crtcs = dev_priv->active_crtcs;
13187
13188         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13189                 if (crtc_state->active)
13190                         intel_state->active_crtcs |= 1 << i;
13191                 else
13192                         intel_state->active_crtcs &= ~(1 << i);
13193         }
13194
13195         /*
13196          * See if the config requires any additional preparation, e.g.
13197          * to adjust global state with pipes off.  We need to do this
13198          * here so we can get the modeset_pipe updated config for the new
13199          * mode set on this crtc.  For other crtcs we need to use the
13200          * adjusted_mode bits in the crtc directly.
13201          */
13202         if (dev_priv->display.modeset_calc_cdclk) {
13203                 ret = dev_priv->display.modeset_calc_cdclk(state);
13204
13205                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13206                         ret = intel_modeset_all_pipes(state);
13207
13208                 if (ret < 0)
13209                         return ret;
13210
13211                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13212                               intel_state->cdclk, intel_state->dev_cdclk);
13213         } else
13214                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13215
13216         intel_modeset_clear_plls(state);
13217
13218         if (IS_HASWELL(dev_priv))
13219                 return haswell_mode_set_planes_workaround(state);
13220
13221         return 0;
13222 }
13223
13224 /*
13225  * Handle calculation of various watermark data at the end of the atomic check
13226  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13227  * handlers to ensure that all derived state has been updated.
13228  */
13229 static void calc_watermark_data(struct drm_atomic_state *state)
13230 {
13231         struct drm_device *dev = state->dev;
13232         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13233         struct drm_crtc *crtc;
13234         struct drm_crtc_state *cstate;
13235         struct drm_plane *plane;
13236         struct drm_plane_state *pstate;
13237
13238         /*
13239          * Calculate watermark configuration details now that derived
13240          * plane/crtc state is all properly updated.
13241          */
13242         drm_for_each_crtc(crtc, dev) {
13243                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13244                         crtc->state;
13245
13246                 if (cstate->active)
13247                         intel_state->wm_config.num_pipes_active++;
13248         }
13249         drm_for_each_legacy_plane(plane, dev) {
13250                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13251                         plane->state;
13252
13253                 if (!to_intel_plane_state(pstate)->visible)
13254                         continue;
13255
13256                 intel_state->wm_config.sprites_enabled = true;
13257                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13258                     pstate->crtc_h != pstate->src_h >> 16)
13259                         intel_state->wm_config.sprites_scaled = true;
13260         }
13261 }
13262
13263 /**
13264  * intel_atomic_check - validate state object
13265  * @dev: drm device
13266  * @state: state to validate
13267  */
13268 static int intel_atomic_check(struct drm_device *dev,
13269                               struct drm_atomic_state *state)
13270 {
13271         struct drm_i915_private *dev_priv = to_i915(dev);
13272         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13273         struct drm_crtc *crtc;
13274         struct drm_crtc_state *crtc_state;
13275         int ret, i;
13276         bool any_ms = false;
13277
13278         ret = drm_atomic_helper_check_modeset(dev, state);
13279         if (ret)
13280                 return ret;
13281
13282         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13283                 struct intel_crtc_state *pipe_config =
13284                         to_intel_crtc_state(crtc_state);
13285
13286                 memset(&to_intel_crtc(crtc)->atomic, 0,
13287                        sizeof(struct intel_crtc_atomic_commit));
13288
13289                 /* Catch I915_MODE_FLAG_INHERITED */
13290                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13291                         crtc_state->mode_changed = true;
13292
13293                 if (!crtc_state->enable) {
13294                         if (needs_modeset(crtc_state))
13295                                 any_ms = true;
13296                         continue;
13297                 }
13298
13299                 if (!needs_modeset(crtc_state))
13300                         continue;
13301
13302                 /* FIXME: For only active_changed we shouldn't need to do any
13303                  * state recomputation at all. */
13304
13305                 ret = drm_atomic_add_affected_connectors(state, crtc);
13306                 if (ret)
13307                         return ret;
13308
13309                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13310                 if (ret)
13311                         return ret;
13312
13313                 if (i915.fastboot &&
13314                     intel_pipe_config_compare(dev,
13315                                         to_intel_crtc_state(crtc->state),
13316                                         pipe_config, true)) {
13317                         crtc_state->mode_changed = false;
13318                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13319                 }
13320
13321                 if (needs_modeset(crtc_state)) {
13322                         any_ms = true;
13323
13324                         ret = drm_atomic_add_affected_planes(state, crtc);
13325                         if (ret)
13326                                 return ret;
13327                 }
13328
13329                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13330                                        needs_modeset(crtc_state) ?
13331                                        "[modeset]" : "[fastset]");
13332         }
13333
13334         if (any_ms) {
13335                 ret = intel_modeset_checks(state);
13336
13337                 if (ret)
13338                         return ret;
13339         } else
13340                 intel_state->cdclk = dev_priv->cdclk_freq;
13341
13342         ret = drm_atomic_helper_check_planes(dev, state);
13343         if (ret)
13344                 return ret;
13345
13346         intel_fbc_choose_crtc(dev_priv, state);
13347         calc_watermark_data(state);
13348
13349         return 0;
13350 }
13351
13352 static int intel_atomic_prepare_commit(struct drm_device *dev,
13353                                        struct drm_atomic_state *state,
13354                                        bool async)
13355 {
13356         struct drm_i915_private *dev_priv = dev->dev_private;
13357         struct drm_plane_state *plane_state;
13358         struct drm_crtc_state *crtc_state;
13359         struct drm_plane *plane;
13360         struct drm_crtc *crtc;
13361         int i, ret;
13362
13363         if (async) {
13364                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13365                 return -EINVAL;
13366         }
13367
13368         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13369                 ret = intel_crtc_wait_for_pending_flips(crtc);
13370                 if (ret)
13371                         return ret;
13372
13373                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13374                         flush_workqueue(dev_priv->wq);
13375         }
13376
13377         ret = mutex_lock_interruptible(&dev->struct_mutex);
13378         if (ret)
13379                 return ret;
13380
13381         ret = drm_atomic_helper_prepare_planes(dev, state);
13382         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13383                 u32 reset_counter;
13384
13385                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13386                 mutex_unlock(&dev->struct_mutex);
13387
13388                 for_each_plane_in_state(state, plane, plane_state, i) {
13389                         struct intel_plane_state *intel_plane_state =
13390                                 to_intel_plane_state(plane_state);
13391
13392                         if (!intel_plane_state->wait_req)
13393                                 continue;
13394
13395                         ret = __i915_wait_request(intel_plane_state->wait_req,
13396                                                   reset_counter, true,
13397                                                   NULL, NULL);
13398
13399                         /* Swallow -EIO errors to allow updates during hw lockup. */
13400                         if (ret == -EIO)
13401                                 ret = 0;
13402
13403                         if (ret)
13404                                 break;
13405                 }
13406
13407                 if (!ret)
13408                         return 0;
13409
13410                 mutex_lock(&dev->struct_mutex);
13411                 drm_atomic_helper_cleanup_planes(dev, state);
13412         }
13413
13414         mutex_unlock(&dev->struct_mutex);
13415         return ret;
13416 }
13417
13418 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13419                                           struct drm_i915_private *dev_priv,
13420                                           unsigned crtc_mask)
13421 {
13422         unsigned last_vblank_count[I915_MAX_PIPES];
13423         enum pipe pipe;
13424         int ret;
13425
13426         if (!crtc_mask)
13427                 return;
13428
13429         for_each_pipe(dev_priv, pipe) {
13430                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13431
13432                 if (!((1 << pipe) & crtc_mask))
13433                         continue;
13434
13435                 ret = drm_crtc_vblank_get(crtc);
13436                 if (WARN_ON(ret != 0)) {
13437                         crtc_mask &= ~(1 << pipe);
13438                         continue;
13439                 }
13440
13441                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13442         }
13443
13444         for_each_pipe(dev_priv, pipe) {
13445                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13446                 long lret;
13447
13448                 if (!((1 << pipe) & crtc_mask))
13449                         continue;
13450
13451                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13452                                 last_vblank_count[pipe] !=
13453                                         drm_crtc_vblank_count(crtc),
13454                                 msecs_to_jiffies(50));
13455
13456                 WARN_ON(!lret);
13457
13458                 drm_crtc_vblank_put(crtc);
13459         }
13460 }
13461
13462 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13463 {
13464         /* fb updated, need to unpin old fb */
13465         if (crtc_state->fb_changed)
13466                 return true;
13467
13468         /* wm changes, need vblank before final wm's */
13469         if (crtc_state->update_wm_post)
13470                 return true;
13471
13472         /*
13473          * cxsr is re-enabled after vblank.
13474          * This is already handled by crtc_state->update_wm_post,
13475          * but added for clarity.
13476          */
13477         if (crtc_state->disable_cxsr)
13478                 return true;
13479
13480         return false;
13481 }
13482
13483 /**
13484  * intel_atomic_commit - commit validated state object
13485  * @dev: DRM device
13486  * @state: the top-level driver state object
13487  * @async: asynchronous commit
13488  *
13489  * This function commits a top-level state object that has been validated
13490  * with drm_atomic_helper_check().
13491  *
13492  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13493  * we can only handle plane-related operations and do not yet support
13494  * asynchronous commit.
13495  *
13496  * RETURNS
13497  * Zero for success or -errno.
13498  */
13499 static int intel_atomic_commit(struct drm_device *dev,
13500                                struct drm_atomic_state *state,
13501                                bool async)
13502 {
13503         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13504         struct drm_i915_private *dev_priv = dev->dev_private;
13505         struct drm_crtc_state *old_crtc_state;
13506         struct drm_crtc *crtc;
13507         struct intel_crtc_state *intel_cstate;
13508         int ret = 0, i;
13509         bool hw_check = intel_state->modeset;
13510         unsigned long put_domains[I915_MAX_PIPES] = {};
13511         unsigned crtc_vblank_mask = 0;
13512
13513         ret = intel_atomic_prepare_commit(dev, state, async);
13514         if (ret) {
13515                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13516                 return ret;
13517         }
13518
13519         drm_atomic_helper_swap_state(dev, state);
13520         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13521
13522         if (intel_state->modeset) {
13523                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13524                        sizeof(intel_state->min_pixclk));
13525                 dev_priv->active_crtcs = intel_state->active_crtcs;
13526                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13527
13528                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13529         }
13530
13531         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13532                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13533
13534                 if (needs_modeset(crtc->state) ||
13535                     to_intel_crtc_state(crtc->state)->update_pipe) {
13536                         hw_check = true;
13537
13538                         put_domains[to_intel_crtc(crtc)->pipe] =
13539                                 modeset_get_crtc_power_domains(crtc,
13540                                         to_intel_crtc_state(crtc->state));
13541                 }
13542
13543                 if (!needs_modeset(crtc->state))
13544                         continue;
13545
13546                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13547
13548                 if (old_crtc_state->active) {
13549                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13550                         dev_priv->display.crtc_disable(crtc);
13551                         intel_crtc->active = false;
13552                         intel_fbc_disable(intel_crtc);
13553                         intel_disable_shared_dpll(intel_crtc);
13554
13555                         /*
13556                          * Underruns don't always raise
13557                          * interrupts, so check manually.
13558                          */
13559                         intel_check_cpu_fifo_underruns(dev_priv);
13560                         intel_check_pch_fifo_underruns(dev_priv);
13561
13562                         if (!crtc->state->active)
13563                                 intel_update_watermarks(crtc);
13564                 }
13565         }
13566
13567         /* Only after disabling all output pipelines that will be changed can we
13568          * update the the output configuration. */
13569         intel_modeset_update_crtc_state(state);
13570
13571         if (intel_state->modeset) {
13572                 intel_shared_dpll_commit(state);
13573
13574                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13575
13576                 if (dev_priv->display.modeset_commit_cdclk &&
13577                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13578                         dev_priv->display.modeset_commit_cdclk(state);
13579         }
13580
13581         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13582         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13583                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13584                 bool modeset = needs_modeset(crtc->state);
13585                 struct intel_crtc_state *pipe_config =
13586                         to_intel_crtc_state(crtc->state);
13587                 bool update_pipe = !modeset && pipe_config->update_pipe;
13588
13589                 if (modeset && crtc->state->active) {
13590                         update_scanline_offset(to_intel_crtc(crtc));
13591                         dev_priv->display.crtc_enable(crtc);
13592                 }
13593
13594                 if (!modeset)
13595                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13596
13597                 if (crtc->state->active && intel_crtc->atomic.update_fbc)
13598                         intel_fbc_enable(intel_crtc);
13599
13600                 if (crtc->state->active &&
13601                     (crtc->state->planes_changed || update_pipe))
13602                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13603
13604                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13605                         crtc_vblank_mask |= 1 << i;
13606         }
13607
13608         /* FIXME: add subpixel order */
13609
13610         if (!state->legacy_cursor_update)
13611                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13612
13613         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13614                 intel_post_plane_update(to_intel_crtc(crtc));
13615
13616                 if (put_domains[i])
13617                         modeset_put_power_domains(dev_priv, put_domains[i]);
13618         }
13619
13620         if (intel_state->modeset)
13621                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13622
13623         /*
13624          * Now that the vblank has passed, we can go ahead and program the
13625          * optimal watermarks on platforms that need two-step watermark
13626          * programming.
13627          *
13628          * TODO: Move this (and other cleanup) to an async worker eventually.
13629          */
13630         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13631                 intel_cstate = to_intel_crtc_state(crtc->state);
13632
13633                 if (dev_priv->display.optimize_watermarks)
13634                         dev_priv->display.optimize_watermarks(intel_cstate);
13635         }
13636
13637         mutex_lock(&dev->struct_mutex);
13638         drm_atomic_helper_cleanup_planes(dev, state);
13639         mutex_unlock(&dev->struct_mutex);
13640
13641         if (hw_check)
13642                 intel_modeset_check_state(dev, state);
13643
13644         drm_atomic_state_free(state);
13645
13646         /* As one of the primary mmio accessors, KMS has a high likelihood
13647          * of triggering bugs in unclaimed access. After we finish
13648          * modesetting, see if an error has been flagged, and if so
13649          * enable debugging for the next modeset - and hope we catch
13650          * the culprit.
13651          *
13652          * XXX note that we assume display power is on at this point.
13653          * This might hold true now but we need to add pm helper to check
13654          * unclaimed only when the hardware is on, as atomic commits
13655          * can happen also when the device is completely off.
13656          */
13657         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13658
13659         return 0;
13660 }
13661
13662 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13663 {
13664         struct drm_device *dev = crtc->dev;
13665         struct drm_atomic_state *state;
13666         struct drm_crtc_state *crtc_state;
13667         int ret;
13668
13669         state = drm_atomic_state_alloc(dev);
13670         if (!state) {
13671                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13672                               crtc->base.id);
13673                 return;
13674         }
13675
13676         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13677
13678 retry:
13679         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13680         ret = PTR_ERR_OR_ZERO(crtc_state);
13681         if (!ret) {
13682                 if (!crtc_state->active)
13683                         goto out;
13684
13685                 crtc_state->mode_changed = true;
13686                 ret = drm_atomic_commit(state);
13687         }
13688
13689         if (ret == -EDEADLK) {
13690                 drm_atomic_state_clear(state);
13691                 drm_modeset_backoff(state->acquire_ctx);
13692                 goto retry;
13693         }
13694
13695         if (ret)
13696 out:
13697                 drm_atomic_state_free(state);
13698 }
13699
13700 #undef for_each_intel_crtc_masked
13701
13702 static const struct drm_crtc_funcs intel_crtc_funcs = {
13703         .gamma_set = intel_crtc_gamma_set,
13704         .set_config = drm_atomic_helper_set_config,
13705         .destroy = intel_crtc_destroy,
13706         .page_flip = intel_crtc_page_flip,
13707         .atomic_duplicate_state = intel_crtc_duplicate_state,
13708         .atomic_destroy_state = intel_crtc_destroy_state,
13709 };
13710
13711 /**
13712  * intel_prepare_plane_fb - Prepare fb for usage on plane
13713  * @plane: drm plane to prepare for
13714  * @fb: framebuffer to prepare for presentation
13715  *
13716  * Prepares a framebuffer for usage on a display plane.  Generally this
13717  * involves pinning the underlying object and updating the frontbuffer tracking
13718  * bits.  Some older platforms need special physical address handling for
13719  * cursor planes.
13720  *
13721  * Must be called with struct_mutex held.
13722  *
13723  * Returns 0 on success, negative error code on failure.
13724  */
13725 int
13726 intel_prepare_plane_fb(struct drm_plane *plane,
13727                        const struct drm_plane_state *new_state)
13728 {
13729         struct drm_device *dev = plane->dev;
13730         struct drm_framebuffer *fb = new_state->fb;
13731         struct intel_plane *intel_plane = to_intel_plane(plane);
13732         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13733         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13734         int ret = 0;
13735
13736         if (!obj && !old_obj)
13737                 return 0;
13738
13739         if (old_obj) {
13740                 struct drm_crtc_state *crtc_state =
13741                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13742
13743                 /* Big Hammer, we also need to ensure that any pending
13744                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13745                  * current scanout is retired before unpinning the old
13746                  * framebuffer. Note that we rely on userspace rendering
13747                  * into the buffer attached to the pipe they are waiting
13748                  * on. If not, userspace generates a GPU hang with IPEHR
13749                  * point to the MI_WAIT_FOR_EVENT.
13750                  *
13751                  * This should only fail upon a hung GPU, in which case we
13752                  * can safely continue.
13753                  */
13754                 if (needs_modeset(crtc_state))
13755                         ret = i915_gem_object_wait_rendering(old_obj, true);
13756
13757                 /* Swallow -EIO errors to allow updates during hw lockup. */
13758                 if (ret && ret != -EIO)
13759                         return ret;
13760         }
13761
13762         /* For framebuffer backed by dmabuf, wait for fence */
13763         if (obj && obj->base.dma_buf) {
13764                 long lret;
13765
13766                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13767                                                            false, true,
13768                                                            MAX_SCHEDULE_TIMEOUT);
13769                 if (lret == -ERESTARTSYS)
13770                         return lret;
13771
13772                 WARN(lret < 0, "waiting returns %li\n", lret);
13773         }
13774
13775         if (!obj) {
13776                 ret = 0;
13777         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13778             INTEL_INFO(dev)->cursor_needs_physical) {
13779                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13780                 ret = i915_gem_object_attach_phys(obj, align);
13781                 if (ret)
13782                         DRM_DEBUG_KMS("failed to attach phys object\n");
13783         } else {
13784                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13785         }
13786
13787         if (ret == 0) {
13788                 if (obj) {
13789                         struct intel_plane_state *plane_state =
13790                                 to_intel_plane_state(new_state);
13791
13792                         i915_gem_request_assign(&plane_state->wait_req,
13793                                                 obj->last_write_req);
13794                 }
13795
13796                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13797         }
13798
13799         return ret;
13800 }
13801
13802 /**
13803  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13804  * @plane: drm plane to clean up for
13805  * @fb: old framebuffer that was on plane
13806  *
13807  * Cleans up a framebuffer that has just been removed from a plane.
13808  *
13809  * Must be called with struct_mutex held.
13810  */
13811 void
13812 intel_cleanup_plane_fb(struct drm_plane *plane,
13813                        const struct drm_plane_state *old_state)
13814 {
13815         struct drm_device *dev = plane->dev;
13816         struct intel_plane *intel_plane = to_intel_plane(plane);
13817         struct intel_plane_state *old_intel_state;
13818         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13819         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13820
13821         old_intel_state = to_intel_plane_state(old_state);
13822
13823         if (!obj && !old_obj)
13824                 return;
13825
13826         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13827             !INTEL_INFO(dev)->cursor_needs_physical))
13828                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13829
13830         /* prepare_fb aborted? */
13831         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13832             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13833                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13834
13835         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13836 }
13837
13838 int
13839 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13840 {
13841         int max_scale;
13842         struct drm_device *dev;
13843         struct drm_i915_private *dev_priv;
13844         int crtc_clock, cdclk;
13845
13846         if (!intel_crtc || !crtc_state->base.enable)
13847                 return DRM_PLANE_HELPER_NO_SCALING;
13848
13849         dev = intel_crtc->base.dev;
13850         dev_priv = dev->dev_private;
13851         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13852         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13853
13854         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13855                 return DRM_PLANE_HELPER_NO_SCALING;
13856
13857         /*
13858          * skl max scale is lower of:
13859          *    close to 3 but not 3, -1 is for that purpose
13860          *            or
13861          *    cdclk/crtc_clock
13862          */
13863         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13864
13865         return max_scale;
13866 }
13867
13868 static int
13869 intel_check_primary_plane(struct drm_plane *plane,
13870                           struct intel_crtc_state *crtc_state,
13871                           struct intel_plane_state *state)
13872 {
13873         struct drm_crtc *crtc = state->base.crtc;
13874         struct drm_framebuffer *fb = state->base.fb;
13875         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13876         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13877         bool can_position = false;
13878
13879         if (INTEL_INFO(plane->dev)->gen >= 9) {
13880                 /* use scaler when colorkey is not required */
13881                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13882                         min_scale = 1;
13883                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13884                 }
13885                 can_position = true;
13886         }
13887
13888         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13889                                              &state->dst, &state->clip,
13890                                              min_scale, max_scale,
13891                                              can_position, true,
13892                                              &state->visible);
13893 }
13894
13895 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13896                                     struct drm_crtc_state *old_crtc_state)
13897 {
13898         struct drm_device *dev = crtc->dev;
13899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13900         struct intel_crtc_state *old_intel_state =
13901                 to_intel_crtc_state(old_crtc_state);
13902         bool modeset = needs_modeset(crtc->state);
13903
13904         /* Perform vblank evasion around commit operation */
13905         intel_pipe_update_start(intel_crtc);
13906
13907         if (modeset)
13908                 return;
13909
13910         if (to_intel_crtc_state(crtc->state)->update_pipe)
13911                 intel_update_pipe_config(intel_crtc, old_intel_state);
13912         else if (INTEL_INFO(dev)->gen >= 9)
13913                 skl_detach_scalers(intel_crtc);
13914 }
13915
13916 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13917                                      struct drm_crtc_state *old_crtc_state)
13918 {
13919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13920
13921         intel_pipe_update_end(intel_crtc);
13922 }
13923
13924 /**
13925  * intel_plane_destroy - destroy a plane
13926  * @plane: plane to destroy
13927  *
13928  * Common destruction function for all types of planes (primary, cursor,
13929  * sprite).
13930  */
13931 void intel_plane_destroy(struct drm_plane *plane)
13932 {
13933         struct intel_plane *intel_plane = to_intel_plane(plane);
13934         drm_plane_cleanup(plane);
13935         kfree(intel_plane);
13936 }
13937
13938 const struct drm_plane_funcs intel_plane_funcs = {
13939         .update_plane = drm_atomic_helper_update_plane,
13940         .disable_plane = drm_atomic_helper_disable_plane,
13941         .destroy = intel_plane_destroy,
13942         .set_property = drm_atomic_helper_plane_set_property,
13943         .atomic_get_property = intel_plane_atomic_get_property,
13944         .atomic_set_property = intel_plane_atomic_set_property,
13945         .atomic_duplicate_state = intel_plane_duplicate_state,
13946         .atomic_destroy_state = intel_plane_destroy_state,
13947
13948 };
13949
13950 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13951                                                     int pipe)
13952 {
13953         struct intel_plane *primary;
13954         struct intel_plane_state *state;
13955         const uint32_t *intel_primary_formats;
13956         unsigned int num_formats;
13957
13958         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13959         if (primary == NULL)
13960                 return NULL;
13961
13962         state = intel_create_plane_state(&primary->base);
13963         if (!state) {
13964                 kfree(primary);
13965                 return NULL;
13966         }
13967         primary->base.state = &state->base;
13968
13969         primary->can_scale = false;
13970         primary->max_downscale = 1;
13971         if (INTEL_INFO(dev)->gen >= 9) {
13972                 primary->can_scale = true;
13973                 state->scaler_id = -1;
13974         }
13975         primary->pipe = pipe;
13976         primary->plane = pipe;
13977         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13978         primary->check_plane = intel_check_primary_plane;
13979         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13980                 primary->plane = !pipe;
13981
13982         if (INTEL_INFO(dev)->gen >= 9) {
13983                 intel_primary_formats = skl_primary_formats;
13984                 num_formats = ARRAY_SIZE(skl_primary_formats);
13985
13986                 primary->update_plane = skylake_update_primary_plane;
13987                 primary->disable_plane = skylake_disable_primary_plane;
13988         } else if (HAS_PCH_SPLIT(dev)) {
13989                 intel_primary_formats = i965_primary_formats;
13990                 num_formats = ARRAY_SIZE(i965_primary_formats);
13991
13992                 primary->update_plane = ironlake_update_primary_plane;
13993                 primary->disable_plane = i9xx_disable_primary_plane;
13994         } else if (INTEL_INFO(dev)->gen >= 4) {
13995                 intel_primary_formats = i965_primary_formats;
13996                 num_formats = ARRAY_SIZE(i965_primary_formats);
13997
13998                 primary->update_plane = i9xx_update_primary_plane;
13999                 primary->disable_plane = i9xx_disable_primary_plane;
14000         } else {
14001                 intel_primary_formats = i8xx_primary_formats;
14002                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14003
14004                 primary->update_plane = i9xx_update_primary_plane;
14005                 primary->disable_plane = i9xx_disable_primary_plane;
14006         }
14007
14008         drm_universal_plane_init(dev, &primary->base, 0,
14009                                  &intel_plane_funcs,
14010                                  intel_primary_formats, num_formats,
14011                                  DRM_PLANE_TYPE_PRIMARY, NULL);
14012
14013         if (INTEL_INFO(dev)->gen >= 4)
14014                 intel_create_rotation_property(dev, primary);
14015
14016         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14017
14018         return &primary->base;
14019 }
14020
14021 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14022 {
14023         if (!dev->mode_config.rotation_property) {
14024                 unsigned long flags = BIT(DRM_ROTATE_0) |
14025                         BIT(DRM_ROTATE_180);
14026
14027                 if (INTEL_INFO(dev)->gen >= 9)
14028                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14029
14030                 dev->mode_config.rotation_property =
14031                         drm_mode_create_rotation_property(dev, flags);
14032         }
14033         if (dev->mode_config.rotation_property)
14034                 drm_object_attach_property(&plane->base.base,
14035                                 dev->mode_config.rotation_property,
14036                                 plane->base.state->rotation);
14037 }
14038
14039 static int
14040 intel_check_cursor_plane(struct drm_plane *plane,
14041                          struct intel_crtc_state *crtc_state,
14042                          struct intel_plane_state *state)
14043 {
14044         struct drm_crtc *crtc = crtc_state->base.crtc;
14045         struct drm_framebuffer *fb = state->base.fb;
14046         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14047         enum pipe pipe = to_intel_plane(plane)->pipe;
14048         unsigned stride;
14049         int ret;
14050
14051         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14052                                             &state->dst, &state->clip,
14053                                             DRM_PLANE_HELPER_NO_SCALING,
14054                                             DRM_PLANE_HELPER_NO_SCALING,
14055                                             true, true, &state->visible);
14056         if (ret)
14057                 return ret;
14058
14059         /* if we want to turn off the cursor ignore width and height */
14060         if (!obj)
14061                 return 0;
14062
14063         /* Check for which cursor types we support */
14064         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14065                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14066                           state->base.crtc_w, state->base.crtc_h);
14067                 return -EINVAL;
14068         }
14069
14070         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14071         if (obj->base.size < stride * state->base.crtc_h) {
14072                 DRM_DEBUG_KMS("buffer is too small\n");
14073                 return -ENOMEM;
14074         }
14075
14076         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14077                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14078                 return -EINVAL;
14079         }
14080
14081         /*
14082          * There's something wrong with the cursor on CHV pipe C.
14083          * If it straddles the left edge of the screen then
14084          * moving it away from the edge or disabling it often
14085          * results in a pipe underrun, and often that can lead to
14086          * dead pipe (constant underrun reported, and it scans
14087          * out just a solid color). To recover from that, the
14088          * display power well must be turned off and on again.
14089          * Refuse the put the cursor into that compromised position.
14090          */
14091         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14092             state->visible && state->base.crtc_x < 0) {
14093                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14094                 return -EINVAL;
14095         }
14096
14097         return 0;
14098 }
14099
14100 static void
14101 intel_disable_cursor_plane(struct drm_plane *plane,
14102                            struct drm_crtc *crtc)
14103 {
14104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14105
14106         intel_crtc->cursor_addr = 0;
14107         intel_crtc_update_cursor(crtc, NULL);
14108 }
14109
14110 static void
14111 intel_update_cursor_plane(struct drm_plane *plane,
14112                           const struct intel_crtc_state *crtc_state,
14113                           const struct intel_plane_state *state)
14114 {
14115         struct drm_crtc *crtc = crtc_state->base.crtc;
14116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14117         struct drm_device *dev = plane->dev;
14118         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14119         uint32_t addr;
14120
14121         if (!obj)
14122                 addr = 0;
14123         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14124                 addr = i915_gem_obj_ggtt_offset(obj);
14125         else
14126                 addr = obj->phys_handle->busaddr;
14127
14128         intel_crtc->cursor_addr = addr;
14129         intel_crtc_update_cursor(crtc, state);
14130 }
14131
14132 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14133                                                    int pipe)
14134 {
14135         struct intel_plane *cursor;
14136         struct intel_plane_state *state;
14137
14138         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14139         if (cursor == NULL)
14140                 return NULL;
14141
14142         state = intel_create_plane_state(&cursor->base);
14143         if (!state) {
14144                 kfree(cursor);
14145                 return NULL;
14146         }
14147         cursor->base.state = &state->base;
14148
14149         cursor->can_scale = false;
14150         cursor->max_downscale = 1;
14151         cursor->pipe = pipe;
14152         cursor->plane = pipe;
14153         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14154         cursor->check_plane = intel_check_cursor_plane;
14155         cursor->update_plane = intel_update_cursor_plane;
14156         cursor->disable_plane = intel_disable_cursor_plane;
14157
14158         drm_universal_plane_init(dev, &cursor->base, 0,
14159                                  &intel_plane_funcs,
14160                                  intel_cursor_formats,
14161                                  ARRAY_SIZE(intel_cursor_formats),
14162                                  DRM_PLANE_TYPE_CURSOR, NULL);
14163
14164         if (INTEL_INFO(dev)->gen >= 4) {
14165                 if (!dev->mode_config.rotation_property)
14166                         dev->mode_config.rotation_property =
14167                                 drm_mode_create_rotation_property(dev,
14168                                                         BIT(DRM_ROTATE_0) |
14169                                                         BIT(DRM_ROTATE_180));
14170                 if (dev->mode_config.rotation_property)
14171                         drm_object_attach_property(&cursor->base.base,
14172                                 dev->mode_config.rotation_property,
14173                                 state->base.rotation);
14174         }
14175
14176         if (INTEL_INFO(dev)->gen >=9)
14177                 state->scaler_id = -1;
14178
14179         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14180
14181         return &cursor->base;
14182 }
14183
14184 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14185         struct intel_crtc_state *crtc_state)
14186 {
14187         int i;
14188         struct intel_scaler *intel_scaler;
14189         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14190
14191         for (i = 0; i < intel_crtc->num_scalers; i++) {
14192                 intel_scaler = &scaler_state->scalers[i];
14193                 intel_scaler->in_use = 0;
14194                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14195         }
14196
14197         scaler_state->scaler_id = -1;
14198 }
14199
14200 static void intel_crtc_init(struct drm_device *dev, int pipe)
14201 {
14202         struct drm_i915_private *dev_priv = dev->dev_private;
14203         struct intel_crtc *intel_crtc;
14204         struct intel_crtc_state *crtc_state = NULL;
14205         struct drm_plane *primary = NULL;
14206         struct drm_plane *cursor = NULL;
14207         int i, ret;
14208
14209         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14210         if (intel_crtc == NULL)
14211                 return;
14212
14213         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14214         if (!crtc_state)
14215                 goto fail;
14216         intel_crtc->config = crtc_state;
14217         intel_crtc->base.state = &crtc_state->base;
14218         crtc_state->base.crtc = &intel_crtc->base;
14219
14220         /* initialize shared scalers */
14221         if (INTEL_INFO(dev)->gen >= 9) {
14222                 if (pipe == PIPE_C)
14223                         intel_crtc->num_scalers = 1;
14224                 else
14225                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14226
14227                 skl_init_scalers(dev, intel_crtc, crtc_state);
14228         }
14229
14230         primary = intel_primary_plane_create(dev, pipe);
14231         if (!primary)
14232                 goto fail;
14233
14234         cursor = intel_cursor_plane_create(dev, pipe);
14235         if (!cursor)
14236                 goto fail;
14237
14238         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14239                                         cursor, &intel_crtc_funcs, NULL);
14240         if (ret)
14241                 goto fail;
14242
14243         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14244         for (i = 0; i < 256; i++) {
14245                 intel_crtc->lut_r[i] = i;
14246                 intel_crtc->lut_g[i] = i;
14247                 intel_crtc->lut_b[i] = i;
14248         }
14249
14250         /*
14251          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14252          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14253          */
14254         intel_crtc->pipe = pipe;
14255         intel_crtc->plane = pipe;
14256         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14257                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14258                 intel_crtc->plane = !pipe;
14259         }
14260
14261         intel_crtc->cursor_base = ~0;
14262         intel_crtc->cursor_cntl = ~0;
14263         intel_crtc->cursor_size = ~0;
14264
14265         intel_crtc->wm.cxsr_allowed = true;
14266
14267         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14268                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14269         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14270         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14271
14272         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14273
14274         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14275         return;
14276
14277 fail:
14278         if (primary)
14279                 drm_plane_cleanup(primary);
14280         if (cursor)
14281                 drm_plane_cleanup(cursor);
14282         kfree(crtc_state);
14283         kfree(intel_crtc);
14284 }
14285
14286 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14287 {
14288         struct drm_encoder *encoder = connector->base.encoder;
14289         struct drm_device *dev = connector->base.dev;
14290
14291         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14292
14293         if (!encoder || WARN_ON(!encoder->crtc))
14294                 return INVALID_PIPE;
14295
14296         return to_intel_crtc(encoder->crtc)->pipe;
14297 }
14298
14299 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14300                                 struct drm_file *file)
14301 {
14302         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14303         struct drm_crtc *drmmode_crtc;
14304         struct intel_crtc *crtc;
14305
14306         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14307
14308         if (!drmmode_crtc) {
14309                 DRM_ERROR("no such CRTC id\n");
14310                 return -ENOENT;
14311         }
14312
14313         crtc = to_intel_crtc(drmmode_crtc);
14314         pipe_from_crtc_id->pipe = crtc->pipe;
14315
14316         return 0;
14317 }
14318
14319 static int intel_encoder_clones(struct intel_encoder *encoder)
14320 {
14321         struct drm_device *dev = encoder->base.dev;
14322         struct intel_encoder *source_encoder;
14323         int index_mask = 0;
14324         int entry = 0;
14325
14326         for_each_intel_encoder(dev, source_encoder) {
14327                 if (encoders_cloneable(encoder, source_encoder))
14328                         index_mask |= (1 << entry);
14329
14330                 entry++;
14331         }
14332
14333         return index_mask;
14334 }
14335
14336 static bool has_edp_a(struct drm_device *dev)
14337 {
14338         struct drm_i915_private *dev_priv = dev->dev_private;
14339
14340         if (!IS_MOBILE(dev))
14341                 return false;
14342
14343         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14344                 return false;
14345
14346         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14347                 return false;
14348
14349         return true;
14350 }
14351
14352 static bool intel_crt_present(struct drm_device *dev)
14353 {
14354         struct drm_i915_private *dev_priv = dev->dev_private;
14355
14356         if (INTEL_INFO(dev)->gen >= 9)
14357                 return false;
14358
14359         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14360                 return false;
14361
14362         if (IS_CHERRYVIEW(dev))
14363                 return false;
14364
14365         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14366                 return false;
14367
14368         /* DDI E can't be used if DDI A requires 4 lanes */
14369         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14370                 return false;
14371
14372         if (!dev_priv->vbt.int_crt_support)
14373                 return false;
14374
14375         return true;
14376 }
14377
14378 static void intel_setup_outputs(struct drm_device *dev)
14379 {
14380         struct drm_i915_private *dev_priv = dev->dev_private;
14381         struct intel_encoder *encoder;
14382         bool dpd_is_edp = false;
14383
14384         intel_lvds_init(dev);
14385
14386         if (intel_crt_present(dev))
14387                 intel_crt_init(dev);
14388
14389         if (IS_BROXTON(dev)) {
14390                 /*
14391                  * FIXME: Broxton doesn't support port detection via the
14392                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14393                  * detect the ports.
14394                  */
14395                 intel_ddi_init(dev, PORT_A);
14396                 intel_ddi_init(dev, PORT_B);
14397                 intel_ddi_init(dev, PORT_C);
14398         } else if (HAS_DDI(dev)) {
14399                 int found;
14400
14401                 /*
14402                  * Haswell uses DDI functions to detect digital outputs.
14403                  * On SKL pre-D0 the strap isn't connected, so we assume
14404                  * it's there.
14405                  */
14406                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14407                 /* WaIgnoreDDIAStrap: skl */
14408                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14409                         intel_ddi_init(dev, PORT_A);
14410
14411                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14412                  * register */
14413                 found = I915_READ(SFUSE_STRAP);
14414
14415                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14416                         intel_ddi_init(dev, PORT_B);
14417                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14418                         intel_ddi_init(dev, PORT_C);
14419                 if (found & SFUSE_STRAP_DDID_DETECTED)
14420                         intel_ddi_init(dev, PORT_D);
14421                 /*
14422                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14423                  */
14424                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14425                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14426                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14427                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14428                         intel_ddi_init(dev, PORT_E);
14429
14430         } else if (HAS_PCH_SPLIT(dev)) {
14431                 int found;
14432                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14433
14434                 if (has_edp_a(dev))
14435                         intel_dp_init(dev, DP_A, PORT_A);
14436
14437                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14438                         /* PCH SDVOB multiplex with HDMIB */
14439                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14440                         if (!found)
14441                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14442                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14443                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14444                 }
14445
14446                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14447                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14448
14449                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14450                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14451
14452                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14453                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14454
14455                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14456                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14457         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14458                 /*
14459                  * The DP_DETECTED bit is the latched state of the DDC
14460                  * SDA pin at boot. However since eDP doesn't require DDC
14461                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14462                  * eDP ports may have been muxed to an alternate function.
14463                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14464                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14465                  * detect eDP ports.
14466                  */
14467                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14468                     !intel_dp_is_edp(dev, PORT_B))
14469                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14470                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14471                     intel_dp_is_edp(dev, PORT_B))
14472                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14473
14474                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14475                     !intel_dp_is_edp(dev, PORT_C))
14476                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14477                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14478                     intel_dp_is_edp(dev, PORT_C))
14479                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14480
14481                 if (IS_CHERRYVIEW(dev)) {
14482                         /* eDP not supported on port D, so don't check VBT */
14483                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14484                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14485                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14486                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14487                 }
14488
14489                 intel_dsi_init(dev);
14490         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14491                 bool found = false;
14492
14493                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14494                         DRM_DEBUG_KMS("probing SDVOB\n");
14495                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14496                         if (!found && IS_G4X(dev)) {
14497                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14498                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14499                         }
14500
14501                         if (!found && IS_G4X(dev))
14502                                 intel_dp_init(dev, DP_B, PORT_B);
14503                 }
14504
14505                 /* Before G4X SDVOC doesn't have its own detect register */
14506
14507                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14508                         DRM_DEBUG_KMS("probing SDVOC\n");
14509                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14510                 }
14511
14512                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14513
14514                         if (IS_G4X(dev)) {
14515                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14516                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14517                         }
14518                         if (IS_G4X(dev))
14519                                 intel_dp_init(dev, DP_C, PORT_C);
14520                 }
14521
14522                 if (IS_G4X(dev) &&
14523                     (I915_READ(DP_D) & DP_DETECTED))
14524                         intel_dp_init(dev, DP_D, PORT_D);
14525         } else if (IS_GEN2(dev))
14526                 intel_dvo_init(dev);
14527
14528         if (SUPPORTS_TV(dev))
14529                 intel_tv_init(dev);
14530
14531         intel_psr_init(dev);
14532
14533         for_each_intel_encoder(dev, encoder) {
14534                 encoder->base.possible_crtcs = encoder->crtc_mask;
14535                 encoder->base.possible_clones =
14536                         intel_encoder_clones(encoder);
14537         }
14538
14539         intel_init_pch_refclk(dev);
14540
14541         drm_helper_move_panel_connectors_to_head(dev);
14542 }
14543
14544 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14545 {
14546         struct drm_device *dev = fb->dev;
14547         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14548
14549         drm_framebuffer_cleanup(fb);
14550         mutex_lock(&dev->struct_mutex);
14551         WARN_ON(!intel_fb->obj->framebuffer_references--);
14552         drm_gem_object_unreference(&intel_fb->obj->base);
14553         mutex_unlock(&dev->struct_mutex);
14554         kfree(intel_fb);
14555 }
14556
14557 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14558                                                 struct drm_file *file,
14559                                                 unsigned int *handle)
14560 {
14561         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14562         struct drm_i915_gem_object *obj = intel_fb->obj;
14563
14564         if (obj->userptr.mm) {
14565                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14566                 return -EINVAL;
14567         }
14568
14569         return drm_gem_handle_create(file, &obj->base, handle);
14570 }
14571
14572 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14573                                         struct drm_file *file,
14574                                         unsigned flags, unsigned color,
14575                                         struct drm_clip_rect *clips,
14576                                         unsigned num_clips)
14577 {
14578         struct drm_device *dev = fb->dev;
14579         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14580         struct drm_i915_gem_object *obj = intel_fb->obj;
14581
14582         mutex_lock(&dev->struct_mutex);
14583         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14584         mutex_unlock(&dev->struct_mutex);
14585
14586         return 0;
14587 }
14588
14589 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14590         .destroy = intel_user_framebuffer_destroy,
14591         .create_handle = intel_user_framebuffer_create_handle,
14592         .dirty = intel_user_framebuffer_dirty,
14593 };
14594
14595 static
14596 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14597                          uint32_t pixel_format)
14598 {
14599         u32 gen = INTEL_INFO(dev)->gen;
14600
14601         if (gen >= 9) {
14602                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14603
14604                 /* "The stride in bytes must not exceed the of the size of 8K
14605                  *  pixels and 32K bytes."
14606                  */
14607                 return min(8192 * cpp, 32768);
14608         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14609                 return 32*1024;
14610         } else if (gen >= 4) {
14611                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14612                         return 16*1024;
14613                 else
14614                         return 32*1024;
14615         } else if (gen >= 3) {
14616                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14617                         return 8*1024;
14618                 else
14619                         return 16*1024;
14620         } else {
14621                 /* XXX DSPC is limited to 4k tiled */
14622                 return 8*1024;
14623         }
14624 }
14625
14626 static int intel_framebuffer_init(struct drm_device *dev,
14627                                   struct intel_framebuffer *intel_fb,
14628                                   struct drm_mode_fb_cmd2 *mode_cmd,
14629                                   struct drm_i915_gem_object *obj)
14630 {
14631         struct drm_i915_private *dev_priv = to_i915(dev);
14632         unsigned int aligned_height;
14633         int ret;
14634         u32 pitch_limit, stride_alignment;
14635
14636         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14637
14638         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14639                 /* Enforce that fb modifier and tiling mode match, but only for
14640                  * X-tiled. This is needed for FBC. */
14641                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14642                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14643                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14644                         return -EINVAL;
14645                 }
14646         } else {
14647                 if (obj->tiling_mode == I915_TILING_X)
14648                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14649                 else if (obj->tiling_mode == I915_TILING_Y) {
14650                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14651                         return -EINVAL;
14652                 }
14653         }
14654
14655         /* Passed in modifier sanity checking. */
14656         switch (mode_cmd->modifier[0]) {
14657         case I915_FORMAT_MOD_Y_TILED:
14658         case I915_FORMAT_MOD_Yf_TILED:
14659                 if (INTEL_INFO(dev)->gen < 9) {
14660                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14661                                   mode_cmd->modifier[0]);
14662                         return -EINVAL;
14663                 }
14664         case DRM_FORMAT_MOD_NONE:
14665         case I915_FORMAT_MOD_X_TILED:
14666                 break;
14667         default:
14668                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14669                           mode_cmd->modifier[0]);
14670                 return -EINVAL;
14671         }
14672
14673         stride_alignment = intel_fb_stride_alignment(dev_priv,
14674                                                      mode_cmd->modifier[0],
14675                                                      mode_cmd->pixel_format);
14676         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14677                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14678                           mode_cmd->pitches[0], stride_alignment);
14679                 return -EINVAL;
14680         }
14681
14682         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14683                                            mode_cmd->pixel_format);
14684         if (mode_cmd->pitches[0] > pitch_limit) {
14685                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14686                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14687                           "tiled" : "linear",
14688                           mode_cmd->pitches[0], pitch_limit);
14689                 return -EINVAL;
14690         }
14691
14692         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14693             mode_cmd->pitches[0] != obj->stride) {
14694                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14695                           mode_cmd->pitches[0], obj->stride);
14696                 return -EINVAL;
14697         }
14698
14699         /* Reject formats not supported by any plane early. */
14700         switch (mode_cmd->pixel_format) {
14701         case DRM_FORMAT_C8:
14702         case DRM_FORMAT_RGB565:
14703         case DRM_FORMAT_XRGB8888:
14704         case DRM_FORMAT_ARGB8888:
14705                 break;
14706         case DRM_FORMAT_XRGB1555:
14707                 if (INTEL_INFO(dev)->gen > 3) {
14708                         DRM_DEBUG("unsupported pixel format: %s\n",
14709                                   drm_get_format_name(mode_cmd->pixel_format));
14710                         return -EINVAL;
14711                 }
14712                 break;
14713         case DRM_FORMAT_ABGR8888:
14714                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14715                     INTEL_INFO(dev)->gen < 9) {
14716                         DRM_DEBUG("unsupported pixel format: %s\n",
14717                                   drm_get_format_name(mode_cmd->pixel_format));
14718                         return -EINVAL;
14719                 }
14720                 break;
14721         case DRM_FORMAT_XBGR8888:
14722         case DRM_FORMAT_XRGB2101010:
14723         case DRM_FORMAT_XBGR2101010:
14724                 if (INTEL_INFO(dev)->gen < 4) {
14725                         DRM_DEBUG("unsupported pixel format: %s\n",
14726                                   drm_get_format_name(mode_cmd->pixel_format));
14727                         return -EINVAL;
14728                 }
14729                 break;
14730         case DRM_FORMAT_ABGR2101010:
14731                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14732                         DRM_DEBUG("unsupported pixel format: %s\n",
14733                                   drm_get_format_name(mode_cmd->pixel_format));
14734                         return -EINVAL;
14735                 }
14736                 break;
14737         case DRM_FORMAT_YUYV:
14738         case DRM_FORMAT_UYVY:
14739         case DRM_FORMAT_YVYU:
14740         case DRM_FORMAT_VYUY:
14741                 if (INTEL_INFO(dev)->gen < 5) {
14742                         DRM_DEBUG("unsupported pixel format: %s\n",
14743                                   drm_get_format_name(mode_cmd->pixel_format));
14744                         return -EINVAL;
14745                 }
14746                 break;
14747         default:
14748                 DRM_DEBUG("unsupported pixel format: %s\n",
14749                           drm_get_format_name(mode_cmd->pixel_format));
14750                 return -EINVAL;
14751         }
14752
14753         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14754         if (mode_cmd->offsets[0] != 0)
14755                 return -EINVAL;
14756
14757         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14758                                                mode_cmd->pixel_format,
14759                                                mode_cmd->modifier[0]);
14760         /* FIXME drm helper for size checks (especially planar formats)? */
14761         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14762                 return -EINVAL;
14763
14764         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14765         intel_fb->obj = obj;
14766
14767         intel_fill_fb_info(dev_priv, &intel_fb->base);
14768
14769         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14770         if (ret) {
14771                 DRM_ERROR("framebuffer init failed %d\n", ret);
14772                 return ret;
14773         }
14774
14775         intel_fb->obj->framebuffer_references++;
14776
14777         return 0;
14778 }
14779
14780 static struct drm_framebuffer *
14781 intel_user_framebuffer_create(struct drm_device *dev,
14782                               struct drm_file *filp,
14783                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14784 {
14785         struct drm_framebuffer *fb;
14786         struct drm_i915_gem_object *obj;
14787         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14788
14789         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14790                                                 mode_cmd.handles[0]));
14791         if (&obj->base == NULL)
14792                 return ERR_PTR(-ENOENT);
14793
14794         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14795         if (IS_ERR(fb))
14796                 drm_gem_object_unreference_unlocked(&obj->base);
14797
14798         return fb;
14799 }
14800
14801 #ifndef CONFIG_DRM_FBDEV_EMULATION
14802 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14803 {
14804 }
14805 #endif
14806
14807 static const struct drm_mode_config_funcs intel_mode_funcs = {
14808         .fb_create = intel_user_framebuffer_create,
14809         .output_poll_changed = intel_fbdev_output_poll_changed,
14810         .atomic_check = intel_atomic_check,
14811         .atomic_commit = intel_atomic_commit,
14812         .atomic_state_alloc = intel_atomic_state_alloc,
14813         .atomic_state_clear = intel_atomic_state_clear,
14814 };
14815
14816 /* Set up chip specific display functions */
14817 static void intel_init_display(struct drm_device *dev)
14818 {
14819         struct drm_i915_private *dev_priv = dev->dev_private;
14820
14821         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14822                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14823         else if (IS_CHERRYVIEW(dev))
14824                 dev_priv->display.find_dpll = chv_find_best_dpll;
14825         else if (IS_VALLEYVIEW(dev))
14826                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14827         else if (IS_PINEVIEW(dev))
14828                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14829         else
14830                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14831
14832         if (INTEL_INFO(dev)->gen >= 9) {
14833                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14834                 dev_priv->display.get_initial_plane_config =
14835                         skylake_get_initial_plane_config;
14836                 dev_priv->display.crtc_compute_clock =
14837                         haswell_crtc_compute_clock;
14838                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14839                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14840         } else if (HAS_DDI(dev)) {
14841                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14842                 dev_priv->display.get_initial_plane_config =
14843                         ironlake_get_initial_plane_config;
14844                 dev_priv->display.crtc_compute_clock =
14845                         haswell_crtc_compute_clock;
14846                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14847                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14848         } else if (HAS_PCH_SPLIT(dev)) {
14849                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14850                 dev_priv->display.get_initial_plane_config =
14851                         ironlake_get_initial_plane_config;
14852                 dev_priv->display.crtc_compute_clock =
14853                         ironlake_crtc_compute_clock;
14854                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14855                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14856         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14857                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14858                 dev_priv->display.get_initial_plane_config =
14859                         i9xx_get_initial_plane_config;
14860                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14861                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14862                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14863         } else {
14864                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14865                 dev_priv->display.get_initial_plane_config =
14866                         i9xx_get_initial_plane_config;
14867                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14868                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14869                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14870         }
14871
14872         /* Returns the core display clock speed */
14873         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14874                 dev_priv->display.get_display_clock_speed =
14875                         skylake_get_display_clock_speed;
14876         else if (IS_BROXTON(dev))
14877                 dev_priv->display.get_display_clock_speed =
14878                         broxton_get_display_clock_speed;
14879         else if (IS_BROADWELL(dev))
14880                 dev_priv->display.get_display_clock_speed =
14881                         broadwell_get_display_clock_speed;
14882         else if (IS_HASWELL(dev))
14883                 dev_priv->display.get_display_clock_speed =
14884                         haswell_get_display_clock_speed;
14885         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14886                 dev_priv->display.get_display_clock_speed =
14887                         valleyview_get_display_clock_speed;
14888         else if (IS_GEN5(dev))
14889                 dev_priv->display.get_display_clock_speed =
14890                         ilk_get_display_clock_speed;
14891         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14892                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14893                 dev_priv->display.get_display_clock_speed =
14894                         i945_get_display_clock_speed;
14895         else if (IS_GM45(dev))
14896                 dev_priv->display.get_display_clock_speed =
14897                         gm45_get_display_clock_speed;
14898         else if (IS_CRESTLINE(dev))
14899                 dev_priv->display.get_display_clock_speed =
14900                         i965gm_get_display_clock_speed;
14901         else if (IS_PINEVIEW(dev))
14902                 dev_priv->display.get_display_clock_speed =
14903                         pnv_get_display_clock_speed;
14904         else if (IS_G33(dev) || IS_G4X(dev))
14905                 dev_priv->display.get_display_clock_speed =
14906                         g33_get_display_clock_speed;
14907         else if (IS_I915G(dev))
14908                 dev_priv->display.get_display_clock_speed =
14909                         i915_get_display_clock_speed;
14910         else if (IS_I945GM(dev) || IS_845G(dev))
14911                 dev_priv->display.get_display_clock_speed =
14912                         i9xx_misc_get_display_clock_speed;
14913         else if (IS_I915GM(dev))
14914                 dev_priv->display.get_display_clock_speed =
14915                         i915gm_get_display_clock_speed;
14916         else if (IS_I865G(dev))
14917                 dev_priv->display.get_display_clock_speed =
14918                         i865_get_display_clock_speed;
14919         else if (IS_I85X(dev))
14920                 dev_priv->display.get_display_clock_speed =
14921                         i85x_get_display_clock_speed;
14922         else { /* 830 */
14923                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14924                 dev_priv->display.get_display_clock_speed =
14925                         i830_get_display_clock_speed;
14926         }
14927
14928         if (IS_GEN5(dev)) {
14929                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14930         } else if (IS_GEN6(dev)) {
14931                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14932         } else if (IS_IVYBRIDGE(dev)) {
14933                 /* FIXME: detect B0+ stepping and use auto training */
14934                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14935         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14936                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14937                 if (IS_BROADWELL(dev)) {
14938                         dev_priv->display.modeset_commit_cdclk =
14939                                 broadwell_modeset_commit_cdclk;
14940                         dev_priv->display.modeset_calc_cdclk =
14941                                 broadwell_modeset_calc_cdclk;
14942                 }
14943         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14944                 dev_priv->display.modeset_commit_cdclk =
14945                         valleyview_modeset_commit_cdclk;
14946                 dev_priv->display.modeset_calc_cdclk =
14947                         valleyview_modeset_calc_cdclk;
14948         } else if (IS_BROXTON(dev)) {
14949                 dev_priv->display.modeset_commit_cdclk =
14950                         broxton_modeset_commit_cdclk;
14951                 dev_priv->display.modeset_calc_cdclk =
14952                         broxton_modeset_calc_cdclk;
14953         }
14954
14955         switch (INTEL_INFO(dev)->gen) {
14956         case 2:
14957                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14958                 break;
14959
14960         case 3:
14961                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14962                 break;
14963
14964         case 4:
14965         case 5:
14966                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14967                 break;
14968
14969         case 6:
14970                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14971                 break;
14972         case 7:
14973         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14974                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14975                 break;
14976         case 9:
14977                 /* Drop through - unsupported since execlist only. */
14978         default:
14979                 /* Default just returns -ENODEV to indicate unsupported */
14980                 dev_priv->display.queue_flip = intel_default_queue_flip;
14981         }
14982
14983         mutex_init(&dev_priv->pps_mutex);
14984 }
14985
14986 /*
14987  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14988  * resume, or other times.  This quirk makes sure that's the case for
14989  * affected systems.
14990  */
14991 static void quirk_pipea_force(struct drm_device *dev)
14992 {
14993         struct drm_i915_private *dev_priv = dev->dev_private;
14994
14995         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14996         DRM_INFO("applying pipe a force quirk\n");
14997 }
14998
14999 static void quirk_pipeb_force(struct drm_device *dev)
15000 {
15001         struct drm_i915_private *dev_priv = dev->dev_private;
15002
15003         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15004         DRM_INFO("applying pipe b force quirk\n");
15005 }
15006
15007 /*
15008  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15009  */
15010 static void quirk_ssc_force_disable(struct drm_device *dev)
15011 {
15012         struct drm_i915_private *dev_priv = dev->dev_private;
15013         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15014         DRM_INFO("applying lvds SSC disable quirk\n");
15015 }
15016
15017 /*
15018  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15019  * brightness value
15020  */
15021 static void quirk_invert_brightness(struct drm_device *dev)
15022 {
15023         struct drm_i915_private *dev_priv = dev->dev_private;
15024         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15025         DRM_INFO("applying inverted panel brightness quirk\n");
15026 }
15027
15028 /* Some VBT's incorrectly indicate no backlight is present */
15029 static void quirk_backlight_present(struct drm_device *dev)
15030 {
15031         struct drm_i915_private *dev_priv = dev->dev_private;
15032         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15033         DRM_INFO("applying backlight present quirk\n");
15034 }
15035
15036 struct intel_quirk {
15037         int device;
15038         int subsystem_vendor;
15039         int subsystem_device;
15040         void (*hook)(struct drm_device *dev);
15041 };
15042
15043 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15044 struct intel_dmi_quirk {
15045         void (*hook)(struct drm_device *dev);
15046         const struct dmi_system_id (*dmi_id_list)[];
15047 };
15048
15049 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15050 {
15051         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15052         return 1;
15053 }
15054
15055 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15056         {
15057                 .dmi_id_list = &(const struct dmi_system_id[]) {
15058                         {
15059                                 .callback = intel_dmi_reverse_brightness,
15060                                 .ident = "NCR Corporation",
15061                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15062                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15063                                 },
15064                         },
15065                         { }  /* terminating entry */
15066                 },
15067                 .hook = quirk_invert_brightness,
15068         },
15069 };
15070
15071 static struct intel_quirk intel_quirks[] = {
15072         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15073         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15074
15075         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15076         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15077
15078         /* 830 needs to leave pipe A & dpll A up */
15079         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15080
15081         /* 830 needs to leave pipe B & dpll B up */
15082         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15083
15084         /* Lenovo U160 cannot use SSC on LVDS */
15085         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15086
15087         /* Sony Vaio Y cannot use SSC on LVDS */
15088         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15089
15090         /* Acer Aspire 5734Z must invert backlight brightness */
15091         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15092
15093         /* Acer/eMachines G725 */
15094         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15095
15096         /* Acer/eMachines e725 */
15097         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15098
15099         /* Acer/Packard Bell NCL20 */
15100         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15101
15102         /* Acer Aspire 4736Z */
15103         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15104
15105         /* Acer Aspire 5336 */
15106         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15107
15108         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15109         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15110
15111         /* Acer C720 Chromebook (Core i3 4005U) */
15112         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15113
15114         /* Apple Macbook 2,1 (Core 2 T7400) */
15115         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15116
15117         /* Apple Macbook 4,1 */
15118         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15119
15120         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15121         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15122
15123         /* HP Chromebook 14 (Celeron 2955U) */
15124         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15125
15126         /* Dell Chromebook 11 */
15127         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15128
15129         /* Dell Chromebook 11 (2015 version) */
15130         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15131 };
15132
15133 static void intel_init_quirks(struct drm_device *dev)
15134 {
15135         struct pci_dev *d = dev->pdev;
15136         int i;
15137
15138         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15139                 struct intel_quirk *q = &intel_quirks[i];
15140
15141                 if (d->device == q->device &&
15142                     (d->subsystem_vendor == q->subsystem_vendor ||
15143                      q->subsystem_vendor == PCI_ANY_ID) &&
15144                     (d->subsystem_device == q->subsystem_device ||
15145                      q->subsystem_device == PCI_ANY_ID))
15146                         q->hook(dev);
15147         }
15148         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15149                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15150                         intel_dmi_quirks[i].hook(dev);
15151         }
15152 }
15153
15154 /* Disable the VGA plane that we never use */
15155 static void i915_disable_vga(struct drm_device *dev)
15156 {
15157         struct drm_i915_private *dev_priv = dev->dev_private;
15158         u8 sr1;
15159         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15160
15161         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15162         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15163         outb(SR01, VGA_SR_INDEX);
15164         sr1 = inb(VGA_SR_DATA);
15165         outb(sr1 | 1<<5, VGA_SR_DATA);
15166         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15167         udelay(300);
15168
15169         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15170         POSTING_READ(vga_reg);
15171 }
15172
15173 void intel_modeset_init_hw(struct drm_device *dev)
15174 {
15175         struct drm_i915_private *dev_priv = dev->dev_private;
15176
15177         intel_update_cdclk(dev);
15178
15179         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15180
15181         intel_init_clock_gating(dev);
15182         intel_enable_gt_powersave(dev);
15183 }
15184
15185 /*
15186  * Calculate what we think the watermarks should be for the state we've read
15187  * out of the hardware and then immediately program those watermarks so that
15188  * we ensure the hardware settings match our internal state.
15189  *
15190  * We can calculate what we think WM's should be by creating a duplicate of the
15191  * current state (which was constructed during hardware readout) and running it
15192  * through the atomic check code to calculate new watermark values in the
15193  * state object.
15194  */
15195 static void sanitize_watermarks(struct drm_device *dev)
15196 {
15197         struct drm_i915_private *dev_priv = to_i915(dev);
15198         struct drm_atomic_state *state;
15199         struct drm_crtc *crtc;
15200         struct drm_crtc_state *cstate;
15201         struct drm_modeset_acquire_ctx ctx;
15202         int ret;
15203         int i;
15204
15205         /* Only supported on platforms that use atomic watermark design */
15206         if (!dev_priv->display.optimize_watermarks)
15207                 return;
15208
15209         /*
15210          * We need to hold connection_mutex before calling duplicate_state so
15211          * that the connector loop is protected.
15212          */
15213         drm_modeset_acquire_init(&ctx, 0);
15214 retry:
15215         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15216         if (ret == -EDEADLK) {
15217                 drm_modeset_backoff(&ctx);
15218                 goto retry;
15219         } else if (WARN_ON(ret)) {
15220                 goto fail;
15221         }
15222
15223         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15224         if (WARN_ON(IS_ERR(state)))
15225                 goto fail;
15226
15227         /*
15228          * Hardware readout is the only time we don't want to calculate
15229          * intermediate watermarks (since we don't trust the current
15230          * watermarks).
15231          */
15232         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15233
15234         ret = intel_atomic_check(dev, state);
15235         if (ret) {
15236                 /*
15237                  * If we fail here, it means that the hardware appears to be
15238                  * programmed in a way that shouldn't be possible, given our
15239                  * understanding of watermark requirements.  This might mean a
15240                  * mistake in the hardware readout code or a mistake in the
15241                  * watermark calculations for a given platform.  Raise a WARN
15242                  * so that this is noticeable.
15243                  *
15244                  * If this actually happens, we'll have to just leave the
15245                  * BIOS-programmed watermarks untouched and hope for the best.
15246                  */
15247                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15248                 goto fail;
15249         }
15250
15251         /* Write calculated watermark values back */
15252         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15253         for_each_crtc_in_state(state, crtc, cstate, i) {
15254                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15255
15256                 cs->wm.need_postvbl_update = true;
15257                 dev_priv->display.optimize_watermarks(cs);
15258         }
15259
15260         drm_atomic_state_free(state);
15261 fail:
15262         drm_modeset_drop_locks(&ctx);
15263         drm_modeset_acquire_fini(&ctx);
15264 }
15265
15266 void intel_modeset_init(struct drm_device *dev)
15267 {
15268         struct drm_i915_private *dev_priv = dev->dev_private;
15269         int sprite, ret;
15270         enum pipe pipe;
15271         struct intel_crtc *crtc;
15272
15273         drm_mode_config_init(dev);
15274
15275         dev->mode_config.min_width = 0;
15276         dev->mode_config.min_height = 0;
15277
15278         dev->mode_config.preferred_depth = 24;
15279         dev->mode_config.prefer_shadow = 1;
15280
15281         dev->mode_config.allow_fb_modifiers = true;
15282
15283         dev->mode_config.funcs = &intel_mode_funcs;
15284
15285         intel_init_quirks(dev);
15286
15287         intel_init_pm(dev);
15288
15289         if (INTEL_INFO(dev)->num_pipes == 0)
15290                 return;
15291
15292         /*
15293          * There may be no VBT; and if the BIOS enabled SSC we can
15294          * just keep using it to avoid unnecessary flicker.  Whereas if the
15295          * BIOS isn't using it, don't assume it will work even if the VBT
15296          * indicates as much.
15297          */
15298         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15299                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15300                                             DREF_SSC1_ENABLE);
15301
15302                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15303                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15304                                      bios_lvds_use_ssc ? "en" : "dis",
15305                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15306                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15307                 }
15308         }
15309
15310         intel_init_display(dev);
15311         intel_init_audio(dev);
15312
15313         if (IS_GEN2(dev)) {
15314                 dev->mode_config.max_width = 2048;
15315                 dev->mode_config.max_height = 2048;
15316         } else if (IS_GEN3(dev)) {
15317                 dev->mode_config.max_width = 4096;
15318                 dev->mode_config.max_height = 4096;
15319         } else {
15320                 dev->mode_config.max_width = 8192;
15321                 dev->mode_config.max_height = 8192;
15322         }
15323
15324         if (IS_845G(dev) || IS_I865G(dev)) {
15325                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15326                 dev->mode_config.cursor_height = 1023;
15327         } else if (IS_GEN2(dev)) {
15328                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15329                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15330         } else {
15331                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15332                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15333         }
15334
15335         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15336
15337         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15338                       INTEL_INFO(dev)->num_pipes,
15339                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15340
15341         for_each_pipe(dev_priv, pipe) {
15342                 intel_crtc_init(dev, pipe);
15343                 for_each_sprite(dev_priv, pipe, sprite) {
15344                         ret = intel_plane_init(dev, pipe, sprite);
15345                         if (ret)
15346                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15347                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15348                 }
15349         }
15350
15351         intel_update_czclk(dev_priv);
15352         intel_update_rawclk(dev_priv);
15353         intel_update_cdclk(dev);
15354
15355         intel_shared_dpll_init(dev);
15356
15357         /* Just disable it once at startup */
15358         i915_disable_vga(dev);
15359         intel_setup_outputs(dev);
15360
15361         drm_modeset_lock_all(dev);
15362         intel_modeset_setup_hw_state(dev);
15363         drm_modeset_unlock_all(dev);
15364
15365         for_each_intel_crtc(dev, crtc) {
15366                 struct intel_initial_plane_config plane_config = {};
15367
15368                 if (!crtc->active)
15369                         continue;
15370
15371                 /*
15372                  * Note that reserving the BIOS fb up front prevents us
15373                  * from stuffing other stolen allocations like the ring
15374                  * on top.  This prevents some ugliness at boot time, and
15375                  * can even allow for smooth boot transitions if the BIOS
15376                  * fb is large enough for the active pipe configuration.
15377                  */
15378                 dev_priv->display.get_initial_plane_config(crtc,
15379                                                            &plane_config);
15380
15381                 /*
15382                  * If the fb is shared between multiple heads, we'll
15383                  * just get the first one.
15384                  */
15385                 intel_find_initial_plane_obj(crtc, &plane_config);
15386         }
15387
15388         /*
15389          * Make sure hardware watermarks really match the state we read out.
15390          * Note that we need to do this after reconstructing the BIOS fb's
15391          * since the watermark calculation done here will use pstate->fb.
15392          */
15393         sanitize_watermarks(dev);
15394 }
15395
15396 static void intel_enable_pipe_a(struct drm_device *dev)
15397 {
15398         struct intel_connector *connector;
15399         struct drm_connector *crt = NULL;
15400         struct intel_load_detect_pipe load_detect_temp;
15401         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15402
15403         /* We can't just switch on the pipe A, we need to set things up with a
15404          * proper mode and output configuration. As a gross hack, enable pipe A
15405          * by enabling the load detect pipe once. */
15406         for_each_intel_connector(dev, connector) {
15407                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15408                         crt = &connector->base;
15409                         break;
15410                 }
15411         }
15412
15413         if (!crt)
15414                 return;
15415
15416         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15417                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15418 }
15419
15420 static bool
15421 intel_check_plane_mapping(struct intel_crtc *crtc)
15422 {
15423         struct drm_device *dev = crtc->base.dev;
15424         struct drm_i915_private *dev_priv = dev->dev_private;
15425         u32 val;
15426
15427         if (INTEL_INFO(dev)->num_pipes == 1)
15428                 return true;
15429
15430         val = I915_READ(DSPCNTR(!crtc->plane));
15431
15432         if ((val & DISPLAY_PLANE_ENABLE) &&
15433             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15434                 return false;
15435
15436         return true;
15437 }
15438
15439 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15440 {
15441         struct drm_device *dev = crtc->base.dev;
15442         struct intel_encoder *encoder;
15443
15444         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15445                 return true;
15446
15447         return false;
15448 }
15449
15450 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15451 {
15452         struct drm_device *dev = encoder->base.dev;
15453         struct intel_connector *connector;
15454
15455         for_each_connector_on_encoder(dev, &encoder->base, connector)
15456                 return true;
15457
15458         return false;
15459 }
15460
15461 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15462 {
15463         struct drm_device *dev = crtc->base.dev;
15464         struct drm_i915_private *dev_priv = dev->dev_private;
15465         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15466
15467         /* Clear any frame start delays used for debugging left by the BIOS */
15468         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15469
15470         /* restore vblank interrupts to correct state */
15471         drm_crtc_vblank_reset(&crtc->base);
15472         if (crtc->active) {
15473                 struct intel_plane *plane;
15474
15475                 drm_crtc_vblank_on(&crtc->base);
15476
15477                 /* Disable everything but the primary plane */
15478                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15479                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15480                                 continue;
15481
15482                         plane->disable_plane(&plane->base, &crtc->base);
15483                 }
15484         }
15485
15486         /* We need to sanitize the plane -> pipe mapping first because this will
15487          * disable the crtc (and hence change the state) if it is wrong. Note
15488          * that gen4+ has a fixed plane -> pipe mapping.  */
15489         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15490                 bool plane;
15491
15492                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15493                               crtc->base.base.id);
15494
15495                 /* Pipe has the wrong plane attached and the plane is active.
15496                  * Temporarily change the plane mapping and disable everything
15497                  * ...  */
15498                 plane = crtc->plane;
15499                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15500                 crtc->plane = !plane;
15501                 intel_crtc_disable_noatomic(&crtc->base);
15502                 crtc->plane = plane;
15503         }
15504
15505         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15506             crtc->pipe == PIPE_A && !crtc->active) {
15507                 /* BIOS forgot to enable pipe A, this mostly happens after
15508                  * resume. Force-enable the pipe to fix this, the update_dpms
15509                  * call below we restore the pipe to the right state, but leave
15510                  * the required bits on. */
15511                 intel_enable_pipe_a(dev);
15512         }
15513
15514         /* Adjust the state of the output pipe according to whether we
15515          * have active connectors/encoders. */
15516         if (!intel_crtc_has_encoders(crtc))
15517                 intel_crtc_disable_noatomic(&crtc->base);
15518
15519         if (crtc->active != crtc->base.state->active) {
15520                 struct intel_encoder *encoder;
15521
15522                 /* This can happen either due to bugs in the get_hw_state
15523                  * functions or because of calls to intel_crtc_disable_noatomic,
15524                  * or because the pipe is force-enabled due to the
15525                  * pipe A quirk. */
15526                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15527                               crtc->base.base.id,
15528                               crtc->base.state->enable ? "enabled" : "disabled",
15529                               crtc->active ? "enabled" : "disabled");
15530
15531                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15532                 crtc->base.state->active = crtc->active;
15533                 crtc->base.enabled = crtc->active;
15534                 crtc->base.state->connector_mask = 0;
15535                 crtc->base.state->encoder_mask = 0;
15536
15537                 /* Because we only establish the connector -> encoder ->
15538                  * crtc links if something is active, this means the
15539                  * crtc is now deactivated. Break the links. connector
15540                  * -> encoder links are only establish when things are
15541                  *  actually up, hence no need to break them. */
15542                 WARN_ON(crtc->active);
15543
15544                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15545                         encoder->base.crtc = NULL;
15546         }
15547
15548         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15549                 /*
15550                  * We start out with underrun reporting disabled to avoid races.
15551                  * For correct bookkeeping mark this on active crtcs.
15552                  *
15553                  * Also on gmch platforms we dont have any hardware bits to
15554                  * disable the underrun reporting. Which means we need to start
15555                  * out with underrun reporting disabled also on inactive pipes,
15556                  * since otherwise we'll complain about the garbage we read when
15557                  * e.g. coming up after runtime pm.
15558                  *
15559                  * No protection against concurrent access is required - at
15560                  * worst a fifo underrun happens which also sets this to false.
15561                  */
15562                 crtc->cpu_fifo_underrun_disabled = true;
15563                 crtc->pch_fifo_underrun_disabled = true;
15564         }
15565 }
15566
15567 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15568 {
15569         struct intel_connector *connector;
15570         struct drm_device *dev = encoder->base.dev;
15571
15572         /* We need to check both for a crtc link (meaning that the
15573          * encoder is active and trying to read from a pipe) and the
15574          * pipe itself being active. */
15575         bool has_active_crtc = encoder->base.crtc &&
15576                 to_intel_crtc(encoder->base.crtc)->active;
15577
15578         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15579                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15580                               encoder->base.base.id,
15581                               encoder->base.name);
15582
15583                 /* Connector is active, but has no active pipe. This is
15584                  * fallout from our resume register restoring. Disable
15585                  * the encoder manually again. */
15586                 if (encoder->base.crtc) {
15587                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15588                                       encoder->base.base.id,
15589                                       encoder->base.name);
15590                         encoder->disable(encoder);
15591                         if (encoder->post_disable)
15592                                 encoder->post_disable(encoder);
15593                 }
15594                 encoder->base.crtc = NULL;
15595
15596                 /* Inconsistent output/port/pipe state happens presumably due to
15597                  * a bug in one of the get_hw_state functions. Or someplace else
15598                  * in our code, like the register restore mess on resume. Clamp
15599                  * things to off as a safer default. */
15600                 for_each_intel_connector(dev, connector) {
15601                         if (connector->encoder != encoder)
15602                                 continue;
15603                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15604                         connector->base.encoder = NULL;
15605                 }
15606         }
15607         /* Enabled encoders without active connectors will be fixed in
15608          * the crtc fixup. */
15609 }
15610
15611 void i915_redisable_vga_power_on(struct drm_device *dev)
15612 {
15613         struct drm_i915_private *dev_priv = dev->dev_private;
15614         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15615
15616         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15617                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15618                 i915_disable_vga(dev);
15619         }
15620 }
15621
15622 void i915_redisable_vga(struct drm_device *dev)
15623 {
15624         struct drm_i915_private *dev_priv = dev->dev_private;
15625
15626         /* This function can be called both from intel_modeset_setup_hw_state or
15627          * at a very early point in our resume sequence, where the power well
15628          * structures are not yet restored. Since this function is at a very
15629          * paranoid "someone might have enabled VGA while we were not looking"
15630          * level, just check if the power well is enabled instead of trying to
15631          * follow the "don't touch the power well if we don't need it" policy
15632          * the rest of the driver uses. */
15633         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15634                 return;
15635
15636         i915_redisable_vga_power_on(dev);
15637
15638         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15639 }
15640
15641 static bool primary_get_hw_state(struct intel_plane *plane)
15642 {
15643         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15644
15645         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15646 }
15647
15648 /* FIXME read out full plane state for all planes */
15649 static void readout_plane_state(struct intel_crtc *crtc)
15650 {
15651         struct drm_plane *primary = crtc->base.primary;
15652         struct intel_plane_state *plane_state =
15653                 to_intel_plane_state(primary->state);
15654
15655         plane_state->visible = crtc->active &&
15656                 primary_get_hw_state(to_intel_plane(primary));
15657
15658         if (plane_state->visible)
15659                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15660 }
15661
15662 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15663 {
15664         struct drm_i915_private *dev_priv = dev->dev_private;
15665         enum pipe pipe;
15666         struct intel_crtc *crtc;
15667         struct intel_encoder *encoder;
15668         struct intel_connector *connector;
15669         int i;
15670
15671         dev_priv->active_crtcs = 0;
15672
15673         for_each_intel_crtc(dev, crtc) {
15674                 struct intel_crtc_state *crtc_state = crtc->config;
15675                 int pixclk = 0;
15676
15677                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15678                 memset(crtc_state, 0, sizeof(*crtc_state));
15679                 crtc_state->base.crtc = &crtc->base;
15680
15681                 crtc_state->base.active = crtc_state->base.enable =
15682                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15683
15684                 crtc->base.enabled = crtc_state->base.enable;
15685                 crtc->active = crtc_state->base.active;
15686
15687                 if (crtc_state->base.active) {
15688                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15689
15690                         if (IS_BROADWELL(dev_priv)) {
15691                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15692
15693                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15694                                 if (crtc_state->ips_enabled)
15695                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15696                         } else if (IS_VALLEYVIEW(dev_priv) ||
15697                                    IS_CHERRYVIEW(dev_priv) ||
15698                                    IS_BROXTON(dev_priv))
15699                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15700                         else
15701                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15702                 }
15703
15704                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15705
15706                 readout_plane_state(crtc);
15707
15708                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15709                               crtc->base.base.id,
15710                               crtc->active ? "enabled" : "disabled");
15711         }
15712
15713         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15714                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15715
15716                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15717                                                   &pll->config.hw_state);
15718                 pll->active = 0;
15719                 pll->config.crtc_mask = 0;
15720                 for_each_intel_crtc(dev, crtc) {
15721                         if (crtc->active && crtc->config->shared_dpll == pll) {
15722                                 pll->active++;
15723                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15724                         }
15725                 }
15726
15727                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15728                               pll->name, pll->config.crtc_mask, pll->on);
15729
15730                 if (pll->config.crtc_mask)
15731                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15732         }
15733
15734         for_each_intel_encoder(dev, encoder) {
15735                 pipe = 0;
15736
15737                 if (encoder->get_hw_state(encoder, &pipe)) {
15738                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15739                         encoder->base.crtc = &crtc->base;
15740                         encoder->get_config(encoder, crtc->config);
15741                 } else {
15742                         encoder->base.crtc = NULL;
15743                 }
15744
15745                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15746                               encoder->base.base.id,
15747                               encoder->base.name,
15748                               encoder->base.crtc ? "enabled" : "disabled",
15749                               pipe_name(pipe));
15750         }
15751
15752         for_each_intel_connector(dev, connector) {
15753                 if (connector->get_hw_state(connector)) {
15754                         connector->base.dpms = DRM_MODE_DPMS_ON;
15755
15756                         encoder = connector->encoder;
15757                         connector->base.encoder = &encoder->base;
15758
15759                         if (encoder->base.crtc &&
15760                             encoder->base.crtc->state->active) {
15761                                 /*
15762                                  * This has to be done during hardware readout
15763                                  * because anything calling .crtc_disable may
15764                                  * rely on the connector_mask being accurate.
15765                                  */
15766                                 encoder->base.crtc->state->connector_mask |=
15767                                         1 << drm_connector_index(&connector->base);
15768                                 encoder->base.crtc->state->encoder_mask |=
15769                                         1 << drm_encoder_index(&encoder->base);
15770                         }
15771
15772                 } else {
15773                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15774                         connector->base.encoder = NULL;
15775                 }
15776                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15777                               connector->base.base.id,
15778                               connector->base.name,
15779                               connector->base.encoder ? "enabled" : "disabled");
15780         }
15781
15782         for_each_intel_crtc(dev, crtc) {
15783                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15784
15785                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15786                 if (crtc->base.state->active) {
15787                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15788                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15789                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15790
15791                         /*
15792                          * The initial mode needs to be set in order to keep
15793                          * the atomic core happy. It wants a valid mode if the
15794                          * crtc's enabled, so we do the above call.
15795                          *
15796                          * At this point some state updated by the connectors
15797                          * in their ->detect() callback has not run yet, so
15798                          * no recalculation can be done yet.
15799                          *
15800                          * Even if we could do a recalculation and modeset
15801                          * right now it would cause a double modeset if
15802                          * fbdev or userspace chooses a different initial mode.
15803                          *
15804                          * If that happens, someone indicated they wanted a
15805                          * mode change, which means it's safe to do a full
15806                          * recalculation.
15807                          */
15808                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15809
15810                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15811                         update_scanline_offset(crtc);
15812                 }
15813
15814                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15815         }
15816 }
15817
15818 /* Scan out the current hw modeset state,
15819  * and sanitizes it to the current state
15820  */
15821 static void
15822 intel_modeset_setup_hw_state(struct drm_device *dev)
15823 {
15824         struct drm_i915_private *dev_priv = dev->dev_private;
15825         enum pipe pipe;
15826         struct intel_crtc *crtc;
15827         struct intel_encoder *encoder;
15828         int i;
15829
15830         intel_modeset_readout_hw_state(dev);
15831
15832         /* HW state is read out, now we need to sanitize this mess. */
15833         for_each_intel_encoder(dev, encoder) {
15834                 intel_sanitize_encoder(encoder);
15835         }
15836
15837         for_each_pipe(dev_priv, pipe) {
15838                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15839                 intel_sanitize_crtc(crtc);
15840                 intel_dump_pipe_config(crtc, crtc->config,
15841                                        "[setup_hw_state]");
15842         }
15843
15844         intel_modeset_update_connector_atomic_state(dev);
15845
15846         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15847                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15848
15849                 if (!pll->on || pll->active)
15850                         continue;
15851
15852                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15853
15854                 pll->funcs.disable(dev_priv, pll);
15855                 pll->on = false;
15856         }
15857
15858         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15859                 vlv_wm_get_hw_state(dev);
15860         else if (IS_GEN9(dev))
15861                 skl_wm_get_hw_state(dev);
15862         else if (HAS_PCH_SPLIT(dev))
15863                 ilk_wm_get_hw_state(dev);
15864
15865         for_each_intel_crtc(dev, crtc) {
15866                 unsigned long put_domains;
15867
15868                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15869                 if (WARN_ON(put_domains))
15870                         modeset_put_power_domains(dev_priv, put_domains);
15871         }
15872         intel_display_set_init_power(dev_priv, false);
15873
15874         intel_fbc_init_pipe_state(dev_priv);
15875 }
15876
15877 void intel_display_resume(struct drm_device *dev)
15878 {
15879         struct drm_i915_private *dev_priv = to_i915(dev);
15880         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15881         struct drm_modeset_acquire_ctx ctx;
15882         int ret;
15883         bool setup = false;
15884
15885         dev_priv->modeset_restore_state = NULL;
15886
15887         /*
15888          * This is a cludge because with real atomic modeset mode_config.mutex
15889          * won't be taken. Unfortunately some probed state like
15890          * audio_codec_enable is still protected by mode_config.mutex, so lock
15891          * it here for now.
15892          */
15893         mutex_lock(&dev->mode_config.mutex);
15894         drm_modeset_acquire_init(&ctx, 0);
15895
15896 retry:
15897         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15898
15899         if (ret == 0 && !setup) {
15900                 setup = true;
15901
15902                 intel_modeset_setup_hw_state(dev);
15903                 i915_redisable_vga(dev);
15904         }
15905
15906         if (ret == 0 && state) {
15907                 struct drm_crtc_state *crtc_state;
15908                 struct drm_crtc *crtc;
15909                 int i;
15910
15911                 state->acquire_ctx = &ctx;
15912
15913                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15914                         /*
15915                          * Force recalculation even if we restore
15916                          * current state. With fast modeset this may not result
15917                          * in a modeset when the state is compatible.
15918                          */
15919                         crtc_state->mode_changed = true;
15920                 }
15921
15922                 ret = drm_atomic_commit(state);
15923         }
15924
15925         if (ret == -EDEADLK) {
15926                 drm_modeset_backoff(&ctx);
15927                 goto retry;
15928         }
15929
15930         drm_modeset_drop_locks(&ctx);
15931         drm_modeset_acquire_fini(&ctx);
15932         mutex_unlock(&dev->mode_config.mutex);
15933
15934         if (ret) {
15935                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15936                 drm_atomic_state_free(state);
15937         }
15938 }
15939
15940 void intel_modeset_gem_init(struct drm_device *dev)
15941 {
15942         struct drm_crtc *c;
15943         struct drm_i915_gem_object *obj;
15944         int ret;
15945
15946         intel_init_gt_powersave(dev);
15947
15948         intel_modeset_init_hw(dev);
15949
15950         intel_setup_overlay(dev);
15951
15952         /*
15953          * Make sure any fbs we allocated at startup are properly
15954          * pinned & fenced.  When we do the allocation it's too early
15955          * for this.
15956          */
15957         for_each_crtc(dev, c) {
15958                 obj = intel_fb_obj(c->primary->fb);
15959                 if (obj == NULL)
15960                         continue;
15961
15962                 mutex_lock(&dev->struct_mutex);
15963                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15964                                                  c->primary->state->rotation);
15965                 mutex_unlock(&dev->struct_mutex);
15966                 if (ret) {
15967                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15968                                   to_intel_crtc(c)->pipe);
15969                         drm_framebuffer_unreference(c->primary->fb);
15970                         c->primary->fb = NULL;
15971                         c->primary->crtc = c->primary->state->crtc = NULL;
15972                         update_state_fb(c->primary);
15973                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15974                 }
15975         }
15976
15977         intel_backlight_register(dev);
15978 }
15979
15980 void intel_connector_unregister(struct intel_connector *intel_connector)
15981 {
15982         struct drm_connector *connector = &intel_connector->base;
15983
15984         intel_panel_destroy_backlight(connector);
15985         drm_connector_unregister(connector);
15986 }
15987
15988 void intel_modeset_cleanup(struct drm_device *dev)
15989 {
15990         struct drm_i915_private *dev_priv = dev->dev_private;
15991         struct intel_connector *connector;
15992
15993         intel_disable_gt_powersave(dev);
15994
15995         intel_backlight_unregister(dev);
15996
15997         /*
15998          * Interrupts and polling as the first thing to avoid creating havoc.
15999          * Too much stuff here (turning of connectors, ...) would
16000          * experience fancy races otherwise.
16001          */
16002         intel_irq_uninstall(dev_priv);
16003
16004         /*
16005          * Due to the hpd irq storm handling the hotplug work can re-arm the
16006          * poll handlers. Hence disable polling after hpd handling is shut down.
16007          */
16008         drm_kms_helper_poll_fini(dev);
16009
16010         intel_unregister_dsm_handler();
16011
16012         intel_fbc_global_disable(dev_priv);
16013
16014         /* flush any delayed tasks or pending work */
16015         flush_scheduled_work();
16016
16017         /* destroy the backlight and sysfs files before encoders/connectors */
16018         for_each_intel_connector(dev, connector)
16019                 connector->unregister(connector);
16020
16021         drm_mode_config_cleanup(dev);
16022
16023         intel_cleanup_overlay(dev);
16024
16025         intel_cleanup_gt_powersave(dev);
16026
16027         intel_teardown_gmbus(dev);
16028 }
16029
16030 /*
16031  * Return which encoder is currently attached for connector.
16032  */
16033 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16034 {
16035         return &intel_attached_encoder(connector)->base;
16036 }
16037
16038 void intel_connector_attach_encoder(struct intel_connector *connector,
16039                                     struct intel_encoder *encoder)
16040 {
16041         connector->encoder = encoder;
16042         drm_mode_connector_attach_encoder(&connector->base,
16043                                           &encoder->base);
16044 }
16045
16046 /*
16047  * set vga decode state - true == enable VGA decode
16048  */
16049 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16050 {
16051         struct drm_i915_private *dev_priv = dev->dev_private;
16052         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16053         u16 gmch_ctrl;
16054
16055         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16056                 DRM_ERROR("failed to read control word\n");
16057                 return -EIO;
16058         }
16059
16060         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16061                 return 0;
16062
16063         if (state)
16064                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16065         else
16066                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16067
16068         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16069                 DRM_ERROR("failed to write control word\n");
16070                 return -EIO;
16071         }
16072
16073         return 0;
16074 }
16075
16076 struct intel_display_error_state {
16077
16078         u32 power_well_driver;
16079
16080         int num_transcoders;
16081
16082         struct intel_cursor_error_state {
16083                 u32 control;
16084                 u32 position;
16085                 u32 base;
16086                 u32 size;
16087         } cursor[I915_MAX_PIPES];
16088
16089         struct intel_pipe_error_state {
16090                 bool power_domain_on;
16091                 u32 source;
16092                 u32 stat;
16093         } pipe[I915_MAX_PIPES];
16094
16095         struct intel_plane_error_state {
16096                 u32 control;
16097                 u32 stride;
16098                 u32 size;
16099                 u32 pos;
16100                 u32 addr;
16101                 u32 surface;
16102                 u32 tile_offset;
16103         } plane[I915_MAX_PIPES];
16104
16105         struct intel_transcoder_error_state {
16106                 bool power_domain_on;
16107                 enum transcoder cpu_transcoder;
16108
16109                 u32 conf;
16110
16111                 u32 htotal;
16112                 u32 hblank;
16113                 u32 hsync;
16114                 u32 vtotal;
16115                 u32 vblank;
16116                 u32 vsync;
16117         } transcoder[4];
16118 };
16119
16120 struct intel_display_error_state *
16121 intel_display_capture_error_state(struct drm_device *dev)
16122 {
16123         struct drm_i915_private *dev_priv = dev->dev_private;
16124         struct intel_display_error_state *error;
16125         int transcoders[] = {
16126                 TRANSCODER_A,
16127                 TRANSCODER_B,
16128                 TRANSCODER_C,
16129                 TRANSCODER_EDP,
16130         };
16131         int i;
16132
16133         if (INTEL_INFO(dev)->num_pipes == 0)
16134                 return NULL;
16135
16136         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16137         if (error == NULL)
16138                 return NULL;
16139
16140         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16141                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16142
16143         for_each_pipe(dev_priv, i) {
16144                 error->pipe[i].power_domain_on =
16145                         __intel_display_power_is_enabled(dev_priv,
16146                                                          POWER_DOMAIN_PIPE(i));
16147                 if (!error->pipe[i].power_domain_on)
16148                         continue;
16149
16150                 error->cursor[i].control = I915_READ(CURCNTR(i));
16151                 error->cursor[i].position = I915_READ(CURPOS(i));
16152                 error->cursor[i].base = I915_READ(CURBASE(i));
16153
16154                 error->plane[i].control = I915_READ(DSPCNTR(i));
16155                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16156                 if (INTEL_INFO(dev)->gen <= 3) {
16157                         error->plane[i].size = I915_READ(DSPSIZE(i));
16158                         error->plane[i].pos = I915_READ(DSPPOS(i));
16159                 }
16160                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16161                         error->plane[i].addr = I915_READ(DSPADDR(i));
16162                 if (INTEL_INFO(dev)->gen >= 4) {
16163                         error->plane[i].surface = I915_READ(DSPSURF(i));
16164                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16165                 }
16166
16167                 error->pipe[i].source = I915_READ(PIPESRC(i));
16168
16169                 if (HAS_GMCH_DISPLAY(dev))
16170                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16171         }
16172
16173         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16174         if (HAS_DDI(dev_priv->dev))
16175                 error->num_transcoders++; /* Account for eDP. */
16176
16177         for (i = 0; i < error->num_transcoders; i++) {
16178                 enum transcoder cpu_transcoder = transcoders[i];
16179
16180                 error->transcoder[i].power_domain_on =
16181                         __intel_display_power_is_enabled(dev_priv,
16182                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16183                 if (!error->transcoder[i].power_domain_on)
16184                         continue;
16185
16186                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16187
16188                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16189                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16190                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16191                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16192                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16193                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16194                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16195         }
16196
16197         return error;
16198 }
16199
16200 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16201
16202 void
16203 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16204                                 struct drm_device *dev,
16205                                 struct intel_display_error_state *error)
16206 {
16207         struct drm_i915_private *dev_priv = dev->dev_private;
16208         int i;
16209
16210         if (!error)
16211                 return;
16212
16213         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16214         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16215                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16216                            error->power_well_driver);
16217         for_each_pipe(dev_priv, i) {
16218                 err_printf(m, "Pipe [%d]:\n", i);
16219                 err_printf(m, "  Power: %s\n",
16220                            onoff(error->pipe[i].power_domain_on));
16221                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16222                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16223
16224                 err_printf(m, "Plane [%d]:\n", i);
16225                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16226                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16227                 if (INTEL_INFO(dev)->gen <= 3) {
16228                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16229                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16230                 }
16231                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16232                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16233                 if (INTEL_INFO(dev)->gen >= 4) {
16234                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16235                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16236                 }
16237
16238                 err_printf(m, "Cursor [%d]:\n", i);
16239                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16240                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16241                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16242         }
16243
16244         for (i = 0; i < error->num_transcoders; i++) {
16245                 err_printf(m, "CPU transcoder: %c\n",
16246                            transcoder_name(error->transcoder[i].cpu_transcoder));
16247                 err_printf(m, "  Power: %s\n",
16248                            onoff(error->transcoder[i].power_domain_on));
16249                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16250                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16251                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16252                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16253                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16254                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16255                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16256         }
16257 }