drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats supported by all gen */
  49 #define COMMON_PRIMARY_FORMATS \
  50         DRM_FORMAT_C8, \
  51         DRM_FORMAT_RGB565, \
  52         DRM_FORMAT_XRGB8888, \
  53         DRM_FORMAT_ARGB8888
  54
  55 /* Primary plane formats for gen <= 3 */
  56 static const uint32_t i8xx_primary_formats[] = {
  57         COMMON_PRIMARY_FORMATS,
  58         DRM_FORMAT_XRGB1555,
  59         DRM_FORMAT_ARGB1555,
  60 };
  61
  62 /* Primary plane formats for gen >= 4 */
  63 static const uint32_t i965_primary_formats[] = {
  64         COMMON_PRIMARY_FORMATS, \
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_ABGR8888,
  67         DRM_FORMAT_XRGB2101010,
  68         DRM_FORMAT_ARGB2101010,
  69         DRM_FORMAT_XBGR2101010,
  70         DRM_FORMAT_ABGR2101010,
  71 };
  72
  73 /* Cursor formats */
  74 static const uint32_t intel_cursor_formats[] = {
  75         DRM_FORMAT_ARGB8888,
  76 };
  77
  78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  79
  80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  81                                 struct intel_crtc_state *pipe_config);
  82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  83                                    struct intel_crtc_state *pipe_config);
  84
  85 static int intel_set_mode(struct drm_crtc *crtc,
  86                           struct drm_atomic_state *state);
  87 static int intel_framebuffer_init(struct drm_device *dev,
  88                                   struct intel_framebuffer *ifb,
  89                                   struct drm_mode_fb_cmd2 *mode_cmd,
  90                                   struct drm_i915_gem_object *obj);
  91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  94                                          struct intel_link_m_n *m_n,
  95                                          struct intel_link_m_n *m2_n2);
  96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  99 static void vlv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_state *pipe_config);
 101 static void chv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 105 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 106         struct intel_crtc_state *crtc_state);
 107 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 108                            int num_connectors);
 109 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
 110 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
 111
 112 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 113 {
 114         if (!connector->mst_port)
 115                 return connector->encoder;
 116         else
 117                 return &connector->mst_port->mst_encoders[pipe]->base;
 118 }
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 int
 136 intel_pch_rawclk(struct drm_device *dev)
 137 {
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139
 140         WARN_ON(!HAS_PCH_SPLIT(dev));
 141
 142         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 143 }
 144
 145 static inline u32 /* units of 100MHz */
 146 intel_fdi_link_freq(struct drm_device *dev)
 147 {
 148         if (IS_GEN5(dev)) {
 149                 struct drm_i915_private *dev_priv = dev->dev_private;
 150                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 151         } else
 152                 return 27;
 153 }
 154
 155 static const intel_limit_t intel_limits_i8xx_dac = {
 156         .dot = { .min = 25000, .max = 350000 },
 157         .vco = { .min = 908000, .max = 1512000 },
 158         .n = { .min = 2, .max = 16 },
 159         .m = { .min = 96, .max = 140 },
 160         .m1 = { .min = 18, .max = 26 },
 161         .m2 = { .min = 6, .max = 16 },
 162         .p = { .min = 4, .max = 128 },
 163         .p1 = { .min = 2, .max = 33 },
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 4, .p2_fast = 2 },
 166 };
 167
 168 static const intel_limit_t intel_limits_i8xx_dvo = {
 169         .dot = { .min = 25000, .max = 350000 },
 170         .vco = { .min = 908000, .max = 1512000 },
 171         .n = { .min = 2, .max = 16 },
 172         .m = { .min = 96, .max = 140 },
 173         .m1 = { .min = 18, .max = 26 },
 174         .m2 = { .min = 6, .max = 16 },
 175         .p = { .min = 4, .max = 128 },
 176         .p1 = { .min = 2, .max = 33 },
 177         .p2 = { .dot_limit = 165000,
 178                 .p2_slow = 4, .p2_fast = 4 },
 179 };
 180
 181 static const intel_limit_t intel_limits_i8xx_lvds = {
 182         .dot = { .min = 25000, .max = 350000 },
 183         .vco = { .min = 908000, .max = 1512000 },
 184         .n = { .min = 2, .max = 16 },
 185         .m = { .min = 96, .max = 140 },
 186         .m1 = { .min = 18, .max = 26 },
 187         .m2 = { .min = 6, .max = 16 },
 188         .p = { .min = 4, .max = 128 },
 189         .p1 = { .min = 1, .max = 6 },
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 14, .p2_fast = 7 },
 192 };
 193
 194 static const intel_limit_t intel_limits_i9xx_sdvo = {
 195         .dot = { .min = 20000, .max = 400000 },
 196         .vco = { .min = 1400000, .max = 2800000 },
 197         .n = { .min = 1, .max = 6 },
 198         .m = { .min = 70, .max = 120 },
 199         .m1 = { .min = 8, .max = 18 },
 200         .m2 = { .min = 3, .max = 7 },
 201         .p = { .min = 5, .max = 80 },
 202         .p1 = { .min = 1, .max = 8 },
 203         .p2 = { .dot_limit = 200000,
 204                 .p2_slow = 10, .p2_fast = 5 },
 205 };
 206
 207 static const intel_limit_t intel_limits_i9xx_lvds = {
 208         .dot = { .min = 20000, .max = 400000 },
 209         .vco = { .min = 1400000, .max = 2800000 },
 210         .n = { .min = 1, .max = 6 },
 211         .m = { .min = 70, .max = 120 },
 212         .m1 = { .min = 8, .max = 18 },
 213         .m2 = { .min = 3, .max = 7 },
 214         .p = { .min = 7, .max = 98 },
 215         .p1 = { .min = 1, .max = 8 },
 216         .p2 = { .dot_limit = 112000,
 217                 .p2_slow = 14, .p2_fast = 7 },
 218 };
 219
 220
 221 static const intel_limit_t intel_limits_g4x_sdvo = {
 222         .dot = { .min = 25000, .max = 270000 },
 223         .vco = { .min = 1750000, .max = 3500000},
 224         .n = { .min = 1, .max = 4 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 10, .max = 30 },
 229         .p1 = { .min = 1, .max = 3},
 230         .p2 = { .dot_limit = 270000,
 231                 .p2_slow = 10,
 232                 .p2_fast = 10
 233         },
 234 };
 235
 236 static const intel_limit_t intel_limits_g4x_hdmi = {
 237         .dot = { .min = 22000, .max = 400000 },
 238         .vco = { .min = 1750000, .max = 3500000},
 239         .n = { .min = 1, .max = 4 },
 240         .m = { .min = 104, .max = 138 },
 241         .m1 = { .min = 16, .max = 23 },
 242         .m2 = { .min = 5, .max = 11 },
 243         .p = { .min = 5, .max = 80 },
 244         .p1 = { .min = 1, .max = 8},
 245         .p2 = { .dot_limit = 165000,
 246                 .p2_slow = 10, .p2_fast = 5 },
 247 };
 248
 249 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 250         .dot = { .min = 20000, .max = 115000 },
 251         .vco = { .min = 1750000, .max = 3500000 },
 252         .n = { .min = 1, .max = 3 },
 253         .m = { .min = 104, .max = 138 },
 254         .m1 = { .min = 17, .max = 23 },
 255         .m2 = { .min = 5, .max = 11 },
 256         .p = { .min = 28, .max = 112 },
 257         .p1 = { .min = 2, .max = 8 },
 258         .p2 = { .dot_limit = 0,
 259                 .p2_slow = 14, .p2_fast = 14
 260         },
 261 };
 262
 263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 264         .dot = { .min = 80000, .max = 224000 },
 265         .vco = { .min = 1750000, .max = 3500000 },
 266         .n = { .min = 1, .max = 3 },
 267         .m = { .min = 104, .max = 138 },
 268         .m1 = { .min = 17, .max = 23 },
 269         .m2 = { .min = 5, .max = 11 },
 270         .p = { .min = 14, .max = 42 },
 271         .p1 = { .min = 2, .max = 6 },
 272         .p2 = { .dot_limit = 0,
 273                 .p2_slow = 7, .p2_fast = 7
 274         },
 275 };
 276
 277 static const intel_limit_t intel_limits_pineview_sdvo = {
 278         .dot = { .min = 20000, .max = 400000},
 279         .vco = { .min = 1700000, .max = 3500000 },
 280         /* Pineview's Ncounter is a ring counter */
 281         .n = { .min = 3, .max = 6 },
 282         .m = { .min = 2, .max = 256 },
 283         /* Pineview only has one combined m divider, which we treat as m2. */
 284         .m1 = { .min = 0, .max = 0 },
 285         .m2 = { .min = 0, .max = 254 },
 286         .p = { .min = 5, .max = 80 },
 287         .p1 = { .min = 1, .max = 8 },
 288         .p2 = { .dot_limit = 200000,
 289                 .p2_slow = 10, .p2_fast = 5 },
 290 };
 291
 292 static const intel_limit_t intel_limits_pineview_lvds = {
 293         .dot = { .min = 20000, .max = 400000 },
 294         .vco = { .min = 1700000, .max = 3500000 },
 295         .n = { .min = 3, .max = 6 },
 296         .m = { .min = 2, .max = 256 },
 297         .m1 = { .min = 0, .max = 0 },
 298         .m2 = { .min = 0, .max = 254 },
 299         .p = { .min = 7, .max = 112 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 112000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 /* Ironlake / Sandybridge
 306  *
 307  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 308  * the range value for them is (actual_value - 2).
 309  */
 310 static const intel_limit_t intel_limits_ironlake_dac = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 5 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 5, .max = 80 },
 318         .p1 = { .min = 1, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 10, .p2_fast = 5 },
 321 };
 322
 323 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 324         .dot = { .min = 25000, .max = 350000 },
 325         .vco = { .min = 1760000, .max = 3510000 },
 326         .n = { .min = 1, .max = 3 },
 327         .m = { .min = 79, .max = 118 },
 328         .m1 = { .min = 12, .max = 22 },
 329         .m2 = { .min = 5, .max = 9 },
 330         .p = { .min = 28, .max = 112 },
 331         .p1 = { .min = 2, .max = 8 },
 332         .p2 = { .dot_limit = 225000,
 333                 .p2_slow = 14, .p2_fast = 14 },
 334 };
 335
 336 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 337         .dot = { .min = 25000, .max = 350000 },
 338         .vco = { .min = 1760000, .max = 3510000 },
 339         .n = { .min = 1, .max = 3 },
 340         .m = { .min = 79, .max = 127 },
 341         .m1 = { .min = 12, .max = 22 },
 342         .m2 = { .min = 5, .max = 9 },
 343         .p = { .min = 14, .max = 56 },
 344         .p1 = { .min = 2, .max = 8 },
 345         .p2 = { .dot_limit = 225000,
 346                 .p2_slow = 7, .p2_fast = 7 },
 347 };
 348
 349 /* LVDS 100mhz refclk limits. */
 350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 351         .dot = { .min = 25000, .max = 350000 },
 352         .vco = { .min = 1760000, .max = 3510000 },
 353         .n = { .min = 1, .max = 2 },
 354         .m = { .min = 79, .max = 126 },
 355         .m1 = { .min = 12, .max = 22 },
 356         .m2 = { .min = 5, .max = 9 },
 357         .p = { .min = 28, .max = 112 },
 358         .p1 = { .min = 2, .max = 8 },
 359         .p2 = { .dot_limit = 225000,
 360                 .p2_slow = 14, .p2_fast = 14 },
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000 },
 366         .n = { .min = 1, .max = 3 },
 367         .m = { .min = 79, .max = 126 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 14, .max = 42 },
 371         .p1 = { .min = 2, .max = 6 },
 372         .p2 = { .dot_limit = 225000,
 373                 .p2_slow = 7, .p2_fast = 7 },
 374 };
 375
 376 static const intel_limit_t intel_limits_vlv = {
 377          /*
 378           * These are the data rate limits (measured in fast clocks)
 379           * since those are the strictest limits we have. The fast
 380           * clock and actual rate limits are more relaxed, so checking
 381           * them would make no difference.
 382           */
 383         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 384         .vco = { .min = 4000000, .max = 6000000 },
 385         .n = { .min = 1, .max = 7 },
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p1 = { .min = 2, .max = 3 },
 389         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 390 };
 391
 392 static const intel_limit_t intel_limits_chv = {
 393         /*
 394          * These are the data rate limits (measured in fast clocks)
 395          * since those are the strictest limits we have.  The fast
 396          * clock and actual rate limits are more relaxed, so checking
 397          * them would make no difference.
 398          */
 399         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 400         .vco = { .min = 4800000, .max = 6480000 },
 401         .n = { .min = 1, .max = 1 },
 402         .m1 = { .min = 2, .max = 2 },
 403         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 404         .p1 = { .min = 2, .max = 4 },
 405         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 406 };
 407
 408 static const intel_limit_t intel_limits_bxt = {
 409         /* FIXME: find real dot limits */
 410         .dot = { .min = 0, .max = INT_MAX },
 411         .vco = { .min = 4800000, .max = 6480000 },
 412         .n = { .min = 1, .max = 1 },
 413         .m1 = { .min = 2, .max = 2 },
 414         /* FIXME: find real m2 limits */
 415         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 416         .p1 = { .min = 2, .max = 4 },
 417         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 418 };
 419
 420 static void vlv_clock(int refclk, intel_clock_t *clock)
 421 {
 422         clock->m = clock->m1 * clock->m2;
 423         clock->p = clock->p1 * clock->p2;
 424         if (WARN_ON(clock->n == 0 || clock->p == 0))
 425                 return;
 426         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 427         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 428 }
 429
 430 /**
 431  * Returns whether any output on the specified pipe is of the specified type
 432  */
 433 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 434 {
 435         struct drm_device *dev = crtc->base.dev;
 436         struct intel_encoder *encoder;
 437
 438         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 439                 if (encoder->type == type)
 440                         return true;
 441
 442         return false;
 443 }
 444
 445 /**
 446  * Returns whether any output on the specified pipe will have the specified
 447  * type after a staged modeset is complete, i.e., the same as
 448  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 449  * encoder->crtc.
 450  */
 451 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 452                                       int type)
 453 {
 454         struct drm_atomic_state *state = crtc_state->base.state;
 455         struct drm_connector *connector;
 456         struct drm_connector_state *connector_state;
 457         struct intel_encoder *encoder;
 458         int i, num_connectors = 0;
 459
 460         for_each_connector_in_state(state, connector, connector_state, i) {
 461                 if (connector_state->crtc != crtc_state->base.crtc)
 462                         continue;
 463
 464                 num_connectors++;
 465
 466                 encoder = to_intel_encoder(connector_state->best_encoder);
 467                 if (encoder->type == type)
 468                         return true;
 469         }
 470
 471         WARN_ON(num_connectors == 0);
 472
 473         return false;
 474 }
 475
 476 static const intel_limit_t *
 477 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 478 {
 479         struct drm_device *dev = crtc_state->base.crtc->dev;
 480         const intel_limit_t *limit;
 481
 482         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 483                 if (intel_is_dual_link_lvds(dev)) {
 484                         if (refclk == 100000)
 485                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 486                         else
 487                                 limit = &intel_limits_ironlake_dual_lvds;
 488                 } else {
 489                         if (refclk == 100000)
 490                                 limit = &intel_limits_ironlake_single_lvds_100m;
 491                         else
 492                                 limit = &intel_limits_ironlake_single_lvds;
 493                 }
 494         } else
 495                 limit = &intel_limits_ironlake_dac;
 496
 497         return limit;
 498 }
 499
 500 static const intel_limit_t *
 501 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 502 {
 503         struct drm_device *dev = crtc_state->base.crtc->dev;
 504         const intel_limit_t *limit;
 505
 506         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 507                 if (intel_is_dual_link_lvds(dev))
 508                         limit = &intel_limits_g4x_dual_channel_lvds;
 509                 else
 510                         limit = &intel_limits_g4x_single_channel_lvds;
 511         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 512                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 513                 limit = &intel_limits_g4x_hdmi;
 514         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 515                 limit = &intel_limits_g4x_sdvo;
 516         } else /* The option is for other outputs */
 517                 limit = &intel_limits_i9xx_sdvo;
 518
 519         return limit;
 520 }
 521
 522 static const intel_limit_t *
 523 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 524 {
 525         struct drm_device *dev = crtc_state->base.crtc->dev;
 526         const intel_limit_t *limit;
 527
 528         if (IS_BROXTON(dev))
 529                 limit = &intel_limits_bxt;
 530         else if (HAS_PCH_SPLIT(dev))
 531                 limit = intel_ironlake_limit(crtc_state, refclk);
 532         else if (IS_G4X(dev)) {
 533                 limit = intel_g4x_limit(crtc_state);
 534         } else if (IS_PINEVIEW(dev)) {
 535                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 536                         limit = &intel_limits_pineview_lvds;
 537                 else
 538                         limit = &intel_limits_pineview_sdvo;
 539         } else if (IS_CHERRYVIEW(dev)) {
 540                 limit = &intel_limits_chv;
 541         } else if (IS_VALLEYVIEW(dev)) {
 542                 limit = &intel_limits_vlv;
 543         } else if (!IS_GEN2(dev)) {
 544                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 545                         limit = &intel_limits_i9xx_lvds;
 546                 else
 547                         limit = &intel_limits_i9xx_sdvo;
 548         } else {
 549                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 550                         limit = &intel_limits_i8xx_lvds;
 551                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 552                         limit = &intel_limits_i8xx_dvo;
 553                 else
 554                         limit = &intel_limits_i8xx_dac;
 555         }
 556         return limit;
 557 }
 558
 559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 560 static void pineview_clock(int refclk, intel_clock_t *clock)
 561 {
 562         clock->m = clock->m2 + 2;
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n == 0 || clock->p == 0))
 565                 return;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568 }
 569
 570 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 571 {
 572         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 573 }
 574
 575 static void i9xx_clock(int refclk, intel_clock_t *clock)
 576 {
 577         clock->m = i9xx_dpll_compute_m(clock);
 578         clock->p = clock->p1 * clock->p2;
 579         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 580                 return;
 581         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 582         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 583 }
 584
 585 static void chv_clock(int refclk, intel_clock_t *clock)
 586 {
 587         clock->m = clock->m1 * clock->m2;
 588         clock->p = clock->p1 * clock->p2;
 589         if (WARN_ON(clock->n == 0 || clock->p == 0))
 590                 return;
 591         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 592                         clock->n << 22);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594 }
 595
 596 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 597 /**
 598  * Returns whether the given set of divisors are valid for a given refclk with
 599  * the given connectors.
 600  */
 601
 602 static bool intel_PLL_is_valid(struct drm_device *dev,
 603                                const intel_limit_t *limit,
 604                                const intel_clock_t *clock)
 605 {
 606         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 607                 INTELPllInvalid("n out of range\n");
 608         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 609                 INTELPllInvalid("p1 out of range\n");
 610         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 611                 INTELPllInvalid("m2 out of range\n");
 612         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 613                 INTELPllInvalid("m1 out of range\n");
 614
 615         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 616                 if (clock->m1 <= clock->m2)
 617                         INTELPllInvalid("m1 <= m2\n");
 618
 619         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 620                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 621                         INTELPllInvalid("p out of range\n");
 622                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 623                         INTELPllInvalid("m out of range\n");
 624         }
 625
 626         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 627                 INTELPllInvalid("vco out of range\n");
 628         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 629          * connector, etc., rather than just a single range.
 630          */
 631         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 632                 INTELPllInvalid("dot out of range\n");
 633
 634         return true;
 635 }
 636
 637 static bool
 638 i9xx_find_best_dpll(const intel_limit_t *limit,
 639                     struct intel_crtc_state *crtc_state,
 640                     int target, int refclk, intel_clock_t *match_clock,
 641                     intel_clock_t *best_clock)
 642 {
 643         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 644         struct drm_device *dev = crtc->base.dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         if (clock.m2 >= clock.m1)
 672                                 break;
 673                         for (clock.n = limit->n.min;
 674                              clock.n <= limit->n.max; clock.n++) {
 675                                 for (clock.p1 = limit->p1.min;
 676                                         clock.p1 <= limit->p1.max; clock.p1++) {
 677                                         int this_err;
 678
 679                                         i9xx_clock(refclk, &clock);
 680                                         if (!intel_PLL_is_valid(dev, limit,
 681                                                                 &clock))
 682                                                 continue;
 683                                         if (match_clock &&
 684                                             clock.p != match_clock->p)
 685                                                 continue;
 686
 687                                         this_err = abs(clock.dot - target);
 688                                         if (this_err < err) {
 689                                                 *best_clock = clock;
 690                                                 err = this_err;
 691                                         }
 692                                 }
 693                         }
 694                 }
 695         }
 696
 697         return (err != target);
 698 }
 699
 700 static bool
 701 pnv_find_best_dpll(const intel_limit_t *limit,
 702                    struct intel_crtc_state *crtc_state,
 703                    int target, int refclk, intel_clock_t *match_clock,
 704                    intel_clock_t *best_clock)
 705 {
 706         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 707         struct drm_device *dev = crtc->base.dev;
 708         intel_clock_t clock;
 709         int err = target;
 710
 711         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 712                 /*
 713                  * For LVDS just rely on its current settings for dual-channel.
 714                  * We haven't figured out how to reliably set up different
 715                  * single/dual channel state, if we even can.
 716                  */
 717                 if (intel_is_dual_link_lvds(dev))
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729
 730         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 731              clock.m1++) {
 732                 for (clock.m2 = limit->m2.min;
 733                      clock.m2 <= limit->m2.max; clock.m2++) {
 734                         for (clock.n = limit->n.min;
 735                              clock.n <= limit->n.max; clock.n++) {
 736                                 for (clock.p1 = limit->p1.min;
 737                                         clock.p1 <= limit->p1.max; clock.p1++) {
 738                                         int this_err;
 739
 740                                         pineview_clock(refclk, &clock);
 741                                         if (!intel_PLL_is_valid(dev, limit,
 742                                                                 &clock))
 743                                                 continue;
 744                                         if (match_clock &&
 745                                             clock.p != match_clock->p)
 746                                                 continue;
 747
 748                                         this_err = abs(clock.dot - target);
 749                                         if (this_err < err) {
 750                                                 *best_clock = clock;
 751                                                 err = this_err;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         return (err != target);
 759 }
 760
 761 static bool
 762 g4x_find_best_dpll(const intel_limit_t *limit,
 763                    struct intel_crtc_state *crtc_state,
 764                    int target, int refclk, intel_clock_t *match_clock,
 765                    intel_clock_t *best_clock)
 766 {
 767         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 768         struct drm_device *dev = crtc->base.dev;
 769         intel_clock_t clock;
 770         int max_n;
 771         bool found;
 772         /* approximately equals target * 0.00585 */
 773         int err_most = (target >> 8) + (target >> 9);
 774         found = false;
 775
 776         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 777                 if (intel_is_dual_link_lvds(dev))
 778                         clock.p2 = limit->p2.p2_fast;
 779                 else
 780                         clock.p2 = limit->p2.p2_slow;
 781         } else {
 782                 if (target < limit->p2.dot_limit)
 783                         clock.p2 = limit->p2.p2_slow;
 784                 else
 785                         clock.p2 = limit->p2.p2_fast;
 786         }
 787
 788         memset(best_clock, 0, sizeof(*best_clock));
 789         max_n = limit->n.max;
 790         /* based on hardware requirement, prefer smaller n to precision */
 791         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 792                 /* based on hardware requirement, prefere larger m1,m2 */
 793                 for (clock.m1 = limit->m1.max;
 794                      clock.m1 >= limit->m1.min; clock.m1--) {
 795                         for (clock.m2 = limit->m2.max;
 796                              clock.m2 >= limit->m2.min; clock.m2--) {
 797                                 for (clock.p1 = limit->p1.max;
 798                                      clock.p1 >= limit->p1.min; clock.p1--) {
 799                                         int this_err;
 800
 801                                         i9xx_clock(refclk, &clock);
 802                                         if (!intel_PLL_is_valid(dev, limit,
 803                                                                 &clock))
 804                                                 continue;
 805
 806                                         this_err = abs(clock.dot - target);
 807                                         if (this_err < err_most) {
 808                                                 *best_clock = clock;
 809                                                 err_most = this_err;
 810                                                 max_n = clock.n;
 811                                                 found = true;
 812                                         }
 813                                 }
 814                         }
 815                 }
 816         }
 817         return found;
 818 }
 819
 820 /*
 821  * Check if the calculated PLL configuration is more optimal compared to the
 822  * best configuration and error found so far. Return the calculated error.
 823  */
 824 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 825                                const intel_clock_t *calculated_clock,
 826                                const intel_clock_t *best_clock,
 827                                unsigned int best_error_ppm,
 828                                unsigned int *error_ppm)
 829 {
 830         /*
 831          * For CHV ignore the error and consider only the P value.
 832          * Prefer a bigger P value based on HW requirements.
 833          */
 834         if (IS_CHERRYVIEW(dev)) {
 835                 *error_ppm = 0;
 836
 837                 return calculated_clock->p > best_clock->p;
 838         }
 839
 840         if (WARN_ON_ONCE(!target_freq))
 841                 return false;
 842
 843         *error_ppm = div_u64(1000000ULL *
 844                                 abs(target_freq - calculated_clock->dot),
 845                              target_freq);
 846         /*
 847          * Prefer a better P value over a better (smaller) error if the error
 848          * is small. Ensure this preference for future configurations too by
 849          * setting the error to 0.
 850          */
 851         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 852                 *error_ppm = 0;
 853
 854                 return true;
 855         }
 856
 857         return *error_ppm + 10 < best_error_ppm;
 858 }
 859
 860 static bool
 861 vlv_find_best_dpll(const intel_limit_t *limit,
 862                    struct intel_crtc_state *crtc_state,
 863                    int target, int refclk, intel_clock_t *match_clock,
 864                    intel_clock_t *best_clock)
 865 {
 866         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 867         struct drm_device *dev = crtc->base.dev;
 868         intel_clock_t clock;
 869         unsigned int bestppm = 1000000;
 870         /* min update 19.2 MHz */
 871         int max_n = min(limit->n.max, refclk / 19200);
 872         bool found = false;
 873
 874         target *= 5; /* fast clock */
 875
 876         memset(best_clock, 0, sizeof(*best_clock));
 877
 878         /* based on hardware requirement, prefer smaller n to precision */
 879         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 880                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 881                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 882                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 883                                 clock.p = clock.p1 * clock.p2;
 884                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 885                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 886                                         unsigned int ppm;
 887
 888                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 889                                                                      refclk * clock.m1);
 890
 891                                         vlv_clock(refclk, &clock);
 892
 893                                         if (!intel_PLL_is_valid(dev, limit,
 894                                                                 &clock))
 895                                                 continue;
 896
 897                                         if (!vlv_PLL_is_optimal(dev, target,
 898                                                                 &clock,
 899                                                                 best_clock,
 900                                                                 bestppm, &ppm))
 901                                                 continue;
 902
 903                                         *best_clock = clock;
 904                                         bestppm = ppm;
 905                                         found = true;
 906                                 }
 907                         }
 908                 }
 909         }
 910
 911         return found;
 912 }
 913
 914 static bool
 915 chv_find_best_dpll(const intel_limit_t *limit,
 916                    struct intel_crtc_state *crtc_state,
 917                    int target, int refclk, intel_clock_t *match_clock,
 918                    intel_clock_t *best_clock)
 919 {
 920         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 921         struct drm_device *dev = crtc->base.dev;
 922         unsigned int best_error_ppm;
 923         intel_clock_t clock;
 924         uint64_t m2;
 925         int found = false;
 926
 927         memset(best_clock, 0, sizeof(*best_clock));
 928         best_error_ppm = 1000000;
 929
 930         /*
 931          * Based on hardware doc, the n always set to 1, and m1 always
 932          * set to 2.  If requires to support 200Mhz refclk, we need to
 933          * revisit this because n may not 1 anymore.
 934          */
 935         clock.n = 1, clock.m1 = 2;
 936         target *= 5;    /* fast clock */
 937
 938         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 939                 for (clock.p2 = limit->p2.p2_fast;
 940                                 clock.p2 >= limit->p2.p2_slow;
 941                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 942                         unsigned int error_ppm;
 943
 944                         clock.p = clock.p1 * clock.p2;
 945
 946                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 947                                         clock.n) << 22, refclk * clock.m1);
 948
 949                         if (m2 > INT_MAX/clock.m1)
 950                                 continue;
 951
 952                         clock.m2 = m2;
 953
 954                         chv_clock(refclk, &clock);
 955
 956                         if (!intel_PLL_is_valid(dev, limit, &clock))
 957                                 continue;
 958
 959                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 960                                                 best_error_ppm, &error_ppm))
 961                                 continue;
 962
 963                         *best_clock = clock;
 964                         best_error_ppm = error_ppm;
 965                         found = true;
 966                 }
 967         }
 968
 969         return found;
 970 }
 971
 972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 973                         intel_clock_t *best_clock)
 974 {
 975         int refclk = i9xx_get_refclk(crtc_state, 0);
 976
 977         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 978                                   target_clock, refclk, NULL, best_clock);
 979 }
 980
 981 bool intel_crtc_active(struct drm_crtc *crtc)
 982 {
 983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 984
 985         /* Be paranoid as we can arrive here with only partial
 986          * state retrieved from the hardware during setup.
 987          *
 988          * We can ditch the adjusted_mode.crtc_clock check as soon
 989          * as Haswell has gained clock readout/fastboot support.
 990          *
 991          * We can ditch the crtc->primary->fb check as soon as we can
 992          * properly reconstruct framebuffers.
 993          *
 994          * FIXME: The intel_crtc->active here should be switched to
 995          * crtc->state->active once we have proper CRTC states wired up
 996          * for atomic.
 997          */
 998         return intel_crtc->active && crtc->primary->state->fb &&
 999                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1000 }
1001
1002 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003                                              enum pipe pipe)
1004 {
1005         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
1008         return intel_crtc->config->cpu_transcoder;
1009 }
1010
1011 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012 {
1013         struct drm_i915_private *dev_priv = dev->dev_private;
1014         u32 reg = PIPEDSL(pipe);
1015         u32 line1, line2;
1016         u32 line_mask;
1017
1018         if (IS_GEN2(dev))
1019                 line_mask = DSL_LINEMASK_GEN2;
1020         else
1021                 line_mask = DSL_LINEMASK_GEN3;
1022
1023         line1 = I915_READ(reg) & line_mask;
1024         mdelay(5);
1025         line2 = I915_READ(reg) & line_mask;
1026
1027         return line1 == line2;
1028 }
1029
1030 /*
1031  * intel_wait_for_pipe_off - wait for pipe to turn off
1032  * @crtc: crtc whose pipe to wait for
1033  *
1034  * After disabling a pipe, we can't wait for vblank in the usual way,
1035  * spinning on the vblank interrupt status bit, since we won't actually
1036  * see an interrupt when the pipe is disabled.
1037  *
1038  * On Gen4 and above:
1039  *   wait for the pipe register state bit to turn off
1040  *
1041  * Otherwise:
1042  *   wait for the display line value to settle (it usually
1043  *   ends up stopping at the start of the next frame).
1044  *
1045  */
1046 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1047 {
1048         struct drm_device *dev = crtc->base.dev;
1049         struct drm_i915_private *dev_priv = dev->dev_private;
1050         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1051         enum pipe pipe = crtc->pipe;
1052
1053         if (INTEL_INFO(dev)->gen >= 4) {
1054                 int reg = PIPECONF(cpu_transcoder);
1055
1056                 /* Wait for the Pipe State to go off */
1057                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058                              100))
1059                         WARN(1, "pipe_off wait timed out\n");
1060         } else {
1061                 /* Wait for the display line to settle */
1062                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1063                         WARN(1, "pipe_off wait timed out\n");
1064         }
1065 }
1066
1067 /*
1068  * ibx_digital_port_connected - is the specified port connected?
1069  * @dev_priv: i915 private structure
1070  * @port: the port to test
1071  *
1072  * Returns true if @port is connected, false otherwise.
1073  */
1074 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075                                 struct intel_digital_port *port)
1076 {
1077         u32 bit;
1078
1079         if (HAS_PCH_IBX(dev_priv->dev)) {
1080                 switch (port->port) {
1081                 case PORT_B:
1082                         bit = SDE_PORTB_HOTPLUG;
1083                         break;
1084                 case PORT_C:
1085                         bit = SDE_PORTC_HOTPLUG;
1086                         break;
1087                 case PORT_D:
1088                         bit = SDE_PORTD_HOTPLUG;
1089                         break;
1090                 default:
1091                         return true;
1092                 }
1093         } else {
1094                 switch (port->port) {
1095                 case PORT_B:
1096                         bit = SDE_PORTB_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_C:
1099                         bit = SDE_PORTC_HOTPLUG_CPT;
1100                         break;
1101                 case PORT_D:
1102                         bit = SDE_PORTD_HOTPLUG_CPT;
1103                         break;
1104                 default:
1105                         return true;
1106                 }
1107         }
1108
1109         return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114         return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119                 enum pipe pipe, bool state)
1120 {
1121         int reg;
1122         u32 val;
1123         bool cur_state;
1124
1125         reg = DPLL(pipe);
1126         val = I915_READ(reg);
1127         cur_state = !!(val & DPLL_VCO_ENABLE);
1128         I915_STATE_WARN(cur_state != state,
1129              "PLL state assertion failure (expected %s, current %s)\n",
1130              state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136         u32 val;
1137         bool cur_state;
1138
1139         mutex_lock(&dev_priv->dpio_lock);
1140         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141         mutex_unlock(&dev_priv->dpio_lock);
1142
1143         cur_state = val & DSI_PLL_VCO_EN;
1144         I915_STATE_WARN(cur_state != state,
1145              "DSI PLL state assertion failure (expected %s, current %s)\n",
1146              state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156         if (crtc->config->shared_dpll < 0)
1157                 return NULL;
1158
1159         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164                         struct intel_shared_dpll *pll,
1165                         bool state)
1166 {
1167         bool cur_state;
1168         struct intel_dpll_hw_state hw_state;
1169
1170         if (WARN (!pll,
1171                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1172                 return;
1173
1174         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175         I915_STATE_WARN(cur_state != state,
1176              "%s assertion failure (expected %s, current %s)\n",
1177              pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181                           enum pipe pipe, bool state)
1182 {
1183         int reg;
1184         u32 val;
1185         bool cur_state;
1186         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187                                                                       pipe);
1188
1189         if (HAS_DDI(dev_priv->dev)) {
1190                 /* DDI does not have a specific FDI_TX register */
1191                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192                 val = I915_READ(reg);
1193                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194         } else {
1195                 reg = FDI_TX_CTL(pipe);
1196                 val = I915_READ(reg);
1197                 cur_state = !!(val & FDI_TX_ENABLE);
1198         }
1199         I915_STATE_WARN(cur_state != state,
1200              "FDI TX state assertion failure (expected %s, current %s)\n",
1201              state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207                           enum pipe pipe, bool state)
1208 {
1209         int reg;
1210         u32 val;
1211         bool cur_state;
1212
1213         reg = FDI_RX_CTL(pipe);
1214         val = I915_READ(reg);
1215         cur_state = !!(val & FDI_RX_ENABLE);
1216         I915_STATE_WARN(cur_state != state,
1217              "FDI RX state assertion failure (expected %s, current %s)\n",
1218              state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224                                       enum pipe pipe)
1225 {
1226         int reg;
1227         u32 val;
1228
1229         /* ILK FDI PLL is always enabled */
1230         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231                 return;
1232
1233         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234         if (HAS_DDI(dev_priv->dev))
1235                 return;
1236
1237         reg = FDI_TX_CTL(pipe);
1238         val = I915_READ(reg);
1239         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243                        enum pipe pipe, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = FDI_RX_CTL(pipe);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252         I915_STATE_WARN(cur_state != state,
1253              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254              state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258                            enum pipe pipe)
1259 {
1260         struct drm_device *dev = dev_priv->dev;
1261         int pp_reg;
1262         u32 val;
1263         enum pipe panel_pipe = PIPE_A;
1264         bool locked = true;
1265
1266         if (WARN_ON(HAS_DDI(dev)))
1267                 return;
1268
1269         if (HAS_PCH_SPLIT(dev)) {
1270                 u32 port_sel;
1271
1272                 pp_reg = PCH_PP_CONTROL;
1273                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277                         panel_pipe = PIPE_B;
1278                 /* XXX: else fix for eDP */
1279         } else if (IS_VALLEYVIEW(dev)) {
1280                 /* presumably write lock depends on pipe, not port select */
1281                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282                 panel_pipe = pipe;
1283         } else {
1284                 pp_reg = PP_CONTROL;
1285                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286                         panel_pipe = PIPE_B;
1287         }
1288
1289         val = I915_READ(pp_reg);
1290         if (!(val & PANEL_POWER_ON) ||
1291             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292                 locked = false;
1293
1294         I915_STATE_WARN(panel_pipe == pipe && locked,
1295              "panel assertion failure, pipe %c regs locked\n",
1296              pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300                           enum pipe pipe, bool state)
1301 {
1302         struct drm_device *dev = dev_priv->dev;
1303         bool cur_state;
1304
1305         if (IS_845G(dev) || IS_I865G(dev))
1306                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307         else
1308                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310         I915_STATE_WARN(cur_state != state,
1311              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312              pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318                  enum pipe pipe, bool state)
1319 {
1320         int reg;
1321         u32 val;
1322         bool cur_state;
1323         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324                                                                       pipe);
1325
1326         /* if we need the pipe quirk it must be always on */
1327         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329                 state = true;
1330
1331         if (!intel_display_power_is_enabled(dev_priv,
1332                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333                 cur_state = false;
1334         } else {
1335                 reg = PIPECONF(cpu_transcoder);
1336                 val = I915_READ(reg);
1337                 cur_state = !!(val & PIPECONF_ENABLE);
1338         }
1339
1340         I915_STATE_WARN(cur_state != state,
1341              "pipe %c assertion failure (expected %s, current %s)\n",
1342              pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346                          enum plane plane, bool state)
1347 {
1348         int reg;
1349         u32 val;
1350         bool cur_state;
1351
1352         reg = DSPCNTR(plane);
1353         val = I915_READ(reg);
1354         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355         I915_STATE_WARN(cur_state != state,
1356              "plane %c assertion failure (expected %s, current %s)\n",
1357              plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364                                    enum pipe pipe)
1365 {
1366         struct drm_device *dev = dev_priv->dev;
1367         int reg, i;
1368         u32 val;
1369         int cur_pipe;
1370
1371         /* Primary planes are fixed to pipes on gen4+ */
1372         if (INTEL_INFO(dev)->gen >= 4) {
1373                 reg = DSPCNTR(pipe);
1374                 val = I915_READ(reg);
1375                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376                      "plane %c assertion failure, should be disabled but not\n",
1377                      plane_name(pipe));
1378                 return;
1379         }
1380
1381         /* Need to check both planes against the pipe */
1382         for_each_pipe(dev_priv, i) {
1383                 reg = DSPCNTR(i);
1384                 val = I915_READ(reg);
1385                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386                         DISPPLANE_SEL_PIPE_SHIFT;
1387                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(i), pipe_name(pipe));
1390         }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394                                     enum pipe pipe)
1395 {
1396         struct drm_device *dev = dev_priv->dev;
1397         int reg, sprite;
1398         u32 val;
1399
1400         if (INTEL_INFO(dev)->gen >= 9) {
1401                 for_each_sprite(dev_priv, pipe, sprite) {
1402                         val = I915_READ(PLANE_CTL(pipe, sprite));
1403                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405                              sprite, pipe_name(pipe));
1406                 }
1407         } else if (IS_VALLEYVIEW(dev)) {
1408                 for_each_sprite(dev_priv, pipe, sprite) {
1409                         reg = SPCNTR(pipe, sprite);
1410                         val = I915_READ(reg);
1411                         I915_STATE_WARN(val & SP_ENABLE,
1412                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413                              sprite_name(pipe, sprite), pipe_name(pipe));
1414                 }
1415         } else if (INTEL_INFO(dev)->gen >= 7) {
1416                 reg = SPRCTL(pipe);
1417                 val = I915_READ(reg);
1418                 I915_STATE_WARN(val & SPRITE_ENABLE,
1419                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420                      plane_name(pipe), pipe_name(pipe));
1421         } else if (INTEL_INFO(dev)->gen >= 5) {
1422                 reg = DVSCNTR(pipe);
1423                 val = I915_READ(reg);
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438         u32 val;
1439         bool enabled;
1440
1441         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443         val = I915_READ(PCH_DREF_CONTROL);
1444         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445                             DREF_SUPERSPREAD_SOURCE_MASK));
1446         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450                                            enum pipe pipe)
1451 {
1452         int reg;
1453         u32 val;
1454         bool enabled;
1455
1456         reg = PCH_TRANSCONF(pipe);
1457         val = I915_READ(reg);
1458         enabled = !!(val & TRANS_ENABLE);
1459         I915_STATE_WARN(enabled,
1460              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461              pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465                             enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467         if ((val & DP_PORT_EN) == 0)
1468                 return false;
1469
1470         if (HAS_PCH_CPT(dev_priv->dev)) {
1471                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474                         return false;
1475         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477                         return false;
1478         } else {
1479                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480                         return false;
1481         }
1482         return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486                               enum pipe pipe, u32 val)
1487 {
1488         if ((val & SDVO_ENABLE) == 0)
1489                 return false;
1490
1491         if (HAS_PCH_CPT(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493                         return false;
1494         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & LVDS_PORT_EN) == 0)
1508                 return false;
1509
1510         if (HAS_PCH_CPT(dev_priv->dev)) {
1511                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512                         return false;
1513         } else {
1514                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515                         return false;
1516         }
1517         return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521                               enum pipe pipe, u32 val)
1522 {
1523         if ((val & ADPA_DAC_ENABLE) == 0)
1524                 return false;
1525         if (HAS_PCH_CPT(dev_priv->dev)) {
1526                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527                         return false;
1528         } else {
1529                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530                         return false;
1531         }
1532         return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536                                    enum pipe pipe, int reg, u32 port_sel)
1537 {
1538         u32 val = I915_READ(reg);
1539         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541              reg, pipe_name(pipe));
1542
1543         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544              && (val & DP_PIPEB_SELECT),
1545              "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549                                      enum pipe pipe, int reg)
1550 {
1551         u32 val = I915_READ(reg);
1552         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554              reg, pipe_name(pipe));
1555
1556         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557              && (val & SDVO_PIPE_B_SELECT),
1558              "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562                                       enum pipe pipe)
1563 {
1564         int reg;
1565         u32 val;
1566
1567         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571         reg = PCH_ADPA;
1572         val = I915_READ(reg);
1573         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574              "PCH VGA enabled on transcoder %c, should be disabled\n",
1575              pipe_name(pipe));
1576
1577         reg = PCH_LVDS;
1578         val = I915_READ(reg);
1579         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581              pipe_name(pipe));
1582
1583         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         if (!IS_VALLEYVIEW(dev))
1593                 return;
1594
1595         /*
1596          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597          * CHV x1 PHY (DP/HDMI D)
1598          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599          */
1600         if (IS_CHERRYVIEW(dev)) {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603         } else {
1604                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605         }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609                            const struct intel_crtc_state *pipe_config)
1610 {
1611         struct drm_device *dev = crtc->base.dev;
1612         struct drm_i915_private *dev_priv = dev->dev_private;
1613         int reg = DPLL(crtc->pipe);
1614         u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616         assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618         /* No really, not for ILK+ */
1619         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev_priv->dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633         POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635         /* We do this three times for luck */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648                            const struct intel_crtc_state *pipe_config)
1649 {
1650         struct drm_device *dev = crtc->base.dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         int pipe = crtc->pipe;
1653         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654         u32 tmp;
1655
1656         assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660         mutex_lock(&dev_priv->dpio_lock);
1661
1662         /* Enable back the 10bit clock to display controller */
1663         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664         tmp |= DPIO_DCLKP_EN;
1665         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667         /*
1668          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669          */
1670         udelay(1);
1671
1672         /* Enable PLL */
1673         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674
1675         /* Check PLL is locked */
1676         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1677                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
1679         /* not sure when this should be written */
1680         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1681         POSTING_READ(DPLL_MD(pipe));
1682
1683         mutex_unlock(&dev_priv->dpio_lock);
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688         struct intel_crtc *crtc;
1689         int count = 0;
1690
1691         for_each_intel_crtc(dev, crtc)
1692                 count += crtc->active &&
1693                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695         return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700         struct drm_device *dev = crtc->base.dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         int reg = DPLL(crtc->pipe);
1703         u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705         assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707         /* No really, not for ILK+ */
1708         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710         /* PLL is protected by panel, make sure we can write it */
1711         if (IS_MOBILE(dev) && !IS_I830(dev))
1712                 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714         /* Enable DVO 2x clock on both PLLs if necessary */
1715         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716                 /*
1717                  * It appears to be important that we don't enable this
1718                  * for the current pipe before otherwise configuring the
1719                  * PLL. No idea how this should be handled if multiple
1720                  * DVO outputs are enabled simultaneosly.
1721                  */
1722                 dpll |= DPLL_DVO_2X_MODE;
1723                 I915_WRITE(DPLL(!crtc->pipe),
1724                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725         }
1726
1727         /* Wait for the clocks to stabilize. */
1728         POSTING_READ(reg);
1729         udelay(150);
1730
1731         if (INTEL_INFO(dev)->gen >= 4) {
1732                 I915_WRITE(DPLL_MD(crtc->pipe),
1733                            crtc->config->dpll_hw_state.dpll_md);
1734         } else {
1735                 /* The pixel multiplier can only be updated once the
1736                  * DPLL is enabled and the clocks are stable.
1737                  *
1738                  * So write it again.
1739                  */
1740                 I915_WRITE(reg, dpll);
1741         }
1742
1743         /* We do this three times for luck */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756  * i9xx_disable_pll - disable a PLL
1757  * @dev_priv: i915 private structure
1758  * @pipe: pipe PLL to disable
1759  *
1760  * Disable the PLL for @pipe, making sure the pipe is off first.
1761  *
1762  * Note!  This is for pre-ILK only.
1763  */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766         struct drm_device *dev = crtc->base.dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         enum pipe pipe = crtc->pipe;
1769
1770         /* Disable DVO 2x clock on both PLLs if necessary */
1771         if (IS_I830(dev) &&
1772             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773             intel_num_dvo_pipes(dev) == 1) {
1774                 I915_WRITE(DPLL(PIPE_B),
1775                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776                 I915_WRITE(DPLL(PIPE_A),
1777                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778         }
1779
1780         /* Don't disable pipe or pipe PLLs if needed */
1781         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783                 return;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         I915_WRITE(DPLL(pipe), 0);
1789         POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794         u32 val = 0;
1795
1796         /* Make sure the pipe isn't still relying on us */
1797         assert_pipe_disabled(dev_priv, pipe);
1798
1799         /*
1800          * Leave integrated clock source and reference clock enabled for pipe B.
1801          * The latter is needed for VGA hotplug / manual detection.
1802          */
1803         if (pipe == PIPE_B)
1804                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1805         I915_WRITE(DPLL(pipe), val);
1806         POSTING_READ(DPLL(pipe));
1807
1808 }
1809
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811 {
1812         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813         u32 val;
1814
1815         /* Make sure the pipe isn't still relying on us */
1816         assert_pipe_disabled(dev_priv, pipe);
1817
1818         /* Set PLL en = 0 */
1819         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->dpio_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         /* disable left/right clock distribution */
1833         if (pipe != PIPE_B) {
1834                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837         } else {
1838                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841         }
1842
1843         mutex_unlock(&dev_priv->dpio_lock);
1844 }
1845
1846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1847                          struct intel_digital_port *dport,
1848                          unsigned int expected_mask)
1849 {
1850         u32 port_mask;
1851         int dpll_reg;
1852
1853         switch (dport->port) {
1854         case PORT_B:
1855                 port_mask = DPLL_PORTB_READY_MASK;
1856                 dpll_reg = DPLL(0);
1857                 break;
1858         case PORT_C:
1859                 port_mask = DPLL_PORTC_READY_MASK;
1860                 dpll_reg = DPLL(0);
1861                 expected_mask <<= 4;
1862                 break;
1863         case PORT_D:
1864                 port_mask = DPLL_PORTD_READY_MASK;
1865                 dpll_reg = DPIO_PHY_STATUS;
1866                 break;
1867         default:
1868                 BUG();
1869         }
1870
1871         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1874 }
1875
1876 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 {
1878         struct drm_device *dev = crtc->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882         if (WARN_ON(pll == NULL))
1883                 return;
1884
1885         WARN_ON(!pll->config.crtc_mask);
1886         if (pll->active == 0) {
1887                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888                 WARN_ON(pll->on);
1889                 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891                 pll->mode_set(dev_priv, pll);
1892         }
1893 }
1894
1895 /**
1896  * intel_enable_shared_dpll - enable PCH PLL
1897  * @dev_priv: i915 private structure
1898  * @pipe: pipe PLL to enable
1899  *
1900  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901  * drives the transcoder clock.
1902  */
1903 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 {
1905         struct drm_device *dev = crtc->base.dev;
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908
1909         if (WARN_ON(pll == NULL))
1910                 return;
1911
1912         if (WARN_ON(pll->config.crtc_mask == 0))
1913                 return;
1914
1915         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1916                       pll->name, pll->active, pll->on,
1917                       crtc->base.base.id);
1918
1919         if (pll->active++) {
1920                 WARN_ON(!pll->on);
1921                 assert_shared_dpll_enabled(dev_priv, pll);
1922                 return;
1923         }
1924         WARN_ON(pll->on);
1925
1926         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
1928         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1929         pll->enable(dev_priv, pll);
1930         pll->on = true;
1931 }
1932
1933 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 {
1935         struct drm_device *dev = crtc->base.dev;
1936         struct drm_i915_private *dev_priv = dev->dev_private;
1937         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938
1939         /* PCH only available on ILK+ */
1940         BUG_ON(INTEL_INFO(dev)->gen < 5);
1941         if (WARN_ON(pll == NULL))
1942                return;
1943
1944         if (WARN_ON(pll->config.crtc_mask == 0))
1945                 return;
1946
1947         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948                       pll->name, pll->active, pll->on,
1949                       crtc->base.base.id);
1950
1951         if (WARN_ON(pll->active == 0)) {
1952                 assert_shared_dpll_disabled(dev_priv, pll);
1953                 return;
1954         }
1955
1956         assert_shared_dpll_enabled(dev_priv, pll);
1957         WARN_ON(!pll->on);
1958         if (--pll->active)
1959                 return;
1960
1961         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1962         pll->disable(dev_priv, pll);
1963         pll->on = false;
1964
1965         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1966 }
1967
1968 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969                                            enum pipe pipe)
1970 {
1971         struct drm_device *dev = dev_priv->dev;
1972         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1974         uint32_t reg, val, pipeconf_val;
1975
1976         /* PCH only available on ILK+ */
1977         BUG_ON(!HAS_PCH_SPLIT(dev));
1978
1979         /* Make sure PCH DPLL is enabled */
1980         assert_shared_dpll_enabled(dev_priv,
1981                                    intel_crtc_to_shared_dpll(intel_crtc));
1982
1983         /* FDI must be feeding us bits for PCH ports */
1984         assert_fdi_tx_enabled(dev_priv, pipe);
1985         assert_fdi_rx_enabled(dev_priv, pipe);
1986
1987         if (HAS_PCH_CPT(dev)) {
1988                 /* Workaround: Set the timing override bit before enabling the
1989                  * pch transcoder. */
1990                 reg = TRANS_CHICKEN2(pipe);
1991                 val = I915_READ(reg);
1992                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993                 I915_WRITE(reg, val);
1994         }
1995
1996         reg = PCH_TRANSCONF(pipe);
1997         val = I915_READ(reg);
1998         pipeconf_val = I915_READ(PIPECONF(pipe));
1999
2000         if (HAS_PCH_IBX(dev_priv->dev)) {
2001                 /*
2002                  * make the BPC in transcoder be consistent with
2003                  * that in pipeconf reg.
2004                  */
2005                 val &= ~PIPECONF_BPC_MASK;
2006                 val |= pipeconf_val & PIPECONF_BPC_MASK;
2007         }
2008
2009         val &= ~TRANS_INTERLACE_MASK;
2010         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2011                 if (HAS_PCH_IBX(dev_priv->dev) &&
2012                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2013                         val |= TRANS_LEGACY_INTERLACED_ILK;
2014                 else
2015                         val |= TRANS_INTERLACED;
2016         else
2017                 val |= TRANS_PROGRESSIVE;
2018
2019         I915_WRITE(reg, val | TRANS_ENABLE);
2020         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2021                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2022 }
2023
2024 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2025                                       enum transcoder cpu_transcoder)
2026 {
2027         u32 val, pipeconf_val;
2028
2029         /* PCH only available on ILK+ */
2030         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2031
2032         /* FDI must be feeding us bits for PCH ports */
2033         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2034         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2035
2036         /* Workaround: set timing override bit. */
2037         val = I915_READ(_TRANSA_CHICKEN2);
2038         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2039         I915_WRITE(_TRANSA_CHICKEN2, val);
2040
2041         val = TRANS_ENABLE;
2042         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2043
2044         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045             PIPECONF_INTERLACED_ILK)
2046                 val |= TRANS_INTERLACED;
2047         else
2048                 val |= TRANS_PROGRESSIVE;
2049
2050         I915_WRITE(LPT_TRANSCONF, val);
2051         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2052                 DRM_ERROR("Failed to enable PCH transcoder\n");
2053 }
2054
2055 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056                                             enum pipe pipe)
2057 {
2058         struct drm_device *dev = dev_priv->dev;
2059         uint32_t reg, val;
2060
2061         /* FDI relies on the transcoder */
2062         assert_fdi_tx_disabled(dev_priv, pipe);
2063         assert_fdi_rx_disabled(dev_priv, pipe);
2064
2065         /* Ports must be off as well */
2066         assert_pch_ports_disabled(dev_priv, pipe);
2067
2068         reg = PCH_TRANSCONF(pipe);
2069         val = I915_READ(reg);
2070         val &= ~TRANS_ENABLE;
2071         I915_WRITE(reg, val);
2072         /* wait for PCH transcoder off, transcoder state */
2073         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2074                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2075
2076         if (!HAS_PCH_IBX(dev)) {
2077                 /* Workaround: Clear the timing override chicken bit again. */
2078                 reg = TRANS_CHICKEN2(pipe);
2079                 val = I915_READ(reg);
2080                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081                 I915_WRITE(reg, val);
2082         }
2083 }
2084
2085 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2086 {
2087         u32 val;
2088
2089         val = I915_READ(LPT_TRANSCONF);
2090         val &= ~TRANS_ENABLE;
2091         I915_WRITE(LPT_TRANSCONF, val);
2092         /* wait for PCH transcoder off, transcoder state */
2093         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2094                 DRM_ERROR("Failed to disable PCH transcoder\n");
2095
2096         /* Workaround: clear timing override bit. */
2097         val = I915_READ(_TRANSA_CHICKEN2);
2098         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2099         I915_WRITE(_TRANSA_CHICKEN2, val);
2100 }
2101
2102 /**
2103  * intel_enable_pipe - enable a pipe, asserting requirements
2104  * @crtc: crtc responsible for the pipe
2105  *
2106  * Enable @crtc's pipe, making sure that various hardware specific requirements
2107  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2108  */
2109 static void intel_enable_pipe(struct intel_crtc *crtc)
2110 {
2111         struct drm_device *dev = crtc->base.dev;
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113         enum pipe pipe = crtc->pipe;
2114         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115                                                                       pipe);
2116         enum pipe pch_transcoder;
2117         int reg;
2118         u32 val;
2119
2120         assert_planes_disabled(dev_priv, pipe);
2121         assert_cursor_disabled(dev_priv, pipe);
2122         assert_sprites_disabled(dev_priv, pipe);
2123
2124         if (HAS_PCH_LPT(dev_priv->dev))
2125                 pch_transcoder = TRANSCODER_A;
2126         else
2127                 pch_transcoder = pipe;
2128
2129         /*
2130          * A pipe without a PLL won't actually be able to drive bits from
2131          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2132          * need the check.
2133          */
2134         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2136                         assert_dsi_pll_enabled(dev_priv);
2137                 else
2138                         assert_pll_enabled(dev_priv, pipe);
2139         else {
2140                 if (crtc->config->has_pch_encoder) {
2141                         /* if driving the PCH, we need FDI enabled */
2142                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143                         assert_fdi_tx_pll_enabled(dev_priv,
2144                                                   (enum pipe) cpu_transcoder);
2145                 }
2146                 /* FIXME: assert CPU port conditions for SNB+ */
2147         }
2148
2149         reg = PIPECONF(cpu_transcoder);
2150         val = I915_READ(reg);
2151         if (val & PIPECONF_ENABLE) {
2152                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154                 return;
2155         }
2156
2157         I915_WRITE(reg, val | PIPECONF_ENABLE);
2158         POSTING_READ(reg);
2159 }
2160
2161 /**
2162  * intel_disable_pipe - disable a pipe, asserting requirements
2163  * @crtc: crtc whose pipes is to be disabled
2164  *
2165  * Disable the pipe of @crtc, making sure that various hardware
2166  * specific requirements are met, if applicable, e.g. plane
2167  * disabled, panel fitter off, etc.
2168  *
2169  * Will wait until the pipe has shut down before returning.
2170  */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175         enum pipe pipe = crtc->pipe;
2176         int reg;
2177         u32 val;
2178
2179         /*
2180          * Make sure planes won't keep trying to pump pixels to us,
2181          * or we might hang the display.
2182          */
2183         assert_planes_disabled(dev_priv, pipe);
2184         assert_cursor_disabled(dev_priv, pipe);
2185         assert_sprites_disabled(dev_priv, pipe);
2186
2187         reg = PIPECONF(cpu_transcoder);
2188         val = I915_READ(reg);
2189         if ((val & PIPECONF_ENABLE) == 0)
2190                 return;
2191
2192         /*
2193          * Double wide has implications for planes
2194          * so best keep it disabled when not needed.
2195          */
2196         if (crtc->config->double_wide)
2197                 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199         /* Don't disable pipe or pipe PLLs if needed */
2200         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202                 val &= ~PIPECONF_ENABLE;
2203
2204         I915_WRITE(reg, val);
2205         if ((val & PIPECONF_ENABLE) == 0)
2206                 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 /*
2210  * Plane regs are double buffered, going from enabled->disabled needs a
2211  * trigger in order to latch.  The display address reg provides this.
2212  */
2213 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214                                enum plane plane)
2215 {
2216         struct drm_device *dev = dev_priv->dev;
2217         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2218
2219         I915_WRITE(reg, I915_READ(reg));
2220         POSTING_READ(reg);
2221 }
2222
2223 /**
2224  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2225  * @plane:  plane to be enabled
2226  * @crtc: crtc for the plane
2227  *
2228  * Enable @plane on @crtc, making sure that the pipe is running first.
2229  */
2230 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231                                           struct drm_crtc *crtc)
2232 {
2233         struct drm_device *dev = plane->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236
2237         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2238         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2239         to_intel_plane_state(plane->state)->visible = true;
2240
2241         dev_priv->display.update_primary_plane(crtc, plane->fb,
2242                                                crtc->x, crtc->y);
2243 }
2244
2245 static bool need_vtd_wa(struct drm_device *dev)
2246 {
2247 #ifdef CONFIG_INTEL_IOMMU
2248         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249                 return true;
2250 #endif
2251         return false;
2252 }
2253
2254 unsigned int
2255 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256                   uint64_t fb_format_modifier)
2257 {
2258         unsigned int tile_height;
2259         uint32_t pixel_bytes;
2260
2261         switch (fb_format_modifier) {
2262         case DRM_FORMAT_MOD_NONE:
2263                 tile_height = 1;
2264                 break;
2265         case I915_FORMAT_MOD_X_TILED:
2266                 tile_height = IS_GEN2(dev) ? 16 : 8;
2267                 break;
2268         case I915_FORMAT_MOD_Y_TILED:
2269                 tile_height = 32;
2270                 break;
2271         case I915_FORMAT_MOD_Yf_TILED:
2272                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273                 switch (pixel_bytes) {
2274                 default:
2275                 case 1:
2276                         tile_height = 64;
2277                         break;
2278                 case 2:
2279                 case 4:
2280                         tile_height = 32;
2281                         break;
2282                 case 8:
2283                         tile_height = 16;
2284                         break;
2285                 case 16:
2286                         WARN_ONCE(1,
2287                                   "128-bit pixels are not supported for display!");
2288                         tile_height = 16;
2289                         break;
2290                 }
2291                 break;
2292         default:
2293                 MISSING_CASE(fb_format_modifier);
2294                 tile_height = 1;
2295                 break;
2296         }
2297
2298         return tile_height;
2299 }
2300
2301 unsigned int
2302 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303                       uint32_t pixel_format, uint64_t fb_format_modifier)
2304 {
2305         return ALIGN(height, intel_tile_height(dev, pixel_format,
2306                                                fb_format_modifier));
2307 }
2308
2309 static int
2310 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311                         const struct drm_plane_state *plane_state)
2312 {
2313         struct intel_rotation_info *info = &view->rotation_info;
2314
2315         *view = i915_ggtt_view_normal;
2316
2317         if (!plane_state)
2318                 return 0;
2319
2320         if (!intel_rotation_90_or_270(plane_state->rotation))
2321                 return 0;
2322
2323         *view = i915_ggtt_view_rotated;
2324
2325         info->height = fb->height;
2326         info->pixel_format = fb->pixel_format;
2327         info->pitch = fb->pitches[0];
2328         info->fb_modifier = fb->modifier[0];
2329
2330         return 0;
2331 }
2332
2333 int
2334 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335                            struct drm_framebuffer *fb,
2336                            const struct drm_plane_state *plane_state,
2337                            struct intel_engine_cs *pipelined)
2338 {
2339         struct drm_device *dev = fb->dev;
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2342         struct i915_ggtt_view view;
2343         u32 alignment;
2344         int ret;
2345
2346         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
2348         switch (fb->modifier[0]) {
2349         case DRM_FORMAT_MOD_NONE:
2350                 if (INTEL_INFO(dev)->gen >= 9)
2351                         alignment = 256 * 1024;
2352                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2353                         alignment = 128 * 1024;
2354                 else if (INTEL_INFO(dev)->gen >= 4)
2355                         alignment = 4 * 1024;
2356                 else
2357                         alignment = 64 * 1024;
2358                 break;
2359         case I915_FORMAT_MOD_X_TILED:
2360                 if (INTEL_INFO(dev)->gen >= 9)
2361                         alignment = 256 * 1024;
2362                 else {
2363                         /* pin() will align the object as required by fence */
2364                         alignment = 0;
2365                 }
2366                 break;
2367         case I915_FORMAT_MOD_Y_TILED:
2368         case I915_FORMAT_MOD_Yf_TILED:
2369                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370                           "Y tiling bo slipped through, driver bug!\n"))
2371                         return -EINVAL;
2372                 alignment = 1 * 1024 * 1024;
2373                 break;
2374         default:
2375                 MISSING_CASE(fb->modifier[0]);
2376                 return -EINVAL;
2377         }
2378
2379         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380         if (ret)
2381                 return ret;
2382
2383         /* Note that the w/a also requires 64 PTE of padding following the
2384          * bo. We currently fill all unused PTE with the shadow page and so
2385          * we should always have valid PTE following the scanout preventing
2386          * the VT-d warning.
2387          */
2388         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389                 alignment = 256 * 1024;
2390
2391         /*
2392          * Global gtt pte registers are special registers which actually forward
2393          * writes to a chunk of system memory. Which means that there is no risk
2394          * that the register values disappear as soon as we call
2395          * intel_runtime_pm_put(), so it is correct to wrap only the
2396          * pin/unpin/fence and not more.
2397          */
2398         intel_runtime_pm_get(dev_priv);
2399
2400         dev_priv->mm.interruptible = false;
2401         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2402                                                    &view);
2403         if (ret)
2404                 goto err_interruptible;
2405
2406         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407          * fence, whereas 965+ only requires a fence if using
2408          * framebuffer compression.  For simplicity, we always install
2409          * a fence as the cost is not that onerous.
2410          */
2411         ret = i915_gem_object_get_fence(obj);
2412         if (ret)
2413                 goto err_unpin;
2414
2415         i915_gem_object_pin_fence(obj);
2416
2417         dev_priv->mm.interruptible = true;
2418         intel_runtime_pm_put(dev_priv);
2419         return 0;
2420
2421 err_unpin:
2422         i915_gem_object_unpin_from_display_plane(obj, &view);
2423 err_interruptible:
2424         dev_priv->mm.interruptible = true;
2425         intel_runtime_pm_put(dev_priv);
2426         return ret;
2427 }
2428
2429 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430                                const struct drm_plane_state *plane_state)
2431 {
2432         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2433         struct i915_ggtt_view view;
2434         int ret;
2435
2436         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
2438         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439         WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
2441         i915_gem_object_unpin_fence(obj);
2442         i915_gem_object_unpin_from_display_plane(obj, &view);
2443 }
2444
2445 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446  * is assumed to be a power-of-two. */
2447 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448                                              unsigned int tiling_mode,
2449                                              unsigned int cpp,
2450                                              unsigned int pitch)
2451 {
2452         if (tiling_mode != I915_TILING_NONE) {
2453                 unsigned int tile_rows, tiles;
2454
2455                 tile_rows = *y / 8;
2456                 *y %= 8;
2457
2458                 tiles = *x / (512/cpp);
2459                 *x %= 512/cpp;
2460
2461                 return tile_rows * pitch * 8 + tiles * 4096;
2462         } else {
2463                 unsigned int offset;
2464
2465                 offset = *y * pitch + *x * cpp;
2466                 *y = 0;
2467                 *x = (offset & 4095) / cpp;
2468                 return offset & -4096;
2469         }
2470 }
2471
2472 static int i9xx_format_to_fourcc(int format)
2473 {
2474         switch (format) {
2475         case DISPPLANE_8BPP:
2476                 return DRM_FORMAT_C8;
2477         case DISPPLANE_BGRX555:
2478                 return DRM_FORMAT_XRGB1555;
2479         case DISPPLANE_BGRX565:
2480                 return DRM_FORMAT_RGB565;
2481         default:
2482         case DISPPLANE_BGRX888:
2483                 return DRM_FORMAT_XRGB8888;
2484         case DISPPLANE_RGBX888:
2485                 return DRM_FORMAT_XBGR8888;
2486         case DISPPLANE_BGRX101010:
2487                 return DRM_FORMAT_XRGB2101010;
2488         case DISPPLANE_RGBX101010:
2489                 return DRM_FORMAT_XBGR2101010;
2490         }
2491 }
2492
2493 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494 {
2495         switch (format) {
2496         case PLANE_CTL_FORMAT_RGB_565:
2497                 return DRM_FORMAT_RGB565;
2498         default:
2499         case PLANE_CTL_FORMAT_XRGB_8888:
2500                 if (rgb_order) {
2501                         if (alpha)
2502                                 return DRM_FORMAT_ABGR8888;
2503                         else
2504                                 return DRM_FORMAT_XBGR8888;
2505                 } else {
2506                         if (alpha)
2507                                 return DRM_FORMAT_ARGB8888;
2508                         else
2509                                 return DRM_FORMAT_XRGB8888;
2510                 }
2511         case PLANE_CTL_FORMAT_XRGB_2101010:
2512                 if (rgb_order)
2513                         return DRM_FORMAT_XBGR2101010;
2514                 else
2515                         return DRM_FORMAT_XRGB2101010;
2516         }
2517 }
2518
2519 static bool
2520 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521                               struct intel_initial_plane_config *plane_config)
2522 {
2523         struct drm_device *dev = crtc->base.dev;
2524         struct drm_i915_gem_object *obj = NULL;
2525         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526         struct drm_framebuffer *fb = &plane_config->fb->base;
2527         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529                                     PAGE_SIZE);
2530
2531         size_aligned -= base_aligned;
2532
2533         if (plane_config->size == 0)
2534                 return false;
2535
2536         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537                                                              base_aligned,
2538                                                              base_aligned,
2539                                                              size_aligned);
2540         if (!obj)
2541                 return false;
2542
2543         obj->tiling_mode = plane_config->tiling;
2544         if (obj->tiling_mode == I915_TILING_X)
2545                 obj->stride = fb->pitches[0];
2546
2547         mode_cmd.pixel_format = fb->pixel_format;
2548         mode_cmd.width = fb->width;
2549         mode_cmd.height = fb->height;
2550         mode_cmd.pitches[0] = fb->pitches[0];
2551         mode_cmd.modifier[0] = fb->modifier[0];
2552         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2553
2554         mutex_lock(&dev->struct_mutex);
2555         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2556                                    &mode_cmd, obj)) {
2557                 DRM_DEBUG_KMS("intel fb init failed\n");
2558                 goto out_unref_obj;
2559         }
2560         mutex_unlock(&dev->struct_mutex);
2561
2562         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2563         return true;
2564
2565 out_unref_obj:
2566         drm_gem_object_unreference(&obj->base);
2567         mutex_unlock(&dev->struct_mutex);
2568         return false;
2569 }
2570
2571 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2572 static void
2573 update_state_fb(struct drm_plane *plane)
2574 {
2575         if (plane->fb == plane->state->fb)
2576                 return;
2577
2578         if (plane->state->fb)
2579                 drm_framebuffer_unreference(plane->state->fb);
2580         plane->state->fb = plane->fb;
2581         if (plane->state->fb)
2582                 drm_framebuffer_reference(plane->state->fb);
2583 }
2584
2585 static void
2586 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587                              struct intel_initial_plane_config *plane_config)
2588 {
2589         struct drm_device *dev = intel_crtc->base.dev;
2590         struct drm_i915_private *dev_priv = dev->dev_private;
2591         struct drm_crtc *c;
2592         struct intel_crtc *i;
2593         struct drm_i915_gem_object *obj;
2594         struct drm_plane *primary = intel_crtc->base.primary;
2595         struct drm_framebuffer *fb;
2596
2597         if (!plane_config->fb)
2598                 return;
2599
2600         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2601                 fb = &plane_config->fb->base;
2602                 goto valid_fb;
2603         }
2604
2605         kfree(plane_config->fb);
2606
2607         /*
2608          * Failed to alloc the obj, check to see if we should share
2609          * an fb with another CRTC instead
2610          */
2611         for_each_crtc(dev, c) {
2612                 i = to_intel_crtc(c);
2613
2614                 if (c == &intel_crtc->base)
2615                         continue;
2616
2617                 if (!i->active)
2618                         continue;
2619
2620                 fb = c->primary->fb;
2621                 if (!fb)
2622                         continue;
2623
2624                 obj = intel_fb_obj(fb);
2625                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2626                         drm_framebuffer_reference(fb);
2627                         goto valid_fb;
2628                 }
2629         }
2630
2631         return;
2632
2633 valid_fb:
2634         obj = intel_fb_obj(fb);
2635         if (obj->tiling_mode != I915_TILING_NONE)
2636                 dev_priv->preserve_bios_swizzle = true;
2637
2638         primary->fb = fb;
2639         primary->state->crtc = &intel_crtc->base;
2640         primary->crtc = &intel_crtc->base;
2641         update_state_fb(primary);
2642         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2643 }
2644
2645 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646                                       struct drm_framebuffer *fb,
2647                                       int x, int y)
2648 {
2649         struct drm_device *dev = crtc->dev;
2650         struct drm_i915_private *dev_priv = dev->dev_private;
2651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2652         struct drm_plane *primary = crtc->primary;
2653         bool visible = to_intel_plane_state(primary->state)->visible;
2654         struct drm_i915_gem_object *obj;
2655         int plane = intel_crtc->plane;
2656         unsigned long linear_offset;
2657         u32 dspcntr;
2658         u32 reg = DSPCNTR(plane);
2659         int pixel_size;
2660
2661         if (!visible || !fb) {
2662                 I915_WRITE(reg, 0);
2663                 if (INTEL_INFO(dev)->gen >= 4)
2664                         I915_WRITE(DSPSURF(plane), 0);
2665                 else
2666                         I915_WRITE(DSPADDR(plane), 0);
2667                 POSTING_READ(reg);
2668                 return;
2669         }
2670
2671         obj = intel_fb_obj(fb);
2672         if (WARN_ON(obj == NULL))
2673                 return;
2674
2675         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
2677         dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
2679         dspcntr |= DISPLAY_PLANE_ENABLE;
2680
2681         if (INTEL_INFO(dev)->gen < 4) {
2682                 if (intel_crtc->pipe == PIPE_B)
2683                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685                 /* pipesrc and dspsize control the size that is scaled from,
2686                  * which should always be the user's requested size.
2687                  */
2688                 I915_WRITE(DSPSIZE(plane),
2689                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690                            (intel_crtc->config->pipe_src_w - 1));
2691                 I915_WRITE(DSPPOS(plane), 0);
2692         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693                 I915_WRITE(PRIMSIZE(plane),
2694                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695                            (intel_crtc->config->pipe_src_w - 1));
2696                 I915_WRITE(PRIMPOS(plane), 0);
2697                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2698         }
2699
2700         switch (fb->pixel_format) {
2701         case DRM_FORMAT_C8:
2702                 dspcntr |= DISPPLANE_8BPP;
2703                 break;
2704         case DRM_FORMAT_XRGB1555:
2705         case DRM_FORMAT_ARGB1555:
2706                 dspcntr |= DISPPLANE_BGRX555;
2707                 break;
2708         case DRM_FORMAT_RGB565:
2709                 dspcntr |= DISPPLANE_BGRX565;
2710                 break;
2711         case DRM_FORMAT_XRGB8888:
2712         case DRM_FORMAT_ARGB8888:
2713                 dspcntr |= DISPPLANE_BGRX888;
2714                 break;
2715         case DRM_FORMAT_XBGR8888:
2716         case DRM_FORMAT_ABGR8888:
2717                 dspcntr |= DISPPLANE_RGBX888;
2718                 break;
2719         case DRM_FORMAT_XRGB2101010:
2720         case DRM_FORMAT_ARGB2101010:
2721                 dspcntr |= DISPPLANE_BGRX101010;
2722                 break;
2723         case DRM_FORMAT_XBGR2101010:
2724         case DRM_FORMAT_ABGR2101010:
2725                 dspcntr |= DISPPLANE_RGBX101010;
2726                 break;
2727         default:
2728                 BUG();
2729         }
2730
2731         if (INTEL_INFO(dev)->gen >= 4 &&
2732             obj->tiling_mode != I915_TILING_NONE)
2733                 dspcntr |= DISPPLANE_TILED;
2734
2735         if (IS_G4X(dev))
2736                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738         linear_offset = y * fb->pitches[0] + x * pixel_size;
2739
2740         if (INTEL_INFO(dev)->gen >= 4) {
2741                 intel_crtc->dspaddr_offset =
2742                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2743                                                        pixel_size,
2744                                                        fb->pitches[0]);
2745                 linear_offset -= intel_crtc->dspaddr_offset;
2746         } else {
2747                 intel_crtc->dspaddr_offset = linear_offset;
2748         }
2749
2750         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2751                 dspcntr |= DISPPLANE_ROTATE_180;
2752
2753                 x += (intel_crtc->config->pipe_src_w - 1);
2754                 y += (intel_crtc->config->pipe_src_h - 1);
2755
2756                 /* Finding the last pixel of the last line of the display
2757                 data and adding to linear_offset*/
2758                 linear_offset +=
2759                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2761         }
2762
2763         I915_WRITE(reg, dspcntr);
2764
2765         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2766         if (INTEL_INFO(dev)->gen >= 4) {
2767                 I915_WRITE(DSPSURF(plane),
2768                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2769                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2770                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2771         } else
2772                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2773         POSTING_READ(reg);
2774 }
2775
2776 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777                                           struct drm_framebuffer *fb,
2778                                           int x, int y)
2779 {
2780         struct drm_device *dev = crtc->dev;
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783         struct drm_plane *primary = crtc->primary;
2784         bool visible = to_intel_plane_state(primary->state)->visible;
2785         struct drm_i915_gem_object *obj;
2786         int plane = intel_crtc->plane;
2787         unsigned long linear_offset;
2788         u32 dspcntr;
2789         u32 reg = DSPCNTR(plane);
2790         int pixel_size;
2791
2792         if (!visible || !fb) {
2793                 I915_WRITE(reg, 0);
2794                 I915_WRITE(DSPSURF(plane), 0);
2795                 POSTING_READ(reg);
2796                 return;
2797         }
2798
2799         obj = intel_fb_obj(fb);
2800         if (WARN_ON(obj == NULL))
2801                 return;
2802
2803         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
2805         dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
2807         dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812         switch (fb->pixel_format) {
2813         case DRM_FORMAT_C8:
2814                 dspcntr |= DISPPLANE_8BPP;
2815                 break;
2816         case DRM_FORMAT_RGB565:
2817                 dspcntr |= DISPPLANE_BGRX565;
2818                 break;
2819         case DRM_FORMAT_XRGB8888:
2820         case DRM_FORMAT_ARGB8888:
2821                 dspcntr |= DISPPLANE_BGRX888;
2822                 break;
2823         case DRM_FORMAT_XBGR8888:
2824         case DRM_FORMAT_ABGR8888:
2825                 dspcntr |= DISPPLANE_RGBX888;
2826                 break;
2827         case DRM_FORMAT_XRGB2101010:
2828         case DRM_FORMAT_ARGB2101010:
2829                 dspcntr |= DISPPLANE_BGRX101010;
2830                 break;
2831         case DRM_FORMAT_XBGR2101010:
2832         case DRM_FORMAT_ABGR2101010:
2833                 dspcntr |= DISPPLANE_RGBX101010;
2834                 break;
2835         default:
2836                 BUG();
2837         }
2838
2839         if (obj->tiling_mode != I915_TILING_NONE)
2840                 dspcntr |= DISPPLANE_TILED;
2841
2842         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2843                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2844
2845         linear_offset = y * fb->pitches[0] + x * pixel_size;
2846         intel_crtc->dspaddr_offset =
2847                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2848                                                pixel_size,
2849                                                fb->pitches[0]);
2850         linear_offset -= intel_crtc->dspaddr_offset;
2851         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852                 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855                         x += (intel_crtc->config->pipe_src_w - 1);
2856                         y += (intel_crtc->config->pipe_src_h - 1);
2857
2858                         /* Finding the last pixel of the last line of the display
2859                         data and adding to linear_offset*/
2860                         linear_offset +=
2861                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863                 }
2864         }
2865
2866         I915_WRITE(reg, dspcntr);
2867
2868         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869         I915_WRITE(DSPSURF(plane),
2870                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873         } else {
2874                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876         }
2877         POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881                               uint32_t pixel_format)
2882 {
2883         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885         /*
2886          * The stride is either expressed as a multiple of 64 bytes
2887          * chunks for linear buffers or in number of tiles for tiled
2888          * buffers.
2889          */
2890         switch (fb_modifier) {
2891         case DRM_FORMAT_MOD_NONE:
2892                 return 64;
2893         case I915_FORMAT_MOD_X_TILED:
2894                 if (INTEL_INFO(dev)->gen == 2)
2895                         return 128;
2896                 return 512;
2897         case I915_FORMAT_MOD_Y_TILED:
2898                 /* No need to check for old gens and Y tiling since this is
2899                  * about the display engine and those will be blocked before
2900                  * we get here.
2901                  */
2902                 return 128;
2903         case I915_FORMAT_MOD_Yf_TILED:
2904                 if (bits_per_pixel == 8)
2905                         return 64;
2906                 else
2907                         return 128;
2908         default:
2909                 MISSING_CASE(fb_modifier);
2910                 return 64;
2911         }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915                                      struct drm_i915_gem_object *obj)
2916 {
2917         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920                 view = &i915_ggtt_view_rotated;
2921
2922         return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926  * This function detaches (aka. unbinds) unused scalers in hardware
2927  */
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930         struct drm_device *dev;
2931         struct drm_i915_private *dev_priv;
2932         struct intel_crtc_scaler_state *scaler_state;
2933         int i;
2934
2935         if (!intel_crtc || !intel_crtc->config)
2936                 return;
2937
2938         dev = intel_crtc->base.dev;
2939         dev_priv = dev->dev_private;
2940         scaler_state = &intel_crtc->config->scaler_state;
2941
2942         /* loop through and disable scalers that aren't in use */
2943         for (i = 0; i < intel_crtc->num_scalers; i++) {
2944                 if (!scaler_state->scalers[i].in_use) {
2945                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950                 }
2951         }
2952 }
2953
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2955 {
2956         switch (pixel_format) {
2957         case DRM_FORMAT_C8:
2958                 return PLANE_CTL_FORMAT_INDEXED;
2959         case DRM_FORMAT_RGB565:
2960                 return PLANE_CTL_FORMAT_RGB_565;
2961         case DRM_FORMAT_XBGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963         case DRM_FORMAT_XRGB8888:
2964                 return PLANE_CTL_FORMAT_XRGB_8888;
2965         /*
2966          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967          * to be already pre-multiplied. We need to add a knob (or a different
2968          * DRM_FORMAT) for user-space to configure that.
2969          */
2970         case DRM_FORMAT_ABGR8888:
2971                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2972                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973         case DRM_FORMAT_ARGB8888:
2974                 return PLANE_CTL_FORMAT_XRGB_8888 |
2975                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2976         case DRM_FORMAT_XRGB2101010:
2977                 return PLANE_CTL_FORMAT_XRGB_2101010;
2978         case DRM_FORMAT_XBGR2101010:
2979                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2980         case DRM_FORMAT_YUYV:
2981                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2982         case DRM_FORMAT_YVYU:
2983                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2984         case DRM_FORMAT_UYVY:
2985                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2986         case DRM_FORMAT_VYUY:
2987                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2988         default:
2989                 MISSING_CASE(pixel_format);
2990         }
2991
2992         return 0;
2993 }
2994
2995 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2996 {
2997         switch (fb_modifier) {
2998         case DRM_FORMAT_MOD_NONE:
2999                 break;
3000         case I915_FORMAT_MOD_X_TILED:
3001                 return PLANE_CTL_TILED_X;
3002         case I915_FORMAT_MOD_Y_TILED:
3003                 return PLANE_CTL_TILED_Y;
3004         case I915_FORMAT_MOD_Yf_TILED:
3005                 return PLANE_CTL_TILED_YF;
3006         default:
3007                 MISSING_CASE(fb_modifier);
3008         }
3009
3010         return 0;
3011 }
3012
3013 u32 skl_plane_ctl_rotation(unsigned int rotation)
3014 {
3015         switch (rotation) {
3016         case BIT(DRM_ROTATE_0):
3017                 break;
3018         case BIT(DRM_ROTATE_90):
3019                 return PLANE_CTL_ROTATE_90;
3020         case BIT(DRM_ROTATE_180):
3021                 return PLANE_CTL_ROTATE_180;
3022         case BIT(DRM_ROTATE_270):
3023                 return PLANE_CTL_ROTATE_270;
3024         default:
3025                 MISSING_CASE(rotation);
3026         }
3027
3028         return 0;
3029 }
3030
3031 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3032                                          struct drm_framebuffer *fb,
3033                                          int x, int y)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         struct drm_plane *plane = crtc->primary;
3039         bool visible = to_intel_plane_state(plane->state)->visible;
3040         struct drm_i915_gem_object *obj;
3041         int pipe = intel_crtc->pipe;
3042         u32 plane_ctl, stride_div, stride;
3043         u32 tile_height, plane_offset, plane_size;
3044         unsigned int rotation;
3045         int x_offset, y_offset;
3046         unsigned long surf_addr;
3047         struct intel_crtc_state *crtc_state = intel_crtc->config;
3048         struct intel_plane_state *plane_state;
3049         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3050         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3051         int scaler_id = -1;
3052
3053         plane_state = to_intel_plane_state(plane->state);
3054
3055         if (!visible || !fb) {
3056                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3057                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3058                 POSTING_READ(PLANE_CTL(pipe, 0));
3059                 return;
3060         }
3061
3062         plane_ctl = PLANE_CTL_ENABLE |
3063                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3064                     PLANE_CTL_PIPE_CSC_ENABLE;
3065
3066         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3067         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3068         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3069
3070         rotation = plane->state->rotation;
3071         plane_ctl |= skl_plane_ctl_rotation(rotation);
3072
3073         obj = intel_fb_obj(fb);
3074         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3075                                                fb->pixel_format);
3076         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3077
3078         /*
3079          * FIXME: intel_plane_state->src, dst aren't set when transitional
3080          * update_plane helpers are called from legacy paths.
3081          * Once full atomic crtc is available, below check can be avoided.
3082          */
3083         if (drm_rect_width(&plane_state->src)) {
3084                 scaler_id = plane_state->scaler_id;
3085                 src_x = plane_state->src.x1 >> 16;
3086                 src_y = plane_state->src.y1 >> 16;
3087                 src_w = drm_rect_width(&plane_state->src) >> 16;
3088                 src_h = drm_rect_height(&plane_state->src) >> 16;
3089                 dst_x = plane_state->dst.x1;
3090                 dst_y = plane_state->dst.y1;
3091                 dst_w = drm_rect_width(&plane_state->dst);
3092                 dst_h = drm_rect_height(&plane_state->dst);
3093
3094                 WARN_ON(x != src_x || y != src_y);
3095         } else {
3096                 src_w = intel_crtc->config->pipe_src_w;
3097                 src_h = intel_crtc->config->pipe_src_h;
3098         }
3099
3100         if (intel_rotation_90_or_270(rotation)) {
3101                 /* stride = Surface height in tiles */
3102                 tile_height = intel_tile_height(dev, fb->pixel_format,
3103                                                 fb->modifier[0]);
3104                 stride = DIV_ROUND_UP(fb->height, tile_height);
3105                 x_offset = stride * tile_height - y - src_h;
3106                 y_offset = x;
3107                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3108         } else {
3109                 stride = fb->pitches[0] / stride_div;
3110                 x_offset = x;
3111                 y_offset = y;
3112                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3113         }
3114         plane_offset = y_offset << 16 | x_offset;
3115
3116         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3117         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3118         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3119         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3120
3121         if (scaler_id >= 0) {
3122                 uint32_t ps_ctrl = 0;
3123
3124                 WARN_ON(!dst_w || !dst_h);
3125                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3126                         crtc_state->scaler_state.scalers[scaler_id].mode;
3127                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3128                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3129                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3130                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3131                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3132         } else {
3133                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3134         }
3135
3136         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3137
3138         POSTING_READ(PLANE_SURF(pipe, 0));
3139 }
3140
3141 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3142 static int
3143 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3144                            int x, int y, enum mode_set_atomic state)
3145 {
3146         struct drm_device *dev = crtc->dev;
3147         struct drm_i915_private *dev_priv = dev->dev_private;
3148
3149         if (dev_priv->display.disable_fbc)
3150                 dev_priv->display.disable_fbc(dev);
3151
3152         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3153
3154         return 0;
3155 }
3156
3157 static void intel_complete_page_flips(struct drm_device *dev)
3158 {
3159         struct drm_crtc *crtc;
3160
3161         for_each_crtc(dev, crtc) {
3162                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163                 enum plane plane = intel_crtc->plane;
3164
3165                 intel_prepare_page_flip(dev, plane);
3166                 intel_finish_page_flip_plane(dev, plane);
3167         }
3168 }
3169
3170 static void intel_update_primary_planes(struct drm_device *dev)
3171 {
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct drm_crtc *crtc;
3174
3175         for_each_crtc(dev, crtc) {
3176                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177
3178                 drm_modeset_lock(&crtc->mutex, NULL);
3179                 /*
3180                  * FIXME: Once we have proper support for primary planes (and
3181                  * disabling them without disabling the entire crtc) allow again
3182                  * a NULL crtc->primary->fb.
3183                  */
3184                 if (intel_crtc->active && crtc->primary->fb)
3185                         dev_priv->display.update_primary_plane(crtc,
3186                                                                crtc->primary->fb,
3187                                                                crtc->x,
3188                                                                crtc->y);
3189                 drm_modeset_unlock(&crtc->mutex);
3190         }
3191 }
3192
3193 void intel_crtc_reset(struct intel_crtc *crtc)
3194 {
3195         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3196
3197         if (!crtc->active)
3198                 return;
3199
3200         intel_crtc_disable_planes(&crtc->base);
3201         dev_priv->display.crtc_disable(&crtc->base);
3202         dev_priv->display.crtc_enable(&crtc->base);
3203         intel_crtc_enable_planes(&crtc->base);
3204 }
3205
3206 void intel_prepare_reset(struct drm_device *dev)
3207 {
3208         struct drm_i915_private *dev_priv = to_i915(dev);
3209         struct intel_crtc *crtc;
3210
3211         /* no reset support for gen2 */
3212         if (IS_GEN2(dev))
3213                 return;
3214
3215         /* reset doesn't touch the display */
3216         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3217                 return;
3218
3219         drm_modeset_lock_all(dev);
3220
3221         /*
3222          * Disabling the crtcs gracefully seems nicer. Also the
3223          * g33 docs say we should at least disable all the planes.
3224          */
3225         for_each_intel_crtc(dev, crtc) {
3226                 if (!crtc->active)
3227                         continue;
3228
3229                 intel_crtc_disable_planes(&crtc->base);
3230                 dev_priv->display.crtc_disable(&crtc->base);
3231         }
3232 }
3233
3234 void intel_finish_reset(struct drm_device *dev)
3235 {
3236         struct drm_i915_private *dev_priv = to_i915(dev);
3237
3238         /*
3239          * Flips in the rings will be nuked by the reset,
3240          * so complete all pending flips so that user space
3241          * will get its events and not get stuck.
3242          */
3243         intel_complete_page_flips(dev);
3244
3245         /* no reset support for gen2 */
3246         if (IS_GEN2(dev))
3247                 return;
3248
3249         /* reset doesn't touch the display */
3250         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3251                 /*
3252                  * Flips in the rings have been nuked by the reset,
3253                  * so update the base address of all primary
3254                  * planes to the the last fb to make sure we're
3255                  * showing the correct fb after a reset.
3256                  */
3257                 intel_update_primary_planes(dev);
3258                 return;
3259         }
3260
3261         /*
3262          * The display has been reset as well,
3263          * so need a full re-initialization.
3264          */
3265         intel_runtime_pm_disable_interrupts(dev_priv);
3266         intel_runtime_pm_enable_interrupts(dev_priv);
3267
3268         intel_modeset_init_hw(dev);
3269
3270         spin_lock_irq(&dev_priv->irq_lock);
3271         if (dev_priv->display.hpd_irq_setup)
3272                 dev_priv->display.hpd_irq_setup(dev);
3273         spin_unlock_irq(&dev_priv->irq_lock);
3274
3275         intel_modeset_setup_hw_state(dev, true);
3276
3277         intel_hpd_init(dev_priv);
3278
3279         drm_modeset_unlock_all(dev);
3280 }
3281
3282 static void
3283 intel_finish_fb(struct drm_framebuffer *old_fb)
3284 {
3285         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3286         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3287         bool was_interruptible = dev_priv->mm.interruptible;
3288         int ret;
3289
3290         /* Big Hammer, we also need to ensure that any pending
3291          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3292          * current scanout is retired before unpinning the old
3293          * framebuffer. Note that we rely on userspace rendering
3294          * into the buffer attached to the pipe they are waiting
3295          * on. If not, userspace generates a GPU hang with IPEHR
3296          * point to the MI_WAIT_FOR_EVENT.
3297          *
3298          * This should only fail upon a hung GPU, in which case we
3299          * can safely continue.
3300          */
3301         dev_priv->mm.interruptible = false;
3302         ret = i915_gem_object_wait_rendering(obj, true);
3303         dev_priv->mm.interruptible = was_interruptible;
3304
3305         WARN_ON(ret);
3306 }
3307
3308 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3309 {
3310         struct drm_device *dev = crtc->dev;
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3313         bool pending;
3314
3315         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3316             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3317                 return false;
3318
3319         spin_lock_irq(&dev->event_lock);
3320         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3321         spin_unlock_irq(&dev->event_lock);
3322
3323         return pending;
3324 }
3325
3326 static void intel_update_pipe_size(struct intel_crtc *crtc)
3327 {
3328         struct drm_device *dev = crtc->base.dev;
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         const struct drm_display_mode *adjusted_mode;
3331
3332         if (!i915.fastboot)
3333                 return;
3334
3335         /*
3336          * Update pipe size and adjust fitter if needed: the reason for this is
3337          * that in compute_mode_changes we check the native mode (not the pfit
3338          * mode) to see if we can flip rather than do a full mode set. In the
3339          * fastboot case, we'll flip, but if we don't update the pipesrc and
3340          * pfit state, we'll end up with a big fb scanned out into the wrong
3341          * sized surface.
3342          *
3343          * To fix this properly, we need to hoist the checks up into
3344          * compute_mode_changes (or above), check the actual pfit state and
3345          * whether the platform allows pfit disable with pipe active, and only
3346          * then update the pipesrc and pfit state, even on the flip path.
3347          */
3348
3349         adjusted_mode = &crtc->config->base.adjusted_mode;
3350
3351         I915_WRITE(PIPESRC(crtc->pipe),
3352                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3353                    (adjusted_mode->crtc_vdisplay - 1));
3354         if (!crtc->config->pch_pfit.enabled &&
3355             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3356              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3357                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3358                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3359                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3360         }
3361         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3362         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3363 }
3364
3365 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3366 {
3367         struct drm_device *dev = crtc->dev;
3368         struct drm_i915_private *dev_priv = dev->dev_private;
3369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370         int pipe = intel_crtc->pipe;
3371         u32 reg, temp;
3372
3373         /* enable normal train */
3374         reg = FDI_TX_CTL(pipe);
3375         temp = I915_READ(reg);
3376         if (IS_IVYBRIDGE(dev)) {
3377                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3378                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3379         } else {
3380                 temp &= ~FDI_LINK_TRAIN_NONE;
3381                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3382         }
3383         I915_WRITE(reg, temp);
3384
3385         reg = FDI_RX_CTL(pipe);
3386         temp = I915_READ(reg);
3387         if (HAS_PCH_CPT(dev)) {
3388                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3390         } else {
3391                 temp &= ~FDI_LINK_TRAIN_NONE;
3392                 temp |= FDI_LINK_TRAIN_NONE;
3393         }
3394         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3395
3396         /* wait one idle pattern time */
3397         POSTING_READ(reg);
3398         udelay(1000);
3399
3400         /* IVB wants error correction enabled */
3401         if (IS_IVYBRIDGE(dev))
3402                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3403                            FDI_FE_ERRC_ENABLE);
3404 }
3405
3406 /* The FDI link training functions for ILK/Ibexpeak. */
3407 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3408 {
3409         struct drm_device *dev = crtc->dev;
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3412         int pipe = intel_crtc->pipe;
3413         u32 reg, temp, tries;
3414
3415         /* FDI needs bits from pipe first */
3416         assert_pipe_enabled(dev_priv, pipe);
3417
3418         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3419            for train result */
3420         reg = FDI_RX_IMR(pipe);
3421         temp = I915_READ(reg);
3422         temp &= ~FDI_RX_SYMBOL_LOCK;
3423         temp &= ~FDI_RX_BIT_LOCK;
3424         I915_WRITE(reg, temp);
3425         I915_READ(reg);
3426         udelay(150);
3427
3428         /* enable CPU FDI TX and PCH FDI RX */
3429         reg = FDI_TX_CTL(pipe);
3430         temp = I915_READ(reg);
3431         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3432         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3433         temp &= ~FDI_LINK_TRAIN_NONE;
3434         temp |= FDI_LINK_TRAIN_PATTERN_1;
3435         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3436
3437         reg = FDI_RX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         temp &= ~FDI_LINK_TRAIN_NONE;
3440         temp |= FDI_LINK_TRAIN_PATTERN_1;
3441         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3442
3443         POSTING_READ(reg);
3444         udelay(150);
3445
3446         /* Ironlake workaround, enable clock pointer after FDI enable*/
3447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3448         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3449                    FDI_RX_PHASE_SYNC_POINTER_EN);
3450
3451         reg = FDI_RX_IIR(pipe);
3452         for (tries = 0; tries < 5; tries++) {
3453                 temp = I915_READ(reg);
3454                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3455
3456                 if ((temp & FDI_RX_BIT_LOCK)) {
3457                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3458                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3459                         break;
3460                 }
3461         }
3462         if (tries == 5)
3463                 DRM_ERROR("FDI train 1 fail!\n");
3464
3465         /* Train 2 */
3466         reg = FDI_TX_CTL(pipe);
3467         temp = I915_READ(reg);
3468         temp &= ~FDI_LINK_TRAIN_NONE;
3469         temp |= FDI_LINK_TRAIN_PATTERN_2;
3470         I915_WRITE(reg, temp);
3471
3472         reg = FDI_RX_CTL(pipe);
3473         temp = I915_READ(reg);
3474         temp &= ~FDI_LINK_TRAIN_NONE;
3475         temp |= FDI_LINK_TRAIN_PATTERN_2;
3476         I915_WRITE(reg, temp);
3477
3478         POSTING_READ(reg);
3479         udelay(150);
3480
3481         reg = FDI_RX_IIR(pipe);
3482         for (tries = 0; tries < 5; tries++) {
3483                 temp = I915_READ(reg);
3484                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485
3486                 if (temp & FDI_RX_SYMBOL_LOCK) {
3487                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3488                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3489                         break;
3490                 }
3491         }
3492         if (tries == 5)
3493                 DRM_ERROR("FDI train 2 fail!\n");
3494
3495         DRM_DEBUG_KMS("FDI train done\n");
3496
3497 }
3498
3499 static const int snb_b_fdi_train_param[] = {
3500         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3501         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3502         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3503         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3504 };
3505
3506 /* The FDI link training functions for SNB/Cougarpoint. */
3507 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3508 {
3509         struct drm_device *dev = crtc->dev;
3510         struct drm_i915_private *dev_priv = dev->dev_private;
3511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3512         int pipe = intel_crtc->pipe;
3513         u32 reg, temp, i, retry;
3514
3515         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3516            for train result */
3517         reg = FDI_RX_IMR(pipe);
3518         temp = I915_READ(reg);
3519         temp &= ~FDI_RX_SYMBOL_LOCK;
3520         temp &= ~FDI_RX_BIT_LOCK;
3521         I915_WRITE(reg, temp);
3522
3523         POSTING_READ(reg);
3524         udelay(150);
3525
3526         /* enable CPU FDI TX and PCH FDI RX */
3527         reg = FDI_TX_CTL(pipe);
3528         temp = I915_READ(reg);
3529         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3530         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3531         temp &= ~FDI_LINK_TRAIN_NONE;
3532         temp |= FDI_LINK_TRAIN_PATTERN_1;
3533         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3534         /* SNB-B */
3535         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3536         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3537
3538         I915_WRITE(FDI_RX_MISC(pipe),
3539                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3540
3541         reg = FDI_RX_CTL(pipe);
3542         temp = I915_READ(reg);
3543         if (HAS_PCH_CPT(dev)) {
3544                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3545                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3546         } else {
3547                 temp &= ~FDI_LINK_TRAIN_NONE;
3548                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3549         }
3550         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3551
3552         POSTING_READ(reg);
3553         udelay(150);
3554
3555         for (i = 0; i < 4; i++) {
3556                 reg = FDI_TX_CTL(pipe);
3557                 temp = I915_READ(reg);
3558                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3559                 temp |= snb_b_fdi_train_param[i];
3560                 I915_WRITE(reg, temp);
3561
3562                 POSTING_READ(reg);
3563                 udelay(500);
3564
3565                 for (retry = 0; retry < 5; retry++) {
3566                         reg = FDI_RX_IIR(pipe);
3567                         temp = I915_READ(reg);
3568                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3569                         if (temp & FDI_RX_BIT_LOCK) {
3570                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3571                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3572                                 break;
3573                         }
3574                         udelay(50);
3575                 }
3576                 if (retry < 5)
3577                         break;
3578         }
3579         if (i == 4)
3580                 DRM_ERROR("FDI train 1 fail!\n");
3581
3582         /* Train 2 */
3583         reg = FDI_TX_CTL(pipe);
3584         temp = I915_READ(reg);
3585         temp &= ~FDI_LINK_TRAIN_NONE;
3586         temp |= FDI_LINK_TRAIN_PATTERN_2;
3587         if (IS_GEN6(dev)) {
3588                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3589                 /* SNB-B */
3590                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3591         }
3592         I915_WRITE(reg, temp);
3593
3594         reg = FDI_RX_CTL(pipe);
3595         temp = I915_READ(reg);
3596         if (HAS_PCH_CPT(dev)) {
3597                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3598                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3599         } else {
3600                 temp &= ~FDI_LINK_TRAIN_NONE;
3601                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3602         }
3603         I915_WRITE(reg, temp);
3604
3605         POSTING_READ(reg);
3606         udelay(150);
3607
3608         for (i = 0; i < 4; i++) {
3609                 reg = FDI_TX_CTL(pipe);
3610                 temp = I915_READ(reg);
3611                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3612                 temp |= snb_b_fdi_train_param[i];
3613                 I915_WRITE(reg, temp);
3614
3615                 POSTING_READ(reg);
3616                 udelay(500);
3617
3618                 for (retry = 0; retry < 5; retry++) {
3619                         reg = FDI_RX_IIR(pipe);
3620                         temp = I915_READ(reg);
3621                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3622                         if (temp & FDI_RX_SYMBOL_LOCK) {
3623                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3624                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3625                                 break;
3626                         }
3627                         udelay(50);
3628                 }
3629                 if (retry < 5)
3630                         break;
3631         }
3632         if (i == 4)
3633                 DRM_ERROR("FDI train 2 fail!\n");
3634
3635         DRM_DEBUG_KMS("FDI train done.\n");
3636 }
3637
3638 /* Manual link training for Ivy Bridge A0 parts */
3639 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         int pipe = intel_crtc->pipe;
3645         u32 reg, temp, i, j;
3646
3647         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3648            for train result */
3649         reg = FDI_RX_IMR(pipe);
3650         temp = I915_READ(reg);
3651         temp &= ~FDI_RX_SYMBOL_LOCK;
3652         temp &= ~FDI_RX_BIT_LOCK;
3653         I915_WRITE(reg, temp);
3654
3655         POSTING_READ(reg);
3656         udelay(150);
3657
3658         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3659                       I915_READ(FDI_RX_IIR(pipe)));
3660
3661         /* Try each vswing and preemphasis setting twice before moving on */
3662         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3663                 /* disable first in case we need to retry */
3664                 reg = FDI_TX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3667                 temp &= ~FDI_TX_ENABLE;
3668                 I915_WRITE(reg, temp);
3669
3670                 reg = FDI_RX_CTL(pipe);
3671                 temp = I915_READ(reg);
3672                 temp &= ~FDI_LINK_TRAIN_AUTO;
3673                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674                 temp &= ~FDI_RX_ENABLE;
3675                 I915_WRITE(reg, temp);
3676
3677                 /* enable CPU FDI TX and PCH FDI RX */
3678                 reg = FDI_TX_CTL(pipe);
3679                 temp = I915_READ(reg);
3680                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3681                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3682                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3683                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3684                 temp |= snb_b_fdi_train_param[j/2];
3685                 temp |= FDI_COMPOSITE_SYNC;
3686                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3687
3688                 I915_WRITE(FDI_RX_MISC(pipe),
3689                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3690
3691                 reg = FDI_RX_CTL(pipe);
3692                 temp = I915_READ(reg);
3693                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3694                 temp |= FDI_COMPOSITE_SYNC;
3695                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3696
3697                 POSTING_READ(reg);
3698                 udelay(1); /* should be 0.5us */
3699
3700                 for (i = 0; i < 4; i++) {
3701                         reg = FDI_RX_IIR(pipe);
3702                         temp = I915_READ(reg);
3703                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3704
3705                         if (temp & FDI_RX_BIT_LOCK ||
3706                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3707                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3708                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3709                                               i);
3710                                 break;
3711                         }
3712                         udelay(1); /* should be 0.5us */
3713                 }
3714                 if (i == 4) {
3715                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3716                         continue;
3717                 }
3718
3719                 /* Train 2 */
3720                 reg = FDI_TX_CTL(pipe);
3721                 temp = I915_READ(reg);
3722                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3723                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3724                 I915_WRITE(reg, temp);
3725
3726                 reg = FDI_RX_CTL(pipe);
3727                 temp = I915_READ(reg);
3728                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3729                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3730                 I915_WRITE(reg, temp);
3731
3732                 POSTING_READ(reg);
3733                 udelay(2); /* should be 1.5us */
3734
3735                 for (i = 0; i < 4; i++) {
3736                         reg = FDI_RX_IIR(pipe);
3737                         temp = I915_READ(reg);
3738                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3739
3740                         if (temp & FDI_RX_SYMBOL_LOCK ||
3741                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3742                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3743                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3744                                               i);
3745                                 goto train_done;
3746                         }
3747                         udelay(2); /* should be 1.5us */
3748                 }
3749                 if (i == 4)
3750                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3751         }
3752
3753 train_done:
3754         DRM_DEBUG_KMS("FDI train done.\n");
3755 }
3756
3757 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3758 {
3759         struct drm_device *dev = intel_crtc->base.dev;
3760         struct drm_i915_private *dev_priv = dev->dev_private;
3761         int pipe = intel_crtc->pipe;
3762         u32 reg, temp;
3763
3764
3765         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3766         reg = FDI_RX_CTL(pipe);
3767         temp = I915_READ(reg);
3768         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3769         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3770         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3771         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3772
3773         POSTING_READ(reg);
3774         udelay(200);
3775
3776         /* Switch from Rawclk to PCDclk */
3777         temp = I915_READ(reg);
3778         I915_WRITE(reg, temp | FDI_PCDCLK);
3779
3780         POSTING_READ(reg);
3781         udelay(200);
3782
3783         /* Enable CPU FDI TX PLL, always on for Ironlake */
3784         reg = FDI_TX_CTL(pipe);
3785         temp = I915_READ(reg);
3786         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3787                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3788
3789                 POSTING_READ(reg);
3790                 udelay(100);
3791         }
3792 }
3793
3794 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3795 {
3796         struct drm_device *dev = intel_crtc->base.dev;
3797         struct drm_i915_private *dev_priv = dev->dev_private;
3798         int pipe = intel_crtc->pipe;
3799         u32 reg, temp;
3800
3801         /* Switch from PCDclk to Rawclk */
3802         reg = FDI_RX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3805
3806         /* Disable CPU FDI TX PLL */
3807         reg = FDI_TX_CTL(pipe);
3808         temp = I915_READ(reg);
3809         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3810
3811         POSTING_READ(reg);
3812         udelay(100);
3813
3814         reg = FDI_RX_CTL(pipe);
3815         temp = I915_READ(reg);
3816         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3817
3818         /* Wait for the clocks to turn off. */
3819         POSTING_READ(reg);
3820         udelay(100);
3821 }
3822
3823 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3824 {
3825         struct drm_device *dev = crtc->dev;
3826         struct drm_i915_private *dev_priv = dev->dev_private;
3827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828         int pipe = intel_crtc->pipe;
3829         u32 reg, temp;
3830
3831         /* disable CPU FDI tx and PCH FDI rx */
3832         reg = FDI_TX_CTL(pipe);
3833         temp = I915_READ(reg);
3834         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3835         POSTING_READ(reg);
3836
3837         reg = FDI_RX_CTL(pipe);
3838         temp = I915_READ(reg);
3839         temp &= ~(0x7 << 16);
3840         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3841         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3842
3843         POSTING_READ(reg);
3844         udelay(100);
3845
3846         /* Ironlake workaround, disable clock pointer after downing FDI */
3847         if (HAS_PCH_IBX(dev))
3848                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3849
3850         /* still set train pattern 1 */
3851         reg = FDI_TX_CTL(pipe);
3852         temp = I915_READ(reg);
3853         temp &= ~FDI_LINK_TRAIN_NONE;
3854         temp |= FDI_LINK_TRAIN_PATTERN_1;
3855         I915_WRITE(reg, temp);
3856
3857         reg = FDI_RX_CTL(pipe);
3858         temp = I915_READ(reg);
3859         if (HAS_PCH_CPT(dev)) {
3860                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3861                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3862         } else {
3863                 temp &= ~FDI_LINK_TRAIN_NONE;
3864                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3865         }
3866         /* BPC in FDI rx is consistent with that in PIPECONF */
3867         temp &= ~(0x07 << 16);
3868         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3869         I915_WRITE(reg, temp);
3870
3871         POSTING_READ(reg);
3872         udelay(100);
3873 }
3874
3875 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3876 {
3877         struct intel_crtc *crtc;
3878
3879         /* Note that we don't need to be called with mode_config.lock here
3880          * as our list of CRTC objects is static for the lifetime of the
3881          * device and so cannot disappear as we iterate. Similarly, we can
3882          * happily treat the predicates as racy, atomic checks as userspace
3883          * cannot claim and pin a new fb without at least acquring the
3884          * struct_mutex and so serialising with us.
3885          */
3886         for_each_intel_crtc(dev, crtc) {
3887                 if (atomic_read(&crtc->unpin_work_count) == 0)
3888                         continue;
3889
3890                 if (crtc->unpin_work)
3891                         intel_wait_for_vblank(dev, crtc->pipe);
3892
3893                 return true;
3894         }
3895
3896         return false;
3897 }
3898
3899 static void page_flip_completed(struct intel_crtc *intel_crtc)
3900 {
3901         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3902         struct intel_unpin_work *work = intel_crtc->unpin_work;
3903
3904         /* ensure that the unpin work is consistent wrt ->pending. */
3905         smp_rmb();
3906         intel_crtc->unpin_work = NULL;
3907
3908         if (work->event)
3909                 drm_send_vblank_event(intel_crtc->base.dev,
3910                                       intel_crtc->pipe,
3911                                       work->event);
3912
3913         drm_crtc_vblank_put(&intel_crtc->base);
3914
3915         wake_up_all(&dev_priv->pending_flip_queue);
3916         queue_work(dev_priv->wq, &work->work);
3917
3918         trace_i915_flip_complete(intel_crtc->plane,
3919                                  work->pending_flip_obj);
3920 }
3921
3922 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3923 {
3924         struct drm_device *dev = crtc->dev;
3925         struct drm_i915_private *dev_priv = dev->dev_private;
3926
3927         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3928         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3929                                        !intel_crtc_has_pending_flip(crtc),
3930                                        60*HZ) == 0)) {
3931                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3932
3933                 spin_lock_irq(&dev->event_lock);
3934                 if (intel_crtc->unpin_work) {
3935                         WARN_ONCE(1, "Removing stuck page flip\n");
3936                         page_flip_completed(intel_crtc);
3937                 }
3938                 spin_unlock_irq(&dev->event_lock);
3939         }
3940
3941         if (crtc->primary->fb) {
3942                 mutex_lock(&dev->struct_mutex);
3943                 intel_finish_fb(crtc->primary->fb);
3944                 mutex_unlock(&dev->struct_mutex);
3945         }
3946 }
3947
3948 /* Program iCLKIP clock to the desired frequency */
3949 static void lpt_program_iclkip(struct drm_crtc *crtc)
3950 {
3951         struct drm_device *dev = crtc->dev;
3952         struct drm_i915_private *dev_priv = dev->dev_private;
3953         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3954         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3955         u32 temp;
3956
3957         mutex_lock(&dev_priv->dpio_lock);
3958
3959         /* It is necessary to ungate the pixclk gate prior to programming
3960          * the divisors, and gate it back when it is done.
3961          */
3962         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3963
3964         /* Disable SSCCTL */
3965         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3966                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3967                                 SBI_SSCCTL_DISABLE,
3968                         SBI_ICLK);
3969
3970         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3971         if (clock == 20000) {
3972                 auxdiv = 1;
3973                 divsel = 0x41;
3974                 phaseinc = 0x20;
3975         } else {
3976                 /* The iCLK virtual clock root frequency is in MHz,
3977                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3978                  * divisors, it is necessary to divide one by another, so we
3979                  * convert the virtual clock precision to KHz here for higher
3980                  * precision.
3981                  */
3982                 u32 iclk_virtual_root_freq = 172800 * 1000;
3983                 u32 iclk_pi_range = 64;
3984                 u32 desired_divisor, msb_divisor_value, pi_value;
3985
3986                 desired_divisor = (iclk_virtual_root_freq / clock);
3987                 msb_divisor_value = desired_divisor / iclk_pi_range;
3988                 pi_value = desired_divisor % iclk_pi_range;
3989
3990                 auxdiv = 0;
3991                 divsel = msb_divisor_value - 2;
3992                 phaseinc = pi_value;
3993         }
3994
3995         /* This should not happen with any sane values */
3996         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3997                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3998         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3999                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4000
4001         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4002                         clock,
4003                         auxdiv,
4004                         divsel,
4005                         phasedir,
4006                         phaseinc);
4007
4008         /* Program SSCDIVINTPHASE6 */
4009         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4010         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4011         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4012         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4013         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4014         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4015         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4016         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4017
4018         /* Program SSCAUXDIV */
4019         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4020         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4021         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4022         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4023
4024         /* Enable modulator and associated divider */
4025         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4026         temp &= ~SBI_SSCCTL_DISABLE;
4027         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4028
4029         /* Wait for initialization time */
4030         udelay(24);
4031
4032         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4033
4034         mutex_unlock(&dev_priv->dpio_lock);
4035 }
4036
4037 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4038                                                 enum pipe pch_transcoder)
4039 {
4040         struct drm_device *dev = crtc->base.dev;
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4043
4044         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4045                    I915_READ(HTOTAL(cpu_transcoder)));
4046         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4047                    I915_READ(HBLANK(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4049                    I915_READ(HSYNC(cpu_transcoder)));
4050
4051         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4052                    I915_READ(VTOTAL(cpu_transcoder)));
4053         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4054                    I915_READ(VBLANK(cpu_transcoder)));
4055         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4056                    I915_READ(VSYNC(cpu_transcoder)));
4057         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4058                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4059 }
4060
4061 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4062 {
4063         struct drm_i915_private *dev_priv = dev->dev_private;
4064         uint32_t temp;
4065
4066         temp = I915_READ(SOUTH_CHICKEN1);
4067         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4068                 return;
4069
4070         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4071         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4072
4073         temp &= ~FDI_BC_BIFURCATION_SELECT;
4074         if (enable)
4075                 temp |= FDI_BC_BIFURCATION_SELECT;
4076
4077         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4078         I915_WRITE(SOUTH_CHICKEN1, temp);
4079         POSTING_READ(SOUTH_CHICKEN1);
4080 }
4081
4082 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4083 {
4084         struct drm_device *dev = intel_crtc->base.dev;
4085
4086         switch (intel_crtc->pipe) {
4087         case PIPE_A:
4088                 break;
4089         case PIPE_B:
4090                 if (intel_crtc->config->fdi_lanes > 2)
4091                         cpt_set_fdi_bc_bifurcation(dev, false);
4092                 else
4093                         cpt_set_fdi_bc_bifurcation(dev, true);
4094
4095                 break;
4096         case PIPE_C:
4097                 cpt_set_fdi_bc_bifurcation(dev, true);
4098
4099                 break;
4100         default:
4101                 BUG();
4102         }
4103 }
4104
4105 /*
4106  * Enable PCH resources required for PCH ports:
4107  *   - PCH PLLs
4108  *   - FDI training & RX/TX
4109  *   - update transcoder timings
4110  *   - DP transcoding bits
4111  *   - transcoder
4112  */
4113 static void ironlake_pch_enable(struct drm_crtc *crtc)
4114 {
4115         struct drm_device *dev = crtc->dev;
4116         struct drm_i915_private *dev_priv = dev->dev_private;
4117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4118         int pipe = intel_crtc->pipe;
4119         u32 reg, temp;
4120
4121         assert_pch_transcoder_disabled(dev_priv, pipe);
4122
4123         if (IS_IVYBRIDGE(dev))
4124                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4125
4126         /* Write the TU size bits before fdi link training, so that error
4127          * detection works. */
4128         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4129                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4130
4131         /* For PCH output, training FDI link */
4132         dev_priv->display.fdi_link_train(crtc);
4133
4134         /* We need to program the right clock selection before writing the pixel
4135          * mutliplier into the DPLL. */
4136         if (HAS_PCH_CPT(dev)) {
4137                 u32 sel;
4138
4139                 temp = I915_READ(PCH_DPLL_SEL);
4140                 temp |= TRANS_DPLL_ENABLE(pipe);
4141                 sel = TRANS_DPLLB_SEL(pipe);
4142                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4143                         temp |= sel;
4144                 else
4145                         temp &= ~sel;
4146                 I915_WRITE(PCH_DPLL_SEL, temp);
4147         }
4148
4149         /* XXX: pch pll's can be enabled any time before we enable the PCH
4150          * transcoder, and we actually should do this to not upset any PCH
4151          * transcoder that already use the clock when we share it.
4152          *
4153          * Note that enable_shared_dpll tries to do the right thing, but
4154          * get_shared_dpll unconditionally resets the pll - we need that to have
4155          * the right LVDS enable sequence. */
4156         intel_enable_shared_dpll(intel_crtc);
4157
4158         /* set transcoder timing, panel must allow it */
4159         assert_panel_unlocked(dev_priv, pipe);
4160         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4161
4162         intel_fdi_normal_train(crtc);
4163
4164         /* For PCH DP, enable TRANS_DP_CTL */
4165         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4166                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4167                 reg = TRANS_DP_CTL(pipe);
4168                 temp = I915_READ(reg);
4169                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4170                           TRANS_DP_SYNC_MASK |
4171                           TRANS_DP_BPC_MASK);
4172                 temp |= (TRANS_DP_OUTPUT_ENABLE |
4173                          TRANS_DP_ENH_FRAMING);
4174                 temp |= bpc << 9; /* same format but at 11:9 */
4175
4176                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4177                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4178                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4179                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4180
4181                 switch (intel_trans_dp_port_sel(crtc)) {
4182                 case PCH_DP_B:
4183                         temp |= TRANS_DP_PORT_SEL_B;
4184                         break;
4185                 case PCH_DP_C:
4186                         temp |= TRANS_DP_PORT_SEL_C;
4187                         break;
4188                 case PCH_DP_D:
4189                         temp |= TRANS_DP_PORT_SEL_D;
4190                         break;
4191                 default:
4192                         BUG();
4193                 }
4194
4195                 I915_WRITE(reg, temp);
4196         }
4197
4198         ironlake_enable_pch_transcoder(dev_priv, pipe);
4199 }
4200
4201 static void lpt_pch_enable(struct drm_crtc *crtc)
4202 {
4203         struct drm_device *dev = crtc->dev;
4204         struct drm_i915_private *dev_priv = dev->dev_private;
4205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4206         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4207
4208         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4209
4210         lpt_program_iclkip(crtc);
4211
4212         /* Set transcoder timing. */
4213         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4214
4215         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4216 }
4217
4218 void intel_put_shared_dpll(struct intel_crtc *crtc)
4219 {
4220         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4221
4222         if (pll == NULL)
4223                 return;
4224
4225         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4226                 WARN(1, "bad %s crtc mask\n", pll->name);
4227                 return;
4228         }
4229
4230         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4231         if (pll->config.crtc_mask == 0) {
4232                 WARN_ON(pll->on);
4233                 WARN_ON(pll->active);
4234         }
4235
4236         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4237 }
4238
4239 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4240                                                 struct intel_crtc_state *crtc_state)
4241 {
4242         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4243         struct intel_shared_dpll *pll;
4244         enum intel_dpll_id i;
4245
4246         if (HAS_PCH_IBX(dev_priv->dev)) {
4247                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4248                 i = (enum intel_dpll_id) crtc->pipe;
4249                 pll = &dev_priv->shared_dplls[i];
4250
4251                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4252                               crtc->base.base.id, pll->name);
4253
4254                 WARN_ON(pll->new_config->crtc_mask);
4255
4256                 goto found;
4257         }
4258
4259         if (IS_BROXTON(dev_priv->dev)) {
4260                 /* PLL is attached to port in bxt */
4261                 struct intel_encoder *encoder;
4262                 struct intel_digital_port *intel_dig_port;
4263
4264                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4265                 if (WARN_ON(!encoder))
4266                         return NULL;
4267
4268                 intel_dig_port = enc_to_dig_port(&encoder->base);
4269                 /* 1:1 mapping between ports and PLLs */
4270                 i = (enum intel_dpll_id)intel_dig_port->port;
4271                 pll = &dev_priv->shared_dplls[i];
4272                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4273                         crtc->base.base.id, pll->name);
4274                 WARN_ON(pll->new_config->crtc_mask);
4275
4276                 goto found;
4277         }
4278
4279         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4280                 pll = &dev_priv->shared_dplls[i];
4281
4282                 /* Only want to check enabled timings first */
4283                 if (pll->new_config->crtc_mask == 0)
4284                         continue;
4285
4286                 if (memcmp(&crtc_state->dpll_hw_state,
4287                            &pll->new_config->hw_state,
4288                            sizeof(pll->new_config->hw_state)) == 0) {
4289                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4290                                       crtc->base.base.id, pll->name,
4291                                       pll->new_config->crtc_mask,
4292                                       pll->active);
4293                         goto found;
4294                 }
4295         }
4296
4297         /* Ok no matching timings, maybe there's a free one? */
4298         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4299                 pll = &dev_priv->shared_dplls[i];
4300                 if (pll->new_config->crtc_mask == 0) {
4301                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4302                                       crtc->base.base.id, pll->name);
4303                         goto found;
4304                 }
4305         }
4306
4307         return NULL;
4308
4309 found:
4310         if (pll->new_config->crtc_mask == 0)
4311                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4312
4313         crtc_state->shared_dpll = i;
4314         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4315                          pipe_name(crtc->pipe));
4316
4317         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4318
4319         return pll;
4320 }
4321
4322 /**
4323  * intel_shared_dpll_start_config - start a new PLL staged config
4324  * @dev_priv: DRM device
4325  * @clear_pipes: mask of pipes that will have their PLLs freed
4326  *
4327  * Starts a new PLL staged config, copying the current config but
4328  * releasing the references of pipes specified in clear_pipes.
4329  */
4330 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4331                                           unsigned clear_pipes)
4332 {
4333         struct intel_shared_dpll *pll;
4334         enum intel_dpll_id i;
4335
4336         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4337                 pll = &dev_priv->shared_dplls[i];
4338
4339                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4340                                           GFP_KERNEL);
4341                 if (!pll->new_config)
4342                         goto cleanup;
4343
4344                 pll->new_config->crtc_mask &= ~clear_pipes;
4345         }
4346
4347         return 0;
4348
4349 cleanup:
4350         while (--i >= 0) {
4351                 pll = &dev_priv->shared_dplls[i];
4352                 kfree(pll->new_config);
4353                 pll->new_config = NULL;
4354         }
4355
4356         return -ENOMEM;
4357 }
4358
4359 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4360 {
4361         struct intel_shared_dpll *pll;
4362         enum intel_dpll_id i;
4363
4364         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365                 pll = &dev_priv->shared_dplls[i];
4366
4367                 WARN_ON(pll->new_config == &pll->config);
4368
4369                 pll->config = *pll->new_config;
4370                 kfree(pll->new_config);
4371                 pll->new_config = NULL;
4372         }
4373 }
4374
4375 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4376 {
4377         struct intel_shared_dpll *pll;
4378         enum intel_dpll_id i;
4379
4380         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4381                 pll = &dev_priv->shared_dplls[i];
4382
4383                 WARN_ON(pll->new_config == &pll->config);
4384
4385                 kfree(pll->new_config);
4386                 pll->new_config = NULL;
4387         }
4388 }
4389
4390 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4391 {
4392         struct drm_i915_private *dev_priv = dev->dev_private;
4393         int dslreg = PIPEDSL(pipe);
4394         u32 temp;
4395
4396         temp = I915_READ(dslreg);
4397         udelay(500);
4398         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4399                 if (wait_for(I915_READ(dslreg) != temp, 5))
4400                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4401         }
4402 }
4403
4404 /**
4405  * skl_update_scaler_users - Stages update to crtc's scaler state
4406  * @intel_crtc: crtc
4407  * @crtc_state: crtc_state
4408  * @plane: plane (NULL indicates crtc is requesting update)
4409  * @plane_state: plane's state
4410  * @force_detach: request unconditional detachment of scaler
4411  *
4412  * This function updates scaler state for requested plane or crtc.
4413  * To request scaler usage update for a plane, caller shall pass plane pointer.
4414  * To request scaler usage update for crtc, caller shall pass plane pointer
4415  * as NULL.
4416  *
4417  * Return
4418  *     0 - scaler_usage updated successfully
4419  *    error - requested scaling cannot be supported or other error condition
4420  */
4421 int
4422 skl_update_scaler_users(
4423         struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4424         struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4425         int force_detach)
4426 {
4427         int need_scaling;
4428         int idx;
4429         int src_w, src_h, dst_w, dst_h;
4430         int *scaler_id;
4431         struct drm_framebuffer *fb;
4432         struct intel_crtc_scaler_state *scaler_state;
4433         unsigned int rotation;
4434
4435         if (!intel_crtc || !crtc_state)
4436                 return 0;
4437
4438         scaler_state = &crtc_state->scaler_state;
4439
4440         idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4441         fb = intel_plane ? plane_state->base.fb : NULL;
4442
4443         if (intel_plane) {
4444                 src_w = drm_rect_width(&plane_state->src) >> 16;
4445                 src_h = drm_rect_height(&plane_state->src) >> 16;
4446                 dst_w = drm_rect_width(&plane_state->dst);
4447                 dst_h = drm_rect_height(&plane_state->dst);
4448                 scaler_id = &plane_state->scaler_id;
4449                 rotation = plane_state->base.rotation;
4450         } else {
4451                 struct drm_display_mode *adjusted_mode =
4452                         &crtc_state->base.adjusted_mode;
4453                 src_w = crtc_state->pipe_src_w;
4454                 src_h = crtc_state->pipe_src_h;
4455                 dst_w = adjusted_mode->hdisplay;
4456                 dst_h = adjusted_mode->vdisplay;
4457                 scaler_id = &scaler_state->scaler_id;
4458                 rotation = DRM_ROTATE_0;
4459         }
4460
4461         need_scaling = intel_rotation_90_or_270(rotation) ?
4462                 (src_h != dst_w || src_w != dst_h):
4463                 (src_w != dst_w || src_h != dst_h);
4464
4465         /*
4466          * if plane is being disabled or scaler is no more required or force detach
4467          *  - free scaler binded to this plane/crtc
4468          *  - in order to do this, update crtc->scaler_usage
4469          *
4470          * Here scaler state in crtc_state is set free so that
4471          * scaler can be assigned to other user. Actual register
4472          * update to free the scaler is done in plane/panel-fit programming.
4473          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4474          */
4475         if (force_detach || !need_scaling || (intel_plane &&
4476                 (!fb || !plane_state->visible))) {
4477                 if (*scaler_id >= 0) {
4478                         scaler_state->scaler_users &= ~(1 << idx);
4479                         scaler_state->scalers[*scaler_id].in_use = 0;
4480
4481                         DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4482                                 "crtc_state = %p scaler_users = 0x%x\n",
4483                                 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4484                                 intel_plane ? intel_plane->base.base.id :
4485                                 intel_crtc->base.base.id, crtc_state,
4486                                 scaler_state->scaler_users);
4487                         *scaler_id = -1;
4488                 }
4489                 return 0;
4490         }
4491
4492         /* range checks */
4493         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4494                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4495
4496                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4497                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4498                 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4499                         "size is out of scaler range\n",
4500                         intel_plane ? "PLANE" : "CRTC",
4501                         intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4502                         intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4503                 return -EINVAL;
4504         }
4505
4506         /* check colorkey */
4507         if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4508                 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4509                         intel_plane->base.base.id);
4510                 return -EINVAL;
4511         }
4512
4513         /* Check src format */
4514         if (intel_plane) {
4515                 switch (fb->pixel_format) {
4516                 case DRM_FORMAT_RGB565:
4517                 case DRM_FORMAT_XBGR8888:
4518                 case DRM_FORMAT_XRGB8888:
4519                 case DRM_FORMAT_ABGR8888:
4520                 case DRM_FORMAT_ARGB8888:
4521                 case DRM_FORMAT_XRGB2101010:
4522                 case DRM_FORMAT_ARGB2101010:
4523                 case DRM_FORMAT_XBGR2101010:
4524                 case DRM_FORMAT_ABGR2101010:
4525                 case DRM_FORMAT_YUYV:
4526                 case DRM_FORMAT_YVYU:
4527                 case DRM_FORMAT_UYVY:
4528                 case DRM_FORMAT_VYUY:
4529                         break;
4530                 default:
4531                         DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4532                                 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4533                         return -EINVAL;
4534                 }
4535         }
4536
4537         /* mark this plane as a scaler user in crtc_state */
4538         scaler_state->scaler_users |= (1 << idx);
4539         DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4540                 "crtc_state = %p scaler_users = 0x%x\n",
4541                 intel_plane ? "PLANE" : "CRTC",
4542                 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4543                 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4544         return 0;
4545 }
4546
4547 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4548 {
4549         struct drm_device *dev = crtc->base.dev;
4550         struct drm_i915_private *dev_priv = dev->dev_private;
4551         int pipe = crtc->pipe;
4552         struct intel_crtc_scaler_state *scaler_state =
4553                 &crtc->config->scaler_state;
4554
4555         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4556
4557         /* To update pfit, first update scaler state */
4558         skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4559         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4560         skl_detach_scalers(crtc);
4561         if (!enable)
4562                 return;
4563
4564         if (crtc->config->pch_pfit.enabled) {
4565                 int id;
4566
4567                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4568                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4569                         return;
4570                 }
4571
4572                 id = scaler_state->scaler_id;
4573                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4574                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4575                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4576                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4577
4578                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4579         }
4580 }
4581
4582 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4583 {
4584         struct drm_device *dev = crtc->base.dev;
4585         struct drm_i915_private *dev_priv = dev->dev_private;
4586         int pipe = crtc->pipe;
4587
4588         if (crtc->config->pch_pfit.enabled) {
4589                 /* Force use of hard-coded filter coefficients
4590                  * as some pre-programmed values are broken,
4591                  * e.g. x201.
4592                  */
4593                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4594                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4595                                                  PF_PIPE_SEL_IVB(pipe));
4596                 else
4597                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4598                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4599                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4600         }
4601 }
4602
4603 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4604 {
4605         struct drm_device *dev = crtc->dev;
4606         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4607         struct drm_plane *plane;
4608         struct intel_plane *intel_plane;
4609
4610         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4611                 intel_plane = to_intel_plane(plane);
4612                 if (intel_plane->pipe == pipe)
4613                         intel_plane_restore(&intel_plane->base);
4614         }
4615 }
4616
4617 void hsw_enable_ips(struct intel_crtc *crtc)
4618 {
4619         struct drm_device *dev = crtc->base.dev;
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621
4622         if (!crtc->config->ips_enabled)
4623                 return;
4624
4625         /* We can only enable IPS after we enable a plane and wait for a vblank */
4626         intel_wait_for_vblank(dev, crtc->pipe);
4627
4628         assert_plane_enabled(dev_priv, crtc->plane);
4629         if (IS_BROADWELL(dev)) {
4630                 mutex_lock(&dev_priv->rps.hw_lock);
4631                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4632                 mutex_unlock(&dev_priv->rps.hw_lock);
4633                 /* Quoting Art Runyan: "its not safe to expect any particular
4634                  * value in IPS_CTL bit 31 after enabling IPS through the
4635                  * mailbox." Moreover, the mailbox may return a bogus state,
4636                  * so we need to just enable it and continue on.
4637                  */
4638         } else {
4639                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4640                 /* The bit only becomes 1 in the next vblank, so this wait here
4641                  * is essentially intel_wait_for_vblank. If we don't have this
4642                  * and don't wait for vblanks until the end of crtc_enable, then
4643                  * the HW state readout code will complain that the expected
4644                  * IPS_CTL value is not the one we read. */
4645                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4646                         DRM_ERROR("Timed out waiting for IPS enable\n");
4647         }
4648 }
4649
4650 void hsw_disable_ips(struct intel_crtc *crtc)
4651 {
4652         struct drm_device *dev = crtc->base.dev;
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654
4655         if (!crtc->config->ips_enabled)
4656                 return;
4657
4658         assert_plane_enabled(dev_priv, crtc->plane);
4659         if (IS_BROADWELL(dev)) {
4660                 mutex_lock(&dev_priv->rps.hw_lock);
4661                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4662                 mutex_unlock(&dev_priv->rps.hw_lock);
4663                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4664                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4665                         DRM_ERROR("Timed out waiting for IPS disable\n");
4666         } else {
4667                 I915_WRITE(IPS_CTL, 0);
4668                 POSTING_READ(IPS_CTL);
4669         }
4670
4671         /* We need to wait for a vblank before we can disable the plane. */
4672         intel_wait_for_vblank(dev, crtc->pipe);
4673 }
4674
4675 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4676 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4677 {
4678         struct drm_device *dev = crtc->dev;
4679         struct drm_i915_private *dev_priv = dev->dev_private;
4680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4681         enum pipe pipe = intel_crtc->pipe;
4682         int palreg = PALETTE(pipe);
4683         int i;
4684         bool reenable_ips = false;
4685
4686         /* The clocks have to be on to load the palette. */
4687         if (!crtc->state->enable || !intel_crtc->active)
4688                 return;
4689
4690         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4691                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4692                         assert_dsi_pll_enabled(dev_priv);
4693                 else
4694                         assert_pll_enabled(dev_priv, pipe);
4695         }
4696
4697         /* use legacy palette for Ironlake */
4698         if (!HAS_GMCH_DISPLAY(dev))
4699                 palreg = LGC_PALETTE(pipe);
4700
4701         /* Workaround : Do not read or write the pipe palette/gamma data while
4702          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4703          */
4704         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4705             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4706              GAMMA_MODE_MODE_SPLIT)) {
4707                 hsw_disable_ips(intel_crtc);
4708                 reenable_ips = true;
4709         }
4710
4711         for (i = 0; i < 256; i++) {
4712                 I915_WRITE(palreg + 4 * i,
4713                            (intel_crtc->lut_r[i] << 16) |
4714                            (intel_crtc->lut_g[i] << 8) |
4715                            intel_crtc->lut_b[i]);
4716         }
4717
4718         if (reenable_ips)
4719                 hsw_enable_ips(intel_crtc);
4720 }
4721
4722 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4723 {
4724         if (intel_crtc->overlay) {
4725                 struct drm_device *dev = intel_crtc->base.dev;
4726                 struct drm_i915_private *dev_priv = dev->dev_private;
4727
4728                 mutex_lock(&dev->struct_mutex);
4729                 dev_priv->mm.interruptible = false;
4730                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4731                 dev_priv->mm.interruptible = true;
4732                 mutex_unlock(&dev->struct_mutex);
4733         }
4734
4735         /* Let userspace switch the overlay on again. In most cases userspace
4736          * has to recompute where to put it anyway.
4737          */
4738 }
4739
4740 /**
4741  * intel_post_enable_primary - Perform operations after enabling primary plane
4742  * @crtc: the CRTC whose primary plane was just enabled
4743  *
4744  * Performs potentially sleeping operations that must be done after the primary
4745  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4746  * called due to an explicit primary plane update, or due to an implicit
4747  * re-enable that is caused when a sprite plane is updated to no longer
4748  * completely hide the primary plane.
4749  */
4750 static void
4751 intel_post_enable_primary(struct drm_crtc *crtc)
4752 {
4753         struct drm_device *dev = crtc->dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756         int pipe = intel_crtc->pipe;
4757
4758         /*
4759          * BDW signals flip done immediately if the plane
4760          * is disabled, even if the plane enable is already
4761          * armed to occur at the next vblank :(
4762          */
4763         if (IS_BROADWELL(dev))
4764                 intel_wait_for_vblank(dev, pipe);
4765
4766         /*
4767          * FIXME IPS should be fine as long as one plane is
4768          * enabled, but in practice it seems to have problems
4769          * when going from primary only to sprite only and vice
4770          * versa.
4771          */
4772         hsw_enable_ips(intel_crtc);
4773
4774         mutex_lock(&dev->struct_mutex);
4775         intel_fbc_update(dev);
4776         mutex_unlock(&dev->struct_mutex);
4777
4778         /*
4779          * Gen2 reports pipe underruns whenever all planes are disabled.
4780          * So don't enable underrun reporting before at least some planes
4781          * are enabled.
4782          * FIXME: Need to fix the logic to work when we turn off all planes
4783          * but leave the pipe running.
4784          */
4785         if (IS_GEN2(dev))
4786                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4787
4788         /* Underruns don't raise interrupts, so check manually. */
4789         if (HAS_GMCH_DISPLAY(dev))
4790                 i9xx_check_fifo_underruns(dev_priv);
4791 }
4792
4793 /**
4794  * intel_pre_disable_primary - Perform operations before disabling primary plane
4795  * @crtc: the CRTC whose primary plane is to be disabled
4796  *
4797  * Performs potentially sleeping operations that must be done before the
4798  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4799  * be called due to an explicit primary plane update, or due to an implicit
4800  * disable that is caused when a sprite plane completely hides the primary
4801  * plane.
4802  */
4803 static void
4804 intel_pre_disable_primary(struct drm_crtc *crtc)
4805 {
4806         struct drm_device *dev = crtc->dev;
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809         int pipe = intel_crtc->pipe;
4810
4811         /*
4812          * Gen2 reports pipe underruns whenever all planes are disabled.
4813          * So diasble underrun reporting before all the planes get disabled.
4814          * FIXME: Need to fix the logic to work when we turn off all planes
4815          * but leave the pipe running.
4816          */
4817         if (IS_GEN2(dev))
4818                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4819
4820         /*
4821          * Vblank time updates from the shadow to live plane control register
4822          * are blocked if the memory self-refresh mode is active at that
4823          * moment. So to make sure the plane gets truly disabled, disable
4824          * first the self-refresh mode. The self-refresh enable bit in turn
4825          * will be checked/applied by the HW only at the next frame start
4826          * event which is after the vblank start event, so we need to have a
4827          * wait-for-vblank between disabling the plane and the pipe.
4828          */
4829         if (HAS_GMCH_DISPLAY(dev))
4830                 intel_set_memory_cxsr(dev_priv, false);
4831
4832         mutex_lock(&dev->struct_mutex);
4833         if (dev_priv->fbc.crtc == intel_crtc)
4834                 intel_fbc_disable(dev);
4835         mutex_unlock(&dev->struct_mutex);
4836
4837         /*
4838          * FIXME IPS should be fine as long as one plane is
4839          * enabled, but in practice it seems to have problems
4840          * when going from primary only to sprite only and vice
4841          * versa.
4842          */
4843         hsw_disable_ips(intel_crtc);
4844 }
4845
4846 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4847 {
4848         intel_enable_primary_hw_plane(crtc->primary, crtc);
4849         intel_enable_sprite_planes(crtc);
4850         intel_crtc_update_cursor(crtc, true);
4851
4852         intel_post_enable_primary(crtc);
4853 }
4854
4855 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4856 {
4857         struct drm_device *dev = crtc->dev;
4858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4859         struct intel_plane *intel_plane;
4860         int pipe = intel_crtc->pipe;
4861
4862         intel_crtc_wait_for_pending_flips(crtc);
4863
4864         intel_pre_disable_primary(crtc);
4865
4866         intel_crtc_dpms_overlay_disable(intel_crtc);
4867         for_each_intel_plane(dev, intel_plane) {
4868                 if (intel_plane->pipe == pipe) {
4869                         struct drm_crtc *from = intel_plane->base.crtc;
4870
4871                         intel_plane->disable_plane(&intel_plane->base,
4872                                                    from ?: crtc, true);
4873                 }
4874         }
4875
4876         /*
4877          * FIXME: Once we grow proper nuclear flip support out of this we need
4878          * to compute the mask of flip planes precisely. For the time being
4879          * consider this a flip to a NULL plane.
4880          */
4881         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4882 }
4883
4884 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4885 {
4886         struct drm_device *dev = crtc->dev;
4887         struct drm_i915_private *dev_priv = dev->dev_private;
4888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4889         struct intel_encoder *encoder;
4890         int pipe = intel_crtc->pipe;
4891
4892         WARN_ON(!crtc->state->enable);
4893
4894         if (intel_crtc->active)
4895                 return;
4896
4897         if (intel_crtc->config->has_pch_encoder)
4898                 intel_prepare_shared_dpll(intel_crtc);
4899
4900         if (intel_crtc->config->has_dp_encoder)
4901                 intel_dp_set_m_n(intel_crtc, M1_N1);
4902
4903         intel_set_pipe_timings(intel_crtc);
4904
4905         if (intel_crtc->config->has_pch_encoder) {
4906                 intel_cpu_transcoder_set_m_n(intel_crtc,
4907                                      &intel_crtc->config->fdi_m_n, NULL);
4908         }
4909
4910         ironlake_set_pipeconf(crtc);
4911
4912         intel_crtc->active = true;
4913
4914         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4915         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4916
4917         for_each_encoder_on_crtc(dev, crtc, encoder)
4918                 if (encoder->pre_enable)
4919                         encoder->pre_enable(encoder);
4920
4921         if (intel_crtc->config->has_pch_encoder) {
4922                 /* Note: FDI PLL enabling _must_ be done before we enable the
4923                  * cpu pipes, hence this is separate from all the other fdi/pch
4924                  * enabling. */
4925                 ironlake_fdi_pll_enable(intel_crtc);
4926         } else {
4927                 assert_fdi_tx_disabled(dev_priv, pipe);
4928                 assert_fdi_rx_disabled(dev_priv, pipe);
4929         }
4930
4931         ironlake_pfit_enable(intel_crtc);
4932
4933         /*
4934          * On ILK+ LUT must be loaded before the pipe is running but with
4935          * clocks enabled
4936          */
4937         intel_crtc_load_lut(crtc);
4938
4939         intel_update_watermarks(crtc);
4940         intel_enable_pipe(intel_crtc);
4941
4942         if (intel_crtc->config->has_pch_encoder)
4943                 ironlake_pch_enable(crtc);
4944
4945         assert_vblank_disabled(crtc);
4946         drm_crtc_vblank_on(crtc);
4947
4948         for_each_encoder_on_crtc(dev, crtc, encoder)
4949                 encoder->enable(encoder);
4950
4951         if (HAS_PCH_CPT(dev))
4952                 cpt_verify_modeset(dev, intel_crtc->pipe);
4953 }
4954
4955 /* IPS only exists on ULT machines and is tied to pipe A. */
4956 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4957 {
4958         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4959 }
4960
4961 /*
4962  * This implements the workaround described in the "notes" section of the mode
4963  * set sequence documentation. When going from no pipes or single pipe to
4964  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4965  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4966  */
4967 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4968 {
4969         struct drm_device *dev = crtc->base.dev;
4970         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4971
4972         /* We want to get the other_active_crtc only if there's only 1 other
4973          * active crtc. */
4974         for_each_intel_crtc(dev, crtc_it) {
4975                 if (!crtc_it->active || crtc_it == crtc)
4976                         continue;
4977
4978                 if (other_active_crtc)
4979                         return;
4980
4981                 other_active_crtc = crtc_it;
4982         }
4983         if (!other_active_crtc)
4984                 return;
4985
4986         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4987         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4988 }
4989
4990 static void haswell_crtc_enable(struct drm_crtc *crtc)
4991 {
4992         struct drm_device *dev = crtc->dev;
4993         struct drm_i915_private *dev_priv = dev->dev_private;
4994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995         struct intel_encoder *encoder;
4996         int pipe = intel_crtc->pipe;
4997
4998         WARN_ON(!crtc->state->enable);
4999
5000         if (intel_crtc->active)
5001                 return;
5002
5003         if (intel_crtc_to_shared_dpll(intel_crtc))
5004                 intel_enable_shared_dpll(intel_crtc);
5005
5006         if (intel_crtc->config->has_dp_encoder)
5007                 intel_dp_set_m_n(intel_crtc, M1_N1);
5008
5009         intel_set_pipe_timings(intel_crtc);
5010
5011         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5012                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5013                            intel_crtc->config->pixel_multiplier - 1);
5014         }
5015
5016         if (intel_crtc->config->has_pch_encoder) {
5017                 intel_cpu_transcoder_set_m_n(intel_crtc,
5018                                      &intel_crtc->config->fdi_m_n, NULL);
5019         }
5020
5021         haswell_set_pipeconf(crtc);
5022
5023         intel_set_pipe_csc(crtc);
5024
5025         intel_crtc->active = true;
5026
5027         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5028         for_each_encoder_on_crtc(dev, crtc, encoder)
5029                 if (encoder->pre_enable)
5030                         encoder->pre_enable(encoder);
5031
5032         if (intel_crtc->config->has_pch_encoder) {
5033                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034                                                       true);
5035                 dev_priv->display.fdi_link_train(crtc);
5036         }
5037
5038         intel_ddi_enable_pipe_clock(intel_crtc);
5039
5040         if (INTEL_INFO(dev)->gen == 9)
5041                 skylake_pfit_update(intel_crtc, 1);
5042         else if (INTEL_INFO(dev)->gen < 9)
5043                 ironlake_pfit_enable(intel_crtc);
5044         else
5045                 MISSING_CASE(INTEL_INFO(dev)->gen);
5046
5047         /*
5048          * On ILK+ LUT must be loaded before the pipe is running but with
5049          * clocks enabled
5050          */
5051         intel_crtc_load_lut(crtc);
5052
5053         intel_ddi_set_pipe_settings(crtc);
5054         intel_ddi_enable_transcoder_func(crtc);
5055
5056         intel_update_watermarks(crtc);
5057         intel_enable_pipe(intel_crtc);
5058
5059         if (intel_crtc->config->has_pch_encoder)
5060                 lpt_pch_enable(crtc);
5061
5062         if (intel_crtc->config->dp_encoder_is_mst)
5063                 intel_ddi_set_vc_payload_alloc(crtc, true);
5064
5065         assert_vblank_disabled(crtc);
5066         drm_crtc_vblank_on(crtc);
5067
5068         for_each_encoder_on_crtc(dev, crtc, encoder) {
5069                 encoder->enable(encoder);
5070                 intel_opregion_notify_encoder(encoder, true);
5071         }
5072
5073         /* If we change the relative order between pipe/planes enabling, we need
5074          * to change the workaround. */
5075         haswell_mode_set_planes_workaround(intel_crtc);
5076 }
5077
5078 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5079 {
5080         struct drm_device *dev = crtc->base.dev;
5081         struct drm_i915_private *dev_priv = dev->dev_private;
5082         int pipe = crtc->pipe;
5083
5084         /* To avoid upsetting the power well on haswell only disable the pfit if
5085          * it's in use. The hw state code will make sure we get this right. */
5086         if (crtc->config->pch_pfit.enabled) {
5087                 I915_WRITE(PF_CTL(pipe), 0);
5088                 I915_WRITE(PF_WIN_POS(pipe), 0);
5089                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5090         }
5091 }
5092
5093 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5094 {
5095         struct drm_device *dev = crtc->dev;
5096         struct drm_i915_private *dev_priv = dev->dev_private;
5097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5098         struct intel_encoder *encoder;
5099         int pipe = intel_crtc->pipe;
5100         u32 reg, temp;
5101
5102         if (!intel_crtc->active)
5103                 return;
5104
5105         for_each_encoder_on_crtc(dev, crtc, encoder)
5106                 encoder->disable(encoder);
5107
5108         drm_crtc_vblank_off(crtc);
5109         assert_vblank_disabled(crtc);
5110
5111         if (intel_crtc->config->has_pch_encoder)
5112                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5113
5114         intel_disable_pipe(intel_crtc);
5115
5116         ironlake_pfit_disable(intel_crtc);
5117
5118         for_each_encoder_on_crtc(dev, crtc, encoder)
5119                 if (encoder->post_disable)
5120                         encoder->post_disable(encoder);
5121
5122         if (intel_crtc->config->has_pch_encoder) {
5123                 ironlake_fdi_disable(crtc);
5124
5125                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5126
5127                 if (HAS_PCH_CPT(dev)) {
5128                         /* disable TRANS_DP_CTL */
5129                         reg = TRANS_DP_CTL(pipe);
5130                         temp = I915_READ(reg);
5131                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5132                                   TRANS_DP_PORT_SEL_MASK);
5133                         temp |= TRANS_DP_PORT_SEL_NONE;
5134                         I915_WRITE(reg, temp);
5135
5136                         /* disable DPLL_SEL */
5137                         temp = I915_READ(PCH_DPLL_SEL);
5138                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5139                         I915_WRITE(PCH_DPLL_SEL, temp);
5140                 }
5141
5142                 /* disable PCH DPLL */
5143                 intel_disable_shared_dpll(intel_crtc);
5144
5145                 ironlake_fdi_pll_disable(intel_crtc);
5146         }
5147
5148         intel_crtc->active = false;
5149         intel_update_watermarks(crtc);
5150
5151         mutex_lock(&dev->struct_mutex);
5152         intel_fbc_update(dev);
5153         mutex_unlock(&dev->struct_mutex);
5154 }
5155
5156 static void haswell_crtc_disable(struct drm_crtc *crtc)
5157 {
5158         struct drm_device *dev = crtc->dev;
5159         struct drm_i915_private *dev_priv = dev->dev_private;
5160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161         struct intel_encoder *encoder;
5162         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5163
5164         if (!intel_crtc->active)
5165                 return;
5166
5167         for_each_encoder_on_crtc(dev, crtc, encoder) {
5168                 intel_opregion_notify_encoder(encoder, false);
5169                 encoder->disable(encoder);
5170         }
5171
5172         drm_crtc_vblank_off(crtc);
5173         assert_vblank_disabled(crtc);
5174
5175         if (intel_crtc->config->has_pch_encoder)
5176                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5177                                                       false);
5178         intel_disable_pipe(intel_crtc);
5179
5180         if (intel_crtc->config->dp_encoder_is_mst)
5181                 intel_ddi_set_vc_payload_alloc(crtc, false);
5182
5183         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5184
5185         if (INTEL_INFO(dev)->gen == 9)
5186                 skylake_pfit_update(intel_crtc, 0);
5187         else if (INTEL_INFO(dev)->gen < 9)
5188                 ironlake_pfit_disable(intel_crtc);
5189         else
5190                 MISSING_CASE(INTEL_INFO(dev)->gen);
5191
5192         intel_ddi_disable_pipe_clock(intel_crtc);
5193
5194         if (intel_crtc->config->has_pch_encoder) {
5195                 lpt_disable_pch_transcoder(dev_priv);
5196                 intel_ddi_fdi_disable(crtc);
5197         }
5198
5199         for_each_encoder_on_crtc(dev, crtc, encoder)
5200                 if (encoder->post_disable)
5201                         encoder->post_disable(encoder);
5202
5203         intel_crtc->active = false;
5204         intel_update_watermarks(crtc);
5205
5206         mutex_lock(&dev->struct_mutex);
5207         intel_fbc_update(dev);
5208         mutex_unlock(&dev->struct_mutex);
5209
5210         if (intel_crtc_to_shared_dpll(intel_crtc))
5211                 intel_disable_shared_dpll(intel_crtc);
5212 }
5213
5214 static void ironlake_crtc_off(struct drm_crtc *crtc)
5215 {
5216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5217         intel_put_shared_dpll(intel_crtc);
5218 }
5219
5220
5221 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5222 {
5223         struct drm_device *dev = crtc->base.dev;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225         struct intel_crtc_state *pipe_config = crtc->config;
5226
5227         if (!pipe_config->gmch_pfit.control)
5228                 return;
5229
5230         /*
5231          * The panel fitter should only be adjusted whilst the pipe is disabled,
5232          * according to register description and PRM.
5233          */
5234         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5235         assert_pipe_disabled(dev_priv, crtc->pipe);
5236
5237         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5238         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5239
5240         /* Border color in case we don't scale up to the full screen. Black by
5241          * default, change to something else for debugging. */
5242         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5243 }
5244
5245 static enum intel_display_power_domain port_to_power_domain(enum port port)
5246 {
5247         switch (port) {
5248         case PORT_A:
5249                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5250         case PORT_B:
5251                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5252         case PORT_C:
5253                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5254         case PORT_D:
5255                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5256         default:
5257                 WARN_ON_ONCE(1);
5258                 return POWER_DOMAIN_PORT_OTHER;
5259         }
5260 }
5261
5262 #define for_each_power_domain(domain, mask)                             \
5263         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5264                 if ((1 << (domain)) & (mask))
5265
5266 enum intel_display_power_domain
5267 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5268 {
5269         struct drm_device *dev = intel_encoder->base.dev;
5270         struct intel_digital_port *intel_dig_port;
5271
5272         switch (intel_encoder->type) {
5273         case INTEL_OUTPUT_UNKNOWN:
5274                 /* Only DDI platforms should ever use this output type */
5275                 WARN_ON_ONCE(!HAS_DDI(dev));
5276         case INTEL_OUTPUT_DISPLAYPORT:
5277         case INTEL_OUTPUT_HDMI:
5278         case INTEL_OUTPUT_EDP:
5279                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5280                 return port_to_power_domain(intel_dig_port->port);
5281         case INTEL_OUTPUT_DP_MST:
5282                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5283                 return port_to_power_domain(intel_dig_port->port);
5284         case INTEL_OUTPUT_ANALOG:
5285                 return POWER_DOMAIN_PORT_CRT;
5286         case INTEL_OUTPUT_DSI:
5287                 return POWER_DOMAIN_PORT_DSI;
5288         default:
5289                 return POWER_DOMAIN_PORT_OTHER;
5290         }
5291 }
5292
5293 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5294 {
5295         struct drm_device *dev = crtc->dev;
5296         struct intel_encoder *intel_encoder;
5297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5298         enum pipe pipe = intel_crtc->pipe;
5299         unsigned long mask;
5300         enum transcoder transcoder;
5301
5302         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5303
5304         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5305         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5306         if (intel_crtc->config->pch_pfit.enabled ||
5307             intel_crtc->config->pch_pfit.force_thru)
5308                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5309
5310         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5311                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5312
5313         return mask;
5314 }
5315
5316 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5317 {
5318         struct drm_device *dev = state->dev;
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5321         struct intel_crtc *crtc;
5322
5323         /*
5324          * First get all needed power domains, then put all unneeded, to avoid
5325          * any unnecessary toggling of the power wells.
5326          */
5327         for_each_intel_crtc(dev, crtc) {
5328                 enum intel_display_power_domain domain;
5329
5330                 if (!crtc->base.state->enable)
5331                         continue;
5332
5333                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5334
5335                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5336                         intel_display_power_get(dev_priv, domain);
5337         }
5338
5339         if (dev_priv->display.modeset_global_resources)
5340                 dev_priv->display.modeset_global_resources(state);
5341
5342         for_each_intel_crtc(dev, crtc) {
5343                 enum intel_display_power_domain domain;
5344
5345                 for_each_power_domain(domain, crtc->enabled_power_domains)
5346                         intel_display_power_put(dev_priv, domain);
5347
5348                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5349         }
5350
5351         intel_display_set_init_power(dev_priv, false);
5352 }
5353
5354 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5355 {
5356         struct drm_i915_private *dev_priv = dev->dev_private;
5357         uint32_t divider;
5358         uint32_t ratio;
5359         uint32_t current_freq;
5360         int ret;
5361
5362         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5363         switch (frequency) {
5364         case 144000:
5365                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5366                 ratio = BXT_DE_PLL_RATIO(60);
5367                 break;
5368         case 288000:
5369                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5370                 ratio = BXT_DE_PLL_RATIO(60);
5371                 break;
5372         case 384000:
5373                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5374                 ratio = BXT_DE_PLL_RATIO(60);
5375                 break;
5376         case 576000:
5377                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5378                 ratio = BXT_DE_PLL_RATIO(60);
5379                 break;
5380         case 624000:
5381                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5382                 ratio = BXT_DE_PLL_RATIO(65);
5383                 break;
5384         case 19200:
5385                 /*
5386                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5387                  * to suppress GCC warning.
5388                  */
5389                 ratio = 0;
5390                 divider = 0;
5391                 break;
5392         default:
5393                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5394
5395                 return;
5396         }
5397
5398         mutex_lock(&dev_priv->rps.hw_lock);
5399         /* Inform power controller of upcoming frequency change */
5400         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5401                                       0x80000000);
5402         mutex_unlock(&dev_priv->rps.hw_lock);
5403
5404         if (ret) {
5405                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5406                           ret, frequency);
5407                 return;
5408         }
5409
5410         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5411         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5412         current_freq = current_freq * 500 + 1000;
5413
5414         /*
5415          * DE PLL has to be disabled when
5416          * - setting to 19.2MHz (bypass, PLL isn't used)
5417          * - before setting to 624MHz (PLL needs toggling)
5418          * - before setting to any frequency from 624MHz (PLL needs toggling)
5419          */
5420         if (frequency == 19200 || frequency == 624000 ||
5421             current_freq == 624000) {
5422                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5423                 /* Timeout 200us */
5424                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5425                              1))
5426                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5427         }
5428
5429         if (frequency != 19200) {
5430                 uint32_t val;
5431
5432                 val = I915_READ(BXT_DE_PLL_CTL);
5433                 val &= ~BXT_DE_PLL_RATIO_MASK;
5434                 val |= ratio;
5435                 I915_WRITE(BXT_DE_PLL_CTL, val);
5436
5437                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5438                 /* Timeout 200us */
5439                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5440                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5441
5442                 val = I915_READ(CDCLK_CTL);
5443                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5444                 val |= divider;
5445                 /*
5446                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5447                  * enable otherwise.
5448                  */
5449                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5450                 if (frequency >= 500000)
5451                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5452
5453                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5454                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5455                 val |= (frequency - 1000) / 500;
5456                 I915_WRITE(CDCLK_CTL, val);
5457         }
5458
5459         mutex_lock(&dev_priv->rps.hw_lock);
5460         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5461                                       DIV_ROUND_UP(frequency, 25000));
5462         mutex_unlock(&dev_priv->rps.hw_lock);
5463
5464         if (ret) {
5465                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5466                           ret, frequency);
5467                 return;
5468         }
5469
5470         dev_priv->cdclk_freq = frequency;
5471 }
5472
5473 void broxton_init_cdclk(struct drm_device *dev)
5474 {
5475         struct drm_i915_private *dev_priv = dev->dev_private;
5476         uint32_t val;
5477
5478         /*
5479          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5480          * or else the reset will hang because there is no PCH to respond.
5481          * Move the handshake programming to initialization sequence.
5482          * Previously was left up to BIOS.
5483          */
5484         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5485         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5486         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5487
5488         /* Enable PG1 for cdclk */
5489         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5490
5491         /* check if cd clock is enabled */
5492         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5493                 DRM_DEBUG_KMS("Display already initialized\n");
5494                 return;
5495         }
5496
5497         /*
5498          * FIXME:
5499          * - The initial CDCLK needs to be read from VBT.
5500          *   Need to make this change after VBT has changes for BXT.
5501          * - check if setting the max (or any) cdclk freq is really necessary
5502          *   here, it belongs to modeset time
5503          */
5504         broxton_set_cdclk(dev, 624000);
5505
5506         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5507         POSTING_READ(DBUF_CTL);
5508
5509         udelay(10);
5510
5511         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5512                 DRM_ERROR("DBuf power enable timeout!\n");
5513 }
5514
5515 void broxton_uninit_cdclk(struct drm_device *dev)
5516 {
5517         struct drm_i915_private *dev_priv = dev->dev_private;
5518
5519         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5520         POSTING_READ(DBUF_CTL);
5521
5522         udelay(10);
5523
5524         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5525                 DRM_ERROR("DBuf power disable timeout!\n");
5526
5527         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5528         broxton_set_cdclk(dev, 19200);
5529
5530         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5531 }
5532
5533 /* returns HPLL frequency in kHz */
5534 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5535 {
5536         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5537
5538         /* Obtain SKU information */
5539         mutex_lock(&dev_priv->dpio_lock);
5540         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5541                 CCK_FUSE_HPLL_FREQ_MASK;
5542         mutex_unlock(&dev_priv->dpio_lock);
5543
5544         return vco_freq[hpll_freq] * 1000;
5545 }
5546
5547 static void vlv_update_cdclk(struct drm_device *dev)
5548 {
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5552         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5553                          dev_priv->cdclk_freq);
5554
5555         /*
5556          * Program the gmbus_freq based on the cdclk frequency.
5557          * BSpec erroneously claims we should aim for 4MHz, but
5558          * in fact 1MHz is the correct frequency.
5559          */
5560         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5561 }
5562
5563 /* Adjust CDclk dividers to allow high res or save power if possible */
5564 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5565 {
5566         struct drm_i915_private *dev_priv = dev->dev_private;
5567         u32 val, cmd;
5568
5569         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5570                                         != dev_priv->cdclk_freq);
5571
5572         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5573                 cmd = 2;
5574         else if (cdclk == 266667)
5575                 cmd = 1;
5576         else
5577                 cmd = 0;
5578
5579         mutex_lock(&dev_priv->rps.hw_lock);
5580         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5581         val &= ~DSPFREQGUAR_MASK;
5582         val |= (cmd << DSPFREQGUAR_SHIFT);
5583         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5584         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5585                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5586                      50)) {
5587                 DRM_ERROR("timed out waiting for CDclk change\n");
5588         }
5589         mutex_unlock(&dev_priv->rps.hw_lock);
5590
5591         if (cdclk == 400000) {
5592                 u32 divider;
5593
5594                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5595
5596                 mutex_lock(&dev_priv->dpio_lock);
5597                 /* adjust cdclk divider */
5598                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5599                 val &= ~DISPLAY_FREQUENCY_VALUES;
5600                 val |= divider;
5601                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5602
5603                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5604                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5605                              50))
5606                         DRM_ERROR("timed out waiting for CDclk change\n");
5607                 mutex_unlock(&dev_priv->dpio_lock);
5608         }
5609
5610         mutex_lock(&dev_priv->dpio_lock);
5611         /* adjust self-refresh exit latency value */
5612         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5613         val &= ~0x7f;
5614
5615         /*
5616          * For high bandwidth configs, we set a higher latency in the bunit
5617          * so that the core display fetch happens in time to avoid underruns.
5618          */
5619         if (cdclk == 400000)
5620                 val |= 4500 / 250; /* 4.5 usec */
5621         else
5622                 val |= 3000 / 250; /* 3.0 usec */
5623         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5624         mutex_unlock(&dev_priv->dpio_lock);
5625
5626         vlv_update_cdclk(dev);
5627 }
5628
5629 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5630 {
5631         struct drm_i915_private *dev_priv = dev->dev_private;
5632         u32 val, cmd;
5633
5634         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5635                                                 != dev_priv->cdclk_freq);
5636
5637         switch (cdclk) {
5638         case 333333:
5639         case 320000:
5640         case 266667:
5641         case 200000:
5642                 break;
5643         default:
5644                 MISSING_CASE(cdclk);
5645                 return;
5646         }
5647
5648         /*
5649          * Specs are full of misinformation, but testing on actual
5650          * hardware has shown that we just need to write the desired
5651          * CCK divider into the Punit register.
5652          */
5653         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5654
5655         mutex_lock(&dev_priv->rps.hw_lock);
5656         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5657         val &= ~DSPFREQGUAR_MASK_CHV;
5658         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5659         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5660         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5661                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5662                      50)) {
5663                 DRM_ERROR("timed out waiting for CDclk change\n");
5664         }
5665         mutex_unlock(&dev_priv->rps.hw_lock);
5666
5667         vlv_update_cdclk(dev);
5668 }
5669
5670 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5671                                  int max_pixclk)
5672 {
5673         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5674         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5675
5676         /*
5677          * Really only a few cases to deal with, as only 4 CDclks are supported:
5678          *   200MHz
5679          *   267MHz
5680          *   320/333MHz (depends on HPLL freq)
5681          *   400MHz (VLV only)
5682          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5683          * of the lower bin and adjust if needed.
5684          *
5685          * We seem to get an unstable or solid color picture at 200MHz.
5686          * Not sure what's wrong. For now use 200MHz only when all pipes
5687          * are off.
5688          */
5689         if (!IS_CHERRYVIEW(dev_priv) &&
5690             max_pixclk > freq_320*limit/100)
5691                 return 400000;
5692         else if (max_pixclk > 266667*limit/100)
5693                 return freq_320;
5694         else if (max_pixclk > 0)
5695                 return 266667;
5696         else
5697                 return 200000;
5698 }
5699
5700 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5701                               int max_pixclk)
5702 {
5703         /*
5704          * FIXME:
5705          * - remove the guardband, it's not needed on BXT
5706          * - set 19.2MHz bypass frequency if there are no active pipes
5707          */
5708         if (max_pixclk > 576000*9/10)
5709                 return 624000;
5710         else if (max_pixclk > 384000*9/10)
5711                 return 576000;
5712         else if (max_pixclk > 288000*9/10)
5713                 return 384000;
5714         else if (max_pixclk > 144000*9/10)
5715                 return 288000;
5716         else
5717                 return 144000;
5718 }
5719
5720 /* Compute the max pixel clock for new configuration. Uses atomic state if
5721  * that's non-NULL, look at current state otherwise. */
5722 static int intel_mode_max_pixclk(struct drm_device *dev,
5723                                  struct drm_atomic_state *state)
5724 {
5725         struct intel_crtc *intel_crtc;
5726         struct intel_crtc_state *crtc_state;
5727         int max_pixclk = 0;
5728
5729         for_each_intel_crtc(dev, intel_crtc) {
5730                 if (state)
5731                         crtc_state =
5732                                 intel_atomic_get_crtc_state(state, intel_crtc);
5733                 else
5734                         crtc_state = intel_crtc->config;
5735                 if (IS_ERR(crtc_state))
5736                         return PTR_ERR(crtc_state);
5737
5738                 if (!crtc_state->base.enable)
5739                         continue;
5740
5741                 max_pixclk = max(max_pixclk,
5742                                  crtc_state->base.adjusted_mode.crtc_clock);
5743         }
5744
5745         return max_pixclk;
5746 }
5747
5748 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5749 {
5750         struct drm_i915_private *dev_priv = to_i915(state->dev);
5751         struct drm_crtc *crtc;
5752         struct drm_crtc_state *crtc_state;
5753         int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5754         int cdclk, i;
5755
5756         if (max_pixclk < 0)
5757                 return max_pixclk;
5758
5759         if (IS_VALLEYVIEW(dev_priv))
5760                 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5761         else
5762                 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5763
5764         if (cdclk == dev_priv->cdclk_freq)
5765                 return 0;
5766
5767         /* add all active pipes to the state */
5768         for_each_crtc(state->dev, crtc) {
5769                 if (!crtc->state->enable)
5770                         continue;
5771
5772                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5773                 if (IS_ERR(crtc_state))
5774                         return PTR_ERR(crtc_state);
5775         }
5776
5777         /* disable/enable all currently active pipes while we change cdclk */
5778         for_each_crtc_in_state(state, crtc, crtc_state, i)
5779                 if (crtc_state->enable)
5780                         crtc_state->mode_changed = true;
5781
5782         return 0;
5783 }
5784
5785 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5786 {
5787         unsigned int credits, default_credits;
5788
5789         if (IS_CHERRYVIEW(dev_priv))
5790                 default_credits = PFI_CREDIT(12);
5791         else
5792                 default_credits = PFI_CREDIT(8);
5793
5794         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5795                 /* CHV suggested value is 31 or 63 */
5796                 if (IS_CHERRYVIEW(dev_priv))
5797                         credits = PFI_CREDIT_31;
5798                 else
5799                         credits = PFI_CREDIT(15);
5800         } else {
5801                 credits = default_credits;
5802         }
5803
5804         /*
5805          * WA - write default credits before re-programming
5806          * FIXME: should we also set the resend bit here?
5807          */
5808         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5809                    default_credits);
5810
5811         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5812                    credits | PFI_CREDIT_RESEND);
5813
5814         /*
5815          * FIXME is this guaranteed to clear
5816          * immediately or should we poll for it?
5817          */
5818         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5819 }
5820
5821 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5822 {
5823         struct drm_device *dev = old_state->dev;
5824         struct drm_i915_private *dev_priv = dev->dev_private;
5825         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5826         int req_cdclk;
5827
5828         /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5829          * never fail. */
5830         if (WARN_ON(max_pixclk < 0))
5831                 return;
5832
5833         req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5834
5835         if (req_cdclk != dev_priv->cdclk_freq) {
5836                 /*
5837                  * FIXME: We can end up here with all power domains off, yet
5838                  * with a CDCLK frequency other than the minimum. To account
5839                  * for this take the PIPE-A power domain, which covers the HW
5840                  * blocks needed for the following programming. This can be
5841                  * removed once it's guaranteed that we get here either with
5842                  * the minimum CDCLK set, or the required power domains
5843                  * enabled.
5844                  */
5845                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5846
5847                 if (IS_CHERRYVIEW(dev))
5848                         cherryview_set_cdclk(dev, req_cdclk);
5849                 else
5850                         valleyview_set_cdclk(dev, req_cdclk);
5851
5852                 vlv_program_pfi_credits(dev_priv);
5853
5854                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5855         }
5856 }
5857
5858 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5859 {
5860         struct drm_device *dev = crtc->dev;
5861         struct drm_i915_private *dev_priv = to_i915(dev);
5862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5863         struct intel_encoder *encoder;
5864         int pipe = intel_crtc->pipe;
5865         bool is_dsi;
5866
5867         WARN_ON(!crtc->state->enable);
5868
5869         if (intel_crtc->active)
5870                 return;
5871
5872         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5873
5874         if (!is_dsi) {
5875                 if (IS_CHERRYVIEW(dev))
5876                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5877                 else
5878                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5879         }
5880
5881         if (intel_crtc->config->has_dp_encoder)
5882                 intel_dp_set_m_n(intel_crtc, M1_N1);
5883
5884         intel_set_pipe_timings(intel_crtc);
5885
5886         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5887                 struct drm_i915_private *dev_priv = dev->dev_private;
5888
5889                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5890                 I915_WRITE(CHV_CANVAS(pipe), 0);
5891         }
5892
5893         i9xx_set_pipeconf(intel_crtc);
5894
5895         intel_crtc->active = true;
5896
5897         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5898
5899         for_each_encoder_on_crtc(dev, crtc, encoder)
5900                 if (encoder->pre_pll_enable)
5901                         encoder->pre_pll_enable(encoder);
5902
5903         if (!is_dsi) {
5904                 if (IS_CHERRYVIEW(dev))
5905                         chv_enable_pll(intel_crtc, intel_crtc->config);
5906                 else
5907                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5908         }
5909
5910         for_each_encoder_on_crtc(dev, crtc, encoder)
5911                 if (encoder->pre_enable)
5912                         encoder->pre_enable(encoder);
5913
5914         i9xx_pfit_enable(intel_crtc);
5915
5916         intel_crtc_load_lut(crtc);
5917
5918         intel_update_watermarks(crtc);
5919         intel_enable_pipe(intel_crtc);
5920
5921         assert_vblank_disabled(crtc);
5922         drm_crtc_vblank_on(crtc);
5923
5924         for_each_encoder_on_crtc(dev, crtc, encoder)
5925                 encoder->enable(encoder);
5926 }
5927
5928 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5929 {
5930         struct drm_device *dev = crtc->base.dev;
5931         struct drm_i915_private *dev_priv = dev->dev_private;
5932
5933         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5934         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5935 }
5936
5937 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5938 {
5939         struct drm_device *dev = crtc->dev;
5940         struct drm_i915_private *dev_priv = to_i915(dev);
5941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5942         struct intel_encoder *encoder;
5943         int pipe = intel_crtc->pipe;
5944
5945         WARN_ON(!crtc->state->enable);
5946
5947         if (intel_crtc->active)
5948                 return;
5949
5950         i9xx_set_pll_dividers(intel_crtc);
5951
5952         if (intel_crtc->config->has_dp_encoder)
5953                 intel_dp_set_m_n(intel_crtc, M1_N1);
5954
5955         intel_set_pipe_timings(intel_crtc);
5956
5957         i9xx_set_pipeconf(intel_crtc);
5958
5959         intel_crtc->active = true;
5960
5961         if (!IS_GEN2(dev))
5962                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5963
5964         for_each_encoder_on_crtc(dev, crtc, encoder)
5965                 if (encoder->pre_enable)
5966                         encoder->pre_enable(encoder);
5967
5968         i9xx_enable_pll(intel_crtc);
5969
5970         i9xx_pfit_enable(intel_crtc);
5971
5972         intel_crtc_load_lut(crtc);
5973
5974         intel_update_watermarks(crtc);
5975         intel_enable_pipe(intel_crtc);
5976
5977         assert_vblank_disabled(crtc);
5978         drm_crtc_vblank_on(crtc);
5979
5980         for_each_encoder_on_crtc(dev, crtc, encoder)
5981                 encoder->enable(encoder);
5982 }
5983
5984 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5985 {
5986         struct drm_device *dev = crtc->base.dev;
5987         struct drm_i915_private *dev_priv = dev->dev_private;
5988
5989         if (!crtc->config->gmch_pfit.control)
5990                 return;
5991
5992         assert_pipe_disabled(dev_priv, crtc->pipe);
5993
5994         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5995                          I915_READ(PFIT_CONTROL));
5996         I915_WRITE(PFIT_CONTROL, 0);
5997 }
5998
5999 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6000 {
6001         struct drm_device *dev = crtc->dev;
6002         struct drm_i915_private *dev_priv = dev->dev_private;
6003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6004         struct intel_encoder *encoder;
6005         int pipe = intel_crtc->pipe;
6006
6007         if (!intel_crtc->active)
6008                 return;
6009
6010         /*
6011          * On gen2 planes are double buffered but the pipe isn't, so we must
6012          * wait for planes to fully turn off before disabling the pipe.
6013          * We also need to wait on all gmch platforms because of the
6014          * self-refresh mode constraint explained above.
6015          */
6016         intel_wait_for_vblank(dev, pipe);
6017
6018         for_each_encoder_on_crtc(dev, crtc, encoder)
6019                 encoder->disable(encoder);
6020
6021         drm_crtc_vblank_off(crtc);
6022         assert_vblank_disabled(crtc);
6023
6024         intel_disable_pipe(intel_crtc);
6025
6026         i9xx_pfit_disable(intel_crtc);
6027
6028         for_each_encoder_on_crtc(dev, crtc, encoder)
6029                 if (encoder->post_disable)
6030                         encoder->post_disable(encoder);
6031
6032         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6033                 if (IS_CHERRYVIEW(dev))
6034                         chv_disable_pll(dev_priv, pipe);
6035                 else if (IS_VALLEYVIEW(dev))
6036                         vlv_disable_pll(dev_priv, pipe);
6037                 else
6038                         i9xx_disable_pll(intel_crtc);
6039         }
6040
6041         if (!IS_GEN2(dev))
6042                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6043
6044         intel_crtc->active = false;
6045         intel_update_watermarks(crtc);
6046
6047         mutex_lock(&dev->struct_mutex);
6048         intel_fbc_update(dev);
6049         mutex_unlock(&dev->struct_mutex);
6050 }
6051
6052 static void i9xx_crtc_off(struct drm_crtc *crtc)
6053 {
6054 }
6055
6056 /* Master function to enable/disable CRTC and corresponding power wells */
6057 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6058 {
6059         struct drm_device *dev = crtc->dev;
6060         struct drm_i915_private *dev_priv = dev->dev_private;
6061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6062         enum intel_display_power_domain domain;
6063         unsigned long domains;
6064
6065         if (enable) {
6066                 if (!intel_crtc->active) {
6067                         domains = get_crtc_power_domains(crtc);
6068                         for_each_power_domain(domain, domains)
6069                                 intel_display_power_get(dev_priv, domain);
6070                         intel_crtc->enabled_power_domains = domains;
6071
6072                         dev_priv->display.crtc_enable(crtc);
6073                         intel_crtc_enable_planes(crtc);
6074                 }
6075         } else {
6076                 if (intel_crtc->active) {
6077                         intel_crtc_disable_planes(crtc);
6078                         dev_priv->display.crtc_disable(crtc);
6079
6080                         domains = intel_crtc->enabled_power_domains;
6081                         for_each_power_domain(domain, domains)
6082                                 intel_display_power_put(dev_priv, domain);
6083                         intel_crtc->enabled_power_domains = 0;
6084                 }
6085         }
6086 }
6087
6088 /**
6089  * Sets the power management mode of the pipe and plane.
6090  */
6091 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6092 {
6093         struct drm_device *dev = crtc->dev;
6094         struct intel_encoder *intel_encoder;
6095         bool enable = false;
6096
6097         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6098                 enable |= intel_encoder->connectors_active;
6099
6100         intel_crtc_control(crtc, enable);
6101
6102         crtc->state->active = enable;
6103 }
6104
6105 static void intel_crtc_disable(struct drm_crtc *crtc)
6106 {
6107         struct drm_device *dev = crtc->dev;
6108         struct drm_connector *connector;
6109         struct drm_i915_private *dev_priv = dev->dev_private;
6110
6111         /* crtc should still be enabled when we disable it. */
6112         WARN_ON(!crtc->state->enable);
6113
6114         intel_crtc_disable_planes(crtc);
6115         dev_priv->display.crtc_disable(crtc);
6116         dev_priv->display.off(crtc);
6117
6118         drm_plane_helper_disable(crtc->primary);
6119
6120         /* Update computed state. */
6121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6122                 if (!connector->encoder || !connector->encoder->crtc)
6123                         continue;
6124
6125                 if (connector->encoder->crtc != crtc)
6126                         continue;
6127
6128                 connector->dpms = DRM_MODE_DPMS_OFF;
6129                 to_intel_encoder(connector->encoder)->connectors_active = false;
6130         }
6131 }
6132
6133 void intel_encoder_destroy(struct drm_encoder *encoder)
6134 {
6135         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6136
6137         drm_encoder_cleanup(encoder);
6138         kfree(intel_encoder);
6139 }
6140
6141 /* Simple dpms helper for encoders with just one connector, no cloning and only
6142  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6143  * state of the entire output pipe. */
6144 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6145 {
6146         if (mode == DRM_MODE_DPMS_ON) {
6147                 encoder->connectors_active = true;
6148
6149                 intel_crtc_update_dpms(encoder->base.crtc);
6150         } else {
6151                 encoder->connectors_active = false;
6152
6153                 intel_crtc_update_dpms(encoder->base.crtc);
6154         }
6155 }
6156
6157 /* Cross check the actual hw state with our own modeset state tracking (and it's
6158  * internal consistency). */
6159 static void intel_connector_check_state(struct intel_connector *connector)
6160 {
6161         if (connector->get_hw_state(connector)) {
6162                 struct intel_encoder *encoder = connector->encoder;
6163                 struct drm_crtc *crtc;
6164                 bool encoder_enabled;
6165                 enum pipe pipe;
6166
6167                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6168                               connector->base.base.id,
6169                               connector->base.name);
6170
6171                 /* there is no real hw state for MST connectors */
6172                 if (connector->mst_port)
6173                         return;
6174
6175                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6176                      "wrong connector dpms state\n");
6177                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6178                      "active connector not linked to encoder\n");
6179
6180                 if (encoder) {
6181                         I915_STATE_WARN(!encoder->connectors_active,
6182                              "encoder->connectors_active not set\n");
6183
6184                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6185                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6186                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6187                                 return;
6188
6189                         crtc = encoder->base.crtc;
6190
6191                         I915_STATE_WARN(!crtc->state->enable,
6192                                         "crtc not enabled\n");
6193                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6194                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6195                              "encoder active on the wrong pipe\n");
6196                 }
6197         }
6198 }
6199
6200 int intel_connector_init(struct intel_connector *connector)
6201 {
6202         struct drm_connector_state *connector_state;
6203
6204         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6205         if (!connector_state)
6206                 return -ENOMEM;
6207
6208         connector->base.state = connector_state;
6209         return 0;
6210 }
6211
6212 struct intel_connector *intel_connector_alloc(void)
6213 {
6214         struct intel_connector *connector;
6215
6216         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6217         if (!connector)
6218                 return NULL;
6219
6220         if (intel_connector_init(connector) < 0) {
6221                 kfree(connector);
6222                 return NULL;
6223         }
6224
6225         return connector;
6226 }
6227
6228 /* Even simpler default implementation, if there's really no special case to
6229  * consider. */
6230 void intel_connector_dpms(struct drm_connector *connector, int mode)
6231 {
6232         /* All the simple cases only support two dpms states. */
6233         if (mode != DRM_MODE_DPMS_ON)
6234                 mode = DRM_MODE_DPMS_OFF;
6235
6236         if (mode == connector->dpms)
6237                 return;
6238
6239         connector->dpms = mode;
6240
6241         /* Only need to change hw state when actually enabled */
6242         if (connector->encoder)
6243                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6244
6245         intel_modeset_check_state(connector->dev);
6246 }
6247
6248 /* Simple connector->get_hw_state implementation for encoders that support only
6249  * one connector and no cloning and hence the encoder state determines the state
6250  * of the connector. */
6251 bool intel_connector_get_hw_state(struct intel_connector *connector)
6252 {
6253         enum pipe pipe = 0;
6254         struct intel_encoder *encoder = connector->encoder;
6255
6256         return encoder->get_hw_state(encoder, &pipe);
6257 }
6258
6259 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6260 {
6261         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6262                 return crtc_state->fdi_lanes;
6263
6264         return 0;
6265 }
6266
6267 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6268                                      struct intel_crtc_state *pipe_config)
6269 {
6270         struct drm_atomic_state *state = pipe_config->base.state;
6271         struct intel_crtc *other_crtc;
6272         struct intel_crtc_state *other_crtc_state;
6273
6274         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6275                       pipe_name(pipe), pipe_config->fdi_lanes);
6276         if (pipe_config->fdi_lanes > 4) {
6277                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6278                               pipe_name(pipe), pipe_config->fdi_lanes);
6279                 return -EINVAL;
6280         }
6281
6282         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6283                 if (pipe_config->fdi_lanes > 2) {
6284                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6285                                       pipe_config->fdi_lanes);
6286                         return -EINVAL;
6287                 } else {
6288                         return 0;
6289                 }
6290         }
6291
6292         if (INTEL_INFO(dev)->num_pipes == 2)
6293                 return 0;
6294
6295         /* Ivybridge 3 pipe is really complicated */
6296         switch (pipe) {
6297         case PIPE_A:
6298                 return 0;
6299         case PIPE_B:
6300                 if (pipe_config->fdi_lanes <= 2)
6301                         return 0;
6302
6303                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6304                 other_crtc_state =
6305                         intel_atomic_get_crtc_state(state, other_crtc);
6306                 if (IS_ERR(other_crtc_state))
6307                         return PTR_ERR(other_crtc_state);
6308
6309                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6310                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6311                                       pipe_name(pipe), pipe_config->fdi_lanes);
6312                         return -EINVAL;
6313                 }
6314                 return 0;
6315         case PIPE_C:
6316                 if (pipe_config->fdi_lanes > 2) {
6317                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6318                                       pipe_name(pipe), pipe_config->fdi_lanes);
6319                         return -EINVAL;
6320                 }
6321
6322                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6323                 other_crtc_state =
6324                         intel_atomic_get_crtc_state(state, other_crtc);
6325                 if (IS_ERR(other_crtc_state))
6326                         return PTR_ERR(other_crtc_state);
6327
6328                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6329                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6330                         return -EINVAL;
6331                 }
6332                 return 0;
6333         default:
6334                 BUG();
6335         }
6336 }
6337
6338 #define RETRY 1
6339 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6340                                        struct intel_crtc_state *pipe_config)
6341 {
6342         struct drm_device *dev = intel_crtc->base.dev;
6343         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6344         int lane, link_bw, fdi_dotclock, ret;
6345         bool needs_recompute = false;
6346
6347 retry:
6348         /* FDI is a binary signal running at ~2.7GHz, encoding
6349          * each output octet as 10 bits. The actual frequency
6350          * is stored as a divider into a 100MHz clock, and the
6351          * mode pixel clock is stored in units of 1KHz.
6352          * Hence the bw of each lane in terms of the mode signal
6353          * is:
6354          */
6355         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6356
6357         fdi_dotclock = adjusted_mode->crtc_clock;
6358
6359         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6360                                            pipe_config->pipe_bpp);
6361
6362         pipe_config->fdi_lanes = lane;
6363
6364         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6365                                link_bw, &pipe_config->fdi_m_n);
6366
6367         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6368                                        intel_crtc->pipe, pipe_config);
6369         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6370                 pipe_config->pipe_bpp -= 2*3;
6371                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6372                               pipe_config->pipe_bpp);
6373                 needs_recompute = true;
6374                 pipe_config->bw_constrained = true;
6375
6376                 goto retry;
6377         }
6378
6379         if (needs_recompute)
6380                 return RETRY;
6381
6382         return ret;
6383 }
6384
6385 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6386                                    struct intel_crtc_state *pipe_config)
6387 {
6388         pipe_config->ips_enabled = i915.enable_ips &&
6389                                    hsw_crtc_supports_ips(crtc) &&
6390                                    pipe_config->pipe_bpp <= 24;
6391 }
6392
6393 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6394                                      struct intel_crtc_state *pipe_config)
6395 {
6396         struct drm_device *dev = crtc->base.dev;
6397         struct drm_i915_private *dev_priv = dev->dev_private;
6398         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6399         int ret;
6400
6401         /* FIXME should check pixel clock limits on all platforms */
6402         if (INTEL_INFO(dev)->gen < 4) {
6403                 int clock_limit =
6404                         dev_priv->display.get_display_clock_speed(dev);
6405
6406                 /*
6407                  * Enable pixel doubling when the dot clock
6408                  * is > 90% of the (display) core speed.
6409                  *
6410                  * GDG double wide on either pipe,
6411                  * otherwise pipe A only.
6412                  */
6413                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6414                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6415                         clock_limit *= 2;
6416                         pipe_config->double_wide = true;
6417                 }
6418
6419                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6420                         return -EINVAL;
6421         }
6422
6423         /*
6424          * Pipe horizontal size must be even in:
6425          * - DVO ganged mode
6426          * - LVDS dual channel mode
6427          * - Double wide pipe
6428          */
6429         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6430              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6431                 pipe_config->pipe_src_w &= ~1;
6432
6433         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6434          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6435          */
6436         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6437                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6438                 return -EINVAL;
6439
6440         if (HAS_IPS(dev))
6441                 hsw_compute_ips_config(crtc, pipe_config);
6442
6443         if (pipe_config->has_pch_encoder)
6444                 return ironlake_fdi_compute_config(crtc, pipe_config);
6445
6446         /* FIXME: remove below call once atomic mode set is place and all crtc
6447          * related checks called from atomic_crtc_check function */
6448         ret = 0;
6449         DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6450                 crtc, pipe_config->base.state);
6451         ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6452
6453         return ret;
6454 }
6455
6456 static int skylake_get_display_clock_speed(struct drm_device *dev)
6457 {
6458         struct drm_i915_private *dev_priv = to_i915(dev);
6459         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6460         uint32_t cdctl = I915_READ(CDCLK_CTL);
6461         uint32_t linkrate;
6462
6463         if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6464                 WARN(1, "LCPLL1 not enabled\n");
6465                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6466         }
6467
6468         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6469                 return 540000;
6470
6471         linkrate = (I915_READ(DPLL_CTRL1) &
6472                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6473
6474         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6475             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6476                 /* vco 8640 */
6477                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6478                 case CDCLK_FREQ_450_432:
6479                         return 432000;
6480                 case CDCLK_FREQ_337_308:
6481                         return 308570;
6482                 case CDCLK_FREQ_675_617:
6483                         return 617140;
6484                 default:
6485                         WARN(1, "Unknown cd freq selection\n");
6486                 }
6487         } else {
6488                 /* vco 8100 */
6489                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6490                 case CDCLK_FREQ_450_432:
6491                         return 450000;
6492                 case CDCLK_FREQ_337_308:
6493                         return 337500;
6494                 case CDCLK_FREQ_675_617:
6495                         return 675000;
6496                 default:
6497                         WARN(1, "Unknown cd freq selection\n");
6498                 }
6499         }
6500
6501         /* error case, do as if DPLL0 isn't enabled */
6502         return 24000;
6503 }
6504
6505 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6506 {
6507         struct drm_i915_private *dev_priv = dev->dev_private;
6508         uint32_t lcpll = I915_READ(LCPLL_CTL);
6509         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6510
6511         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6512                 return 800000;
6513         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6514                 return 450000;
6515         else if (freq == LCPLL_CLK_FREQ_450)
6516                 return 450000;
6517         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6518                 return 540000;
6519         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6520                 return 337500;
6521         else
6522                 return 675000;
6523 }
6524
6525 static int haswell_get_display_clock_speed(struct drm_device *dev)
6526 {
6527         struct drm_i915_private *dev_priv = dev->dev_private;
6528         uint32_t lcpll = I915_READ(LCPLL_CTL);
6529         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6530
6531         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6532                 return 800000;
6533         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6534                 return 450000;
6535         else if (freq == LCPLL_CLK_FREQ_450)
6536                 return 450000;
6537         else if (IS_HSW_ULT(dev))
6538                 return 337500;
6539         else
6540                 return 540000;
6541 }
6542
6543 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6544 {
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546         u32 val;
6547         int divider;
6548
6549         if (dev_priv->hpll_freq == 0)
6550                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6551
6552         mutex_lock(&dev_priv->dpio_lock);
6553         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6554         mutex_unlock(&dev_priv->dpio_lock);
6555
6556         divider = val & DISPLAY_FREQUENCY_VALUES;
6557
6558         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6559              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6560              "cdclk change in progress\n");
6561
6562         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6563 }
6564
6565 static int ilk_get_display_clock_speed(struct drm_device *dev)
6566 {
6567         return 450000;
6568 }
6569
6570 static int i945_get_display_clock_speed(struct drm_device *dev)
6571 {
6572         return 400000;
6573 }
6574
6575 static int i915_get_display_clock_speed(struct drm_device *dev)
6576 {
6577         return 333333;
6578 }
6579
6580 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6581 {
6582         return 200000;
6583 }
6584
6585 static int pnv_get_display_clock_speed(struct drm_device *dev)
6586 {
6587         u16 gcfgc = 0;
6588
6589         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6590
6591         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6592         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6593                 return 266667;
6594         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6595                 return 333333;
6596         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6597                 return 444444;
6598         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6599                 return 200000;
6600         default:
6601                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6602         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6603                 return 133333;
6604         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6605                 return 166667;
6606         }
6607 }
6608
6609 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6610 {
6611         u16 gcfgc = 0;
6612
6613         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6614
6615         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6616                 return 133333;
6617         else {
6618                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6619                 case GC_DISPLAY_CLOCK_333_MHZ:
6620                         return 333333;
6621                 default:
6622                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6623                         return 190000;
6624                 }
6625         }
6626 }
6627
6628 static int i865_get_display_clock_speed(struct drm_device *dev)
6629 {
6630         return 266667;
6631 }
6632
6633 static int i855_get_display_clock_speed(struct drm_device *dev)
6634 {
6635         u16 hpllcc = 0;
6636         /* Assume that the hardware is in the high speed state.  This
6637          * should be the default.
6638          */
6639         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6640         case GC_CLOCK_133_200:
6641         case GC_CLOCK_100_200:
6642                 return 200000;
6643         case GC_CLOCK_166_250:
6644                 return 250000;
6645         case GC_CLOCK_100_133:
6646                 return 133333;
6647         }
6648
6649         /* Shouldn't happen */
6650         return 0;
6651 }
6652
6653 static int i830_get_display_clock_speed(struct drm_device *dev)
6654 {
6655         return 133333;
6656 }
6657
6658 static void
6659 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6660 {
6661         while (*num > DATA_LINK_M_N_MASK ||
6662                *den > DATA_LINK_M_N_MASK) {
6663                 *num >>= 1;
6664                 *den >>= 1;
6665         }
6666 }
6667
6668 static void compute_m_n(unsigned int m, unsigned int n,
6669                         uint32_t *ret_m, uint32_t *ret_n)
6670 {
6671         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6672         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6673         intel_reduce_m_n_ratio(ret_m, ret_n);
6674 }
6675
6676 void
6677 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6678                        int pixel_clock, int link_clock,
6679                        struct intel_link_m_n *m_n)
6680 {
6681         m_n->tu = 64;
6682
6683         compute_m_n(bits_per_pixel * pixel_clock,
6684                     link_clock * nlanes * 8,
6685                     &m_n->gmch_m, &m_n->gmch_n);
6686
6687         compute_m_n(pixel_clock, link_clock,
6688                     &m_n->link_m, &m_n->link_n);
6689 }
6690
6691 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6692 {
6693         if (i915.panel_use_ssc >= 0)
6694                 return i915.panel_use_ssc != 0;
6695         return dev_priv->vbt.lvds_use_ssc
6696                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6697 }
6698
6699 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6700                            int num_connectors)
6701 {
6702         struct drm_device *dev = crtc_state->base.crtc->dev;
6703         struct drm_i915_private *dev_priv = dev->dev_private;
6704         int refclk;
6705
6706         WARN_ON(!crtc_state->base.state);
6707
6708         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6709                 refclk = 100000;
6710         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6711             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6712                 refclk = dev_priv->vbt.lvds_ssc_freq;
6713                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6714         } else if (!IS_GEN2(dev)) {
6715                 refclk = 96000;
6716         } else {
6717                 refclk = 48000;
6718         }
6719
6720         return refclk;
6721 }
6722
6723 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6724 {
6725         return (1 << dpll->n) << 16 | dpll->m2;
6726 }
6727
6728 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6729 {
6730         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6731 }
6732
6733 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6734                                      struct intel_crtc_state *crtc_state,
6735                                      intel_clock_t *reduced_clock)
6736 {
6737         struct drm_device *dev = crtc->base.dev;
6738         u32 fp, fp2 = 0;
6739
6740         if (IS_PINEVIEW(dev)) {
6741                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6742                 if (reduced_clock)
6743                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6744         } else {
6745                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6746                 if (reduced_clock)
6747                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6748         }
6749
6750         crtc_state->dpll_hw_state.fp0 = fp;
6751
6752         crtc->lowfreq_avail = false;
6753         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6754             reduced_clock) {
6755                 crtc_state->dpll_hw_state.fp1 = fp2;
6756                 crtc->lowfreq_avail = true;
6757         } else {
6758                 crtc_state->dpll_hw_state.fp1 = fp;
6759         }
6760 }
6761
6762 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6763                 pipe)
6764 {
6765         u32 reg_val;
6766
6767         /*
6768          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6769          * and set it to a reasonable value instead.
6770          */
6771         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6772         reg_val &= 0xffffff00;
6773         reg_val |= 0x00000030;
6774         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6775
6776         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6777         reg_val &= 0x8cffffff;
6778         reg_val = 0x8c000000;
6779         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6780
6781         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6782         reg_val &= 0xffffff00;
6783         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6784
6785         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6786         reg_val &= 0x00ffffff;
6787         reg_val |= 0xb0000000;
6788         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6789 }
6790
6791 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6792                                          struct intel_link_m_n *m_n)
6793 {
6794         struct drm_device *dev = crtc->base.dev;
6795         struct drm_i915_private *dev_priv = dev->dev_private;
6796         int pipe = crtc->pipe;
6797
6798         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6799         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6800         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6801         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6802 }
6803
6804 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6805                                          struct intel_link_m_n *m_n,
6806                                          struct intel_link_m_n *m2_n2)
6807 {
6808         struct drm_device *dev = crtc->base.dev;
6809         struct drm_i915_private *dev_priv = dev->dev_private;
6810         int pipe = crtc->pipe;
6811         enum transcoder transcoder = crtc->config->cpu_transcoder;
6812
6813         if (INTEL_INFO(dev)->gen >= 5) {
6814                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6815                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6816                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6817                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6818                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6819                  * for gen < 8) and if DRRS is supported (to make sure the
6820                  * registers are not unnecessarily accessed).
6821                  */
6822                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6823                         crtc->config->has_drrs) {
6824                         I915_WRITE(PIPE_DATA_M2(transcoder),
6825                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6826                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6827                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6828                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6829                 }
6830         } else {
6831                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6832                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6833                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6834                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6835         }
6836 }
6837
6838 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6839 {
6840         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6841
6842         if (m_n == M1_N1) {
6843                 dp_m_n = &crtc->config->dp_m_n;
6844                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6845         } else if (m_n == M2_N2) {
6846
6847                 /*
6848                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6849                  * needs to be programmed into M1_N1.
6850                  */
6851                 dp_m_n = &crtc->config->dp_m2_n2;
6852         } else {
6853                 DRM_ERROR("Unsupported divider value\n");
6854                 return;
6855         }
6856
6857         if (crtc->config->has_pch_encoder)
6858                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6859         else
6860                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6861 }
6862
6863 static void vlv_update_pll(struct intel_crtc *crtc,
6864                            struct intel_crtc_state *pipe_config)
6865 {
6866         u32 dpll, dpll_md;
6867
6868         /*
6869          * Enable DPIO clock input. We should never disable the reference
6870          * clock for pipe B, since VGA hotplug / manual detection depends
6871          * on it.
6872          */
6873         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6874                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6875         /* We should never disable this, set it here for state tracking */
6876         if (crtc->pipe == PIPE_B)
6877                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6878         dpll |= DPLL_VCO_ENABLE;
6879         pipe_config->dpll_hw_state.dpll = dpll;
6880
6881         dpll_md = (pipe_config->pixel_multiplier - 1)
6882                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6883         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6884 }
6885
6886 static void vlv_prepare_pll(struct intel_crtc *crtc,
6887                             const struct intel_crtc_state *pipe_config)
6888 {
6889         struct drm_device *dev = crtc->base.dev;
6890         struct drm_i915_private *dev_priv = dev->dev_private;
6891         int pipe = crtc->pipe;
6892         u32 mdiv;
6893         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6894         u32 coreclk, reg_val;
6895
6896         mutex_lock(&dev_priv->dpio_lock);
6897
6898         bestn = pipe_config->dpll.n;
6899         bestm1 = pipe_config->dpll.m1;
6900         bestm2 = pipe_config->dpll.m2;
6901         bestp1 = pipe_config->dpll.p1;
6902         bestp2 = pipe_config->dpll.p2;
6903
6904         /* See eDP HDMI DPIO driver vbios notes doc */
6905
6906         /* PLL B needs special handling */
6907         if (pipe == PIPE_B)
6908                 vlv_pllb_recal_opamp(dev_priv, pipe);
6909
6910         /* Set up Tx target for periodic Rcomp update */
6911         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6912
6913         /* Disable target IRef on PLL */
6914         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6915         reg_val &= 0x00ffffff;
6916         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6917
6918         /* Disable fast lock */
6919         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6920
6921         /* Set idtafcrecal before PLL is enabled */
6922         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6923         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6924         mdiv |= ((bestn << DPIO_N_SHIFT));
6925         mdiv |= (1 << DPIO_K_SHIFT);
6926
6927         /*
6928          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6929          * but we don't support that).
6930          * Note: don't use the DAC post divider as it seems unstable.
6931          */
6932         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6933         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6934
6935         mdiv |= DPIO_ENABLE_CALIBRATION;
6936         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6937
6938         /* Set HBR and RBR LPF coefficients */
6939         if (pipe_config->port_clock == 162000 ||
6940             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6941             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6942                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6943                                  0x009f0003);
6944         else
6945                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6946                                  0x00d0000f);
6947
6948         if (pipe_config->has_dp_encoder) {
6949                 /* Use SSC source */
6950                 if (pipe == PIPE_A)
6951                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6952                                          0x0df40000);
6953                 else
6954                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6955                                          0x0df70000);
6956         } else { /* HDMI or VGA */
6957                 /* Use bend source */
6958                 if (pipe == PIPE_A)
6959                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6960                                          0x0df70000);
6961                 else
6962                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6963                                          0x0df40000);
6964         }
6965
6966         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6967         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6968         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6969             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6970                 coreclk |= 0x01000000;
6971         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6972
6973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6974         mutex_unlock(&dev_priv->dpio_lock);
6975 }
6976
6977 static void chv_update_pll(struct intel_crtc *crtc,
6978                            struct intel_crtc_state *pipe_config)
6979 {
6980         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6981                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6982                 DPLL_VCO_ENABLE;
6983         if (crtc->pipe != PIPE_A)
6984                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6985
6986         pipe_config->dpll_hw_state.dpll_md =
6987                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6988 }
6989
6990 static void chv_prepare_pll(struct intel_crtc *crtc,
6991                             const struct intel_crtc_state *pipe_config)
6992 {
6993         struct drm_device *dev = crtc->base.dev;
6994         struct drm_i915_private *dev_priv = dev->dev_private;
6995         int pipe = crtc->pipe;
6996         int dpll_reg = DPLL(crtc->pipe);
6997         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6998         u32 loopfilter, tribuf_calcntr;
6999         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7000         u32 dpio_val;
7001         int vco;
7002
7003         bestn = pipe_config->dpll.n;
7004         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7005         bestm1 = pipe_config->dpll.m1;
7006         bestm2 = pipe_config->dpll.m2 >> 22;
7007         bestp1 = pipe_config->dpll.p1;
7008         bestp2 = pipe_config->dpll.p2;
7009         vco = pipe_config->dpll.vco;
7010         dpio_val = 0;
7011         loopfilter = 0;
7012
7013         /*
7014          * Enable Refclk and SSC
7015          */
7016         I915_WRITE(dpll_reg,
7017                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7018
7019         mutex_lock(&dev_priv->dpio_lock);
7020
7021         /* p1 and p2 divider */
7022         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7023                         5 << DPIO_CHV_S1_DIV_SHIFT |
7024                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7025                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7026                         1 << DPIO_CHV_K_DIV_SHIFT);
7027
7028         /* Feedback post-divider - m2 */
7029         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7030
7031         /* Feedback refclk divider - n and m1 */
7032         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7033                         DPIO_CHV_M1_DIV_BY_2 |
7034                         1 << DPIO_CHV_N_DIV_SHIFT);
7035
7036         /* M2 fraction division */
7037         if (bestm2_frac)
7038                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7039
7040         /* M2 fraction division enable */
7041         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7042         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7043         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7044         if (bestm2_frac)
7045                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7046         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7047
7048         /* Program digital lock detect threshold */
7049         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7050         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7051                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7052         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7053         if (!bestm2_frac)
7054                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7055         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7056
7057         /* Loop filter */
7058         if (vco == 5400000) {
7059                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7060                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7061                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7062                 tribuf_calcntr = 0x9;
7063         } else if (vco <= 6200000) {
7064                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7065                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7066                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7067                 tribuf_calcntr = 0x9;
7068         } else if (vco <= 6480000) {
7069                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7070                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7071                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7072                 tribuf_calcntr = 0x8;
7073         } else {
7074                 /* Not supported. Apply the same limits as in the max case */
7075                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7076                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7077                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7078                 tribuf_calcntr = 0;
7079         }
7080         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7081
7082         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7083         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7084         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7085         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7086
7087         /* AFC Recal */
7088         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7089                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7090                         DPIO_AFC_RECAL);
7091
7092         mutex_unlock(&dev_priv->dpio_lock);
7093 }
7094
7095 /**
7096  * vlv_force_pll_on - forcibly enable just the PLL
7097  * @dev_priv: i915 private structure
7098  * @pipe: pipe PLL to enable
7099  * @dpll: PLL configuration
7100  *
7101  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7102  * in cases where we need the PLL enabled even when @pipe is not going to
7103  * be enabled.
7104  */
7105 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7106                       const struct dpll *dpll)
7107 {
7108         struct intel_crtc *crtc =
7109                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7110         struct intel_crtc_state pipe_config = {
7111                 .base.crtc = &crtc->base,
7112                 .pixel_multiplier = 1,
7113                 .dpll = *dpll,
7114         };
7115
7116         if (IS_CHERRYVIEW(dev)) {
7117                 chv_update_pll(crtc, &pipe_config);
7118                 chv_prepare_pll(crtc, &pipe_config);
7119                 chv_enable_pll(crtc, &pipe_config);
7120         } else {
7121                 vlv_update_pll(crtc, &pipe_config);
7122                 vlv_prepare_pll(crtc, &pipe_config);
7123                 vlv_enable_pll(crtc, &pipe_config);
7124         }
7125 }
7126
7127 /**
7128  * vlv_force_pll_off - forcibly disable just the PLL
7129  * @dev_priv: i915 private structure
7130  * @pipe: pipe PLL to disable
7131  *
7132  * Disable the PLL for @pipe. To be used in cases where we need
7133  * the PLL enabled even when @pipe is not going to be enabled.
7134  */
7135 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7136 {
7137         if (IS_CHERRYVIEW(dev))
7138                 chv_disable_pll(to_i915(dev), pipe);
7139         else
7140                 vlv_disable_pll(to_i915(dev), pipe);
7141 }
7142
7143 static void i9xx_update_pll(struct intel_crtc *crtc,
7144                             struct intel_crtc_state *crtc_state,
7145                             intel_clock_t *reduced_clock,
7146                             int num_connectors)
7147 {
7148         struct drm_device *dev = crtc->base.dev;
7149         struct drm_i915_private *dev_priv = dev->dev_private;
7150         u32 dpll;
7151         bool is_sdvo;
7152         struct dpll *clock = &crtc_state->dpll;
7153
7154         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7155
7156         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7157                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7158
7159         dpll = DPLL_VGA_MODE_DIS;
7160
7161         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7162                 dpll |= DPLLB_MODE_LVDS;
7163         else
7164                 dpll |= DPLLB_MODE_DAC_SERIAL;
7165
7166         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7167                 dpll |= (crtc_state->pixel_multiplier - 1)
7168                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7169         }
7170
7171         if (is_sdvo)
7172                 dpll |= DPLL_SDVO_HIGH_SPEED;
7173
7174         if (crtc_state->has_dp_encoder)
7175                 dpll |= DPLL_SDVO_HIGH_SPEED;
7176
7177         /* compute bitmask from p1 value */
7178         if (IS_PINEVIEW(dev))
7179                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7180         else {
7181                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7182                 if (IS_G4X(dev) && reduced_clock)
7183                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7184         }
7185         switch (clock->p2) {
7186         case 5:
7187                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7188                 break;
7189         case 7:
7190                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7191                 break;
7192         case 10:
7193                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7194                 break;
7195         case 14:
7196                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7197                 break;
7198         }
7199         if (INTEL_INFO(dev)->gen >= 4)
7200                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7201
7202         if (crtc_state->sdvo_tv_clock)
7203                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7204         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7205                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7206                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7207         else
7208                 dpll |= PLL_REF_INPUT_DREFCLK;
7209
7210         dpll |= DPLL_VCO_ENABLE;
7211         crtc_state->dpll_hw_state.dpll = dpll;
7212
7213         if (INTEL_INFO(dev)->gen >= 4) {
7214                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7215                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7216                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7217         }
7218 }
7219
7220 static void i8xx_update_pll(struct intel_crtc *crtc,
7221                             struct intel_crtc_state *crtc_state,
7222                             intel_clock_t *reduced_clock,
7223                             int num_connectors)
7224 {
7225         struct drm_device *dev = crtc->base.dev;
7226         struct drm_i915_private *dev_priv = dev->dev_private;
7227         u32 dpll;
7228         struct dpll *clock = &crtc_state->dpll;
7229
7230         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7231
7232         dpll = DPLL_VGA_MODE_DIS;
7233
7234         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7235                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7236         } else {
7237                 if (clock->p1 == 2)
7238                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7239                 else
7240                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7241                 if (clock->p2 == 4)
7242                         dpll |= PLL_P2_DIVIDE_BY_4;
7243         }
7244
7245         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7246                 dpll |= DPLL_DVO_2X_MODE;
7247
7248         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7249                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7250                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7251         else
7252                 dpll |= PLL_REF_INPUT_DREFCLK;
7253
7254         dpll |= DPLL_VCO_ENABLE;
7255         crtc_state->dpll_hw_state.dpll = dpll;
7256 }
7257
7258 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7259 {
7260         struct drm_device *dev = intel_crtc->base.dev;
7261         struct drm_i915_private *dev_priv = dev->dev_private;
7262         enum pipe pipe = intel_crtc->pipe;
7263         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7264         struct drm_display_mode *adjusted_mode =
7265                 &intel_crtc->config->base.adjusted_mode;
7266         uint32_t crtc_vtotal, crtc_vblank_end;
7267         int vsyncshift = 0;
7268
7269         /* We need to be careful not to changed the adjusted mode, for otherwise
7270          * the hw state checker will get angry at the mismatch. */
7271         crtc_vtotal = adjusted_mode->crtc_vtotal;
7272         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7273
7274         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7275                 /* the chip adds 2 halflines automatically */
7276                 crtc_vtotal -= 1;
7277                 crtc_vblank_end -= 1;
7278
7279                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7280                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7281                 else
7282                         vsyncshift = adjusted_mode->crtc_hsync_start -
7283                                 adjusted_mode->crtc_htotal / 2;
7284                 if (vsyncshift < 0)
7285                         vsyncshift += adjusted_mode->crtc_htotal;
7286         }
7287
7288         if (INTEL_INFO(dev)->gen > 3)
7289                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7290
7291         I915_WRITE(HTOTAL(cpu_transcoder),
7292                    (adjusted_mode->crtc_hdisplay - 1) |
7293                    ((adjusted_mode->crtc_htotal - 1) << 16));
7294         I915_WRITE(HBLANK(cpu_transcoder),
7295                    (adjusted_mode->crtc_hblank_start - 1) |
7296                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7297         I915_WRITE(HSYNC(cpu_transcoder),
7298                    (adjusted_mode->crtc_hsync_start - 1) |
7299                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7300
7301         I915_WRITE(VTOTAL(cpu_transcoder),
7302                    (adjusted_mode->crtc_vdisplay - 1) |
7303                    ((crtc_vtotal - 1) << 16));
7304         I915_WRITE(VBLANK(cpu_transcoder),
7305                    (adjusted_mode->crtc_vblank_start - 1) |
7306                    ((crtc_vblank_end - 1) << 16));
7307         I915_WRITE(VSYNC(cpu_transcoder),
7308                    (adjusted_mode->crtc_vsync_start - 1) |
7309                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7310
7311         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7312          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7313          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7314          * bits. */
7315         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7316             (pipe == PIPE_B || pipe == PIPE_C))
7317                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7318
7319         /* pipesrc controls the size that is scaled from, which should
7320          * always be the user's requested size.
7321          */
7322         I915_WRITE(PIPESRC(pipe),
7323                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7324                    (intel_crtc->config->pipe_src_h - 1));
7325 }
7326
7327 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7328                                    struct intel_crtc_state *pipe_config)
7329 {
7330         struct drm_device *dev = crtc->base.dev;
7331         struct drm_i915_private *dev_priv = dev->dev_private;
7332         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7333         uint32_t tmp;
7334
7335         tmp = I915_READ(HTOTAL(cpu_transcoder));
7336         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7337         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7338         tmp = I915_READ(HBLANK(cpu_transcoder));
7339         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7340         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7341         tmp = I915_READ(HSYNC(cpu_transcoder));
7342         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7343         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7344
7345         tmp = I915_READ(VTOTAL(cpu_transcoder));
7346         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7347         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7348         tmp = I915_READ(VBLANK(cpu_transcoder));
7349         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7350         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7351         tmp = I915_READ(VSYNC(cpu_transcoder));
7352         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7353         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7354
7355         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7356                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7357                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7358                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7359         }
7360
7361         tmp = I915_READ(PIPESRC(crtc->pipe));
7362         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7363         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7364
7365         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7366         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7367 }
7368
7369 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7370                                  struct intel_crtc_state *pipe_config)
7371 {
7372         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7373         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7374         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7375         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7376
7377         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7378         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7379         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7380         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7381
7382         mode->flags = pipe_config->base.adjusted_mode.flags;
7383
7384         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7385         mode->flags |= pipe_config->base.adjusted_mode.flags;
7386 }
7387
7388 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7389 {
7390         struct drm_device *dev = intel_crtc->base.dev;
7391         struct drm_i915_private *dev_priv = dev->dev_private;
7392         uint32_t pipeconf;
7393
7394         pipeconf = 0;
7395
7396         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7397             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7398                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7399
7400         if (intel_crtc->config->double_wide)
7401                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7402
7403         /* only g4x and later have fancy bpc/dither controls */
7404         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7405                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7406                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7407                         pipeconf |= PIPECONF_DITHER_EN |
7408                                     PIPECONF_DITHER_TYPE_SP;
7409
7410                 switch (intel_crtc->config->pipe_bpp) {
7411                 case 18:
7412                         pipeconf |= PIPECONF_6BPC;
7413                         break;
7414                 case 24:
7415                         pipeconf |= PIPECONF_8BPC;
7416                         break;
7417                 case 30:
7418                         pipeconf |= PIPECONF_10BPC;
7419                         break;
7420                 default:
7421                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7422                         BUG();
7423                 }
7424         }
7425
7426         if (HAS_PIPE_CXSR(dev)) {
7427                 if (intel_crtc->lowfreq_avail) {
7428                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7429                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7430                 } else {
7431                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7432                 }
7433         }
7434
7435         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7436                 if (INTEL_INFO(dev)->gen < 4 ||
7437                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7438                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7439                 else
7440                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7441         } else
7442                 pipeconf |= PIPECONF_PROGRESSIVE;
7443
7444         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7445                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7446
7447         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7448         POSTING_READ(PIPECONF(intel_crtc->pipe));
7449 }
7450
7451 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7452                                    struct intel_crtc_state *crtc_state)
7453 {
7454         struct drm_device *dev = crtc->base.dev;
7455         struct drm_i915_private *dev_priv = dev->dev_private;
7456         int refclk, num_connectors = 0;
7457         intel_clock_t clock, reduced_clock;
7458         bool ok, has_reduced_clock = false;
7459         bool is_lvds = false, is_dsi = false;
7460         struct intel_encoder *encoder;
7461         const intel_limit_t *limit;
7462         struct drm_atomic_state *state = crtc_state->base.state;
7463         struct drm_connector *connector;
7464         struct drm_connector_state *connector_state;
7465         int i;
7466
7467         for_each_connector_in_state(state, connector, connector_state, i) {
7468                 if (connector_state->crtc != &crtc->base)
7469                         continue;
7470
7471                 encoder = to_intel_encoder(connector_state->best_encoder);
7472
7473                 switch (encoder->type) {
7474                 case INTEL_OUTPUT_LVDS:
7475                         is_lvds = true;
7476                         break;
7477                 case INTEL_OUTPUT_DSI:
7478                         is_dsi = true;
7479                         break;
7480                 default:
7481                         break;
7482                 }
7483
7484                 num_connectors++;
7485         }
7486
7487         if (is_dsi)
7488                 return 0;
7489
7490         if (!crtc_state->clock_set) {
7491                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7492
7493                 /*
7494                  * Returns a set of divisors for the desired target clock with
7495                  * the given refclk, or FALSE.  The returned values represent
7496                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7497                  * 2) / p1 / p2.
7498                  */
7499                 limit = intel_limit(crtc_state, refclk);
7500                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7501                                                  crtc_state->port_clock,
7502                                                  refclk, NULL, &clock);
7503                 if (!ok) {
7504                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7505                         return -EINVAL;
7506                 }
7507
7508                 if (is_lvds && dev_priv->lvds_downclock_avail) {
7509                         /*
7510                          * Ensure we match the reduced clock's P to the target
7511                          * clock.  If the clocks don't match, we can't switch
7512                          * the display clock by using the FP0/FP1. In such case
7513                          * we will disable the LVDS downclock feature.
7514                          */
7515                         has_reduced_clock =
7516                                 dev_priv->display.find_dpll(limit, crtc_state,
7517                                                             dev_priv->lvds_downclock,
7518                                                             refclk, &clock,
7519                                                             &reduced_clock);
7520                 }
7521                 /* Compat-code for transition, will disappear. */
7522                 crtc_state->dpll.n = clock.n;
7523                 crtc_state->dpll.m1 = clock.m1;
7524                 crtc_state->dpll.m2 = clock.m2;
7525                 crtc_state->dpll.p1 = clock.p1;
7526                 crtc_state->dpll.p2 = clock.p2;
7527         }
7528
7529         if (IS_GEN2(dev)) {
7530                 i8xx_update_pll(crtc, crtc_state,
7531                                 has_reduced_clock ? &reduced_clock : NULL,
7532                                 num_connectors);
7533         } else if (IS_CHERRYVIEW(dev)) {
7534                 chv_update_pll(crtc, crtc_state);
7535         } else if (IS_VALLEYVIEW(dev)) {
7536                 vlv_update_pll(crtc, crtc_state);
7537         } else {
7538                 i9xx_update_pll(crtc, crtc_state,
7539                                 has_reduced_clock ? &reduced_clock : NULL,
7540                                 num_connectors);
7541         }
7542
7543         return 0;
7544 }
7545
7546 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7547                                  struct intel_crtc_state *pipe_config)
7548 {
7549         struct drm_device *dev = crtc->base.dev;
7550         struct drm_i915_private *dev_priv = dev->dev_private;
7551         uint32_t tmp;
7552
7553         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7554                 return;
7555
7556         tmp = I915_READ(PFIT_CONTROL);
7557         if (!(tmp & PFIT_ENABLE))
7558                 return;
7559
7560         /* Check whether the pfit is attached to our pipe. */
7561         if (INTEL_INFO(dev)->gen < 4) {
7562                 if (crtc->pipe != PIPE_B)
7563                         return;
7564         } else {
7565                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7566                         return;
7567         }
7568
7569         pipe_config->gmch_pfit.control = tmp;
7570         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7571         if (INTEL_INFO(dev)->gen < 5)
7572                 pipe_config->gmch_pfit.lvds_border_bits =
7573                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7574 }
7575
7576 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7577                                struct intel_crtc_state *pipe_config)
7578 {
7579         struct drm_device *dev = crtc->base.dev;
7580         struct drm_i915_private *dev_priv = dev->dev_private;
7581         int pipe = pipe_config->cpu_transcoder;
7582         intel_clock_t clock;
7583         u32 mdiv;
7584         int refclk = 100000;
7585
7586         /* In case of MIPI DPLL will not even be used */
7587         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7588                 return;
7589
7590         mutex_lock(&dev_priv->dpio_lock);
7591         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7592         mutex_unlock(&dev_priv->dpio_lock);
7593
7594         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7595         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7596         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7597         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7598         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7599
7600         vlv_clock(refclk, &clock);
7601
7602         /* clock.dot is the fast clock */
7603         pipe_config->port_clock = clock.dot / 5;
7604 }
7605
7606 static void
7607 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7608                               struct intel_initial_plane_config *plane_config)
7609 {
7610         struct drm_device *dev = crtc->base.dev;
7611         struct drm_i915_private *dev_priv = dev->dev_private;
7612         u32 val, base, offset;
7613         int pipe = crtc->pipe, plane = crtc->plane;
7614         int fourcc, pixel_format;
7615         unsigned int aligned_height;
7616         struct drm_framebuffer *fb;
7617         struct intel_framebuffer *intel_fb;
7618
7619         val = I915_READ(DSPCNTR(plane));
7620         if (!(val & DISPLAY_PLANE_ENABLE))
7621                 return;
7622
7623         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7624         if (!intel_fb) {
7625                 DRM_DEBUG_KMS("failed to alloc fb\n");
7626                 return;
7627         }
7628
7629         fb = &intel_fb->base;
7630
7631         if (INTEL_INFO(dev)->gen >= 4) {
7632                 if (val & DISPPLANE_TILED) {
7633                         plane_config->tiling = I915_TILING_X;
7634                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7635                 }
7636         }
7637
7638         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7639         fourcc = i9xx_format_to_fourcc(pixel_format);
7640         fb->pixel_format = fourcc;
7641         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7642
7643         if (INTEL_INFO(dev)->gen >= 4) {
7644                 if (plane_config->tiling)
7645                         offset = I915_READ(DSPTILEOFF(plane));
7646                 else
7647                         offset = I915_READ(DSPLINOFF(plane));
7648                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7649         } else {
7650                 base = I915_READ(DSPADDR(plane));
7651         }
7652         plane_config->base = base;
7653
7654         val = I915_READ(PIPESRC(pipe));
7655         fb->width = ((val >> 16) & 0xfff) + 1;
7656         fb->height = ((val >> 0) & 0xfff) + 1;
7657
7658         val = I915_READ(DSPSTRIDE(pipe));
7659         fb->pitches[0] = val & 0xffffffc0;
7660
7661         aligned_height = intel_fb_align_height(dev, fb->height,
7662                                                fb->pixel_format,
7663                                                fb->modifier[0]);
7664
7665         plane_config->size = fb->pitches[0] * aligned_height;
7666
7667         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7668                       pipe_name(pipe), plane, fb->width, fb->height,
7669                       fb->bits_per_pixel, base, fb->pitches[0],
7670                       plane_config->size);
7671
7672         plane_config->fb = intel_fb;
7673 }
7674
7675 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7676                                struct intel_crtc_state *pipe_config)
7677 {
7678         struct drm_device *dev = crtc->base.dev;
7679         struct drm_i915_private *dev_priv = dev->dev_private;
7680         int pipe = pipe_config->cpu_transcoder;
7681         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7682         intel_clock_t clock;
7683         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7684         int refclk = 100000;
7685
7686         mutex_lock(&dev_priv->dpio_lock);
7687         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7688         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7689         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7690         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7691         mutex_unlock(&dev_priv->dpio_lock);
7692
7693         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7694         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7695         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7696         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7697         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7698
7699         chv_clock(refclk, &clock);
7700
7701         /* clock.dot is the fast clock */
7702         pipe_config->port_clock = clock.dot / 5;
7703 }
7704
7705 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7706                                  struct intel_crtc_state *pipe_config)
7707 {
7708         struct drm_device *dev = crtc->base.dev;
7709         struct drm_i915_private *dev_priv = dev->dev_private;
7710         uint32_t tmp;
7711
7712         if (!intel_display_power_is_enabled(dev_priv,
7713                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7714                 return false;
7715
7716         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7717         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7718
7719         tmp = I915_READ(PIPECONF(crtc->pipe));
7720         if (!(tmp & PIPECONF_ENABLE))
7721                 return false;
7722
7723         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7724                 switch (tmp & PIPECONF_BPC_MASK) {
7725                 case PIPECONF_6BPC:
7726                         pipe_config->pipe_bpp = 18;
7727                         break;
7728                 case PIPECONF_8BPC:
7729                         pipe_config->pipe_bpp = 24;
7730                         break;
7731                 case PIPECONF_10BPC:
7732                         pipe_config->pipe_bpp = 30;
7733                         break;
7734                 default:
7735                         break;
7736                 }
7737         }
7738
7739         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7740                 pipe_config->limited_color_range = true;
7741
7742         if (INTEL_INFO(dev)->gen < 4)
7743                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7744
7745         intel_get_pipe_timings(crtc, pipe_config);
7746
7747         i9xx_get_pfit_config(crtc, pipe_config);
7748
7749         if (INTEL_INFO(dev)->gen >= 4) {
7750                 tmp = I915_READ(DPLL_MD(crtc->pipe));
7751                 pipe_config->pixel_multiplier =
7752                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7753                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7754                 pipe_config->dpll_hw_state.dpll_md = tmp;
7755         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7756                 tmp = I915_READ(DPLL(crtc->pipe));
7757                 pipe_config->pixel_multiplier =
7758                         ((tmp & SDVO_MULTIPLIER_MASK)
7759                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7760         } else {
7761                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7762                  * port and will be fixed up in the encoder->get_config
7763                  * function. */
7764                 pipe_config->pixel_multiplier = 1;
7765         }
7766         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7767         if (!IS_VALLEYVIEW(dev)) {
7768                 /*
7769                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7770                  * on 830. Filter it out here so that we don't
7771                  * report errors due to that.
7772                  */
7773                 if (IS_I830(dev))
7774                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7775
7776                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7777                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7778         } else {
7779                 /* Mask out read-only status bits. */
7780                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7781                                                      DPLL_PORTC_READY_MASK |
7782                                                      DPLL_PORTB_READY_MASK);
7783         }
7784
7785         if (IS_CHERRYVIEW(dev))
7786                 chv_crtc_clock_get(crtc, pipe_config);
7787         else if (IS_VALLEYVIEW(dev))
7788                 vlv_crtc_clock_get(crtc, pipe_config);
7789         else
7790                 i9xx_crtc_clock_get(crtc, pipe_config);
7791
7792         return true;
7793 }
7794
7795 static void ironlake_init_pch_refclk(struct drm_device *dev)
7796 {
7797         struct drm_i915_private *dev_priv = dev->dev_private;
7798         struct intel_encoder *encoder;
7799         u32 val, final;
7800         bool has_lvds = false;
7801         bool has_cpu_edp = false;
7802         bool has_panel = false;
7803         bool has_ck505 = false;
7804         bool can_ssc = false;
7805
7806         /* We need to take the global config into account */
7807         for_each_intel_encoder(dev, encoder) {
7808                 switch (encoder->type) {
7809                 case INTEL_OUTPUT_LVDS:
7810                         has_panel = true;
7811                         has_lvds = true;
7812                         break;
7813                 case INTEL_OUTPUT_EDP:
7814                         has_panel = true;
7815                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7816                                 has_cpu_edp = true;
7817                         break;
7818                 default:
7819                         break;
7820                 }
7821         }
7822
7823         if (HAS_PCH_IBX(dev)) {
7824                 has_ck505 = dev_priv->vbt.display_clock_mode;
7825                 can_ssc = has_ck505;
7826         } else {
7827                 has_ck505 = false;
7828                 can_ssc = true;
7829         }
7830
7831         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7832                       has_panel, has_lvds, has_ck505);
7833
7834         /* Ironlake: try to setup display ref clock before DPLL
7835          * enabling. This is only under driver's control after
7836          * PCH B stepping, previous chipset stepping should be
7837          * ignoring this setting.
7838          */
7839         val = I915_READ(PCH_DREF_CONTROL);
7840
7841         /* As we must carefully and slowly disable/enable each source in turn,
7842          * compute the final state we want first and check if we need to
7843          * make any changes at all.
7844          */
7845         final = val;
7846         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7847         if (has_ck505)
7848                 final |= DREF_NONSPREAD_CK505_ENABLE;
7849         else
7850                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7851
7852         final &= ~DREF_SSC_SOURCE_MASK;
7853         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7854         final &= ~DREF_SSC1_ENABLE;
7855
7856         if (has_panel) {
7857                 final |= DREF_SSC_SOURCE_ENABLE;
7858
7859                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7860                         final |= DREF_SSC1_ENABLE;
7861
7862                 if (has_cpu_edp) {
7863                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7864                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7865                         else
7866                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7867                 } else
7868                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7869         } else {
7870                 final |= DREF_SSC_SOURCE_DISABLE;
7871                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7872         }
7873
7874         if (final == val)
7875                 return;
7876
7877         /* Always enable nonspread source */
7878         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7879
7880         if (has_ck505)
7881                 val |= DREF_NONSPREAD_CK505_ENABLE;
7882         else
7883                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7884
7885         if (has_panel) {
7886                 val &= ~DREF_SSC_SOURCE_MASK;
7887                 val |= DREF_SSC_SOURCE_ENABLE;
7888
7889                 /* SSC must be turned on before enabling the CPU output  */
7890                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7891                         DRM_DEBUG_KMS("Using SSC on panel\n");
7892                         val |= DREF_SSC1_ENABLE;
7893                 } else
7894                         val &= ~DREF_SSC1_ENABLE;
7895
7896                 /* Get SSC going before enabling the outputs */
7897                 I915_WRITE(PCH_DREF_CONTROL, val);
7898                 POSTING_READ(PCH_DREF_CONTROL);
7899                 udelay(200);
7900
7901                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7902
7903                 /* Enable CPU source on CPU attached eDP */
7904                 if (has_cpu_edp) {
7905                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7906                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7907                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7908                         } else
7909                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7910                 } else
7911                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7912
7913                 I915_WRITE(PCH_DREF_CONTROL, val);
7914                 POSTING_READ(PCH_DREF_CONTROL);
7915                 udelay(200);
7916         } else {
7917                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7918
7919                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7920
7921                 /* Turn off CPU output */
7922                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7923
7924                 I915_WRITE(PCH_DREF_CONTROL, val);
7925                 POSTING_READ(PCH_DREF_CONTROL);
7926                 udelay(200);
7927
7928                 /* Turn off the SSC source */
7929                 val &= ~DREF_SSC_SOURCE_MASK;
7930                 val |= DREF_SSC_SOURCE_DISABLE;
7931
7932                 /* Turn off SSC1 */
7933                 val &= ~DREF_SSC1_ENABLE;
7934
7935                 I915_WRITE(PCH_DREF_CONTROL, val);
7936                 POSTING_READ(PCH_DREF_CONTROL);
7937                 udelay(200);
7938         }
7939
7940         BUG_ON(val != final);
7941 }
7942
7943 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7944 {
7945         uint32_t tmp;
7946
7947         tmp = I915_READ(SOUTH_CHICKEN2);
7948         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7949         I915_WRITE(SOUTH_CHICKEN2, tmp);
7950
7951         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7952                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7953                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7954
7955         tmp = I915_READ(SOUTH_CHICKEN2);
7956         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7957         I915_WRITE(SOUTH_CHICKEN2, tmp);
7958
7959         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7960                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7961                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7962 }
7963
7964 /* WaMPhyProgramming:hsw */
7965 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7966 {
7967         uint32_t tmp;
7968
7969         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7970         tmp &= ~(0xFF << 24);
7971         tmp |= (0x12 << 24);
7972         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7973
7974         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7975         tmp |= (1 << 11);
7976         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7977
7978         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7979         tmp |= (1 << 11);
7980         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7981
7982         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7983         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7984         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7985
7986         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7987         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7988         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7989
7990         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7991         tmp &= ~(7 << 13);
7992         tmp |= (5 << 13);
7993         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7994
7995         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7996         tmp &= ~(7 << 13);
7997         tmp |= (5 << 13);
7998         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7999
8000         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8001         tmp &= ~0xFF;
8002         tmp |= 0x1C;
8003         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8004
8005         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8006         tmp &= ~0xFF;
8007         tmp |= 0x1C;
8008         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8009
8010         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8011         tmp &= ~(0xFF << 16);
8012         tmp |= (0x1C << 16);
8013         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8014
8015         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8016         tmp &= ~(0xFF << 16);
8017         tmp |= (0x1C << 16);
8018         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8019
8020         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8021         tmp |= (1 << 27);
8022         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8023
8024         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8025         tmp |= (1 << 27);
8026         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8027
8028         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8029         tmp &= ~(0xF << 28);
8030         tmp |= (4 << 28);
8031         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8032
8033         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8034         tmp &= ~(0xF << 28);
8035         tmp |= (4 << 28);
8036         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8037 }
8038
8039 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8040  * Programming" based on the parameters passed:
8041  * - Sequence to enable CLKOUT_DP
8042  * - Sequence to enable CLKOUT_DP without spread
8043  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8044  */
8045 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8046                                  bool with_fdi)
8047 {
8048         struct drm_i915_private *dev_priv = dev->dev_private;
8049         uint32_t reg, tmp;
8050
8051         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8052                 with_spread = true;
8053         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8054                  with_fdi, "LP PCH doesn't have FDI\n"))
8055                 with_fdi = false;
8056
8057         mutex_lock(&dev_priv->dpio_lock);
8058
8059         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8060         tmp &= ~SBI_SSCCTL_DISABLE;
8061         tmp |= SBI_SSCCTL_PATHALT;
8062         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8063
8064         udelay(24);
8065
8066         if (with_spread) {
8067                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8068                 tmp &= ~SBI_SSCCTL_PATHALT;
8069                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8070
8071                 if (with_fdi) {
8072                         lpt_reset_fdi_mphy(dev_priv);
8073                         lpt_program_fdi_mphy(dev_priv);
8074                 }
8075         }
8076
8077         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8078                SBI_GEN0 : SBI_DBUFF0;
8079         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8080         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8081         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8082
8083         mutex_unlock(&dev_priv->dpio_lock);
8084 }
8085
8086 /* Sequence to disable CLKOUT_DP */
8087 static void lpt_disable_clkout_dp(struct drm_device *dev)
8088 {
8089         struct drm_i915_private *dev_priv = dev->dev_private;
8090         uint32_t reg, tmp;
8091
8092         mutex_lock(&dev_priv->dpio_lock);
8093
8094         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8095                SBI_GEN0 : SBI_DBUFF0;
8096         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8097         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8098         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8099
8100         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8101         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8102                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8103                         tmp |= SBI_SSCCTL_PATHALT;
8104                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8105                         udelay(32);
8106                 }
8107                 tmp |= SBI_SSCCTL_DISABLE;
8108                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8109         }
8110
8111         mutex_unlock(&dev_priv->dpio_lock);
8112 }
8113
8114 static void lpt_init_pch_refclk(struct drm_device *dev)
8115 {
8116         struct intel_encoder *encoder;
8117         bool has_vga = false;
8118
8119         for_each_intel_encoder(dev, encoder) {
8120                 switch (encoder->type) {
8121                 case INTEL_OUTPUT_ANALOG:
8122                         has_vga = true;
8123                         break;
8124                 default:
8125                         break;
8126                 }
8127         }
8128
8129         if (has_vga)
8130                 lpt_enable_clkout_dp(dev, true, true);
8131         else
8132                 lpt_disable_clkout_dp(dev);
8133 }
8134
8135 /*
8136  * Initialize reference clocks when the driver loads
8137  */
8138 void intel_init_pch_refclk(struct drm_device *dev)
8139 {
8140         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8141                 ironlake_init_pch_refclk(dev);
8142         else if (HAS_PCH_LPT(dev))
8143                 lpt_init_pch_refclk(dev);
8144 }
8145
8146 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8147 {
8148         struct drm_device *dev = crtc_state->base.crtc->dev;
8149         struct drm_i915_private *dev_priv = dev->dev_private;
8150         struct drm_atomic_state *state = crtc_state->base.state;
8151         struct drm_connector *connector;
8152         struct drm_connector_state *connector_state;
8153         struct intel_encoder *encoder;
8154         int num_connectors = 0, i;
8155         bool is_lvds = false;
8156
8157         for_each_connector_in_state(state, connector, connector_state, i) {
8158                 if (connector_state->crtc != crtc_state->base.crtc)
8159                         continue;
8160
8161                 encoder = to_intel_encoder(connector_state->best_encoder);
8162
8163                 switch (encoder->type) {
8164                 case INTEL_OUTPUT_LVDS:
8165                         is_lvds = true;
8166                         break;
8167                 default:
8168                         break;
8169                 }
8170                 num_connectors++;
8171         }
8172
8173         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8174                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8175                               dev_priv->vbt.lvds_ssc_freq);
8176                 return dev_priv->vbt.lvds_ssc_freq;
8177         }
8178
8179         return 120000;
8180 }
8181
8182 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8183 {
8184         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8186         int pipe = intel_crtc->pipe;
8187         uint32_t val;
8188
8189         val = 0;
8190
8191         switch (intel_crtc->config->pipe_bpp) {
8192         case 18:
8193                 val |= PIPECONF_6BPC;
8194                 break;
8195         case 24:
8196                 val |= PIPECONF_8BPC;
8197                 break;
8198         case 30:
8199                 val |= PIPECONF_10BPC;
8200                 break;
8201         case 36:
8202                 val |= PIPECONF_12BPC;
8203                 break;
8204         default:
8205                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8206                 BUG();
8207         }
8208
8209         if (intel_crtc->config->dither)
8210                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8211
8212         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8213                 val |= PIPECONF_INTERLACED_ILK;
8214         else
8215                 val |= PIPECONF_PROGRESSIVE;
8216
8217         if (intel_crtc->config->limited_color_range)
8218                 val |= PIPECONF_COLOR_RANGE_SELECT;
8219
8220         I915_WRITE(PIPECONF(pipe), val);
8221         POSTING_READ(PIPECONF(pipe));
8222 }
8223
8224 /*
8225  * Set up the pipe CSC unit.
8226  *
8227  * Currently only full range RGB to limited range RGB conversion
8228  * is supported, but eventually this should handle various
8229  * RGB<->YCbCr scenarios as well.
8230  */
8231 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8232 {
8233         struct drm_device *dev = crtc->dev;
8234         struct drm_i915_private *dev_priv = dev->dev_private;
8235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8236         int pipe = intel_crtc->pipe;
8237         uint16_t coeff = 0x7800; /* 1.0 */
8238
8239         /*
8240          * TODO: Check what kind of values actually come out of the pipe
8241          * with these coeff/postoff values and adjust to get the best
8242          * accuracy. Perhaps we even need to take the bpc value into
8243          * consideration.
8244          */
8245
8246         if (intel_crtc->config->limited_color_range)
8247                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8248
8249         /*
8250          * GY/GU and RY/RU should be the other way around according
8251          * to BSpec, but reality doesn't agree. Just set them up in
8252          * a way that results in the correct picture.
8253          */
8254         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8255         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8256
8257         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8258         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8259
8260         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8261         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8262
8263         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8264         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8265         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8266
8267         if (INTEL_INFO(dev)->gen > 6) {
8268                 uint16_t postoff = 0;
8269
8270                 if (intel_crtc->config->limited_color_range)
8271                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8272
8273                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8274                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8275                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8276
8277                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8278         } else {
8279                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8280
8281                 if (intel_crtc->config->limited_color_range)
8282                         mode |= CSC_BLACK_SCREEN_OFFSET;
8283
8284                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8285         }
8286 }
8287
8288 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8289 {
8290         struct drm_device *dev = crtc->dev;
8291         struct drm_i915_private *dev_priv = dev->dev_private;
8292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8293         enum pipe pipe = intel_crtc->pipe;
8294         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8295         uint32_t val;
8296
8297         val = 0;
8298
8299         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8300                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8301
8302         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8303                 val |= PIPECONF_INTERLACED_ILK;
8304         else
8305                 val |= PIPECONF_PROGRESSIVE;
8306
8307         I915_WRITE(PIPECONF(cpu_transcoder), val);
8308         POSTING_READ(PIPECONF(cpu_transcoder));
8309
8310         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8311         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8312
8313         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8314                 val = 0;
8315
8316                 switch (intel_crtc->config->pipe_bpp) {
8317                 case 18:
8318                         val |= PIPEMISC_DITHER_6_BPC;
8319                         break;
8320                 case 24:
8321                         val |= PIPEMISC_DITHER_8_BPC;
8322                         break;
8323                 case 30:
8324                         val |= PIPEMISC_DITHER_10_BPC;
8325                         break;
8326                 case 36:
8327                         val |= PIPEMISC_DITHER_12_BPC;
8328                         break;
8329                 default:
8330                         /* Case prevented by pipe_config_set_bpp. */
8331                         BUG();
8332                 }
8333
8334                 if (intel_crtc->config->dither)
8335                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8336
8337                 I915_WRITE(PIPEMISC(pipe), val);
8338         }
8339 }
8340
8341 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8342                                     struct intel_crtc_state *crtc_state,
8343                                     intel_clock_t *clock,
8344                                     bool *has_reduced_clock,
8345                                     intel_clock_t *reduced_clock)
8346 {
8347         struct drm_device *dev = crtc->dev;
8348         struct drm_i915_private *dev_priv = dev->dev_private;
8349         int refclk;
8350         const intel_limit_t *limit;
8351         bool ret, is_lvds = false;
8352
8353         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8354
8355         refclk = ironlake_get_refclk(crtc_state);
8356
8357         /*
8358          * Returns a set of divisors for the desired target clock with the given
8359          * refclk, or FALSE.  The returned values represent the clock equation:
8360          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8361          */
8362         limit = intel_limit(crtc_state, refclk);
8363         ret = dev_priv->display.find_dpll(limit, crtc_state,
8364                                           crtc_state->port_clock,
8365                                           refclk, NULL, clock);
8366         if (!ret)
8367                 return false;
8368
8369         if (is_lvds && dev_priv->lvds_downclock_avail) {
8370                 /*
8371                  * Ensure we match the reduced clock's P to the target clock.
8372                  * If the clocks don't match, we can't switch the display clock
8373                  * by using the FP0/FP1. In such case we will disable the LVDS
8374                  * downclock feature.
8375                 */
8376                 *has_reduced_clock =
8377                         dev_priv->display.find_dpll(limit, crtc_state,
8378                                                     dev_priv->lvds_downclock,
8379                                                     refclk, clock,
8380                                                     reduced_clock);
8381         }
8382
8383         return true;
8384 }
8385
8386 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8387 {
8388         /*
8389          * Account for spread spectrum to avoid
8390          * oversubscribing the link. Max center spread
8391          * is 2.5%; use 5% for safety's sake.
8392          */
8393         u32 bps = target_clock * bpp * 21 / 20;
8394         return DIV_ROUND_UP(bps, link_bw * 8);
8395 }
8396
8397 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8398 {
8399         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8400 }
8401
8402 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8403                                       struct intel_crtc_state *crtc_state,
8404                                       u32 *fp,
8405                                       intel_clock_t *reduced_clock, u32 *fp2)
8406 {
8407         struct drm_crtc *crtc = &intel_crtc->base;
8408         struct drm_device *dev = crtc->dev;
8409         struct drm_i915_private *dev_priv = dev->dev_private;
8410         struct drm_atomic_state *state = crtc_state->base.state;
8411         struct drm_connector *connector;
8412         struct drm_connector_state *connector_state;
8413         struct intel_encoder *encoder;
8414         uint32_t dpll;
8415         int factor, num_connectors = 0, i;
8416         bool is_lvds = false, is_sdvo = false;
8417
8418         for_each_connector_in_state(state, connector, connector_state, i) {
8419                 if (connector_state->crtc != crtc_state->base.crtc)
8420                         continue;
8421
8422                 encoder = to_intel_encoder(connector_state->best_encoder);
8423
8424                 switch (encoder->type) {
8425                 case INTEL_OUTPUT_LVDS:
8426                         is_lvds = true;
8427                         break;
8428                 case INTEL_OUTPUT_SDVO:
8429                 case INTEL_OUTPUT_HDMI:
8430                         is_sdvo = true;
8431                         break;
8432                 default:
8433                         break;
8434                 }
8435
8436                 num_connectors++;
8437         }
8438
8439         /* Enable autotuning of the PLL clock (if permissible) */
8440         factor = 21;
8441         if (is_lvds) {
8442                 if ((intel_panel_use_ssc(dev_priv) &&
8443                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8444                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8445                         factor = 25;
8446         } else if (crtc_state->sdvo_tv_clock)
8447                 factor = 20;
8448
8449         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8450                 *fp |= FP_CB_TUNE;
8451
8452         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8453                 *fp2 |= FP_CB_TUNE;
8454
8455         dpll = 0;
8456
8457         if (is_lvds)
8458                 dpll |= DPLLB_MODE_LVDS;
8459         else
8460                 dpll |= DPLLB_MODE_DAC_SERIAL;
8461
8462         dpll |= (crtc_state->pixel_multiplier - 1)
8463                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8464
8465         if (is_sdvo)
8466                 dpll |= DPLL_SDVO_HIGH_SPEED;
8467         if (crtc_state->has_dp_encoder)
8468                 dpll |= DPLL_SDVO_HIGH_SPEED;
8469
8470         /* compute bitmask from p1 value */
8471         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8472         /* also FPA1 */
8473         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8474
8475         switch (crtc_state->dpll.p2) {
8476         case 5:
8477                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8478                 break;
8479         case 7:
8480                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8481                 break;
8482         case 10:
8483                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8484                 break;
8485         case 14:
8486                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8487                 break;
8488         }
8489
8490         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8491                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8492         else
8493                 dpll |= PLL_REF_INPUT_DREFCLK;
8494
8495         return dpll | DPLL_VCO_ENABLE;
8496 }
8497
8498 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8499                                        struct intel_crtc_state *crtc_state)
8500 {
8501         struct drm_device *dev = crtc->base.dev;
8502         intel_clock_t clock, reduced_clock;
8503         u32 dpll = 0, fp = 0, fp2 = 0;
8504         bool ok, has_reduced_clock = false;
8505         bool is_lvds = false;
8506         struct intel_shared_dpll *pll;
8507
8508         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8509
8510         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8511              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8512
8513         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8514                                      &has_reduced_clock, &reduced_clock);
8515         if (!ok && !crtc_state->clock_set) {
8516                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8517                 return -EINVAL;
8518         }
8519         /* Compat-code for transition, will disappear. */
8520         if (!crtc_state->clock_set) {
8521                 crtc_state->dpll.n = clock.n;
8522                 crtc_state->dpll.m1 = clock.m1;
8523                 crtc_state->dpll.m2 = clock.m2;
8524                 crtc_state->dpll.p1 = clock.p1;
8525                 crtc_state->dpll.p2 = clock.p2;
8526         }
8527
8528         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8529         if (crtc_state->has_pch_encoder) {
8530                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8531                 if (has_reduced_clock)
8532                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8533
8534                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8535                                              &fp, &reduced_clock,
8536                                              has_reduced_clock ? &fp2 : NULL);
8537
8538                 crtc_state->dpll_hw_state.dpll = dpll;
8539                 crtc_state->dpll_hw_state.fp0 = fp;
8540                 if (has_reduced_clock)
8541                         crtc_state->dpll_hw_state.fp1 = fp2;
8542                 else
8543                         crtc_state->dpll_hw_state.fp1 = fp;
8544
8545                 pll = intel_get_shared_dpll(crtc, crtc_state);
8546                 if (pll == NULL) {
8547                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8548                                          pipe_name(crtc->pipe));
8549                         return -EINVAL;
8550                 }
8551         }
8552
8553         if (is_lvds && has_reduced_clock)
8554                 crtc->lowfreq_avail = true;
8555         else
8556                 crtc->lowfreq_avail = false;
8557
8558         return 0;
8559 }
8560
8561 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8562                                          struct intel_link_m_n *m_n)
8563 {
8564         struct drm_device *dev = crtc->base.dev;
8565         struct drm_i915_private *dev_priv = dev->dev_private;
8566         enum pipe pipe = crtc->pipe;
8567
8568         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8569         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8570         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8571                 & ~TU_SIZE_MASK;
8572         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8573         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8574                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8575 }
8576
8577 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8578                                          enum transcoder transcoder,
8579                                          struct intel_link_m_n *m_n,
8580                                          struct intel_link_m_n *m2_n2)
8581 {
8582         struct drm_device *dev = crtc->base.dev;
8583         struct drm_i915_private *dev_priv = dev->dev_private;
8584         enum pipe pipe = crtc->pipe;
8585
8586         if (INTEL_INFO(dev)->gen >= 5) {
8587                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8588                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8589                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8590                         & ~TU_SIZE_MASK;
8591                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8592                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8593                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8594                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8595                  * gen < 8) and if DRRS is supported (to make sure the
8596                  * registers are not unnecessarily read).
8597                  */
8598                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8599                         crtc->config->has_drrs) {
8600                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8601                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8602                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8603                                         & ~TU_SIZE_MASK;
8604                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8605                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8606                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8607                 }
8608         } else {
8609                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8610                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8611                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8612                         & ~TU_SIZE_MASK;
8613                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8614                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8615                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8616         }
8617 }
8618
8619 void intel_dp_get_m_n(struct intel_crtc *crtc,
8620                       struct intel_crtc_state *pipe_config)
8621 {
8622         if (pipe_config->has_pch_encoder)
8623                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8624         else
8625                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8626                                              &pipe_config->dp_m_n,
8627                                              &pipe_config->dp_m2_n2);
8628 }
8629
8630 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8631                                         struct intel_crtc_state *pipe_config)
8632 {
8633         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8634                                      &pipe_config->fdi_m_n, NULL);
8635 }
8636
8637 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8638                                     struct intel_crtc_state *pipe_config)
8639 {
8640         struct drm_device *dev = crtc->base.dev;
8641         struct drm_i915_private *dev_priv = dev->dev_private;
8642         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8643         uint32_t ps_ctrl = 0;
8644         int id = -1;
8645         int i;
8646
8647         /* find scaler attached to this pipe */
8648         for (i = 0; i < crtc->num_scalers; i++) {
8649                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8650                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8651                         id = i;
8652                         pipe_config->pch_pfit.enabled = true;
8653                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8654                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8655                         break;
8656                 }
8657         }
8658
8659         scaler_state->scaler_id = id;
8660         if (id >= 0) {
8661                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8662         } else {
8663                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8664         }
8665 }
8666
8667 static void
8668 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8669                                  struct intel_initial_plane_config *plane_config)
8670 {
8671         struct drm_device *dev = crtc->base.dev;
8672         struct drm_i915_private *dev_priv = dev->dev_private;
8673         u32 val, base, offset, stride_mult, tiling;
8674         int pipe = crtc->pipe;
8675         int fourcc, pixel_format;
8676         unsigned int aligned_height;
8677         struct drm_framebuffer *fb;
8678         struct intel_framebuffer *intel_fb;
8679
8680         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8681         if (!intel_fb) {
8682                 DRM_DEBUG_KMS("failed to alloc fb\n");
8683                 return;
8684         }
8685
8686         fb = &intel_fb->base;
8687
8688         val = I915_READ(PLANE_CTL(pipe, 0));
8689         if (!(val & PLANE_CTL_ENABLE))
8690                 goto error;
8691
8692         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8693         fourcc = skl_format_to_fourcc(pixel_format,
8694                                       val & PLANE_CTL_ORDER_RGBX,
8695                                       val & PLANE_CTL_ALPHA_MASK);
8696         fb->pixel_format = fourcc;
8697         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8698
8699         tiling = val & PLANE_CTL_TILED_MASK;
8700         switch (tiling) {
8701         case PLANE_CTL_TILED_LINEAR:
8702                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8703                 break;
8704         case PLANE_CTL_TILED_X:
8705                 plane_config->tiling = I915_TILING_X;
8706                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8707                 break;
8708         case PLANE_CTL_TILED_Y:
8709                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8710                 break;
8711         case PLANE_CTL_TILED_YF:
8712                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8713                 break;
8714         default:
8715                 MISSING_CASE(tiling);
8716                 goto error;
8717         }
8718
8719         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8720         plane_config->base = base;
8721
8722         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8723
8724         val = I915_READ(PLANE_SIZE(pipe, 0));
8725         fb->height = ((val >> 16) & 0xfff) + 1;
8726         fb->width = ((val >> 0) & 0x1fff) + 1;
8727
8728         val = I915_READ(PLANE_STRIDE(pipe, 0));
8729         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8730                                                 fb->pixel_format);
8731         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8732
8733         aligned_height = intel_fb_align_height(dev, fb->height,
8734                                                fb->pixel_format,
8735                                                fb->modifier[0]);
8736
8737         plane_config->size = fb->pitches[0] * aligned_height;
8738
8739         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8740                       pipe_name(pipe), fb->width, fb->height,
8741                       fb->bits_per_pixel, base, fb->pitches[0],
8742                       plane_config->size);
8743
8744         plane_config->fb = intel_fb;
8745         return;
8746
8747 error:
8748         kfree(fb);
8749 }
8750
8751 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8752                                      struct intel_crtc_state *pipe_config)
8753 {
8754         struct drm_device *dev = crtc->base.dev;
8755         struct drm_i915_private *dev_priv = dev->dev_private;
8756         uint32_t tmp;
8757
8758         tmp = I915_READ(PF_CTL(crtc->pipe));
8759
8760         if (tmp & PF_ENABLE) {
8761                 pipe_config->pch_pfit.enabled = true;
8762                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8763                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8764
8765                 /* We currently do not free assignements of panel fitters on
8766                  * ivb/hsw (since we don't use the higher upscaling modes which
8767                  * differentiates them) so just WARN about this case for now. */
8768                 if (IS_GEN7(dev)) {
8769                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8770                                 PF_PIPE_SEL_IVB(crtc->pipe));
8771                 }
8772         }
8773 }
8774
8775 static void
8776 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8777                                   struct intel_initial_plane_config *plane_config)
8778 {
8779         struct drm_device *dev = crtc->base.dev;
8780         struct drm_i915_private *dev_priv = dev->dev_private;
8781         u32 val, base, offset;
8782         int pipe = crtc->pipe;
8783         int fourcc, pixel_format;
8784         unsigned int aligned_height;
8785         struct drm_framebuffer *fb;
8786         struct intel_framebuffer *intel_fb;
8787
8788         val = I915_READ(DSPCNTR(pipe));
8789         if (!(val & DISPLAY_PLANE_ENABLE))
8790                 return;
8791
8792         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8793         if (!intel_fb) {
8794                 DRM_DEBUG_KMS("failed to alloc fb\n");
8795                 return;
8796         }
8797
8798         fb = &intel_fb->base;
8799
8800         if (INTEL_INFO(dev)->gen >= 4) {
8801                 if (val & DISPPLANE_TILED) {
8802                         plane_config->tiling = I915_TILING_X;
8803                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8804                 }
8805         }
8806
8807         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8808         fourcc = i9xx_format_to_fourcc(pixel_format);
8809         fb->pixel_format = fourcc;
8810         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8811
8812         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8813         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8814                 offset = I915_READ(DSPOFFSET(pipe));
8815         } else {
8816                 if (plane_config->tiling)
8817                         offset = I915_READ(DSPTILEOFF(pipe));
8818                 else
8819                         offset = I915_READ(DSPLINOFF(pipe));
8820         }
8821         plane_config->base = base;
8822
8823         val = I915_READ(PIPESRC(pipe));
8824         fb->width = ((val >> 16) & 0xfff) + 1;
8825         fb->height = ((val >> 0) & 0xfff) + 1;
8826
8827         val = I915_READ(DSPSTRIDE(pipe));
8828         fb->pitches[0] = val & 0xffffffc0;
8829
8830         aligned_height = intel_fb_align_height(dev, fb->height,
8831                                                fb->pixel_format,
8832                                                fb->modifier[0]);
8833
8834         plane_config->size = fb->pitches[0] * aligned_height;
8835
8836         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8837                       pipe_name(pipe), fb->width, fb->height,
8838                       fb->bits_per_pixel, base, fb->pitches[0],
8839                       plane_config->size);
8840
8841         plane_config->fb = intel_fb;
8842 }
8843
8844 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8845                                      struct intel_crtc_state *pipe_config)
8846 {
8847         struct drm_device *dev = crtc->base.dev;
8848         struct drm_i915_private *dev_priv = dev->dev_private;
8849         uint32_t tmp;
8850
8851         if (!intel_display_power_is_enabled(dev_priv,
8852                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8853                 return false;
8854
8855         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8856         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8857
8858         tmp = I915_READ(PIPECONF(crtc->pipe));
8859         if (!(tmp & PIPECONF_ENABLE))
8860                 return false;
8861
8862         switch (tmp & PIPECONF_BPC_MASK) {
8863         case PIPECONF_6BPC:
8864                 pipe_config->pipe_bpp = 18;
8865                 break;
8866         case PIPECONF_8BPC:
8867                 pipe_config->pipe_bpp = 24;
8868                 break;
8869         case PIPECONF_10BPC:
8870                 pipe_config->pipe_bpp = 30;
8871                 break;
8872         case PIPECONF_12BPC:
8873                 pipe_config->pipe_bpp = 36;
8874                 break;
8875         default:
8876                 break;
8877         }
8878
8879         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8880                 pipe_config->limited_color_range = true;
8881
8882         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8883                 struct intel_shared_dpll *pll;
8884
8885                 pipe_config->has_pch_encoder = true;
8886
8887                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8888                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8889                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8890
8891                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8892
8893                 if (HAS_PCH_IBX(dev_priv->dev)) {
8894                         pipe_config->shared_dpll =
8895                                 (enum intel_dpll_id) crtc->pipe;
8896                 } else {
8897                         tmp = I915_READ(PCH_DPLL_SEL);
8898                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8899                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8900                         else
8901                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8902                 }
8903
8904                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8905
8906                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8907                                            &pipe_config->dpll_hw_state));
8908
8909                 tmp = pipe_config->dpll_hw_state.dpll;
8910                 pipe_config->pixel_multiplier =
8911                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8912                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8913
8914                 ironlake_pch_clock_get(crtc, pipe_config);
8915         } else {
8916                 pipe_config->pixel_multiplier = 1;
8917         }
8918
8919         intel_get_pipe_timings(crtc, pipe_config);
8920
8921         ironlake_get_pfit_config(crtc, pipe_config);
8922
8923         return true;
8924 }
8925
8926 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8927 {
8928         struct drm_device *dev = dev_priv->dev;
8929         struct intel_crtc *crtc;
8930
8931         for_each_intel_crtc(dev, crtc)
8932                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8933                      pipe_name(crtc->pipe));
8934
8935         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8936         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8937         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8938         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8939         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8940         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8941              "CPU PWM1 enabled\n");
8942         if (IS_HASWELL(dev))
8943                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8944                      "CPU PWM2 enabled\n");
8945         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8946              "PCH PWM1 enabled\n");
8947         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8948              "Utility pin enabled\n");
8949         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8950
8951         /*
8952          * In theory we can still leave IRQs enabled, as long as only the HPD
8953          * interrupts remain enabled. We used to check for that, but since it's
8954          * gen-specific and since we only disable LCPLL after we fully disable
8955          * the interrupts, the check below should be enough.
8956          */
8957         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8958 }
8959
8960 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8961 {
8962         struct drm_device *dev = dev_priv->dev;
8963
8964         if (IS_HASWELL(dev))
8965                 return I915_READ(D_COMP_HSW);
8966         else
8967                 return I915_READ(D_COMP_BDW);
8968 }
8969
8970 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8971 {
8972         struct drm_device *dev = dev_priv->dev;
8973
8974         if (IS_HASWELL(dev)) {
8975                 mutex_lock(&dev_priv->rps.hw_lock);
8976                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8977                                             val))
8978                         DRM_ERROR("Failed to write to D_COMP\n");
8979                 mutex_unlock(&dev_priv->rps.hw_lock);
8980         } else {
8981                 I915_WRITE(D_COMP_BDW, val);
8982                 POSTING_READ(D_COMP_BDW);
8983         }
8984 }
8985
8986 /*
8987  * This function implements pieces of two sequences from BSpec:
8988  * - Sequence for display software to disable LCPLL
8989  * - Sequence for display software to allow package C8+
8990  * The steps implemented here are just the steps that actually touch the LCPLL
8991  * register. Callers should take care of disabling all the display engine
8992  * functions, doing the mode unset, fixing interrupts, etc.
8993  */
8994 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8995                               bool switch_to_fclk, bool allow_power_down)
8996 {
8997         uint32_t val;
8998
8999         assert_can_disable_lcpll(dev_priv);
9000
9001         val = I915_READ(LCPLL_CTL);
9002
9003         if (switch_to_fclk) {
9004                 val |= LCPLL_CD_SOURCE_FCLK;
9005                 I915_WRITE(LCPLL_CTL, val);
9006
9007                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9008                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9009                         DRM_ERROR("Switching to FCLK failed\n");
9010
9011                 val = I915_READ(LCPLL_CTL);
9012         }
9013
9014         val |= LCPLL_PLL_DISABLE;
9015         I915_WRITE(LCPLL_CTL, val);
9016         POSTING_READ(LCPLL_CTL);
9017
9018         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9019                 DRM_ERROR("LCPLL still locked\n");
9020
9021         val = hsw_read_dcomp(dev_priv);
9022         val |= D_COMP_COMP_DISABLE;
9023         hsw_write_dcomp(dev_priv, val);
9024         ndelay(100);
9025
9026         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9027                      1))
9028                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9029
9030         if (allow_power_down) {
9031                 val = I915_READ(LCPLL_CTL);
9032                 val |= LCPLL_POWER_DOWN_ALLOW;
9033                 I915_WRITE(LCPLL_CTL, val);
9034                 POSTING_READ(LCPLL_CTL);
9035         }
9036 }
9037
9038 /*
9039  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9040  * source.
9041  */
9042 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9043 {
9044         uint32_t val;
9045
9046         val = I915_READ(LCPLL_CTL);
9047
9048         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9049                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9050                 return;
9051
9052         /*
9053          * Make sure we're not on PC8 state before disabling PC8, otherwise
9054          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9055          */
9056         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9057
9058         if (val & LCPLL_POWER_DOWN_ALLOW) {
9059                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9060                 I915_WRITE(LCPLL_CTL, val);
9061                 POSTING_READ(LCPLL_CTL);
9062         }
9063
9064         val = hsw_read_dcomp(dev_priv);
9065         val |= D_COMP_COMP_FORCE;
9066         val &= ~D_COMP_COMP_DISABLE;
9067         hsw_write_dcomp(dev_priv, val);
9068
9069         val = I915_READ(LCPLL_CTL);
9070         val &= ~LCPLL_PLL_DISABLE;
9071         I915_WRITE(LCPLL_CTL, val);
9072
9073         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9074                 DRM_ERROR("LCPLL not locked yet\n");
9075
9076         if (val & LCPLL_CD_SOURCE_FCLK) {
9077                 val = I915_READ(LCPLL_CTL);
9078                 val &= ~LCPLL_CD_SOURCE_FCLK;
9079                 I915_WRITE(LCPLL_CTL, val);
9080
9081                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9082                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9083                         DRM_ERROR("Switching back to LCPLL failed\n");
9084         }
9085
9086         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9087 }
9088
9089 /*
9090  * Package states C8 and deeper are really deep PC states that can only be
9091  * reached when all the devices on the system allow it, so even if the graphics
9092  * device allows PC8+, it doesn't mean the system will actually get to these
9093  * states. Our driver only allows PC8+ when going into runtime PM.
9094  *
9095  * The requirements for PC8+ are that all the outputs are disabled, the power
9096  * well is disabled and most interrupts are disabled, and these are also
9097  * requirements for runtime PM. When these conditions are met, we manually do
9098  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9099  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9100  * hang the machine.
9101  *
9102  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9103  * the state of some registers, so when we come back from PC8+ we need to
9104  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9105  * need to take care of the registers kept by RC6. Notice that this happens even
9106  * if we don't put the device in PCI D3 state (which is what currently happens
9107  * because of the runtime PM support).
9108  *
9109  * For more, read "Display Sequences for Package C8" on the hardware
9110  * documentation.
9111  */
9112 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9113 {
9114         struct drm_device *dev = dev_priv->dev;
9115         uint32_t val;
9116
9117         DRM_DEBUG_KMS("Enabling package C8+\n");
9118
9119         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9120                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9121                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9122                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9123         }
9124
9125         lpt_disable_clkout_dp(dev);
9126         hsw_disable_lcpll(dev_priv, true, true);
9127 }
9128
9129 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9130 {
9131         struct drm_device *dev = dev_priv->dev;
9132         uint32_t val;
9133
9134         DRM_DEBUG_KMS("Disabling package C8+\n");
9135
9136         hsw_restore_lcpll(dev_priv);
9137         lpt_init_pch_refclk(dev);
9138
9139         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9140                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9141                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9142                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9143         }
9144
9145         intel_prepare_ddi(dev);
9146 }
9147
9148 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9149 {
9150         struct drm_device *dev = old_state->dev;
9151         struct drm_i915_private *dev_priv = dev->dev_private;
9152         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9153         int req_cdclk;
9154
9155         /* see the comment in valleyview_modeset_global_resources */
9156         if (WARN_ON(max_pixclk < 0))
9157                 return;
9158
9159         req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9160
9161         if (req_cdclk != dev_priv->cdclk_freq)
9162                 broxton_set_cdclk(dev, req_cdclk);
9163 }
9164
9165 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9166                                       struct intel_crtc_state *crtc_state)
9167 {
9168         if (!intel_ddi_pll_select(crtc, crtc_state))
9169                 return -EINVAL;
9170
9171         crtc->lowfreq_avail = false;
9172
9173         return 0;
9174 }
9175
9176 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9177                                 enum port port,
9178                                 struct intel_crtc_state *pipe_config)
9179 {
9180         switch (port) {
9181         case PORT_A:
9182                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9183                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9184                 break;
9185         case PORT_B:
9186                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9187                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9188                 break;
9189         case PORT_C:
9190                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9191                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9192                 break;
9193         default:
9194                 DRM_ERROR("Incorrect port type\n");
9195         }
9196 }
9197
9198 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9199                                 enum port port,
9200                                 struct intel_crtc_state *pipe_config)
9201 {
9202         u32 temp, dpll_ctl1;
9203
9204         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9205         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9206
9207         switch (pipe_config->ddi_pll_sel) {
9208         case SKL_DPLL0:
9209                 /*
9210                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9211                  * of the shared DPLL framework and thus needs to be read out
9212                  * separately
9213                  */
9214                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9215                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9216                 break;
9217         case SKL_DPLL1:
9218                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9219                 break;
9220         case SKL_DPLL2:
9221                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9222                 break;
9223         case SKL_DPLL3:
9224                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9225                 break;
9226         }
9227 }
9228
9229 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9230                                 enum port port,
9231                                 struct intel_crtc_state *pipe_config)
9232 {
9233         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9234
9235         switch (pipe_config->ddi_pll_sel) {
9236         case PORT_CLK_SEL_WRPLL1:
9237                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9238                 break;
9239         case PORT_CLK_SEL_WRPLL2:
9240                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9241                 break;
9242         }
9243 }
9244
9245 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9246                                        struct intel_crtc_state *pipe_config)
9247 {
9248         struct drm_device *dev = crtc->base.dev;
9249         struct drm_i915_private *dev_priv = dev->dev_private;
9250         struct intel_shared_dpll *pll;
9251         enum port port;
9252         uint32_t tmp;
9253
9254         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9255
9256         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9257
9258         if (IS_SKYLAKE(dev))
9259                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9260         else if (IS_BROXTON(dev))
9261                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9262         else
9263                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9264
9265         if (pipe_config->shared_dpll >= 0) {
9266                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9267
9268                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9269                                            &pipe_config->dpll_hw_state));
9270         }
9271
9272         /*
9273          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9274          * DDI E. So just check whether this pipe is wired to DDI E and whether
9275          * the PCH transcoder is on.
9276          */
9277         if (INTEL_INFO(dev)->gen < 9 &&
9278             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9279                 pipe_config->has_pch_encoder = true;
9280
9281                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9282                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9283                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9284
9285                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9286         }
9287 }
9288
9289 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9290                                     struct intel_crtc_state *pipe_config)
9291 {
9292         struct drm_device *dev = crtc->base.dev;
9293         struct drm_i915_private *dev_priv = dev->dev_private;
9294         enum intel_display_power_domain pfit_domain;
9295         uint32_t tmp;
9296
9297         if (!intel_display_power_is_enabled(dev_priv,
9298                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9299                 return false;
9300
9301         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9302         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9303
9304         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9305         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9306                 enum pipe trans_edp_pipe;
9307                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9308                 default:
9309                         WARN(1, "unknown pipe linked to edp transcoder\n");
9310                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9311                 case TRANS_DDI_EDP_INPUT_A_ON:
9312                         trans_edp_pipe = PIPE_A;
9313                         break;
9314                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9315                         trans_edp_pipe = PIPE_B;
9316                         break;
9317                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9318                         trans_edp_pipe = PIPE_C;
9319                         break;
9320                 }
9321
9322                 if (trans_edp_pipe == crtc->pipe)
9323                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9324         }
9325
9326         if (!intel_display_power_is_enabled(dev_priv,
9327                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9328                 return false;
9329
9330         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9331         if (!(tmp & PIPECONF_ENABLE))
9332                 return false;
9333
9334         haswell_get_ddi_port_state(crtc, pipe_config);
9335
9336         intel_get_pipe_timings(crtc, pipe_config);
9337
9338         if (INTEL_INFO(dev)->gen >= 9) {
9339                 skl_init_scalers(dev, crtc, pipe_config);
9340         }
9341
9342         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9343
9344         if (INTEL_INFO(dev)->gen >= 9) {
9345                 pipe_config->scaler_state.scaler_id = -1;
9346                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9347         }
9348
9349         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9350                 if (INTEL_INFO(dev)->gen == 9)
9351                         skylake_get_pfit_config(crtc, pipe_config);
9352                 else if (INTEL_INFO(dev)->gen < 9)
9353                         ironlake_get_pfit_config(crtc, pipe_config);
9354                 else
9355                         MISSING_CASE(INTEL_INFO(dev)->gen);
9356         }
9357
9358         if (IS_HASWELL(dev))
9359                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9360                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9361
9362         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9363                 pipe_config->pixel_multiplier =
9364                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9365         } else {
9366                 pipe_config->pixel_multiplier = 1;
9367         }
9368
9369         return true;
9370 }
9371
9372 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9373 {
9374         struct drm_device *dev = crtc->dev;
9375         struct drm_i915_private *dev_priv = dev->dev_private;
9376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9377         uint32_t cntl = 0, size = 0;
9378
9379         if (base) {
9380                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9381                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9382                 unsigned int stride = roundup_pow_of_two(width) * 4;
9383
9384                 switch (stride) {
9385                 default:
9386                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9387                                   width, stride);
9388                         stride = 256;
9389                         /* fallthrough */
9390                 case 256:
9391                 case 512:
9392                 case 1024:
9393                 case 2048:
9394                         break;
9395                 }
9396
9397                 cntl |= CURSOR_ENABLE |
9398                         CURSOR_GAMMA_ENABLE |
9399                         CURSOR_FORMAT_ARGB |
9400                         CURSOR_STRIDE(stride);
9401
9402                 size = (height << 12) | width;
9403         }
9404
9405         if (intel_crtc->cursor_cntl != 0 &&
9406             (intel_crtc->cursor_base != base ||
9407              intel_crtc->cursor_size != size ||
9408              intel_crtc->cursor_cntl != cntl)) {
9409                 /* On these chipsets we can only modify the base/size/stride
9410                  * whilst the cursor is disabled.
9411                  */
9412                 I915_WRITE(_CURACNTR, 0);
9413                 POSTING_READ(_CURACNTR);
9414                 intel_crtc->cursor_cntl = 0;
9415         }
9416
9417         if (intel_crtc->cursor_base != base) {
9418                 I915_WRITE(_CURABASE, base);
9419                 intel_crtc->cursor_base = base;
9420         }
9421
9422         if (intel_crtc->cursor_size != size) {
9423                 I915_WRITE(CURSIZE, size);
9424                 intel_crtc->cursor_size = size;
9425         }
9426
9427         if (intel_crtc->cursor_cntl != cntl) {
9428                 I915_WRITE(_CURACNTR, cntl);
9429                 POSTING_READ(_CURACNTR);
9430                 intel_crtc->cursor_cntl = cntl;
9431         }
9432 }
9433
9434 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9435 {
9436         struct drm_device *dev = crtc->dev;
9437         struct drm_i915_private *dev_priv = dev->dev_private;
9438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9439         int pipe = intel_crtc->pipe;
9440         uint32_t cntl;
9441
9442         cntl = 0;
9443         if (base) {
9444                 cntl = MCURSOR_GAMMA_ENABLE;
9445                 switch (intel_crtc->base.cursor->state->crtc_w) {
9446                         case 64:
9447                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9448                                 break;
9449                         case 128:
9450                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9451                                 break;
9452                         case 256:
9453                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9454                                 break;
9455                         default:
9456                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9457                                 return;
9458                 }
9459                 cntl |= pipe << 28; /* Connect to correct pipe */
9460
9461                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9462                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9463         }
9464
9465         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9466                 cntl |= CURSOR_ROTATE_180;
9467
9468         if (intel_crtc->cursor_cntl != cntl) {
9469                 I915_WRITE(CURCNTR(pipe), cntl);
9470                 POSTING_READ(CURCNTR(pipe));
9471                 intel_crtc->cursor_cntl = cntl;
9472         }
9473
9474         /* and commit changes on next vblank */
9475         I915_WRITE(CURBASE(pipe), base);
9476         POSTING_READ(CURBASE(pipe));
9477
9478         intel_crtc->cursor_base = base;
9479 }
9480
9481 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9482 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9483                                      bool on)
9484 {
9485         struct drm_device *dev = crtc->dev;
9486         struct drm_i915_private *dev_priv = dev->dev_private;
9487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9488         int pipe = intel_crtc->pipe;
9489         int x = crtc->cursor_x;
9490         int y = crtc->cursor_y;
9491         u32 base = 0, pos = 0;
9492
9493         if (on)
9494                 base = intel_crtc->cursor_addr;
9495
9496         if (x >= intel_crtc->config->pipe_src_w)
9497                 base = 0;
9498
9499         if (y >= intel_crtc->config->pipe_src_h)
9500                 base = 0;
9501
9502         if (x < 0) {
9503                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9504                         base = 0;
9505
9506                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9507                 x = -x;
9508         }
9509         pos |= x << CURSOR_X_SHIFT;
9510
9511         if (y < 0) {
9512                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9513                         base = 0;
9514
9515                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9516                 y = -y;
9517         }
9518         pos |= y << CURSOR_Y_SHIFT;
9519
9520         if (base == 0 && intel_crtc->cursor_base == 0)
9521                 return;
9522
9523         I915_WRITE(CURPOS(pipe), pos);
9524
9525         /* ILK+ do this automagically */
9526         if (HAS_GMCH_DISPLAY(dev) &&
9527             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9528                 base += (intel_crtc->base.cursor->state->crtc_h *
9529                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9530         }
9531
9532         if (IS_845G(dev) || IS_I865G(dev))
9533                 i845_update_cursor(crtc, base);
9534         else
9535                 i9xx_update_cursor(crtc, base);
9536 }
9537
9538 static bool cursor_size_ok(struct drm_device *dev,
9539                            uint32_t width, uint32_t height)
9540 {
9541         if (width == 0 || height == 0)
9542                 return false;
9543
9544         /*
9545          * 845g/865g are special in that they are only limited by
9546          * the width of their cursors, the height is arbitrary up to
9547          * the precision of the register. Everything else requires
9548          * square cursors, limited to a few power-of-two sizes.
9549          */
9550         if (IS_845G(dev) || IS_I865G(dev)) {
9551                 if ((width & 63) != 0)
9552                         return false;
9553
9554                 if (width > (IS_845G(dev) ? 64 : 512))
9555                         return false;
9556
9557                 if (height > 1023)
9558                         return false;
9559         } else {
9560                 switch (width | height) {
9561                 case 256:
9562                 case 128:
9563                         if (IS_GEN2(dev))
9564                                 return false;
9565                 case 64:
9566                         break;
9567                 default:
9568                         return false;
9569                 }
9570         }
9571
9572         return true;
9573 }
9574
9575 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9576                                  u16 *blue, uint32_t start, uint32_t size)
9577 {
9578         int end = (start + size > 256) ? 256 : start + size, i;
9579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9580
9581         for (i = start; i < end; i++) {
9582                 intel_crtc->lut_r[i] = red[i] >> 8;
9583                 intel_crtc->lut_g[i] = green[i] >> 8;
9584                 intel_crtc->lut_b[i] = blue[i] >> 8;
9585         }
9586
9587         intel_crtc_load_lut(crtc);
9588 }
9589
9590 /* VESA 640x480x72Hz mode to set on the pipe */
9591 static struct drm_display_mode load_detect_mode = {
9592         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9593                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9594 };
9595
9596 struct drm_framebuffer *
9597 __intel_framebuffer_create(struct drm_device *dev,
9598                            struct drm_mode_fb_cmd2 *mode_cmd,
9599                            struct drm_i915_gem_object *obj)
9600 {
9601         struct intel_framebuffer *intel_fb;
9602         int ret;
9603
9604         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9605         if (!intel_fb) {
9606                 drm_gem_object_unreference(&obj->base);
9607                 return ERR_PTR(-ENOMEM);
9608         }
9609
9610         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9611         if (ret)
9612                 goto err;
9613
9614         return &intel_fb->base;
9615 err:
9616         drm_gem_object_unreference(&obj->base);
9617         kfree(intel_fb);
9618
9619         return ERR_PTR(ret);
9620 }
9621
9622 static struct drm_framebuffer *
9623 intel_framebuffer_create(struct drm_device *dev,
9624                          struct drm_mode_fb_cmd2 *mode_cmd,
9625                          struct drm_i915_gem_object *obj)
9626 {
9627         struct drm_framebuffer *fb;
9628         int ret;
9629
9630         ret = i915_mutex_lock_interruptible(dev);
9631         if (ret)
9632                 return ERR_PTR(ret);
9633         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9634         mutex_unlock(&dev->struct_mutex);
9635
9636         return fb;
9637 }
9638
9639 static u32
9640 intel_framebuffer_pitch_for_width(int width, int bpp)
9641 {
9642         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9643         return ALIGN(pitch, 64);
9644 }
9645
9646 static u32
9647 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9648 {
9649         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9650         return PAGE_ALIGN(pitch * mode->vdisplay);
9651 }
9652
9653 static struct drm_framebuffer *
9654 intel_framebuffer_create_for_mode(struct drm_device *dev,
9655                                   struct drm_display_mode *mode,
9656                                   int depth, int bpp)
9657 {
9658         struct drm_i915_gem_object *obj;
9659         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9660
9661         obj = i915_gem_alloc_object(dev,
9662                                     intel_framebuffer_size_for_mode(mode, bpp));
9663         if (obj == NULL)
9664                 return ERR_PTR(-ENOMEM);
9665
9666         mode_cmd.width = mode->hdisplay;
9667         mode_cmd.height = mode->vdisplay;
9668         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9669                                                                 bpp);
9670         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9671
9672         return intel_framebuffer_create(dev, &mode_cmd, obj);
9673 }
9674
9675 static struct drm_framebuffer *
9676 mode_fits_in_fbdev(struct drm_device *dev,
9677                    struct drm_display_mode *mode)
9678 {
9679 #ifdef CONFIG_DRM_I915_FBDEV
9680         struct drm_i915_private *dev_priv = dev->dev_private;
9681         struct drm_i915_gem_object *obj;
9682         struct drm_framebuffer *fb;
9683
9684         if (!dev_priv->fbdev)
9685                 return NULL;
9686
9687         if (!dev_priv->fbdev->fb)
9688                 return NULL;
9689
9690         obj = dev_priv->fbdev->fb->obj;
9691         BUG_ON(!obj);
9692
9693         fb = &dev_priv->fbdev->fb->base;
9694         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9695                                                                fb->bits_per_pixel))
9696                 return NULL;
9697
9698         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9699                 return NULL;
9700
9701         return fb;
9702 #else
9703         return NULL;
9704 #endif
9705 }
9706
9707 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9708                                            struct drm_crtc *crtc,
9709                                            struct drm_display_mode *mode,
9710                                            struct drm_framebuffer *fb,
9711                                            int x, int y)
9712 {
9713         struct drm_plane_state *plane_state;
9714         int hdisplay, vdisplay;
9715         int ret;
9716
9717         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9718         if (IS_ERR(plane_state))
9719                 return PTR_ERR(plane_state);
9720
9721         if (mode)
9722                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9723         else
9724                 hdisplay = vdisplay = 0;
9725
9726         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9727         if (ret)
9728                 return ret;
9729         drm_atomic_set_fb_for_plane(plane_state, fb);
9730         plane_state->crtc_x = 0;
9731         plane_state->crtc_y = 0;
9732         plane_state->crtc_w = hdisplay;
9733         plane_state->crtc_h = vdisplay;
9734         plane_state->src_x = x << 16;
9735         plane_state->src_y = y << 16;
9736         plane_state->src_w = hdisplay << 16;
9737         plane_state->src_h = vdisplay << 16;
9738
9739         return 0;
9740 }
9741
9742 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9743                                 struct drm_display_mode *mode,
9744                                 struct intel_load_detect_pipe *old,
9745                                 struct drm_modeset_acquire_ctx *ctx)
9746 {
9747         struct intel_crtc *intel_crtc;
9748         struct intel_encoder *intel_encoder =
9749                 intel_attached_encoder(connector);
9750         struct drm_crtc *possible_crtc;
9751         struct drm_encoder *encoder = &intel_encoder->base;
9752         struct drm_crtc *crtc = NULL;
9753         struct drm_device *dev = encoder->dev;
9754         struct drm_framebuffer *fb;
9755         struct drm_mode_config *config = &dev->mode_config;
9756         struct drm_atomic_state *state = NULL;
9757         struct drm_connector_state *connector_state;
9758         struct intel_crtc_state *crtc_state;
9759         int ret, i = -1;
9760
9761         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9762                       connector->base.id, connector->name,
9763                       encoder->base.id, encoder->name);
9764
9765 retry:
9766         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9767         if (ret)
9768                 goto fail_unlock;
9769
9770         /*
9771          * Algorithm gets a little messy:
9772          *
9773          *   - if the connector already has an assigned crtc, use it (but make
9774          *     sure it's on first)
9775          *
9776          *   - try to find the first unused crtc that can drive this connector,
9777          *     and use that if we find one
9778          */
9779
9780         /* See if we already have a CRTC for this connector */
9781         if (encoder->crtc) {
9782                 crtc = encoder->crtc;
9783
9784                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9785                 if (ret)
9786                         goto fail_unlock;
9787                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9788                 if (ret)
9789                         goto fail_unlock;
9790
9791                 old->dpms_mode = connector->dpms;
9792                 old->load_detect_temp = false;
9793
9794                 /* Make sure the crtc and connector are running */
9795                 if (connector->dpms != DRM_MODE_DPMS_ON)
9796                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9797
9798                 return true;
9799         }
9800
9801         /* Find an unused one (if possible) */
9802         for_each_crtc(dev, possible_crtc) {
9803                 i++;
9804                 if (!(encoder->possible_crtcs & (1 << i)))
9805                         continue;
9806                 if (possible_crtc->state->enable)
9807                         continue;
9808                 /* This can occur when applying the pipe A quirk on resume. */
9809                 if (to_intel_crtc(possible_crtc)->new_enabled)
9810                         continue;
9811
9812                 crtc = possible_crtc;
9813                 break;
9814         }
9815
9816         /*
9817          * If we didn't find an unused CRTC, don't use any.
9818          */
9819         if (!crtc) {
9820                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9821                 goto fail_unlock;
9822         }
9823
9824         ret = drm_modeset_lock(&crtc->mutex, ctx);
9825         if (ret)
9826                 goto fail_unlock;
9827         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9828         if (ret)
9829                 goto fail_unlock;
9830         intel_encoder->new_crtc = to_intel_crtc(crtc);
9831         to_intel_connector(connector)->new_encoder = intel_encoder;
9832
9833         intel_crtc = to_intel_crtc(crtc);
9834         intel_crtc->new_enabled = true;
9835         old->dpms_mode = connector->dpms;
9836         old->load_detect_temp = true;
9837         old->release_fb = NULL;
9838
9839         state = drm_atomic_state_alloc(dev);
9840         if (!state)
9841                 return false;
9842
9843         state->acquire_ctx = ctx;
9844
9845         connector_state = drm_atomic_get_connector_state(state, connector);
9846         if (IS_ERR(connector_state)) {
9847                 ret = PTR_ERR(connector_state);
9848                 goto fail;
9849         }
9850
9851         connector_state->crtc = crtc;
9852         connector_state->best_encoder = &intel_encoder->base;
9853
9854         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9855         if (IS_ERR(crtc_state)) {
9856                 ret = PTR_ERR(crtc_state);
9857                 goto fail;
9858         }
9859
9860         crtc_state->base.active = crtc_state->base.enable = true;
9861
9862         if (!mode)
9863                 mode = &load_detect_mode;
9864
9865         /* We need a framebuffer large enough to accommodate all accesses
9866          * that the plane may generate whilst we perform load detection.
9867          * We can not rely on the fbcon either being present (we get called
9868          * during its initialisation to detect all boot displays, or it may
9869          * not even exist) or that it is large enough to satisfy the
9870          * requested mode.
9871          */
9872         fb = mode_fits_in_fbdev(dev, mode);
9873         if (fb == NULL) {
9874                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9875                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9876                 old->release_fb = fb;
9877         } else
9878                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9879         if (IS_ERR(fb)) {
9880                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9881                 goto fail;
9882         }
9883
9884         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9885         if (ret)
9886                 goto fail;
9887
9888         drm_mode_copy(&crtc_state->base.mode, mode);
9889
9890         if (intel_set_mode(crtc, state)) {
9891                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9892                 if (old->release_fb)
9893                         old->release_fb->funcs->destroy(old->release_fb);
9894                 goto fail;
9895         }
9896         crtc->primary->crtc = crtc;
9897
9898         /* let the connector get through one full cycle before testing */
9899         intel_wait_for_vblank(dev, intel_crtc->pipe);
9900         return true;
9901
9902  fail:
9903         intel_crtc->new_enabled = crtc->state->enable;
9904 fail_unlock:
9905         drm_atomic_state_free(state);
9906         state = NULL;
9907
9908         if (ret == -EDEADLK) {
9909                 drm_modeset_backoff(ctx);
9910                 goto retry;
9911         }
9912
9913         return false;
9914 }
9915
9916 void intel_release_load_detect_pipe(struct drm_connector *connector,
9917                                     struct intel_load_detect_pipe *old,
9918                                     struct drm_modeset_acquire_ctx *ctx)
9919 {
9920         struct drm_device *dev = connector->dev;
9921         struct intel_encoder *intel_encoder =
9922                 intel_attached_encoder(connector);
9923         struct drm_encoder *encoder = &intel_encoder->base;
9924         struct drm_crtc *crtc = encoder->crtc;
9925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9926         struct drm_atomic_state *state;
9927         struct drm_connector_state *connector_state;
9928         struct intel_crtc_state *crtc_state;
9929         int ret;
9930
9931         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9932                       connector->base.id, connector->name,
9933                       encoder->base.id, encoder->name);
9934
9935         if (old->load_detect_temp) {
9936                 state = drm_atomic_state_alloc(dev);
9937                 if (!state)
9938                         goto fail;
9939
9940                 state->acquire_ctx = ctx;
9941
9942                 connector_state = drm_atomic_get_connector_state(state, connector);
9943                 if (IS_ERR(connector_state))
9944                         goto fail;
9945
9946                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9947                 if (IS_ERR(crtc_state))
9948                         goto fail;
9949
9950                 to_intel_connector(connector)->new_encoder = NULL;
9951                 intel_encoder->new_crtc = NULL;
9952                 intel_crtc->new_enabled = false;
9953
9954                 connector_state->best_encoder = NULL;
9955                 connector_state->crtc = NULL;
9956
9957                 crtc_state->base.enable = crtc_state->base.active = false;
9958
9959                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9960                                                       0, 0);
9961                 if (ret)
9962                         goto fail;
9963
9964                 ret = intel_set_mode(crtc, state);
9965                 if (ret)
9966                         goto fail;
9967
9968                 if (old->release_fb) {
9969                         drm_framebuffer_unregister_private(old->release_fb);
9970                         drm_framebuffer_unreference(old->release_fb);
9971                 }
9972
9973                 return;
9974         }
9975
9976         /* Switch crtc and encoder back off if necessary */
9977         if (old->dpms_mode != DRM_MODE_DPMS_ON)
9978                 connector->funcs->dpms(connector, old->dpms_mode);
9979
9980         return;
9981 fail:
9982         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9983         drm_atomic_state_free(state);
9984 }
9985
9986 static int i9xx_pll_refclk(struct drm_device *dev,
9987                            const struct intel_crtc_state *pipe_config)
9988 {
9989         struct drm_i915_private *dev_priv = dev->dev_private;
9990         u32 dpll = pipe_config->dpll_hw_state.dpll;
9991
9992         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9993                 return dev_priv->vbt.lvds_ssc_freq;
9994         else if (HAS_PCH_SPLIT(dev))
9995                 return 120000;
9996         else if (!IS_GEN2(dev))
9997                 return 96000;
9998         else
9999                 return 48000;
10000 }
10001
10002 /* Returns the clock of the currently programmed mode of the given pipe. */
10003 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10004                                 struct intel_crtc_state *pipe_config)
10005 {
10006         struct drm_device *dev = crtc->base.dev;
10007         struct drm_i915_private *dev_priv = dev->dev_private;
10008         int pipe = pipe_config->cpu_transcoder;
10009         u32 dpll = pipe_config->dpll_hw_state.dpll;
10010         u32 fp;
10011         intel_clock_t clock;
10012         int refclk = i9xx_pll_refclk(dev, pipe_config);
10013
10014         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10015                 fp = pipe_config->dpll_hw_state.fp0;
10016         else
10017                 fp = pipe_config->dpll_hw_state.fp1;
10018
10019         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10020         if (IS_PINEVIEW(dev)) {
10021                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10022                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10023         } else {
10024                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10025                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10026         }
10027
10028         if (!IS_GEN2(dev)) {
10029                 if (IS_PINEVIEW(dev))
10030                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10031                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10032                 else
10033                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10034                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10035
10036                 switch (dpll & DPLL_MODE_MASK) {
10037                 case DPLLB_MODE_DAC_SERIAL:
10038                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10039                                 5 : 10;
10040                         break;
10041                 case DPLLB_MODE_LVDS:
10042                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10043                                 7 : 14;
10044                         break;
10045                 default:
10046                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10047                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10048                         return;
10049                 }
10050
10051                 if (IS_PINEVIEW(dev))
10052                         pineview_clock(refclk, &clock);
10053                 else
10054                         i9xx_clock(refclk, &clock);
10055         } else {
10056                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10057                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10058
10059                 if (is_lvds) {
10060                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10061                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10062
10063                         if (lvds & LVDS_CLKB_POWER_UP)
10064                                 clock.p2 = 7;
10065                         else
10066                                 clock.p2 = 14;
10067                 } else {
10068                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10069                                 clock.p1 = 2;
10070                         else {
10071                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10072                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10073                         }
10074                         if (dpll & PLL_P2_DIVIDE_BY_4)
10075                                 clock.p2 = 4;
10076                         else
10077                                 clock.p2 = 2;
10078                 }
10079
10080                 i9xx_clock(refclk, &clock);
10081         }
10082
10083         /*
10084          * This value includes pixel_multiplier. We will use
10085          * port_clock to compute adjusted_mode.crtc_clock in the
10086          * encoder's get_config() function.
10087          */
10088         pipe_config->port_clock = clock.dot;
10089 }
10090
10091 int intel_dotclock_calculate(int link_freq,
10092                              const struct intel_link_m_n *m_n)
10093 {
10094         /*
10095          * The calculation for the data clock is:
10096          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10097          * But we want to avoid losing precison if possible, so:
10098          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10099          *
10100          * and the link clock is simpler:
10101          * link_clock = (m * link_clock) / n
10102          */
10103
10104         if (!m_n->link_n)
10105                 return 0;
10106
10107         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10108 }
10109
10110 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10111                                    struct intel_crtc_state *pipe_config)
10112 {
10113         struct drm_device *dev = crtc->base.dev;
10114
10115         /* read out port_clock from the DPLL */
10116         i9xx_crtc_clock_get(crtc, pipe_config);
10117
10118         /*
10119          * This value does not include pixel_multiplier.
10120          * We will check that port_clock and adjusted_mode.crtc_clock
10121          * agree once we know their relationship in the encoder's
10122          * get_config() function.
10123          */
10124         pipe_config->base.adjusted_mode.crtc_clock =
10125                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10126                                          &pipe_config->fdi_m_n);
10127 }
10128
10129 /** Returns the currently programmed mode of the given pipe. */
10130 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10131                                              struct drm_crtc *crtc)
10132 {
10133         struct drm_i915_private *dev_priv = dev->dev_private;
10134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10135         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10136         struct drm_display_mode *mode;
10137         struct intel_crtc_state pipe_config;
10138         int htot = I915_READ(HTOTAL(cpu_transcoder));
10139         int hsync = I915_READ(HSYNC(cpu_transcoder));
10140         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10141         int vsync = I915_READ(VSYNC(cpu_transcoder));
10142         enum pipe pipe = intel_crtc->pipe;
10143
10144         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10145         if (!mode)
10146                 return NULL;
10147
10148         /*
10149          * Construct a pipe_config sufficient for getting the clock info
10150          * back out of crtc_clock_get.
10151          *
10152          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10153          * to use a real value here instead.
10154          */
10155         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10156         pipe_config.pixel_multiplier = 1;
10157         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10158         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10159         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10160         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10161
10162         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10163         mode->hdisplay = (htot & 0xffff) + 1;
10164         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10165         mode->hsync_start = (hsync & 0xffff) + 1;
10166         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10167         mode->vdisplay = (vtot & 0xffff) + 1;
10168         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10169         mode->vsync_start = (vsync & 0xffff) + 1;
10170         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10171
10172         drm_mode_set_name(mode);
10173
10174         return mode;
10175 }
10176
10177 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10178 {
10179         struct drm_device *dev = crtc->dev;
10180         struct drm_i915_private *dev_priv = dev->dev_private;
10181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10182
10183         if (!HAS_GMCH_DISPLAY(dev))
10184                 return;
10185
10186         if (!dev_priv->lvds_downclock_avail)
10187                 return;
10188
10189         /*
10190          * Since this is called by a timer, we should never get here in
10191          * the manual case.
10192          */
10193         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10194                 int pipe = intel_crtc->pipe;
10195                 int dpll_reg = DPLL(pipe);
10196                 int dpll;
10197
10198                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10199
10200                 assert_panel_unlocked(dev_priv, pipe);
10201
10202                 dpll = I915_READ(dpll_reg);
10203                 dpll |= DISPLAY_RATE_SELECT_FPA1;
10204                 I915_WRITE(dpll_reg, dpll);
10205                 intel_wait_for_vblank(dev, pipe);
10206                 dpll = I915_READ(dpll_reg);
10207                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10208                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10209         }
10210
10211 }
10212
10213 void intel_mark_busy(struct drm_device *dev)
10214 {
10215         struct drm_i915_private *dev_priv = dev->dev_private;
10216
10217         if (dev_priv->mm.busy)
10218                 return;
10219
10220         intel_runtime_pm_get(dev_priv);
10221         i915_update_gfx_val(dev_priv);
10222         if (INTEL_INFO(dev)->gen >= 6)
10223                 gen6_rps_busy(dev_priv);
10224         dev_priv->mm.busy = true;
10225 }
10226
10227 void intel_mark_idle(struct drm_device *dev)
10228 {
10229         struct drm_i915_private *dev_priv = dev->dev_private;
10230         struct drm_crtc *crtc;
10231
10232         if (!dev_priv->mm.busy)
10233                 return;
10234
10235         dev_priv->mm.busy = false;
10236
10237         for_each_crtc(dev, crtc) {
10238                 if (!crtc->primary->fb)
10239                         continue;
10240
10241                 intel_decrease_pllclock(crtc);
10242         }
10243
10244         if (INTEL_INFO(dev)->gen >= 6)
10245                 gen6_rps_idle(dev->dev_private);
10246
10247         intel_runtime_pm_put(dev_priv);
10248 }
10249
10250 static void intel_crtc_destroy(struct drm_crtc *crtc)
10251 {
10252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10253         struct drm_device *dev = crtc->dev;
10254         struct intel_unpin_work *work;
10255
10256         spin_lock_irq(&dev->event_lock);
10257         work = intel_crtc->unpin_work;
10258         intel_crtc->unpin_work = NULL;
10259         spin_unlock_irq(&dev->event_lock);
10260
10261         if (work) {
10262                 cancel_work_sync(&work->work);
10263                 kfree(work);
10264         }
10265
10266         drm_crtc_cleanup(crtc);
10267
10268         kfree(intel_crtc);
10269 }
10270
10271 static void intel_unpin_work_fn(struct work_struct *__work)
10272 {
10273         struct intel_unpin_work *work =
10274                 container_of(__work, struct intel_unpin_work, work);
10275         struct drm_device *dev = work->crtc->dev;
10276         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10277
10278         mutex_lock(&dev->struct_mutex);
10279         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10280         drm_gem_object_unreference(&work->pending_flip_obj->base);
10281
10282         intel_fbc_update(dev);
10283
10284         if (work->flip_queued_req)
10285                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10286         mutex_unlock(&dev->struct_mutex);
10287
10288         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10289         drm_framebuffer_unreference(work->old_fb);
10290
10291         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10292         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10293
10294         kfree(work);
10295 }
10296
10297 static void do_intel_finish_page_flip(struct drm_device *dev,
10298                                       struct drm_crtc *crtc)
10299 {
10300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10301         struct intel_unpin_work *work;
10302         unsigned long flags;
10303
10304         /* Ignore early vblank irqs */
10305         if (intel_crtc == NULL)
10306                 return;
10307
10308         /*
10309          * This is called both by irq handlers and the reset code (to complete
10310          * lost pageflips) so needs the full irqsave spinlocks.
10311          */
10312         spin_lock_irqsave(&dev->event_lock, flags);
10313         work = intel_crtc->unpin_work;
10314
10315         /* Ensure we don't miss a work->pending update ... */
10316         smp_rmb();
10317
10318         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10319                 spin_unlock_irqrestore(&dev->event_lock, flags);
10320                 return;
10321         }
10322
10323         page_flip_completed(intel_crtc);
10324
10325         spin_unlock_irqrestore(&dev->event_lock, flags);
10326 }
10327
10328 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10329 {
10330         struct drm_i915_private *dev_priv = dev->dev_private;
10331         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10332
10333         do_intel_finish_page_flip(dev, crtc);
10334 }
10335
10336 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10337 {
10338         struct drm_i915_private *dev_priv = dev->dev_private;
10339         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10340
10341         do_intel_finish_page_flip(dev, crtc);
10342 }
10343
10344 /* Is 'a' after or equal to 'b'? */
10345 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10346 {
10347         return !((a - b) & 0x80000000);
10348 }
10349
10350 static bool page_flip_finished(struct intel_crtc *crtc)
10351 {
10352         struct drm_device *dev = crtc->base.dev;
10353         struct drm_i915_private *dev_priv = dev->dev_private;
10354
10355         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10356             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10357                 return true;
10358
10359         /*
10360          * The relevant registers doen't exist on pre-ctg.
10361          * As the flip done interrupt doesn't trigger for mmio
10362          * flips on gmch platforms, a flip count check isn't
10363          * really needed there. But since ctg has the registers,
10364          * include it in the check anyway.
10365          */
10366         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10367                 return true;
10368
10369         /*
10370          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10371          * used the same base address. In that case the mmio flip might
10372          * have completed, but the CS hasn't even executed the flip yet.
10373          *
10374          * A flip count check isn't enough as the CS might have updated
10375          * the base address just after start of vblank, but before we
10376          * managed to process the interrupt. This means we'd complete the
10377          * CS flip too soon.
10378          *
10379          * Combining both checks should get us a good enough result. It may
10380          * still happen that the CS flip has been executed, but has not
10381          * yet actually completed. But in case the base address is the same
10382          * anyway, we don't really care.
10383          */
10384         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10385                 crtc->unpin_work->gtt_offset &&
10386                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10387                                     crtc->unpin_work->flip_count);
10388 }
10389
10390 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10391 {
10392         struct drm_i915_private *dev_priv = dev->dev_private;
10393         struct intel_crtc *intel_crtc =
10394                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10395         unsigned long flags;
10396
10397
10398         /*
10399          * This is called both by irq handlers and the reset code (to complete
10400          * lost pageflips) so needs the full irqsave spinlocks.
10401          *
10402          * NB: An MMIO update of the plane base pointer will also
10403          * generate a page-flip completion irq, i.e. every modeset
10404          * is also accompanied by a spurious intel_prepare_page_flip().
10405          */
10406         spin_lock_irqsave(&dev->event_lock, flags);
10407         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10408                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10409         spin_unlock_irqrestore(&dev->event_lock, flags);
10410 }
10411
10412 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10413 {
10414         /* Ensure that the work item is consistent when activating it ... */
10415         smp_wmb();
10416         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10417         /* and that it is marked active as soon as the irq could fire. */
10418         smp_wmb();
10419 }
10420
10421 static int intel_gen2_queue_flip(struct drm_device *dev,
10422                                  struct drm_crtc *crtc,
10423                                  struct drm_framebuffer *fb,
10424                                  struct drm_i915_gem_object *obj,
10425                                  struct intel_engine_cs *ring,
10426                                  uint32_t flags)
10427 {
10428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10429         u32 flip_mask;
10430         int ret;
10431
10432         ret = intel_ring_begin(ring, 6);
10433         if (ret)
10434                 return ret;
10435
10436         /* Can't queue multiple flips, so wait for the previous
10437          * one to finish before executing the next.
10438          */
10439         if (intel_crtc->plane)
10440                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10441         else
10442                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10443         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10444         intel_ring_emit(ring, MI_NOOP);
10445         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10446                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10447         intel_ring_emit(ring, fb->pitches[0]);
10448         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10449         intel_ring_emit(ring, 0); /* aux display base address, unused */
10450
10451         intel_mark_page_flip_active(intel_crtc);
10452         __intel_ring_advance(ring);
10453         return 0;
10454 }
10455
10456 static int intel_gen3_queue_flip(struct drm_device *dev,
10457                                  struct drm_crtc *crtc,
10458                                  struct drm_framebuffer *fb,
10459                                  struct drm_i915_gem_object *obj,
10460                                  struct intel_engine_cs *ring,
10461                                  uint32_t flags)
10462 {
10463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10464         u32 flip_mask;
10465         int ret;
10466
10467         ret = intel_ring_begin(ring, 6);
10468         if (ret)
10469                 return ret;
10470
10471         if (intel_crtc->plane)
10472                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10473         else
10474                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10475         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10476         intel_ring_emit(ring, MI_NOOP);
10477         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10478                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10479         intel_ring_emit(ring, fb->pitches[0]);
10480         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10481         intel_ring_emit(ring, MI_NOOP);
10482
10483         intel_mark_page_flip_active(intel_crtc);
10484         __intel_ring_advance(ring);
10485         return 0;
10486 }
10487
10488 static int intel_gen4_queue_flip(struct drm_device *dev,
10489                                  struct drm_crtc *crtc,
10490                                  struct drm_framebuffer *fb,
10491                                  struct drm_i915_gem_object *obj,
10492                                  struct intel_engine_cs *ring,
10493                                  uint32_t flags)
10494 {
10495         struct drm_i915_private *dev_priv = dev->dev_private;
10496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10497         uint32_t pf, pipesrc;
10498         int ret;
10499
10500         ret = intel_ring_begin(ring, 4);
10501         if (ret)
10502                 return ret;
10503
10504         /* i965+ uses the linear or tiled offsets from the
10505          * Display Registers (which do not change across a page-flip)
10506          * so we need only reprogram the base address.
10507          */
10508         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10509                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10510         intel_ring_emit(ring, fb->pitches[0]);
10511         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10512                         obj->tiling_mode);
10513
10514         /* XXX Enabling the panel-fitter across page-flip is so far
10515          * untested on non-native modes, so ignore it for now.
10516          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10517          */
10518         pf = 0;
10519         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10520         intel_ring_emit(ring, pf | pipesrc);
10521
10522         intel_mark_page_flip_active(intel_crtc);
10523         __intel_ring_advance(ring);
10524         return 0;
10525 }
10526
10527 static int intel_gen6_queue_flip(struct drm_device *dev,
10528                                  struct drm_crtc *crtc,
10529                                  struct drm_framebuffer *fb,
10530                                  struct drm_i915_gem_object *obj,
10531                                  struct intel_engine_cs *ring,
10532                                  uint32_t flags)
10533 {
10534         struct drm_i915_private *dev_priv = dev->dev_private;
10535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10536         uint32_t pf, pipesrc;
10537         int ret;
10538
10539         ret = intel_ring_begin(ring, 4);
10540         if (ret)
10541                 return ret;
10542
10543         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10544                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10545         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10546         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10547
10548         /* Contrary to the suggestions in the documentation,
10549          * "Enable Panel Fitter" does not seem to be required when page
10550          * flipping with a non-native mode, and worse causes a normal
10551          * modeset to fail.
10552          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10553          */
10554         pf = 0;
10555         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10556         intel_ring_emit(ring, pf | pipesrc);
10557
10558         intel_mark_page_flip_active(intel_crtc);
10559         __intel_ring_advance(ring);
10560         return 0;
10561 }
10562
10563 static int intel_gen7_queue_flip(struct drm_device *dev,
10564                                  struct drm_crtc *crtc,
10565                                  struct drm_framebuffer *fb,
10566                                  struct drm_i915_gem_object *obj,
10567                                  struct intel_engine_cs *ring,
10568                                  uint32_t flags)
10569 {
10570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10571         uint32_t plane_bit = 0;
10572         int len, ret;
10573
10574         switch (intel_crtc->plane) {
10575         case PLANE_A:
10576                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10577                 break;
10578         case PLANE_B:
10579                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10580                 break;
10581         case PLANE_C:
10582                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10583                 break;
10584         default:
10585                 WARN_ONCE(1, "unknown plane in flip command\n");
10586                 return -ENODEV;
10587         }
10588
10589         len = 4;
10590         if (ring->id == RCS) {
10591                 len += 6;
10592                 /*
10593                  * On Gen 8, SRM is now taking an extra dword to accommodate
10594                  * 48bits addresses, and we need a NOOP for the batch size to
10595                  * stay even.
10596                  */
10597                 if (IS_GEN8(dev))
10598                         len += 2;
10599         }
10600
10601         /*
10602          * BSpec MI_DISPLAY_FLIP for IVB:
10603          * "The full packet must be contained within the same cache line."
10604          *
10605          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10606          * cacheline, if we ever start emitting more commands before
10607          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10608          * then do the cacheline alignment, and finally emit the
10609          * MI_DISPLAY_FLIP.
10610          */
10611         ret = intel_ring_cacheline_align(ring);
10612         if (ret)
10613                 return ret;
10614
10615         ret = intel_ring_begin(ring, len);
10616         if (ret)
10617                 return ret;
10618
10619         /* Unmask the flip-done completion message. Note that the bspec says that
10620          * we should do this for both the BCS and RCS, and that we must not unmask
10621          * more than one flip event at any time (or ensure that one flip message
10622          * can be sent by waiting for flip-done prior to queueing new flips).
10623          * Experimentation says that BCS works despite DERRMR masking all
10624          * flip-done completion events and that unmasking all planes at once
10625          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10626          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10627          */
10628         if (ring->id == RCS) {
10629                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10630                 intel_ring_emit(ring, DERRMR);
10631                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10632                                         DERRMR_PIPEB_PRI_FLIP_DONE |
10633                                         DERRMR_PIPEC_PRI_FLIP_DONE));
10634                 if (IS_GEN8(dev))
10635                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10636                                               MI_SRM_LRM_GLOBAL_GTT);
10637                 else
10638                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10639                                               MI_SRM_LRM_GLOBAL_GTT);
10640                 intel_ring_emit(ring, DERRMR);
10641                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10642                 if (IS_GEN8(dev)) {
10643                         intel_ring_emit(ring, 0);
10644                         intel_ring_emit(ring, MI_NOOP);
10645                 }
10646         }
10647
10648         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10649         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10650         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10651         intel_ring_emit(ring, (MI_NOOP));
10652
10653         intel_mark_page_flip_active(intel_crtc);
10654         __intel_ring_advance(ring);
10655         return 0;
10656 }
10657
10658 static bool use_mmio_flip(struct intel_engine_cs *ring,
10659                           struct drm_i915_gem_object *obj)
10660 {
10661         /*
10662          * This is not being used for older platforms, because
10663          * non-availability of flip done interrupt forces us to use
10664          * CS flips. Older platforms derive flip done using some clever
10665          * tricks involving the flip_pending status bits and vblank irqs.
10666          * So using MMIO flips there would disrupt this mechanism.
10667          */
10668
10669         if (ring == NULL)
10670                 return true;
10671
10672         if (INTEL_INFO(ring->dev)->gen < 5)
10673                 return false;
10674
10675         if (i915.use_mmio_flip < 0)
10676                 return false;
10677         else if (i915.use_mmio_flip > 0)
10678                 return true;
10679         else if (i915.enable_execlists)
10680                 return true;
10681         else
10682                 return ring != i915_gem_request_get_ring(obj->last_read_req);
10683 }
10684
10685 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10686 {
10687         struct drm_device *dev = intel_crtc->base.dev;
10688         struct drm_i915_private *dev_priv = dev->dev_private;
10689         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10690         const enum pipe pipe = intel_crtc->pipe;
10691         u32 ctl, stride;
10692
10693         ctl = I915_READ(PLANE_CTL(pipe, 0));
10694         ctl &= ~PLANE_CTL_TILED_MASK;
10695         switch (fb->modifier[0]) {
10696         case DRM_FORMAT_MOD_NONE:
10697                 break;
10698         case I915_FORMAT_MOD_X_TILED:
10699                 ctl |= PLANE_CTL_TILED_X;
10700                 break;
10701         case I915_FORMAT_MOD_Y_TILED:
10702                 ctl |= PLANE_CTL_TILED_Y;
10703                 break;
10704         case I915_FORMAT_MOD_Yf_TILED:
10705                 ctl |= PLANE_CTL_TILED_YF;
10706                 break;
10707         default:
10708                 MISSING_CASE(fb->modifier[0]);
10709         }
10710
10711         /*
10712          * The stride is either expressed as a multiple of 64 bytes chunks for
10713          * linear buffers or in number of tiles for tiled buffers.
10714          */
10715         stride = fb->pitches[0] /
10716                  intel_fb_stride_alignment(dev, fb->modifier[0],
10717                                            fb->pixel_format);
10718
10719         /*
10720          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10721          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10722          */
10723         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10724         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10725
10726         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10727         POSTING_READ(PLANE_SURF(pipe, 0));
10728 }
10729
10730 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10731 {
10732         struct drm_device *dev = intel_crtc->base.dev;
10733         struct drm_i915_private *dev_priv = dev->dev_private;
10734         struct intel_framebuffer *intel_fb =
10735                 to_intel_framebuffer(intel_crtc->base.primary->fb);
10736         struct drm_i915_gem_object *obj = intel_fb->obj;
10737         u32 dspcntr;
10738         u32 reg;
10739
10740         reg = DSPCNTR(intel_crtc->plane);
10741         dspcntr = I915_READ(reg);
10742
10743         if (obj->tiling_mode != I915_TILING_NONE)
10744                 dspcntr |= DISPPLANE_TILED;
10745         else
10746                 dspcntr &= ~DISPPLANE_TILED;
10747
10748         I915_WRITE(reg, dspcntr);
10749
10750         I915_WRITE(DSPSURF(intel_crtc->plane),
10751                    intel_crtc->unpin_work->gtt_offset);
10752         POSTING_READ(DSPSURF(intel_crtc->plane));
10753
10754 }
10755
10756 /*
10757  * XXX: This is the temporary way to update the plane registers until we get
10758  * around to using the usual plane update functions for MMIO flips
10759  */
10760 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10761 {
10762         struct drm_device *dev = intel_crtc->base.dev;
10763         bool atomic_update;
10764         u32 start_vbl_count;
10765
10766         intel_mark_page_flip_active(intel_crtc);
10767
10768         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10769
10770         if (INTEL_INFO(dev)->gen >= 9)
10771                 skl_do_mmio_flip(intel_crtc);
10772         else
10773                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10774                 ilk_do_mmio_flip(intel_crtc);
10775
10776         if (atomic_update)
10777                 intel_pipe_update_end(intel_crtc, start_vbl_count);
10778 }
10779
10780 static void intel_mmio_flip_work_func(struct work_struct *work)
10781 {
10782         struct intel_mmio_flip *mmio_flip =
10783                 container_of(work, struct intel_mmio_flip, work);
10784
10785         if (mmio_flip->rq)
10786                 WARN_ON(__i915_wait_request(mmio_flip->rq,
10787                                             mmio_flip->crtc->reset_counter,
10788                                             false, NULL, NULL));
10789
10790         intel_do_mmio_flip(mmio_flip->crtc);
10791
10792         i915_gem_request_unreference__unlocked(mmio_flip->rq);
10793         kfree(mmio_flip);
10794 }
10795
10796 static int intel_queue_mmio_flip(struct drm_device *dev,
10797                                  struct drm_crtc *crtc,
10798                                  struct drm_framebuffer *fb,
10799                                  struct drm_i915_gem_object *obj,
10800                                  struct intel_engine_cs *ring,
10801                                  uint32_t flags)
10802 {
10803         struct intel_mmio_flip *mmio_flip;
10804
10805         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10806         if (mmio_flip == NULL)
10807                 return -ENOMEM;
10808
10809         mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10810         mmio_flip->crtc = to_intel_crtc(crtc);
10811
10812         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10813         schedule_work(&mmio_flip->work);
10814
10815         return 0;
10816 }
10817
10818 static int intel_default_queue_flip(struct drm_device *dev,
10819                                     struct drm_crtc *crtc,
10820                                     struct drm_framebuffer *fb,
10821                                     struct drm_i915_gem_object *obj,
10822                                     struct intel_engine_cs *ring,
10823                                     uint32_t flags)
10824 {
10825         return -ENODEV;
10826 }
10827
10828 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10829                                          struct drm_crtc *crtc)
10830 {
10831         struct drm_i915_private *dev_priv = dev->dev_private;
10832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10833         struct intel_unpin_work *work = intel_crtc->unpin_work;
10834         u32 addr;
10835
10836         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10837                 return true;
10838
10839         if (!work->enable_stall_check)
10840                 return false;
10841
10842         if (work->flip_ready_vblank == 0) {
10843                 if (work->flip_queued_req &&
10844                     !i915_gem_request_completed(work->flip_queued_req, true))
10845                         return false;
10846
10847                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10848         }
10849
10850         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10851                 return false;
10852
10853         /* Potential stall - if we see that the flip has happened,
10854          * assume a missed interrupt. */
10855         if (INTEL_INFO(dev)->gen >= 4)
10856                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10857         else
10858                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10859
10860         /* There is a potential issue here with a false positive after a flip
10861          * to the same address. We could address this by checking for a
10862          * non-incrementing frame counter.
10863          */
10864         return addr == work->gtt_offset;
10865 }
10866
10867 void intel_check_page_flip(struct drm_device *dev, int pipe)
10868 {
10869         struct drm_i915_private *dev_priv = dev->dev_private;
10870         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10872         struct intel_unpin_work *work;
10873
10874         WARN_ON(!in_interrupt());
10875
10876         if (crtc == NULL)
10877                 return;
10878
10879         spin_lock(&dev->event_lock);
10880         work = intel_crtc->unpin_work;
10881         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10882                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10883                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10884                 page_flip_completed(intel_crtc);
10885                 work = NULL;
10886         }
10887         if (work != NULL &&
10888             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10889                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10890         spin_unlock(&dev->event_lock);
10891 }
10892
10893 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10894                                 struct drm_framebuffer *fb,
10895                                 struct drm_pending_vblank_event *event,
10896                                 uint32_t page_flip_flags)
10897 {
10898         struct drm_device *dev = crtc->dev;
10899         struct drm_i915_private *dev_priv = dev->dev_private;
10900         struct drm_framebuffer *old_fb = crtc->primary->fb;
10901         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10903         struct drm_plane *primary = crtc->primary;
10904         enum pipe pipe = intel_crtc->pipe;
10905         struct intel_unpin_work *work;
10906         struct intel_engine_cs *ring;
10907         bool mmio_flip;
10908         int ret;
10909
10910         /*
10911          * drm_mode_page_flip_ioctl() should already catch this, but double
10912          * check to be safe.  In the future we may enable pageflipping from
10913          * a disabled primary plane.
10914          */
10915         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10916                 return -EBUSY;
10917
10918         /* Can't change pixel format via MI display flips. */
10919         if (fb->pixel_format != crtc->primary->fb->pixel_format)
10920                 return -EINVAL;
10921
10922         /*
10923          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10924          * Note that pitch changes could also affect these register.
10925          */
10926         if (INTEL_INFO(dev)->gen > 3 &&
10927             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10928              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10929                 return -EINVAL;
10930
10931         if (i915_terminally_wedged(&dev_priv->gpu_error))
10932                 goto out_hang;
10933
10934         work = kzalloc(sizeof(*work), GFP_KERNEL);
10935         if (work == NULL)
10936                 return -ENOMEM;
10937
10938         work->event = event;
10939         work->crtc = crtc;
10940         work->old_fb = old_fb;
10941         INIT_WORK(&work->work, intel_unpin_work_fn);
10942
10943         ret = drm_crtc_vblank_get(crtc);
10944         if (ret)
10945                 goto free_work;
10946
10947         /* We borrow the event spin lock for protecting unpin_work */
10948         spin_lock_irq(&dev->event_lock);
10949         if (intel_crtc->unpin_work) {
10950                 /* Before declaring the flip queue wedged, check if
10951                  * the hardware completed the operation behind our backs.
10952                  */
10953                 if (__intel_pageflip_stall_check(dev, crtc)) {
10954                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10955                         page_flip_completed(intel_crtc);
10956                 } else {
10957                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10958                         spin_unlock_irq(&dev->event_lock);
10959
10960                         drm_crtc_vblank_put(crtc);
10961                         kfree(work);
10962                         return -EBUSY;
10963                 }
10964         }
10965         intel_crtc->unpin_work = work;
10966         spin_unlock_irq(&dev->event_lock);
10967
10968         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10969                 flush_workqueue(dev_priv->wq);
10970
10971         /* Reference the objects for the scheduled work. */
10972         drm_framebuffer_reference(work->old_fb);
10973         drm_gem_object_reference(&obj->base);
10974
10975         crtc->primary->fb = fb;
10976         update_state_fb(crtc->primary);
10977
10978         work->pending_flip_obj = obj;
10979
10980         ret = i915_mutex_lock_interruptible(dev);
10981         if (ret)
10982                 goto cleanup;
10983
10984         atomic_inc(&intel_crtc->unpin_work_count);
10985         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10986
10987         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10988                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10989
10990         if (IS_VALLEYVIEW(dev)) {
10991                 ring = &dev_priv->ring[BCS];
10992                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10993                         /* vlv: DISPLAY_FLIP fails to change tiling */
10994                         ring = NULL;
10995         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10996                 ring = &dev_priv->ring[BCS];
10997         } else if (INTEL_INFO(dev)->gen >= 7) {
10998                 ring = i915_gem_request_get_ring(obj->last_read_req);
10999                 if (ring == NULL || ring->id != RCS)
11000                         ring = &dev_priv->ring[BCS];
11001         } else {
11002                 ring = &dev_priv->ring[RCS];
11003         }
11004
11005         mmio_flip = use_mmio_flip(ring, obj);
11006
11007         /* When using CS flips, we want to emit semaphores between rings.
11008          * However, when using mmio flips we will create a task to do the
11009          * synchronisation, so all we want here is to pin the framebuffer
11010          * into the display plane and skip any waits.
11011          */
11012         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11013                                          crtc->primary->state,
11014                                          mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11015         if (ret)
11016                 goto cleanup_pending;
11017
11018         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11019                                                   + intel_crtc->dspaddr_offset;
11020
11021         if (mmio_flip) {
11022                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11023                                             page_flip_flags);
11024                 if (ret)
11025                         goto cleanup_unpin;
11026
11027                 i915_gem_request_assign(&work->flip_queued_req,
11028                                         obj->last_write_req);
11029         } else {
11030                 if (obj->last_write_req) {
11031                         ret = i915_gem_check_olr(obj->last_write_req);
11032                         if (ret)
11033                                 goto cleanup_unpin;
11034                 }
11035
11036                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11037                                                    page_flip_flags);
11038                 if (ret)
11039                         goto cleanup_unpin;
11040
11041                 i915_gem_request_assign(&work->flip_queued_req,
11042                                         intel_ring_get_request(ring));
11043         }
11044
11045         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11046         work->enable_stall_check = true;
11047
11048         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11049                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11050
11051         intel_fbc_disable(dev);
11052         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11053         mutex_unlock(&dev->struct_mutex);
11054
11055         trace_i915_flip_request(intel_crtc->plane, obj);
11056
11057         return 0;
11058
11059 cleanup_unpin:
11060         intel_unpin_fb_obj(fb, crtc->primary->state);
11061 cleanup_pending:
11062         atomic_dec(&intel_crtc->unpin_work_count);
11063         mutex_unlock(&dev->struct_mutex);
11064 cleanup:
11065         crtc->primary->fb = old_fb;
11066         update_state_fb(crtc->primary);
11067
11068         drm_gem_object_unreference_unlocked(&obj->base);
11069         drm_framebuffer_unreference(work->old_fb);
11070
11071         spin_lock_irq(&dev->event_lock);
11072         intel_crtc->unpin_work = NULL;
11073         spin_unlock_irq(&dev->event_lock);
11074
11075         drm_crtc_vblank_put(crtc);
11076 free_work:
11077         kfree(work);
11078
11079         if (ret == -EIO) {
11080 out_hang:
11081                 ret = intel_plane_restore(primary);
11082                 if (ret == 0 && event) {
11083                         spin_lock_irq(&dev->event_lock);
11084                         drm_send_vblank_event(dev, pipe, event);
11085                         spin_unlock_irq(&dev->event_lock);
11086                 }
11087         }
11088         return ret;
11089 }
11090
11091 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11092         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11093         .load_lut = intel_crtc_load_lut,
11094         .atomic_begin = intel_begin_crtc_commit,
11095         .atomic_flush = intel_finish_crtc_commit,
11096 };
11097
11098 /**
11099  * intel_modeset_update_staged_output_state
11100  *
11101  * Updates the staged output configuration state, e.g. after we've read out the
11102  * current hw state.
11103  */
11104 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11105 {
11106         struct intel_crtc *crtc;
11107         struct intel_encoder *encoder;
11108         struct intel_connector *connector;
11109
11110         for_each_intel_connector(dev, connector) {
11111                 connector->new_encoder =
11112                         to_intel_encoder(connector->base.encoder);
11113         }
11114
11115         for_each_intel_encoder(dev, encoder) {
11116                 encoder->new_crtc =
11117                         to_intel_crtc(encoder->base.crtc);
11118         }
11119
11120         for_each_intel_crtc(dev, crtc) {
11121                 crtc->new_enabled = crtc->base.state->enable;
11122         }
11123 }
11124
11125 /* Transitional helper to copy current connector/encoder state to
11126  * connector->state. This is needed so that code that is partially
11127  * converted to atomic does the right thing.
11128  */
11129 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11130 {
11131         struct intel_connector *connector;
11132
11133         for_each_intel_connector(dev, connector) {
11134                 if (connector->base.encoder) {
11135                         connector->base.state->best_encoder =
11136                                 connector->base.encoder;
11137                         connector->base.state->crtc =
11138                                 connector->base.encoder->crtc;
11139                 } else {
11140                         connector->base.state->best_encoder = NULL;
11141                         connector->base.state->crtc = NULL;
11142                 }
11143         }
11144 }
11145
11146 /* Fixup legacy state after an atomic state swap.
11147  */
11148 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11149 {
11150         struct intel_crtc *crtc;
11151         struct intel_encoder *encoder;
11152         struct intel_connector *connector;
11153
11154         for_each_intel_connector(state->dev, connector) {
11155                 connector->base.encoder = connector->base.state->best_encoder;
11156                 if (connector->base.encoder)
11157                         connector->base.encoder->crtc =
11158                                 connector->base.state->crtc;
11159         }
11160
11161         /* Update crtc of disabled encoders */
11162         for_each_intel_encoder(state->dev, encoder) {
11163                 int num_connectors = 0;
11164
11165                 for_each_intel_connector(state->dev, connector)
11166                         if (connector->base.encoder == &encoder->base)
11167                                 num_connectors++;
11168
11169                 if (num_connectors == 0)
11170                         encoder->base.crtc = NULL;
11171         }
11172
11173         for_each_intel_crtc(state->dev, crtc) {
11174                 crtc->base.enabled = crtc->base.state->enable;
11175                 crtc->config = to_intel_crtc_state(crtc->base.state);
11176         }
11177
11178         /* Copy the new configuration to the staged state, to keep the few
11179          * pieces of code that haven't been converted yet happy */
11180         intel_modeset_update_staged_output_state(state->dev);
11181 }
11182
11183 static void
11184 connected_sink_compute_bpp(struct intel_connector *connector,
11185                            struct intel_crtc_state *pipe_config)
11186 {
11187         int bpp = pipe_config->pipe_bpp;
11188
11189         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11190                 connector->base.base.id,
11191                 connector->base.name);
11192
11193         /* Don't use an invalid EDID bpc value */
11194         if (connector->base.display_info.bpc &&
11195             connector->base.display_info.bpc * 3 < bpp) {
11196                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11197                               bpp, connector->base.display_info.bpc*3);
11198                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11199         }
11200
11201         /* Clamp bpp to 8 on screens without EDID 1.4 */
11202         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11203                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11204                               bpp);
11205                 pipe_config->pipe_bpp = 24;
11206         }
11207 }
11208
11209 static int
11210 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11211                           struct intel_crtc_state *pipe_config)
11212 {
11213         struct drm_device *dev = crtc->base.dev;
11214         struct drm_atomic_state *state;
11215         struct drm_connector *connector;
11216         struct drm_connector_state *connector_state;
11217         int bpp, i;
11218
11219         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11220                 bpp = 10*3;
11221         else if (INTEL_INFO(dev)->gen >= 5)
11222                 bpp = 12*3;
11223         else
11224                 bpp = 8*3;
11225
11226
11227         pipe_config->pipe_bpp = bpp;
11228
11229         state = pipe_config->base.state;
11230
11231         /* Clamp display bpp to EDID value */
11232         for_each_connector_in_state(state, connector, connector_state, i) {
11233                 if (connector_state->crtc != &crtc->base)
11234                         continue;
11235
11236                 connected_sink_compute_bpp(to_intel_connector(connector),
11237                                            pipe_config);
11238         }
11239
11240         return bpp;
11241 }
11242
11243 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11244 {
11245         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11246                         "type: 0x%x flags: 0x%x\n",
11247                 mode->crtc_clock,
11248                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11249                 mode->crtc_hsync_end, mode->crtc_htotal,
11250                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11251                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11252 }
11253
11254 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11255                                    struct intel_crtc_state *pipe_config,
11256                                    const char *context)
11257 {
11258         struct drm_device *dev = crtc->base.dev;
11259         struct drm_plane *plane;
11260         struct intel_plane *intel_plane;
11261         struct intel_plane_state *state;
11262         struct drm_framebuffer *fb;
11263
11264         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11265                       context, pipe_config, pipe_name(crtc->pipe));
11266
11267         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11268         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11269                       pipe_config->pipe_bpp, pipe_config->dither);
11270         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11271                       pipe_config->has_pch_encoder,
11272                       pipe_config->fdi_lanes,
11273                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11274                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11275                       pipe_config->fdi_m_n.tu);
11276         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11277                       pipe_config->has_dp_encoder,
11278                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11279                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11280                       pipe_config->dp_m_n.tu);
11281
11282         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11283                       pipe_config->has_dp_encoder,
11284                       pipe_config->dp_m2_n2.gmch_m,
11285                       pipe_config->dp_m2_n2.gmch_n,
11286                       pipe_config->dp_m2_n2.link_m,
11287                       pipe_config->dp_m2_n2.link_n,
11288                       pipe_config->dp_m2_n2.tu);
11289
11290         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11291                       pipe_config->has_audio,
11292                       pipe_config->has_infoframe);
11293
11294         DRM_DEBUG_KMS("requested mode:\n");
11295         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11296         DRM_DEBUG_KMS("adjusted mode:\n");
11297         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11298         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11299         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11300         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11301                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11302         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11303                       crtc->num_scalers,
11304                       pipe_config->scaler_state.scaler_users,
11305                       pipe_config->scaler_state.scaler_id);
11306         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11307                       pipe_config->gmch_pfit.control,
11308                       pipe_config->gmch_pfit.pgm_ratios,
11309                       pipe_config->gmch_pfit.lvds_border_bits);
11310         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11311                       pipe_config->pch_pfit.pos,
11312                       pipe_config->pch_pfit.size,
11313                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11314         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11315         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11316
11317         DRM_DEBUG_KMS("planes on this crtc\n");
11318         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11319                 intel_plane = to_intel_plane(plane);
11320                 if (intel_plane->pipe != crtc->pipe)
11321                         continue;
11322
11323                 state = to_intel_plane_state(plane->state);
11324                 fb = state->base.fb;
11325                 if (!fb) {
11326                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11327                                 "disabled, scaler_id = %d\n",
11328                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11329                                 plane->base.id, intel_plane->pipe,
11330                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11331                                 drm_plane_index(plane), state->scaler_id);
11332                         continue;
11333                 }
11334
11335                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11336                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11337                         plane->base.id, intel_plane->pipe,
11338                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11339                         drm_plane_index(plane));
11340                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11341                         fb->base.id, fb->width, fb->height, fb->pixel_format);
11342                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11343                         state->scaler_id,
11344                         state->src.x1 >> 16, state->src.y1 >> 16,
11345                         drm_rect_width(&state->src) >> 16,
11346                         drm_rect_height(&state->src) >> 16,
11347                         state->dst.x1, state->dst.y1,
11348                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11349         }
11350 }
11351
11352 static bool encoders_cloneable(const struct intel_encoder *a,
11353                                const struct intel_encoder *b)
11354 {
11355         /* masks could be asymmetric, so check both ways */
11356         return a == b || (a->cloneable & (1 << b->type) &&
11357                           b->cloneable & (1 << a->type));
11358 }
11359
11360 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11361                                          struct intel_crtc *crtc,
11362                                          struct intel_encoder *encoder)
11363 {
11364         struct intel_encoder *source_encoder;
11365         struct drm_connector *connector;
11366         struct drm_connector_state *connector_state;
11367         int i;
11368
11369         for_each_connector_in_state(state, connector, connector_state, i) {
11370                 if (connector_state->crtc != &crtc->base)
11371                         continue;
11372
11373                 source_encoder =
11374                         to_intel_encoder(connector_state->best_encoder);
11375                 if (!encoders_cloneable(encoder, source_encoder))
11376                         return false;
11377         }
11378
11379         return true;
11380 }
11381
11382 static bool check_encoder_cloning(struct drm_atomic_state *state,
11383                                   struct intel_crtc *crtc)
11384 {
11385         struct intel_encoder *encoder;
11386         struct drm_connector *connector;
11387         struct drm_connector_state *connector_state;
11388         int i;
11389
11390         for_each_connector_in_state(state, connector, connector_state, i) {
11391                 if (connector_state->crtc != &crtc->base)
11392                         continue;
11393
11394                 encoder = to_intel_encoder(connector_state->best_encoder);
11395                 if (!check_single_encoder_cloning(state, crtc, encoder))
11396                         return false;
11397         }
11398
11399         return true;
11400 }
11401
11402 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11403 {
11404         struct drm_device *dev = state->dev;
11405         struct intel_encoder *encoder;
11406         struct drm_connector *connector;
11407         struct drm_connector_state *connector_state;
11408         unsigned int used_ports = 0;
11409         int i;
11410
11411         /*
11412          * Walk the connector list instead of the encoder
11413          * list to detect the problem on ddi platforms
11414          * where there's just one encoder per digital port.
11415          */
11416         for_each_connector_in_state(state, connector, connector_state, i) {
11417                 if (!connector_state->best_encoder)
11418                         continue;
11419
11420                 encoder = to_intel_encoder(connector_state->best_encoder);
11421
11422                 WARN_ON(!connector_state->crtc);
11423
11424                 switch (encoder->type) {
11425                         unsigned int port_mask;
11426                 case INTEL_OUTPUT_UNKNOWN:
11427                         if (WARN_ON(!HAS_DDI(dev)))
11428                                 break;
11429                 case INTEL_OUTPUT_DISPLAYPORT:
11430                 case INTEL_OUTPUT_HDMI:
11431                 case INTEL_OUTPUT_EDP:
11432                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11433
11434                         /* the same port mustn't appear more than once */
11435                         if (used_ports & port_mask)
11436                                 return false;
11437
11438                         used_ports |= port_mask;
11439                 default:
11440                         break;
11441                 }
11442         }
11443
11444         return true;
11445 }
11446
11447 static void
11448 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11449 {
11450         struct drm_crtc_state tmp_state;
11451         struct intel_crtc_scaler_state scaler_state;
11452         struct intel_dpll_hw_state dpll_hw_state;
11453         enum intel_dpll_id shared_dpll;
11454
11455         /* Clear only the intel specific part of the crtc state excluding scalers */
11456         tmp_state = crtc_state->base;
11457         scaler_state = crtc_state->scaler_state;
11458         shared_dpll = crtc_state->shared_dpll;
11459         dpll_hw_state = crtc_state->dpll_hw_state;
11460
11461         memset(crtc_state, 0, sizeof *crtc_state);
11462
11463         crtc_state->base = tmp_state;
11464         crtc_state->scaler_state = scaler_state;
11465         crtc_state->shared_dpll = shared_dpll;
11466         crtc_state->dpll_hw_state = dpll_hw_state;
11467 }
11468
11469 static int
11470 intel_modeset_pipe_config(struct drm_crtc *crtc,
11471                           struct drm_atomic_state *state,
11472                           struct intel_crtc_state *pipe_config)
11473 {
11474         struct intel_encoder *encoder;
11475         struct drm_connector *connector;
11476         struct drm_connector_state *connector_state;
11477         int base_bpp, ret = -EINVAL;
11478         int i;
11479         bool retry = true;
11480
11481         if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11482                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11483                 return -EINVAL;
11484         }
11485
11486         if (!check_digital_port_conflicts(state)) {
11487                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11488                 return -EINVAL;
11489         }
11490
11491         clear_intel_crtc_state(pipe_config);
11492
11493         pipe_config->cpu_transcoder =
11494                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11495
11496         /*
11497          * Sanitize sync polarity flags based on requested ones. If neither
11498          * positive or negative polarity is requested, treat this as meaning
11499          * negative polarity.
11500          */
11501         if (!(pipe_config->base.adjusted_mode.flags &
11502               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11503                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11504
11505         if (!(pipe_config->base.adjusted_mode.flags &
11506               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11507                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11508
11509         /* Compute a starting value for pipe_config->pipe_bpp taking the source
11510          * plane pixel format and any sink constraints into account. Returns the
11511          * source plane bpp so that dithering can be selected on mismatches
11512          * after encoders and crtc also have had their say. */
11513         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11514                                              pipe_config);
11515         if (base_bpp < 0)
11516                 goto fail;
11517
11518         /*
11519          * Determine the real pipe dimensions. Note that stereo modes can
11520          * increase the actual pipe size due to the frame doubling and
11521          * insertion of additional space for blanks between the frame. This
11522          * is stored in the crtc timings. We use the requested mode to do this
11523          * computation to clearly distinguish it from the adjusted mode, which
11524          * can be changed by the connectors in the below retry loop.
11525          */
11526         drm_crtc_get_hv_timing(&pipe_config->base.mode,
11527                                &pipe_config->pipe_src_w,
11528                                &pipe_config->pipe_src_h);
11529
11530 encoder_retry:
11531         /* Ensure the port clock defaults are reset when retrying. */
11532         pipe_config->port_clock = 0;
11533         pipe_config->pixel_multiplier = 1;
11534
11535         /* Fill in default crtc timings, allow encoders to overwrite them. */
11536         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11537                               CRTC_STEREO_DOUBLE);
11538
11539         /* Pass our mode to the connectors and the CRTC to give them a chance to
11540          * adjust it according to limitations or connector properties, and also
11541          * a chance to reject the mode entirely.
11542          */
11543         for_each_connector_in_state(state, connector, connector_state, i) {
11544                 if (connector_state->crtc != crtc)
11545                         continue;
11546
11547                 encoder = to_intel_encoder(connector_state->best_encoder);
11548
11549                 if (!(encoder->compute_config(encoder, pipe_config))) {
11550                         DRM_DEBUG_KMS("Encoder config failure\n");
11551                         goto fail;
11552                 }
11553         }
11554
11555         /* Set default port clock if not overwritten by the encoder. Needs to be
11556          * done afterwards in case the encoder adjusts the mode. */
11557         if (!pipe_config->port_clock)
11558                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11559                         * pipe_config->pixel_multiplier;
11560
11561         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11562         if (ret < 0) {
11563                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11564                 goto fail;
11565         }
11566
11567         if (ret == RETRY) {
11568                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11569                         ret = -EINVAL;
11570                         goto fail;
11571                 }
11572
11573                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11574                 retry = false;
11575                 goto encoder_retry;
11576         }
11577
11578         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11579         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11580                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11581
11582         return 0;
11583 fail:
11584         return ret;
11585 }
11586
11587 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11588 {
11589         struct drm_encoder *encoder;
11590         struct drm_device *dev = crtc->dev;
11591
11592         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11593                 if (encoder->crtc == crtc)
11594                         return true;
11595
11596         return false;
11597 }
11598
11599 static bool
11600 needs_modeset(struct drm_crtc_state *state)
11601 {
11602         return state->mode_changed || state->active_changed;
11603 }
11604
11605 static void
11606 intel_modeset_update_state(struct drm_atomic_state *state)
11607 {
11608         struct drm_device *dev = state->dev;
11609         struct drm_i915_private *dev_priv = dev->dev_private;
11610         struct intel_encoder *intel_encoder;
11611         struct drm_crtc *crtc;
11612         struct drm_crtc_state *crtc_state;
11613         struct drm_connector *connector;
11614         int i;
11615
11616         intel_shared_dpll_commit(dev_priv);
11617
11618         for_each_intel_encoder(dev, intel_encoder) {
11619                 if (!intel_encoder->base.crtc)
11620                         continue;
11621
11622                 for_each_crtc_in_state(state, crtc, crtc_state, i)
11623                         if (crtc == intel_encoder->base.crtc)
11624                                 break;
11625
11626                 if (crtc != intel_encoder->base.crtc)
11627                         continue;
11628
11629                 if (crtc_state->enable && needs_modeset(crtc_state))
11630                         intel_encoder->connectors_active = false;
11631         }
11632
11633         drm_atomic_helper_swap_state(state->dev, state);
11634         intel_modeset_fixup_state(state);
11635
11636         /* Double check state. */
11637         for_each_crtc(dev, crtc) {
11638                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11639         }
11640
11641         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11642                 if (!connector->encoder || !connector->encoder->crtc)
11643                         continue;
11644
11645                 for_each_crtc_in_state(state, crtc, crtc_state, i)
11646                         if (crtc == connector->encoder->crtc)
11647                                 break;
11648
11649                 if (crtc != connector->encoder->crtc)
11650                         continue;
11651
11652                 if (crtc->state->enable && needs_modeset(crtc->state)) {
11653                         struct drm_property *dpms_property =
11654                                 dev->mode_config.dpms_property;
11655
11656                         connector->dpms = DRM_MODE_DPMS_ON;
11657                         drm_object_property_set_value(&connector->base,
11658                                                          dpms_property,
11659                                                          DRM_MODE_DPMS_ON);
11660
11661                         intel_encoder = to_intel_encoder(connector->encoder);
11662                         intel_encoder->connectors_active = true;
11663                 }
11664         }
11665
11666 }
11667
11668 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11669 {
11670         int diff;
11671
11672         if (clock1 == clock2)
11673                 return true;
11674
11675         if (!clock1 || !clock2)
11676                 return false;
11677
11678         diff = abs(clock1 - clock2);
11679
11680         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11681                 return true;
11682
11683         return false;
11684 }
11685
11686 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11687         list_for_each_entry((intel_crtc), \
11688                             &(dev)->mode_config.crtc_list, \
11689                             base.head) \
11690                 if (mask & (1 <<(intel_crtc)->pipe))
11691
11692 static bool
11693 intel_pipe_config_compare(struct drm_device *dev,
11694                           struct intel_crtc_state *current_config,
11695                           struct intel_crtc_state *pipe_config)
11696 {
11697 #define PIPE_CONF_CHECK_X(name) \
11698         if (current_config->name != pipe_config->name) { \
11699                 DRM_ERROR("mismatch in " #name " " \
11700                           "(expected 0x%08x, found 0x%08x)\n", \
11701                           current_config->name, \
11702                           pipe_config->name); \
11703                 return false; \
11704         }
11705
11706 #define PIPE_CONF_CHECK_I(name) \
11707         if (current_config->name != pipe_config->name) { \
11708                 DRM_ERROR("mismatch in " #name " " \
11709                           "(expected %i, found %i)\n", \
11710                           current_config->name, \
11711                           pipe_config->name); \
11712                 return false; \
11713         }
11714
11715 /* This is required for BDW+ where there is only one set of registers for
11716  * switching between high and low RR.
11717  * This macro can be used whenever a comparison has to be made between one
11718  * hw state and multiple sw state variables.
11719  */
11720 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11721         if ((current_config->name != pipe_config->name) && \
11722                 (current_config->alt_name != pipe_config->name)) { \
11723                         DRM_ERROR("mismatch in " #name " " \
11724                                   "(expected %i or %i, found %i)\n", \
11725                                   current_config->name, \
11726                                   current_config->alt_name, \
11727                                   pipe_config->name); \
11728                         return false; \
11729         }
11730
11731 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11732         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11733                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
11734                           "(expected %i, found %i)\n", \
11735                           current_config->name & (mask), \
11736                           pipe_config->name & (mask)); \
11737                 return false; \
11738         }
11739
11740 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11741         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11742                 DRM_ERROR("mismatch in " #name " " \
11743                           "(expected %i, found %i)\n", \
11744                           current_config->name, \
11745                           pipe_config->name); \
11746                 return false; \
11747         }
11748
11749 #define PIPE_CONF_QUIRK(quirk)  \
11750         ((current_config->quirks | pipe_config->quirks) & (quirk))
11751
11752         PIPE_CONF_CHECK_I(cpu_transcoder);
11753
11754         PIPE_CONF_CHECK_I(has_pch_encoder);
11755         PIPE_CONF_CHECK_I(fdi_lanes);
11756         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11757         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11758         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11759         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11760         PIPE_CONF_CHECK_I(fdi_m_n.tu);
11761
11762         PIPE_CONF_CHECK_I(has_dp_encoder);
11763
11764         if (INTEL_INFO(dev)->gen < 8) {
11765                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11766                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11767                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11768                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11769                 PIPE_CONF_CHECK_I(dp_m_n.tu);
11770
11771                 if (current_config->has_drrs) {
11772                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11773                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11774                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11775                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11776                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11777                 }
11778         } else {
11779                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11780                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11781                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11782                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11783                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11784         }
11785
11786         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11787         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11788         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11789         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11790         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11791         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11792
11793         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11794         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11795         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11796         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11797         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11798         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11799
11800         PIPE_CONF_CHECK_I(pixel_multiplier);
11801         PIPE_CONF_CHECK_I(has_hdmi_sink);
11802         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11803             IS_VALLEYVIEW(dev))
11804                 PIPE_CONF_CHECK_I(limited_color_range);
11805         PIPE_CONF_CHECK_I(has_infoframe);
11806
11807         PIPE_CONF_CHECK_I(has_audio);
11808
11809         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11810                               DRM_MODE_FLAG_INTERLACE);
11811
11812         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11813                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11814                                       DRM_MODE_FLAG_PHSYNC);
11815                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11816                                       DRM_MODE_FLAG_NHSYNC);
11817                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11818                                       DRM_MODE_FLAG_PVSYNC);
11819                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11820                                       DRM_MODE_FLAG_NVSYNC);
11821         }
11822
11823         PIPE_CONF_CHECK_I(pipe_src_w);
11824         PIPE_CONF_CHECK_I(pipe_src_h);
11825
11826         /*
11827          * FIXME: BIOS likes to set up a cloned config with lvds+external
11828          * screen. Since we don't yet re-compute the pipe config when moving
11829          * just the lvds port away to another pipe the sw tracking won't match.
11830          *
11831          * Proper atomic modesets with recomputed global state will fix this.
11832          * Until then just don't check gmch state for inherited modes.
11833          */
11834         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11835                 PIPE_CONF_CHECK_I(gmch_pfit.control);
11836                 /* pfit ratios are autocomputed by the hw on gen4+ */
11837                 if (INTEL_INFO(dev)->gen < 4)
11838                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11839                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11840         }
11841
11842         PIPE_CONF_CHECK_I(pch_pfit.enabled);
11843         if (current_config->pch_pfit.enabled) {
11844                 PIPE_CONF_CHECK_I(pch_pfit.pos);
11845                 PIPE_CONF_CHECK_I(pch_pfit.size);
11846         }
11847
11848         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11849
11850         /* BDW+ don't expose a synchronous way to read the state */
11851         if (IS_HASWELL(dev))
11852                 PIPE_CONF_CHECK_I(ips_enabled);
11853
11854         PIPE_CONF_CHECK_I(double_wide);
11855
11856         PIPE_CONF_CHECK_X(ddi_pll_sel);
11857
11858         PIPE_CONF_CHECK_I(shared_dpll);
11859         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11860         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11861         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11862         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11863         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11864         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11865         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11866         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11867
11868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11869                 PIPE_CONF_CHECK_I(pipe_bpp);
11870
11871         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11872         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11873
11874 #undef PIPE_CONF_CHECK_X
11875 #undef PIPE_CONF_CHECK_I
11876 #undef PIPE_CONF_CHECK_I_ALT
11877 #undef PIPE_CONF_CHECK_FLAGS
11878 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11879 #undef PIPE_CONF_QUIRK
11880
11881         return true;
11882 }
11883
11884 static void check_wm_state(struct drm_device *dev)
11885 {
11886         struct drm_i915_private *dev_priv = dev->dev_private;
11887         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11888         struct intel_crtc *intel_crtc;
11889         int plane;
11890
11891         if (INTEL_INFO(dev)->gen < 9)
11892                 return;
11893
11894         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11895         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11896
11897         for_each_intel_crtc(dev, intel_crtc) {
11898                 struct skl_ddb_entry *hw_entry, *sw_entry;
11899                 const enum pipe pipe = intel_crtc->pipe;
11900
11901                 if (!intel_crtc->active)
11902                         continue;
11903
11904                 /* planes */
11905                 for_each_plane(dev_priv, pipe, plane) {
11906                         hw_entry = &hw_ddb.plane[pipe][plane];
11907                         sw_entry = &sw_ddb->plane[pipe][plane];
11908
11909                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
11910                                 continue;
11911
11912                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11913                                   "(expected (%u,%u), found (%u,%u))\n",
11914                                   pipe_name(pipe), plane + 1,
11915                                   sw_entry->start, sw_entry->end,
11916                                   hw_entry->start, hw_entry->end);
11917                 }
11918
11919                 /* cursor */
11920                 hw_entry = &hw_ddb.cursor[pipe];
11921                 sw_entry = &sw_ddb->cursor[pipe];
11922
11923                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11924                         continue;
11925
11926                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11927                           "(expected (%u,%u), found (%u,%u))\n",
11928                           pipe_name(pipe),
11929                           sw_entry->start, sw_entry->end,
11930                           hw_entry->start, hw_entry->end);
11931         }
11932 }
11933
11934 static void
11935 check_connector_state(struct drm_device *dev)
11936 {
11937         struct intel_connector *connector;
11938
11939         for_each_intel_connector(dev, connector) {
11940                 /* This also checks the encoder/connector hw state with the
11941                  * ->get_hw_state callbacks. */
11942                 intel_connector_check_state(connector);
11943
11944                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11945                      "connector's staged encoder doesn't match current encoder\n");
11946         }
11947 }
11948
11949 static void
11950 check_encoder_state(struct drm_device *dev)
11951 {
11952         struct intel_encoder *encoder;
11953         struct intel_connector *connector;
11954
11955         for_each_intel_encoder(dev, encoder) {
11956                 bool enabled = false;
11957                 bool active = false;
11958                 enum pipe pipe, tracked_pipe;
11959
11960                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11961                               encoder->base.base.id,
11962                               encoder->base.name);
11963
11964                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11965                      "encoder's stage crtc doesn't match current crtc\n");
11966                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11967                      "encoder's active_connectors set, but no crtc\n");
11968
11969                 for_each_intel_connector(dev, connector) {
11970                         if (connector->base.encoder != &encoder->base)
11971                                 continue;
11972                         enabled = true;
11973                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11974                                 active = true;
11975                 }
11976                 /*
11977                  * for MST connectors if we unplug the connector is gone
11978                  * away but the encoder is still connected to a crtc
11979                  * until a modeset happens in response to the hotplug.
11980                  */
11981                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11982                         continue;
11983
11984                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11985                      "encoder's enabled state mismatch "
11986                      "(expected %i, found %i)\n",
11987                      !!encoder->base.crtc, enabled);
11988                 I915_STATE_WARN(active && !encoder->base.crtc,
11989                      "active encoder with no crtc\n");
11990
11991                 I915_STATE_WARN(encoder->connectors_active != active,
11992                      "encoder's computed active state doesn't match tracked active state "
11993                      "(expected %i, found %i)\n", active, encoder->connectors_active);
11994
11995                 active = encoder->get_hw_state(encoder, &pipe);
11996                 I915_STATE_WARN(active != encoder->connectors_active,
11997                      "encoder's hw state doesn't match sw tracking "
11998                      "(expected %i, found %i)\n",
11999                      encoder->connectors_active, active);
12000
12001                 if (!encoder->base.crtc)
12002                         continue;
12003
12004                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12005                 I915_STATE_WARN(active && pipe != tracked_pipe,
12006                      "active encoder's pipe doesn't match"
12007                      "(expected %i, found %i)\n",
12008                      tracked_pipe, pipe);
12009
12010         }
12011 }
12012
12013 static void
12014 check_crtc_state(struct drm_device *dev)
12015 {
12016         struct drm_i915_private *dev_priv = dev->dev_private;
12017         struct intel_crtc *crtc;
12018         struct intel_encoder *encoder;
12019         struct intel_crtc_state pipe_config;
12020
12021         for_each_intel_crtc(dev, crtc) {
12022                 bool enabled = false;
12023                 bool active = false;
12024
12025                 memset(&pipe_config, 0, sizeof(pipe_config));
12026
12027                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12028                               crtc->base.base.id);
12029
12030                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12031                      "active crtc, but not enabled in sw tracking\n");
12032
12033                 for_each_intel_encoder(dev, encoder) {
12034                         if (encoder->base.crtc != &crtc->base)
12035                                 continue;
12036                         enabled = true;
12037                         if (encoder->connectors_active)
12038                                 active = true;
12039                 }
12040
12041                 I915_STATE_WARN(active != crtc->active,
12042                      "crtc's computed active state doesn't match tracked active state "
12043                      "(expected %i, found %i)\n", active, crtc->active);
12044                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12045                      "crtc's computed enabled state doesn't match tracked enabled state "
12046                      "(expected %i, found %i)\n", enabled,
12047                                 crtc->base.state->enable);
12048
12049                 active = dev_priv->display.get_pipe_config(crtc,
12050                                                            &pipe_config);
12051
12052                 /* hw state is inconsistent with the pipe quirk */
12053                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12054                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12055                         active = crtc->active;
12056
12057                 for_each_intel_encoder(dev, encoder) {
12058                         enum pipe pipe;
12059                         if (encoder->base.crtc != &crtc->base)
12060                                 continue;
12061                         if (encoder->get_hw_state(encoder, &pipe))
12062                                 encoder->get_config(encoder, &pipe_config);
12063                 }
12064
12065                 I915_STATE_WARN(crtc->active != active,
12066                      "crtc active state doesn't match with hw state "
12067                      "(expected %i, found %i)\n", crtc->active, active);
12068
12069                 if (active &&
12070                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12071                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12072                         intel_dump_pipe_config(crtc, &pipe_config,
12073                                                "[hw state]");
12074                         intel_dump_pipe_config(crtc, crtc->config,
12075                                                "[sw state]");
12076                 }
12077         }
12078 }
12079
12080 static void
12081 check_shared_dpll_state(struct drm_device *dev)
12082 {
12083         struct drm_i915_private *dev_priv = dev->dev_private;
12084         struct intel_crtc *crtc;
12085         struct intel_dpll_hw_state dpll_hw_state;
12086         int i;
12087
12088         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12089                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12090                 int enabled_crtcs = 0, active_crtcs = 0;
12091                 bool active;
12092
12093                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12094
12095                 DRM_DEBUG_KMS("%s\n", pll->name);
12096
12097                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12098
12099                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12100                      "more active pll users than references: %i vs %i\n",
12101                      pll->active, hweight32(pll->config.crtc_mask));
12102                 I915_STATE_WARN(pll->active && !pll->on,
12103                      "pll in active use but not on in sw tracking\n");
12104                 I915_STATE_WARN(pll->on && !pll->active,
12105                      "pll in on but not on in use in sw tracking\n");
12106                 I915_STATE_WARN(pll->on != active,
12107                      "pll on state mismatch (expected %i, found %i)\n",
12108                      pll->on, active);
12109
12110                 for_each_intel_crtc(dev, crtc) {
12111                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12112                                 enabled_crtcs++;
12113                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12114                                 active_crtcs++;
12115                 }
12116                 I915_STATE_WARN(pll->active != active_crtcs,
12117                      "pll active crtcs mismatch (expected %i, found %i)\n",
12118                      pll->active, active_crtcs);
12119                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12120                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12121                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12122
12123                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12124                                        sizeof(dpll_hw_state)),
12125                      "pll hw state mismatch\n");
12126         }
12127 }
12128
12129 void
12130 intel_modeset_check_state(struct drm_device *dev)
12131 {
12132         check_wm_state(dev);
12133         check_connector_state(dev);
12134         check_encoder_state(dev);
12135         check_crtc_state(dev);
12136         check_shared_dpll_state(dev);
12137 }
12138
12139 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12140                                      int dotclock)
12141 {
12142         /*
12143          * FDI already provided one idea for the dotclock.
12144          * Yell if the encoder disagrees.
12145          */
12146         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12147              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12148              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12149 }
12150
12151 static void update_scanline_offset(struct intel_crtc *crtc)
12152 {
12153         struct drm_device *dev = crtc->base.dev;
12154
12155         /*
12156          * The scanline counter increments at the leading edge of hsync.
12157          *
12158          * On most platforms it starts counting from vtotal-1 on the
12159          * first active line. That means the scanline counter value is
12160          * always one less than what we would expect. Ie. just after
12161          * start of vblank, which also occurs at start of hsync (on the
12162          * last active line), the scanline counter will read vblank_start-1.
12163          *
12164          * On gen2 the scanline counter starts counting from 1 instead
12165          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12166          * to keep the value positive), instead of adding one.
12167          *
12168          * On HSW+ the behaviour of the scanline counter depends on the output
12169          * type. For DP ports it behaves like most other platforms, but on HDMI
12170          * there's an extra 1 line difference. So we need to add two instead of
12171          * one to the value.
12172          */
12173         if (IS_GEN2(dev)) {
12174                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12175                 int vtotal;
12176
12177                 vtotal = mode->crtc_vtotal;
12178                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12179                         vtotal /= 2;
12180
12181                 crtc->scanline_offset = vtotal - 1;
12182         } else if (HAS_DDI(dev) &&
12183                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12184                 crtc->scanline_offset = 2;
12185         } else
12186                 crtc->scanline_offset = 1;
12187 }
12188
12189 static struct intel_crtc_state *
12190 intel_modeset_compute_config(struct drm_crtc *crtc,
12191                              struct drm_atomic_state *state)
12192 {
12193         struct intel_crtc_state *pipe_config;
12194         int ret = 0;
12195
12196         ret = drm_atomic_add_affected_connectors(state, crtc);
12197         if (ret)
12198                 return ERR_PTR(ret);
12199
12200         ret = drm_atomic_helper_check_modeset(state->dev, state);
12201         if (ret)
12202                 return ERR_PTR(ret);
12203
12204         /*
12205          * Note this needs changes when we start tracking multiple modes
12206          * and crtcs.  At that point we'll need to compute the whole config
12207          * (i.e. one pipe_config for each crtc) rather than just the one
12208          * for this crtc.
12209          */
12210         pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12211         if (IS_ERR(pipe_config))
12212                 return pipe_config;
12213
12214         if (!pipe_config->base.enable)
12215                 return pipe_config;
12216
12217         ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12218         if (ret)
12219                 return ERR_PTR(ret);
12220
12221         /* Check things that can only be changed through modeset */
12222         if (pipe_config->has_audio !=
12223             to_intel_crtc(crtc)->config->has_audio)
12224                 pipe_config->base.mode_changed = true;
12225
12226         /*
12227          * Note we have an issue here with infoframes: current code
12228          * only updates them on the full mode set path per hw
12229          * requirements.  So here we should be checking for any
12230          * required changes and forcing a mode set.
12231          */
12232
12233         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12234
12235         ret = drm_atomic_helper_check_planes(state->dev, state);
12236         if (ret)
12237                 return ERR_PTR(ret);
12238
12239         return pipe_config;
12240 }
12241
12242 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12243 {
12244         struct drm_device *dev = state->dev;
12245         struct drm_i915_private *dev_priv = to_i915(dev);
12246         unsigned clear_pipes = 0;
12247         struct intel_crtc *intel_crtc;
12248         struct intel_crtc_state *intel_crtc_state;
12249         struct drm_crtc *crtc;
12250         struct drm_crtc_state *crtc_state;
12251         int ret = 0;
12252         int i;
12253
12254         if (!dev_priv->display.crtc_compute_clock)
12255                 return 0;
12256
12257         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12258                 intel_crtc = to_intel_crtc(crtc);
12259                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12260
12261                 if (needs_modeset(crtc_state)) {
12262                         clear_pipes |= 1 << intel_crtc->pipe;
12263                         intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12264                         memset(&intel_crtc_state->dpll_hw_state, 0,
12265                                sizeof(intel_crtc_state->dpll_hw_state));
12266                 }
12267         }
12268
12269         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12270         if (ret)
12271                 goto done;
12272
12273         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12274                 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12275                         continue;
12276
12277                 intel_crtc = to_intel_crtc(crtc);
12278                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12279
12280                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12281                                                            intel_crtc_state);
12282                 if (ret) {
12283                         intel_shared_dpll_abort_config(dev_priv);
12284                         goto done;
12285                 }
12286         }
12287
12288 done:
12289         return ret;
12290 }
12291
12292 /* Code that should eventually be part of atomic_check() */
12293 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12294 {
12295         struct drm_device *dev = state->dev;
12296         int ret;
12297
12298         /*
12299          * See if the config requires any additional preparation, e.g.
12300          * to adjust global state with pipes off.  We need to do this
12301          * here so we can get the modeset_pipe updated config for the new
12302          * mode set on this crtc.  For other crtcs we need to use the
12303          * adjusted_mode bits in the crtc directly.
12304          */
12305         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12306                 ret = valleyview_modeset_global_pipes(state);
12307                 if (ret)
12308                         return ret;
12309         }
12310
12311         ret = __intel_set_mode_setup_plls(state);
12312         if (ret)
12313                 return ret;
12314
12315         return 0;
12316 }
12317
12318 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12319                             struct intel_crtc_state *pipe_config)
12320 {
12321         struct drm_device *dev = modeset_crtc->dev;
12322         struct drm_i915_private *dev_priv = dev->dev_private;
12323         struct drm_atomic_state *state = pipe_config->base.state;
12324         struct drm_crtc *crtc;
12325         struct drm_crtc_state *crtc_state;
12326         int ret = 0;
12327         int i;
12328
12329         ret = __intel_set_mode_checks(state);
12330         if (ret < 0)
12331                 return ret;
12332
12333         ret = drm_atomic_helper_prepare_planes(dev, state);
12334         if (ret)
12335                 return ret;
12336
12337         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12338                 if (!needs_modeset(crtc_state))
12339                         continue;
12340
12341                 if (!crtc_state->enable) {
12342                         intel_crtc_disable(crtc);
12343                 } else if (crtc->state->enable) {
12344                         intel_crtc_disable_planes(crtc);
12345                         dev_priv->display.crtc_disable(crtc);
12346                 }
12347         }
12348
12349         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12350          * to set it here already despite that we pass it down the callchain.
12351          *
12352          * Note we'll need to fix this up when we start tracking multiple
12353          * pipes; here we assume a single modeset_pipe and only track the
12354          * single crtc and mode.
12355          */
12356         if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12357                 modeset_crtc->mode = pipe_config->base.mode;
12358
12359                 /*
12360                  * Calculate and store various constants which
12361                  * are later needed by vblank and swap-completion
12362                  * timestamping. They are derived from true hwmode.
12363                  */
12364                 drm_calc_timestamping_constants(modeset_crtc,
12365                                                 &pipe_config->base.adjusted_mode);
12366         }
12367
12368         /* Only after disabling all output pipelines that will be changed can we
12369          * update the the output configuration. */
12370         intel_modeset_update_state(state);
12371
12372         /* The state has been swaped above, so state actually contains the
12373          * old state now. */
12374
12375         modeset_update_crtc_power_domains(state);
12376
12377         drm_atomic_helper_commit_planes(dev, state);
12378
12379         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12380         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12381                 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12382                         continue;
12383
12384                 update_scanline_offset(to_intel_crtc(crtc));
12385
12386                 dev_priv->display.crtc_enable(crtc);
12387                 intel_crtc_enable_planes(crtc);
12388         }
12389
12390         /* FIXME: add subpixel order */
12391
12392         drm_atomic_helper_cleanup_planes(dev, state);
12393
12394         drm_atomic_state_free(state);
12395
12396         return 0;
12397 }
12398
12399 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12400                                       struct intel_crtc_state *pipe_config)
12401 {
12402         int ret;
12403
12404         ret = __intel_set_mode(crtc, pipe_config);
12405
12406         if (ret == 0)
12407                 intel_modeset_check_state(crtc->dev);
12408
12409         return ret;
12410 }
12411
12412 static int intel_set_mode(struct drm_crtc *crtc,
12413                           struct drm_atomic_state *state)
12414 {
12415         struct intel_crtc_state *pipe_config;
12416         int ret = 0;
12417
12418         pipe_config = intel_modeset_compute_config(crtc, state);
12419         if (IS_ERR(pipe_config)) {
12420                 ret = PTR_ERR(pipe_config);
12421                 goto out;
12422         }
12423
12424         ret = intel_set_mode_with_config(crtc, pipe_config);
12425         if (ret)
12426                 goto out;
12427
12428 out:
12429         return ret;
12430 }
12431
12432 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12433 {
12434         struct drm_device *dev = crtc->dev;
12435         struct drm_atomic_state *state;
12436         struct intel_crtc *intel_crtc;
12437         struct intel_encoder *encoder;
12438         struct intel_connector *connector;
12439         struct drm_connector_state *connector_state;
12440         struct intel_crtc_state *crtc_state;
12441         int ret;
12442
12443         state = drm_atomic_state_alloc(dev);
12444         if (!state) {
12445                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12446                               crtc->base.id);
12447                 return;
12448         }
12449
12450         state->acquire_ctx = dev->mode_config.acquire_ctx;
12451
12452         /* The force restore path in the HW readout code relies on the staged
12453          * config still keeping the user requested config while the actual
12454          * state has been overwritten by the configuration read from HW. We
12455          * need to copy the staged config to the atomic state, otherwise the
12456          * mode set will just reapply the state the HW is already in. */
12457         for_each_intel_encoder(dev, encoder) {
12458                 if (&encoder->new_crtc->base != crtc)
12459                         continue;
12460
12461                 for_each_intel_connector(dev, connector) {
12462                         if (connector->new_encoder != encoder)
12463                                 continue;
12464
12465                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
12466                         if (IS_ERR(connector_state)) {
12467                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12468                                               connector->base.base.id,
12469                                               connector->base.name,
12470                                               PTR_ERR(connector_state));
12471                                 continue;
12472                         }
12473
12474                         connector_state->crtc = crtc;
12475                         connector_state->best_encoder = &encoder->base;
12476                 }
12477         }
12478
12479         for_each_intel_crtc(dev, intel_crtc) {
12480                 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12481                         continue;
12482
12483                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12484                 if (IS_ERR(crtc_state)) {
12485                         DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12486                                       intel_crtc->base.base.id,
12487                                       PTR_ERR(crtc_state));
12488                         continue;
12489                 }
12490
12491                 crtc_state->base.active = crtc_state->base.enable =
12492                         intel_crtc->new_enabled;
12493
12494                 if (&intel_crtc->base == crtc)
12495                         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12496         }
12497
12498         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12499                                         crtc->primary->fb, crtc->x, crtc->y);
12500
12501         ret = intel_set_mode(crtc, state);
12502         if (ret)
12503                 drm_atomic_state_free(state);
12504 }
12505
12506 #undef for_each_intel_crtc_masked
12507
12508 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12509                                         struct drm_mode_set *set)
12510 {
12511         int ro;
12512
12513         for (ro = 0; ro < set->num_connectors; ro++)
12514                 if (set->connectors[ro] == &connector->base)
12515                         return true;
12516
12517         return false;
12518 }
12519
12520 static int
12521 intel_modeset_stage_output_state(struct drm_device *dev,
12522                                  struct drm_mode_set *set,
12523                                  struct drm_atomic_state *state)
12524 {
12525         struct intel_connector *connector;
12526         struct drm_connector *drm_connector;
12527         struct drm_connector_state *connector_state;
12528         struct drm_crtc *crtc;
12529         struct drm_crtc_state *crtc_state;
12530         int i, ret;
12531
12532         /* The upper layers ensure that we either disable a crtc or have a list
12533          * of connectors. For paranoia, double-check this. */
12534         WARN_ON(!set->fb && (set->num_connectors != 0));
12535         WARN_ON(set->fb && (set->num_connectors == 0));
12536
12537         for_each_intel_connector(dev, connector) {
12538                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12539
12540                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12541                         continue;
12542
12543                 connector_state =
12544                         drm_atomic_get_connector_state(state, &connector->base);
12545                 if (IS_ERR(connector_state))
12546                         return PTR_ERR(connector_state);
12547
12548                 if (in_mode_set) {
12549                         int pipe = to_intel_crtc(set->crtc)->pipe;
12550                         connector_state->best_encoder =
12551                                 &intel_find_encoder(connector, pipe)->base;
12552                 }
12553
12554                 if (connector->base.state->crtc != set->crtc)
12555                         continue;
12556
12557                 /* If we disable the crtc, disable all its connectors. Also, if
12558                  * the connector is on the changing crtc but not on the new
12559                  * connector list, disable it. */
12560                 if (!set->fb || !in_mode_set) {
12561                         connector_state->best_encoder = NULL;
12562
12563                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12564                                 connector->base.base.id,
12565                                 connector->base.name);
12566                 }
12567         }
12568         /* connector->new_encoder is now updated for all connectors. */
12569
12570         for_each_connector_in_state(state, drm_connector, connector_state, i) {
12571                 connector = to_intel_connector(drm_connector);
12572
12573                 if (!connector_state->best_encoder) {
12574                         ret = drm_atomic_set_crtc_for_connector(connector_state,
12575                                                                 NULL);
12576                         if (ret)
12577                                 return ret;
12578
12579                         continue;
12580                 }
12581
12582                 if (intel_connector_in_mode_set(connector, set)) {
12583                         struct drm_crtc *crtc = connector->base.state->crtc;
12584
12585                         /* If this connector was in a previous crtc, add it
12586                          * to the state. We might need to disable it. */
12587                         if (crtc) {
12588                                 crtc_state =
12589                                         drm_atomic_get_crtc_state(state, crtc);
12590                                 if (IS_ERR(crtc_state))
12591                                         return PTR_ERR(crtc_state);
12592                         }
12593
12594                         ret = drm_atomic_set_crtc_for_connector(connector_state,
12595                                                                 set->crtc);
12596                         if (ret)
12597                                 return ret;
12598                 }
12599
12600                 /* Make sure the new CRTC will work with the encoder */
12601                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12602                                          connector_state->crtc)) {
12603                         return -EINVAL;
12604                 }
12605
12606                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12607                         connector->base.base.id,
12608                         connector->base.name,
12609                         connector_state->crtc->base.id);
12610
12611                 if (connector_state->best_encoder != &connector->encoder->base)
12612                         connector->encoder =
12613                                 to_intel_encoder(connector_state->best_encoder);
12614         }
12615
12616         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12617                 bool has_connectors;
12618
12619                 ret = drm_atomic_add_affected_connectors(state, crtc);
12620                 if (ret)
12621                         return ret;
12622
12623                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12624                 if (has_connectors != crtc_state->enable)
12625                         crtc_state->enable =
12626                         crtc_state->active = has_connectors;
12627         }
12628
12629         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12630                                               set->fb, set->x, set->y);
12631         if (ret)
12632                 return ret;
12633
12634         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12635         if (IS_ERR(crtc_state))
12636                 return PTR_ERR(crtc_state);
12637
12638         if (set->mode)
12639                 drm_mode_copy(&crtc_state->mode, set->mode);
12640
12641         if (set->num_connectors)
12642                 crtc_state->active = true;
12643
12644         return 0;
12645 }
12646
12647 static bool primary_plane_visible(struct drm_crtc *crtc)
12648 {
12649         struct intel_plane_state *plane_state =
12650                 to_intel_plane_state(crtc->primary->state);
12651
12652         return plane_state->visible;
12653 }
12654
12655 static int intel_crtc_set_config(struct drm_mode_set *set)
12656 {
12657         struct drm_device *dev;
12658         struct drm_atomic_state *state = NULL;
12659         struct intel_crtc_state *pipe_config;
12660         bool primary_plane_was_visible;
12661         int ret;
12662
12663         BUG_ON(!set);
12664         BUG_ON(!set->crtc);
12665         BUG_ON(!set->crtc->helper_private);
12666
12667         /* Enforce sane interface api - has been abused by the fb helper. */
12668         BUG_ON(!set->mode && set->fb);
12669         BUG_ON(set->fb && set->num_connectors == 0);
12670
12671         if (set->fb) {
12672                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12673                                 set->crtc->base.id, set->fb->base.id,
12674                                 (int)set->num_connectors, set->x, set->y);
12675         } else {
12676                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12677         }
12678
12679         dev = set->crtc->dev;
12680
12681         state = drm_atomic_state_alloc(dev);
12682         if (!state)
12683                 return -ENOMEM;
12684
12685         state->acquire_ctx = dev->mode_config.acquire_ctx;
12686
12687         ret = intel_modeset_stage_output_state(dev, set, state);
12688         if (ret)
12689                 goto out;
12690
12691         pipe_config = intel_modeset_compute_config(set->crtc, state);
12692         if (IS_ERR(pipe_config)) {
12693                 ret = PTR_ERR(pipe_config);
12694                 goto out;
12695         }
12696
12697         intel_update_pipe_size(to_intel_crtc(set->crtc));
12698
12699         primary_plane_was_visible = primary_plane_visible(set->crtc);
12700
12701         ret = intel_set_mode_with_config(set->crtc, pipe_config);
12702
12703         if (ret == 0 &&
12704             pipe_config->base.enable &&
12705             pipe_config->base.planes_changed &&
12706             !needs_modeset(&pipe_config->base)) {
12707                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12708
12709                 /*
12710                  * We need to make sure the primary plane is re-enabled if it
12711                  * has previously been turned off.
12712                  */
12713                 if (ret == 0 && !primary_plane_was_visible &&
12714                     primary_plane_visible(set->crtc)) {
12715                         WARN_ON(!intel_crtc->active);
12716                         intel_post_enable_primary(set->crtc);
12717                 }
12718
12719                 /*
12720                  * In the fastboot case this may be our only check of the
12721                  * state after boot.  It would be better to only do it on
12722                  * the first update, but we don't have a nice way of doing that
12723                  * (and really, set_config isn't used much for high freq page
12724                  * flipping, so increasing its cost here shouldn't be a big
12725                  * deal).
12726                  */
12727                 if (i915.fastboot && ret == 0)
12728                         intel_modeset_check_state(set->crtc->dev);
12729         }
12730
12731         if (ret) {
12732                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12733                               set->crtc->base.id, ret);
12734         }
12735
12736 out:
12737         if (ret)
12738                 drm_atomic_state_free(state);
12739         return ret;
12740 }
12741
12742 static const struct drm_crtc_funcs intel_crtc_funcs = {
12743         .gamma_set = intel_crtc_gamma_set,
12744         .set_config = intel_crtc_set_config,
12745         .destroy = intel_crtc_destroy,
12746         .page_flip = intel_crtc_page_flip,
12747         .atomic_duplicate_state = intel_crtc_duplicate_state,
12748         .atomic_destroy_state = intel_crtc_destroy_state,
12749 };
12750
12751 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12752                                       struct intel_shared_dpll *pll,
12753                                       struct intel_dpll_hw_state *hw_state)
12754 {
12755         uint32_t val;
12756
12757         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12758                 return false;
12759
12760         val = I915_READ(PCH_DPLL(pll->id));
12761         hw_state->dpll = val;
12762         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12763         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12764
12765         return val & DPLL_VCO_ENABLE;
12766 }
12767
12768 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12769                                   struct intel_shared_dpll *pll)
12770 {
12771         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12772         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12773 }
12774
12775 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12776                                 struct intel_shared_dpll *pll)
12777 {
12778         /* PCH refclock must be enabled first */
12779         ibx_assert_pch_refclk_enabled(dev_priv);
12780
12781         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12782
12783         /* Wait for the clocks to stabilize. */
12784         POSTING_READ(PCH_DPLL(pll->id));
12785         udelay(150);
12786
12787         /* The pixel multiplier can only be updated once the
12788          * DPLL is enabled and the clocks are stable.
12789          *
12790          * So write it again.
12791          */
12792         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12793         POSTING_READ(PCH_DPLL(pll->id));
12794         udelay(200);
12795 }
12796
12797 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12798                                  struct intel_shared_dpll *pll)
12799 {
12800         struct drm_device *dev = dev_priv->dev;
12801         struct intel_crtc *crtc;
12802
12803         /* Make sure no transcoder isn't still depending on us. */
12804         for_each_intel_crtc(dev, crtc) {
12805                 if (intel_crtc_to_shared_dpll(crtc) == pll)
12806                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12807         }
12808
12809         I915_WRITE(PCH_DPLL(pll->id), 0);
12810         POSTING_READ(PCH_DPLL(pll->id));
12811         udelay(200);
12812 }
12813
12814 static char *ibx_pch_dpll_names[] = {
12815         "PCH DPLL A",
12816         "PCH DPLL B",
12817 };
12818
12819 static void ibx_pch_dpll_init(struct drm_device *dev)
12820 {
12821         struct drm_i915_private *dev_priv = dev->dev_private;
12822         int i;
12823
12824         dev_priv->num_shared_dpll = 2;
12825
12826         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12827                 dev_priv->shared_dplls[i].id = i;
12828                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12829                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12830                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12831                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12832                 dev_priv->shared_dplls[i].get_hw_state =
12833                         ibx_pch_dpll_get_hw_state;
12834         }
12835 }
12836
12837 static void intel_shared_dpll_init(struct drm_device *dev)
12838 {
12839         struct drm_i915_private *dev_priv = dev->dev_private;
12840
12841         if (HAS_DDI(dev))
12842                 intel_ddi_pll_init(dev);
12843         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12844                 ibx_pch_dpll_init(dev);
12845         else
12846                 dev_priv->num_shared_dpll = 0;
12847
12848         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12849 }
12850
12851 /**
12852  * intel_wm_need_update - Check whether watermarks need updating
12853  * @plane: drm plane
12854  * @state: new plane state
12855  *
12856  * Check current plane state versus the new one to determine whether
12857  * watermarks need to be recalculated.
12858  *
12859  * Returns true or false.
12860  */
12861 bool intel_wm_need_update(struct drm_plane *plane,
12862                           struct drm_plane_state *state)
12863 {
12864         /* Update watermarks on tiling changes. */
12865         if (!plane->state->fb || !state->fb ||
12866             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12867             plane->state->rotation != state->rotation)
12868                 return true;
12869
12870         return false;
12871 }
12872
12873 /**
12874  * intel_prepare_plane_fb - Prepare fb for usage on plane
12875  * @plane: drm plane to prepare for
12876  * @fb: framebuffer to prepare for presentation
12877  *
12878  * Prepares a framebuffer for usage on a display plane.  Generally this
12879  * involves pinning the underlying object and updating the frontbuffer tracking
12880  * bits.  Some older platforms need special physical address handling for
12881  * cursor planes.
12882  *
12883  * Returns 0 on success, negative error code on failure.
12884  */
12885 int
12886 intel_prepare_plane_fb(struct drm_plane *plane,
12887                        struct drm_framebuffer *fb,
12888                        const struct drm_plane_state *new_state)
12889 {
12890         struct drm_device *dev = plane->dev;
12891         struct intel_plane *intel_plane = to_intel_plane(plane);
12892         enum pipe pipe = intel_plane->pipe;
12893         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12894         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12895         unsigned frontbuffer_bits = 0;
12896         int ret = 0;
12897
12898         if (!obj)
12899                 return 0;
12900
12901         switch (plane->type) {
12902         case DRM_PLANE_TYPE_PRIMARY:
12903                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12904                 break;
12905         case DRM_PLANE_TYPE_CURSOR:
12906                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12907                 break;
12908         case DRM_PLANE_TYPE_OVERLAY:
12909                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12910                 break;
12911         }
12912
12913         mutex_lock(&dev->struct_mutex);
12914
12915         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12916             INTEL_INFO(dev)->cursor_needs_physical) {
12917                 int align = IS_I830(dev) ? 16 * 1024 : 256;
12918                 ret = i915_gem_object_attach_phys(obj, align);
12919                 if (ret)
12920                         DRM_DEBUG_KMS("failed to attach phys object\n");
12921         } else {
12922                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12923         }
12924
12925         if (ret == 0)
12926                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12927
12928         mutex_unlock(&dev->struct_mutex);
12929
12930         return ret;
12931 }
12932
12933 /**
12934  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12935  * @plane: drm plane to clean up for
12936  * @fb: old framebuffer that was on plane
12937  *
12938  * Cleans up a framebuffer that has just been removed from a plane.
12939  */
12940 void
12941 intel_cleanup_plane_fb(struct drm_plane *plane,
12942                        struct drm_framebuffer *fb,
12943                        const struct drm_plane_state *old_state)
12944 {
12945         struct drm_device *dev = plane->dev;
12946         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12947
12948         if (WARN_ON(!obj))
12949                 return;
12950
12951         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12952             !INTEL_INFO(dev)->cursor_needs_physical) {
12953                 mutex_lock(&dev->struct_mutex);
12954                 intel_unpin_fb_obj(fb, old_state);
12955                 mutex_unlock(&dev->struct_mutex);
12956         }
12957 }
12958
12959 int
12960 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12961 {
12962         int max_scale;
12963         struct drm_device *dev;
12964         struct drm_i915_private *dev_priv;
12965         int crtc_clock, cdclk;
12966
12967         if (!intel_crtc || !crtc_state)
12968                 return DRM_PLANE_HELPER_NO_SCALING;
12969
12970         dev = intel_crtc->base.dev;
12971         dev_priv = dev->dev_private;
12972         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12973         cdclk = dev_priv->display.get_display_clock_speed(dev);
12974
12975         if (!crtc_clock || !cdclk)
12976                 return DRM_PLANE_HELPER_NO_SCALING;
12977
12978         /*
12979          * skl max scale is lower of:
12980          *    close to 3 but not 3, -1 is for that purpose
12981          *            or
12982          *    cdclk/crtc_clock
12983          */
12984         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
12985
12986         return max_scale;
12987 }
12988
12989 static int
12990 intel_check_primary_plane(struct drm_plane *plane,
12991                           struct intel_plane_state *state)
12992 {
12993         struct drm_device *dev = plane->dev;
12994         struct drm_i915_private *dev_priv = dev->dev_private;
12995         struct drm_crtc *crtc = state->base.crtc;
12996         struct intel_crtc *intel_crtc;
12997         struct intel_crtc_state *crtc_state;
12998         struct drm_framebuffer *fb = state->base.fb;
12999         struct drm_rect *dest = &state->dst;
13000         struct drm_rect *src = &state->src;
13001         const struct drm_rect *clip = &state->clip;
13002         bool can_position = false;
13003         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13004         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13005         int ret;
13006
13007         crtc = crtc ? crtc : plane->crtc;
13008         intel_crtc = to_intel_crtc(crtc);
13009         crtc_state = state->base.state ?
13010                 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13011
13012         if (INTEL_INFO(dev)->gen >= 9) {
13013                 min_scale = 1;
13014                 max_scale = skl_max_scale(intel_crtc, crtc_state);
13015                 can_position = true;
13016         }
13017
13018         ret = drm_plane_helper_check_update(plane, crtc, fb,
13019                                             src, dest, clip,
13020                                             min_scale,
13021                                             max_scale,
13022                                             can_position, true,
13023                                             &state->visible);
13024         if (ret)
13025                 return ret;
13026
13027         if (intel_crtc->active) {
13028                 struct intel_plane_state *old_state =
13029                         to_intel_plane_state(plane->state);
13030
13031                 intel_crtc->atomic.wait_for_flips = true;
13032
13033                 /*
13034                  * FBC does not work on some platforms for rotated
13035                  * planes, so disable it when rotation is not 0 and
13036                  * update it when rotation is set back to 0.
13037                  *
13038                  * FIXME: This is redundant with the fbc update done in
13039                  * the primary plane enable function except that that
13040                  * one is done too late. We eventually need to unify
13041                  * this.
13042                  */
13043                 if (state->visible &&
13044                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13045                     dev_priv->fbc.crtc == intel_crtc &&
13046                     state->base.rotation != BIT(DRM_ROTATE_0)) {
13047                         intel_crtc->atomic.disable_fbc = true;
13048                 }
13049
13050                 if (state->visible && !old_state->visible) {
13051                         /*
13052                          * BDW signals flip done immediately if the plane
13053                          * is disabled, even if the plane enable is already
13054                          * armed to occur at the next vblank :(
13055                          */
13056                         if (IS_BROADWELL(dev))
13057                                 intel_crtc->atomic.wait_vblank = true;
13058                 }
13059
13060                 intel_crtc->atomic.fb_bits |=
13061                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13062
13063                 intel_crtc->atomic.update_fbc = true;
13064
13065                 if (intel_wm_need_update(plane, &state->base))
13066                         intel_crtc->atomic.update_wm = true;
13067         }
13068
13069         if (INTEL_INFO(dev)->gen >= 9) {
13070                 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13071                         to_intel_plane(plane), state, 0);
13072                 if (ret)
13073                         return ret;
13074         }
13075
13076         return 0;
13077 }
13078
13079 static void
13080 intel_commit_primary_plane(struct drm_plane *plane,
13081                            struct intel_plane_state *state)
13082 {
13083         struct drm_crtc *crtc = state->base.crtc;
13084         struct drm_framebuffer *fb = state->base.fb;
13085         struct drm_device *dev = plane->dev;
13086         struct drm_i915_private *dev_priv = dev->dev_private;
13087         struct intel_crtc *intel_crtc;
13088         struct drm_rect *src = &state->src;
13089
13090         crtc = crtc ? crtc : plane->crtc;
13091         intel_crtc = to_intel_crtc(crtc);
13092
13093         plane->fb = fb;
13094         crtc->x = src->x1 >> 16;
13095         crtc->y = src->y1 >> 16;
13096
13097         if (intel_crtc->active) {
13098                 if (state->visible)
13099                         /* FIXME: kill this fastboot hack */
13100                         intel_update_pipe_size(intel_crtc);
13101
13102                 dev_priv->display.update_primary_plane(crtc, plane->fb,
13103                                                        crtc->x, crtc->y);
13104         }
13105 }
13106
13107 static void
13108 intel_disable_primary_plane(struct drm_plane *plane,
13109                             struct drm_crtc *crtc,
13110                             bool force)
13111 {
13112         struct drm_device *dev = plane->dev;
13113         struct drm_i915_private *dev_priv = dev->dev_private;
13114
13115         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13116 }
13117
13118 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13119 {
13120         struct drm_device *dev = crtc->dev;
13121         struct drm_i915_private *dev_priv = dev->dev_private;
13122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13123         struct intel_plane *intel_plane;
13124         struct drm_plane *p;
13125         unsigned fb_bits = 0;
13126
13127         /* Track fb's for any planes being disabled */
13128         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13129                 intel_plane = to_intel_plane(p);
13130
13131                 if (intel_crtc->atomic.disabled_planes &
13132                     (1 << drm_plane_index(p))) {
13133                         switch (p->type) {
13134                         case DRM_PLANE_TYPE_PRIMARY:
13135                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13136                                 break;
13137                         case DRM_PLANE_TYPE_CURSOR:
13138                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13139                                 break;
13140                         case DRM_PLANE_TYPE_OVERLAY:
13141                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13142                                 break;
13143                         }
13144
13145                         mutex_lock(&dev->struct_mutex);
13146                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13147                         mutex_unlock(&dev->struct_mutex);
13148                 }
13149         }
13150
13151         if (intel_crtc->atomic.wait_for_flips)
13152                 intel_crtc_wait_for_pending_flips(crtc);
13153
13154         if (intel_crtc->atomic.disable_fbc)
13155                 intel_fbc_disable(dev);
13156
13157         if (intel_crtc->atomic.pre_disable_primary)
13158                 intel_pre_disable_primary(crtc);
13159
13160         if (intel_crtc->atomic.update_wm)
13161                 intel_update_watermarks(crtc);
13162
13163         intel_runtime_pm_get(dev_priv);
13164
13165         /* Perform vblank evasion around commit operation */
13166         if (intel_crtc->active)
13167                 intel_crtc->atomic.evade =
13168                         intel_pipe_update_start(intel_crtc,
13169                                                 &intel_crtc->atomic.start_vbl_count);
13170 }
13171
13172 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13173 {
13174         struct drm_device *dev = crtc->dev;
13175         struct drm_i915_private *dev_priv = dev->dev_private;
13176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13177         struct drm_plane *p;
13178
13179         if (intel_crtc->atomic.evade)
13180                 intel_pipe_update_end(intel_crtc,
13181                                       intel_crtc->atomic.start_vbl_count);
13182
13183         intel_runtime_pm_put(dev_priv);
13184
13185         if (intel_crtc->atomic.wait_vblank)
13186                 intel_wait_for_vblank(dev, intel_crtc->pipe);
13187
13188         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13189
13190         if (intel_crtc->atomic.update_fbc) {
13191                 mutex_lock(&dev->struct_mutex);
13192                 intel_fbc_update(dev);
13193                 mutex_unlock(&dev->struct_mutex);
13194         }
13195
13196         if (intel_crtc->atomic.post_enable_primary)
13197                 intel_post_enable_primary(crtc);
13198
13199         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13200                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13201                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13202                                                        false, false);
13203
13204         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13205 }
13206
13207 /**
13208  * intel_plane_destroy - destroy a plane
13209  * @plane: plane to destroy
13210  *
13211  * Common destruction function for all types of planes (primary, cursor,
13212  * sprite).
13213  */
13214 void intel_plane_destroy(struct drm_plane *plane)
13215 {
13216         struct intel_plane *intel_plane = to_intel_plane(plane);
13217         drm_plane_cleanup(plane);
13218         kfree(intel_plane);
13219 }
13220
13221 const struct drm_plane_funcs intel_plane_funcs = {
13222         .update_plane = drm_atomic_helper_update_plane,
13223         .disable_plane = drm_atomic_helper_disable_plane,
13224         .destroy = intel_plane_destroy,
13225         .set_property = drm_atomic_helper_plane_set_property,
13226         .atomic_get_property = intel_plane_atomic_get_property,
13227         .atomic_set_property = intel_plane_atomic_set_property,
13228         .atomic_duplicate_state = intel_plane_duplicate_state,
13229         .atomic_destroy_state = intel_plane_destroy_state,
13230
13231 };
13232
13233 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13234                                                     int pipe)
13235 {
13236         struct intel_plane *primary;
13237         struct intel_plane_state *state;
13238         const uint32_t *intel_primary_formats;
13239         int num_formats;
13240
13241         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13242         if (primary == NULL)
13243                 return NULL;
13244
13245         state = intel_create_plane_state(&primary->base);
13246         if (!state) {
13247                 kfree(primary);
13248                 return NULL;
13249         }
13250         primary->base.state = &state->base;
13251
13252         primary->can_scale = false;
13253         primary->max_downscale = 1;
13254         if (INTEL_INFO(dev)->gen >= 9) {
13255                 primary->can_scale = true;
13256                 state->scaler_id = -1;
13257         }
13258         primary->pipe = pipe;
13259         primary->plane = pipe;
13260         primary->check_plane = intel_check_primary_plane;
13261         primary->commit_plane = intel_commit_primary_plane;
13262         primary->disable_plane = intel_disable_primary_plane;
13263         primary->ckey.flags = I915_SET_COLORKEY_NONE;
13264         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13265                 primary->plane = !pipe;
13266
13267         if (INTEL_INFO(dev)->gen <= 3) {
13268                 intel_primary_formats = i8xx_primary_formats;
13269                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13270         } else {
13271                 intel_primary_formats = i965_primary_formats;
13272                 num_formats = ARRAY_SIZE(i965_primary_formats);
13273         }
13274
13275         drm_universal_plane_init(dev, &primary->base, 0,
13276                                  &intel_plane_funcs,
13277                                  intel_primary_formats, num_formats,
13278                                  DRM_PLANE_TYPE_PRIMARY);
13279
13280         if (INTEL_INFO(dev)->gen >= 4)
13281                 intel_create_rotation_property(dev, primary);
13282
13283         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13284
13285         return &primary->base;
13286 }
13287
13288 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13289 {
13290         if (!dev->mode_config.rotation_property) {
13291                 unsigned long flags = BIT(DRM_ROTATE_0) |
13292                         BIT(DRM_ROTATE_180);
13293
13294                 if (INTEL_INFO(dev)->gen >= 9)
13295                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13296
13297                 dev->mode_config.rotation_property =
13298                         drm_mode_create_rotation_property(dev, flags);
13299         }
13300         if (dev->mode_config.rotation_property)
13301                 drm_object_attach_property(&plane->base.base,
13302                                 dev->mode_config.rotation_property,
13303                                 plane->base.state->rotation);
13304 }
13305
13306 static int
13307 intel_check_cursor_plane(struct drm_plane *plane,
13308                          struct intel_plane_state *state)
13309 {
13310         struct drm_crtc *crtc = state->base.crtc;
13311         struct drm_device *dev = plane->dev;
13312         struct drm_framebuffer *fb = state->base.fb;
13313         struct drm_rect *dest = &state->dst;
13314         struct drm_rect *src = &state->src;
13315         const struct drm_rect *clip = &state->clip;
13316         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13317         struct intel_crtc *intel_crtc;
13318         unsigned stride;
13319         int ret;
13320
13321         crtc = crtc ? crtc : plane->crtc;
13322         intel_crtc = to_intel_crtc(crtc);
13323
13324         ret = drm_plane_helper_check_update(plane, crtc, fb,
13325                                             src, dest, clip,
13326                                             DRM_PLANE_HELPER_NO_SCALING,
13327                                             DRM_PLANE_HELPER_NO_SCALING,
13328                                             true, true, &state->visible);
13329         if (ret)
13330                 return ret;
13331
13332
13333         /* if we want to turn off the cursor ignore width and height */
13334         if (!obj)
13335                 goto finish;
13336
13337         /* Check for which cursor types we support */
13338         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13339                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13340                           state->base.crtc_w, state->base.crtc_h);
13341                 return -EINVAL;
13342         }
13343
13344         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13345         if (obj->base.size < stride * state->base.crtc_h) {
13346                 DRM_DEBUG_KMS("buffer is too small\n");
13347                 return -ENOMEM;
13348         }
13349
13350         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13351                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13352                 ret = -EINVAL;
13353         }
13354
13355 finish:
13356         if (intel_crtc->active) {
13357                 if (plane->state->crtc_w != state->base.crtc_w)
13358                         intel_crtc->atomic.update_wm = true;
13359
13360                 intel_crtc->atomic.fb_bits |=
13361                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13362         }
13363
13364         return ret;
13365 }
13366
13367 static void
13368 intel_disable_cursor_plane(struct drm_plane *plane,
13369                            struct drm_crtc *crtc,
13370                            bool force)
13371 {
13372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13373
13374         if (!force) {
13375                 plane->fb = NULL;
13376                 intel_crtc->cursor_bo = NULL;
13377                 intel_crtc->cursor_addr = 0;
13378         }
13379
13380         intel_crtc_update_cursor(crtc, false);
13381 }
13382
13383 static void
13384 intel_commit_cursor_plane(struct drm_plane *plane,
13385                           struct intel_plane_state *state)
13386 {
13387         struct drm_crtc *crtc = state->base.crtc;
13388         struct drm_device *dev = plane->dev;
13389         struct intel_crtc *intel_crtc;
13390         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13391         uint32_t addr;
13392
13393         crtc = crtc ? crtc : plane->crtc;
13394         intel_crtc = to_intel_crtc(crtc);
13395
13396         plane->fb = state->base.fb;
13397         crtc->cursor_x = state->base.crtc_x;
13398         crtc->cursor_y = state->base.crtc_y;
13399
13400         if (intel_crtc->cursor_bo == obj)
13401                 goto update;
13402
13403         if (!obj)
13404                 addr = 0;
13405         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13406                 addr = i915_gem_obj_ggtt_offset(obj);
13407         else
13408                 addr = obj->phys_handle->busaddr;
13409
13410         intel_crtc->cursor_addr = addr;
13411         intel_crtc->cursor_bo = obj;
13412 update:
13413
13414         if (intel_crtc->active)
13415                 intel_crtc_update_cursor(crtc, state->visible);
13416 }
13417
13418 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13419                                                    int pipe)
13420 {
13421         struct intel_plane *cursor;
13422         struct intel_plane_state *state;
13423
13424         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13425         if (cursor == NULL)
13426                 return NULL;
13427
13428         state = intel_create_plane_state(&cursor->base);
13429         if (!state) {
13430                 kfree(cursor);
13431                 return NULL;
13432         }
13433         cursor->base.state = &state->base;
13434
13435         cursor->can_scale = false;
13436         cursor->max_downscale = 1;
13437         cursor->pipe = pipe;
13438         cursor->plane = pipe;
13439         cursor->check_plane = intel_check_cursor_plane;
13440         cursor->commit_plane = intel_commit_cursor_plane;
13441         cursor->disable_plane = intel_disable_cursor_plane;
13442
13443         drm_universal_plane_init(dev, &cursor->base, 0,
13444                                  &intel_plane_funcs,
13445                                  intel_cursor_formats,
13446                                  ARRAY_SIZE(intel_cursor_formats),
13447                                  DRM_PLANE_TYPE_CURSOR);
13448
13449         if (INTEL_INFO(dev)->gen >= 4) {
13450                 if (!dev->mode_config.rotation_property)
13451                         dev->mode_config.rotation_property =
13452                                 drm_mode_create_rotation_property(dev,
13453                                                         BIT(DRM_ROTATE_0) |
13454                                                         BIT(DRM_ROTATE_180));
13455                 if (dev->mode_config.rotation_property)
13456                         drm_object_attach_property(&cursor->base.base,
13457                                 dev->mode_config.rotation_property,
13458                                 state->base.rotation);
13459         }
13460
13461         if (INTEL_INFO(dev)->gen >=9)
13462                 state->scaler_id = -1;
13463
13464         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13465
13466         return &cursor->base;
13467 }
13468
13469 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13470         struct intel_crtc_state *crtc_state)
13471 {
13472         int i;
13473         struct intel_scaler *intel_scaler;
13474         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13475
13476         for (i = 0; i < intel_crtc->num_scalers; i++) {
13477                 intel_scaler = &scaler_state->scalers[i];
13478                 intel_scaler->in_use = 0;
13479                 intel_scaler->id = i;
13480
13481                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13482         }
13483
13484         scaler_state->scaler_id = -1;
13485 }
13486
13487 static void intel_crtc_init(struct drm_device *dev, int pipe)
13488 {
13489         struct drm_i915_private *dev_priv = dev->dev_private;
13490         struct intel_crtc *intel_crtc;
13491         struct intel_crtc_state *crtc_state = NULL;
13492         struct drm_plane *primary = NULL;
13493         struct drm_plane *cursor = NULL;
13494         int i, ret;
13495
13496         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13497         if (intel_crtc == NULL)
13498                 return;
13499
13500         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13501         if (!crtc_state)
13502                 goto fail;
13503         intel_crtc->config = crtc_state;
13504         intel_crtc->base.state = &crtc_state->base;
13505         crtc_state->base.crtc = &intel_crtc->base;
13506
13507         /* initialize shared scalers */
13508         if (INTEL_INFO(dev)->gen >= 9) {
13509                 if (pipe == PIPE_C)
13510                         intel_crtc->num_scalers = 1;
13511                 else
13512                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13513
13514                 skl_init_scalers(dev, intel_crtc, crtc_state);
13515         }
13516
13517         primary = intel_primary_plane_create(dev, pipe);
13518         if (!primary)
13519                 goto fail;
13520
13521         cursor = intel_cursor_plane_create(dev, pipe);
13522         if (!cursor)
13523                 goto fail;
13524
13525         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13526                                         cursor, &intel_crtc_funcs);
13527         if (ret)
13528                 goto fail;
13529
13530         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13531         for (i = 0; i < 256; i++) {
13532                 intel_crtc->lut_r[i] = i;
13533                 intel_crtc->lut_g[i] = i;
13534                 intel_crtc->lut_b[i] = i;
13535         }
13536
13537         /*
13538          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13539          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13540          */
13541         intel_crtc->pipe = pipe;
13542         intel_crtc->plane = pipe;
13543         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13544                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13545                 intel_crtc->plane = !pipe;
13546         }
13547
13548         intel_crtc->cursor_base = ~0;
13549         intel_crtc->cursor_cntl = ~0;
13550         intel_crtc->cursor_size = ~0;
13551
13552         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13553                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13554         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13555         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13556
13557         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13558
13559         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13560         return;
13561
13562 fail:
13563         if (primary)
13564                 drm_plane_cleanup(primary);
13565         if (cursor)
13566                 drm_plane_cleanup(cursor);
13567         kfree(crtc_state);
13568         kfree(intel_crtc);
13569 }
13570
13571 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13572 {
13573         struct drm_encoder *encoder = connector->base.encoder;
13574         struct drm_device *dev = connector->base.dev;
13575
13576         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13577
13578         if (!encoder || WARN_ON(!encoder->crtc))
13579                 return INVALID_PIPE;
13580
13581         return to_intel_crtc(encoder->crtc)->pipe;
13582 }
13583
13584 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13585                                 struct drm_file *file)
13586 {
13587         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13588         struct drm_crtc *drmmode_crtc;
13589         struct intel_crtc *crtc;
13590
13591         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13592
13593         if (!drmmode_crtc) {
13594                 DRM_ERROR("no such CRTC id\n");
13595                 return -ENOENT;
13596         }
13597
13598         crtc = to_intel_crtc(drmmode_crtc);
13599         pipe_from_crtc_id->pipe = crtc->pipe;
13600
13601         return 0;
13602 }
13603
13604 static int intel_encoder_clones(struct intel_encoder *encoder)
13605 {
13606         struct drm_device *dev = encoder->base.dev;
13607         struct intel_encoder *source_encoder;
13608         int index_mask = 0;
13609         int entry = 0;
13610
13611         for_each_intel_encoder(dev, source_encoder) {
13612                 if (encoders_cloneable(encoder, source_encoder))
13613                         index_mask |= (1 << entry);
13614
13615                 entry++;
13616         }
13617
13618         return index_mask;
13619 }
13620
13621 static bool has_edp_a(struct drm_device *dev)
13622 {
13623         struct drm_i915_private *dev_priv = dev->dev_private;
13624
13625         if (!IS_MOBILE(dev))
13626                 return false;
13627
13628         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13629                 return false;
13630
13631         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13632                 return false;
13633
13634         return true;
13635 }
13636
13637 static bool intel_crt_present(struct drm_device *dev)
13638 {
13639         struct drm_i915_private *dev_priv = dev->dev_private;
13640
13641         if (INTEL_INFO(dev)->gen >= 9)
13642                 return false;
13643
13644         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13645                 return false;
13646
13647         if (IS_CHERRYVIEW(dev))
13648                 return false;
13649
13650         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13651                 return false;
13652
13653         return true;
13654 }
13655
13656 static void intel_setup_outputs(struct drm_device *dev)
13657 {
13658         struct drm_i915_private *dev_priv = dev->dev_private;
13659         struct intel_encoder *encoder;
13660         bool dpd_is_edp = false;
13661
13662         intel_lvds_init(dev);
13663
13664         if (intel_crt_present(dev))
13665                 intel_crt_init(dev);
13666
13667         if (IS_BROXTON(dev)) {
13668                 /*
13669                  * FIXME: Broxton doesn't support port detection via the
13670                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13671                  * detect the ports.
13672                  */
13673                 intel_ddi_init(dev, PORT_A);
13674                 intel_ddi_init(dev, PORT_B);
13675                 intel_ddi_init(dev, PORT_C);
13676         } else if (HAS_DDI(dev)) {
13677                 int found;
13678
13679                 /*
13680                  * Haswell uses DDI functions to detect digital outputs.
13681                  * On SKL pre-D0 the strap isn't connected, so we assume
13682                  * it's there.
13683                  */
13684                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13685                 /* WaIgnoreDDIAStrap: skl */
13686                 if (found ||
13687                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13688                         intel_ddi_init(dev, PORT_A);
13689
13690                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13691                  * register */
13692                 found = I915_READ(SFUSE_STRAP);
13693
13694                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13695                         intel_ddi_init(dev, PORT_B);
13696                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13697                         intel_ddi_init(dev, PORT_C);
13698                 if (found & SFUSE_STRAP_DDID_DETECTED)
13699                         intel_ddi_init(dev, PORT_D);
13700         } else if (HAS_PCH_SPLIT(dev)) {
13701                 int found;
13702                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13703
13704                 if (has_edp_a(dev))
13705                         intel_dp_init(dev, DP_A, PORT_A);
13706
13707                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13708                         /* PCH SDVOB multiplex with HDMIB */
13709                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13710                         if (!found)
13711                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13712                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13713                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13714                 }
13715
13716                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13717                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13718
13719                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13720                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13721
13722                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13723                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13724
13725                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13726                         intel_dp_init(dev, PCH_DP_D, PORT_D);
13727         } else if (IS_VALLEYVIEW(dev)) {
13728                 /*
13729                  * The DP_DETECTED bit is the latched state of the DDC
13730                  * SDA pin at boot. However since eDP doesn't require DDC
13731                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13732                  * eDP ports may have been muxed to an alternate function.
13733                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13734                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13735                  * detect eDP ports.
13736                  */
13737                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13738                     !intel_dp_is_edp(dev, PORT_B))
13739                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13740                                         PORT_B);
13741                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13742                     intel_dp_is_edp(dev, PORT_B))
13743                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13744
13745                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13746                     !intel_dp_is_edp(dev, PORT_C))
13747                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13748                                         PORT_C);
13749                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13750                     intel_dp_is_edp(dev, PORT_C))
13751                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13752
13753                 if (IS_CHERRYVIEW(dev)) {
13754                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13755                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13756                                                 PORT_D);
13757                         /* eDP not supported on port D, so don't check VBT */
13758                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13759                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13760                 }
13761
13762                 intel_dsi_init(dev);
13763         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13764                 bool found = false;
13765
13766                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13767                         DRM_DEBUG_KMS("probing SDVOB\n");
13768                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13769                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13770                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13771                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13772                         }
13773
13774                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
13775                                 intel_dp_init(dev, DP_B, PORT_B);
13776                 }
13777
13778                 /* Before G4X SDVOC doesn't have its own detect register */
13779
13780                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13781                         DRM_DEBUG_KMS("probing SDVOC\n");
13782                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13783                 }
13784
13785                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13786
13787                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13788                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13789                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13790                         }
13791                         if (SUPPORTS_INTEGRATED_DP(dev))
13792                                 intel_dp_init(dev, DP_C, PORT_C);
13793                 }
13794
13795                 if (SUPPORTS_INTEGRATED_DP(dev) &&
13796                     (I915_READ(DP_D) & DP_DETECTED))
13797                         intel_dp_init(dev, DP_D, PORT_D);
13798         } else if (IS_GEN2(dev))
13799                 intel_dvo_init(dev);
13800
13801         if (SUPPORTS_TV(dev))
13802                 intel_tv_init(dev);
13803
13804         intel_psr_init(dev);
13805
13806         for_each_intel_encoder(dev, encoder) {
13807                 encoder->base.possible_crtcs = encoder->crtc_mask;
13808                 encoder->base.possible_clones =
13809                         intel_encoder_clones(encoder);
13810         }
13811
13812         intel_init_pch_refclk(dev);
13813
13814         drm_helper_move_panel_connectors_to_head(dev);
13815 }
13816
13817 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13818 {
13819         struct drm_device *dev = fb->dev;
13820         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13821
13822         drm_framebuffer_cleanup(fb);
13823         mutex_lock(&dev->struct_mutex);
13824         WARN_ON(!intel_fb->obj->framebuffer_references--);
13825         drm_gem_object_unreference(&intel_fb->obj->base);
13826         mutex_unlock(&dev->struct_mutex);
13827         kfree(intel_fb);
13828 }
13829
13830 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13831                                                 struct drm_file *file,
13832                                                 unsigned int *handle)
13833 {
13834         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13835         struct drm_i915_gem_object *obj = intel_fb->obj;
13836
13837         return drm_gem_handle_create(file, &obj->base, handle);
13838 }
13839
13840 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13841         .destroy = intel_user_framebuffer_destroy,
13842         .create_handle = intel_user_framebuffer_create_handle,
13843 };
13844
13845 static
13846 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13847                          uint32_t pixel_format)
13848 {
13849         u32 gen = INTEL_INFO(dev)->gen;
13850
13851         if (gen >= 9) {
13852                 /* "The stride in bytes must not exceed the of the size of 8K
13853                  *  pixels and 32K bytes."
13854                  */
13855                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13856         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13857                 return 32*1024;
13858         } else if (gen >= 4) {
13859                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13860                         return 16*1024;
13861                 else
13862                         return 32*1024;
13863         } else if (gen >= 3) {
13864                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13865                         return 8*1024;
13866                 else
13867                         return 16*1024;
13868         } else {
13869                 /* XXX DSPC is limited to 4k tiled */
13870                 return 8*1024;
13871         }
13872 }
13873
13874 static int intel_framebuffer_init(struct drm_device *dev,
13875                                   struct intel_framebuffer *intel_fb,
13876                                   struct drm_mode_fb_cmd2 *mode_cmd,
13877                                   struct drm_i915_gem_object *obj)
13878 {
13879         unsigned int aligned_height;
13880         int ret;
13881         u32 pitch_limit, stride_alignment;
13882
13883         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13884
13885         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13886                 /* Enforce that fb modifier and tiling mode match, but only for
13887                  * X-tiled. This is needed for FBC. */
13888                 if (!!(obj->tiling_mode == I915_TILING_X) !=
13889                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13890                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13891                         return -EINVAL;
13892                 }
13893         } else {
13894                 if (obj->tiling_mode == I915_TILING_X)
13895                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13896                 else if (obj->tiling_mode == I915_TILING_Y) {
13897                         DRM_DEBUG("No Y tiling for legacy addfb\n");
13898                         return -EINVAL;
13899                 }
13900         }
13901
13902         /* Passed in modifier sanity checking. */
13903         switch (mode_cmd->modifier[0]) {
13904         case I915_FORMAT_MOD_Y_TILED:
13905         case I915_FORMAT_MOD_Yf_TILED:
13906                 if (INTEL_INFO(dev)->gen < 9) {
13907                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13908                                   mode_cmd->modifier[0]);
13909                         return -EINVAL;
13910                 }
13911         case DRM_FORMAT_MOD_NONE:
13912         case I915_FORMAT_MOD_X_TILED:
13913                 break;
13914         default:
13915                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13916                           mode_cmd->modifier[0]);
13917                 return -EINVAL;
13918         }
13919
13920         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13921                                                      mode_cmd->pixel_format);
13922         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13923                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13924                           mode_cmd->pitches[0], stride_alignment);
13925                 return -EINVAL;
13926         }
13927
13928         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13929                                            mode_cmd->pixel_format);
13930         if (mode_cmd->pitches[0] > pitch_limit) {
13931                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13932                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13933                           "tiled" : "linear",
13934                           mode_cmd->pitches[0], pitch_limit);
13935                 return -EINVAL;
13936         }
13937
13938         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13939             mode_cmd->pitches[0] != obj->stride) {
13940                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13941                           mode_cmd->pitches[0], obj->stride);
13942                 return -EINVAL;
13943         }
13944
13945         /* Reject formats not supported by any plane early. */
13946         switch (mode_cmd->pixel_format) {
13947         case DRM_FORMAT_C8:
13948         case DRM_FORMAT_RGB565:
13949         case DRM_FORMAT_XRGB8888:
13950         case DRM_FORMAT_ARGB8888:
13951                 break;
13952         case DRM_FORMAT_XRGB1555:
13953         case DRM_FORMAT_ARGB1555:
13954                 if (INTEL_INFO(dev)->gen > 3) {
13955                         DRM_DEBUG("unsupported pixel format: %s\n",
13956                                   drm_get_format_name(mode_cmd->pixel_format));
13957                         return -EINVAL;
13958                 }
13959                 break;
13960         case DRM_FORMAT_XBGR8888:
13961         case DRM_FORMAT_ABGR8888:
13962         case DRM_FORMAT_XRGB2101010:
13963         case DRM_FORMAT_ARGB2101010:
13964         case DRM_FORMAT_XBGR2101010:
13965         case DRM_FORMAT_ABGR2101010:
13966                 if (INTEL_INFO(dev)->gen < 4) {
13967                         DRM_DEBUG("unsupported pixel format: %s\n",
13968                                   drm_get_format_name(mode_cmd->pixel_format));
13969                         return -EINVAL;
13970                 }
13971                 break;
13972         case DRM_FORMAT_YUYV:
13973         case DRM_FORMAT_UYVY:
13974         case DRM_FORMAT_YVYU:
13975         case DRM_FORMAT_VYUY:
13976                 if (INTEL_INFO(dev)->gen < 5) {
13977                         DRM_DEBUG("unsupported pixel format: %s\n",
13978                                   drm_get_format_name(mode_cmd->pixel_format));
13979                         return -EINVAL;
13980                 }
13981                 break;
13982         default:
13983                 DRM_DEBUG("unsupported pixel format: %s\n",
13984                           drm_get_format_name(mode_cmd->pixel_format));
13985                 return -EINVAL;
13986         }
13987
13988         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13989         if (mode_cmd->offsets[0] != 0)
13990                 return -EINVAL;
13991
13992         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13993                                                mode_cmd->pixel_format,
13994                                                mode_cmd->modifier[0]);
13995         /* FIXME drm helper for size checks (especially planar formats)? */
13996         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13997                 return -EINVAL;
13998
13999         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14000         intel_fb->obj = obj;
14001         intel_fb->obj->framebuffer_references++;
14002
14003         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14004         if (ret) {
14005                 DRM_ERROR("framebuffer init failed %d\n", ret);
14006                 return ret;
14007         }
14008
14009         return 0;
14010 }
14011
14012 static struct drm_framebuffer *
14013 intel_user_framebuffer_create(struct drm_device *dev,
14014                               struct drm_file *filp,
14015                               struct drm_mode_fb_cmd2 *mode_cmd)
14016 {
14017         struct drm_i915_gem_object *obj;
14018
14019         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14020                                                 mode_cmd->handles[0]));
14021         if (&obj->base == NULL)
14022                 return ERR_PTR(-ENOENT);
14023
14024         return intel_framebuffer_create(dev, mode_cmd, obj);
14025 }
14026
14027 #ifndef CONFIG_DRM_I915_FBDEV
14028 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14029 {
14030 }
14031 #endif
14032
14033 static const struct drm_mode_config_funcs intel_mode_funcs = {
14034         .fb_create = intel_user_framebuffer_create,
14035         .output_poll_changed = intel_fbdev_output_poll_changed,
14036         .atomic_check = intel_atomic_check,
14037         .atomic_commit = intel_atomic_commit,
14038 };
14039
14040 /* Set up chip specific display functions */
14041 static void intel_init_display(struct drm_device *dev)
14042 {
14043         struct drm_i915_private *dev_priv = dev->dev_private;
14044
14045         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14046                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14047         else if (IS_CHERRYVIEW(dev))
14048                 dev_priv->display.find_dpll = chv_find_best_dpll;
14049         else if (IS_VALLEYVIEW(dev))
14050                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14051         else if (IS_PINEVIEW(dev))
14052                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14053         else
14054                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14055
14056         if (INTEL_INFO(dev)->gen >= 9) {
14057                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14058                 dev_priv->display.get_initial_plane_config =
14059                         skylake_get_initial_plane_config;
14060                 dev_priv->display.crtc_compute_clock =
14061                         haswell_crtc_compute_clock;
14062                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14063                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14064                 dev_priv->display.off = ironlake_crtc_off;
14065                 dev_priv->display.update_primary_plane =
14066                         skylake_update_primary_plane;
14067         } else if (HAS_DDI(dev)) {
14068                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14069                 dev_priv->display.get_initial_plane_config =
14070                         ironlake_get_initial_plane_config;
14071                 dev_priv->display.crtc_compute_clock =
14072                         haswell_crtc_compute_clock;
14073                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14074                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14075                 dev_priv->display.off = ironlake_crtc_off;
14076                 dev_priv->display.update_primary_plane =
14077                         ironlake_update_primary_plane;
14078         } else if (HAS_PCH_SPLIT(dev)) {
14079                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14080                 dev_priv->display.get_initial_plane_config =
14081                         ironlake_get_initial_plane_config;
14082                 dev_priv->display.crtc_compute_clock =
14083                         ironlake_crtc_compute_clock;
14084                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14085                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14086                 dev_priv->display.off = ironlake_crtc_off;
14087                 dev_priv->display.update_primary_plane =
14088                         ironlake_update_primary_plane;
14089         } else if (IS_VALLEYVIEW(dev)) {
14090                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14091                 dev_priv->display.get_initial_plane_config =
14092                         i9xx_get_initial_plane_config;
14093                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14094                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14095                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14096                 dev_priv->display.off = i9xx_crtc_off;
14097                 dev_priv->display.update_primary_plane =
14098                         i9xx_update_primary_plane;
14099         } else {
14100                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14101                 dev_priv->display.get_initial_plane_config =
14102                         i9xx_get_initial_plane_config;
14103                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14104                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14105                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14106                 dev_priv->display.off = i9xx_crtc_off;
14107                 dev_priv->display.update_primary_plane =
14108                         i9xx_update_primary_plane;
14109         }
14110
14111         /* Returns the core display clock speed */
14112         if (IS_SKYLAKE(dev))
14113                 dev_priv->display.get_display_clock_speed =
14114                         skylake_get_display_clock_speed;
14115         else if (IS_BROADWELL(dev))
14116                 dev_priv->display.get_display_clock_speed =
14117                         broadwell_get_display_clock_speed;
14118         else if (IS_HASWELL(dev))
14119                 dev_priv->display.get_display_clock_speed =
14120                         haswell_get_display_clock_speed;
14121         else if (IS_VALLEYVIEW(dev))
14122                 dev_priv->display.get_display_clock_speed =
14123                         valleyview_get_display_clock_speed;
14124         else if (IS_GEN5(dev))
14125                 dev_priv->display.get_display_clock_speed =
14126                         ilk_get_display_clock_speed;
14127         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14128                  IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14129                 dev_priv->display.get_display_clock_speed =
14130                         i945_get_display_clock_speed;
14131         else if (IS_I915G(dev))
14132                 dev_priv->display.get_display_clock_speed =
14133                         i915_get_display_clock_speed;
14134         else if (IS_I945GM(dev) || IS_845G(dev))
14135                 dev_priv->display.get_display_clock_speed =
14136                         i9xx_misc_get_display_clock_speed;
14137         else if (IS_PINEVIEW(dev))
14138                 dev_priv->display.get_display_clock_speed =
14139                         pnv_get_display_clock_speed;
14140         else if (IS_I915GM(dev))
14141                 dev_priv->display.get_display_clock_speed =
14142                         i915gm_get_display_clock_speed;
14143         else if (IS_I865G(dev))
14144                 dev_priv->display.get_display_clock_speed =
14145                         i865_get_display_clock_speed;
14146         else if (IS_I85X(dev))
14147                 dev_priv->display.get_display_clock_speed =
14148                         i855_get_display_clock_speed;
14149         else /* 852, 830 */
14150                 dev_priv->display.get_display_clock_speed =
14151                         i830_get_display_clock_speed;
14152
14153         if (IS_GEN5(dev)) {
14154                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14155         } else if (IS_GEN6(dev)) {
14156                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14157         } else if (IS_IVYBRIDGE(dev)) {
14158                 /* FIXME: detect B0+ stepping and use auto training */
14159                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14160         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14161                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14162         } else if (IS_VALLEYVIEW(dev)) {
14163                 dev_priv->display.modeset_global_resources =
14164                         valleyview_modeset_global_resources;
14165         } else if (IS_BROXTON(dev)) {
14166                 dev_priv->display.modeset_global_resources =
14167                         broxton_modeset_global_resources;
14168         }
14169
14170         switch (INTEL_INFO(dev)->gen) {
14171         case 2:
14172                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14173                 break;
14174
14175         case 3:
14176                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14177                 break;
14178
14179         case 4:
14180         case 5:
14181                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14182                 break;
14183
14184         case 6:
14185                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14186                 break;
14187         case 7:
14188         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14189                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14190                 break;
14191         case 9:
14192                 /* Drop through - unsupported since execlist only. */
14193         default:
14194                 /* Default just returns -ENODEV to indicate unsupported */
14195                 dev_priv->display.queue_flip = intel_default_queue_flip;
14196         }
14197
14198         intel_panel_init_backlight_funcs(dev);
14199
14200         mutex_init(&dev_priv->pps_mutex);
14201 }
14202
14203 /*
14204  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14205  * resume, or other times.  This quirk makes sure that's the case for
14206  * affected systems.
14207  */
14208 static void quirk_pipea_force(struct drm_device *dev)
14209 {
14210         struct drm_i915_private *dev_priv = dev->dev_private;
14211
14212         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14213         DRM_INFO("applying pipe a force quirk\n");
14214 }
14215
14216 static void quirk_pipeb_force(struct drm_device *dev)
14217 {
14218         struct drm_i915_private *dev_priv = dev->dev_private;
14219
14220         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14221         DRM_INFO("applying pipe b force quirk\n");
14222 }
14223
14224 /*
14225  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14226  */
14227 static void quirk_ssc_force_disable(struct drm_device *dev)
14228 {
14229         struct drm_i915_private *dev_priv = dev->dev_private;
14230         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14231         DRM_INFO("applying lvds SSC disable quirk\n");
14232 }
14233
14234 /*
14235  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14236  * brightness value
14237  */
14238 static void quirk_invert_brightness(struct drm_device *dev)
14239 {
14240         struct drm_i915_private *dev_priv = dev->dev_private;
14241         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14242         DRM_INFO("applying inverted panel brightness quirk\n");
14243 }
14244
14245 /* Some VBT's incorrectly indicate no backlight is present */
14246 static void quirk_backlight_present(struct drm_device *dev)
14247 {
14248         struct drm_i915_private *dev_priv = dev->dev_private;
14249         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14250         DRM_INFO("applying backlight present quirk\n");
14251 }
14252
14253 struct intel_quirk {
14254         int device;
14255         int subsystem_vendor;
14256         int subsystem_device;
14257         void (*hook)(struct drm_device *dev);
14258 };
14259
14260 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14261 struct intel_dmi_quirk {
14262         void (*hook)(struct drm_device *dev);
14263         const struct dmi_system_id (*dmi_id_list)[];
14264 };
14265
14266 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14267 {
14268         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14269         return 1;
14270 }
14271
14272 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14273         {
14274                 .dmi_id_list = &(const struct dmi_system_id[]) {
14275                         {
14276                                 .callback = intel_dmi_reverse_brightness,
14277                                 .ident = "NCR Corporation",
14278                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14279                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14280                                 },
14281                         },
14282                         { }  /* terminating entry */
14283                 },
14284                 .hook = quirk_invert_brightness,
14285         },
14286 };
14287
14288 static struct intel_quirk intel_quirks[] = {
14289         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14290         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14291
14292         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14293         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14294
14295         /* 830 needs to leave pipe A & dpll A up */
14296         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14297
14298         /* 830 needs to leave pipe B & dpll B up */
14299         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14300
14301         /* Lenovo U160 cannot use SSC on LVDS */
14302         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14303
14304         /* Sony Vaio Y cannot use SSC on LVDS */
14305         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14306
14307         /* Acer Aspire 5734Z must invert backlight brightness */
14308         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14309
14310         /* Acer/eMachines G725 */
14311         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14312
14313         /* Acer/eMachines e725 */
14314         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14315
14316         /* Acer/Packard Bell NCL20 */
14317         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14318
14319         /* Acer Aspire 4736Z */
14320         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14321
14322         /* Acer Aspire 5336 */
14323         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14324
14325         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14326         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14327
14328         /* Acer C720 Chromebook (Core i3 4005U) */
14329         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14330
14331         /* Apple Macbook 2,1 (Core 2 T7400) */
14332         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14333
14334         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14335         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14336
14337         /* HP Chromebook 14 (Celeron 2955U) */
14338         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14339
14340         /* Dell Chromebook 11 */
14341         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14342 };
14343
14344 static void intel_init_quirks(struct drm_device *dev)
14345 {
14346         struct pci_dev *d = dev->pdev;
14347         int i;
14348
14349         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14350                 struct intel_quirk *q = &intel_quirks[i];
14351
14352                 if (d->device == q->device &&
14353                     (d->subsystem_vendor == q->subsystem_vendor ||
14354                      q->subsystem_vendor == PCI_ANY_ID) &&
14355                     (d->subsystem_device == q->subsystem_device ||
14356                      q->subsystem_device == PCI_ANY_ID))
14357                         q->hook(dev);
14358         }
14359         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14360                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14361                         intel_dmi_quirks[i].hook(dev);
14362         }
14363 }
14364
14365 /* Disable the VGA plane that we never use */
14366 static void i915_disable_vga(struct drm_device *dev)
14367 {
14368         struct drm_i915_private *dev_priv = dev->dev_private;
14369         u8 sr1;
14370         u32 vga_reg = i915_vgacntrl_reg(dev);
14371
14372         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14373         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14374         outb(SR01, VGA_SR_INDEX);
14375         sr1 = inb(VGA_SR_DATA);
14376         outb(sr1 | 1<<5, VGA_SR_DATA);
14377         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14378         udelay(300);
14379
14380         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14381         POSTING_READ(vga_reg);
14382 }
14383
14384 void intel_modeset_init_hw(struct drm_device *dev)
14385 {
14386         intel_prepare_ddi(dev);
14387
14388         if (IS_VALLEYVIEW(dev))
14389                 vlv_update_cdclk(dev);
14390
14391         intel_init_clock_gating(dev);
14392
14393         intel_enable_gt_powersave(dev);
14394 }
14395
14396 void intel_modeset_init(struct drm_device *dev)
14397 {
14398         struct drm_i915_private *dev_priv = dev->dev_private;
14399         int sprite, ret;
14400         enum pipe pipe;
14401         struct intel_crtc *crtc;
14402
14403         drm_mode_config_init(dev);
14404
14405         dev->mode_config.min_width = 0;
14406         dev->mode_config.min_height = 0;
14407
14408         dev->mode_config.preferred_depth = 24;
14409         dev->mode_config.prefer_shadow = 1;
14410
14411         dev->mode_config.allow_fb_modifiers = true;
14412
14413         dev->mode_config.funcs = &intel_mode_funcs;
14414
14415         intel_init_quirks(dev);
14416
14417         intel_init_pm(dev);
14418
14419         if (INTEL_INFO(dev)->num_pipes == 0)
14420                 return;
14421
14422         intel_init_display(dev);
14423         intel_init_audio(dev);
14424
14425         if (IS_GEN2(dev)) {
14426                 dev->mode_config.max_width = 2048;
14427                 dev->mode_config.max_height = 2048;
14428         } else if (IS_GEN3(dev)) {
14429                 dev->mode_config.max_width = 4096;
14430                 dev->mode_config.max_height = 4096;
14431         } else {
14432                 dev->mode_config.max_width = 8192;
14433                 dev->mode_config.max_height = 8192;
14434         }
14435
14436         if (IS_845G(dev) || IS_I865G(dev)) {
14437                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14438                 dev->mode_config.cursor_height = 1023;
14439         } else if (IS_GEN2(dev)) {
14440                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14441                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14442         } else {
14443                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14444                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14445         }
14446
14447         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14448
14449         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14450                       INTEL_INFO(dev)->num_pipes,
14451                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14452
14453         for_each_pipe(dev_priv, pipe) {
14454                 intel_crtc_init(dev, pipe);
14455                 for_each_sprite(dev_priv, pipe, sprite) {
14456                         ret = intel_plane_init(dev, pipe, sprite);
14457                         if (ret)
14458                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14459                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14460                 }
14461         }
14462
14463         intel_init_dpio(dev);
14464
14465         intel_shared_dpll_init(dev);
14466
14467         /* Just disable it once at startup */
14468         i915_disable_vga(dev);
14469         intel_setup_outputs(dev);
14470
14471         /* Just in case the BIOS is doing something questionable. */
14472         intel_fbc_disable(dev);
14473
14474         drm_modeset_lock_all(dev);
14475         intel_modeset_setup_hw_state(dev, false);
14476         drm_modeset_unlock_all(dev);
14477
14478         for_each_intel_crtc(dev, crtc) {
14479                 if (!crtc->active)
14480                         continue;
14481
14482                 /*
14483                  * Note that reserving the BIOS fb up front prevents us
14484                  * from stuffing other stolen allocations like the ring
14485                  * on top.  This prevents some ugliness at boot time, and
14486                  * can even allow for smooth boot transitions if the BIOS
14487                  * fb is large enough for the active pipe configuration.
14488                  */
14489                 if (dev_priv->display.get_initial_plane_config) {
14490                         dev_priv->display.get_initial_plane_config(crtc,
14491                                                            &crtc->plane_config);
14492                         /*
14493                          * If the fb is shared between multiple heads, we'll
14494                          * just get the first one.
14495                          */
14496                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14497                 }
14498         }
14499 }
14500
14501 static void intel_enable_pipe_a(struct drm_device *dev)
14502 {
14503         struct intel_connector *connector;
14504         struct drm_connector *crt = NULL;
14505         struct intel_load_detect_pipe load_detect_temp;
14506         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14507
14508         /* We can't just switch on the pipe A, we need to set things up with a
14509          * proper mode and output configuration. As a gross hack, enable pipe A
14510          * by enabling the load detect pipe once. */
14511         for_each_intel_connector(dev, connector) {
14512                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14513                         crt = &connector->base;
14514                         break;
14515                 }
14516         }
14517
14518         if (!crt)
14519                 return;
14520
14521         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14522                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14523 }
14524
14525 static bool
14526 intel_check_plane_mapping(struct intel_crtc *crtc)
14527 {
14528         struct drm_device *dev = crtc->base.dev;
14529         struct drm_i915_private *dev_priv = dev->dev_private;
14530         u32 reg, val;
14531
14532         if (INTEL_INFO(dev)->num_pipes == 1)
14533                 return true;
14534
14535         reg = DSPCNTR(!crtc->plane);
14536         val = I915_READ(reg);
14537
14538         if ((val & DISPLAY_PLANE_ENABLE) &&
14539             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14540                 return false;
14541
14542         return true;
14543 }
14544
14545 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14546 {
14547         struct drm_device *dev = crtc->base.dev;
14548         struct drm_i915_private *dev_priv = dev->dev_private;
14549         u32 reg;
14550
14551         /* Clear any frame start delays used for debugging left by the BIOS */
14552         reg = PIPECONF(crtc->config->cpu_transcoder);
14553         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14554
14555         /* restore vblank interrupts to correct state */
14556         drm_crtc_vblank_reset(&crtc->base);
14557         if (crtc->active) {
14558                 update_scanline_offset(crtc);
14559                 drm_crtc_vblank_on(&crtc->base);
14560         }
14561
14562         /* We need to sanitize the plane -> pipe mapping first because this will
14563          * disable the crtc (and hence change the state) if it is wrong. Note
14564          * that gen4+ has a fixed plane -> pipe mapping.  */
14565         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14566                 struct intel_connector *connector;
14567                 bool plane;
14568
14569                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14570                               crtc->base.base.id);
14571
14572                 /* Pipe has the wrong plane attached and the plane is active.
14573                  * Temporarily change the plane mapping and disable everything
14574                  * ...  */
14575                 plane = crtc->plane;
14576                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14577                 crtc->plane = !plane;
14578                 intel_crtc_disable_planes(&crtc->base);
14579                 dev_priv->display.crtc_disable(&crtc->base);
14580                 crtc->plane = plane;
14581
14582                 /* ... and break all links. */
14583                 for_each_intel_connector(dev, connector) {
14584                         if (connector->encoder->base.crtc != &crtc->base)
14585                                 continue;
14586
14587                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14588                         connector->base.encoder = NULL;
14589                 }
14590                 /* multiple connectors may have the same encoder:
14591                  *  handle them and break crtc link separately */
14592                 for_each_intel_connector(dev, connector)
14593                         if (connector->encoder->base.crtc == &crtc->base) {
14594                                 connector->encoder->base.crtc = NULL;
14595                                 connector->encoder->connectors_active = false;
14596                         }
14597
14598                 WARN_ON(crtc->active);
14599                 crtc->base.state->enable = false;
14600                 crtc->base.state->active = false;
14601                 crtc->base.enabled = false;
14602         }
14603
14604         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14605             crtc->pipe == PIPE_A && !crtc->active) {
14606                 /* BIOS forgot to enable pipe A, this mostly happens after
14607                  * resume. Force-enable the pipe to fix this, the update_dpms
14608                  * call below we restore the pipe to the right state, but leave
14609                  * the required bits on. */
14610                 intel_enable_pipe_a(dev);
14611         }
14612
14613         /* Adjust the state of the output pipe according to whether we
14614          * have active connectors/encoders. */
14615         intel_crtc_update_dpms(&crtc->base);
14616
14617         if (crtc->active != crtc->base.state->enable) {
14618                 struct intel_encoder *encoder;
14619
14620                 /* This can happen either due to bugs in the get_hw_state
14621                  * functions or because the pipe is force-enabled due to the
14622                  * pipe A quirk. */
14623                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14624                               crtc->base.base.id,
14625                               crtc->base.state->enable ? "enabled" : "disabled",
14626                               crtc->active ? "enabled" : "disabled");
14627
14628                 crtc->base.state->enable = crtc->active;
14629                 crtc->base.state->active = crtc->active;
14630                 crtc->base.enabled = crtc->active;
14631
14632                 /* Because we only establish the connector -> encoder ->
14633                  * crtc links if something is active, this means the
14634                  * crtc is now deactivated. Break the links. connector
14635                  * -> encoder links are only establish when things are
14636                  *  actually up, hence no need to break them. */
14637                 WARN_ON(crtc->active);
14638
14639                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14640                         WARN_ON(encoder->connectors_active);
14641                         encoder->base.crtc = NULL;
14642                 }
14643         }
14644
14645         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14646                 /*
14647                  * We start out with underrun reporting disabled to avoid races.
14648                  * For correct bookkeeping mark this on active crtcs.
14649                  *
14650                  * Also on gmch platforms we dont have any hardware bits to
14651                  * disable the underrun reporting. Which means we need to start
14652                  * out with underrun reporting disabled also on inactive pipes,
14653                  * since otherwise we'll complain about the garbage we read when
14654                  * e.g. coming up after runtime pm.
14655                  *
14656                  * No protection against concurrent access is required - at
14657                  * worst a fifo underrun happens which also sets this to false.
14658                  */
14659                 crtc->cpu_fifo_underrun_disabled = true;
14660                 crtc->pch_fifo_underrun_disabled = true;
14661         }
14662 }
14663
14664 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14665 {
14666         struct intel_connector *connector;
14667         struct drm_device *dev = encoder->base.dev;
14668
14669         /* We need to check both for a crtc link (meaning that the
14670          * encoder is active and trying to read from a pipe) and the
14671          * pipe itself being active. */
14672         bool has_active_crtc = encoder->base.crtc &&
14673                 to_intel_crtc(encoder->base.crtc)->active;
14674
14675         if (encoder->connectors_active && !has_active_crtc) {
14676                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14677                               encoder->base.base.id,
14678                               encoder->base.name);
14679
14680                 /* Connector is active, but has no active pipe. This is
14681                  * fallout from our resume register restoring. Disable
14682                  * the encoder manually again. */
14683                 if (encoder->base.crtc) {
14684                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14685                                       encoder->base.base.id,
14686                                       encoder->base.name);
14687                         encoder->disable(encoder);
14688                         if (encoder->post_disable)
14689                                 encoder->post_disable(encoder);
14690                 }
14691                 encoder->base.crtc = NULL;
14692                 encoder->connectors_active = false;
14693
14694                 /* Inconsistent output/port/pipe state happens presumably due to
14695                  * a bug in one of the get_hw_state functions. Or someplace else
14696                  * in our code, like the register restore mess on resume. Clamp
14697                  * things to off as a safer default. */
14698                 for_each_intel_connector(dev, connector) {
14699                         if (connector->encoder != encoder)
14700                                 continue;
14701                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14702                         connector->base.encoder = NULL;
14703                 }
14704         }
14705         /* Enabled encoders without active connectors will be fixed in
14706          * the crtc fixup. */
14707 }
14708
14709 void i915_redisable_vga_power_on(struct drm_device *dev)
14710 {
14711         struct drm_i915_private *dev_priv = dev->dev_private;
14712         u32 vga_reg = i915_vgacntrl_reg(dev);
14713
14714         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14715                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14716                 i915_disable_vga(dev);
14717         }
14718 }
14719
14720 void i915_redisable_vga(struct drm_device *dev)
14721 {
14722         struct drm_i915_private *dev_priv = dev->dev_private;
14723
14724         /* This function can be called both from intel_modeset_setup_hw_state or
14725          * at a very early point in our resume sequence, where the power well
14726          * structures are not yet restored. Since this function is at a very
14727          * paranoid "someone might have enabled VGA while we were not looking"
14728          * level, just check if the power well is enabled instead of trying to
14729          * follow the "don't touch the power well if we don't need it" policy
14730          * the rest of the driver uses. */
14731         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14732                 return;
14733
14734         i915_redisable_vga_power_on(dev);
14735 }
14736
14737 static bool primary_get_hw_state(struct intel_crtc *crtc)
14738 {
14739         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14740
14741         if (!crtc->active)
14742                 return false;
14743
14744         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14745 }
14746
14747 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14748 {
14749         struct drm_i915_private *dev_priv = dev->dev_private;
14750         enum pipe pipe;
14751         struct intel_crtc *crtc;
14752         struct intel_encoder *encoder;
14753         struct intel_connector *connector;
14754         int i;
14755
14756         for_each_intel_crtc(dev, crtc) {
14757                 struct drm_plane *primary = crtc->base.primary;
14758                 struct intel_plane_state *plane_state;
14759
14760                 memset(crtc->config, 0, sizeof(*crtc->config));
14761
14762                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14763
14764                 crtc->active = dev_priv->display.get_pipe_config(crtc,
14765                                                                  crtc->config);
14766
14767                 crtc->base.state->enable = crtc->active;
14768                 crtc->base.state->active = crtc->active;
14769                 crtc->base.enabled = crtc->active;
14770
14771                 plane_state = to_intel_plane_state(primary->state);
14772                 plane_state->visible = primary_get_hw_state(crtc);
14773
14774                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14775                               crtc->base.base.id,
14776                               crtc->active ? "enabled" : "disabled");
14777         }
14778
14779         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14780                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14781
14782                 pll->on = pll->get_hw_state(dev_priv, pll,
14783                                             &pll->config.hw_state);
14784                 pll->active = 0;
14785                 pll->config.crtc_mask = 0;
14786                 for_each_intel_crtc(dev, crtc) {
14787                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14788                                 pll->active++;
14789                                 pll->config.crtc_mask |= 1 << crtc->pipe;
14790                         }
14791                 }
14792
14793                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14794                               pll->name, pll->config.crtc_mask, pll->on);
14795
14796                 if (pll->config.crtc_mask)
14797                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14798         }
14799
14800         for_each_intel_encoder(dev, encoder) {
14801                 pipe = 0;
14802
14803                 if (encoder->get_hw_state(encoder, &pipe)) {
14804                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14805                         encoder->base.crtc = &crtc->base;
14806                         encoder->get_config(encoder, crtc->config);
14807                 } else {
14808                         encoder->base.crtc = NULL;
14809                 }
14810
14811                 encoder->connectors_active = false;
14812                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14813                               encoder->base.base.id,
14814                               encoder->base.name,
14815                               encoder->base.crtc ? "enabled" : "disabled",
14816                               pipe_name(pipe));
14817         }
14818
14819         for_each_intel_connector(dev, connector) {
14820                 if (connector->get_hw_state(connector)) {
14821                         connector->base.dpms = DRM_MODE_DPMS_ON;
14822                         connector->encoder->connectors_active = true;
14823                         connector->base.encoder = &connector->encoder->base;
14824                 } else {
14825                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14826                         connector->base.encoder = NULL;
14827                 }
14828                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14829                               connector->base.base.id,
14830                               connector->base.name,
14831                               connector->base.encoder ? "enabled" : "disabled");
14832         }
14833 }
14834
14835 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14836  * and i915 state tracking structures. */
14837 void intel_modeset_setup_hw_state(struct drm_device *dev,
14838                                   bool force_restore)
14839 {
14840         struct drm_i915_private *dev_priv = dev->dev_private;
14841         enum pipe pipe;
14842         struct intel_crtc *crtc;
14843         struct intel_encoder *encoder;
14844         int i;
14845
14846         intel_modeset_readout_hw_state(dev);
14847
14848         /*
14849          * Now that we have the config, copy it to each CRTC struct
14850          * Note that this could go away if we move to using crtc_config
14851          * checking everywhere.
14852          */
14853         for_each_intel_crtc(dev, crtc) {
14854                 if (crtc->active && i915.fastboot) {
14855                         intel_mode_from_pipe_config(&crtc->base.mode,
14856                                                     crtc->config);
14857                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14858                                       crtc->base.base.id);
14859                         drm_mode_debug_printmodeline(&crtc->base.mode);
14860                 }
14861         }
14862
14863         /* HW state is read out, now we need to sanitize this mess. */
14864         for_each_intel_encoder(dev, encoder) {
14865                 intel_sanitize_encoder(encoder);
14866         }
14867
14868         for_each_pipe(dev_priv, pipe) {
14869                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14870                 intel_sanitize_crtc(crtc);
14871                 intel_dump_pipe_config(crtc, crtc->config,
14872                                        "[setup_hw_state]");
14873         }
14874
14875         intel_modeset_update_connector_atomic_state(dev);
14876
14877         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14878                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14879
14880                 if (!pll->on || pll->active)
14881                         continue;
14882
14883                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14884
14885                 pll->disable(dev_priv, pll);
14886                 pll->on = false;
14887         }
14888
14889         if (IS_GEN9(dev))
14890                 skl_wm_get_hw_state(dev);
14891         else if (HAS_PCH_SPLIT(dev))
14892                 ilk_wm_get_hw_state(dev);
14893
14894         if (force_restore) {
14895                 i915_redisable_vga(dev);
14896
14897                 /*
14898                  * We need to use raw interfaces for restoring state to avoid
14899                  * checking (bogus) intermediate states.
14900                  */
14901                 for_each_pipe(dev_priv, pipe) {
14902                         struct drm_crtc *crtc =
14903                                 dev_priv->pipe_to_crtc_mapping[pipe];
14904
14905                         intel_crtc_restore_mode(crtc);
14906                 }
14907         } else {
14908                 intel_modeset_update_staged_output_state(dev);
14909         }
14910
14911         intel_modeset_check_state(dev);
14912 }
14913
14914 void intel_modeset_gem_init(struct drm_device *dev)
14915 {
14916         struct drm_i915_private *dev_priv = dev->dev_private;
14917         struct drm_crtc *c;
14918         struct drm_i915_gem_object *obj;
14919         int ret;
14920
14921         mutex_lock(&dev->struct_mutex);
14922         intel_init_gt_powersave(dev);
14923         mutex_unlock(&dev->struct_mutex);
14924
14925         /*
14926          * There may be no VBT; and if the BIOS enabled SSC we can
14927          * just keep using it to avoid unnecessary flicker.  Whereas if the
14928          * BIOS isn't using it, don't assume it will work even if the VBT
14929          * indicates as much.
14930          */
14931         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14932                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14933                                                 DREF_SSC1_ENABLE);
14934
14935         intel_modeset_init_hw(dev);
14936
14937         intel_setup_overlay(dev);
14938
14939         /*
14940          * Make sure any fbs we allocated at startup are properly
14941          * pinned & fenced.  When we do the allocation it's too early
14942          * for this.
14943          */
14944         for_each_crtc(dev, c) {
14945                 obj = intel_fb_obj(c->primary->fb);
14946                 if (obj == NULL)
14947                         continue;
14948
14949                 mutex_lock(&dev->struct_mutex);
14950                 ret = intel_pin_and_fence_fb_obj(c->primary,
14951                                                  c->primary->fb,
14952                                                  c->primary->state,
14953                                                  NULL);
14954                 mutex_unlock(&dev->struct_mutex);
14955                 if (ret) {
14956                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
14957                                   to_intel_crtc(c)->pipe);
14958                         drm_framebuffer_unreference(c->primary->fb);
14959                         c->primary->fb = NULL;
14960                         update_state_fb(c->primary);
14961                 }
14962         }
14963
14964         intel_backlight_register(dev);
14965 }
14966
14967 void intel_connector_unregister(struct intel_connector *intel_connector)
14968 {
14969         struct drm_connector *connector = &intel_connector->base;
14970
14971         intel_panel_destroy_backlight(connector);
14972         drm_connector_unregister(connector);
14973 }
14974
14975 void intel_modeset_cleanup(struct drm_device *dev)
14976 {
14977         struct drm_i915_private *dev_priv = dev->dev_private;
14978         struct drm_connector *connector;
14979
14980         intel_disable_gt_powersave(dev);
14981
14982         intel_backlight_unregister(dev);
14983
14984         /*
14985          * Interrupts and polling as the first thing to avoid creating havoc.
14986          * Too much stuff here (turning of connectors, ...) would
14987          * experience fancy races otherwise.
14988          */
14989         intel_irq_uninstall(dev_priv);
14990
14991         /*
14992          * Due to the hpd irq storm handling the hotplug work can re-arm the
14993          * poll handlers. Hence disable polling after hpd handling is shut down.
14994          */
14995         drm_kms_helper_poll_fini(dev);
14996
14997         mutex_lock(&dev->struct_mutex);
14998
14999         intel_unregister_dsm_handler();
15000
15001         intel_fbc_disable(dev);
15002
15003         mutex_unlock(&dev->struct_mutex);
15004
15005         /* flush any delayed tasks or pending work */
15006         flush_scheduled_work();
15007
15008         /* destroy the backlight and sysfs files before encoders/connectors */
15009         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15010                 struct intel_connector *intel_connector;
15011
15012                 intel_connector = to_intel_connector(connector);
15013                 intel_connector->unregister(intel_connector);
15014         }
15015
15016         drm_mode_config_cleanup(dev);
15017
15018         intel_cleanup_overlay(dev);
15019
15020         mutex_lock(&dev->struct_mutex);
15021         intel_cleanup_gt_powersave(dev);
15022         mutex_unlock(&dev->struct_mutex);
15023 }
15024
15025 /*
15026  * Return which encoder is currently attached for connector.
15027  */
15028 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15029 {
15030         return &intel_attached_encoder(connector)->base;
15031 }
15032
15033 void intel_connector_attach_encoder(struct intel_connector *connector,
15034                                     struct intel_encoder *encoder)
15035 {
15036         connector->encoder = encoder;
15037         drm_mode_connector_attach_encoder(&connector->base,
15038                                           &encoder->base);
15039 }
15040
15041 /*
15042  * set vga decode state - true == enable VGA decode
15043  */
15044 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15045 {
15046         struct drm_i915_private *dev_priv = dev->dev_private;
15047         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15048         u16 gmch_ctrl;
15049
15050         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15051                 DRM_ERROR("failed to read control word\n");
15052                 return -EIO;
15053         }
15054
15055         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15056                 return 0;
15057
15058         if (state)
15059                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15060         else
15061                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15062
15063         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15064                 DRM_ERROR("failed to write control word\n");
15065                 return -EIO;
15066         }
15067
15068         return 0;
15069 }
15070
15071 struct intel_display_error_state {
15072
15073         u32 power_well_driver;
15074
15075         int num_transcoders;
15076
15077         struct intel_cursor_error_state {
15078                 u32 control;
15079                 u32 position;
15080                 u32 base;
15081                 u32 size;
15082         } cursor[I915_MAX_PIPES];
15083
15084         struct intel_pipe_error_state {
15085                 bool power_domain_on;
15086                 u32 source;
15087                 u32 stat;
15088         } pipe[I915_MAX_PIPES];
15089
15090         struct intel_plane_error_state {
15091                 u32 control;
15092                 u32 stride;
15093                 u32 size;
15094                 u32 pos;
15095                 u32 addr;
15096                 u32 surface;
15097                 u32 tile_offset;
15098         } plane[I915_MAX_PIPES];
15099
15100         struct intel_transcoder_error_state {
15101                 bool power_domain_on;
15102                 enum transcoder cpu_transcoder;
15103
15104                 u32 conf;
15105
15106                 u32 htotal;
15107                 u32 hblank;
15108                 u32 hsync;
15109                 u32 vtotal;
15110                 u32 vblank;
15111                 u32 vsync;
15112         } transcoder[4];
15113 };
15114
15115 struct intel_display_error_state *
15116 intel_display_capture_error_state(struct drm_device *dev)
15117 {
15118         struct drm_i915_private *dev_priv = dev->dev_private;
15119         struct intel_display_error_state *error;
15120         int transcoders[] = {
15121                 TRANSCODER_A,
15122                 TRANSCODER_B,
15123                 TRANSCODER_C,
15124                 TRANSCODER_EDP,
15125         };
15126         int i;
15127
15128         if (INTEL_INFO(dev)->num_pipes == 0)
15129                 return NULL;
15130
15131         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15132         if (error == NULL)
15133                 return NULL;
15134
15135         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15136                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15137
15138         for_each_pipe(dev_priv, i) {
15139                 error->pipe[i].power_domain_on =
15140                         __intel_display_power_is_enabled(dev_priv,
15141                                                          POWER_DOMAIN_PIPE(i));
15142                 if (!error->pipe[i].power_domain_on)
15143                         continue;
15144
15145                 error->cursor[i].control = I915_READ(CURCNTR(i));
15146                 error->cursor[i].position = I915_READ(CURPOS(i));
15147                 error->cursor[i].base = I915_READ(CURBASE(i));
15148
15149                 error->plane[i].control = I915_READ(DSPCNTR(i));
15150                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15151                 if (INTEL_INFO(dev)->gen <= 3) {
15152                         error->plane[i].size = I915_READ(DSPSIZE(i));
15153                         error->plane[i].pos = I915_READ(DSPPOS(i));
15154                 }
15155                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15156                         error->plane[i].addr = I915_READ(DSPADDR(i));
15157                 if (INTEL_INFO(dev)->gen >= 4) {
15158                         error->plane[i].surface = I915_READ(DSPSURF(i));
15159                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15160                 }
15161
15162                 error->pipe[i].source = I915_READ(PIPESRC(i));
15163
15164                 if (HAS_GMCH_DISPLAY(dev))
15165                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15166         }
15167
15168         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15169         if (HAS_DDI(dev_priv->dev))
15170                 error->num_transcoders++; /* Account for eDP. */
15171
15172         for (i = 0; i < error->num_transcoders; i++) {
15173                 enum transcoder cpu_transcoder = transcoders[i];
15174
15175                 error->transcoder[i].power_domain_on =
15176                         __intel_display_power_is_enabled(dev_priv,
15177                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15178                 if (!error->transcoder[i].power_domain_on)
15179                         continue;
15180
15181                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15182
15183                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15184                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15185                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15186                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15187                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15188                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15189                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15190         }
15191
15192         return error;
15193 }
15194
15195 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15196
15197 void
15198 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15199                                 struct drm_device *dev,
15200                                 struct intel_display_error_state *error)
15201 {
15202         struct drm_i915_private *dev_priv = dev->dev_private;
15203         int i;
15204
15205         if (!error)
15206                 return;
15207
15208         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15209         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15210                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15211                            error->power_well_driver);
15212         for_each_pipe(dev_priv, i) {
15213                 err_printf(m, "Pipe [%d]:\n", i);
15214                 err_printf(m, "  Power: %s\n",
15215                            error->pipe[i].power_domain_on ? "on" : "off");
15216                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15217                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15218
15219                 err_printf(m, "Plane [%d]:\n", i);
15220                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15221                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15222                 if (INTEL_INFO(dev)->gen <= 3) {
15223                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15224                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15225                 }
15226                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15227                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15228                 if (INTEL_INFO(dev)->gen >= 4) {
15229                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15230                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15231                 }
15232
15233                 err_printf(m, "Cursor [%d]:\n", i);
15234                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15235                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15236                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15237         }
15238
15239         for (i = 0; i < error->num_transcoders; i++) {
15240                 err_printf(m, "CPU transcoder: %c\n",
15241                            transcoder_name(error->transcoder[i].cpu_transcoder));
15242                 err_printf(m, "  Power: %s\n",
15243                            error->transcoder[i].power_domain_on ? "on" : "off");
15244                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15245                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15246                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15247                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15248                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15249                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15250                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15251         }
15252 }
15253
15254 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15255 {
15256         struct intel_crtc *crtc;
15257
15258         for_each_intel_crtc(dev, crtc) {
15259                 struct intel_unpin_work *work;
15260
15261                 spin_lock_irq(&dev->event_lock);
15262
15263                 work = crtc->unpin_work;
15264
15265                 if (work && work->event &&
15266                     work->event->base.file_priv == file) {
15267                         kfree(work->event);
15268                         work->event = NULL;
15269                 }
15270
15271                 spin_unlock_irq(&dev->event_lock);
15272         }
15273 }