drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_gem_dmabuf.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 119         struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int bxt_calc_cdclk(int max_pixclk);
 127
 128 struct intel_limit {
 129         struct {
 130                 int min, max;
 131         } dot, vco, n, m, m1, m2, p, p1;
 132
 133         struct {
 134                 int dot_limit;
 135                 int p2_slow, p2_fast;
 136         } p2;
 137 };
 138
 139 /* returns HPLL frequency in kHz */
 140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 141 {
 142         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 143
 144         /* Obtain SKU information */
 145         mutex_lock(&dev_priv->sb_lock);
 146         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 147                 CCK_FUSE_HPLL_FREQ_MASK;
 148         mutex_unlock(&dev_priv->sb_lock);
 149
 150         return vco_freq[hpll_freq] * 1000;
 151 }
 152
 153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 154                       const char *name, u32 reg, int ref_freq)
 155 {
 156         u32 val;
 157         int divider;
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 170 }
 171
 172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 173                                   const char *name, u32 reg)
 174 {
 175         if (dev_priv->hpll_freq == 0)
 176                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 177
 178         return vlv_get_cck_clock(dev_priv, name, reg,
 179                                  dev_priv->hpll_freq);
 180 }
 181
 182 static int
 183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 184 {
 185         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 186 }
 187
 188 static int
 189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 190 {
 191         /* RAWCLK_FREQ_VLV register updated from power well code */
 192         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 193                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 194 }
 195
 196 static int
 197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 198 {
 199         uint32_t clkcfg;
 200
 201         /* hrawclock is 1/4 the FSB frequency */
 202         clkcfg = I915_READ(CLKCFG);
 203         switch (clkcfg & CLKCFG_FSB_MASK) {
 204         case CLKCFG_FSB_400:
 205                 return 100000;
 206         case CLKCFG_FSB_533:
 207                 return 133333;
 208         case CLKCFG_FSB_667:
 209                 return 166667;
 210         case CLKCFG_FSB_800:
 211                 return 200000;
 212         case CLKCFG_FSB_1067:
 213                 return 266667;
 214         case CLKCFG_FSB_1333:
 215                 return 333333;
 216         /* these two are just a guess; one of them might be right */
 217         case CLKCFG_FSB_1600:
 218         case CLKCFG_FSB_1600_ALT:
 219                 return 400000;
 220         default:
 221                 return 133333;
 222         }
 223 }
 224
 225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 226 {
 227         if (HAS_PCH_SPLIT(dev_priv))
 228                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 229         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 230                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 231         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 232                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 233         else
 234                 return; /* no rawclk on other platforms, or no need to know it */
 235
 236         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 237 }
 238
 239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 240 {
 241         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 242                 return;
 243
 244         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 245                                                       CCK_CZ_CLOCK_CONTROL);
 246
 247         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 248 }
 249
 250 static inline u32 /* units of 100MHz */
 251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 252                     const struct intel_crtc_state *pipe_config)
 253 {
 254         if (HAS_DDI(dev_priv))
 255                 return pipe_config->port_clock; /* SPLL */
 256         else if (IS_GEN5(dev_priv))
 257                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 258         else
 259                 return 270000;
 260 }
 261
 262 static const struct intel_limit intel_limits_i8xx_dac = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 2, .max = 33 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 4, .p2_fast = 2 },
 273 };
 274
 275 static const struct intel_limit intel_limits_i8xx_dvo = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 908000, .max = 1512000 },
 278         .n = { .min = 2, .max = 16 },
 279         .m = { .min = 96, .max = 140 },
 280         .m1 = { .min = 18, .max = 26 },
 281         .m2 = { .min = 6, .max = 16 },
 282         .p = { .min = 4, .max = 128 },
 283         .p1 = { .min = 2, .max = 33 },
 284         .p2 = { .dot_limit = 165000,
 285                 .p2_slow = 4, .p2_fast = 4 },
 286 };
 287
 288 static const struct intel_limit intel_limits_i8xx_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 908000, .max = 1512000 },
 291         .n = { .min = 2, .max = 16 },
 292         .m = { .min = 96, .max = 140 },
 293         .m1 = { .min = 18, .max = 26 },
 294         .m2 = { .min = 6, .max = 16 },
 295         .p = { .min = 4, .max = 128 },
 296         .p1 = { .min = 1, .max = 6 },
 297         .p2 = { .dot_limit = 165000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301 static const struct intel_limit intel_limits_i9xx_sdvo = {
 302         .dot = { .min = 20000, .max = 400000 },
 303         .vco = { .min = 1400000, .max = 2800000 },
 304         .n = { .min = 1, .max = 6 },
 305         .m = { .min = 70, .max = 120 },
 306         .m1 = { .min = 8, .max = 18 },
 307         .m2 = { .min = 3, .max = 7 },
 308         .p = { .min = 5, .max = 80 },
 309         .p1 = { .min = 1, .max = 8 },
 310         .p2 = { .dot_limit = 200000,
 311                 .p2_slow = 10, .p2_fast = 5 },
 312 };
 313
 314 static const struct intel_limit intel_limits_i9xx_lvds = {
 315         .dot = { .min = 20000, .max = 400000 },
 316         .vco = { .min = 1400000, .max = 2800000 },
 317         .n = { .min = 1, .max = 6 },
 318         .m = { .min = 70, .max = 120 },
 319         .m1 = { .min = 8, .max = 18 },
 320         .m2 = { .min = 3, .max = 7 },
 321         .p = { .min = 7, .max = 98 },
 322         .p1 = { .min = 1, .max = 8 },
 323         .p2 = { .dot_limit = 112000,
 324                 .p2_slow = 14, .p2_fast = 7 },
 325 };
 326
 327
 328 static const struct intel_limit intel_limits_g4x_sdvo = {
 329         .dot = { .min = 25000, .max = 270000 },
 330         .vco = { .min = 1750000, .max = 3500000},
 331         .n = { .min = 1, .max = 4 },
 332         .m = { .min = 104, .max = 138 },
 333         .m1 = { .min = 17, .max = 23 },
 334         .m2 = { .min = 5, .max = 11 },
 335         .p = { .min = 10, .max = 30 },
 336         .p1 = { .min = 1, .max = 3},
 337         .p2 = { .dot_limit = 270000,
 338                 .p2_slow = 10,
 339                 .p2_fast = 10
 340         },
 341 };
 342
 343 static const struct intel_limit intel_limits_g4x_hdmi = {
 344         .dot = { .min = 22000, .max = 400000 },
 345         .vco = { .min = 1750000, .max = 3500000},
 346         .n = { .min = 1, .max = 4 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 16, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 5, .max = 80 },
 351         .p1 = { .min = 1, .max = 8},
 352         .p2 = { .dot_limit = 165000,
 353                 .p2_slow = 10, .p2_fast = 5 },
 354 };
 355
 356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 357         .dot = { .min = 20000, .max = 115000 },
 358         .vco = { .min = 1750000, .max = 3500000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 104, .max = 138 },
 361         .m1 = { .min = 17, .max = 23 },
 362         .m2 = { .min = 5, .max = 11 },
 363         .p = { .min = 28, .max = 112 },
 364         .p1 = { .min = 2, .max = 8 },
 365         .p2 = { .dot_limit = 0,
 366                 .p2_slow = 14, .p2_fast = 14
 367         },
 368 };
 369
 370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 371         .dot = { .min = 80000, .max = 224000 },
 372         .vco = { .min = 1750000, .max = 3500000 },
 373         .n = { .min = 1, .max = 3 },
 374         .m = { .min = 104, .max = 138 },
 375         .m1 = { .min = 17, .max = 23 },
 376         .m2 = { .min = 5, .max = 11 },
 377         .p = { .min = 14, .max = 42 },
 378         .p1 = { .min = 2, .max = 6 },
 379         .p2 = { .dot_limit = 0,
 380                 .p2_slow = 7, .p2_fast = 7
 381         },
 382 };
 383
 384 static const struct intel_limit intel_limits_pineview_sdvo = {
 385         .dot = { .min = 20000, .max = 400000},
 386         .vco = { .min = 1700000, .max = 3500000 },
 387         /* Pineview's Ncounter is a ring counter */
 388         .n = { .min = 3, .max = 6 },
 389         .m = { .min = 2, .max = 256 },
 390         /* Pineview only has one combined m divider, which we treat as m2. */
 391         .m1 = { .min = 0, .max = 0 },
 392         .m2 = { .min = 0, .max = 254 },
 393         .p = { .min = 5, .max = 80 },
 394         .p1 = { .min = 1, .max = 8 },
 395         .p2 = { .dot_limit = 200000,
 396                 .p2_slow = 10, .p2_fast = 5 },
 397 };
 398
 399 static const struct intel_limit intel_limits_pineview_lvds = {
 400         .dot = { .min = 20000, .max = 400000 },
 401         .vco = { .min = 1700000, .max = 3500000 },
 402         .n = { .min = 3, .max = 6 },
 403         .m = { .min = 2, .max = 256 },
 404         .m1 = { .min = 0, .max = 0 },
 405         .m2 = { .min = 0, .max = 254 },
 406         .p = { .min = 7, .max = 112 },
 407         .p1 = { .min = 1, .max = 8 },
 408         .p2 = { .dot_limit = 112000,
 409                 .p2_slow = 14, .p2_fast = 14 },
 410 };
 411
 412 /* Ironlake / Sandybridge
 413  *
 414  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 415  * the range value for them is (actual_value - 2).
 416  */
 417 static const struct intel_limit intel_limits_ironlake_dac = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 5 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 5, .max = 80 },
 425         .p1 = { .min = 1, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 10, .p2_fast = 5 },
 428 };
 429
 430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 3 },
 434         .m = { .min = 79, .max = 118 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 127 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 56 },
 451         .p1 = { .min = 2, .max = 8 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 /* LVDS 100mhz refclk limits. */
 457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 458         .dot = { .min = 25000, .max = 350000 },
 459         .vco = { .min = 1760000, .max = 3510000 },
 460         .n = { .min = 1, .max = 2 },
 461         .m = { .min = 79, .max = 126 },
 462         .m1 = { .min = 12, .max = 22 },
 463         .m2 = { .min = 5, .max = 9 },
 464         .p = { .min = 28, .max = 112 },
 465         .p1 = { .min = 2, .max = 8 },
 466         .p2 = { .dot_limit = 225000,
 467                 .p2_slow = 14, .p2_fast = 14 },
 468 };
 469
 470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 471         .dot = { .min = 25000, .max = 350000 },
 472         .vco = { .min = 1760000, .max = 3510000 },
 473         .n = { .min = 1, .max = 3 },
 474         .m = { .min = 79, .max = 126 },
 475         .m1 = { .min = 12, .max = 22 },
 476         .m2 = { .min = 5, .max = 9 },
 477         .p = { .min = 14, .max = 42 },
 478         .p1 = { .min = 2, .max = 6 },
 479         .p2 = { .dot_limit = 225000,
 480                 .p2_slow = 7, .p2_fast = 7 },
 481 };
 482
 483 static const struct intel_limit intel_limits_vlv = {
 484          /*
 485           * These are the data rate limits (measured in fast clocks)
 486           * since those are the strictest limits we have. The fast
 487           * clock and actual rate limits are more relaxed, so checking
 488           * them would make no difference.
 489           */
 490         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 491         .vco = { .min = 4000000, .max = 6000000 },
 492         .n = { .min = 1, .max = 7 },
 493         .m1 = { .min = 2, .max = 3 },
 494         .m2 = { .min = 11, .max = 156 },
 495         .p1 = { .min = 2, .max = 3 },
 496         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 497 };
 498
 499 static const struct intel_limit intel_limits_chv = {
 500         /*
 501          * These are the data rate limits (measured in fast clocks)
 502          * since those are the strictest limits we have.  The fast
 503          * clock and actual rate limits are more relaxed, so checking
 504          * them would make no difference.
 505          */
 506         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 507         .vco = { .min = 4800000, .max = 6480000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 511         .p1 = { .min = 2, .max = 4 },
 512         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 513 };
 514
 515 static const struct intel_limit intel_limits_bxt = {
 516         /* FIXME: find real dot limits */
 517         .dot = { .min = 0, .max = INT_MAX },
 518         .vco = { .min = 4800000, .max = 6700000 },
 519         .n = { .min = 1, .max = 1 },
 520         .m1 = { .min = 2, .max = 2 },
 521         /* FIXME: find real m2 limits */
 522         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 523         .p1 = { .min = 2, .max = 4 },
 524         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 525 };
 526
 527 static bool
 528 needs_modeset(struct drm_crtc_state *state)
 529 {
 530         return drm_atomic_crtc_needs_modeset(state);
 531 }
 532
 533 /**
 534  * Returns whether any output on the specified pipe is of the specified type
 535  */
 536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 537 {
 538         struct drm_device *dev = crtc->base.dev;
 539         struct intel_encoder *encoder;
 540
 541         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 542                 if (encoder->type == type)
 543                         return true;
 544
 545         return false;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe will have the specified
 550  * type after a staged modeset is complete, i.e., the same as
 551  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 552  * encoder->crtc.
 553  */
 554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 555                                       int type)
 556 {
 557         struct drm_atomic_state *state = crtc_state->base.state;
 558         struct drm_connector *connector;
 559         struct drm_connector_state *connector_state;
 560         struct intel_encoder *encoder;
 561         int i, num_connectors = 0;
 562
 563         for_each_connector_in_state(state, connector, connector_state, i) {
 564                 if (connector_state->crtc != crtc_state->base.crtc)
 565                         continue;
 566
 567                 num_connectors++;
 568
 569                 encoder = to_intel_encoder(connector_state->best_encoder);
 570                 if (encoder->type == type)
 571                         return true;
 572         }
 573
 574         WARN_ON(num_connectors == 0);
 575
 576         return false;
 577 }
 578
 579 /*
 580  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 581  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 582  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 583  * The helpers' return value is the rate of the clock that is fed to the
 584  * display engine's pipe which can be the above fast dot clock rate or a
 585  * divided-down version of it.
 586  */
 587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 589 {
 590         clock->m = clock->m2 + 2;
 591         clock->p = clock->p1 * clock->p2;
 592         if (WARN_ON(clock->n == 0 || clock->p == 0))
 593                 return 0;
 594         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 595         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 596
 597         return clock->dot;
 598 }
 599
 600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 601 {
 602         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 603 }
 604
 605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 606 {
 607         clock->m = i9xx_dpll_compute_m(clock);
 608         clock->p = clock->p1 * clock->p2;
 609         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 610                 return 0;
 611         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 612         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 613
 614         return clock->dot;
 615 }
 616
 617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 618 {
 619         clock->m = clock->m1 * clock->m2;
 620         clock->p = clock->p1 * clock->p2;
 621         if (WARN_ON(clock->n == 0 || clock->p == 0))
 622                 return 0;
 623         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 624         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 625
 626         return clock->dot / 5;
 627 }
 628
 629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 630 {
 631         clock->m = clock->m1 * clock->m2;
 632         clock->p = clock->p1 * clock->p2;
 633         if (WARN_ON(clock->n == 0 || clock->p == 0))
 634                 return 0;
 635         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 636                         clock->n << 22);
 637         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 638
 639         return clock->dot / 5;
 640 }
 641
 642 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 643 /**
 644  * Returns whether the given set of divisors are valid for a given refclk with
 645  * the given connectors.
 646  */
 647
 648 static bool intel_PLL_is_valid(struct drm_device *dev,
 649                                const struct intel_limit *limit,
 650                                const struct dpll *clock)
 651 {
 652         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 653                 INTELPllInvalid("n out of range\n");
 654         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 655                 INTELPllInvalid("p1 out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid("m1 out of range\n");
 660
 661         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 662             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 663                 if (clock->m1 <= clock->m2)
 664                         INTELPllInvalid("m1 <= m2\n");
 665
 666         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 667                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 668                         INTELPllInvalid("p out of range\n");
 669                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 670                         INTELPllInvalid("m out of range\n");
 671         }
 672
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static int
 685 i9xx_select_p2_div(const struct intel_limit *limit,
 686                    const struct intel_crtc_state *crtc_state,
 687                    int target)
 688 {
 689         struct drm_device *dev = crtc_state->base.crtc->dev;
 690
 691         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 692                 /*
 693                  * For LVDS just rely on its current settings for dual-channel.
 694                  * We haven't figured out how to reliably set up different
 695                  * single/dual channel state, if we even can.
 696                  */
 697                 if (intel_is_dual_link_lvds(dev))
 698                         return limit->p2.p2_fast;
 699                 else
 700                         return limit->p2.p2_slow;
 701         } else {
 702                 if (target < limit->p2.dot_limit)
 703                         return limit->p2.p2_slow;
 704                 else
 705                         return limit->p2.p2_fast;
 706         }
 707 }
 708
 709 /*
 710  * Returns a set of divisors for the desired target clock with the given
 711  * refclk, or FALSE.  The returned values represent the clock equation:
 712  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 713  *
 714  * Target and reference clocks are specified in kHz.
 715  *
 716  * If match_clock is provided, then best_clock P divider must match the P
 717  * divider from @match_clock used for LVDS downclocking.
 718  */
 719 static bool
 720 i9xx_find_best_dpll(const struct intel_limit *limit,
 721                     struct intel_crtc_state *crtc_state,
 722                     int target, int refclk, struct dpll *match_clock,
 723                     struct dpll *best_clock)
 724 {
 725         struct drm_device *dev = crtc_state->base.crtc->dev;
 726         struct dpll clock;
 727         int err = target;
 728
 729         memset(best_clock, 0, sizeof(*best_clock));
 730
 731         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 732
 733         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 734              clock.m1++) {
 735                 for (clock.m2 = limit->m2.min;
 736                      clock.m2 <= limit->m2.max; clock.m2++) {
 737                         if (clock.m2 >= clock.m1)
 738                                 break;
 739                         for (clock.n = limit->n.min;
 740                              clock.n <= limit->n.max; clock.n++) {
 741                                 for (clock.p1 = limit->p1.min;
 742                                         clock.p1 <= limit->p1.max; clock.p1++) {
 743                                         int this_err;
 744
 745                                         i9xx_calc_dpll_params(refclk, &clock);
 746                                         if (!intel_PLL_is_valid(dev, limit,
 747                                                                 &clock))
 748                                                 continue;
 749                                         if (match_clock &&
 750                                             clock.p != match_clock->p)
 751                                                 continue;
 752
 753                                         this_err = abs(clock.dot - target);
 754                                         if (this_err < err) {
 755                                                 *best_clock = clock;
 756                                                 err = this_err;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return (err != target);
 764 }
 765
 766 /*
 767  * Returns a set of divisors for the desired target clock with the given
 768  * refclk, or FALSE.  The returned values represent the clock equation:
 769  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 770  *
 771  * Target and reference clocks are specified in kHz.
 772  *
 773  * If match_clock is provided, then best_clock P divider must match the P
 774  * divider from @match_clock used for LVDS downclocking.
 775  */
 776 static bool
 777 pnv_find_best_dpll(const struct intel_limit *limit,
 778                    struct intel_crtc_state *crtc_state,
 779                    int target, int refclk, struct dpll *match_clock,
 780                    struct dpll *best_clock)
 781 {
 782         struct drm_device *dev = crtc_state->base.crtc->dev;
 783         struct dpll clock;
 784         int err = target;
 785
 786         memset(best_clock, 0, sizeof(*best_clock));
 787
 788         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 789
 790         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 791              clock.m1++) {
 792                 for (clock.m2 = limit->m2.min;
 793                      clock.m2 <= limit->m2.max; clock.m2++) {
 794                         for (clock.n = limit->n.min;
 795                              clock.n <= limit->n.max; clock.n++) {
 796                                 for (clock.p1 = limit->p1.min;
 797                                         clock.p1 <= limit->p1.max; clock.p1++) {
 798                                         int this_err;
 799
 800                                         pnv_calc_dpll_params(refclk, &clock);
 801                                         if (!intel_PLL_is_valid(dev, limit,
 802                                                                 &clock))
 803                                                 continue;
 804                                         if (match_clock &&
 805                                             clock.p != match_clock->p)
 806                                                 continue;
 807
 808                                         this_err = abs(clock.dot - target);
 809                                         if (this_err < err) {
 810                                                 *best_clock = clock;
 811                                                 err = this_err;
 812                                         }
 813                                 }
 814                         }
 815                 }
 816         }
 817
 818         return (err != target);
 819 }
 820
 821 /*
 822  * Returns a set of divisors for the desired target clock with the given
 823  * refclk, or FALSE.  The returned values represent the clock equation:
 824  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 825  *
 826  * Target and reference clocks are specified in kHz.
 827  *
 828  * If match_clock is provided, then best_clock P divider must match the P
 829  * divider from @match_clock used for LVDS downclocking.
 830  */
 831 static bool
 832 g4x_find_best_dpll(const struct intel_limit *limit,
 833                    struct intel_crtc_state *crtc_state,
 834                    int target, int refclk, struct dpll *match_clock,
 835                    struct dpll *best_clock)
 836 {
 837         struct drm_device *dev = crtc_state->base.crtc->dev;
 838         struct dpll clock;
 839         int max_n;
 840         bool found = false;
 841         /* approximately equals target * 0.00585 */
 842         int err_most = (target >> 8) + (target >> 9);
 843
 844         memset(best_clock, 0, sizeof(*best_clock));
 845
 846         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 847
 848         max_n = limit->n.max;
 849         /* based on hardware requirement, prefer smaller n to precision */
 850         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 851                 /* based on hardware requirement, prefere larger m1,m2 */
 852                 for (clock.m1 = limit->m1.max;
 853                      clock.m1 >= limit->m1.min; clock.m1--) {
 854                         for (clock.m2 = limit->m2.max;
 855                              clock.m2 >= limit->m2.min; clock.m2--) {
 856                                 for (clock.p1 = limit->p1.max;
 857                                      clock.p1 >= limit->p1.min; clock.p1--) {
 858                                         int this_err;
 859
 860                                         i9xx_calc_dpll_params(refclk, &clock);
 861                                         if (!intel_PLL_is_valid(dev, limit,
 862                                                                 &clock))
 863                                                 continue;
 864
 865                                         this_err = abs(clock.dot - target);
 866                                         if (this_err < err_most) {
 867                                                 *best_clock = clock;
 868                                                 err_most = this_err;
 869                                                 max_n = clock.n;
 870                                                 found = true;
 871                                         }
 872                                 }
 873                         }
 874                 }
 875         }
 876         return found;
 877 }
 878
 879 /*
 880  * Check if the calculated PLL configuration is more optimal compared to the
 881  * best configuration and error found so far. Return the calculated error.
 882  */
 883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 884                                const struct dpll *calculated_clock,
 885                                const struct dpll *best_clock,
 886                                unsigned int best_error_ppm,
 887                                unsigned int *error_ppm)
 888 {
 889         /*
 890          * For CHV ignore the error and consider only the P value.
 891          * Prefer a bigger P value based on HW requirements.
 892          */
 893         if (IS_CHERRYVIEW(dev)) {
 894                 *error_ppm = 0;
 895
 896                 return calculated_clock->p > best_clock->p;
 897         }
 898
 899         if (WARN_ON_ONCE(!target_freq))
 900                 return false;
 901
 902         *error_ppm = div_u64(1000000ULL *
 903                                 abs(target_freq - calculated_clock->dot),
 904                              target_freq);
 905         /*
 906          * Prefer a better P value over a better (smaller) error if the error
 907          * is small. Ensure this preference for future configurations too by
 908          * setting the error to 0.
 909          */
 910         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 911                 *error_ppm = 0;
 912
 913                 return true;
 914         }
 915
 916         return *error_ppm + 10 < best_error_ppm;
 917 }
 918
 919 /*
 920  * Returns a set of divisors for the desired target clock with the given
 921  * refclk, or FALSE.  The returned values represent the clock equation:
 922  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 923  */
 924 static bool
 925 vlv_find_best_dpll(const struct intel_limit *limit,
 926                    struct intel_crtc_state *crtc_state,
 927                    int target, int refclk, struct dpll *match_clock,
 928                    struct dpll *best_clock)
 929 {
 930         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 931         struct drm_device *dev = crtc->base.dev;
 932         struct dpll clock;
 933         unsigned int bestppm = 1000000;
 934         /* min update 19.2 MHz */
 935         int max_n = min(limit->n.max, refclk / 19200);
 936         bool found = false;
 937
 938         target *= 5; /* fast clock */
 939
 940         memset(best_clock, 0, sizeof(*best_clock));
 941
 942         /* based on hardware requirement, prefer smaller n to precision */
 943         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 944                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 945                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 946                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 947                                 clock.p = clock.p1 * clock.p2;
 948                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 949                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 950                                         unsigned int ppm;
 951
 952                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 953                                                                      refclk * clock.m1);
 954
 955                                         vlv_calc_dpll_params(refclk, &clock);
 956
 957                                         if (!intel_PLL_is_valid(dev, limit,
 958                                                                 &clock))
 959                                                 continue;
 960
 961                                         if (!vlv_PLL_is_optimal(dev, target,
 962                                                                 &clock,
 963                                                                 best_clock,
 964                                                                 bestppm, &ppm))
 965                                                 continue;
 966
 967                                         *best_clock = clock;
 968                                         bestppm = ppm;
 969                                         found = true;
 970                                 }
 971                         }
 972                 }
 973         }
 974
 975         return found;
 976 }
 977
 978 /*
 979  * Returns a set of divisors for the desired target clock with the given
 980  * refclk, or FALSE.  The returned values represent the clock equation:
 981  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 982  */
 983 static bool
 984 chv_find_best_dpll(const struct intel_limit *limit,
 985                    struct intel_crtc_state *crtc_state,
 986                    int target, int refclk, struct dpll *match_clock,
 987                    struct dpll *best_clock)
 988 {
 989         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 990         struct drm_device *dev = crtc->base.dev;
 991         unsigned int best_error_ppm;
 992         struct dpll clock;
 993         uint64_t m2;
 994         int found = false;
 995
 996         memset(best_clock, 0, sizeof(*best_clock));
 997         best_error_ppm = 1000000;
 998
 999         /*
1000          * Based on hardware doc, the n always set to 1, and m1 always
1001          * set to 2.  If requires to support 200Mhz refclk, we need to
1002          * revisit this because n may not 1 anymore.
1003          */
1004         clock.n = 1, clock.m1 = 2;
1005         target *= 5;    /* fast clock */
1006
1007         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008                 for (clock.p2 = limit->p2.p2_fast;
1009                                 clock.p2 >= limit->p2.p2_slow;
1010                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011                         unsigned int error_ppm;
1012
1013                         clock.p = clock.p1 * clock.p2;
1014
1015                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016                                         clock.n) << 22, refclk * clock.m1);
1017
1018                         if (m2 > INT_MAX/clock.m1)
1019                                 continue;
1020
1021                         clock.m2 = m2;
1022
1023                         chv_calc_dpll_params(refclk, &clock);
1024
1025                         if (!intel_PLL_is_valid(dev, limit, &clock))
1026                                 continue;
1027
1028                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029                                                 best_error_ppm, &error_ppm))
1030                                 continue;
1031
1032                         *best_clock = clock;
1033                         best_error_ppm = error_ppm;
1034                         found = true;
1035                 }
1036         }
1037
1038         return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042                         struct dpll *best_clock)
1043 {
1044         int refclk = 100000;
1045         const struct intel_limit *limit = &intel_limits_bxt;
1046
1047         return chv_find_best_dpll(limit, crtc_state,
1048                                   target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055         /* Be paranoid as we can arrive here with only partial
1056          * state retrieved from the hardware during setup.
1057          *
1058          * We can ditch the adjusted_mode.crtc_clock check as soon
1059          * as Haswell has gained clock readout/fastboot support.
1060          *
1061          * We can ditch the crtc->primary->fb check as soon as we can
1062          * properly reconstruct framebuffers.
1063          *
1064          * FIXME: The intel_crtc->active here should be switched to
1065          * crtc->state->active once we have proper CRTC states wired up
1066          * for atomic.
1067          */
1068         return intel_crtc->active && crtc->primary->state->fb &&
1069                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073                                              enum pipe pipe)
1074 {
1075         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078         return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         i915_reg_t reg = PIPEDSL(pipe);
1085         u32 line1, line2;
1086         u32 line_mask;
1087
1088         if (IS_GEN2(dev))
1089                 line_mask = DSL_LINEMASK_GEN2;
1090         else
1091                 line_mask = DSL_LINEMASK_GEN3;
1092
1093         line1 = I915_READ(reg) & line_mask;
1094         msleep(5);
1095         line2 = I915_READ(reg) & line_mask;
1096
1097         return line1 == line2;
1098 }
1099
1100 /*
1101  * intel_wait_for_pipe_off - wait for pipe to turn off
1102  * @crtc: crtc whose pipe to wait for
1103  *
1104  * After disabling a pipe, we can't wait for vblank in the usual way,
1105  * spinning on the vblank interrupt status bit, since we won't actually
1106  * see an interrupt when the pipe is disabled.
1107  *
1108  * On Gen4 and above:
1109  *   wait for the pipe register state bit to turn off
1110  *
1111  * Otherwise:
1112  *   wait for the display line value to settle (it usually
1113  *   ends up stopping at the start of the next frame).
1114  *
1115  */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118         struct drm_device *dev = crtc->base.dev;
1119         struct drm_i915_private *dev_priv = dev->dev_private;
1120         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121         enum pipe pipe = crtc->pipe;
1122
1123         if (INTEL_INFO(dev)->gen >= 4) {
1124                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126                 /* Wait for the Pipe State to go off */
1127                 if (intel_wait_for_register(dev_priv,
1128                                             reg, I965_PIPECONF_ACTIVE, 0,
1129                                             100))
1130                         WARN(1, "pipe_off wait timed out\n");
1131         } else {
1132                 /* Wait for the display line to settle */
1133                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1134                         WARN(1, "pipe_off wait timed out\n");
1135         }
1136 }
1137
1138 /* Only for pre-ILK configs */
1139 void assert_pll(struct drm_i915_private *dev_priv,
1140                 enum pipe pipe, bool state)
1141 {
1142         u32 val;
1143         bool cur_state;
1144
1145         val = I915_READ(DPLL(pipe));
1146         cur_state = !!(val & DPLL_VCO_ENABLE);
1147         I915_STATE_WARN(cur_state != state,
1148              "PLL state assertion failure (expected %s, current %s)\n",
1149                         onoff(state), onoff(cur_state));
1150 }
1151
1152 /* XXX: the dsi pll is shared between MIPI DSI ports */
1153 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1154 {
1155         u32 val;
1156         bool cur_state;
1157
1158         mutex_lock(&dev_priv->sb_lock);
1159         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1160         mutex_unlock(&dev_priv->sb_lock);
1161
1162         cur_state = val & DSI_PLL_VCO_EN;
1163         I915_STATE_WARN(cur_state != state,
1164              "DSI PLL state assertion failure (expected %s, current %s)\n",
1165                         onoff(state), onoff(cur_state));
1166 }
1167
1168 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1169                           enum pipe pipe, bool state)
1170 {
1171         bool cur_state;
1172         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1173                                                                       pipe);
1174
1175         if (HAS_DDI(dev_priv)) {
1176                 /* DDI does not have a specific FDI_TX register */
1177                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1178                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1179         } else {
1180                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1181                 cur_state = !!(val & FDI_TX_ENABLE);
1182         }
1183         I915_STATE_WARN(cur_state != state,
1184              "FDI TX state assertion failure (expected %s, current %s)\n",
1185                         onoff(state), onoff(cur_state));
1186 }
1187 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1188 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1189
1190 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1191                           enum pipe pipe, bool state)
1192 {
1193         u32 val;
1194         bool cur_state;
1195
1196         val = I915_READ(FDI_RX_CTL(pipe));
1197         cur_state = !!(val & FDI_RX_ENABLE);
1198         I915_STATE_WARN(cur_state != state,
1199              "FDI RX state assertion failure (expected %s, current %s)\n",
1200                         onoff(state), onoff(cur_state));
1201 }
1202 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1203 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1204
1205 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1206                                       enum pipe pipe)
1207 {
1208         u32 val;
1209
1210         /* ILK FDI PLL is always enabled */
1211         if (IS_GEN5(dev_priv))
1212                 return;
1213
1214         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1215         if (HAS_DDI(dev_priv))
1216                 return;
1217
1218         val = I915_READ(FDI_TX_CTL(pipe));
1219         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1220 }
1221
1222 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1223                        enum pipe pipe, bool state)
1224 {
1225         u32 val;
1226         bool cur_state;
1227
1228         val = I915_READ(FDI_RX_CTL(pipe));
1229         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1230         I915_STATE_WARN(cur_state != state,
1231              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1232                         onoff(state), onoff(cur_state));
1233 }
1234
1235 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1236                            enum pipe pipe)
1237 {
1238         struct drm_device *dev = dev_priv->dev;
1239         i915_reg_t pp_reg;
1240         u32 val;
1241         enum pipe panel_pipe = PIPE_A;
1242         bool locked = true;
1243
1244         if (WARN_ON(HAS_DDI(dev)))
1245                 return;
1246
1247         if (HAS_PCH_SPLIT(dev)) {
1248                 u32 port_sel;
1249
1250                 pp_reg = PCH_PP_CONTROL;
1251                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1252
1253                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1254                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1255                         panel_pipe = PIPE_B;
1256                 /* XXX: else fix for eDP */
1257         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1258                 /* presumably write lock depends on pipe, not port select */
1259                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1260                 panel_pipe = pipe;
1261         } else {
1262                 pp_reg = PP_CONTROL;
1263                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1264                         panel_pipe = PIPE_B;
1265         }
1266
1267         val = I915_READ(pp_reg);
1268         if (!(val & PANEL_POWER_ON) ||
1269             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1270                 locked = false;
1271
1272         I915_STATE_WARN(panel_pipe == pipe && locked,
1273              "panel assertion failure, pipe %c regs locked\n",
1274              pipe_name(pipe));
1275 }
1276
1277 static void assert_cursor(struct drm_i915_private *dev_priv,
1278                           enum pipe pipe, bool state)
1279 {
1280         struct drm_device *dev = dev_priv->dev;
1281         bool cur_state;
1282
1283         if (IS_845G(dev) || IS_I865G(dev))
1284                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1285         else
1286                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1287
1288         I915_STATE_WARN(cur_state != state,
1289              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1290                         pipe_name(pipe), onoff(state), onoff(cur_state));
1291 }
1292 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1293 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1294
1295 void assert_pipe(struct drm_i915_private *dev_priv,
1296                  enum pipe pipe, bool state)
1297 {
1298         bool cur_state;
1299         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1300                                                                       pipe);
1301         enum intel_display_power_domain power_domain;
1302
1303         /* if we need the pipe quirk it must be always on */
1304         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1306                 state = true;
1307
1308         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1309         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1310                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1311                 cur_state = !!(val & PIPECONF_ENABLE);
1312
1313                 intel_display_power_put(dev_priv, power_domain);
1314         } else {
1315                 cur_state = false;
1316         }
1317
1318         I915_STATE_WARN(cur_state != state,
1319              "pipe %c assertion failure (expected %s, current %s)\n",
1320                         pipe_name(pipe), onoff(state), onoff(cur_state));
1321 }
1322
1323 static void assert_plane(struct drm_i915_private *dev_priv,
1324                          enum plane plane, bool state)
1325 {
1326         u32 val;
1327         bool cur_state;
1328
1329         val = I915_READ(DSPCNTR(plane));
1330         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1331         I915_STATE_WARN(cur_state != state,
1332              "plane %c assertion failure (expected %s, current %s)\n",
1333                         plane_name(plane), onoff(state), onoff(cur_state));
1334 }
1335
1336 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1337 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338
1339 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1340                                    enum pipe pipe)
1341 {
1342         struct drm_device *dev = dev_priv->dev;
1343         int i;
1344
1345         /* Primary planes are fixed to pipes on gen4+ */
1346         if (INTEL_INFO(dev)->gen >= 4) {
1347                 u32 val = I915_READ(DSPCNTR(pipe));
1348                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1349                      "plane %c assertion failure, should be disabled but not\n",
1350                      plane_name(pipe));
1351                 return;
1352         }
1353
1354         /* Need to check both planes against the pipe */
1355         for_each_pipe(dev_priv, i) {
1356                 u32 val = I915_READ(DSPCNTR(i));
1357                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1358                         DISPPLANE_SEL_PIPE_SHIFT;
1359                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1360                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1361                      plane_name(i), pipe_name(pipe));
1362         }
1363 }
1364
1365 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1366                                     enum pipe pipe)
1367 {
1368         struct drm_device *dev = dev_priv->dev;
1369         int sprite;
1370
1371         if (INTEL_INFO(dev)->gen >= 9) {
1372                 for_each_sprite(dev_priv, pipe, sprite) {
1373                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1374                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1375                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1376                              sprite, pipe_name(pipe));
1377                 }
1378         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1379                 for_each_sprite(dev_priv, pipe, sprite) {
1380                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1381                         I915_STATE_WARN(val & SP_ENABLE,
1382                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383                              sprite_name(pipe, sprite), pipe_name(pipe));
1384                 }
1385         } else if (INTEL_INFO(dev)->gen >= 7) {
1386                 u32 val = I915_READ(SPRCTL(pipe));
1387                 I915_STATE_WARN(val & SPRITE_ENABLE,
1388                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(pipe), pipe_name(pipe));
1390         } else if (INTEL_INFO(dev)->gen >= 5) {
1391                 u32 val = I915_READ(DVSCNTR(pipe));
1392                 I915_STATE_WARN(val & DVS_ENABLE,
1393                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1394                      plane_name(pipe), pipe_name(pipe));
1395         }
1396 }
1397
1398 static void assert_vblank_disabled(struct drm_crtc *crtc)
1399 {
1400         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1401                 drm_crtc_vblank_put(crtc);
1402 }
1403
1404 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1405                                     enum pipe pipe)
1406 {
1407         u32 val;
1408         bool enabled;
1409
1410         val = I915_READ(PCH_TRANSCONF(pipe));
1411         enabled = !!(val & TRANS_ENABLE);
1412         I915_STATE_WARN(enabled,
1413              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1414              pipe_name(pipe));
1415 }
1416
1417 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1418                             enum pipe pipe, u32 port_sel, u32 val)
1419 {
1420         if ((val & DP_PORT_EN) == 0)
1421                 return false;
1422
1423         if (HAS_PCH_CPT(dev_priv)) {
1424                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1425                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1426                         return false;
1427         } else if (IS_CHERRYVIEW(dev_priv)) {
1428                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1438                               enum pipe pipe, u32 val)
1439 {
1440         if ((val & SDVO_ENABLE) == 0)
1441                 return false;
1442
1443         if (HAS_PCH_CPT(dev_priv)) {
1444                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1445                         return false;
1446         } else if (IS_CHERRYVIEW(dev_priv)) {
1447                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1448                         return false;
1449         } else {
1450                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1451                         return false;
1452         }
1453         return true;
1454 }
1455
1456 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1457                               enum pipe pipe, u32 val)
1458 {
1459         if ((val & LVDS_PORT_EN) == 0)
1460                 return false;
1461
1462         if (HAS_PCH_CPT(dev_priv)) {
1463                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1464                         return false;
1465         } else {
1466                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1467                         return false;
1468         }
1469         return true;
1470 }
1471
1472 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1473                               enum pipe pipe, u32 val)
1474 {
1475         if ((val & ADPA_DAC_ENABLE) == 0)
1476                 return false;
1477         if (HAS_PCH_CPT(dev_priv)) {
1478                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1479                         return false;
1480         } else {
1481                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1482                         return false;
1483         }
1484         return true;
1485 }
1486
1487 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1488                                    enum pipe pipe, i915_reg_t reg,
1489                                    u32 port_sel)
1490 {
1491         u32 val = I915_READ(reg);
1492         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1493              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1494              i915_mmio_reg_offset(reg), pipe_name(pipe));
1495
1496         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1497              && (val & DP_PIPEB_SELECT),
1498              "IBX PCH dp port still using transcoder B\n");
1499 }
1500
1501 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1502                                      enum pipe pipe, i915_reg_t reg)
1503 {
1504         u32 val = I915_READ(reg);
1505         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1506              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1507              i915_mmio_reg_offset(reg), pipe_name(pipe));
1508
1509         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1510              && (val & SDVO_PIPE_B_SELECT),
1511              "IBX PCH hdmi port still using transcoder B\n");
1512 }
1513
1514 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1515                                       enum pipe pipe)
1516 {
1517         u32 val;
1518
1519         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1520         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1521         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1522
1523         val = I915_READ(PCH_ADPA);
1524         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1525              "PCH VGA enabled on transcoder %c, should be disabled\n",
1526              pipe_name(pipe));
1527
1528         val = I915_READ(PCH_LVDS);
1529         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1530              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1531              pipe_name(pipe));
1532
1533         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1534         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1535         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1536 }
1537
1538 static void _vlv_enable_pll(struct intel_crtc *crtc,
1539                             const struct intel_crtc_state *pipe_config)
1540 {
1541         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1542         enum pipe pipe = crtc->pipe;
1543
1544         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1545         POSTING_READ(DPLL(pipe));
1546         udelay(150);
1547
1548         if (intel_wait_for_register(dev_priv,
1549                                     DPLL(pipe),
1550                                     DPLL_LOCK_VLV,
1551                                     DPLL_LOCK_VLV,
1552                                     1))
1553                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1554 }
1555
1556 static void vlv_enable_pll(struct intel_crtc *crtc,
1557                            const struct intel_crtc_state *pipe_config)
1558 {
1559         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1560         enum pipe pipe = crtc->pipe;
1561
1562         assert_pipe_disabled(dev_priv, pipe);
1563
1564         /* PLL is protected by panel, make sure we can write it */
1565         assert_panel_unlocked(dev_priv, pipe);
1566
1567         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1568                 _vlv_enable_pll(crtc, pipe_config);
1569
1570         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1571         POSTING_READ(DPLL_MD(pipe));
1572 }
1573
1574
1575 static void _chv_enable_pll(struct intel_crtc *crtc,
1576                             const struct intel_crtc_state *pipe_config)
1577 {
1578         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1579         enum pipe pipe = crtc->pipe;
1580         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1581         u32 tmp;
1582
1583         mutex_lock(&dev_priv->sb_lock);
1584
1585         /* Enable back the 10bit clock to display controller */
1586         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587         tmp |= DPIO_DCLKP_EN;
1588         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590         mutex_unlock(&dev_priv->sb_lock);
1591
1592         /*
1593          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1594          */
1595         udelay(1);
1596
1597         /* Enable PLL */
1598         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1599
1600         /* Check PLL is locked */
1601         if (intel_wait_for_register(dev_priv,
1602                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1603                                     1))
1604                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1605 }
1606
1607 static void chv_enable_pll(struct intel_crtc *crtc,
1608                            const struct intel_crtc_state *pipe_config)
1609 {
1610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1611         enum pipe pipe = crtc->pipe;
1612
1613         assert_pipe_disabled(dev_priv, pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         assert_panel_unlocked(dev_priv, pipe);
1617
1618         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1619                 _chv_enable_pll(crtc, pipe_config);
1620
1621         if (pipe != PIPE_A) {
1622                 /*
1623                  * WaPixelRepeatModeFixForC0:chv
1624                  *
1625                  * DPLLCMD is AWOL. Use chicken bits to propagate
1626                  * the value from DPLLBMD to either pipe B or C.
1627                  */
1628                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1629                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1630                 I915_WRITE(CBR4_VLV, 0);
1631                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1632
1633                 /*
1634                  * DPLLB VGA mode also seems to cause problems.
1635                  * We should always have it disabled.
1636                  */
1637                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1638         } else {
1639                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640                 POSTING_READ(DPLL_MD(pipe));
1641         }
1642 }
1643
1644 static int intel_num_dvo_pipes(struct drm_device *dev)
1645 {
1646         struct intel_crtc *crtc;
1647         int count = 0;
1648
1649         for_each_intel_crtc(dev, crtc)
1650                 count += crtc->base.state->active &&
1651                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1652
1653         return count;
1654 }
1655
1656 static void i9xx_enable_pll(struct intel_crtc *crtc)
1657 {
1658         struct drm_device *dev = crtc->base.dev;
1659         struct drm_i915_private *dev_priv = dev->dev_private;
1660         i915_reg_t reg = DPLL(crtc->pipe);
1661         u32 dpll = crtc->config->dpll_hw_state.dpll;
1662
1663         assert_pipe_disabled(dev_priv, crtc->pipe);
1664
1665         /* PLL is protected by panel, make sure we can write it */
1666         if (IS_MOBILE(dev) && !IS_I830(dev))
1667                 assert_panel_unlocked(dev_priv, crtc->pipe);
1668
1669         /* Enable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1671                 /*
1672                  * It appears to be important that we don't enable this
1673                  * for the current pipe before otherwise configuring the
1674                  * PLL. No idea how this should be handled if multiple
1675                  * DVO outputs are enabled simultaneosly.
1676                  */
1677                 dpll |= DPLL_DVO_2X_MODE;
1678                 I915_WRITE(DPLL(!crtc->pipe),
1679                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1680         }
1681
1682         /*
1683          * Apparently we need to have VGA mode enabled prior to changing
1684          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1685          * dividers, even though the register value does change.
1686          */
1687         I915_WRITE(reg, 0);
1688
1689         I915_WRITE(reg, dpll);
1690
1691         /* Wait for the clocks to stabilize. */
1692         POSTING_READ(reg);
1693         udelay(150);
1694
1695         if (INTEL_INFO(dev)->gen >= 4) {
1696                 I915_WRITE(DPLL_MD(crtc->pipe),
1697                            crtc->config->dpll_hw_state.dpll_md);
1698         } else {
1699                 /* The pixel multiplier can only be updated once the
1700                  * DPLL is enabled and the clocks are stable.
1701                  *
1702                  * So write it again.
1703                  */
1704                 I915_WRITE(reg, dpll);
1705         }
1706
1707         /* We do this three times for luck */
1708         I915_WRITE(reg, dpll);
1709         POSTING_READ(reg);
1710         udelay(150); /* wait for warmup */
1711         I915_WRITE(reg, dpll);
1712         POSTING_READ(reg);
1713         udelay(150); /* wait for warmup */
1714         I915_WRITE(reg, dpll);
1715         POSTING_READ(reg);
1716         udelay(150); /* wait for warmup */
1717 }
1718
1719 /**
1720  * i9xx_disable_pll - disable a PLL
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe PLL to disable
1723  *
1724  * Disable the PLL for @pipe, making sure the pipe is off first.
1725  *
1726  * Note!  This is for pre-ILK only.
1727  */
1728 static void i9xx_disable_pll(struct intel_crtc *crtc)
1729 {
1730         struct drm_device *dev = crtc->base.dev;
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         enum pipe pipe = crtc->pipe;
1733
1734         /* Disable DVO 2x clock on both PLLs if necessary */
1735         if (IS_I830(dev) &&
1736             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1737             !intel_num_dvo_pipes(dev)) {
1738                 I915_WRITE(DPLL(PIPE_B),
1739                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1740                 I915_WRITE(DPLL(PIPE_A),
1741                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1742         }
1743
1744         /* Don't disable pipe or pipe PLLs if needed */
1745         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1746             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1747                 return;
1748
1749         /* Make sure the pipe isn't still relying on us */
1750         assert_pipe_disabled(dev_priv, pipe);
1751
1752         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1753         POSTING_READ(DPLL(pipe));
1754 }
1755
1756 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758         u32 val;
1759
1760         /* Make sure the pipe isn't still relying on us */
1761         assert_pipe_disabled(dev_priv, pipe);
1762
1763         val = DPLL_INTEGRATED_REF_CLK_VLV |
1764                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1765         if (pipe != PIPE_A)
1766                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1767
1768         I915_WRITE(DPLL(pipe), val);
1769         POSTING_READ(DPLL(pipe));
1770 }
1771
1772 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1773 {
1774         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1775         u32 val;
1776
1777         /* Make sure the pipe isn't still relying on us */
1778         assert_pipe_disabled(dev_priv, pipe);
1779
1780         val = DPLL_SSC_REF_CLK_CHV |
1781                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1782         if (pipe != PIPE_A)
1783                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1784
1785         I915_WRITE(DPLL(pipe), val);
1786         POSTING_READ(DPLL(pipe));
1787
1788         mutex_lock(&dev_priv->sb_lock);
1789
1790         /* Disable 10bit clock to display controller */
1791         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1792         val &= ~DPIO_DCLKP_EN;
1793         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1794
1795         mutex_unlock(&dev_priv->sb_lock);
1796 }
1797
1798 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1799                          struct intel_digital_port *dport,
1800                          unsigned int expected_mask)
1801 {
1802         u32 port_mask;
1803         i915_reg_t dpll_reg;
1804
1805         switch (dport->port) {
1806         case PORT_B:
1807                 port_mask = DPLL_PORTB_READY_MASK;
1808                 dpll_reg = DPLL(0);
1809                 break;
1810         case PORT_C:
1811                 port_mask = DPLL_PORTC_READY_MASK;
1812                 dpll_reg = DPLL(0);
1813                 expected_mask <<= 4;
1814                 break;
1815         case PORT_D:
1816                 port_mask = DPLL_PORTD_READY_MASK;
1817                 dpll_reg = DPIO_PHY_STATUS;
1818                 break;
1819         default:
1820                 BUG();
1821         }
1822
1823         if (intel_wait_for_register(dev_priv,
1824                                     dpll_reg, port_mask, expected_mask,
1825                                     1000))
1826                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1827                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1828 }
1829
1830 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1831                                            enum pipe pipe)
1832 {
1833         struct drm_device *dev = dev_priv->dev;
1834         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1836         i915_reg_t reg;
1837         uint32_t val, pipeconf_val;
1838
1839         /* Make sure PCH DPLL is enabled */
1840         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, pipe);
1844         assert_fdi_rx_enabled(dev_priv, pipe);
1845
1846         if (HAS_PCH_CPT(dev)) {
1847                 /* Workaround: Set the timing override bit before enabling the
1848                  * pch transcoder. */
1849                 reg = TRANS_CHICKEN2(pipe);
1850                 val = I915_READ(reg);
1851                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1852                 I915_WRITE(reg, val);
1853         }
1854
1855         reg = PCH_TRANSCONF(pipe);
1856         val = I915_READ(reg);
1857         pipeconf_val = I915_READ(PIPECONF(pipe));
1858
1859         if (HAS_PCH_IBX(dev_priv)) {
1860                 /*
1861                  * Make the BPC in transcoder be consistent with
1862                  * that in pipeconf reg. For HDMI we must use 8bpc
1863                  * here for both 8bpc and 12bpc.
1864                  */
1865                 val &= ~PIPECONF_BPC_MASK;
1866                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1867                         val |= PIPECONF_8BPC;
1868                 else
1869                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1870         }
1871
1872         val &= ~TRANS_INTERLACE_MASK;
1873         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874                 if (HAS_PCH_IBX(dev_priv) &&
1875                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1876                         val |= TRANS_LEGACY_INTERLACED_ILK;
1877                 else
1878                         val |= TRANS_INTERLACED;
1879         else
1880                 val |= TRANS_PROGRESSIVE;
1881
1882         I915_WRITE(reg, val | TRANS_ENABLE);
1883         if (intel_wait_for_register(dev_priv,
1884                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1885                                     100))
1886                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1887 }
1888
1889 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1890                                       enum transcoder cpu_transcoder)
1891 {
1892         u32 val, pipeconf_val;
1893
1894         /* FDI must be feeding us bits for PCH ports */
1895         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1896         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1897
1898         /* Workaround: set timing override bit. */
1899         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1900         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1901         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1902
1903         val = TRANS_ENABLE;
1904         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1905
1906         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1907             PIPECONF_INTERLACED_ILK)
1908                 val |= TRANS_INTERLACED;
1909         else
1910                 val |= TRANS_PROGRESSIVE;
1911
1912         I915_WRITE(LPT_TRANSCONF, val);
1913         if (intel_wait_for_register(dev_priv,
1914                                     LPT_TRANSCONF,
1915                                     TRANS_STATE_ENABLE,
1916                                     TRANS_STATE_ENABLE,
1917                                     100))
1918                 DRM_ERROR("Failed to enable PCH transcoder\n");
1919 }
1920
1921 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                             enum pipe pipe)
1923 {
1924         struct drm_device *dev = dev_priv->dev;
1925         i915_reg_t reg;
1926         uint32_t val;
1927
1928         /* FDI relies on the transcoder */
1929         assert_fdi_tx_disabled(dev_priv, pipe);
1930         assert_fdi_rx_disabled(dev_priv, pipe);
1931
1932         /* Ports must be off as well */
1933         assert_pch_ports_disabled(dev_priv, pipe);
1934
1935         reg = PCH_TRANSCONF(pipe);
1936         val = I915_READ(reg);
1937         val &= ~TRANS_ENABLE;
1938         I915_WRITE(reg, val);
1939         /* wait for PCH transcoder off, transcoder state */
1940         if (intel_wait_for_register(dev_priv,
1941                                     reg, TRANS_STATE_ENABLE, 0,
1942                                     50))
1943                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1944
1945         if (HAS_PCH_CPT(dev)) {
1946                 /* Workaround: Clear the timing override chicken bit again. */
1947                 reg = TRANS_CHICKEN2(pipe);
1948                 val = I915_READ(reg);
1949                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950                 I915_WRITE(reg, val);
1951         }
1952 }
1953
1954 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1955 {
1956         u32 val;
1957
1958         val = I915_READ(LPT_TRANSCONF);
1959         val &= ~TRANS_ENABLE;
1960         I915_WRITE(LPT_TRANSCONF, val);
1961         /* wait for PCH transcoder off, transcoder state */
1962         if (intel_wait_for_register(dev_priv,
1963                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1964                                     50))
1965                 DRM_ERROR("Failed to disable PCH transcoder\n");
1966
1967         /* Workaround: clear timing override bit. */
1968         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1969         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1970         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1971 }
1972
1973 /**
1974  * intel_enable_pipe - enable a pipe, asserting requirements
1975  * @crtc: crtc responsible for the pipe
1976  *
1977  * Enable @crtc's pipe, making sure that various hardware specific requirements
1978  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1979  */
1980 static void intel_enable_pipe(struct intel_crtc *crtc)
1981 {
1982         struct drm_device *dev = crtc->base.dev;
1983         struct drm_i915_private *dev_priv = dev->dev_private;
1984         enum pipe pipe = crtc->pipe;
1985         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1986         enum pipe pch_transcoder;
1987         i915_reg_t reg;
1988         u32 val;
1989
1990         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1991
1992         assert_planes_disabled(dev_priv, pipe);
1993         assert_cursor_disabled(dev_priv, pipe);
1994         assert_sprites_disabled(dev_priv, pipe);
1995
1996         if (HAS_PCH_LPT(dev_priv))
1997                 pch_transcoder = TRANSCODER_A;
1998         else
1999                 pch_transcoder = pipe;
2000
2001         /*
2002          * A pipe without a PLL won't actually be able to drive bits from
2003          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2004          * need the check.
2005          */
2006         if (HAS_GMCH_DISPLAY(dev_priv))
2007                 if (crtc->config->has_dsi_encoder)
2008                         assert_dsi_pll_enabled(dev_priv);
2009                 else
2010                         assert_pll_enabled(dev_priv, pipe);
2011         else {
2012                 if (crtc->config->has_pch_encoder) {
2013                         /* if driving the PCH, we need FDI enabled */
2014                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2015                         assert_fdi_tx_pll_enabled(dev_priv,
2016                                                   (enum pipe) cpu_transcoder);
2017                 }
2018                 /* FIXME: assert CPU port conditions for SNB+ */
2019         }
2020
2021         reg = PIPECONF(cpu_transcoder);
2022         val = I915_READ(reg);
2023         if (val & PIPECONF_ENABLE) {
2024                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2025                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2026                 return;
2027         }
2028
2029         I915_WRITE(reg, val | PIPECONF_ENABLE);
2030         POSTING_READ(reg);
2031
2032         /*
2033          * Until the pipe starts DSL will read as 0, which would cause
2034          * an apparent vblank timestamp jump, which messes up also the
2035          * frame count when it's derived from the timestamps. So let's
2036          * wait for the pipe to start properly before we call
2037          * drm_crtc_vblank_on()
2038          */
2039         if (dev->max_vblank_count == 0 &&
2040             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2041                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2042 }
2043
2044 /**
2045  * intel_disable_pipe - disable a pipe, asserting requirements
2046  * @crtc: crtc whose pipes is to be disabled
2047  *
2048  * Disable the pipe of @crtc, making sure that various hardware
2049  * specific requirements are met, if applicable, e.g. plane
2050  * disabled, panel fitter off, etc.
2051  *
2052  * Will wait until the pipe has shut down before returning.
2053  */
2054 static void intel_disable_pipe(struct intel_crtc *crtc)
2055 {
2056         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2057         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2058         enum pipe pipe = crtc->pipe;
2059         i915_reg_t reg;
2060         u32 val;
2061
2062         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2063
2064         /*
2065          * Make sure planes won't keep trying to pump pixels to us,
2066          * or we might hang the display.
2067          */
2068         assert_planes_disabled(dev_priv, pipe);
2069         assert_cursor_disabled(dev_priv, pipe);
2070         assert_sprites_disabled(dev_priv, pipe);
2071
2072         reg = PIPECONF(cpu_transcoder);
2073         val = I915_READ(reg);
2074         if ((val & PIPECONF_ENABLE) == 0)
2075                 return;
2076
2077         /*
2078          * Double wide has implications for planes
2079          * so best keep it disabled when not needed.
2080          */
2081         if (crtc->config->double_wide)
2082                 val &= ~PIPECONF_DOUBLE_WIDE;
2083
2084         /* Don't disable pipe or pipe PLLs if needed */
2085         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2086             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2087                 val &= ~PIPECONF_ENABLE;
2088
2089         I915_WRITE(reg, val);
2090         if ((val & PIPECONF_ENABLE) == 0)
2091                 intel_wait_for_pipe_off(crtc);
2092 }
2093
2094 static bool need_vtd_wa(struct drm_device *dev)
2095 {
2096 #ifdef CONFIG_INTEL_IOMMU
2097         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2098                 return true;
2099 #endif
2100         return false;
2101 }
2102
2103 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2104 {
2105         return IS_GEN2(dev_priv) ? 2048 : 4096;
2106 }
2107
2108 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2109                                            uint64_t fb_modifier, unsigned int cpp)
2110 {
2111         switch (fb_modifier) {
2112         case DRM_FORMAT_MOD_NONE:
2113                 return cpp;
2114         case I915_FORMAT_MOD_X_TILED:
2115                 if (IS_GEN2(dev_priv))
2116                         return 128;
2117                 else
2118                         return 512;
2119         case I915_FORMAT_MOD_Y_TILED:
2120                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2121                         return 128;
2122                 else
2123                         return 512;
2124         case I915_FORMAT_MOD_Yf_TILED:
2125                 switch (cpp) {
2126                 case 1:
2127                         return 64;
2128                 case 2:
2129                 case 4:
2130                         return 128;
2131                 case 8:
2132                 case 16:
2133                         return 256;
2134                 default:
2135                         MISSING_CASE(cpp);
2136                         return cpp;
2137                 }
2138                 break;
2139         default:
2140                 MISSING_CASE(fb_modifier);
2141                 return cpp;
2142         }
2143 }
2144
2145 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2146                                uint64_t fb_modifier, unsigned int cpp)
2147 {
2148         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2149                 return 1;
2150         else
2151                 return intel_tile_size(dev_priv) /
2152                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2153 }
2154
2155 /* Return the tile dimensions in pixel units */
2156 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2157                             unsigned int *tile_width,
2158                             unsigned int *tile_height,
2159                             uint64_t fb_modifier,
2160                             unsigned int cpp)
2161 {
2162         unsigned int tile_width_bytes =
2163                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2164
2165         *tile_width = tile_width_bytes / cpp;
2166         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2167 }
2168
2169 unsigned int
2170 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2171                       uint32_t pixel_format, uint64_t fb_modifier)
2172 {
2173         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2174         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2175
2176         return ALIGN(height, tile_height);
2177 }
2178
2179 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2180 {
2181         unsigned int size = 0;
2182         int i;
2183
2184         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2185                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2186
2187         return size;
2188 }
2189
2190 static void
2191 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2192                         const struct drm_framebuffer *fb,
2193                         unsigned int rotation)
2194 {
2195         if (intel_rotation_90_or_270(rotation)) {
2196                 *view = i915_ggtt_view_rotated;
2197                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2198         } else {
2199                 *view = i915_ggtt_view_normal;
2200         }
2201 }
2202
2203 static void
2204 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2205                    struct drm_framebuffer *fb)
2206 {
2207         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2208         unsigned int tile_size, tile_width, tile_height, cpp;
2209
2210         tile_size = intel_tile_size(dev_priv);
2211
2212         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2213         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2214                         fb->modifier[0], cpp);
2215
2216         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2217         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2218
2219         if (info->pixel_format == DRM_FORMAT_NV12) {
2220                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2221                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2222                                 fb->modifier[1], cpp);
2223
2224                 info->uv_offset = fb->offsets[1];
2225                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2226                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2227         }
2228 }
2229
2230 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2231 {
2232         if (INTEL_INFO(dev_priv)->gen >= 9)
2233                 return 256 * 1024;
2234         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2235                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2236                 return 128 * 1024;
2237         else if (INTEL_INFO(dev_priv)->gen >= 4)
2238                 return 4 * 1024;
2239         else
2240                 return 0;
2241 }
2242
2243 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2244                                          uint64_t fb_modifier)
2245 {
2246         switch (fb_modifier) {
2247         case DRM_FORMAT_MOD_NONE:
2248                 return intel_linear_alignment(dev_priv);
2249         case I915_FORMAT_MOD_X_TILED:
2250                 if (INTEL_INFO(dev_priv)->gen >= 9)
2251                         return 256 * 1024;
2252                 return 0;
2253         case I915_FORMAT_MOD_Y_TILED:
2254         case I915_FORMAT_MOD_Yf_TILED:
2255                 return 1 * 1024 * 1024;
2256         default:
2257                 MISSING_CASE(fb_modifier);
2258                 return 0;
2259         }
2260 }
2261
2262 int
2263 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2264                            unsigned int rotation)
2265 {
2266         struct drm_device *dev = fb->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2269         struct i915_ggtt_view view;
2270         u32 alignment;
2271         int ret;
2272
2273         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2274
2275         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2276
2277         intel_fill_fb_ggtt_view(&view, fb, rotation);
2278
2279         /* Note that the w/a also requires 64 PTE of padding following the
2280          * bo. We currently fill all unused PTE with the shadow page and so
2281          * we should always have valid PTE following the scanout preventing
2282          * the VT-d warning.
2283          */
2284         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2285                 alignment = 256 * 1024;
2286
2287         /*
2288          * Global gtt pte registers are special registers which actually forward
2289          * writes to a chunk of system memory. Which means that there is no risk
2290          * that the register values disappear as soon as we call
2291          * intel_runtime_pm_put(), so it is correct to wrap only the
2292          * pin/unpin/fence and not more.
2293          */
2294         intel_runtime_pm_get(dev_priv);
2295
2296         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2297                                                    &view);
2298         if (ret)
2299                 goto err_pm;
2300
2301         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2302          * fence, whereas 965+ only requires a fence if using
2303          * framebuffer compression.  For simplicity, we always install
2304          * a fence as the cost is not that onerous.
2305          */
2306         if (view.type == I915_GGTT_VIEW_NORMAL) {
2307                 ret = i915_gem_object_get_fence(obj);
2308                 if (ret == -EDEADLK) {
2309                         /*
2310                          * -EDEADLK means there are no free fences
2311                          * no pending flips.
2312                          *
2313                          * This is propagated to atomic, but it uses
2314                          * -EDEADLK to force a locking recovery, so
2315                          * change the returned error to -EBUSY.
2316                          */
2317                         ret = -EBUSY;
2318                         goto err_unpin;
2319                 } else if (ret)
2320                         goto err_unpin;
2321
2322                 i915_gem_object_pin_fence(obj);
2323         }
2324
2325         intel_runtime_pm_put(dev_priv);
2326         return 0;
2327
2328 err_unpin:
2329         i915_gem_object_unpin_from_display_plane(obj, &view);
2330 err_pm:
2331         intel_runtime_pm_put(dev_priv);
2332         return ret;
2333 }
2334
2335 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2336 {
2337         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338         struct i915_ggtt_view view;
2339
2340         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2341
2342         intel_fill_fb_ggtt_view(&view, fb, rotation);
2343
2344         if (view.type == I915_GGTT_VIEW_NORMAL)
2345                 i915_gem_object_unpin_fence(obj);
2346
2347         i915_gem_object_unpin_from_display_plane(obj, &view);
2348 }
2349
2350 /*
2351  * Adjust the tile offset by moving the difference into
2352  * the x/y offsets.
2353  *
2354  * Input tile dimensions and pitch must already be
2355  * rotated to match x and y, and in pixel units.
2356  */
2357 static u32 intel_adjust_tile_offset(int *x, int *y,
2358                                     unsigned int tile_width,
2359                                     unsigned int tile_height,
2360                                     unsigned int tile_size,
2361                                     unsigned int pitch_tiles,
2362                                     u32 old_offset,
2363                                     u32 new_offset)
2364 {
2365         unsigned int tiles;
2366
2367         WARN_ON(old_offset & (tile_size - 1));
2368         WARN_ON(new_offset & (tile_size - 1));
2369         WARN_ON(new_offset > old_offset);
2370
2371         tiles = (old_offset - new_offset) / tile_size;
2372
2373         *y += tiles / pitch_tiles * tile_height;
2374         *x += tiles % pitch_tiles * tile_width;
2375
2376         return new_offset;
2377 }
2378
2379 /*
2380  * Computes the linear offset to the base tile and adjusts
2381  * x, y. bytes per pixel is assumed to be a power-of-two.
2382  *
2383  * In the 90/270 rotated case, x and y are assumed
2384  * to be already rotated to match the rotated GTT view, and
2385  * pitch is the tile_height aligned framebuffer height.
2386  */
2387 u32 intel_compute_tile_offset(int *x, int *y,
2388                               const struct drm_framebuffer *fb, int plane,
2389                               unsigned int pitch,
2390                               unsigned int rotation)
2391 {
2392         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2393         uint64_t fb_modifier = fb->modifier[plane];
2394         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2395         u32 offset, offset_aligned, alignment;
2396
2397         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2398         if (alignment)
2399                 alignment--;
2400
2401         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2402                 unsigned int tile_size, tile_width, tile_height;
2403                 unsigned int tile_rows, tiles, pitch_tiles;
2404
2405                 tile_size = intel_tile_size(dev_priv);
2406                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2407                                 fb_modifier, cpp);
2408
2409                 if (intel_rotation_90_or_270(rotation)) {
2410                         pitch_tiles = pitch / tile_height;
2411                         swap(tile_width, tile_height);
2412                 } else {
2413                         pitch_tiles = pitch / (tile_width * cpp);
2414                 }
2415
2416                 tile_rows = *y / tile_height;
2417                 *y %= tile_height;
2418
2419                 tiles = *x / tile_width;
2420                 *x %= tile_width;
2421
2422                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2423                 offset_aligned = offset & ~alignment;
2424
2425                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2426                                          tile_size, pitch_tiles,
2427                                          offset, offset_aligned);
2428         } else {
2429                 offset = *y * pitch + *x * cpp;
2430                 offset_aligned = offset & ~alignment;
2431
2432                 *y = (offset & alignment) / pitch;
2433                 *x = ((offset & alignment) - *y * pitch) / cpp;
2434         }
2435
2436         return offset_aligned;
2437 }
2438
2439 static int i9xx_format_to_fourcc(int format)
2440 {
2441         switch (format) {
2442         case DISPPLANE_8BPP:
2443                 return DRM_FORMAT_C8;
2444         case DISPPLANE_BGRX555:
2445                 return DRM_FORMAT_XRGB1555;
2446         case DISPPLANE_BGRX565:
2447                 return DRM_FORMAT_RGB565;
2448         default:
2449         case DISPPLANE_BGRX888:
2450                 return DRM_FORMAT_XRGB8888;
2451         case DISPPLANE_RGBX888:
2452                 return DRM_FORMAT_XBGR8888;
2453         case DISPPLANE_BGRX101010:
2454                 return DRM_FORMAT_XRGB2101010;
2455         case DISPPLANE_RGBX101010:
2456                 return DRM_FORMAT_XBGR2101010;
2457         }
2458 }
2459
2460 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2461 {
2462         switch (format) {
2463         case PLANE_CTL_FORMAT_RGB_565:
2464                 return DRM_FORMAT_RGB565;
2465         default:
2466         case PLANE_CTL_FORMAT_XRGB_8888:
2467                 if (rgb_order) {
2468                         if (alpha)
2469                                 return DRM_FORMAT_ABGR8888;
2470                         else
2471                                 return DRM_FORMAT_XBGR8888;
2472                 } else {
2473                         if (alpha)
2474                                 return DRM_FORMAT_ARGB8888;
2475                         else
2476                                 return DRM_FORMAT_XRGB8888;
2477                 }
2478         case PLANE_CTL_FORMAT_XRGB_2101010:
2479                 if (rgb_order)
2480                         return DRM_FORMAT_XBGR2101010;
2481                 else
2482                         return DRM_FORMAT_XRGB2101010;
2483         }
2484 }
2485
2486 static bool
2487 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2488                               struct intel_initial_plane_config *plane_config)
2489 {
2490         struct drm_device *dev = crtc->base.dev;
2491         struct drm_i915_private *dev_priv = to_i915(dev);
2492         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2493         struct drm_i915_gem_object *obj = NULL;
2494         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2495         struct drm_framebuffer *fb = &plane_config->fb->base;
2496         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2497         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2498                                     PAGE_SIZE);
2499
2500         size_aligned -= base_aligned;
2501
2502         if (plane_config->size == 0)
2503                 return false;
2504
2505         /* If the FB is too big, just don't use it since fbdev is not very
2506          * important and we should probably use that space with FBC or other
2507          * features. */
2508         if (size_aligned * 2 > ggtt->stolen_usable_size)
2509                 return false;
2510
2511         mutex_lock(&dev->struct_mutex);
2512
2513         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2514                                                              base_aligned,
2515                                                              base_aligned,
2516                                                              size_aligned);
2517         if (!obj) {
2518                 mutex_unlock(&dev->struct_mutex);
2519                 return false;
2520         }
2521
2522         obj->tiling_mode = plane_config->tiling;
2523         if (obj->tiling_mode == I915_TILING_X)
2524                 obj->stride = fb->pitches[0];
2525
2526         mode_cmd.pixel_format = fb->pixel_format;
2527         mode_cmd.width = fb->width;
2528         mode_cmd.height = fb->height;
2529         mode_cmd.pitches[0] = fb->pitches[0];
2530         mode_cmd.modifier[0] = fb->modifier[0];
2531         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2532
2533         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2534                                    &mode_cmd, obj)) {
2535                 DRM_DEBUG_KMS("intel fb init failed\n");
2536                 goto out_unref_obj;
2537         }
2538
2539         mutex_unlock(&dev->struct_mutex);
2540
2541         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2542         return true;
2543
2544 out_unref_obj:
2545         drm_gem_object_unreference(&obj->base);
2546         mutex_unlock(&dev->struct_mutex);
2547         return false;
2548 }
2549
2550 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2551 static void
2552 update_state_fb(struct drm_plane *plane)
2553 {
2554         if (plane->fb == plane->state->fb)
2555                 return;
2556
2557         if (plane->state->fb)
2558                 drm_framebuffer_unreference(plane->state->fb);
2559         plane->state->fb = plane->fb;
2560         if (plane->state->fb)
2561                 drm_framebuffer_reference(plane->state->fb);
2562 }
2563
2564 static void
2565 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2566                              struct intel_initial_plane_config *plane_config)
2567 {
2568         struct drm_device *dev = intel_crtc->base.dev;
2569         struct drm_i915_private *dev_priv = dev->dev_private;
2570         struct drm_crtc *c;
2571         struct intel_crtc *i;
2572         struct drm_i915_gem_object *obj;
2573         struct drm_plane *primary = intel_crtc->base.primary;
2574         struct drm_plane_state *plane_state = primary->state;
2575         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2576         struct intel_plane *intel_plane = to_intel_plane(primary);
2577         struct intel_plane_state *intel_state =
2578                 to_intel_plane_state(plane_state);
2579         struct drm_framebuffer *fb;
2580
2581         if (!plane_config->fb)
2582                 return;
2583
2584         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2585                 fb = &plane_config->fb->base;
2586                 goto valid_fb;
2587         }
2588
2589         kfree(plane_config->fb);
2590
2591         /*
2592          * Failed to alloc the obj, check to see if we should share
2593          * an fb with another CRTC instead
2594          */
2595         for_each_crtc(dev, c) {
2596                 i = to_intel_crtc(c);
2597
2598                 if (c == &intel_crtc->base)
2599                         continue;
2600
2601                 if (!i->active)
2602                         continue;
2603
2604                 fb = c->primary->fb;
2605                 if (!fb)
2606                         continue;
2607
2608                 obj = intel_fb_obj(fb);
2609                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2610                         drm_framebuffer_reference(fb);
2611                         goto valid_fb;
2612                 }
2613         }
2614
2615         /*
2616          * We've failed to reconstruct the BIOS FB.  Current display state
2617          * indicates that the primary plane is visible, but has a NULL FB,
2618          * which will lead to problems later if we don't fix it up.  The
2619          * simplest solution is to just disable the primary plane now and
2620          * pretend the BIOS never had it enabled.
2621          */
2622         to_intel_plane_state(plane_state)->visible = false;
2623         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2624         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2625         intel_plane->disable_plane(primary, &intel_crtc->base);
2626
2627         return;
2628
2629 valid_fb:
2630         plane_state->src_x = 0;
2631         plane_state->src_y = 0;
2632         plane_state->src_w = fb->width << 16;
2633         plane_state->src_h = fb->height << 16;
2634
2635         plane_state->crtc_x = 0;
2636         plane_state->crtc_y = 0;
2637         plane_state->crtc_w = fb->width;
2638         plane_state->crtc_h = fb->height;
2639
2640         intel_state->src.x1 = plane_state->src_x;
2641         intel_state->src.y1 = plane_state->src_y;
2642         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2643         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2644         intel_state->dst.x1 = plane_state->crtc_x;
2645         intel_state->dst.y1 = plane_state->crtc_y;
2646         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2647         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2648
2649         obj = intel_fb_obj(fb);
2650         if (obj->tiling_mode != I915_TILING_NONE)
2651                 dev_priv->preserve_bios_swizzle = true;
2652
2653         drm_framebuffer_reference(fb);
2654         primary->fb = primary->state->fb = fb;
2655         primary->crtc = primary->state->crtc = &intel_crtc->base;
2656         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 }
2659
2660 static void i9xx_update_primary_plane(struct drm_plane *primary,
2661                                       const struct intel_crtc_state *crtc_state,
2662                                       const struct intel_plane_state *plane_state)
2663 {
2664         struct drm_device *dev = primary->dev;
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2667         struct drm_framebuffer *fb = plane_state->base.fb;
2668         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2669         int plane = intel_crtc->plane;
2670         u32 linear_offset;
2671         u32 dspcntr;
2672         i915_reg_t reg = DSPCNTR(plane);
2673         unsigned int rotation = plane_state->base.rotation;
2674         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2675         int x = plane_state->src.x1 >> 16;
2676         int y = plane_state->src.y1 >> 16;
2677
2678         dspcntr = DISPPLANE_GAMMA_ENABLE;
2679
2680         dspcntr |= DISPLAY_PLANE_ENABLE;
2681
2682         if (INTEL_INFO(dev)->gen < 4) {
2683                 if (intel_crtc->pipe == PIPE_B)
2684                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2685
2686                 /* pipesrc and dspsize control the size that is scaled from,
2687                  * which should always be the user's requested size.
2688                  */
2689                 I915_WRITE(DSPSIZE(plane),
2690                            ((crtc_state->pipe_src_h - 1) << 16) |
2691                            (crtc_state->pipe_src_w - 1));
2692                 I915_WRITE(DSPPOS(plane), 0);
2693         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2694                 I915_WRITE(PRIMSIZE(plane),
2695                            ((crtc_state->pipe_src_h - 1) << 16) |
2696                            (crtc_state->pipe_src_w - 1));
2697                 I915_WRITE(PRIMPOS(plane), 0);
2698                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2699         }
2700
2701         switch (fb->pixel_format) {
2702         case DRM_FORMAT_C8:
2703                 dspcntr |= DISPPLANE_8BPP;
2704                 break;
2705         case DRM_FORMAT_XRGB1555:
2706                 dspcntr |= DISPPLANE_BGRX555;
2707                 break;
2708         case DRM_FORMAT_RGB565:
2709                 dspcntr |= DISPPLANE_BGRX565;
2710                 break;
2711         case DRM_FORMAT_XRGB8888:
2712                 dspcntr |= DISPPLANE_BGRX888;
2713                 break;
2714         case DRM_FORMAT_XBGR8888:
2715                 dspcntr |= DISPPLANE_RGBX888;
2716                 break;
2717         case DRM_FORMAT_XRGB2101010:
2718                 dspcntr |= DISPPLANE_BGRX101010;
2719                 break;
2720         case DRM_FORMAT_XBGR2101010:
2721                 dspcntr |= DISPPLANE_RGBX101010;
2722                 break;
2723         default:
2724                 BUG();
2725         }
2726
2727         if (INTEL_INFO(dev)->gen >= 4 &&
2728             obj->tiling_mode != I915_TILING_NONE)
2729                 dspcntr |= DISPPLANE_TILED;
2730
2731         if (IS_G4X(dev))
2732                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2733
2734         linear_offset = y * fb->pitches[0] + x * cpp;
2735
2736         if (INTEL_INFO(dev)->gen >= 4) {
2737                 intel_crtc->dspaddr_offset =
2738                         intel_compute_tile_offset(&x, &y, fb, 0,
2739                                                   fb->pitches[0], rotation);
2740                 linear_offset -= intel_crtc->dspaddr_offset;
2741         } else {
2742                 intel_crtc->dspaddr_offset = linear_offset;
2743         }
2744
2745         if (rotation == BIT(DRM_ROTATE_180)) {
2746                 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748                 x += (crtc_state->pipe_src_w - 1);
2749                 y += (crtc_state->pipe_src_h - 1);
2750
2751                 /* Finding the last pixel of the last line of the display
2752                 data and adding to linear_offset*/
2753                 linear_offset +=
2754                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2755                         (crtc_state->pipe_src_w - 1) * cpp;
2756         }
2757
2758         intel_crtc->adjusted_x = x;
2759         intel_crtc->adjusted_y = y;
2760
2761         I915_WRITE(reg, dspcntr);
2762
2763         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2764         if (INTEL_INFO(dev)->gen >= 4) {
2765                 I915_WRITE(DSPSURF(plane),
2766                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2768                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2769         } else
2770                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2771         POSTING_READ(reg);
2772 }
2773
2774 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2775                                        struct drm_crtc *crtc)
2776 {
2777         struct drm_device *dev = crtc->dev;
2778         struct drm_i915_private *dev_priv = dev->dev_private;
2779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780         int plane = intel_crtc->plane;
2781
2782         I915_WRITE(DSPCNTR(plane), 0);
2783         if (INTEL_INFO(dev_priv)->gen >= 4)
2784                 I915_WRITE(DSPSURF(plane), 0);
2785         else
2786                 I915_WRITE(DSPADDR(plane), 0);
2787         POSTING_READ(DSPCNTR(plane));
2788 }
2789
2790 static void ironlake_update_primary_plane(struct drm_plane *primary,
2791                                           const struct intel_crtc_state *crtc_state,
2792                                           const struct intel_plane_state *plane_state)
2793 {
2794         struct drm_device *dev = primary->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2797         struct drm_framebuffer *fb = plane_state->base.fb;
2798         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2799         int plane = intel_crtc->plane;
2800         u32 linear_offset;
2801         u32 dspcntr;
2802         i915_reg_t reg = DSPCNTR(plane);
2803         unsigned int rotation = plane_state->base.rotation;
2804         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2805         int x = plane_state->src.x1 >> 16;
2806         int y = plane_state->src.y1 >> 16;
2807
2808         dspcntr = DISPPLANE_GAMMA_ENABLE;
2809         dspcntr |= DISPLAY_PLANE_ENABLE;
2810
2811         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2812                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2813
2814         switch (fb->pixel_format) {
2815         case DRM_FORMAT_C8:
2816                 dspcntr |= DISPPLANE_8BPP;
2817                 break;
2818         case DRM_FORMAT_RGB565:
2819                 dspcntr |= DISPPLANE_BGRX565;
2820                 break;
2821         case DRM_FORMAT_XRGB8888:
2822                 dspcntr |= DISPPLANE_BGRX888;
2823                 break;
2824         case DRM_FORMAT_XBGR8888:
2825                 dspcntr |= DISPPLANE_RGBX888;
2826                 break;
2827         case DRM_FORMAT_XRGB2101010:
2828                 dspcntr |= DISPPLANE_BGRX101010;
2829                 break;
2830         case DRM_FORMAT_XBGR2101010:
2831                 dspcntr |= DISPPLANE_RGBX101010;
2832                 break;
2833         default:
2834                 BUG();
2835         }
2836
2837         if (obj->tiling_mode != I915_TILING_NONE)
2838                 dspcntr |= DISPPLANE_TILED;
2839
2840         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2841                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2842
2843         linear_offset = y * fb->pitches[0] + x * cpp;
2844         intel_crtc->dspaddr_offset =
2845                 intel_compute_tile_offset(&x, &y, fb, 0,
2846                                           fb->pitches[0], rotation);
2847         linear_offset -= intel_crtc->dspaddr_offset;
2848         if (rotation == BIT(DRM_ROTATE_180)) {
2849                 dspcntr |= DISPPLANE_ROTATE_180;
2850
2851                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2852                         x += (crtc_state->pipe_src_w - 1);
2853                         y += (crtc_state->pipe_src_h - 1);
2854
2855                         /* Finding the last pixel of the last line of the display
2856                         data and adding to linear_offset*/
2857                         linear_offset +=
2858                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2859                                 (crtc_state->pipe_src_w - 1) * cpp;
2860                 }
2861         }
2862
2863         intel_crtc->adjusted_x = x;
2864         intel_crtc->adjusted_y = y;
2865
2866         I915_WRITE(reg, dspcntr);
2867
2868         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869         I915_WRITE(DSPSURF(plane),
2870                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873         } else {
2874                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876         }
2877         POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2881                               uint64_t fb_modifier, uint32_t pixel_format)
2882 {
2883         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2884                 return 64;
2885         } else {
2886                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2887
2888                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2889         }
2890 }
2891
2892 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2893                            struct drm_i915_gem_object *obj,
2894                            unsigned int plane)
2895 {
2896         struct i915_ggtt_view view;
2897         struct i915_vma *vma;
2898         u64 offset;
2899
2900         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2901                                 intel_plane->base.state->rotation);
2902
2903         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2904         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2905                 view.type))
2906                 return -1;
2907
2908         offset = vma->node.start;
2909
2910         if (plane == 1) {
2911                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2912                           PAGE_SIZE;
2913         }
2914
2915         WARN_ON(upper_32_bits(offset));
2916
2917         return lower_32_bits(offset);
2918 }
2919
2920 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2921 {
2922         struct drm_device *dev = intel_crtc->base.dev;
2923         struct drm_i915_private *dev_priv = dev->dev_private;
2924
2925         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2926         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2927         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2928 }
2929
2930 /*
2931  * This function detaches (aka. unbinds) unused scalers in hardware
2932  */
2933 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2934 {
2935         struct intel_crtc_scaler_state *scaler_state;
2936         int i;
2937
2938         scaler_state = &intel_crtc->config->scaler_state;
2939
2940         /* loop through and disable scalers that aren't in use */
2941         for (i = 0; i < intel_crtc->num_scalers; i++) {
2942                 if (!scaler_state->scalers[i].in_use)
2943                         skl_detach_scaler(intel_crtc, i);
2944         }
2945 }
2946
2947 u32 skl_plane_ctl_format(uint32_t pixel_format)
2948 {
2949         switch (pixel_format) {
2950         case DRM_FORMAT_C8:
2951                 return PLANE_CTL_FORMAT_INDEXED;
2952         case DRM_FORMAT_RGB565:
2953                 return PLANE_CTL_FORMAT_RGB_565;
2954         case DRM_FORMAT_XBGR8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2956         case DRM_FORMAT_XRGB8888:
2957                 return PLANE_CTL_FORMAT_XRGB_8888;
2958         /*
2959          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2960          * to be already pre-multiplied. We need to add a knob (or a different
2961          * DRM_FORMAT) for user-space to configure that.
2962          */
2963         case DRM_FORMAT_ABGR8888:
2964                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2965                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966         case DRM_FORMAT_ARGB8888:
2967                 return PLANE_CTL_FORMAT_XRGB_8888 |
2968                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2969         case DRM_FORMAT_XRGB2101010:
2970                 return PLANE_CTL_FORMAT_XRGB_2101010;
2971         case DRM_FORMAT_XBGR2101010:
2972                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2973         case DRM_FORMAT_YUYV:
2974                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2975         case DRM_FORMAT_YVYU:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2977         case DRM_FORMAT_UYVY:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2979         case DRM_FORMAT_VYUY:
2980                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2981         default:
2982                 MISSING_CASE(pixel_format);
2983         }
2984
2985         return 0;
2986 }
2987
2988 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2989 {
2990         switch (fb_modifier) {
2991         case DRM_FORMAT_MOD_NONE:
2992                 break;
2993         case I915_FORMAT_MOD_X_TILED:
2994                 return PLANE_CTL_TILED_X;
2995         case I915_FORMAT_MOD_Y_TILED:
2996                 return PLANE_CTL_TILED_Y;
2997         case I915_FORMAT_MOD_Yf_TILED:
2998                 return PLANE_CTL_TILED_YF;
2999         default:
3000                 MISSING_CASE(fb_modifier);
3001         }
3002
3003         return 0;
3004 }
3005
3006 u32 skl_plane_ctl_rotation(unsigned int rotation)
3007 {
3008         switch (rotation) {
3009         case BIT(DRM_ROTATE_0):
3010                 break;
3011         /*
3012          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3013          * while i915 HW rotation is clockwise, thats why this swapping.
3014          */
3015         case BIT(DRM_ROTATE_90):
3016                 return PLANE_CTL_ROTATE_270;
3017         case BIT(DRM_ROTATE_180):
3018                 return PLANE_CTL_ROTATE_180;
3019         case BIT(DRM_ROTATE_270):
3020                 return PLANE_CTL_ROTATE_90;
3021         default:
3022                 MISSING_CASE(rotation);
3023         }
3024
3025         return 0;
3026 }
3027
3028 static void skylake_update_primary_plane(struct drm_plane *plane,
3029                                          const struct intel_crtc_state *crtc_state,
3030                                          const struct intel_plane_state *plane_state)
3031 {
3032         struct drm_device *dev = plane->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3035         struct drm_framebuffer *fb = plane_state->base.fb;
3036         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3037         int pipe = intel_crtc->pipe;
3038         u32 plane_ctl, stride_div, stride;
3039         u32 tile_height, plane_offset, plane_size;
3040         unsigned int rotation = plane_state->base.rotation;
3041         int x_offset, y_offset;
3042         u32 surf_addr;
3043         int scaler_id = plane_state->scaler_id;
3044         int src_x = plane_state->src.x1 >> 16;
3045         int src_y = plane_state->src.y1 >> 16;
3046         int src_w = drm_rect_width(&plane_state->src) >> 16;
3047         int src_h = drm_rect_height(&plane_state->src) >> 16;
3048         int dst_x = plane_state->dst.x1;
3049         int dst_y = plane_state->dst.y1;
3050         int dst_w = drm_rect_width(&plane_state->dst);
3051         int dst_h = drm_rect_height(&plane_state->dst);
3052
3053         plane_ctl = PLANE_CTL_ENABLE |
3054                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3055                     PLANE_CTL_PIPE_CSC_ENABLE;
3056
3057         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3058         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3059         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3060         plane_ctl |= skl_plane_ctl_rotation(rotation);
3061
3062         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3063                                                fb->pixel_format);
3064         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3065
3066         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3067
3068         if (intel_rotation_90_or_270(rotation)) {
3069                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3070
3071                 /* stride = Surface height in tiles */
3072                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3073                 stride = DIV_ROUND_UP(fb->height, tile_height);
3074                 x_offset = stride * tile_height - src_y - src_h;
3075                 y_offset = src_x;
3076                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3077         } else {
3078                 stride = fb->pitches[0] / stride_div;
3079                 x_offset = src_x;
3080                 y_offset = src_y;
3081                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3082         }
3083         plane_offset = y_offset << 16 | x_offset;
3084
3085         intel_crtc->adjusted_x = x_offset;
3086         intel_crtc->adjusted_y = y_offset;
3087
3088         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3089         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3090         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3091         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3092
3093         if (scaler_id >= 0) {
3094                 uint32_t ps_ctrl = 0;
3095
3096                 WARN_ON(!dst_w || !dst_h);
3097                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3098                         crtc_state->scaler_state.scalers[scaler_id].mode;
3099                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3100                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3101                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3102                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3103                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3104         } else {
3105                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3106         }
3107
3108         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3109
3110         POSTING_READ(PLANE_SURF(pipe, 0));
3111 }
3112
3113 static void skylake_disable_primary_plane(struct drm_plane *primary,
3114                                           struct drm_crtc *crtc)
3115 {
3116         struct drm_device *dev = crtc->dev;
3117         struct drm_i915_private *dev_priv = dev->dev_private;
3118         int pipe = to_intel_crtc(crtc)->pipe;
3119
3120         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3121         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3122         POSTING_READ(PLANE_SURF(pipe, 0));
3123 }
3124
3125 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3126 static int
3127 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3128                            int x, int y, enum mode_set_atomic state)
3129 {
3130         /* Support for kgdboc is disabled, this needs a major rework. */
3131         DRM_ERROR("legacy panic handler not supported any more.\n");
3132
3133         return -ENODEV;
3134 }
3135
3136 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3137 {
3138         struct intel_crtc *crtc;
3139
3140         for_each_intel_crtc(dev_priv->dev, crtc)
3141                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3142 }
3143
3144 static void intel_update_primary_planes(struct drm_device *dev)
3145 {
3146         struct drm_crtc *crtc;
3147
3148         for_each_crtc(dev, crtc) {
3149                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3150                 struct intel_plane_state *plane_state;
3151
3152                 drm_modeset_lock_crtc(crtc, &plane->base);
3153                 plane_state = to_intel_plane_state(plane->base.state);
3154
3155                 if (plane_state->visible)
3156                         plane->update_plane(&plane->base,
3157                                             to_intel_crtc_state(crtc->state),
3158                                             plane_state);
3159
3160                 drm_modeset_unlock_crtc(crtc);
3161         }
3162 }
3163
3164 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3165 {
3166         /* no reset support for gen2 */
3167         if (IS_GEN2(dev_priv))
3168                 return;
3169
3170         /* reset doesn't touch the display */
3171         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3172                 return;
3173
3174         drm_modeset_lock_all(dev_priv->dev);
3175         /*
3176          * Disabling the crtcs gracefully seems nicer. Also the
3177          * g33 docs say we should at least disable all the planes.
3178          */
3179         intel_display_suspend(dev_priv->dev);
3180 }
3181
3182 void intel_finish_reset(struct drm_i915_private *dev_priv)
3183 {
3184         /*
3185          * Flips in the rings will be nuked by the reset,
3186          * so complete all pending flips so that user space
3187          * will get its events and not get stuck.
3188          */
3189         intel_complete_page_flips(dev_priv);
3190
3191         /* no reset support for gen2 */
3192         if (IS_GEN2(dev_priv))
3193                 return;
3194
3195         /* reset doesn't touch the display */
3196         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3197                 /*
3198                  * Flips in the rings have been nuked by the reset,
3199                  * so update the base address of all primary
3200                  * planes to the the last fb to make sure we're
3201                  * showing the correct fb after a reset.
3202                  *
3203                  * FIXME: Atomic will make this obsolete since we won't schedule
3204                  * CS-based flips (which might get lost in gpu resets) any more.
3205                  */
3206                 intel_update_primary_planes(dev_priv->dev);
3207                 return;
3208         }
3209
3210         /*
3211          * The display has been reset as well,
3212          * so need a full re-initialization.
3213          */
3214         intel_runtime_pm_disable_interrupts(dev_priv);
3215         intel_runtime_pm_enable_interrupts(dev_priv);
3216
3217         intel_modeset_init_hw(dev_priv->dev);
3218
3219         spin_lock_irq(&dev_priv->irq_lock);
3220         if (dev_priv->display.hpd_irq_setup)
3221                 dev_priv->display.hpd_irq_setup(dev_priv);
3222         spin_unlock_irq(&dev_priv->irq_lock);
3223
3224         intel_display_resume(dev_priv->dev);
3225
3226         intel_hpd_init(dev_priv);
3227
3228         drm_modeset_unlock_all(dev_priv->dev);
3229 }
3230
3231 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3232 {
3233         struct drm_device *dev = crtc->dev;
3234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3235         unsigned reset_counter;
3236         bool pending;
3237
3238         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3239         if (intel_crtc->reset_counter != reset_counter)
3240                 return false;
3241
3242         spin_lock_irq(&dev->event_lock);
3243         pending = to_intel_crtc(crtc)->flip_work != NULL;
3244         spin_unlock_irq(&dev->event_lock);
3245
3246         return pending;
3247 }
3248
3249 static void intel_update_pipe_config(struct intel_crtc *crtc,
3250                                      struct intel_crtc_state *old_crtc_state)
3251 {
3252         struct drm_device *dev = crtc->base.dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         struct intel_crtc_state *pipe_config =
3255                 to_intel_crtc_state(crtc->base.state);
3256
3257         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3258         crtc->base.mode = crtc->base.state->mode;
3259
3260         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3261                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3262                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3263
3264         /*
3265          * Update pipe size and adjust fitter if needed: the reason for this is
3266          * that in compute_mode_changes we check the native mode (not the pfit
3267          * mode) to see if we can flip rather than do a full mode set. In the
3268          * fastboot case, we'll flip, but if we don't update the pipesrc and
3269          * pfit state, we'll end up with a big fb scanned out into the wrong
3270          * sized surface.
3271          */
3272
3273         I915_WRITE(PIPESRC(crtc->pipe),
3274                    ((pipe_config->pipe_src_w - 1) << 16) |
3275                    (pipe_config->pipe_src_h - 1));
3276
3277         /* on skylake this is done by detaching scalers */
3278         if (INTEL_INFO(dev)->gen >= 9) {
3279                 skl_detach_scalers(crtc);
3280
3281                 if (pipe_config->pch_pfit.enabled)
3282                         skylake_pfit_enable(crtc);
3283         } else if (HAS_PCH_SPLIT(dev)) {
3284                 if (pipe_config->pch_pfit.enabled)
3285                         ironlake_pfit_enable(crtc);
3286                 else if (old_crtc_state->pch_pfit.enabled)
3287                         ironlake_pfit_disable(crtc, true);
3288         }
3289 }
3290
3291 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3292 {
3293         struct drm_device *dev = crtc->dev;
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296         int pipe = intel_crtc->pipe;
3297         i915_reg_t reg;
3298         u32 temp;
3299
3300         /* enable normal train */
3301         reg = FDI_TX_CTL(pipe);
3302         temp = I915_READ(reg);
3303         if (IS_IVYBRIDGE(dev)) {
3304                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3305                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3306         } else {
3307                 temp &= ~FDI_LINK_TRAIN_NONE;
3308                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3309         }
3310         I915_WRITE(reg, temp);
3311
3312         reg = FDI_RX_CTL(pipe);
3313         temp = I915_READ(reg);
3314         if (HAS_PCH_CPT(dev)) {
3315                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3316                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3317         } else {
3318                 temp &= ~FDI_LINK_TRAIN_NONE;
3319                 temp |= FDI_LINK_TRAIN_NONE;
3320         }
3321         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3322
3323         /* wait one idle pattern time */
3324         POSTING_READ(reg);
3325         udelay(1000);
3326
3327         /* IVB wants error correction enabled */
3328         if (IS_IVYBRIDGE(dev))
3329                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3330                            FDI_FE_ERRC_ENABLE);
3331 }
3332
3333 /* The FDI link training functions for ILK/Ibexpeak. */
3334 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3335 {
3336         struct drm_device *dev = crtc->dev;
3337         struct drm_i915_private *dev_priv = dev->dev_private;
3338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3339         int pipe = intel_crtc->pipe;
3340         i915_reg_t reg;
3341         u32 temp, tries;
3342
3343         /* FDI needs bits from pipe first */
3344         assert_pipe_enabled(dev_priv, pipe);
3345
3346         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3347            for train result */
3348         reg = FDI_RX_IMR(pipe);
3349         temp = I915_READ(reg);
3350         temp &= ~FDI_RX_SYMBOL_LOCK;
3351         temp &= ~FDI_RX_BIT_LOCK;
3352         I915_WRITE(reg, temp);
3353         I915_READ(reg);
3354         udelay(150);
3355
3356         /* enable CPU FDI TX and PCH FDI RX */
3357         reg = FDI_TX_CTL(pipe);
3358         temp = I915_READ(reg);
3359         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3360         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3361         temp &= ~FDI_LINK_TRAIN_NONE;
3362         temp |= FDI_LINK_TRAIN_PATTERN_1;
3363         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3364
3365         reg = FDI_RX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         temp &= ~FDI_LINK_TRAIN_NONE;
3368         temp |= FDI_LINK_TRAIN_PATTERN_1;
3369         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3370
3371         POSTING_READ(reg);
3372         udelay(150);
3373
3374         /* Ironlake workaround, enable clock pointer after FDI enable*/
3375         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3376         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3377                    FDI_RX_PHASE_SYNC_POINTER_EN);
3378
3379         reg = FDI_RX_IIR(pipe);
3380         for (tries = 0; tries < 5; tries++) {
3381                 temp = I915_READ(reg);
3382                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3383
3384                 if ((temp & FDI_RX_BIT_LOCK)) {
3385                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3386                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3387                         break;
3388                 }
3389         }
3390         if (tries == 5)
3391                 DRM_ERROR("FDI train 1 fail!\n");
3392
3393         /* Train 2 */
3394         reg = FDI_TX_CTL(pipe);
3395         temp = I915_READ(reg);
3396         temp &= ~FDI_LINK_TRAIN_NONE;
3397         temp |= FDI_LINK_TRAIN_PATTERN_2;
3398         I915_WRITE(reg, temp);
3399
3400         reg = FDI_RX_CTL(pipe);
3401         temp = I915_READ(reg);
3402         temp &= ~FDI_LINK_TRAIN_NONE;
3403         temp |= FDI_LINK_TRAIN_PATTERN_2;
3404         I915_WRITE(reg, temp);
3405
3406         POSTING_READ(reg);
3407         udelay(150);
3408
3409         reg = FDI_RX_IIR(pipe);
3410         for (tries = 0; tries < 5; tries++) {
3411                 temp = I915_READ(reg);
3412                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413
3414                 if (temp & FDI_RX_SYMBOL_LOCK) {
3415                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3416                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3417                         break;
3418                 }
3419         }
3420         if (tries == 5)
3421                 DRM_ERROR("FDI train 2 fail!\n");
3422
3423         DRM_DEBUG_KMS("FDI train done\n");
3424
3425 }
3426
3427 static const int snb_b_fdi_train_param[] = {
3428         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3429         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3430         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3431         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3432 };
3433
3434 /* The FDI link training functions for SNB/Cougarpoint. */
3435 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         struct drm_i915_private *dev_priv = dev->dev_private;
3439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3440         int pipe = intel_crtc->pipe;
3441         i915_reg_t reg;
3442         u32 temp, i, retry;
3443
3444         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3445            for train result */
3446         reg = FDI_RX_IMR(pipe);
3447         temp = I915_READ(reg);
3448         temp &= ~FDI_RX_SYMBOL_LOCK;
3449         temp &= ~FDI_RX_BIT_LOCK;
3450         I915_WRITE(reg, temp);
3451
3452         POSTING_READ(reg);
3453         udelay(150);
3454
3455         /* enable CPU FDI TX and PCH FDI RX */
3456         reg = FDI_TX_CTL(pipe);
3457         temp = I915_READ(reg);
3458         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3459         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3460         temp &= ~FDI_LINK_TRAIN_NONE;
3461         temp |= FDI_LINK_TRAIN_PATTERN_1;
3462         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3463         /* SNB-B */
3464         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3465         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3466
3467         I915_WRITE(FDI_RX_MISC(pipe),
3468                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3469
3470         reg = FDI_RX_CTL(pipe);
3471         temp = I915_READ(reg);
3472         if (HAS_PCH_CPT(dev)) {
3473                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3474                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3475         } else {
3476                 temp &= ~FDI_LINK_TRAIN_NONE;
3477                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3478         }
3479         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3480
3481         POSTING_READ(reg);
3482         udelay(150);
3483
3484         for (i = 0; i < 4; i++) {
3485                 reg = FDI_TX_CTL(pipe);
3486                 temp = I915_READ(reg);
3487                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3488                 temp |= snb_b_fdi_train_param[i];
3489                 I915_WRITE(reg, temp);
3490
3491                 POSTING_READ(reg);
3492                 udelay(500);
3493
3494                 for (retry = 0; retry < 5; retry++) {
3495                         reg = FDI_RX_IIR(pipe);
3496                         temp = I915_READ(reg);
3497                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3498                         if (temp & FDI_RX_BIT_LOCK) {
3499                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3500                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3501                                 break;
3502                         }
3503                         udelay(50);
3504                 }
3505                 if (retry < 5)
3506                         break;
3507         }
3508         if (i == 4)
3509                 DRM_ERROR("FDI train 1 fail!\n");
3510
3511         /* Train 2 */
3512         reg = FDI_TX_CTL(pipe);
3513         temp = I915_READ(reg);
3514         temp &= ~FDI_LINK_TRAIN_NONE;
3515         temp |= FDI_LINK_TRAIN_PATTERN_2;
3516         if (IS_GEN6(dev)) {
3517                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518                 /* SNB-B */
3519                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3520         }
3521         I915_WRITE(reg, temp);
3522
3523         reg = FDI_RX_CTL(pipe);
3524         temp = I915_READ(reg);
3525         if (HAS_PCH_CPT(dev)) {
3526                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3527                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3528         } else {
3529                 temp &= ~FDI_LINK_TRAIN_NONE;
3530                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3531         }
3532         I915_WRITE(reg, temp);
3533
3534         POSTING_READ(reg);
3535         udelay(150);
3536
3537         for (i = 0; i < 4; i++) {
3538                 reg = FDI_TX_CTL(pipe);
3539                 temp = I915_READ(reg);
3540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3541                 temp |= snb_b_fdi_train_param[i];
3542                 I915_WRITE(reg, temp);
3543
3544                 POSTING_READ(reg);
3545                 udelay(500);
3546
3547                 for (retry = 0; retry < 5; retry++) {
3548                         reg = FDI_RX_IIR(pipe);
3549                         temp = I915_READ(reg);
3550                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3551                         if (temp & FDI_RX_SYMBOL_LOCK) {
3552                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3553                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3554                                 break;
3555                         }
3556                         udelay(50);
3557                 }
3558                 if (retry < 5)
3559                         break;
3560         }
3561         if (i == 4)
3562                 DRM_ERROR("FDI train 2 fail!\n");
3563
3564         DRM_DEBUG_KMS("FDI train done.\n");
3565 }
3566
3567 /* Manual link training for Ivy Bridge A0 parts */
3568 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3569 {
3570         struct drm_device *dev = crtc->dev;
3571         struct drm_i915_private *dev_priv = dev->dev_private;
3572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3573         int pipe = intel_crtc->pipe;
3574         i915_reg_t reg;
3575         u32 temp, i, j;
3576
3577         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3578            for train result */
3579         reg = FDI_RX_IMR(pipe);
3580         temp = I915_READ(reg);
3581         temp &= ~FDI_RX_SYMBOL_LOCK;
3582         temp &= ~FDI_RX_BIT_LOCK;
3583         I915_WRITE(reg, temp);
3584
3585         POSTING_READ(reg);
3586         udelay(150);
3587
3588         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3589                       I915_READ(FDI_RX_IIR(pipe)));
3590
3591         /* Try each vswing and preemphasis setting twice before moving on */
3592         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3593                 /* disable first in case we need to retry */
3594                 reg = FDI_TX_CTL(pipe);
3595                 temp = I915_READ(reg);
3596                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3597                 temp &= ~FDI_TX_ENABLE;
3598                 I915_WRITE(reg, temp);
3599
3600                 reg = FDI_RX_CTL(pipe);
3601                 temp = I915_READ(reg);
3602                 temp &= ~FDI_LINK_TRAIN_AUTO;
3603                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3604                 temp &= ~FDI_RX_ENABLE;
3605                 I915_WRITE(reg, temp);
3606
3607                 /* enable CPU FDI TX and PCH FDI RX */
3608                 reg = FDI_TX_CTL(pipe);
3609                 temp = I915_READ(reg);
3610                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3611                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3612                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3613                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3614                 temp |= snb_b_fdi_train_param[j/2];
3615                 temp |= FDI_COMPOSITE_SYNC;
3616                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3617
3618                 I915_WRITE(FDI_RX_MISC(pipe),
3619                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3620
3621                 reg = FDI_RX_CTL(pipe);
3622                 temp = I915_READ(reg);
3623                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3624                 temp |= FDI_COMPOSITE_SYNC;
3625                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3626
3627                 POSTING_READ(reg);
3628                 udelay(1); /* should be 0.5us */
3629
3630                 for (i = 0; i < 4; i++) {
3631                         reg = FDI_RX_IIR(pipe);
3632                         temp = I915_READ(reg);
3633                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3634
3635                         if (temp & FDI_RX_BIT_LOCK ||
3636                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3637                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3638                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3639                                               i);
3640                                 break;
3641                         }
3642                         udelay(1); /* should be 0.5us */
3643                 }
3644                 if (i == 4) {
3645                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3646                         continue;
3647                 }
3648
3649                 /* Train 2 */
3650                 reg = FDI_TX_CTL(pipe);
3651                 temp = I915_READ(reg);
3652                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3653                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3654                 I915_WRITE(reg, temp);
3655
3656                 reg = FDI_RX_CTL(pipe);
3657                 temp = I915_READ(reg);
3658                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3660                 I915_WRITE(reg, temp);
3661
3662                 POSTING_READ(reg);
3663                 udelay(2); /* should be 1.5us */
3664
3665                 for (i = 0; i < 4; i++) {
3666                         reg = FDI_RX_IIR(pipe);
3667                         temp = I915_READ(reg);
3668                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3669
3670                         if (temp & FDI_RX_SYMBOL_LOCK ||
3671                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3672                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3673                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3674                                               i);
3675                                 goto train_done;
3676                         }
3677                         udelay(2); /* should be 1.5us */
3678                 }
3679                 if (i == 4)
3680                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3681         }
3682
3683 train_done:
3684         DRM_DEBUG_KMS("FDI train done.\n");
3685 }
3686
3687 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3688 {
3689         struct drm_device *dev = intel_crtc->base.dev;
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         int pipe = intel_crtc->pipe;
3692         i915_reg_t reg;
3693         u32 temp;
3694
3695         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3696         reg = FDI_RX_CTL(pipe);
3697         temp = I915_READ(reg);
3698         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3699         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3700         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3701         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3702
3703         POSTING_READ(reg);
3704         udelay(200);
3705
3706         /* Switch from Rawclk to PCDclk */
3707         temp = I915_READ(reg);
3708         I915_WRITE(reg, temp | FDI_PCDCLK);
3709
3710         POSTING_READ(reg);
3711         udelay(200);
3712
3713         /* Enable CPU FDI TX PLL, always on for Ironlake */
3714         reg = FDI_TX_CTL(pipe);
3715         temp = I915_READ(reg);
3716         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3717                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3718
3719                 POSTING_READ(reg);
3720                 udelay(100);
3721         }
3722 }
3723
3724 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3725 {
3726         struct drm_device *dev = intel_crtc->base.dev;
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728         int pipe = intel_crtc->pipe;
3729         i915_reg_t reg;
3730         u32 temp;
3731
3732         /* Switch from PCDclk to Rawclk */
3733         reg = FDI_RX_CTL(pipe);
3734         temp = I915_READ(reg);
3735         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3736
3737         /* Disable CPU FDI TX PLL */
3738         reg = FDI_TX_CTL(pipe);
3739         temp = I915_READ(reg);
3740         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3741
3742         POSTING_READ(reg);
3743         udelay(100);
3744
3745         reg = FDI_RX_CTL(pipe);
3746         temp = I915_READ(reg);
3747         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3748
3749         /* Wait for the clocks to turn off. */
3750         POSTING_READ(reg);
3751         udelay(100);
3752 }
3753
3754 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3755 {
3756         struct drm_device *dev = crtc->dev;
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759         int pipe = intel_crtc->pipe;
3760         i915_reg_t reg;
3761         u32 temp;
3762
3763         /* disable CPU FDI tx and PCH FDI rx */
3764         reg = FDI_TX_CTL(pipe);
3765         temp = I915_READ(reg);
3766         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3767         POSTING_READ(reg);
3768
3769         reg = FDI_RX_CTL(pipe);
3770         temp = I915_READ(reg);
3771         temp &= ~(0x7 << 16);
3772         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3773         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3774
3775         POSTING_READ(reg);
3776         udelay(100);
3777
3778         /* Ironlake workaround, disable clock pointer after downing FDI */
3779         if (HAS_PCH_IBX(dev))
3780                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3781
3782         /* still set train pattern 1 */
3783         reg = FDI_TX_CTL(pipe);
3784         temp = I915_READ(reg);
3785         temp &= ~FDI_LINK_TRAIN_NONE;
3786         temp |= FDI_LINK_TRAIN_PATTERN_1;
3787         I915_WRITE(reg, temp);
3788
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         if (HAS_PCH_CPT(dev)) {
3792                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3793                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3794         } else {
3795                 temp &= ~FDI_LINK_TRAIN_NONE;
3796                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3797         }
3798         /* BPC in FDI rx is consistent with that in PIPECONF */
3799         temp &= ~(0x07 << 16);
3800         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3801         I915_WRITE(reg, temp);
3802
3803         POSTING_READ(reg);
3804         udelay(100);
3805 }
3806
3807 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3808 {
3809         struct intel_crtc *crtc;
3810
3811         /* Note that we don't need to be called with mode_config.lock here
3812          * as our list of CRTC objects is static for the lifetime of the
3813          * device and so cannot disappear as we iterate. Similarly, we can
3814          * happily treat the predicates as racy, atomic checks as userspace
3815          * cannot claim and pin a new fb without at least acquring the
3816          * struct_mutex and so serialising with us.
3817          */
3818         for_each_intel_crtc(dev, crtc) {
3819                 if (atomic_read(&crtc->unpin_work_count) == 0)
3820                         continue;
3821
3822                 if (crtc->flip_work)
3823                         intel_wait_for_vblank(dev, crtc->pipe);
3824
3825                 return true;
3826         }
3827
3828         return false;
3829 }
3830
3831 static void page_flip_completed(struct intel_crtc *intel_crtc)
3832 {
3833         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3834         struct intel_flip_work *work = intel_crtc->flip_work;
3835
3836         intel_crtc->flip_work = NULL;
3837
3838         if (work->event)
3839                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3840
3841         drm_crtc_vblank_put(&intel_crtc->base);
3842
3843         wake_up_all(&dev_priv->pending_flip_queue);
3844         queue_work(dev_priv->wq, &work->unpin_work);
3845
3846         trace_i915_flip_complete(intel_crtc->plane,
3847                                  work->pending_flip_obj);
3848 }
3849
3850 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3851 {
3852         struct drm_device *dev = crtc->dev;
3853         struct drm_i915_private *dev_priv = dev->dev_private;
3854         long ret;
3855
3856         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3857
3858         ret = wait_event_interruptible_timeout(
3859                                         dev_priv->pending_flip_queue,
3860                                         !intel_crtc_has_pending_flip(crtc),
3861                                         60*HZ);
3862
3863         if (ret < 0)
3864                 return ret;
3865
3866         if (ret == 0) {
3867                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3868                 struct intel_flip_work *work;
3869
3870                 spin_lock_irq(&dev->event_lock);
3871                 work = intel_crtc->flip_work;
3872                 if (work && !is_mmio_work(work)) {
3873                         WARN_ONCE(1, "Removing stuck page flip\n");
3874                         page_flip_completed(intel_crtc);
3875                 }
3876                 spin_unlock_irq(&dev->event_lock);
3877         }
3878
3879         return 0;
3880 }
3881
3882 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3883 {
3884         u32 temp;
3885
3886         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3887
3888         mutex_lock(&dev_priv->sb_lock);
3889
3890         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3891         temp |= SBI_SSCCTL_DISABLE;
3892         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3893
3894         mutex_unlock(&dev_priv->sb_lock);
3895 }
3896
3897 /* Program iCLKIP clock to the desired frequency */
3898 static void lpt_program_iclkip(struct drm_crtc *crtc)
3899 {
3900         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3901         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3902         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3903         u32 temp;
3904
3905         lpt_disable_iclkip(dev_priv);
3906
3907         /* The iCLK virtual clock root frequency is in MHz,
3908          * but the adjusted_mode->crtc_clock in in KHz. To get the
3909          * divisors, it is necessary to divide one by another, so we
3910          * convert the virtual clock precision to KHz here for higher
3911          * precision.
3912          */
3913         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3914                 u32 iclk_virtual_root_freq = 172800 * 1000;
3915                 u32 iclk_pi_range = 64;
3916                 u32 desired_divisor;
3917
3918                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3919                                                     clock << auxdiv);
3920                 divsel = (desired_divisor / iclk_pi_range) - 2;
3921                 phaseinc = desired_divisor % iclk_pi_range;
3922
3923                 /*
3924                  * Near 20MHz is a corner case which is
3925                  * out of range for the 7-bit divisor
3926                  */
3927                 if (divsel <= 0x7f)
3928                         break;
3929         }
3930
3931         /* This should not happen with any sane values */
3932         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3933                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3934         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3935                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3936
3937         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3938                         clock,
3939                         auxdiv,
3940                         divsel,
3941                         phasedir,
3942                         phaseinc);
3943
3944         mutex_lock(&dev_priv->sb_lock);
3945
3946         /* Program SSCDIVINTPHASE6 */
3947         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3948         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3949         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3950         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3951         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3952         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3953         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3954         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3955
3956         /* Program SSCAUXDIV */
3957         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3958         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3959         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3960         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3961
3962         /* Enable modulator and associated divider */
3963         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3964         temp &= ~SBI_SSCCTL_DISABLE;
3965         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3966
3967         mutex_unlock(&dev_priv->sb_lock);
3968
3969         /* Wait for initialization time */
3970         udelay(24);
3971
3972         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3973 }
3974
3975 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3976 {
3977         u32 divsel, phaseinc, auxdiv;
3978         u32 iclk_virtual_root_freq = 172800 * 1000;
3979         u32 iclk_pi_range = 64;
3980         u32 desired_divisor;
3981         u32 temp;
3982
3983         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3984                 return 0;
3985
3986         mutex_lock(&dev_priv->sb_lock);
3987
3988         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3989         if (temp & SBI_SSCCTL_DISABLE) {
3990                 mutex_unlock(&dev_priv->sb_lock);
3991                 return 0;
3992         }
3993
3994         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3995         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3996                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3997         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3998                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3999
4000         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4001         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4002                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4003
4004         mutex_unlock(&dev_priv->sb_lock);
4005
4006         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4007
4008         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4009                                  desired_divisor << auxdiv);
4010 }
4011
4012 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4013                                                 enum pipe pch_transcoder)
4014 {
4015         struct drm_device *dev = crtc->base.dev;
4016         struct drm_i915_private *dev_priv = dev->dev_private;
4017         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4018
4019         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4020                    I915_READ(HTOTAL(cpu_transcoder)));
4021         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4022                    I915_READ(HBLANK(cpu_transcoder)));
4023         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4024                    I915_READ(HSYNC(cpu_transcoder)));
4025
4026         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4027                    I915_READ(VTOTAL(cpu_transcoder)));
4028         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4029                    I915_READ(VBLANK(cpu_transcoder)));
4030         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4031                    I915_READ(VSYNC(cpu_transcoder)));
4032         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4033                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4034 }
4035
4036 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4037 {
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039         uint32_t temp;
4040
4041         temp = I915_READ(SOUTH_CHICKEN1);
4042         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4043                 return;
4044
4045         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4046         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4047
4048         temp &= ~FDI_BC_BIFURCATION_SELECT;
4049         if (enable)
4050                 temp |= FDI_BC_BIFURCATION_SELECT;
4051
4052         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4053         I915_WRITE(SOUTH_CHICKEN1, temp);
4054         POSTING_READ(SOUTH_CHICKEN1);
4055 }
4056
4057 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4058 {
4059         struct drm_device *dev = intel_crtc->base.dev;
4060
4061         switch (intel_crtc->pipe) {
4062         case PIPE_A:
4063                 break;
4064         case PIPE_B:
4065                 if (intel_crtc->config->fdi_lanes > 2)
4066                         cpt_set_fdi_bc_bifurcation(dev, false);
4067                 else
4068                         cpt_set_fdi_bc_bifurcation(dev, true);
4069
4070                 break;
4071         case PIPE_C:
4072                 cpt_set_fdi_bc_bifurcation(dev, true);
4073
4074                 break;
4075         default:
4076                 BUG();
4077         }
4078 }
4079
4080 /* Return which DP Port should be selected for Transcoder DP control */
4081 static enum port
4082 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4083 {
4084         struct drm_device *dev = crtc->dev;
4085         struct intel_encoder *encoder;
4086
4087         for_each_encoder_on_crtc(dev, crtc, encoder) {
4088                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4089                     encoder->type == INTEL_OUTPUT_EDP)
4090                         return enc_to_dig_port(&encoder->base)->port;
4091         }
4092
4093         return -1;
4094 }
4095
4096 /*
4097  * Enable PCH resources required for PCH ports:
4098  *   - PCH PLLs
4099  *   - FDI training & RX/TX
4100  *   - update transcoder timings
4101  *   - DP transcoding bits
4102  *   - transcoder
4103  */
4104 static void ironlake_pch_enable(struct drm_crtc *crtc)
4105 {
4106         struct drm_device *dev = crtc->dev;
4107         struct drm_i915_private *dev_priv = dev->dev_private;
4108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109         int pipe = intel_crtc->pipe;
4110         u32 temp;
4111
4112         assert_pch_transcoder_disabled(dev_priv, pipe);
4113
4114         if (IS_IVYBRIDGE(dev))
4115                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4116
4117         /* Write the TU size bits before fdi link training, so that error
4118          * detection works. */
4119         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4120                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4121
4122         /* For PCH output, training FDI link */
4123         dev_priv->display.fdi_link_train(crtc);
4124
4125         /* We need to program the right clock selection before writing the pixel
4126          * mutliplier into the DPLL. */
4127         if (HAS_PCH_CPT(dev)) {
4128                 u32 sel;
4129
4130                 temp = I915_READ(PCH_DPLL_SEL);
4131                 temp |= TRANS_DPLL_ENABLE(pipe);
4132                 sel = TRANS_DPLLB_SEL(pipe);
4133                 if (intel_crtc->config->shared_dpll ==
4134                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4135                         temp |= sel;
4136                 else
4137                         temp &= ~sel;
4138                 I915_WRITE(PCH_DPLL_SEL, temp);
4139         }
4140
4141         /* XXX: pch pll's can be enabled any time before we enable the PCH
4142          * transcoder, and we actually should do this to not upset any PCH
4143          * transcoder that already use the clock when we share it.
4144          *
4145          * Note that enable_shared_dpll tries to do the right thing, but
4146          * get_shared_dpll unconditionally resets the pll - we need that to have
4147          * the right LVDS enable sequence. */
4148         intel_enable_shared_dpll(intel_crtc);
4149
4150         /* set transcoder timing, panel must allow it */
4151         assert_panel_unlocked(dev_priv, pipe);
4152         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4153
4154         intel_fdi_normal_train(crtc);
4155
4156         /* For PCH DP, enable TRANS_DP_CTL */
4157         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4158                 const struct drm_display_mode *adjusted_mode =
4159                         &intel_crtc->config->base.adjusted_mode;
4160                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4161                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4162                 temp = I915_READ(reg);
4163                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4164                           TRANS_DP_SYNC_MASK |
4165                           TRANS_DP_BPC_MASK);
4166                 temp |= TRANS_DP_OUTPUT_ENABLE;
4167                 temp |= bpc << 9; /* same format but at 11:9 */
4168
4169                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4170                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4171                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4172                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4173
4174                 switch (intel_trans_dp_port_sel(crtc)) {
4175                 case PORT_B:
4176                         temp |= TRANS_DP_PORT_SEL_B;
4177                         break;
4178                 case PORT_C:
4179                         temp |= TRANS_DP_PORT_SEL_C;
4180                         break;
4181                 case PORT_D:
4182                         temp |= TRANS_DP_PORT_SEL_D;
4183                         break;
4184                 default:
4185                         BUG();
4186                 }
4187
4188                 I915_WRITE(reg, temp);
4189         }
4190
4191         ironlake_enable_pch_transcoder(dev_priv, pipe);
4192 }
4193
4194 static void lpt_pch_enable(struct drm_crtc *crtc)
4195 {
4196         struct drm_device *dev = crtc->dev;
4197         struct drm_i915_private *dev_priv = dev->dev_private;
4198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4200
4201         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4202
4203         lpt_program_iclkip(crtc);
4204
4205         /* Set transcoder timing. */
4206         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4207
4208         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4209 }
4210
4211 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4212 {
4213         struct drm_i915_private *dev_priv = dev->dev_private;
4214         i915_reg_t dslreg = PIPEDSL(pipe);
4215         u32 temp;
4216
4217         temp = I915_READ(dslreg);
4218         udelay(500);
4219         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4220                 if (wait_for(I915_READ(dslreg) != temp, 5))
4221                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4222         }
4223 }
4224
4225 static int
4226 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4227                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4228                   int src_w, int src_h, int dst_w, int dst_h)
4229 {
4230         struct intel_crtc_scaler_state *scaler_state =
4231                 &crtc_state->scaler_state;
4232         struct intel_crtc *intel_crtc =
4233                 to_intel_crtc(crtc_state->base.crtc);
4234         int need_scaling;
4235
4236         need_scaling = intel_rotation_90_or_270(rotation) ?
4237                 (src_h != dst_w || src_w != dst_h):
4238                 (src_w != dst_w || src_h != dst_h);
4239
4240         /*
4241          * if plane is being disabled or scaler is no more required or force detach
4242          *  - free scaler binded to this plane/crtc
4243          *  - in order to do this, update crtc->scaler_usage
4244          *
4245          * Here scaler state in crtc_state is set free so that
4246          * scaler can be assigned to other user. Actual register
4247          * update to free the scaler is done in plane/panel-fit programming.
4248          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4249          */
4250         if (force_detach || !need_scaling) {
4251                 if (*scaler_id >= 0) {
4252                         scaler_state->scaler_users &= ~(1 << scaler_user);
4253                         scaler_state->scalers[*scaler_id].in_use = 0;
4254
4255                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4256                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4257                                 intel_crtc->pipe, scaler_user, *scaler_id,
4258                                 scaler_state->scaler_users);
4259                         *scaler_id = -1;
4260                 }
4261                 return 0;
4262         }
4263
4264         /* range checks */
4265         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4266                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4267
4268                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4269                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4270                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4271                         "size is out of scaler range\n",
4272                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4273                 return -EINVAL;
4274         }
4275
4276         /* mark this plane as a scaler user in crtc_state */
4277         scaler_state->scaler_users |= (1 << scaler_user);
4278         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4279                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4280                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4281                 scaler_state->scaler_users);
4282
4283         return 0;
4284 }
4285
4286 /**
4287  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4288  *
4289  * @state: crtc's scaler state
4290  *
4291  * Return
4292  *     0 - scaler_usage updated successfully
4293  *    error - requested scaling cannot be supported or other error condition
4294  */
4295 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4296 {
4297         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4298         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4299
4300         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4301                       intel_crtc->base.base.id, intel_crtc->base.name,
4302                       intel_crtc->pipe, SKL_CRTC_INDEX);
4303
4304         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4305                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4306                 state->pipe_src_w, state->pipe_src_h,
4307                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4308 }
4309
4310 /**
4311  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4312  *
4313  * @state: crtc's scaler state
4314  * @plane_state: atomic plane state to update
4315  *
4316  * Return
4317  *     0 - scaler_usage updated successfully
4318  *    error - requested scaling cannot be supported or other error condition
4319  */
4320 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4321                                    struct intel_plane_state *plane_state)
4322 {
4323
4324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4325         struct intel_plane *intel_plane =
4326                 to_intel_plane(plane_state->base.plane);
4327         struct drm_framebuffer *fb = plane_state->base.fb;
4328         int ret;
4329
4330         bool force_detach = !fb || !plane_state->visible;
4331
4332         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4333                       intel_plane->base.base.id, intel_plane->base.name,
4334                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4335
4336         ret = skl_update_scaler(crtc_state, force_detach,
4337                                 drm_plane_index(&intel_plane->base),
4338                                 &plane_state->scaler_id,
4339                                 plane_state->base.rotation,
4340                                 drm_rect_width(&plane_state->src) >> 16,
4341                                 drm_rect_height(&plane_state->src) >> 16,
4342                                 drm_rect_width(&plane_state->dst),
4343                                 drm_rect_height(&plane_state->dst));
4344
4345         if (ret || plane_state->scaler_id < 0)
4346                 return ret;
4347
4348         /* check colorkey */
4349         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4350                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4351                               intel_plane->base.base.id,
4352                               intel_plane->base.name);
4353                 return -EINVAL;
4354         }
4355
4356         /* Check src format */
4357         switch (fb->pixel_format) {
4358         case DRM_FORMAT_RGB565:
4359         case DRM_FORMAT_XBGR8888:
4360         case DRM_FORMAT_XRGB8888:
4361         case DRM_FORMAT_ABGR8888:
4362         case DRM_FORMAT_ARGB8888:
4363         case DRM_FORMAT_XRGB2101010:
4364         case DRM_FORMAT_XBGR2101010:
4365         case DRM_FORMAT_YUYV:
4366         case DRM_FORMAT_YVYU:
4367         case DRM_FORMAT_UYVY:
4368         case DRM_FORMAT_VYUY:
4369                 break;
4370         default:
4371                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4372                               intel_plane->base.base.id, intel_plane->base.name,
4373                               fb->base.id, fb->pixel_format);
4374                 return -EINVAL;
4375         }
4376
4377         return 0;
4378 }
4379
4380 static void skylake_scaler_disable(struct intel_crtc *crtc)
4381 {
4382         int i;
4383
4384         for (i = 0; i < crtc->num_scalers; i++)
4385                 skl_detach_scaler(crtc, i);
4386 }
4387
4388 static void skylake_pfit_enable(struct intel_crtc *crtc)
4389 {
4390         struct drm_device *dev = crtc->base.dev;
4391         struct drm_i915_private *dev_priv = dev->dev_private;
4392         int pipe = crtc->pipe;
4393         struct intel_crtc_scaler_state *scaler_state =
4394                 &crtc->config->scaler_state;
4395
4396         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4397
4398         if (crtc->config->pch_pfit.enabled) {
4399                 int id;
4400
4401                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4402                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4403                         return;
4404                 }
4405
4406                 id = scaler_state->scaler_id;
4407                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4408                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4409                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4410                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4411
4412                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4413         }
4414 }
4415
4416 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4417 {
4418         struct drm_device *dev = crtc->base.dev;
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420         int pipe = crtc->pipe;
4421
4422         if (crtc->config->pch_pfit.enabled) {
4423                 /* Force use of hard-coded filter coefficients
4424                  * as some pre-programmed values are broken,
4425                  * e.g. x201.
4426                  */
4427                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4428                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4429                                                  PF_PIPE_SEL_IVB(pipe));
4430                 else
4431                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4432                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4433                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4434         }
4435 }
4436
4437 void hsw_enable_ips(struct intel_crtc *crtc)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = dev->dev_private;
4441
4442         if (!crtc->config->ips_enabled)
4443                 return;
4444
4445         /*
4446          * We can only enable IPS after we enable a plane and wait for a vblank
4447          * This function is called from post_plane_update, which is run after
4448          * a vblank wait.
4449          */
4450
4451         assert_plane_enabled(dev_priv, crtc->plane);
4452         if (IS_BROADWELL(dev)) {
4453                 mutex_lock(&dev_priv->rps.hw_lock);
4454                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4455                 mutex_unlock(&dev_priv->rps.hw_lock);
4456                 /* Quoting Art Runyan: "its not safe to expect any particular
4457                  * value in IPS_CTL bit 31 after enabling IPS through the
4458                  * mailbox." Moreover, the mailbox may return a bogus state,
4459                  * so we need to just enable it and continue on.
4460                  */
4461         } else {
4462                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4463                 /* The bit only becomes 1 in the next vblank, so this wait here
4464                  * is essentially intel_wait_for_vblank. If we don't have this
4465                  * and don't wait for vblanks until the end of crtc_enable, then
4466                  * the HW state readout code will complain that the expected
4467                  * IPS_CTL value is not the one we read. */
4468                 if (intel_wait_for_register(dev_priv,
4469                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4470                                             50))
4471                         DRM_ERROR("Timed out waiting for IPS enable\n");
4472         }
4473 }
4474
4475 void hsw_disable_ips(struct intel_crtc *crtc)
4476 {
4477         struct drm_device *dev = crtc->base.dev;
4478         struct drm_i915_private *dev_priv = dev->dev_private;
4479
4480         if (!crtc->config->ips_enabled)
4481                 return;
4482
4483         assert_plane_enabled(dev_priv, crtc->plane);
4484         if (IS_BROADWELL(dev)) {
4485                 mutex_lock(&dev_priv->rps.hw_lock);
4486                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4487                 mutex_unlock(&dev_priv->rps.hw_lock);
4488                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4489                 if (intel_wait_for_register(dev_priv,
4490                                             IPS_CTL, IPS_ENABLE, 0,
4491                                             42))
4492                         DRM_ERROR("Timed out waiting for IPS disable\n");
4493         } else {
4494                 I915_WRITE(IPS_CTL, 0);
4495                 POSTING_READ(IPS_CTL);
4496         }
4497
4498         /* We need to wait for a vblank before we can disable the plane. */
4499         intel_wait_for_vblank(dev, crtc->pipe);
4500 }
4501
4502 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4503 {
4504         if (intel_crtc->overlay) {
4505                 struct drm_device *dev = intel_crtc->base.dev;
4506                 struct drm_i915_private *dev_priv = dev->dev_private;
4507
4508                 mutex_lock(&dev->struct_mutex);
4509                 dev_priv->mm.interruptible = false;
4510                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4511                 dev_priv->mm.interruptible = true;
4512                 mutex_unlock(&dev->struct_mutex);
4513         }
4514
4515         /* Let userspace switch the overlay on again. In most cases userspace
4516          * has to recompute where to put it anyway.
4517          */
4518 }
4519
4520 /**
4521  * intel_post_enable_primary - Perform operations after enabling primary plane
4522  * @crtc: the CRTC whose primary plane was just enabled
4523  *
4524  * Performs potentially sleeping operations that must be done after the primary
4525  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4526  * called due to an explicit primary plane update, or due to an implicit
4527  * re-enable that is caused when a sprite plane is updated to no longer
4528  * completely hide the primary plane.
4529  */
4530 static void
4531 intel_post_enable_primary(struct drm_crtc *crtc)
4532 {
4533         struct drm_device *dev = crtc->dev;
4534         struct drm_i915_private *dev_priv = dev->dev_private;
4535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4536         int pipe = intel_crtc->pipe;
4537
4538         /*
4539          * FIXME IPS should be fine as long as one plane is
4540          * enabled, but in practice it seems to have problems
4541          * when going from primary only to sprite only and vice
4542          * versa.
4543          */
4544         hsw_enable_ips(intel_crtc);
4545
4546         /*
4547          * Gen2 reports pipe underruns whenever all planes are disabled.
4548          * So don't enable underrun reporting before at least some planes
4549          * are enabled.
4550          * FIXME: Need to fix the logic to work when we turn off all planes
4551          * but leave the pipe running.
4552          */
4553         if (IS_GEN2(dev))
4554                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4555
4556         /* Underruns don't always raise interrupts, so check manually. */
4557         intel_check_cpu_fifo_underruns(dev_priv);
4558         intel_check_pch_fifo_underruns(dev_priv);
4559 }
4560
4561 /* FIXME move all this to pre_plane_update() with proper state tracking */
4562 static void
4563 intel_pre_disable_primary(struct drm_crtc *crtc)
4564 {
4565         struct drm_device *dev = crtc->dev;
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4568         int pipe = intel_crtc->pipe;
4569
4570         /*
4571          * Gen2 reports pipe underruns whenever all planes are disabled.
4572          * So diasble underrun reporting before all the planes get disabled.
4573          * FIXME: Need to fix the logic to work when we turn off all planes
4574          * but leave the pipe running.
4575          */
4576         if (IS_GEN2(dev))
4577                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4578
4579         /*
4580          * FIXME IPS should be fine as long as one plane is
4581          * enabled, but in practice it seems to have problems
4582          * when going from primary only to sprite only and vice
4583          * versa.
4584          */
4585         hsw_disable_ips(intel_crtc);
4586 }
4587
4588 /* FIXME get rid of this and use pre_plane_update */
4589 static void
4590 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4591 {
4592         struct drm_device *dev = crtc->dev;
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595         int pipe = intel_crtc->pipe;
4596
4597         intel_pre_disable_primary(crtc);
4598
4599         /*
4600          * Vblank time updates from the shadow to live plane control register
4601          * are blocked if the memory self-refresh mode is active at that
4602          * moment. So to make sure the plane gets truly disabled, disable
4603          * first the self-refresh mode. The self-refresh enable bit in turn
4604          * will be checked/applied by the HW only at the next frame start
4605          * event which is after the vblank start event, so we need to have a
4606          * wait-for-vblank between disabling the plane and the pipe.
4607          */
4608         if (HAS_GMCH_DISPLAY(dev)) {
4609                 intel_set_memory_cxsr(dev_priv, false);
4610                 dev_priv->wm.vlv.cxsr = false;
4611                 intel_wait_for_vblank(dev, pipe);
4612         }
4613 }
4614
4615 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4616 {
4617         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4618         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4619         struct intel_crtc_state *pipe_config =
4620                 to_intel_crtc_state(crtc->base.state);
4621         struct drm_device *dev = crtc->base.dev;
4622         struct drm_plane *primary = crtc->base.primary;
4623         struct drm_plane_state *old_pri_state =
4624                 drm_atomic_get_existing_plane_state(old_state, primary);
4625
4626         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4627
4628         crtc->wm.cxsr_allowed = true;
4629
4630         if (pipe_config->update_wm_post && pipe_config->base.active)
4631                 intel_update_watermarks(&crtc->base);
4632
4633         if (old_pri_state) {
4634                 struct intel_plane_state *primary_state =
4635                         to_intel_plane_state(primary->state);
4636                 struct intel_plane_state *old_primary_state =
4637                         to_intel_plane_state(old_pri_state);
4638
4639                 intel_fbc_post_update(crtc);
4640
4641                 if (primary_state->visible &&
4642                     (needs_modeset(&pipe_config->base) ||
4643                      !old_primary_state->visible))
4644                         intel_post_enable_primary(&crtc->base);
4645         }
4646 }
4647
4648 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4649 {
4650         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4651         struct drm_device *dev = crtc->base.dev;
4652         struct drm_i915_private *dev_priv = dev->dev_private;
4653         struct intel_crtc_state *pipe_config =
4654                 to_intel_crtc_state(crtc->base.state);
4655         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4656         struct drm_plane *primary = crtc->base.primary;
4657         struct drm_plane_state *old_pri_state =
4658                 drm_atomic_get_existing_plane_state(old_state, primary);
4659         bool modeset = needs_modeset(&pipe_config->base);
4660
4661         if (old_pri_state) {
4662                 struct intel_plane_state *primary_state =
4663                         to_intel_plane_state(primary->state);
4664                 struct intel_plane_state *old_primary_state =
4665                         to_intel_plane_state(old_pri_state);
4666
4667                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4668
4669                 if (old_primary_state->visible &&
4670                     (modeset || !primary_state->visible))
4671                         intel_pre_disable_primary(&crtc->base);
4672         }
4673
4674         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4675                 crtc->wm.cxsr_allowed = false;
4676
4677                 /*
4678                  * Vblank time updates from the shadow to live plane control register
4679                  * are blocked if the memory self-refresh mode is active at that
4680                  * moment. So to make sure the plane gets truly disabled, disable
4681                  * first the self-refresh mode. The self-refresh enable bit in turn
4682                  * will be checked/applied by the HW only at the next frame start
4683                  * event which is after the vblank start event, so we need to have a
4684                  * wait-for-vblank between disabling the plane and the pipe.
4685                  */
4686                 if (old_crtc_state->base.active) {
4687                         intel_set_memory_cxsr(dev_priv, false);
4688                         dev_priv->wm.vlv.cxsr = false;
4689                         intel_wait_for_vblank(dev, crtc->pipe);
4690                 }
4691         }
4692
4693         /*
4694          * IVB workaround: must disable low power watermarks for at least
4695          * one frame before enabling scaling.  LP watermarks can be re-enabled
4696          * when scaling is disabled.
4697          *
4698          * WaCxSRDisabledForSpriteScaling:ivb
4699          */
4700         if (pipe_config->disable_lp_wm) {
4701                 ilk_disable_lp_wm(dev);
4702                 intel_wait_for_vblank(dev, crtc->pipe);
4703         }
4704
4705         /*
4706          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4707          * watermark programming here.
4708          */
4709         if (needs_modeset(&pipe_config->base))
4710                 return;
4711
4712         /*
4713          * For platforms that support atomic watermarks, program the
4714          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4715          * will be the intermediate values that are safe for both pre- and
4716          * post- vblank; when vblank happens, the 'active' values will be set
4717          * to the final 'target' values and we'll do this again to get the
4718          * optimal watermarks.  For gen9+ platforms, the values we program here
4719          * will be the final target values which will get automatically latched
4720          * at vblank time; no further programming will be necessary.
4721          *
4722          * If a platform hasn't been transitioned to atomic watermarks yet,
4723          * we'll continue to update watermarks the old way, if flags tell
4724          * us to.
4725          */
4726         if (dev_priv->display.initial_watermarks != NULL)
4727                 dev_priv->display.initial_watermarks(pipe_config);
4728         else if (pipe_config->update_wm_pre)
4729                 intel_update_watermarks(&crtc->base);
4730 }
4731
4732 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4733 {
4734         struct drm_device *dev = crtc->dev;
4735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4736         struct drm_plane *p;
4737         int pipe = intel_crtc->pipe;
4738
4739         intel_crtc_dpms_overlay_disable(intel_crtc);
4740
4741         drm_for_each_plane_mask(p, dev, plane_mask)
4742                 to_intel_plane(p)->disable_plane(p, crtc);
4743
4744         /*
4745          * FIXME: Once we grow proper nuclear flip support out of this we need
4746          * to compute the mask of flip planes precisely. For the time being
4747          * consider this a flip to a NULL plane.
4748          */
4749         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4750 }
4751
4752 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4753 {
4754         struct drm_device *dev = crtc->dev;
4755         struct drm_i915_private *dev_priv = dev->dev_private;
4756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4757         struct intel_encoder *encoder;
4758         int pipe = intel_crtc->pipe;
4759         struct intel_crtc_state *pipe_config =
4760                 to_intel_crtc_state(crtc->state);
4761
4762         if (WARN_ON(intel_crtc->active))
4763                 return;
4764
4765         /*
4766          * Sometimes spurious CPU pipe underruns happen during FDI
4767          * training, at least with VGA+HDMI cloning. Suppress them.
4768          *
4769          * On ILK we get an occasional spurious CPU pipe underruns
4770          * between eDP port A enable and vdd enable. Also PCH port
4771          * enable seems to result in the occasional CPU pipe underrun.
4772          *
4773          * Spurious PCH underruns also occur during PCH enabling.
4774          */
4775         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4776                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4777         if (intel_crtc->config->has_pch_encoder)
4778                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4779
4780         if (intel_crtc->config->has_pch_encoder)
4781                 intel_prepare_shared_dpll(intel_crtc);
4782
4783         if (intel_crtc->config->has_dp_encoder)
4784                 intel_dp_set_m_n(intel_crtc, M1_N1);
4785
4786         intel_set_pipe_timings(intel_crtc);
4787         intel_set_pipe_src_size(intel_crtc);
4788
4789         if (intel_crtc->config->has_pch_encoder) {
4790                 intel_cpu_transcoder_set_m_n(intel_crtc,
4791                                      &intel_crtc->config->fdi_m_n, NULL);
4792         }
4793
4794         ironlake_set_pipeconf(crtc);
4795
4796         intel_crtc->active = true;
4797
4798         for_each_encoder_on_crtc(dev, crtc, encoder)
4799                 if (encoder->pre_enable)
4800                         encoder->pre_enable(encoder);
4801
4802         if (intel_crtc->config->has_pch_encoder) {
4803                 /* Note: FDI PLL enabling _must_ be done before we enable the
4804                  * cpu pipes, hence this is separate from all the other fdi/pch
4805                  * enabling. */
4806                 ironlake_fdi_pll_enable(intel_crtc);
4807         } else {
4808                 assert_fdi_tx_disabled(dev_priv, pipe);
4809                 assert_fdi_rx_disabled(dev_priv, pipe);
4810         }
4811
4812         ironlake_pfit_enable(intel_crtc);
4813
4814         /*
4815          * On ILK+ LUT must be loaded before the pipe is running but with
4816          * clocks enabled
4817          */
4818         intel_color_load_luts(&pipe_config->base);
4819
4820         if (dev_priv->display.initial_watermarks != NULL)
4821                 dev_priv->display.initial_watermarks(intel_crtc->config);
4822         intel_enable_pipe(intel_crtc);
4823
4824         if (intel_crtc->config->has_pch_encoder)
4825                 ironlake_pch_enable(crtc);
4826
4827         assert_vblank_disabled(crtc);
4828         drm_crtc_vblank_on(crtc);
4829
4830         for_each_encoder_on_crtc(dev, crtc, encoder)
4831                 encoder->enable(encoder);
4832
4833         if (HAS_PCH_CPT(dev))
4834                 cpt_verify_modeset(dev, intel_crtc->pipe);
4835
4836         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4837         if (intel_crtc->config->has_pch_encoder)
4838                 intel_wait_for_vblank(dev, pipe);
4839         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4840         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4841 }
4842
4843 /* IPS only exists on ULT machines and is tied to pipe A. */
4844 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4845 {
4846         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4847 }
4848
4849 static void haswell_crtc_enable(struct drm_crtc *crtc)
4850 {
4851         struct drm_device *dev = crtc->dev;
4852         struct drm_i915_private *dev_priv = dev->dev_private;
4853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854         struct intel_encoder *encoder;
4855         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4856         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4857         struct intel_crtc_state *pipe_config =
4858                 to_intel_crtc_state(crtc->state);
4859
4860         if (WARN_ON(intel_crtc->active))
4861                 return;
4862
4863         if (intel_crtc->config->has_pch_encoder)
4864                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4865                                                       false);
4866
4867         for_each_encoder_on_crtc(dev, crtc, encoder)
4868                 if (encoder->pre_pll_enable)
4869                         encoder->pre_pll_enable(encoder);
4870
4871         if (intel_crtc->config->shared_dpll)
4872                 intel_enable_shared_dpll(intel_crtc);
4873
4874         if (intel_crtc->config->has_dp_encoder)
4875                 intel_dp_set_m_n(intel_crtc, M1_N1);
4876
4877         if (!intel_crtc->config->has_dsi_encoder)
4878                 intel_set_pipe_timings(intel_crtc);
4879
4880         intel_set_pipe_src_size(intel_crtc);
4881
4882         if (cpu_transcoder != TRANSCODER_EDP &&
4883             !transcoder_is_dsi(cpu_transcoder)) {
4884                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4885                            intel_crtc->config->pixel_multiplier - 1);
4886         }
4887
4888         if (intel_crtc->config->has_pch_encoder) {
4889                 intel_cpu_transcoder_set_m_n(intel_crtc,
4890                                      &intel_crtc->config->fdi_m_n, NULL);
4891         }
4892
4893         if (!intel_crtc->config->has_dsi_encoder)
4894                 haswell_set_pipeconf(crtc);
4895
4896         haswell_set_pipemisc(crtc);
4897
4898         intel_color_set_csc(&pipe_config->base);
4899
4900         intel_crtc->active = true;
4901
4902         if (intel_crtc->config->has_pch_encoder)
4903                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4904         else
4905                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906
4907         for_each_encoder_on_crtc(dev, crtc, encoder) {
4908                 if (encoder->pre_enable)
4909                         encoder->pre_enable(encoder);
4910         }
4911
4912         if (intel_crtc->config->has_pch_encoder)
4913                 dev_priv->display.fdi_link_train(crtc);
4914
4915         if (!intel_crtc->config->has_dsi_encoder)
4916                 intel_ddi_enable_pipe_clock(intel_crtc);
4917
4918         if (INTEL_INFO(dev)->gen >= 9)
4919                 skylake_pfit_enable(intel_crtc);
4920         else
4921                 ironlake_pfit_enable(intel_crtc);
4922
4923         /*
4924          * On ILK+ LUT must be loaded before the pipe is running but with
4925          * clocks enabled
4926          */
4927         intel_color_load_luts(&pipe_config->base);
4928
4929         intel_ddi_set_pipe_settings(crtc);
4930         if (!intel_crtc->config->has_dsi_encoder)
4931                 intel_ddi_enable_transcoder_func(crtc);
4932
4933         if (dev_priv->display.initial_watermarks != NULL)
4934                 dev_priv->display.initial_watermarks(pipe_config);
4935         else
4936                 intel_update_watermarks(crtc);
4937
4938         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4939         if (!intel_crtc->config->has_dsi_encoder)
4940                 intel_enable_pipe(intel_crtc);
4941
4942         if (intel_crtc->config->has_pch_encoder)
4943                 lpt_pch_enable(crtc);
4944
4945         if (intel_crtc->config->dp_encoder_is_mst)
4946                 intel_ddi_set_vc_payload_alloc(crtc, true);
4947
4948         assert_vblank_disabled(crtc);
4949         drm_crtc_vblank_on(crtc);
4950
4951         for_each_encoder_on_crtc(dev, crtc, encoder) {
4952                 encoder->enable(encoder);
4953                 intel_opregion_notify_encoder(encoder, true);
4954         }
4955
4956         if (intel_crtc->config->has_pch_encoder) {
4957                 intel_wait_for_vblank(dev, pipe);
4958                 intel_wait_for_vblank(dev, pipe);
4959                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4960                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4961                                                       true);
4962         }
4963
4964         /* If we change the relative order between pipe/planes enabling, we need
4965          * to change the workaround. */
4966         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4967         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4968                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4969                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4970         }
4971 }
4972
4973 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4974 {
4975         struct drm_device *dev = crtc->base.dev;
4976         struct drm_i915_private *dev_priv = dev->dev_private;
4977         int pipe = crtc->pipe;
4978
4979         /* To avoid upsetting the power well on haswell only disable the pfit if
4980          * it's in use. The hw state code will make sure we get this right. */
4981         if (force || crtc->config->pch_pfit.enabled) {
4982                 I915_WRITE(PF_CTL(pipe), 0);
4983                 I915_WRITE(PF_WIN_POS(pipe), 0);
4984                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4985         }
4986 }
4987
4988 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4989 {
4990         struct drm_device *dev = crtc->dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993         struct intel_encoder *encoder;
4994         int pipe = intel_crtc->pipe;
4995
4996         /*
4997          * Sometimes spurious CPU pipe underruns happen when the
4998          * pipe is already disabled, but FDI RX/TX is still enabled.
4999          * Happens at least with VGA+HDMI cloning. Suppress them.
5000          */
5001         if (intel_crtc->config->has_pch_encoder) {
5002                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5003                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5004         }
5005
5006         for_each_encoder_on_crtc(dev, crtc, encoder)
5007                 encoder->disable(encoder);
5008
5009         drm_crtc_vblank_off(crtc);
5010         assert_vblank_disabled(crtc);
5011
5012         intel_disable_pipe(intel_crtc);
5013
5014         ironlake_pfit_disable(intel_crtc, false);
5015
5016         if (intel_crtc->config->has_pch_encoder)
5017                 ironlake_fdi_disable(crtc);
5018
5019         for_each_encoder_on_crtc(dev, crtc, encoder)
5020                 if (encoder->post_disable)
5021                         encoder->post_disable(encoder);
5022
5023         if (intel_crtc->config->has_pch_encoder) {
5024                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5025
5026                 if (HAS_PCH_CPT(dev)) {
5027                         i915_reg_t reg;
5028                         u32 temp;
5029
5030                         /* disable TRANS_DP_CTL */
5031                         reg = TRANS_DP_CTL(pipe);
5032                         temp = I915_READ(reg);
5033                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5034                                   TRANS_DP_PORT_SEL_MASK);
5035                         temp |= TRANS_DP_PORT_SEL_NONE;
5036                         I915_WRITE(reg, temp);
5037
5038                         /* disable DPLL_SEL */
5039                         temp = I915_READ(PCH_DPLL_SEL);
5040                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5041                         I915_WRITE(PCH_DPLL_SEL, temp);
5042                 }
5043
5044                 ironlake_fdi_pll_disable(intel_crtc);
5045         }
5046
5047         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5048         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5049 }
5050
5051 static void haswell_crtc_disable(struct drm_crtc *crtc)
5052 {
5053         struct drm_device *dev = crtc->dev;
5054         struct drm_i915_private *dev_priv = dev->dev_private;
5055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5056         struct intel_encoder *encoder;
5057         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5058
5059         if (intel_crtc->config->has_pch_encoder)
5060                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5061                                                       false);
5062
5063         for_each_encoder_on_crtc(dev, crtc, encoder) {
5064                 intel_opregion_notify_encoder(encoder, false);
5065                 encoder->disable(encoder);
5066         }
5067
5068         drm_crtc_vblank_off(crtc);
5069         assert_vblank_disabled(crtc);
5070
5071         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5072         if (!intel_crtc->config->has_dsi_encoder)
5073                 intel_disable_pipe(intel_crtc);
5074
5075         if (intel_crtc->config->dp_encoder_is_mst)
5076                 intel_ddi_set_vc_payload_alloc(crtc, false);
5077
5078         if (!intel_crtc->config->has_dsi_encoder)
5079                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5080
5081         if (INTEL_INFO(dev)->gen >= 9)
5082                 skylake_scaler_disable(intel_crtc);
5083         else
5084                 ironlake_pfit_disable(intel_crtc, false);
5085
5086         if (!intel_crtc->config->has_dsi_encoder)
5087                 intel_ddi_disable_pipe_clock(intel_crtc);
5088
5089         for_each_encoder_on_crtc(dev, crtc, encoder)
5090                 if (encoder->post_disable)
5091                         encoder->post_disable(encoder);
5092
5093         if (intel_crtc->config->has_pch_encoder) {
5094                 lpt_disable_pch_transcoder(dev_priv);
5095                 lpt_disable_iclkip(dev_priv);
5096                 intel_ddi_fdi_disable(crtc);
5097
5098                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5099                                                       true);
5100         }
5101 }
5102
5103 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5104 {
5105         struct drm_device *dev = crtc->base.dev;
5106         struct drm_i915_private *dev_priv = dev->dev_private;
5107         struct intel_crtc_state *pipe_config = crtc->config;
5108
5109         if (!pipe_config->gmch_pfit.control)
5110                 return;
5111
5112         /*
5113          * The panel fitter should only be adjusted whilst the pipe is disabled,
5114          * according to register description and PRM.
5115          */
5116         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5117         assert_pipe_disabled(dev_priv, crtc->pipe);
5118
5119         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5120         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5121
5122         /* Border color in case we don't scale up to the full screen. Black by
5123          * default, change to something else for debugging. */
5124         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5125 }
5126
5127 static enum intel_display_power_domain port_to_power_domain(enum port port)
5128 {
5129         switch (port) {
5130         case PORT_A:
5131                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5132         case PORT_B:
5133                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5134         case PORT_C:
5135                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5136         case PORT_D:
5137                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5138         case PORT_E:
5139                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5140         default:
5141                 MISSING_CASE(port);
5142                 return POWER_DOMAIN_PORT_OTHER;
5143         }
5144 }
5145
5146 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5147 {
5148         switch (port) {
5149         case PORT_A:
5150                 return POWER_DOMAIN_AUX_A;
5151         case PORT_B:
5152                 return POWER_DOMAIN_AUX_B;
5153         case PORT_C:
5154                 return POWER_DOMAIN_AUX_C;
5155         case PORT_D:
5156                 return POWER_DOMAIN_AUX_D;
5157         case PORT_E:
5158                 /* FIXME: Check VBT for actual wiring of PORT E */
5159                 return POWER_DOMAIN_AUX_D;
5160         default:
5161                 MISSING_CASE(port);
5162                 return POWER_DOMAIN_AUX_A;
5163         }
5164 }
5165
5166 enum intel_display_power_domain
5167 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5168 {
5169         struct drm_device *dev = intel_encoder->base.dev;
5170         struct intel_digital_port *intel_dig_port;
5171
5172         switch (intel_encoder->type) {
5173         case INTEL_OUTPUT_UNKNOWN:
5174                 /* Only DDI platforms should ever use this output type */
5175                 WARN_ON_ONCE(!HAS_DDI(dev));
5176         case INTEL_OUTPUT_DISPLAYPORT:
5177         case INTEL_OUTPUT_HDMI:
5178         case INTEL_OUTPUT_EDP:
5179                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5180                 return port_to_power_domain(intel_dig_port->port);
5181         case INTEL_OUTPUT_DP_MST:
5182                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5183                 return port_to_power_domain(intel_dig_port->port);
5184         case INTEL_OUTPUT_ANALOG:
5185                 return POWER_DOMAIN_PORT_CRT;
5186         case INTEL_OUTPUT_DSI:
5187                 return POWER_DOMAIN_PORT_DSI;
5188         default:
5189                 return POWER_DOMAIN_PORT_OTHER;
5190         }
5191 }
5192
5193 enum intel_display_power_domain
5194 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5195 {
5196         struct drm_device *dev = intel_encoder->base.dev;
5197         struct intel_digital_port *intel_dig_port;
5198
5199         switch (intel_encoder->type) {
5200         case INTEL_OUTPUT_UNKNOWN:
5201         case INTEL_OUTPUT_HDMI:
5202                 /*
5203                  * Only DDI platforms should ever use these output types.
5204                  * We can get here after the HDMI detect code has already set
5205                  * the type of the shared encoder. Since we can't be sure
5206                  * what's the status of the given connectors, play safe and
5207                  * run the DP detection too.
5208                  */
5209                 WARN_ON_ONCE(!HAS_DDI(dev));
5210         case INTEL_OUTPUT_DISPLAYPORT:
5211         case INTEL_OUTPUT_EDP:
5212                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5213                 return port_to_aux_power_domain(intel_dig_port->port);
5214         case INTEL_OUTPUT_DP_MST:
5215                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5216                 return port_to_aux_power_domain(intel_dig_port->port);
5217         default:
5218                 MISSING_CASE(intel_encoder->type);
5219                 return POWER_DOMAIN_AUX_A;
5220         }
5221 }
5222
5223 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5224                                             struct intel_crtc_state *crtc_state)
5225 {
5226         struct drm_device *dev = crtc->dev;
5227         struct drm_encoder *encoder;
5228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229         enum pipe pipe = intel_crtc->pipe;
5230         unsigned long mask;
5231         enum transcoder transcoder = crtc_state->cpu_transcoder;
5232
5233         if (!crtc_state->base.active)
5234                 return 0;
5235
5236         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5237         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5238         if (crtc_state->pch_pfit.enabled ||
5239             crtc_state->pch_pfit.force_thru)
5240                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5241
5242         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5243                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5244
5245                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5246         }
5247
5248         if (crtc_state->shared_dpll)
5249                 mask |= BIT(POWER_DOMAIN_PLLS);
5250
5251         return mask;
5252 }
5253
5254 static unsigned long
5255 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5256                                struct intel_crtc_state *crtc_state)
5257 {
5258         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5260         enum intel_display_power_domain domain;
5261         unsigned long domains, new_domains, old_domains;
5262
5263         old_domains = intel_crtc->enabled_power_domains;
5264         intel_crtc->enabled_power_domains = new_domains =
5265                 get_crtc_power_domains(crtc, crtc_state);
5266
5267         domains = new_domains & ~old_domains;
5268
5269         for_each_power_domain(domain, domains)
5270                 intel_display_power_get(dev_priv, domain);
5271
5272         return old_domains & ~new_domains;
5273 }
5274
5275 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5276                                       unsigned long domains)
5277 {
5278         enum intel_display_power_domain domain;
5279
5280         for_each_power_domain(domain, domains)
5281                 intel_display_power_put(dev_priv, domain);
5282 }
5283
5284 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5285 {
5286         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5287
5288         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5289             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5290                 return max_cdclk_freq;
5291         else if (IS_CHERRYVIEW(dev_priv))
5292                 return max_cdclk_freq*95/100;
5293         else if (INTEL_INFO(dev_priv)->gen < 4)
5294                 return 2*max_cdclk_freq*90/100;
5295         else
5296                 return max_cdclk_freq*90/100;
5297 }
5298
5299 static int skl_calc_cdclk(int max_pixclk, int vco);
5300
5301 static void intel_update_max_cdclk(struct drm_device *dev)
5302 {
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304
5305         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5306                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5307                 int max_cdclk, vco;
5308
5309                 vco = dev_priv->skl_preferred_vco_freq;
5310                 WARN_ON(vco != 8100000 && vco != 8640000);
5311
5312                 /*
5313                  * Use the lower (vco 8640) cdclk values as a
5314                  * first guess. skl_calc_cdclk() will correct it
5315                  * if the preferred vco is 8100 instead.
5316                  */
5317                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5318                         max_cdclk = 617143;
5319                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5320                         max_cdclk = 540000;
5321                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5322                         max_cdclk = 432000;
5323                 else
5324                         max_cdclk = 308571;
5325
5326                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5327         } else if (IS_BROXTON(dev)) {
5328                 dev_priv->max_cdclk_freq = 624000;
5329         } else if (IS_BROADWELL(dev))  {
5330                 /*
5331                  * FIXME with extra cooling we can allow
5332                  * 540 MHz for ULX and 675 Mhz for ULT.
5333                  * How can we know if extra cooling is
5334                  * available? PCI ID, VTB, something else?
5335                  */
5336                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5337                         dev_priv->max_cdclk_freq = 450000;
5338                 else if (IS_BDW_ULX(dev))
5339                         dev_priv->max_cdclk_freq = 450000;
5340                 else if (IS_BDW_ULT(dev))
5341                         dev_priv->max_cdclk_freq = 540000;
5342                 else
5343                         dev_priv->max_cdclk_freq = 675000;
5344         } else if (IS_CHERRYVIEW(dev)) {
5345                 dev_priv->max_cdclk_freq = 320000;
5346         } else if (IS_VALLEYVIEW(dev)) {
5347                 dev_priv->max_cdclk_freq = 400000;
5348         } else {
5349                 /* otherwise assume cdclk is fixed */
5350                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5351         }
5352
5353         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5354
5355         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5356                          dev_priv->max_cdclk_freq);
5357
5358         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5359                          dev_priv->max_dotclk_freq);
5360 }
5361
5362 static void intel_update_cdclk(struct drm_device *dev)
5363 {
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5367
5368         if (INTEL_GEN(dev_priv) >= 9)
5369                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5370                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5371                                  dev_priv->cdclk_pll.ref);
5372         else
5373                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5374                                  dev_priv->cdclk_freq);
5375
5376         /*
5377          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5378          * Programmng [sic] note: bit[9:2] should be programmed to the number
5379          * of cdclk that generates 4MHz reference clock freq which is used to
5380          * generate GMBus clock. This will vary with the cdclk freq.
5381          */
5382         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5383                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5384 }
5385
5386 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5387 static int skl_cdclk_decimal(int cdclk)
5388 {
5389         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5390 }
5391
5392 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5393 {
5394         int ratio;
5395
5396         if (cdclk == dev_priv->cdclk_pll.ref)
5397                 return 0;
5398
5399         switch (cdclk) {
5400         default:
5401                 MISSING_CASE(cdclk);
5402         case 144000:
5403         case 288000:
5404         case 384000:
5405         case 576000:
5406                 ratio = 60;
5407                 break;
5408         case 624000:
5409                 ratio = 65;
5410                 break;
5411         }
5412
5413         return dev_priv->cdclk_pll.ref * ratio;
5414 }
5415
5416 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5417 {
5418         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5419
5420         /* Timeout 200us */
5421         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5422                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5423
5424         dev_priv->cdclk_pll.vco = 0;
5425 }
5426
5427 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5428 {
5429         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5430         u32 val;
5431
5432         val = I915_READ(BXT_DE_PLL_CTL);
5433         val &= ~BXT_DE_PLL_RATIO_MASK;
5434         val |= BXT_DE_PLL_RATIO(ratio);
5435         I915_WRITE(BXT_DE_PLL_CTL, val);
5436
5437         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5438
5439         /* Timeout 200us */
5440         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5441                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5442
5443         dev_priv->cdclk_pll.vco = vco;
5444 }
5445
5446 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5447 {
5448         u32 val, divider;
5449         int vco, ret;
5450
5451         vco = bxt_de_pll_vco(dev_priv, cdclk);
5452
5453         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5454
5455         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5456         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5457         case 8:
5458                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5459                 break;
5460         case 4:
5461                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5462                 break;
5463         case 3:
5464                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5465                 break;
5466         case 2:
5467                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5468                 break;
5469         default:
5470                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5471                 WARN_ON(vco != 0);
5472
5473                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5474                 break;
5475         }
5476
5477         /* Inform power controller of upcoming frequency change */
5478         mutex_lock(&dev_priv->rps.hw_lock);
5479         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5480                                       0x80000000);
5481         mutex_unlock(&dev_priv->rps.hw_lock);
5482
5483         if (ret) {
5484                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5485                           ret, cdclk);
5486                 return;
5487         }
5488
5489         if (dev_priv->cdclk_pll.vco != 0 &&
5490             dev_priv->cdclk_pll.vco != vco)
5491                 bxt_de_pll_disable(dev_priv);
5492
5493         if (dev_priv->cdclk_pll.vco != vco)
5494                 bxt_de_pll_enable(dev_priv, vco);
5495
5496         val = divider | skl_cdclk_decimal(cdclk);
5497         /*
5498          * FIXME if only the cd2x divider needs changing, it could be done
5499          * without shutting off the pipe (if only one pipe is active).
5500          */
5501         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5502         /*
5503          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5504          * enable otherwise.
5505          */
5506         if (cdclk >= 500000)
5507                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5508         I915_WRITE(CDCLK_CTL, val);
5509
5510         mutex_lock(&dev_priv->rps.hw_lock);
5511         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5512                                       DIV_ROUND_UP(cdclk, 25000));
5513         mutex_unlock(&dev_priv->rps.hw_lock);
5514
5515         if (ret) {
5516                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5517                           ret, cdclk);
5518                 return;
5519         }
5520
5521         intel_update_cdclk(dev_priv->dev);
5522 }
5523
5524 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5525 {
5526         u32 cdctl, expected;
5527
5528         intel_update_cdclk(dev_priv->dev);
5529
5530         if (dev_priv->cdclk_pll.vco == 0 ||
5531             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5532                 goto sanitize;
5533
5534         /* DPLL okay; verify the cdclock
5535          *
5536          * Some BIOS versions leave an incorrect decimal frequency value and
5537          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5538          * so sanitize this register.
5539          */
5540         cdctl = I915_READ(CDCLK_CTL);
5541         /*
5542          * Let's ignore the pipe field, since BIOS could have configured the
5543          * dividers both synching to an active pipe, or asynchronously
5544          * (PIPE_NONE).
5545          */
5546         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5547
5548         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5549                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5550         /*
5551          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5552          * enable otherwise.
5553          */
5554         if (dev_priv->cdclk_freq >= 500000)
5555                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5556
5557         if (cdctl == expected)
5558                 /* All well; nothing to sanitize */
5559                 return;
5560
5561 sanitize:
5562         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5563
5564         /* force cdclk programming */
5565         dev_priv->cdclk_freq = 0;
5566
5567         /* force full PLL disable + enable */
5568         dev_priv->cdclk_pll.vco = -1;
5569 }
5570
5571 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5572 {
5573         bxt_sanitize_cdclk(dev_priv);
5574
5575         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5576                 return;
5577
5578         /*
5579          * FIXME:
5580          * - The initial CDCLK needs to be read from VBT.
5581          *   Need to make this change after VBT has changes for BXT.
5582          */
5583         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5584 }
5585
5586 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5587 {
5588         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5589 }
5590
5591 static int skl_calc_cdclk(int max_pixclk, int vco)
5592 {
5593         if (vco == 8640000) {
5594                 if (max_pixclk > 540000)
5595                         return 617143;
5596                 else if (max_pixclk > 432000)
5597                         return 540000;
5598                 else if (max_pixclk > 308571)
5599                         return 432000;
5600                 else
5601                         return 308571;
5602         } else {
5603                 if (max_pixclk > 540000)
5604                         return 675000;
5605                 else if (max_pixclk > 450000)
5606                         return 540000;
5607                 else if (max_pixclk > 337500)
5608                         return 450000;
5609                 else
5610                         return 337500;
5611         }
5612 }
5613
5614 static void
5615 skl_dpll0_update(struct drm_i915_private *dev_priv)
5616 {
5617         u32 val;
5618
5619         dev_priv->cdclk_pll.ref = 24000;
5620         dev_priv->cdclk_pll.vco = 0;
5621
5622         val = I915_READ(LCPLL1_CTL);
5623         if ((val & LCPLL_PLL_ENABLE) == 0)
5624                 return;
5625
5626         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5627                 return;
5628
5629         val = I915_READ(DPLL_CTRL1);
5630
5631         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5632                             DPLL_CTRL1_SSC(SKL_DPLL0) |
5633                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5634                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5635                 return;
5636
5637         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5638         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5639         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5640         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5641         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5642                 dev_priv->cdclk_pll.vco = 8100000;
5643                 break;
5644         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5645         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5646                 dev_priv->cdclk_pll.vco = 8640000;
5647                 break;
5648         default:
5649                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5650                 break;
5651         }
5652 }
5653
5654 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5655 {
5656         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5657
5658         dev_priv->skl_preferred_vco_freq = vco;
5659
5660         if (changed)
5661                 intel_update_max_cdclk(dev_priv->dev);
5662 }
5663
5664 static void
5665 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5666 {
5667         int min_cdclk = skl_calc_cdclk(0, vco);
5668         u32 val;
5669
5670         WARN_ON(vco != 8100000 && vco != 8640000);
5671
5672         /* select the minimum CDCLK before enabling DPLL 0 */
5673         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5674         I915_WRITE(CDCLK_CTL, val);
5675         POSTING_READ(CDCLK_CTL);
5676
5677         /*
5678          * We always enable DPLL0 with the lowest link rate possible, but still
5679          * taking into account the VCO required to operate the eDP panel at the
5680          * desired frequency. The usual DP link rates operate with a VCO of
5681          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5682          * The modeset code is responsible for the selection of the exact link
5683          * rate later on, with the constraint of choosing a frequency that
5684          * works with vco.
5685          */
5686         val = I915_READ(DPLL_CTRL1);
5687
5688         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5689                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5690         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5691         if (vco == 8640000)
5692                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5693                                             SKL_DPLL0);
5694         else
5695                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5696                                             SKL_DPLL0);
5697
5698         I915_WRITE(DPLL_CTRL1, val);
5699         POSTING_READ(DPLL_CTRL1);
5700
5701         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5702
5703         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5704                 DRM_ERROR("DPLL0 not locked\n");
5705
5706         dev_priv->cdclk_pll.vco = vco;
5707
5708         /* We'll want to keep using the current vco from now on. */
5709         skl_set_preferred_cdclk_vco(dev_priv, vco);
5710 }
5711
5712 static void
5713 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5714 {
5715         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5716         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5717                 DRM_ERROR("Couldn't disable DPLL0\n");
5718
5719         dev_priv->cdclk_pll.vco = 0;
5720 }
5721
5722 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5723 {
5724         int ret;
5725         u32 val;
5726
5727         /* inform PCU we want to change CDCLK */
5728         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5729         mutex_lock(&dev_priv->rps.hw_lock);
5730         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5731         mutex_unlock(&dev_priv->rps.hw_lock);
5732
5733         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5734 }
5735
5736 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5737 {
5738         unsigned int i;
5739
5740         for (i = 0; i < 15; i++) {
5741                 if (skl_cdclk_pcu_ready(dev_priv))
5742                         return true;
5743                 udelay(10);
5744         }
5745
5746         return false;
5747 }
5748
5749 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5750 {
5751         struct drm_device *dev = dev_priv->dev;
5752         u32 freq_select, pcu_ack;
5753
5754         WARN_ON((cdclk == 24000) != (vco == 0));
5755
5756         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5757
5758         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5759                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5760                 return;
5761         }
5762
5763         /* set CDCLK_CTL */
5764         switch (cdclk) {
5765         case 450000:
5766         case 432000:
5767                 freq_select = CDCLK_FREQ_450_432;
5768                 pcu_ack = 1;
5769                 break;
5770         case 540000:
5771                 freq_select = CDCLK_FREQ_540;
5772                 pcu_ack = 2;
5773                 break;
5774         case 308571:
5775         case 337500:
5776         default:
5777                 freq_select = CDCLK_FREQ_337_308;
5778                 pcu_ack = 0;
5779                 break;
5780         case 617143:
5781         case 675000:
5782                 freq_select = CDCLK_FREQ_675_617;
5783                 pcu_ack = 3;
5784                 break;
5785         }
5786
5787         if (dev_priv->cdclk_pll.vco != 0 &&
5788             dev_priv->cdclk_pll.vco != vco)
5789                 skl_dpll0_disable(dev_priv);
5790
5791         if (dev_priv->cdclk_pll.vco != vco)
5792                 skl_dpll0_enable(dev_priv, vco);
5793
5794         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5795         POSTING_READ(CDCLK_CTL);
5796
5797         /* inform PCU of the change */
5798         mutex_lock(&dev_priv->rps.hw_lock);
5799         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5800         mutex_unlock(&dev_priv->rps.hw_lock);
5801
5802         intel_update_cdclk(dev);
5803 }
5804
5805 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5806
5807 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5808 {
5809         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5810 }
5811
5812 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5813 {
5814         int cdclk, vco;
5815
5816         skl_sanitize_cdclk(dev_priv);
5817
5818         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5819                 /*
5820                  * Use the current vco as our initial
5821                  * guess as to what the preferred vco is.
5822                  */
5823                 if (dev_priv->skl_preferred_vco_freq == 0)
5824                         skl_set_preferred_cdclk_vco(dev_priv,
5825                                                     dev_priv->cdclk_pll.vco);
5826                 return;
5827         }
5828
5829         vco = dev_priv->skl_preferred_vco_freq;
5830         if (vco == 0)
5831                 vco = 8100000;
5832         cdclk = skl_calc_cdclk(0, vco);
5833
5834         skl_set_cdclk(dev_priv, cdclk, vco);
5835 }
5836
5837 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5838 {
5839         uint32_t cdctl, expected;
5840
5841         /*
5842          * check if the pre-os intialized the display
5843          * There is SWF18 scratchpad register defined which is set by the
5844          * pre-os which can be used by the OS drivers to check the status
5845          */
5846         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5847                 goto sanitize;
5848
5849         intel_update_cdclk(dev_priv->dev);
5850         /* Is PLL enabled and locked ? */
5851         if (dev_priv->cdclk_pll.vco == 0 ||
5852             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5853                 goto sanitize;
5854
5855         /* DPLL okay; verify the cdclock
5856          *
5857          * Noticed in some instances that the freq selection is correct but
5858          * decimal part is programmed wrong from BIOS where pre-os does not
5859          * enable display. Verify the same as well.
5860          */
5861         cdctl = I915_READ(CDCLK_CTL);
5862         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5863                 skl_cdclk_decimal(dev_priv->cdclk_freq);
5864         if (cdctl == expected)
5865                 /* All well; nothing to sanitize */
5866                 return;
5867
5868 sanitize:
5869         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5870
5871         /* force cdclk programming */
5872         dev_priv->cdclk_freq = 0;
5873         /* force full PLL disable + enable */
5874         dev_priv->cdclk_pll.vco = -1;
5875 }
5876
5877 /* Adjust CDclk dividers to allow high res or save power if possible */
5878 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5879 {
5880         struct drm_i915_private *dev_priv = dev->dev_private;
5881         u32 val, cmd;
5882
5883         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5884                                         != dev_priv->cdclk_freq);
5885
5886         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5887                 cmd = 2;
5888         else if (cdclk == 266667)
5889                 cmd = 1;
5890         else
5891                 cmd = 0;
5892
5893         mutex_lock(&dev_priv->rps.hw_lock);
5894         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5895         val &= ~DSPFREQGUAR_MASK;
5896         val |= (cmd << DSPFREQGUAR_SHIFT);
5897         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5898         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5899                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5900                      50)) {
5901                 DRM_ERROR("timed out waiting for CDclk change\n");
5902         }
5903         mutex_unlock(&dev_priv->rps.hw_lock);
5904
5905         mutex_lock(&dev_priv->sb_lock);
5906
5907         if (cdclk == 400000) {
5908                 u32 divider;
5909
5910                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5911
5912                 /* adjust cdclk divider */
5913                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5914                 val &= ~CCK_FREQUENCY_VALUES;
5915                 val |= divider;
5916                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5917
5918                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5919                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5920                              50))
5921                         DRM_ERROR("timed out waiting for CDclk change\n");
5922         }
5923
5924         /* adjust self-refresh exit latency value */
5925         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5926         val &= ~0x7f;
5927
5928         /*
5929          * For high bandwidth configs, we set a higher latency in the bunit
5930          * so that the core display fetch happens in time to avoid underruns.
5931          */
5932         if (cdclk == 400000)
5933                 val |= 4500 / 250; /* 4.5 usec */
5934         else
5935                 val |= 3000 / 250; /* 3.0 usec */
5936         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5937
5938         mutex_unlock(&dev_priv->sb_lock);
5939
5940         intel_update_cdclk(dev);
5941 }
5942
5943 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5944 {
5945         struct drm_i915_private *dev_priv = dev->dev_private;
5946         u32 val, cmd;
5947
5948         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5949                                                 != dev_priv->cdclk_freq);
5950
5951         switch (cdclk) {
5952         case 333333:
5953         case 320000:
5954         case 266667:
5955         case 200000:
5956                 break;
5957         default:
5958                 MISSING_CASE(cdclk);
5959                 return;
5960         }
5961
5962         /*
5963          * Specs are full of misinformation, but testing on actual
5964          * hardware has shown that we just need to write the desired
5965          * CCK divider into the Punit register.
5966          */
5967         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5968
5969         mutex_lock(&dev_priv->rps.hw_lock);
5970         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5971         val &= ~DSPFREQGUAR_MASK_CHV;
5972         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5973         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5974         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5975                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5976                      50)) {
5977                 DRM_ERROR("timed out waiting for CDclk change\n");
5978         }
5979         mutex_unlock(&dev_priv->rps.hw_lock);
5980
5981         intel_update_cdclk(dev);
5982 }
5983
5984 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5985                                  int max_pixclk)
5986 {
5987         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5988         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5989
5990         /*
5991          * Really only a few cases to deal with, as only 4 CDclks are supported:
5992          *   200MHz
5993          *   267MHz
5994          *   320/333MHz (depends on HPLL freq)
5995          *   400MHz (VLV only)
5996          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5997          * of the lower bin and adjust if needed.
5998          *
5999          * We seem to get an unstable or solid color picture at 200MHz.
6000          * Not sure what's wrong. For now use 200MHz only when all pipes
6001          * are off.
6002          */
6003         if (!IS_CHERRYVIEW(dev_priv) &&
6004             max_pixclk > freq_320*limit/100)
6005                 return 400000;
6006         else if (max_pixclk > 266667*limit/100)
6007                 return freq_320;
6008         else if (max_pixclk > 0)
6009                 return 266667;
6010         else
6011                 return 200000;
6012 }
6013
6014 static int bxt_calc_cdclk(int max_pixclk)
6015 {
6016         if (max_pixclk > 576000)
6017                 return 624000;
6018         else if (max_pixclk > 384000)
6019                 return 576000;
6020         else if (max_pixclk > 288000)
6021                 return 384000;
6022         else if (max_pixclk > 144000)
6023                 return 288000;
6024         else
6025                 return 144000;
6026 }
6027
6028 /* Compute the max pixel clock for new configuration. */
6029 static int intel_mode_max_pixclk(struct drm_device *dev,
6030                                  struct drm_atomic_state *state)
6031 {
6032         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6033         struct drm_i915_private *dev_priv = dev->dev_private;
6034         struct drm_crtc *crtc;
6035         struct drm_crtc_state *crtc_state;
6036         unsigned max_pixclk = 0, i;
6037         enum pipe pipe;
6038
6039         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6040                sizeof(intel_state->min_pixclk));
6041
6042         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6043                 int pixclk = 0;
6044
6045                 if (crtc_state->enable)
6046                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6047
6048                 intel_state->min_pixclk[i] = pixclk;
6049         }
6050
6051         for_each_pipe(dev_priv, pipe)
6052                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6053
6054         return max_pixclk;
6055 }
6056
6057 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6058 {
6059         struct drm_device *dev = state->dev;
6060         struct drm_i915_private *dev_priv = dev->dev_private;
6061         int max_pixclk = intel_mode_max_pixclk(dev, state);
6062         struct intel_atomic_state *intel_state =
6063                 to_intel_atomic_state(state);
6064
6065         intel_state->cdclk = intel_state->dev_cdclk =
6066                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6067
6068         if (!intel_state->active_crtcs)
6069                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6070
6071         return 0;
6072 }
6073
6074 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6075 {
6076         int max_pixclk = ilk_max_pixel_rate(state);
6077         struct intel_atomic_state *intel_state =
6078                 to_intel_atomic_state(state);
6079
6080         intel_state->cdclk = intel_state->dev_cdclk =
6081                 bxt_calc_cdclk(max_pixclk);
6082
6083         if (!intel_state->active_crtcs)
6084                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6085
6086         return 0;
6087 }
6088
6089 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6090 {
6091         unsigned int credits, default_credits;
6092
6093         if (IS_CHERRYVIEW(dev_priv))
6094                 default_credits = PFI_CREDIT(12);
6095         else
6096                 default_credits = PFI_CREDIT(8);
6097
6098         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6099                 /* CHV suggested value is 31 or 63 */
6100                 if (IS_CHERRYVIEW(dev_priv))
6101                         credits = PFI_CREDIT_63;
6102                 else
6103                         credits = PFI_CREDIT(15);
6104         } else {
6105                 credits = default_credits;
6106         }
6107
6108         /*
6109          * WA - write default credits before re-programming
6110          * FIXME: should we also set the resend bit here?
6111          */
6112         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6113                    default_credits);
6114
6115         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6116                    credits | PFI_CREDIT_RESEND);
6117
6118         /*
6119          * FIXME is this guaranteed to clear
6120          * immediately or should we poll for it?
6121          */
6122         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6123 }
6124
6125 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6126 {
6127         struct drm_device *dev = old_state->dev;
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129         struct intel_atomic_state *old_intel_state =
6130                 to_intel_atomic_state(old_state);
6131         unsigned req_cdclk = old_intel_state->dev_cdclk;
6132
6133         /*
6134          * FIXME: We can end up here with all power domains off, yet
6135          * with a CDCLK frequency other than the minimum. To account
6136          * for this take the PIPE-A power domain, which covers the HW
6137          * blocks needed for the following programming. This can be
6138          * removed once it's guaranteed that we get here either with
6139          * the minimum CDCLK set, or the required power domains
6140          * enabled.
6141          */
6142         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6143
6144         if (IS_CHERRYVIEW(dev))
6145                 cherryview_set_cdclk(dev, req_cdclk);
6146         else
6147                 valleyview_set_cdclk(dev, req_cdclk);
6148
6149         vlv_program_pfi_credits(dev_priv);
6150
6151         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6152 }
6153
6154 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6155 {
6156         struct drm_device *dev = crtc->dev;
6157         struct drm_i915_private *dev_priv = to_i915(dev);
6158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159         struct intel_encoder *encoder;
6160         struct intel_crtc_state *pipe_config =
6161                 to_intel_crtc_state(crtc->state);
6162         int pipe = intel_crtc->pipe;
6163
6164         if (WARN_ON(intel_crtc->active))
6165                 return;
6166
6167         if (intel_crtc->config->has_dp_encoder)
6168                 intel_dp_set_m_n(intel_crtc, M1_N1);
6169
6170         intel_set_pipe_timings(intel_crtc);
6171         intel_set_pipe_src_size(intel_crtc);
6172
6173         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6174                 struct drm_i915_private *dev_priv = dev->dev_private;
6175
6176                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6177                 I915_WRITE(CHV_CANVAS(pipe), 0);
6178         }
6179
6180         i9xx_set_pipeconf(intel_crtc);
6181
6182         intel_crtc->active = true;
6183
6184         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6185
6186         for_each_encoder_on_crtc(dev, crtc, encoder)
6187                 if (encoder->pre_pll_enable)
6188                         encoder->pre_pll_enable(encoder);
6189
6190         if (IS_CHERRYVIEW(dev)) {
6191                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6192                 chv_enable_pll(intel_crtc, intel_crtc->config);
6193         } else {
6194                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6195                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6196         }
6197
6198         for_each_encoder_on_crtc(dev, crtc, encoder)
6199                 if (encoder->pre_enable)
6200                         encoder->pre_enable(encoder);
6201
6202         i9xx_pfit_enable(intel_crtc);
6203
6204         intel_color_load_luts(&pipe_config->base);
6205
6206         intel_update_watermarks(crtc);
6207         intel_enable_pipe(intel_crtc);
6208
6209         assert_vblank_disabled(crtc);
6210         drm_crtc_vblank_on(crtc);
6211
6212         for_each_encoder_on_crtc(dev, crtc, encoder)
6213                 encoder->enable(encoder);
6214 }
6215
6216 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6217 {
6218         struct drm_device *dev = crtc->base.dev;
6219         struct drm_i915_private *dev_priv = dev->dev_private;
6220
6221         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6222         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6223 }
6224
6225 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6226 {
6227         struct drm_device *dev = crtc->dev;
6228         struct drm_i915_private *dev_priv = to_i915(dev);
6229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230         struct intel_encoder *encoder;
6231         struct intel_crtc_state *pipe_config =
6232                 to_intel_crtc_state(crtc->state);
6233         enum pipe pipe = intel_crtc->pipe;
6234
6235         if (WARN_ON(intel_crtc->active))
6236                 return;
6237
6238         i9xx_set_pll_dividers(intel_crtc);
6239
6240         if (intel_crtc->config->has_dp_encoder)
6241                 intel_dp_set_m_n(intel_crtc, M1_N1);
6242
6243         intel_set_pipe_timings(intel_crtc);
6244         intel_set_pipe_src_size(intel_crtc);
6245
6246         i9xx_set_pipeconf(intel_crtc);
6247
6248         intel_crtc->active = true;
6249
6250         if (!IS_GEN2(dev))
6251                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6252
6253         for_each_encoder_on_crtc(dev, crtc, encoder)
6254                 if (encoder->pre_enable)
6255                         encoder->pre_enable(encoder);
6256
6257         i9xx_enable_pll(intel_crtc);
6258
6259         i9xx_pfit_enable(intel_crtc);
6260
6261         intel_color_load_luts(&pipe_config->base);
6262
6263         intel_update_watermarks(crtc);
6264         intel_enable_pipe(intel_crtc);
6265
6266         assert_vblank_disabled(crtc);
6267         drm_crtc_vblank_on(crtc);
6268
6269         for_each_encoder_on_crtc(dev, crtc, encoder)
6270                 encoder->enable(encoder);
6271 }
6272
6273 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6274 {
6275         struct drm_device *dev = crtc->base.dev;
6276         struct drm_i915_private *dev_priv = dev->dev_private;
6277
6278         if (!crtc->config->gmch_pfit.control)
6279                 return;
6280
6281         assert_pipe_disabled(dev_priv, crtc->pipe);
6282
6283         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6284                          I915_READ(PFIT_CONTROL));
6285         I915_WRITE(PFIT_CONTROL, 0);
6286 }
6287
6288 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6289 {
6290         struct drm_device *dev = crtc->dev;
6291         struct drm_i915_private *dev_priv = dev->dev_private;
6292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6293         struct intel_encoder *encoder;
6294         int pipe = intel_crtc->pipe;
6295
6296         /*
6297          * On gen2 planes are double buffered but the pipe isn't, so we must
6298          * wait for planes to fully turn off before disabling the pipe.
6299          */
6300         if (IS_GEN2(dev))
6301                 intel_wait_for_vblank(dev, pipe);
6302
6303         for_each_encoder_on_crtc(dev, crtc, encoder)
6304                 encoder->disable(encoder);
6305
6306         drm_crtc_vblank_off(crtc);
6307         assert_vblank_disabled(crtc);
6308
6309         intel_disable_pipe(intel_crtc);
6310
6311         i9xx_pfit_disable(intel_crtc);
6312
6313         for_each_encoder_on_crtc(dev, crtc, encoder)
6314                 if (encoder->post_disable)
6315                         encoder->post_disable(encoder);
6316
6317         if (!intel_crtc->config->has_dsi_encoder) {
6318                 if (IS_CHERRYVIEW(dev))
6319                         chv_disable_pll(dev_priv, pipe);
6320                 else if (IS_VALLEYVIEW(dev))
6321                         vlv_disable_pll(dev_priv, pipe);
6322                 else
6323                         i9xx_disable_pll(intel_crtc);
6324         }
6325
6326         for_each_encoder_on_crtc(dev, crtc, encoder)
6327                 if (encoder->post_pll_disable)
6328                         encoder->post_pll_disable(encoder);
6329
6330         if (!IS_GEN2(dev))
6331                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6332 }
6333
6334 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6335 {
6336         struct intel_encoder *encoder;
6337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6339         enum intel_display_power_domain domain;
6340         unsigned long domains;
6341
6342         if (!intel_crtc->active)
6343                 return;
6344
6345         if (to_intel_plane_state(crtc->primary->state)->visible) {
6346                 WARN_ON(intel_crtc->flip_work);
6347
6348                 intel_pre_disable_primary_noatomic(crtc);
6349
6350                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6351                 to_intel_plane_state(crtc->primary->state)->visible = false;
6352         }
6353
6354         dev_priv->display.crtc_disable(crtc);
6355
6356         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6357                       crtc->base.id, crtc->name);
6358
6359         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6360         crtc->state->active = false;
6361         intel_crtc->active = false;
6362         crtc->enabled = false;
6363         crtc->state->connector_mask = 0;
6364         crtc->state->encoder_mask = 0;
6365
6366         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6367                 encoder->base.crtc = NULL;
6368
6369         intel_fbc_disable(intel_crtc);
6370         intel_update_watermarks(crtc);
6371         intel_disable_shared_dpll(intel_crtc);
6372
6373         domains = intel_crtc->enabled_power_domains;
6374         for_each_power_domain(domain, domains)
6375                 intel_display_power_put(dev_priv, domain);
6376         intel_crtc->enabled_power_domains = 0;
6377
6378         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6379         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6380 }
6381
6382 /*
6383  * turn all crtc's off, but do not adjust state
6384  * This has to be paired with a call to intel_modeset_setup_hw_state.
6385  */
6386 int intel_display_suspend(struct drm_device *dev)
6387 {
6388         struct drm_i915_private *dev_priv = to_i915(dev);
6389         struct drm_atomic_state *state;
6390         int ret;
6391
6392         state = drm_atomic_helper_suspend(dev);
6393         ret = PTR_ERR_OR_ZERO(state);
6394         if (ret)
6395                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6396         else
6397                 dev_priv->modeset_restore_state = state;
6398         return ret;
6399 }
6400
6401 void intel_encoder_destroy(struct drm_encoder *encoder)
6402 {
6403         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6404
6405         drm_encoder_cleanup(encoder);
6406         kfree(intel_encoder);
6407 }
6408
6409 /* Cross check the actual hw state with our own modeset state tracking (and it's
6410  * internal consistency). */
6411 static void intel_connector_verify_state(struct intel_connector *connector)
6412 {
6413         struct drm_crtc *crtc = connector->base.state->crtc;
6414
6415         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6416                       connector->base.base.id,
6417                       connector->base.name);
6418
6419         if (connector->get_hw_state(connector)) {
6420                 struct intel_encoder *encoder = connector->encoder;
6421                 struct drm_connector_state *conn_state = connector->base.state;
6422
6423                 I915_STATE_WARN(!crtc,
6424                          "connector enabled without attached crtc\n");
6425
6426                 if (!crtc)
6427                         return;
6428
6429                 I915_STATE_WARN(!crtc->state->active,
6430                       "connector is active, but attached crtc isn't\n");
6431
6432                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6433                         return;
6434
6435                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6436                         "atomic encoder doesn't match attached encoder\n");
6437
6438                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6439                         "attached encoder crtc differs from connector crtc\n");
6440         } else {
6441                 I915_STATE_WARN(crtc && crtc->state->active,
6442                         "attached crtc is active, but connector isn't\n");
6443                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6444                         "best encoder set without crtc!\n");
6445         }
6446 }
6447
6448 int intel_connector_init(struct intel_connector *connector)
6449 {
6450         drm_atomic_helper_connector_reset(&connector->base);
6451
6452         if (!connector->base.state)
6453                 return -ENOMEM;
6454
6455         return 0;
6456 }
6457
6458 struct intel_connector *intel_connector_alloc(void)
6459 {
6460         struct intel_connector *connector;
6461
6462         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6463         if (!connector)
6464                 return NULL;
6465
6466         if (intel_connector_init(connector) < 0) {
6467                 kfree(connector);
6468                 return NULL;
6469         }
6470
6471         return connector;
6472 }
6473
6474 /* Simple connector->get_hw_state implementation for encoders that support only
6475  * one connector and no cloning and hence the encoder state determines the state
6476  * of the connector. */
6477 bool intel_connector_get_hw_state(struct intel_connector *connector)
6478 {
6479         enum pipe pipe = 0;
6480         struct intel_encoder *encoder = connector->encoder;
6481
6482         return encoder->get_hw_state(encoder, &pipe);
6483 }
6484
6485 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6486 {
6487         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6488                 return crtc_state->fdi_lanes;
6489
6490         return 0;
6491 }
6492
6493 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6494                                      struct intel_crtc_state *pipe_config)
6495 {
6496         struct drm_atomic_state *state = pipe_config->base.state;
6497         struct intel_crtc *other_crtc;
6498         struct intel_crtc_state *other_crtc_state;
6499
6500         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6501                       pipe_name(pipe), pipe_config->fdi_lanes);
6502         if (pipe_config->fdi_lanes > 4) {
6503                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6504                               pipe_name(pipe), pipe_config->fdi_lanes);
6505                 return -EINVAL;
6506         }
6507
6508         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6509                 if (pipe_config->fdi_lanes > 2) {
6510                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6511                                       pipe_config->fdi_lanes);
6512                         return -EINVAL;
6513                 } else {
6514                         return 0;
6515                 }
6516         }
6517
6518         if (INTEL_INFO(dev)->num_pipes == 2)
6519                 return 0;
6520
6521         /* Ivybridge 3 pipe is really complicated */
6522         switch (pipe) {
6523         case PIPE_A:
6524                 return 0;
6525         case PIPE_B:
6526                 if (pipe_config->fdi_lanes <= 2)
6527                         return 0;
6528
6529                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6530                 other_crtc_state =
6531                         intel_atomic_get_crtc_state(state, other_crtc);
6532                 if (IS_ERR(other_crtc_state))
6533                         return PTR_ERR(other_crtc_state);
6534
6535                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6536                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6537                                       pipe_name(pipe), pipe_config->fdi_lanes);
6538                         return -EINVAL;
6539                 }
6540                 return 0;
6541         case PIPE_C:
6542                 if (pipe_config->fdi_lanes > 2) {
6543                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6544                                       pipe_name(pipe), pipe_config->fdi_lanes);
6545                         return -EINVAL;
6546                 }
6547
6548                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6549                 other_crtc_state =
6550                         intel_atomic_get_crtc_state(state, other_crtc);
6551                 if (IS_ERR(other_crtc_state))
6552                         return PTR_ERR(other_crtc_state);
6553
6554                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6555                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6556                         return -EINVAL;
6557                 }
6558                 return 0;
6559         default:
6560                 BUG();
6561         }
6562 }
6563
6564 #define RETRY 1
6565 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6566                                        struct intel_crtc_state *pipe_config)
6567 {
6568         struct drm_device *dev = intel_crtc->base.dev;
6569         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6570         int lane, link_bw, fdi_dotclock, ret;
6571         bool needs_recompute = false;
6572
6573 retry:
6574         /* FDI is a binary signal running at ~2.7GHz, encoding
6575          * each output octet as 10 bits. The actual frequency
6576          * is stored as a divider into a 100MHz clock, and the
6577          * mode pixel clock is stored in units of 1KHz.
6578          * Hence the bw of each lane in terms of the mode signal
6579          * is:
6580          */
6581         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6582
6583         fdi_dotclock = adjusted_mode->crtc_clock;
6584
6585         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6586                                            pipe_config->pipe_bpp);
6587
6588         pipe_config->fdi_lanes = lane;
6589
6590         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6591                                link_bw, &pipe_config->fdi_m_n);
6592
6593         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6594         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6595                 pipe_config->pipe_bpp -= 2*3;
6596                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6597                               pipe_config->pipe_bpp);
6598                 needs_recompute = true;
6599                 pipe_config->bw_constrained = true;
6600
6601                 goto retry;
6602         }
6603
6604         if (needs_recompute)
6605                 return RETRY;
6606
6607         return ret;
6608 }
6609
6610 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6611                                      struct intel_crtc_state *pipe_config)
6612 {
6613         if (pipe_config->pipe_bpp > 24)
6614                 return false;
6615
6616         /* HSW can handle pixel rate up to cdclk? */
6617         if (IS_HASWELL(dev_priv))
6618                 return true;
6619
6620         /*
6621          * We compare against max which means we must take
6622          * the increased cdclk requirement into account when
6623          * calculating the new cdclk.
6624          *
6625          * Should measure whether using a lower cdclk w/o IPS
6626          */
6627         return ilk_pipe_pixel_rate(pipe_config) <=
6628                 dev_priv->max_cdclk_freq * 95 / 100;
6629 }
6630
6631 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6632                                    struct intel_crtc_state *pipe_config)
6633 {
6634         struct drm_device *dev = crtc->base.dev;
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636
6637         pipe_config->ips_enabled = i915.enable_ips &&
6638                 hsw_crtc_supports_ips(crtc) &&
6639                 pipe_config_supports_ips(dev_priv, pipe_config);
6640 }
6641
6642 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6643 {
6644         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6645
6646         /* GDG double wide on either pipe, otherwise pipe A only */
6647         return INTEL_INFO(dev_priv)->gen < 4 &&
6648                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6649 }
6650
6651 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6652                                      struct intel_crtc_state *pipe_config)
6653 {
6654         struct drm_device *dev = crtc->base.dev;
6655         struct drm_i915_private *dev_priv = dev->dev_private;
6656         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6657         int clock_limit = dev_priv->max_dotclk_freq;
6658
6659         if (INTEL_INFO(dev)->gen < 4) {
6660                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6661
6662                 /*
6663                  * Enable double wide mode when the dot clock
6664                  * is > 90% of the (display) core speed.
6665                  */
6666                 if (intel_crtc_supports_double_wide(crtc) &&
6667                     adjusted_mode->crtc_clock > clock_limit) {
6668                         clock_limit = dev_priv->max_dotclk_freq;
6669                         pipe_config->double_wide = true;
6670                 }
6671         }
6672
6673         if (adjusted_mode->crtc_clock > clock_limit) {
6674                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6675                               adjusted_mode->crtc_clock, clock_limit,
6676                               yesno(pipe_config->double_wide));
6677                 return -EINVAL;
6678         }
6679
6680         /*
6681          * Pipe horizontal size must be even in:
6682          * - DVO ganged mode
6683          * - LVDS dual channel mode
6684          * - Double wide pipe
6685          */
6686         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6687              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6688                 pipe_config->pipe_src_w &= ~1;
6689
6690         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6691          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6692          */
6693         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6694                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6695                 return -EINVAL;
6696
6697         if (HAS_IPS(dev))
6698                 hsw_compute_ips_config(crtc, pipe_config);
6699
6700         if (pipe_config->has_pch_encoder)
6701                 return ironlake_fdi_compute_config(crtc, pipe_config);
6702
6703         return 0;
6704 }
6705
6706 static int skylake_get_display_clock_speed(struct drm_device *dev)
6707 {
6708         struct drm_i915_private *dev_priv = to_i915(dev);
6709         uint32_t cdctl;
6710
6711         skl_dpll0_update(dev_priv);
6712
6713         if (dev_priv->cdclk_pll.vco == 0)
6714                 return dev_priv->cdclk_pll.ref;
6715
6716         cdctl = I915_READ(CDCLK_CTL);
6717
6718         if (dev_priv->cdclk_pll.vco == 8640000) {
6719                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6720                 case CDCLK_FREQ_450_432:
6721                         return 432000;
6722                 case CDCLK_FREQ_337_308:
6723                         return 308571;
6724                 case CDCLK_FREQ_540:
6725                         return 540000;
6726                 case CDCLK_FREQ_675_617:
6727                         return 617143;
6728                 default:
6729                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6730                 }
6731         } else {
6732                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6733                 case CDCLK_FREQ_450_432:
6734                         return 450000;
6735                 case CDCLK_FREQ_337_308:
6736                         return 337500;
6737                 case CDCLK_FREQ_540:
6738                         return 540000;
6739                 case CDCLK_FREQ_675_617:
6740                         return 675000;
6741                 default:
6742                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6743                 }
6744         }
6745
6746         return dev_priv->cdclk_pll.ref;
6747 }
6748
6749 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6750 {
6751         u32 val;
6752
6753         dev_priv->cdclk_pll.ref = 19200;
6754         dev_priv->cdclk_pll.vco = 0;
6755
6756         val = I915_READ(BXT_DE_PLL_ENABLE);
6757         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6758                 return;
6759
6760         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6761                 return;
6762
6763         val = I915_READ(BXT_DE_PLL_CTL);
6764         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6765                 dev_priv->cdclk_pll.ref;
6766 }
6767
6768 static int broxton_get_display_clock_speed(struct drm_device *dev)
6769 {
6770         struct drm_i915_private *dev_priv = to_i915(dev);
6771         u32 divider;
6772         int div, vco;
6773
6774         bxt_de_pll_update(dev_priv);
6775
6776         vco = dev_priv->cdclk_pll.vco;
6777         if (vco == 0)
6778                 return dev_priv->cdclk_pll.ref;
6779
6780         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6781
6782         switch (divider) {
6783         case BXT_CDCLK_CD2X_DIV_SEL_1:
6784                 div = 2;
6785                 break;
6786         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6787                 div = 3;
6788                 break;
6789         case BXT_CDCLK_CD2X_DIV_SEL_2:
6790                 div = 4;
6791                 break;
6792         case BXT_CDCLK_CD2X_DIV_SEL_4:
6793                 div = 8;
6794                 break;
6795         default:
6796                 MISSING_CASE(divider);
6797                 return dev_priv->cdclk_pll.ref;
6798         }
6799
6800         return DIV_ROUND_CLOSEST(vco, div);
6801 }
6802
6803 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6804 {
6805         struct drm_i915_private *dev_priv = dev->dev_private;
6806         uint32_t lcpll = I915_READ(LCPLL_CTL);
6807         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6808
6809         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6810                 return 800000;
6811         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6812                 return 450000;
6813         else if (freq == LCPLL_CLK_FREQ_450)
6814                 return 450000;
6815         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6816                 return 540000;
6817         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6818                 return 337500;
6819         else
6820                 return 675000;
6821 }
6822
6823 static int haswell_get_display_clock_speed(struct drm_device *dev)
6824 {
6825         struct drm_i915_private *dev_priv = dev->dev_private;
6826         uint32_t lcpll = I915_READ(LCPLL_CTL);
6827         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6828
6829         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6830                 return 800000;
6831         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6832                 return 450000;
6833         else if (freq == LCPLL_CLK_FREQ_450)
6834                 return 450000;
6835         else if (IS_HSW_ULT(dev))
6836                 return 337500;
6837         else
6838                 return 540000;
6839 }
6840
6841 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6842 {
6843         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6844                                       CCK_DISPLAY_CLOCK_CONTROL);
6845 }
6846
6847 static int ilk_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         return 450000;
6850 }
6851
6852 static int i945_get_display_clock_speed(struct drm_device *dev)
6853 {
6854         return 400000;
6855 }
6856
6857 static int i915_get_display_clock_speed(struct drm_device *dev)
6858 {
6859         return 333333;
6860 }
6861
6862 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6863 {
6864         return 200000;
6865 }
6866
6867 static int pnv_get_display_clock_speed(struct drm_device *dev)
6868 {
6869         u16 gcfgc = 0;
6870
6871         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6872
6873         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6874         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6875                 return 266667;
6876         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6877                 return 333333;
6878         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6879                 return 444444;
6880         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6881                 return 200000;
6882         default:
6883                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6884         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6885                 return 133333;
6886         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6887                 return 166667;
6888         }
6889 }
6890
6891 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6892 {
6893         u16 gcfgc = 0;
6894
6895         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6896
6897         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6898                 return 133333;
6899         else {
6900                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6901                 case GC_DISPLAY_CLOCK_333_MHZ:
6902                         return 333333;
6903                 default:
6904                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6905                         return 190000;
6906                 }
6907         }
6908 }
6909
6910 static int i865_get_display_clock_speed(struct drm_device *dev)
6911 {
6912         return 266667;
6913 }
6914
6915 static int i85x_get_display_clock_speed(struct drm_device *dev)
6916 {
6917         u16 hpllcc = 0;
6918
6919         /*
6920          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6921          * encoding is different :(
6922          * FIXME is this the right way to detect 852GM/852GMV?
6923          */
6924         if (dev->pdev->revision == 0x1)
6925                 return 133333;
6926
6927         pci_bus_read_config_word(dev->pdev->bus,
6928                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6929
6930         /* Assume that the hardware is in the high speed state.  This
6931          * should be the default.
6932          */
6933         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6934         case GC_CLOCK_133_200:
6935         case GC_CLOCK_133_200_2:
6936         case GC_CLOCK_100_200:
6937                 return 200000;
6938         case GC_CLOCK_166_250:
6939                 return 250000;
6940         case GC_CLOCK_100_133:
6941                 return 133333;
6942         case GC_CLOCK_133_266:
6943         case GC_CLOCK_133_266_2:
6944         case GC_CLOCK_166_266:
6945                 return 266667;
6946         }
6947
6948         /* Shouldn't happen */
6949         return 0;
6950 }
6951
6952 static int i830_get_display_clock_speed(struct drm_device *dev)
6953 {
6954         return 133333;
6955 }
6956
6957 static unsigned int intel_hpll_vco(struct drm_device *dev)
6958 {
6959         struct drm_i915_private *dev_priv = dev->dev_private;
6960         static const unsigned int blb_vco[8] = {
6961                 [0] = 3200000,
6962                 [1] = 4000000,
6963                 [2] = 5333333,
6964                 [3] = 4800000,
6965                 [4] = 6400000,
6966         };
6967         static const unsigned int pnv_vco[8] = {
6968                 [0] = 3200000,
6969                 [1] = 4000000,
6970                 [2] = 5333333,
6971                 [3] = 4800000,
6972                 [4] = 2666667,
6973         };
6974         static const unsigned int cl_vco[8] = {
6975                 [0] = 3200000,
6976                 [1] = 4000000,
6977                 [2] = 5333333,
6978                 [3] = 6400000,
6979                 [4] = 3333333,
6980                 [5] = 3566667,
6981                 [6] = 4266667,
6982         };
6983         static const unsigned int elk_vco[8] = {
6984                 [0] = 3200000,
6985                 [1] = 4000000,
6986                 [2] = 5333333,
6987                 [3] = 4800000,
6988         };
6989         static const unsigned int ctg_vco[8] = {
6990                 [0] = 3200000,
6991                 [1] = 4000000,
6992                 [2] = 5333333,
6993                 [3] = 6400000,
6994                 [4] = 2666667,
6995                 [5] = 4266667,
6996         };
6997         const unsigned int *vco_table;
6998         unsigned int vco;
6999         uint8_t tmp = 0;
7000
7001         /* FIXME other chipsets? */
7002         if (IS_GM45(dev))
7003                 vco_table = ctg_vco;
7004         else if (IS_G4X(dev))
7005                 vco_table = elk_vco;
7006         else if (IS_CRESTLINE(dev))
7007                 vco_table = cl_vco;
7008         else if (IS_PINEVIEW(dev))
7009                 vco_table = pnv_vco;
7010         else if (IS_G33(dev))
7011                 vco_table = blb_vco;
7012         else
7013                 return 0;
7014
7015         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7016
7017         vco = vco_table[tmp & 0x7];
7018         if (vco == 0)
7019                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7020         else
7021                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7022
7023         return vco;
7024 }
7025
7026 static int gm45_get_display_clock_speed(struct drm_device *dev)
7027 {
7028         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7029         uint16_t tmp = 0;
7030
7031         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7032
7033         cdclk_sel = (tmp >> 12) & 0x1;
7034
7035         switch (vco) {
7036         case 2666667:
7037         case 4000000:
7038         case 5333333:
7039                 return cdclk_sel ? 333333 : 222222;
7040         case 3200000:
7041                 return cdclk_sel ? 320000 : 228571;
7042         default:
7043                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7044                 return 222222;
7045         }
7046 }
7047
7048 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7049 {
7050         static const uint8_t div_3200[] = { 16, 10,  8 };
7051         static const uint8_t div_4000[] = { 20, 12, 10 };
7052         static const uint8_t div_5333[] = { 24, 16, 14 };
7053         const uint8_t *div_table;
7054         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7055         uint16_t tmp = 0;
7056
7057         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7058
7059         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7060
7061         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7062                 goto fail;
7063
7064         switch (vco) {
7065         case 3200000:
7066                 div_table = div_3200;
7067                 break;
7068         case 4000000:
7069                 div_table = div_4000;
7070                 break;
7071         case 5333333:
7072                 div_table = div_5333;
7073                 break;
7074         default:
7075                 goto fail;
7076         }
7077
7078         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7079
7080 fail:
7081         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7082         return 200000;
7083 }
7084
7085 static int g33_get_display_clock_speed(struct drm_device *dev)
7086 {
7087         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7088         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7089         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7090         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7091         const uint8_t *div_table;
7092         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7093         uint16_t tmp = 0;
7094
7095         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7096
7097         cdclk_sel = (tmp >> 4) & 0x7;
7098
7099         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7100                 goto fail;
7101
7102         switch (vco) {
7103         case 3200000:
7104                 div_table = div_3200;
7105                 break;
7106         case 4000000:
7107                 div_table = div_4000;
7108                 break;
7109         case 4800000:
7110                 div_table = div_4800;
7111                 break;
7112         case 5333333:
7113                 div_table = div_5333;
7114                 break;
7115         default:
7116                 goto fail;
7117         }
7118
7119         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7120
7121 fail:
7122         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7123         return 190476;
7124 }
7125
7126 static void
7127 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7128 {
7129         while (*num > DATA_LINK_M_N_MASK ||
7130                *den > DATA_LINK_M_N_MASK) {
7131                 *num >>= 1;
7132                 *den >>= 1;
7133         }
7134 }
7135
7136 static void compute_m_n(unsigned int m, unsigned int n,
7137                         uint32_t *ret_m, uint32_t *ret_n)
7138 {
7139         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7140         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7141         intel_reduce_m_n_ratio(ret_m, ret_n);
7142 }
7143
7144 void
7145 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7146                        int pixel_clock, int link_clock,
7147                        struct intel_link_m_n *m_n)
7148 {
7149         m_n->tu = 64;
7150
7151         compute_m_n(bits_per_pixel * pixel_clock,
7152                     link_clock * nlanes * 8,
7153                     &m_n->gmch_m, &m_n->gmch_n);
7154
7155         compute_m_n(pixel_clock, link_clock,
7156                     &m_n->link_m, &m_n->link_n);
7157 }
7158
7159 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7160 {
7161         if (i915.panel_use_ssc >= 0)
7162                 return i915.panel_use_ssc != 0;
7163         return dev_priv->vbt.lvds_use_ssc
7164                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7165 }
7166
7167 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7168 {
7169         return (1 << dpll->n) << 16 | dpll->m2;
7170 }
7171
7172 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7173 {
7174         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7175 }
7176
7177 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7178                                      struct intel_crtc_state *crtc_state,
7179                                      struct dpll *reduced_clock)
7180 {
7181         struct drm_device *dev = crtc->base.dev;
7182         u32 fp, fp2 = 0;
7183
7184         if (IS_PINEVIEW(dev)) {
7185                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7186                 if (reduced_clock)
7187                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7188         } else {
7189                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7190                 if (reduced_clock)
7191                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7192         }
7193
7194         crtc_state->dpll_hw_state.fp0 = fp;
7195
7196         crtc->lowfreq_avail = false;
7197         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7198             reduced_clock) {
7199                 crtc_state->dpll_hw_state.fp1 = fp2;
7200                 crtc->lowfreq_avail = true;
7201         } else {
7202                 crtc_state->dpll_hw_state.fp1 = fp;
7203         }
7204 }
7205
7206 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7207                 pipe)
7208 {
7209         u32 reg_val;
7210
7211         /*
7212          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7213          * and set it to a reasonable value instead.
7214          */
7215         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7216         reg_val &= 0xffffff00;
7217         reg_val |= 0x00000030;
7218         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7219
7220         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7221         reg_val &= 0x8cffffff;
7222         reg_val = 0x8c000000;
7223         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7224
7225         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7226         reg_val &= 0xffffff00;
7227         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7228
7229         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7230         reg_val &= 0x00ffffff;
7231         reg_val |= 0xb0000000;
7232         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7233 }
7234
7235 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7236                                          struct intel_link_m_n *m_n)
7237 {
7238         struct drm_device *dev = crtc->base.dev;
7239         struct drm_i915_private *dev_priv = dev->dev_private;
7240         int pipe = crtc->pipe;
7241
7242         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7243         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7244         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7245         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7246 }
7247
7248 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7249                                          struct intel_link_m_n *m_n,
7250                                          struct intel_link_m_n *m2_n2)
7251 {
7252         struct drm_device *dev = crtc->base.dev;
7253         struct drm_i915_private *dev_priv = dev->dev_private;
7254         int pipe = crtc->pipe;
7255         enum transcoder transcoder = crtc->config->cpu_transcoder;
7256
7257         if (INTEL_INFO(dev)->gen >= 5) {
7258                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7259                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7260                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7261                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7262                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7263                  * for gen < 8) and if DRRS is supported (to make sure the
7264                  * registers are not unnecessarily accessed).
7265                  */
7266                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7267                         crtc->config->has_drrs) {
7268                         I915_WRITE(PIPE_DATA_M2(transcoder),
7269                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7270                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7271                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7272                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7273                 }
7274         } else {
7275                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7276                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7277                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7278                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7279         }
7280 }
7281
7282 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7283 {
7284         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7285
7286         if (m_n == M1_N1) {
7287                 dp_m_n = &crtc->config->dp_m_n;
7288                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7289         } else if (m_n == M2_N2) {
7290
7291                 /*
7292                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7293                  * needs to be programmed into M1_N1.
7294                  */
7295                 dp_m_n = &crtc->config->dp_m2_n2;
7296         } else {
7297                 DRM_ERROR("Unsupported divider value\n");
7298                 return;
7299         }
7300
7301         if (crtc->config->has_pch_encoder)
7302                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7303         else
7304                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7305 }
7306
7307 static void vlv_compute_dpll(struct intel_crtc *crtc,
7308                              struct intel_crtc_state *pipe_config)
7309 {
7310         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7311                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7312         if (crtc->pipe != PIPE_A)
7313                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7314
7315         /* DPLL not used with DSI, but still need the rest set up */
7316         if (!pipe_config->has_dsi_encoder)
7317                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7318                         DPLL_EXT_BUFFER_ENABLE_VLV;
7319
7320         pipe_config->dpll_hw_state.dpll_md =
7321                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7322 }
7323
7324 static void chv_compute_dpll(struct intel_crtc *crtc,
7325                              struct intel_crtc_state *pipe_config)
7326 {
7327         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7328                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7329         if (crtc->pipe != PIPE_A)
7330                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7331
7332         /* DPLL not used with DSI, but still need the rest set up */
7333         if (!pipe_config->has_dsi_encoder)
7334                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7335
7336         pipe_config->dpll_hw_state.dpll_md =
7337                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7338 }
7339
7340 static void vlv_prepare_pll(struct intel_crtc *crtc,
7341                             const struct intel_crtc_state *pipe_config)
7342 {
7343         struct drm_device *dev = crtc->base.dev;
7344         struct drm_i915_private *dev_priv = dev->dev_private;
7345         enum pipe pipe = crtc->pipe;
7346         u32 mdiv;
7347         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7348         u32 coreclk, reg_val;
7349
7350         /* Enable Refclk */
7351         I915_WRITE(DPLL(pipe),
7352                    pipe_config->dpll_hw_state.dpll &
7353                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7354
7355         /* No need to actually set up the DPLL with DSI */
7356         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7357                 return;
7358
7359         mutex_lock(&dev_priv->sb_lock);
7360
7361         bestn = pipe_config->dpll.n;
7362         bestm1 = pipe_config->dpll.m1;
7363         bestm2 = pipe_config->dpll.m2;
7364         bestp1 = pipe_config->dpll.p1;
7365         bestp2 = pipe_config->dpll.p2;
7366
7367         /* See eDP HDMI DPIO driver vbios notes doc */
7368
7369         /* PLL B needs special handling */
7370         if (pipe == PIPE_B)
7371                 vlv_pllb_recal_opamp(dev_priv, pipe);
7372
7373         /* Set up Tx target for periodic Rcomp update */
7374         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7375
7376         /* Disable target IRef on PLL */
7377         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7378         reg_val &= 0x00ffffff;
7379         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7380
7381         /* Disable fast lock */
7382         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7383
7384         /* Set idtafcrecal before PLL is enabled */
7385         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7386         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7387         mdiv |= ((bestn << DPIO_N_SHIFT));
7388         mdiv |= (1 << DPIO_K_SHIFT);
7389
7390         /*
7391          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7392          * but we don't support that).
7393          * Note: don't use the DAC post divider as it seems unstable.
7394          */
7395         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7396         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7397
7398         mdiv |= DPIO_ENABLE_CALIBRATION;
7399         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7400
7401         /* Set HBR and RBR LPF coefficients */
7402         if (pipe_config->port_clock == 162000 ||
7403             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7404             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7405                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7406                                  0x009f0003);
7407         else
7408                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7409                                  0x00d0000f);
7410
7411         if (pipe_config->has_dp_encoder) {
7412                 /* Use SSC source */
7413                 if (pipe == PIPE_A)
7414                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7415                                          0x0df40000);
7416                 else
7417                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7418                                          0x0df70000);
7419         } else { /* HDMI or VGA */
7420                 /* Use bend source */
7421                 if (pipe == PIPE_A)
7422                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7423                                          0x0df70000);
7424                 else
7425                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7426                                          0x0df40000);
7427         }
7428
7429         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7430         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7431         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7432             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7433                 coreclk |= 0x01000000;
7434         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7435
7436         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7437         mutex_unlock(&dev_priv->sb_lock);
7438 }
7439
7440 static void chv_prepare_pll(struct intel_crtc *crtc,
7441                             const struct intel_crtc_state *pipe_config)
7442 {
7443         struct drm_device *dev = crtc->base.dev;
7444         struct drm_i915_private *dev_priv = dev->dev_private;
7445         enum pipe pipe = crtc->pipe;
7446         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7447         u32 loopfilter, tribuf_calcntr;
7448         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7449         u32 dpio_val;
7450         int vco;
7451
7452         /* Enable Refclk and SSC */
7453         I915_WRITE(DPLL(pipe),
7454                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7455
7456         /* No need to actually set up the DPLL with DSI */
7457         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7458                 return;
7459
7460         bestn = pipe_config->dpll.n;
7461         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7462         bestm1 = pipe_config->dpll.m1;
7463         bestm2 = pipe_config->dpll.m2 >> 22;
7464         bestp1 = pipe_config->dpll.p1;
7465         bestp2 = pipe_config->dpll.p2;
7466         vco = pipe_config->dpll.vco;
7467         dpio_val = 0;
7468         loopfilter = 0;
7469
7470         mutex_lock(&dev_priv->sb_lock);
7471
7472         /* p1 and p2 divider */
7473         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7474                         5 << DPIO_CHV_S1_DIV_SHIFT |
7475                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7476                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7477                         1 << DPIO_CHV_K_DIV_SHIFT);
7478
7479         /* Feedback post-divider - m2 */
7480         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7481
7482         /* Feedback refclk divider - n and m1 */
7483         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7484                         DPIO_CHV_M1_DIV_BY_2 |
7485                         1 << DPIO_CHV_N_DIV_SHIFT);
7486
7487         /* M2 fraction division */
7488         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7489
7490         /* M2 fraction division enable */
7491         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7492         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7493         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7494         if (bestm2_frac)
7495                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7496         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7497
7498         /* Program digital lock detect threshold */
7499         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7500         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7501                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7502         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7503         if (!bestm2_frac)
7504                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7505         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7506
7507         /* Loop filter */
7508         if (vco == 5400000) {
7509                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7510                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7511                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7512                 tribuf_calcntr = 0x9;
7513         } else if (vco <= 6200000) {
7514                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7515                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7516                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7517                 tribuf_calcntr = 0x9;
7518         } else if (vco <= 6480000) {
7519                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7520                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7521                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7522                 tribuf_calcntr = 0x8;
7523         } else {
7524                 /* Not supported. Apply the same limits as in the max case */
7525                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7526                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7527                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7528                 tribuf_calcntr = 0;
7529         }
7530         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7531
7532         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7533         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7534         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7535         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7536
7537         /* AFC Recal */
7538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7539                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7540                         DPIO_AFC_RECAL);
7541
7542         mutex_unlock(&dev_priv->sb_lock);
7543 }
7544
7545 /**
7546  * vlv_force_pll_on - forcibly enable just the PLL
7547  * @dev_priv: i915 private structure
7548  * @pipe: pipe PLL to enable
7549  * @dpll: PLL configuration
7550  *
7551  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7552  * in cases where we need the PLL enabled even when @pipe is not going to
7553  * be enabled.
7554  */
7555 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7556                      const struct dpll *dpll)
7557 {
7558         struct intel_crtc *crtc =
7559                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7560         struct intel_crtc_state *pipe_config;
7561
7562         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7563         if (!pipe_config)
7564                 return -ENOMEM;
7565
7566         pipe_config->base.crtc = &crtc->base;
7567         pipe_config->pixel_multiplier = 1;
7568         pipe_config->dpll = *dpll;
7569
7570         if (IS_CHERRYVIEW(dev)) {
7571                 chv_compute_dpll(crtc, pipe_config);
7572                 chv_prepare_pll(crtc, pipe_config);
7573                 chv_enable_pll(crtc, pipe_config);
7574         } else {
7575                 vlv_compute_dpll(crtc, pipe_config);
7576                 vlv_prepare_pll(crtc, pipe_config);
7577                 vlv_enable_pll(crtc, pipe_config);
7578         }
7579
7580         kfree(pipe_config);
7581
7582         return 0;
7583 }
7584
7585 /**
7586  * vlv_force_pll_off - forcibly disable just the PLL
7587  * @dev_priv: i915 private structure
7588  * @pipe: pipe PLL to disable
7589  *
7590  * Disable the PLL for @pipe. To be used in cases where we need
7591  * the PLL enabled even when @pipe is not going to be enabled.
7592  */
7593 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7594 {
7595         if (IS_CHERRYVIEW(dev))
7596                 chv_disable_pll(to_i915(dev), pipe);
7597         else
7598                 vlv_disable_pll(to_i915(dev), pipe);
7599 }
7600
7601 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7602                               struct intel_crtc_state *crtc_state,
7603                               struct dpll *reduced_clock)
7604 {
7605         struct drm_device *dev = crtc->base.dev;
7606         struct drm_i915_private *dev_priv = dev->dev_private;
7607         u32 dpll;
7608         bool is_sdvo;
7609         struct dpll *clock = &crtc_state->dpll;
7610
7611         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7612
7613         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7614                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7615
7616         dpll = DPLL_VGA_MODE_DIS;
7617
7618         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7619                 dpll |= DPLLB_MODE_LVDS;
7620         else
7621                 dpll |= DPLLB_MODE_DAC_SERIAL;
7622
7623         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7624                 dpll |= (crtc_state->pixel_multiplier - 1)
7625                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7626         }
7627
7628         if (is_sdvo)
7629                 dpll |= DPLL_SDVO_HIGH_SPEED;
7630
7631         if (crtc_state->has_dp_encoder)
7632                 dpll |= DPLL_SDVO_HIGH_SPEED;
7633
7634         /* compute bitmask from p1 value */
7635         if (IS_PINEVIEW(dev))
7636                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7637         else {
7638                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7639                 if (IS_G4X(dev) && reduced_clock)
7640                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7641         }
7642         switch (clock->p2) {
7643         case 5:
7644                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7645                 break;
7646         case 7:
7647                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7648                 break;
7649         case 10:
7650                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7651                 break;
7652         case 14:
7653                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7654                 break;
7655         }
7656         if (INTEL_INFO(dev)->gen >= 4)
7657                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7658
7659         if (crtc_state->sdvo_tv_clock)
7660                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7661         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7662                  intel_panel_use_ssc(dev_priv))
7663                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7664         else
7665                 dpll |= PLL_REF_INPUT_DREFCLK;
7666
7667         dpll |= DPLL_VCO_ENABLE;
7668         crtc_state->dpll_hw_state.dpll = dpll;
7669
7670         if (INTEL_INFO(dev)->gen >= 4) {
7671                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7672                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7673                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7674         }
7675 }
7676
7677 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7678                               struct intel_crtc_state *crtc_state,
7679                               struct dpll *reduced_clock)
7680 {
7681         struct drm_device *dev = crtc->base.dev;
7682         struct drm_i915_private *dev_priv = dev->dev_private;
7683         u32 dpll;
7684         struct dpll *clock = &crtc_state->dpll;
7685
7686         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7687
7688         dpll = DPLL_VGA_MODE_DIS;
7689
7690         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7691                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7692         } else {
7693                 if (clock->p1 == 2)
7694                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7695                 else
7696                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7697                 if (clock->p2 == 4)
7698                         dpll |= PLL_P2_DIVIDE_BY_4;
7699         }
7700
7701         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7702                 dpll |= DPLL_DVO_2X_MODE;
7703
7704         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7705             intel_panel_use_ssc(dev_priv))
7706                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7707         else
7708                 dpll |= PLL_REF_INPUT_DREFCLK;
7709
7710         dpll |= DPLL_VCO_ENABLE;
7711         crtc_state->dpll_hw_state.dpll = dpll;
7712 }
7713
7714 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7715 {
7716         struct drm_device *dev = intel_crtc->base.dev;
7717         struct drm_i915_private *dev_priv = dev->dev_private;
7718         enum pipe pipe = intel_crtc->pipe;
7719         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7720         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7721         uint32_t crtc_vtotal, crtc_vblank_end;
7722         int vsyncshift = 0;
7723
7724         /* We need to be careful not to changed the adjusted mode, for otherwise
7725          * the hw state checker will get angry at the mismatch. */
7726         crtc_vtotal = adjusted_mode->crtc_vtotal;
7727         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7728
7729         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7730                 /* the chip adds 2 halflines automatically */
7731                 crtc_vtotal -= 1;
7732                 crtc_vblank_end -= 1;
7733
7734                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7735                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7736                 else
7737                         vsyncshift = adjusted_mode->crtc_hsync_start -
7738                                 adjusted_mode->crtc_htotal / 2;
7739                 if (vsyncshift < 0)
7740                         vsyncshift += adjusted_mode->crtc_htotal;
7741         }
7742
7743         if (INTEL_INFO(dev)->gen > 3)
7744                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7745
7746         I915_WRITE(HTOTAL(cpu_transcoder),
7747                    (adjusted_mode->crtc_hdisplay - 1) |
7748                    ((adjusted_mode->crtc_htotal - 1) << 16));
7749         I915_WRITE(HBLANK(cpu_transcoder),
7750                    (adjusted_mode->crtc_hblank_start - 1) |
7751                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7752         I915_WRITE(HSYNC(cpu_transcoder),
7753                    (adjusted_mode->crtc_hsync_start - 1) |
7754                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7755
7756         I915_WRITE(VTOTAL(cpu_transcoder),
7757                    (adjusted_mode->crtc_vdisplay - 1) |
7758                    ((crtc_vtotal - 1) << 16));
7759         I915_WRITE(VBLANK(cpu_transcoder),
7760                    (adjusted_mode->crtc_vblank_start - 1) |
7761                    ((crtc_vblank_end - 1) << 16));
7762         I915_WRITE(VSYNC(cpu_transcoder),
7763                    (adjusted_mode->crtc_vsync_start - 1) |
7764                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7765
7766         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7767          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7768          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7769          * bits. */
7770         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7771             (pipe == PIPE_B || pipe == PIPE_C))
7772                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7773
7774 }
7775
7776 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7777 {
7778         struct drm_device *dev = intel_crtc->base.dev;
7779         struct drm_i915_private *dev_priv = dev->dev_private;
7780         enum pipe pipe = intel_crtc->pipe;
7781
7782         /* pipesrc controls the size that is scaled from, which should
7783          * always be the user's requested size.
7784          */
7785         I915_WRITE(PIPESRC(pipe),
7786                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7787                    (intel_crtc->config->pipe_src_h - 1));
7788 }
7789
7790 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7791                                    struct intel_crtc_state *pipe_config)
7792 {
7793         struct drm_device *dev = crtc->base.dev;
7794         struct drm_i915_private *dev_priv = dev->dev_private;
7795         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7796         uint32_t tmp;
7797
7798         tmp = I915_READ(HTOTAL(cpu_transcoder));
7799         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7800         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7801         tmp = I915_READ(HBLANK(cpu_transcoder));
7802         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7803         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7804         tmp = I915_READ(HSYNC(cpu_transcoder));
7805         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7806         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7807
7808         tmp = I915_READ(VTOTAL(cpu_transcoder));
7809         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7810         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7811         tmp = I915_READ(VBLANK(cpu_transcoder));
7812         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7813         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7814         tmp = I915_READ(VSYNC(cpu_transcoder));
7815         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7816         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7817
7818         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7819                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7820                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7821                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7822         }
7823 }
7824
7825 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7826                                     struct intel_crtc_state *pipe_config)
7827 {
7828         struct drm_device *dev = crtc->base.dev;
7829         struct drm_i915_private *dev_priv = dev->dev_private;
7830         u32 tmp;
7831
7832         tmp = I915_READ(PIPESRC(crtc->pipe));
7833         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7834         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7835
7836         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7837         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7838 }
7839
7840 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7841                                  struct intel_crtc_state *pipe_config)
7842 {
7843         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7844         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7845         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7846         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7847
7848         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7849         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7850         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7851         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7852
7853         mode->flags = pipe_config->base.adjusted_mode.flags;
7854         mode->type = DRM_MODE_TYPE_DRIVER;
7855
7856         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7857         mode->flags |= pipe_config->base.adjusted_mode.flags;
7858
7859         mode->hsync = drm_mode_hsync(mode);
7860         mode->vrefresh = drm_mode_vrefresh(mode);
7861         drm_mode_set_name(mode);
7862 }
7863
7864 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7865 {
7866         struct drm_device *dev = intel_crtc->base.dev;
7867         struct drm_i915_private *dev_priv = dev->dev_private;
7868         uint32_t pipeconf;
7869
7870         pipeconf = 0;
7871
7872         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7873             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7874                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7875
7876         if (intel_crtc->config->double_wide)
7877                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7878
7879         /* only g4x and later have fancy bpc/dither controls */
7880         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7881                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7882                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7883                         pipeconf |= PIPECONF_DITHER_EN |
7884                                     PIPECONF_DITHER_TYPE_SP;
7885
7886                 switch (intel_crtc->config->pipe_bpp) {
7887                 case 18:
7888                         pipeconf |= PIPECONF_6BPC;
7889                         break;
7890                 case 24:
7891                         pipeconf |= PIPECONF_8BPC;
7892                         break;
7893                 case 30:
7894                         pipeconf |= PIPECONF_10BPC;
7895                         break;
7896                 default:
7897                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7898                         BUG();
7899                 }
7900         }
7901
7902         if (HAS_PIPE_CXSR(dev)) {
7903                 if (intel_crtc->lowfreq_avail) {
7904                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7905                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7906                 } else {
7907                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7908                 }
7909         }
7910
7911         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7912                 if (INTEL_INFO(dev)->gen < 4 ||
7913                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7914                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7915                 else
7916                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7917         } else
7918                 pipeconf |= PIPECONF_PROGRESSIVE;
7919
7920         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7921              intel_crtc->config->limited_color_range)
7922                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7923
7924         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7925         POSTING_READ(PIPECONF(intel_crtc->pipe));
7926 }
7927
7928 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7929                                    struct intel_crtc_state *crtc_state)
7930 {
7931         struct drm_device *dev = crtc->base.dev;
7932         struct drm_i915_private *dev_priv = dev->dev_private;
7933         const struct intel_limit *limit;
7934         int refclk = 48000;
7935
7936         memset(&crtc_state->dpll_hw_state, 0,
7937                sizeof(crtc_state->dpll_hw_state));
7938
7939         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7940                 if (intel_panel_use_ssc(dev_priv)) {
7941                         refclk = dev_priv->vbt.lvds_ssc_freq;
7942                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7943                 }
7944
7945                 limit = &intel_limits_i8xx_lvds;
7946         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7947                 limit = &intel_limits_i8xx_dvo;
7948         } else {
7949                 limit = &intel_limits_i8xx_dac;
7950         }
7951
7952         if (!crtc_state->clock_set &&
7953             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7954                                  refclk, NULL, &crtc_state->dpll)) {
7955                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7956                 return -EINVAL;
7957         }
7958
7959         i8xx_compute_dpll(crtc, crtc_state, NULL);
7960
7961         return 0;
7962 }
7963
7964 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7965                                   struct intel_crtc_state *crtc_state)
7966 {
7967         struct drm_device *dev = crtc->base.dev;
7968         struct drm_i915_private *dev_priv = dev->dev_private;
7969         const struct intel_limit *limit;
7970         int refclk = 96000;
7971
7972         memset(&crtc_state->dpll_hw_state, 0,
7973                sizeof(crtc_state->dpll_hw_state));
7974
7975         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7976                 if (intel_panel_use_ssc(dev_priv)) {
7977                         refclk = dev_priv->vbt.lvds_ssc_freq;
7978                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7979                 }
7980
7981                 if (intel_is_dual_link_lvds(dev))
7982                         limit = &intel_limits_g4x_dual_channel_lvds;
7983                 else
7984                         limit = &intel_limits_g4x_single_channel_lvds;
7985         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7986                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7987                 limit = &intel_limits_g4x_hdmi;
7988         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7989                 limit = &intel_limits_g4x_sdvo;
7990         } else {
7991                 /* The option is for other outputs */
7992                 limit = &intel_limits_i9xx_sdvo;
7993         }
7994
7995         if (!crtc_state->clock_set &&
7996             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7997                                 refclk, NULL, &crtc_state->dpll)) {
7998                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7999                 return -EINVAL;
8000         }
8001
8002         i9xx_compute_dpll(crtc, crtc_state, NULL);
8003
8004         return 0;
8005 }
8006
8007 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8008                                   struct intel_crtc_state *crtc_state)
8009 {
8010         struct drm_device *dev = crtc->base.dev;
8011         struct drm_i915_private *dev_priv = dev->dev_private;
8012         const struct intel_limit *limit;
8013         int refclk = 96000;
8014
8015         memset(&crtc_state->dpll_hw_state, 0,
8016                sizeof(crtc_state->dpll_hw_state));
8017
8018         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8019                 if (intel_panel_use_ssc(dev_priv)) {
8020                         refclk = dev_priv->vbt.lvds_ssc_freq;
8021                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8022                 }
8023
8024                 limit = &intel_limits_pineview_lvds;
8025         } else {
8026                 limit = &intel_limits_pineview_sdvo;
8027         }
8028
8029         if (!crtc_state->clock_set &&
8030             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8031                                 refclk, NULL, &crtc_state->dpll)) {
8032                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8033                 return -EINVAL;
8034         }
8035
8036         i9xx_compute_dpll(crtc, crtc_state, NULL);
8037
8038         return 0;
8039 }
8040
8041 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8042                                    struct intel_crtc_state *crtc_state)
8043 {
8044         struct drm_device *dev = crtc->base.dev;
8045         struct drm_i915_private *dev_priv = dev->dev_private;
8046         const struct intel_limit *limit;
8047         int refclk = 96000;
8048
8049         memset(&crtc_state->dpll_hw_state, 0,
8050                sizeof(crtc_state->dpll_hw_state));
8051
8052         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8053                 if (intel_panel_use_ssc(dev_priv)) {
8054                         refclk = dev_priv->vbt.lvds_ssc_freq;
8055                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8056                 }
8057
8058                 limit = &intel_limits_i9xx_lvds;
8059         } else {
8060                 limit = &intel_limits_i9xx_sdvo;
8061         }
8062
8063         if (!crtc_state->clock_set &&
8064             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8065                                  refclk, NULL, &crtc_state->dpll)) {
8066                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8067                 return -EINVAL;
8068         }
8069
8070         i9xx_compute_dpll(crtc, crtc_state, NULL);
8071
8072         return 0;
8073 }
8074
8075 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8076                                   struct intel_crtc_state *crtc_state)
8077 {
8078         int refclk = 100000;
8079         const struct intel_limit *limit = &intel_limits_chv;
8080
8081         memset(&crtc_state->dpll_hw_state, 0,
8082                sizeof(crtc_state->dpll_hw_state));
8083
8084         if (!crtc_state->clock_set &&
8085             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8086                                 refclk, NULL, &crtc_state->dpll)) {
8087                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8088                 return -EINVAL;
8089         }
8090
8091         chv_compute_dpll(crtc, crtc_state);
8092
8093         return 0;
8094 }
8095
8096 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8097                                   struct intel_crtc_state *crtc_state)
8098 {
8099         int refclk = 100000;
8100         const struct intel_limit *limit = &intel_limits_vlv;
8101
8102         memset(&crtc_state->dpll_hw_state, 0,
8103                sizeof(crtc_state->dpll_hw_state));
8104
8105         if (!crtc_state->clock_set &&
8106             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8107                                 refclk, NULL, &crtc_state->dpll)) {
8108                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8109                 return -EINVAL;
8110         }
8111
8112         vlv_compute_dpll(crtc, crtc_state);
8113
8114         return 0;
8115 }
8116
8117 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8118                                  struct intel_crtc_state *pipe_config)
8119 {
8120         struct drm_device *dev = crtc->base.dev;
8121         struct drm_i915_private *dev_priv = dev->dev_private;
8122         uint32_t tmp;
8123
8124         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8125                 return;
8126
8127         tmp = I915_READ(PFIT_CONTROL);
8128         if (!(tmp & PFIT_ENABLE))
8129                 return;
8130
8131         /* Check whether the pfit is attached to our pipe. */
8132         if (INTEL_INFO(dev)->gen < 4) {
8133                 if (crtc->pipe != PIPE_B)
8134                         return;
8135         } else {
8136                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8137                         return;
8138         }
8139
8140         pipe_config->gmch_pfit.control = tmp;
8141         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8142 }
8143
8144 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8145                                struct intel_crtc_state *pipe_config)
8146 {
8147         struct drm_device *dev = crtc->base.dev;
8148         struct drm_i915_private *dev_priv = dev->dev_private;
8149         int pipe = pipe_config->cpu_transcoder;
8150         struct dpll clock;
8151         u32 mdiv;
8152         int refclk = 100000;
8153
8154         /* In case of DSI, DPLL will not be used */
8155         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8156                 return;
8157
8158         mutex_lock(&dev_priv->sb_lock);
8159         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8160         mutex_unlock(&dev_priv->sb_lock);
8161
8162         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8163         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8164         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8165         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8166         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8167
8168         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8169 }
8170
8171 static void
8172 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8173                               struct intel_initial_plane_config *plane_config)
8174 {
8175         struct drm_device *dev = crtc->base.dev;
8176         struct drm_i915_private *dev_priv = dev->dev_private;
8177         u32 val, base, offset;
8178         int pipe = crtc->pipe, plane = crtc->plane;
8179         int fourcc, pixel_format;
8180         unsigned int aligned_height;
8181         struct drm_framebuffer *fb;
8182         struct intel_framebuffer *intel_fb;
8183
8184         val = I915_READ(DSPCNTR(plane));
8185         if (!(val & DISPLAY_PLANE_ENABLE))
8186                 return;
8187
8188         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8189         if (!intel_fb) {
8190                 DRM_DEBUG_KMS("failed to alloc fb\n");
8191                 return;
8192         }
8193
8194         fb = &intel_fb->base;
8195
8196         if (INTEL_INFO(dev)->gen >= 4) {
8197                 if (val & DISPPLANE_TILED) {
8198                         plane_config->tiling = I915_TILING_X;
8199                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8200                 }
8201         }
8202
8203         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8204         fourcc = i9xx_format_to_fourcc(pixel_format);
8205         fb->pixel_format = fourcc;
8206         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8207
8208         if (INTEL_INFO(dev)->gen >= 4) {
8209                 if (plane_config->tiling)
8210                         offset = I915_READ(DSPTILEOFF(plane));
8211                 else
8212                         offset = I915_READ(DSPLINOFF(plane));
8213                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8214         } else {
8215                 base = I915_READ(DSPADDR(plane));
8216         }
8217         plane_config->base = base;
8218
8219         val = I915_READ(PIPESRC(pipe));
8220         fb->width = ((val >> 16) & 0xfff) + 1;
8221         fb->height = ((val >> 0) & 0xfff) + 1;
8222
8223         val = I915_READ(DSPSTRIDE(pipe));
8224         fb->pitches[0] = val & 0xffffffc0;
8225
8226         aligned_height = intel_fb_align_height(dev, fb->height,
8227                                                fb->pixel_format,
8228                                                fb->modifier[0]);
8229
8230         plane_config->size = fb->pitches[0] * aligned_height;
8231
8232         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8233                       pipe_name(pipe), plane, fb->width, fb->height,
8234                       fb->bits_per_pixel, base, fb->pitches[0],
8235                       plane_config->size);
8236
8237         plane_config->fb = intel_fb;
8238 }
8239
8240 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8241                                struct intel_crtc_state *pipe_config)
8242 {
8243         struct drm_device *dev = crtc->base.dev;
8244         struct drm_i915_private *dev_priv = dev->dev_private;
8245         int pipe = pipe_config->cpu_transcoder;
8246         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8247         struct dpll clock;
8248         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8249         int refclk = 100000;
8250
8251         /* In case of DSI, DPLL will not be used */
8252         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8253                 return;
8254
8255         mutex_lock(&dev_priv->sb_lock);
8256         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8257         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8258         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8259         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8260         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8261         mutex_unlock(&dev_priv->sb_lock);
8262
8263         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8264         clock.m2 = (pll_dw0 & 0xff) << 22;
8265         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8266                 clock.m2 |= pll_dw2 & 0x3fffff;
8267         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8268         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8269         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8270
8271         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8272 }
8273
8274 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8275                                  struct intel_crtc_state *pipe_config)
8276 {
8277         struct drm_device *dev = crtc->base.dev;
8278         struct drm_i915_private *dev_priv = dev->dev_private;
8279         enum intel_display_power_domain power_domain;
8280         uint32_t tmp;
8281         bool ret;
8282
8283         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8284         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8285                 return false;
8286
8287         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8288         pipe_config->shared_dpll = NULL;
8289
8290         ret = false;
8291
8292         tmp = I915_READ(PIPECONF(crtc->pipe));
8293         if (!(tmp & PIPECONF_ENABLE))
8294                 goto out;
8295
8296         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8297                 switch (tmp & PIPECONF_BPC_MASK) {
8298                 case PIPECONF_6BPC:
8299                         pipe_config->pipe_bpp = 18;
8300                         break;
8301                 case PIPECONF_8BPC:
8302                         pipe_config->pipe_bpp = 24;
8303                         break;
8304                 case PIPECONF_10BPC:
8305                         pipe_config->pipe_bpp = 30;
8306                         break;
8307                 default:
8308                         break;
8309                 }
8310         }
8311
8312         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8313             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8314                 pipe_config->limited_color_range = true;
8315
8316         if (INTEL_INFO(dev)->gen < 4)
8317                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8318
8319         intel_get_pipe_timings(crtc, pipe_config);
8320         intel_get_pipe_src_size(crtc, pipe_config);
8321
8322         i9xx_get_pfit_config(crtc, pipe_config);
8323
8324         if (INTEL_INFO(dev)->gen >= 4) {
8325                 /* No way to read it out on pipes B and C */
8326                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8327                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8328                 else
8329                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8330                 pipe_config->pixel_multiplier =
8331                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8332                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8333                 pipe_config->dpll_hw_state.dpll_md = tmp;
8334         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8335                 tmp = I915_READ(DPLL(crtc->pipe));
8336                 pipe_config->pixel_multiplier =
8337                         ((tmp & SDVO_MULTIPLIER_MASK)
8338                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8339         } else {
8340                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8341                  * port and will be fixed up in the encoder->get_config
8342                  * function. */
8343                 pipe_config->pixel_multiplier = 1;
8344         }
8345         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8346         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8347                 /*
8348                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8349                  * on 830. Filter it out here so that we don't
8350                  * report errors due to that.
8351                  */
8352                 if (IS_I830(dev))
8353                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8354
8355                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8356                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8357         } else {
8358                 /* Mask out read-only status bits. */
8359                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8360                                                      DPLL_PORTC_READY_MASK |
8361                                                      DPLL_PORTB_READY_MASK);
8362         }
8363
8364         if (IS_CHERRYVIEW(dev))
8365                 chv_crtc_clock_get(crtc, pipe_config);
8366         else if (IS_VALLEYVIEW(dev))
8367                 vlv_crtc_clock_get(crtc, pipe_config);
8368         else
8369                 i9xx_crtc_clock_get(crtc, pipe_config);
8370
8371         /*
8372          * Normally the dotclock is filled in by the encoder .get_config()
8373          * but in case the pipe is enabled w/o any ports we need a sane
8374          * default.
8375          */
8376         pipe_config->base.adjusted_mode.crtc_clock =
8377                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8378
8379         ret = true;
8380
8381 out:
8382         intel_display_power_put(dev_priv, power_domain);
8383
8384         return ret;
8385 }
8386
8387 static void ironlake_init_pch_refclk(struct drm_device *dev)
8388 {
8389         struct drm_i915_private *dev_priv = dev->dev_private;
8390         struct intel_encoder *encoder;
8391         int i;
8392         u32 val, final;
8393         bool has_lvds = false;
8394         bool has_cpu_edp = false;
8395         bool has_panel = false;
8396         bool has_ck505 = false;
8397         bool can_ssc = false;
8398         bool using_ssc_source = false;
8399
8400         /* We need to take the global config into account */
8401         for_each_intel_encoder(dev, encoder) {
8402                 switch (encoder->type) {
8403                 case INTEL_OUTPUT_LVDS:
8404                         has_panel = true;
8405                         has_lvds = true;
8406                         break;
8407                 case INTEL_OUTPUT_EDP:
8408                         has_panel = true;
8409                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8410                                 has_cpu_edp = true;
8411                         break;
8412                 default:
8413                         break;
8414                 }
8415         }
8416
8417         if (HAS_PCH_IBX(dev)) {
8418                 has_ck505 = dev_priv->vbt.display_clock_mode;
8419                 can_ssc = has_ck505;
8420         } else {
8421                 has_ck505 = false;
8422                 can_ssc = true;
8423         }
8424
8425         /* Check if any DPLLs are using the SSC source */
8426         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8427                 u32 temp = I915_READ(PCH_DPLL(i));
8428
8429                 if (!(temp & DPLL_VCO_ENABLE))
8430                         continue;
8431
8432                 if ((temp & PLL_REF_INPUT_MASK) ==
8433                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8434                         using_ssc_source = true;
8435                         break;
8436                 }
8437         }
8438
8439         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8440                       has_panel, has_lvds, has_ck505, using_ssc_source);
8441
8442         /* Ironlake: try to setup display ref clock before DPLL
8443          * enabling. This is only under driver's control after
8444          * PCH B stepping, previous chipset stepping should be
8445          * ignoring this setting.
8446          */
8447         val = I915_READ(PCH_DREF_CONTROL);
8448
8449         /* As we must carefully and slowly disable/enable each source in turn,
8450          * compute the final state we want first and check if we need to
8451          * make any changes at all.
8452          */
8453         final = val;
8454         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8455         if (has_ck505)
8456                 final |= DREF_NONSPREAD_CK505_ENABLE;
8457         else
8458                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8459
8460         final &= ~DREF_SSC_SOURCE_MASK;
8461         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8462         final &= ~DREF_SSC1_ENABLE;
8463
8464         if (has_panel) {
8465                 final |= DREF_SSC_SOURCE_ENABLE;
8466
8467                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8468                         final |= DREF_SSC1_ENABLE;
8469
8470                 if (has_cpu_edp) {
8471                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8472                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8473                         else
8474                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8475                 } else
8476                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8477         } else if (using_ssc_source) {
8478                 final |= DREF_SSC_SOURCE_ENABLE;
8479                 final |= DREF_SSC1_ENABLE;
8480         }
8481
8482         if (final == val)
8483                 return;
8484
8485         /* Always enable nonspread source */
8486         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8487
8488         if (has_ck505)
8489                 val |= DREF_NONSPREAD_CK505_ENABLE;
8490         else
8491                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8492
8493         if (has_panel) {
8494                 val &= ~DREF_SSC_SOURCE_MASK;
8495                 val |= DREF_SSC_SOURCE_ENABLE;
8496
8497                 /* SSC must be turned on before enabling the CPU output  */
8498                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8499                         DRM_DEBUG_KMS("Using SSC on panel\n");
8500                         val |= DREF_SSC1_ENABLE;
8501                 } else
8502                         val &= ~DREF_SSC1_ENABLE;
8503
8504                 /* Get SSC going before enabling the outputs */
8505                 I915_WRITE(PCH_DREF_CONTROL, val);
8506                 POSTING_READ(PCH_DREF_CONTROL);
8507                 udelay(200);
8508
8509                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8510
8511                 /* Enable CPU source on CPU attached eDP */
8512                 if (has_cpu_edp) {
8513                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8514                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8515                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8516                         } else
8517                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8518                 } else
8519                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8520
8521                 I915_WRITE(PCH_DREF_CONTROL, val);
8522                 POSTING_READ(PCH_DREF_CONTROL);
8523                 udelay(200);
8524         } else {
8525                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8526
8527                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8528
8529                 /* Turn off CPU output */
8530                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8531
8532                 I915_WRITE(PCH_DREF_CONTROL, val);
8533                 POSTING_READ(PCH_DREF_CONTROL);
8534                 udelay(200);
8535
8536                 if (!using_ssc_source) {
8537                         DRM_DEBUG_KMS("Disabling SSC source\n");
8538
8539                         /* Turn off the SSC source */
8540                         val &= ~DREF_SSC_SOURCE_MASK;
8541                         val |= DREF_SSC_SOURCE_DISABLE;
8542
8543                         /* Turn off SSC1 */
8544                         val &= ~DREF_SSC1_ENABLE;
8545
8546                         I915_WRITE(PCH_DREF_CONTROL, val);
8547                         POSTING_READ(PCH_DREF_CONTROL);
8548                         udelay(200);
8549                 }
8550         }
8551
8552         BUG_ON(val != final);
8553 }
8554
8555 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8556 {
8557         uint32_t tmp;
8558
8559         tmp = I915_READ(SOUTH_CHICKEN2);
8560         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8561         I915_WRITE(SOUTH_CHICKEN2, tmp);
8562
8563         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8564                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8565                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8566
8567         tmp = I915_READ(SOUTH_CHICKEN2);
8568         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8569         I915_WRITE(SOUTH_CHICKEN2, tmp);
8570
8571         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8572                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8573                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8574 }
8575
8576 /* WaMPhyProgramming:hsw */
8577 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8578 {
8579         uint32_t tmp;
8580
8581         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8582         tmp &= ~(0xFF << 24);
8583         tmp |= (0x12 << 24);
8584         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8585
8586         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8587         tmp |= (1 << 11);
8588         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8589
8590         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8591         tmp |= (1 << 11);
8592         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8593
8594         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8595         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8596         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8597
8598         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8599         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8600         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8601
8602         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8603         tmp &= ~(7 << 13);
8604         tmp |= (5 << 13);
8605         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8606
8607         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8608         tmp &= ~(7 << 13);
8609         tmp |= (5 << 13);
8610         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8611
8612         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8613         tmp &= ~0xFF;
8614         tmp |= 0x1C;
8615         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8616
8617         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8618         tmp &= ~0xFF;
8619         tmp |= 0x1C;
8620         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8621
8622         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8623         tmp &= ~(0xFF << 16);
8624         tmp |= (0x1C << 16);
8625         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8626
8627         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8628         tmp &= ~(0xFF << 16);
8629         tmp |= (0x1C << 16);
8630         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8631
8632         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8633         tmp |= (1 << 27);
8634         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8635
8636         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8637         tmp |= (1 << 27);
8638         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8639
8640         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8641         tmp &= ~(0xF << 28);
8642         tmp |= (4 << 28);
8643         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8644
8645         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8646         tmp &= ~(0xF << 28);
8647         tmp |= (4 << 28);
8648         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8649 }
8650
8651 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8652  * Programming" based on the parameters passed:
8653  * - Sequence to enable CLKOUT_DP
8654  * - Sequence to enable CLKOUT_DP without spread
8655  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8656  */
8657 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8658                                  bool with_fdi)
8659 {
8660         struct drm_i915_private *dev_priv = dev->dev_private;
8661         uint32_t reg, tmp;
8662
8663         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8664                 with_spread = true;
8665         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8666                 with_fdi = false;
8667
8668         mutex_lock(&dev_priv->sb_lock);
8669
8670         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8671         tmp &= ~SBI_SSCCTL_DISABLE;
8672         tmp |= SBI_SSCCTL_PATHALT;
8673         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8674
8675         udelay(24);
8676
8677         if (with_spread) {
8678                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8679                 tmp &= ~SBI_SSCCTL_PATHALT;
8680                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8681
8682                 if (with_fdi) {
8683                         lpt_reset_fdi_mphy(dev_priv);
8684                         lpt_program_fdi_mphy(dev_priv);
8685                 }
8686         }
8687
8688         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8689         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8690         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8691         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8692
8693         mutex_unlock(&dev_priv->sb_lock);
8694 }
8695
8696 /* Sequence to disable CLKOUT_DP */
8697 static void lpt_disable_clkout_dp(struct drm_device *dev)
8698 {
8699         struct drm_i915_private *dev_priv = dev->dev_private;
8700         uint32_t reg, tmp;
8701
8702         mutex_lock(&dev_priv->sb_lock);
8703
8704         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8705         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8706         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8707         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8708
8709         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8710         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8711                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8712                         tmp |= SBI_SSCCTL_PATHALT;
8713                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8714                         udelay(32);
8715                 }
8716                 tmp |= SBI_SSCCTL_DISABLE;
8717                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8718         }
8719
8720         mutex_unlock(&dev_priv->sb_lock);
8721 }
8722
8723 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8724
8725 static const uint16_t sscdivintphase[] = {
8726         [BEND_IDX( 50)] = 0x3B23,
8727         [BEND_IDX( 45)] = 0x3B23,
8728         [BEND_IDX( 40)] = 0x3C23,
8729         [BEND_IDX( 35)] = 0x3C23,
8730         [BEND_IDX( 30)] = 0x3D23,
8731         [BEND_IDX( 25)] = 0x3D23,
8732         [BEND_IDX( 20)] = 0x3E23,
8733         [BEND_IDX( 15)] = 0x3E23,
8734         [BEND_IDX( 10)] = 0x3F23,
8735         [BEND_IDX(  5)] = 0x3F23,
8736         [BEND_IDX(  0)] = 0x0025,
8737         [BEND_IDX( -5)] = 0x0025,
8738         [BEND_IDX(-10)] = 0x0125,
8739         [BEND_IDX(-15)] = 0x0125,
8740         [BEND_IDX(-20)] = 0x0225,
8741         [BEND_IDX(-25)] = 0x0225,
8742         [BEND_IDX(-30)] = 0x0325,
8743         [BEND_IDX(-35)] = 0x0325,
8744         [BEND_IDX(-40)] = 0x0425,
8745         [BEND_IDX(-45)] = 0x0425,
8746         [BEND_IDX(-50)] = 0x0525,
8747 };
8748
8749 /*
8750  * Bend CLKOUT_DP
8751  * steps -50 to 50 inclusive, in steps of 5
8752  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8753  * change in clock period = -(steps / 10) * 5.787 ps
8754  */
8755 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8756 {
8757         uint32_t tmp;
8758         int idx = BEND_IDX(steps);
8759
8760         if (WARN_ON(steps % 5 != 0))
8761                 return;
8762
8763         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8764                 return;
8765
8766         mutex_lock(&dev_priv->sb_lock);
8767
8768         if (steps % 10 != 0)
8769                 tmp = 0xAAAAAAAB;
8770         else
8771                 tmp = 0x00000000;
8772         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8773
8774         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8775         tmp &= 0xffff0000;
8776         tmp |= sscdivintphase[idx];
8777         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8778
8779         mutex_unlock(&dev_priv->sb_lock);
8780 }
8781
8782 #undef BEND_IDX
8783
8784 static void lpt_init_pch_refclk(struct drm_device *dev)
8785 {
8786         struct intel_encoder *encoder;
8787         bool has_vga = false;
8788
8789         for_each_intel_encoder(dev, encoder) {
8790                 switch (encoder->type) {
8791                 case INTEL_OUTPUT_ANALOG:
8792                         has_vga = true;
8793                         break;
8794                 default:
8795                         break;
8796                 }
8797         }
8798
8799         if (has_vga) {
8800                 lpt_bend_clkout_dp(to_i915(dev), 0);
8801                 lpt_enable_clkout_dp(dev, true, true);
8802         } else {
8803                 lpt_disable_clkout_dp(dev);
8804         }
8805 }
8806
8807 /*
8808  * Initialize reference clocks when the driver loads
8809  */
8810 void intel_init_pch_refclk(struct drm_device *dev)
8811 {
8812         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8813                 ironlake_init_pch_refclk(dev);
8814         else if (HAS_PCH_LPT(dev))
8815                 lpt_init_pch_refclk(dev);
8816 }
8817
8818 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8819 {
8820         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8822         int pipe = intel_crtc->pipe;
8823         uint32_t val;
8824
8825         val = 0;
8826
8827         switch (intel_crtc->config->pipe_bpp) {
8828         case 18:
8829                 val |= PIPECONF_6BPC;
8830                 break;
8831         case 24:
8832                 val |= PIPECONF_8BPC;
8833                 break;
8834         case 30:
8835                 val |= PIPECONF_10BPC;
8836                 break;
8837         case 36:
8838                 val |= PIPECONF_12BPC;
8839                 break;
8840         default:
8841                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8842                 BUG();
8843         }
8844
8845         if (intel_crtc->config->dither)
8846                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8847
8848         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8849                 val |= PIPECONF_INTERLACED_ILK;
8850         else
8851                 val |= PIPECONF_PROGRESSIVE;
8852
8853         if (intel_crtc->config->limited_color_range)
8854                 val |= PIPECONF_COLOR_RANGE_SELECT;
8855
8856         I915_WRITE(PIPECONF(pipe), val);
8857         POSTING_READ(PIPECONF(pipe));
8858 }
8859
8860 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8861 {
8862         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8864         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8865         u32 val = 0;
8866
8867         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8868                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8869
8870         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8871                 val |= PIPECONF_INTERLACED_ILK;
8872         else
8873                 val |= PIPECONF_PROGRESSIVE;
8874
8875         I915_WRITE(PIPECONF(cpu_transcoder), val);
8876         POSTING_READ(PIPECONF(cpu_transcoder));
8877 }
8878
8879 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8880 {
8881         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8883
8884         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8885                 u32 val = 0;
8886
8887                 switch (intel_crtc->config->pipe_bpp) {
8888                 case 18:
8889                         val |= PIPEMISC_DITHER_6_BPC;
8890                         break;
8891                 case 24:
8892                         val |= PIPEMISC_DITHER_8_BPC;
8893                         break;
8894                 case 30:
8895                         val |= PIPEMISC_DITHER_10_BPC;
8896                         break;
8897                 case 36:
8898                         val |= PIPEMISC_DITHER_12_BPC;
8899                         break;
8900                 default:
8901                         /* Case prevented by pipe_config_set_bpp. */
8902                         BUG();
8903                 }
8904
8905                 if (intel_crtc->config->dither)
8906                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8907
8908                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8909         }
8910 }
8911
8912 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8913 {
8914         /*
8915          * Account for spread spectrum to avoid
8916          * oversubscribing the link. Max center spread
8917          * is 2.5%; use 5% for safety's sake.
8918          */
8919         u32 bps = target_clock * bpp * 21 / 20;
8920         return DIV_ROUND_UP(bps, link_bw * 8);
8921 }
8922
8923 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8924 {
8925         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8926 }
8927
8928 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8929                                   struct intel_crtc_state *crtc_state,
8930                                   struct dpll *reduced_clock)
8931 {
8932         struct drm_crtc *crtc = &intel_crtc->base;
8933         struct drm_device *dev = crtc->dev;
8934         struct drm_i915_private *dev_priv = dev->dev_private;
8935         struct drm_atomic_state *state = crtc_state->base.state;
8936         struct drm_connector *connector;
8937         struct drm_connector_state *connector_state;
8938         struct intel_encoder *encoder;
8939         u32 dpll, fp, fp2;
8940         int factor, i;
8941         bool is_lvds = false, is_sdvo = false;
8942
8943         for_each_connector_in_state(state, connector, connector_state, i) {
8944                 if (connector_state->crtc != crtc_state->base.crtc)
8945                         continue;
8946
8947                 encoder = to_intel_encoder(connector_state->best_encoder);
8948
8949                 switch (encoder->type) {
8950                 case INTEL_OUTPUT_LVDS:
8951                         is_lvds = true;
8952                         break;
8953                 case INTEL_OUTPUT_SDVO:
8954                 case INTEL_OUTPUT_HDMI:
8955                         is_sdvo = true;
8956                         break;
8957                 default:
8958                         break;
8959                 }
8960         }
8961
8962         /* Enable autotuning of the PLL clock (if permissible) */
8963         factor = 21;
8964         if (is_lvds) {
8965                 if ((intel_panel_use_ssc(dev_priv) &&
8966                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8967                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8968                         factor = 25;
8969         } else if (crtc_state->sdvo_tv_clock)
8970                 factor = 20;
8971
8972         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8973
8974         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8975                 fp |= FP_CB_TUNE;
8976
8977         if (reduced_clock) {
8978                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8979
8980                 if (reduced_clock->m < factor * reduced_clock->n)
8981                         fp2 |= FP_CB_TUNE;
8982         } else {
8983                 fp2 = fp;
8984         }
8985
8986         dpll = 0;
8987
8988         if (is_lvds)
8989                 dpll |= DPLLB_MODE_LVDS;
8990         else
8991                 dpll |= DPLLB_MODE_DAC_SERIAL;
8992
8993         dpll |= (crtc_state->pixel_multiplier - 1)
8994                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8995
8996         if (is_sdvo)
8997                 dpll |= DPLL_SDVO_HIGH_SPEED;
8998         if (crtc_state->has_dp_encoder)
8999                 dpll |= DPLL_SDVO_HIGH_SPEED;
9000
9001         /* compute bitmask from p1 value */
9002         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9003         /* also FPA1 */
9004         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9005
9006         switch (crtc_state->dpll.p2) {
9007         case 5:
9008                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9009                 break;
9010         case 7:
9011                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9012                 break;
9013         case 10:
9014                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9015                 break;
9016         case 14:
9017                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9018                 break;
9019         }
9020
9021         if (is_lvds && intel_panel_use_ssc(dev_priv))
9022                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9023         else
9024                 dpll |= PLL_REF_INPUT_DREFCLK;
9025
9026         dpll |= DPLL_VCO_ENABLE;
9027
9028         crtc_state->dpll_hw_state.dpll = dpll;
9029         crtc_state->dpll_hw_state.fp0 = fp;
9030         crtc_state->dpll_hw_state.fp1 = fp2;
9031 }
9032
9033 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9034                                        struct intel_crtc_state *crtc_state)
9035 {
9036         struct drm_device *dev = crtc->base.dev;
9037         struct drm_i915_private *dev_priv = dev->dev_private;
9038         struct dpll reduced_clock;
9039         bool has_reduced_clock = false;
9040         struct intel_shared_dpll *pll;
9041         const struct intel_limit *limit;
9042         int refclk = 120000;
9043
9044         memset(&crtc_state->dpll_hw_state, 0,
9045                sizeof(crtc_state->dpll_hw_state));
9046
9047         crtc->lowfreq_avail = false;
9048
9049         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9050         if (!crtc_state->has_pch_encoder)
9051                 return 0;
9052
9053         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9054                 if (intel_panel_use_ssc(dev_priv)) {
9055                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9056                                       dev_priv->vbt.lvds_ssc_freq);
9057                         refclk = dev_priv->vbt.lvds_ssc_freq;
9058                 }
9059
9060                 if (intel_is_dual_link_lvds(dev)) {
9061                         if (refclk == 100000)
9062                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9063                         else
9064                                 limit = &intel_limits_ironlake_dual_lvds;
9065                 } else {
9066                         if (refclk == 100000)
9067                                 limit = &intel_limits_ironlake_single_lvds_100m;
9068                         else
9069                                 limit = &intel_limits_ironlake_single_lvds;
9070                 }
9071         } else {
9072                 limit = &intel_limits_ironlake_dac;
9073         }
9074
9075         if (!crtc_state->clock_set &&
9076             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9077                                 refclk, NULL, &crtc_state->dpll)) {
9078                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9079                 return -EINVAL;
9080         }
9081
9082         ironlake_compute_dpll(crtc, crtc_state,
9083                               has_reduced_clock ? &reduced_clock : NULL);
9084
9085         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9086         if (pll == NULL) {
9087                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9088                                  pipe_name(crtc->pipe));
9089                 return -EINVAL;
9090         }
9091
9092         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9093             has_reduced_clock)
9094                 crtc->lowfreq_avail = true;
9095
9096         return 0;
9097 }
9098
9099 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9100                                          struct intel_link_m_n *m_n)
9101 {
9102         struct drm_device *dev = crtc->base.dev;
9103         struct drm_i915_private *dev_priv = dev->dev_private;
9104         enum pipe pipe = crtc->pipe;
9105
9106         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9107         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9108         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9109                 & ~TU_SIZE_MASK;
9110         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9111         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9112                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9113 }
9114
9115 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9116                                          enum transcoder transcoder,
9117                                          struct intel_link_m_n *m_n,
9118                                          struct intel_link_m_n *m2_n2)
9119 {
9120         struct drm_device *dev = crtc->base.dev;
9121         struct drm_i915_private *dev_priv = dev->dev_private;
9122         enum pipe pipe = crtc->pipe;
9123
9124         if (INTEL_INFO(dev)->gen >= 5) {
9125                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9126                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9127                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9128                         & ~TU_SIZE_MASK;
9129                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9130                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9131                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9132                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9133                  * gen < 8) and if DRRS is supported (to make sure the
9134                  * registers are not unnecessarily read).
9135                  */
9136                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9137                         crtc->config->has_drrs) {
9138                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9139                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9140                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9141                                         & ~TU_SIZE_MASK;
9142                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9143                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9144                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9145                 }
9146         } else {
9147                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9148                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9149                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9150                         & ~TU_SIZE_MASK;
9151                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9152                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9153                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9154         }
9155 }
9156
9157 void intel_dp_get_m_n(struct intel_crtc *crtc,
9158                       struct intel_crtc_state *pipe_config)
9159 {
9160         if (pipe_config->has_pch_encoder)
9161                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9162         else
9163                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9164                                              &pipe_config->dp_m_n,
9165                                              &pipe_config->dp_m2_n2);
9166 }
9167
9168 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9169                                         struct intel_crtc_state *pipe_config)
9170 {
9171         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9172                                      &pipe_config->fdi_m_n, NULL);
9173 }
9174
9175 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9176                                     struct intel_crtc_state *pipe_config)
9177 {
9178         struct drm_device *dev = crtc->base.dev;
9179         struct drm_i915_private *dev_priv = dev->dev_private;
9180         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9181         uint32_t ps_ctrl = 0;
9182         int id = -1;
9183         int i;
9184
9185         /* find scaler attached to this pipe */
9186         for (i = 0; i < crtc->num_scalers; i++) {
9187                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9188                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9189                         id = i;
9190                         pipe_config->pch_pfit.enabled = true;
9191                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9192                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9193                         break;
9194                 }
9195         }
9196
9197         scaler_state->scaler_id = id;
9198         if (id >= 0) {
9199                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9200         } else {
9201                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9202         }
9203 }
9204
9205 static void
9206 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9207                                  struct intel_initial_plane_config *plane_config)
9208 {
9209         struct drm_device *dev = crtc->base.dev;
9210         struct drm_i915_private *dev_priv = dev->dev_private;
9211         u32 val, base, offset, stride_mult, tiling;
9212         int pipe = crtc->pipe;
9213         int fourcc, pixel_format;
9214         unsigned int aligned_height;
9215         struct drm_framebuffer *fb;
9216         struct intel_framebuffer *intel_fb;
9217
9218         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9219         if (!intel_fb) {
9220                 DRM_DEBUG_KMS("failed to alloc fb\n");
9221                 return;
9222         }
9223
9224         fb = &intel_fb->base;
9225
9226         val = I915_READ(PLANE_CTL(pipe, 0));
9227         if (!(val & PLANE_CTL_ENABLE))
9228                 goto error;
9229
9230         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9231         fourcc = skl_format_to_fourcc(pixel_format,
9232                                       val & PLANE_CTL_ORDER_RGBX,
9233                                       val & PLANE_CTL_ALPHA_MASK);
9234         fb->pixel_format = fourcc;
9235         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9236
9237         tiling = val & PLANE_CTL_TILED_MASK;
9238         switch (tiling) {
9239         case PLANE_CTL_TILED_LINEAR:
9240                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9241                 break;
9242         case PLANE_CTL_TILED_X:
9243                 plane_config->tiling = I915_TILING_X;
9244                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9245                 break;
9246         case PLANE_CTL_TILED_Y:
9247                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9248                 break;
9249         case PLANE_CTL_TILED_YF:
9250                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9251                 break;
9252         default:
9253                 MISSING_CASE(tiling);
9254                 goto error;
9255         }
9256
9257         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9258         plane_config->base = base;
9259
9260         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9261
9262         val = I915_READ(PLANE_SIZE(pipe, 0));
9263         fb->height = ((val >> 16) & 0xfff) + 1;
9264         fb->width = ((val >> 0) & 0x1fff) + 1;
9265
9266         val = I915_READ(PLANE_STRIDE(pipe, 0));
9267         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9268                                                 fb->pixel_format);
9269         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9270
9271         aligned_height = intel_fb_align_height(dev, fb->height,
9272                                                fb->pixel_format,
9273                                                fb->modifier[0]);
9274
9275         plane_config->size = fb->pitches[0] * aligned_height;
9276
9277         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9278                       pipe_name(pipe), fb->width, fb->height,
9279                       fb->bits_per_pixel, base, fb->pitches[0],
9280                       plane_config->size);
9281
9282         plane_config->fb = intel_fb;
9283         return;
9284
9285 error:
9286         kfree(fb);
9287 }
9288
9289 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9290                                      struct intel_crtc_state *pipe_config)
9291 {
9292         struct drm_device *dev = crtc->base.dev;
9293         struct drm_i915_private *dev_priv = dev->dev_private;
9294         uint32_t tmp;
9295
9296         tmp = I915_READ(PF_CTL(crtc->pipe));
9297
9298         if (tmp & PF_ENABLE) {
9299                 pipe_config->pch_pfit.enabled = true;
9300                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9301                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9302
9303                 /* We currently do not free assignements of panel fitters on
9304                  * ivb/hsw (since we don't use the higher upscaling modes which
9305                  * differentiates them) so just WARN about this case for now. */
9306                 if (IS_GEN7(dev)) {
9307                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9308                                 PF_PIPE_SEL_IVB(crtc->pipe));
9309                 }
9310         }
9311 }
9312
9313 static void
9314 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9315                                   struct intel_initial_plane_config *plane_config)
9316 {
9317         struct drm_device *dev = crtc->base.dev;
9318         struct drm_i915_private *dev_priv = dev->dev_private;
9319         u32 val, base, offset;
9320         int pipe = crtc->pipe;
9321         int fourcc, pixel_format;
9322         unsigned int aligned_height;
9323         struct drm_framebuffer *fb;
9324         struct intel_framebuffer *intel_fb;
9325
9326         val = I915_READ(DSPCNTR(pipe));
9327         if (!(val & DISPLAY_PLANE_ENABLE))
9328                 return;
9329
9330         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9331         if (!intel_fb) {
9332                 DRM_DEBUG_KMS("failed to alloc fb\n");
9333                 return;
9334         }
9335
9336         fb = &intel_fb->base;
9337
9338         if (INTEL_INFO(dev)->gen >= 4) {
9339                 if (val & DISPPLANE_TILED) {
9340                         plane_config->tiling = I915_TILING_X;
9341                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9342                 }
9343         }
9344
9345         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9346         fourcc = i9xx_format_to_fourcc(pixel_format);
9347         fb->pixel_format = fourcc;
9348         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9349
9350         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9351         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9352                 offset = I915_READ(DSPOFFSET(pipe));
9353         } else {
9354                 if (plane_config->tiling)
9355                         offset = I915_READ(DSPTILEOFF(pipe));
9356                 else
9357                         offset = I915_READ(DSPLINOFF(pipe));
9358         }
9359         plane_config->base = base;
9360
9361         val = I915_READ(PIPESRC(pipe));
9362         fb->width = ((val >> 16) & 0xfff) + 1;
9363         fb->height = ((val >> 0) & 0xfff) + 1;
9364
9365         val = I915_READ(DSPSTRIDE(pipe));
9366         fb->pitches[0] = val & 0xffffffc0;
9367
9368         aligned_height = intel_fb_align_height(dev, fb->height,
9369                                                fb->pixel_format,
9370                                                fb->modifier[0]);
9371
9372         plane_config->size = fb->pitches[0] * aligned_height;
9373
9374         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9375                       pipe_name(pipe), fb->width, fb->height,
9376                       fb->bits_per_pixel, base, fb->pitches[0],
9377                       plane_config->size);
9378
9379         plane_config->fb = intel_fb;
9380 }
9381
9382 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9383                                      struct intel_crtc_state *pipe_config)
9384 {
9385         struct drm_device *dev = crtc->base.dev;
9386         struct drm_i915_private *dev_priv = dev->dev_private;
9387         enum intel_display_power_domain power_domain;
9388         uint32_t tmp;
9389         bool ret;
9390
9391         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9392         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9393                 return false;
9394
9395         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9396         pipe_config->shared_dpll = NULL;
9397
9398         ret = false;
9399         tmp = I915_READ(PIPECONF(crtc->pipe));
9400         if (!(tmp & PIPECONF_ENABLE))
9401                 goto out;
9402
9403         switch (tmp & PIPECONF_BPC_MASK) {
9404         case PIPECONF_6BPC:
9405                 pipe_config->pipe_bpp = 18;
9406                 break;
9407         case PIPECONF_8BPC:
9408                 pipe_config->pipe_bpp = 24;
9409                 break;
9410         case PIPECONF_10BPC:
9411                 pipe_config->pipe_bpp = 30;
9412                 break;
9413         case PIPECONF_12BPC:
9414                 pipe_config->pipe_bpp = 36;
9415                 break;
9416         default:
9417                 break;
9418         }
9419
9420         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9421                 pipe_config->limited_color_range = true;
9422
9423         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9424                 struct intel_shared_dpll *pll;
9425                 enum intel_dpll_id pll_id;
9426
9427                 pipe_config->has_pch_encoder = true;
9428
9429                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9430                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9431                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9432
9433                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9434
9435                 if (HAS_PCH_IBX(dev_priv)) {
9436                         /*
9437                          * The pipe->pch transcoder and pch transcoder->pll
9438                          * mapping is fixed.
9439                          */
9440                         pll_id = (enum intel_dpll_id) crtc->pipe;
9441                 } else {
9442                         tmp = I915_READ(PCH_DPLL_SEL);
9443                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9444                                 pll_id = DPLL_ID_PCH_PLL_B;
9445                         else
9446                                 pll_id= DPLL_ID_PCH_PLL_A;
9447                 }
9448
9449                 pipe_config->shared_dpll =
9450                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9451                 pll = pipe_config->shared_dpll;
9452
9453                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9454                                                  &pipe_config->dpll_hw_state));
9455
9456                 tmp = pipe_config->dpll_hw_state.dpll;
9457                 pipe_config->pixel_multiplier =
9458                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9459                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9460
9461                 ironlake_pch_clock_get(crtc, pipe_config);
9462         } else {
9463                 pipe_config->pixel_multiplier = 1;
9464         }
9465
9466         intel_get_pipe_timings(crtc, pipe_config);
9467         intel_get_pipe_src_size(crtc, pipe_config);
9468
9469         ironlake_get_pfit_config(crtc, pipe_config);
9470
9471         ret = true;
9472
9473 out:
9474         intel_display_power_put(dev_priv, power_domain);
9475
9476         return ret;
9477 }
9478
9479 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9480 {
9481         struct drm_device *dev = dev_priv->dev;
9482         struct intel_crtc *crtc;
9483
9484         for_each_intel_crtc(dev, crtc)
9485                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9486                      pipe_name(crtc->pipe));
9487
9488         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9489         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9490         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9491         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9492         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9493         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9494              "CPU PWM1 enabled\n");
9495         if (IS_HASWELL(dev))
9496                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9497                      "CPU PWM2 enabled\n");
9498         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9499              "PCH PWM1 enabled\n");
9500         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9501              "Utility pin enabled\n");
9502         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9503
9504         /*
9505          * In theory we can still leave IRQs enabled, as long as only the HPD
9506          * interrupts remain enabled. We used to check for that, but since it's
9507          * gen-specific and since we only disable LCPLL after we fully disable
9508          * the interrupts, the check below should be enough.
9509          */
9510         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9511 }
9512
9513 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9514 {
9515         struct drm_device *dev = dev_priv->dev;
9516
9517         if (IS_HASWELL(dev))
9518                 return I915_READ(D_COMP_HSW);
9519         else
9520                 return I915_READ(D_COMP_BDW);
9521 }
9522
9523 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9524 {
9525         struct drm_device *dev = dev_priv->dev;
9526
9527         if (IS_HASWELL(dev)) {
9528                 mutex_lock(&dev_priv->rps.hw_lock);
9529                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9530                                             val))
9531                         DRM_ERROR("Failed to write to D_COMP\n");
9532                 mutex_unlock(&dev_priv->rps.hw_lock);
9533         } else {
9534                 I915_WRITE(D_COMP_BDW, val);
9535                 POSTING_READ(D_COMP_BDW);
9536         }
9537 }
9538
9539 /*
9540  * This function implements pieces of two sequences from BSpec:
9541  * - Sequence for display software to disable LCPLL
9542  * - Sequence for display software to allow package C8+
9543  * The steps implemented here are just the steps that actually touch the LCPLL
9544  * register. Callers should take care of disabling all the display engine
9545  * functions, doing the mode unset, fixing interrupts, etc.
9546  */
9547 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9548                               bool switch_to_fclk, bool allow_power_down)
9549 {
9550         uint32_t val;
9551
9552         assert_can_disable_lcpll(dev_priv);
9553
9554         val = I915_READ(LCPLL_CTL);
9555
9556         if (switch_to_fclk) {
9557                 val |= LCPLL_CD_SOURCE_FCLK;
9558                 I915_WRITE(LCPLL_CTL, val);
9559
9560                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9561                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9562                         DRM_ERROR("Switching to FCLK failed\n");
9563
9564                 val = I915_READ(LCPLL_CTL);
9565         }
9566
9567         val |= LCPLL_PLL_DISABLE;
9568         I915_WRITE(LCPLL_CTL, val);
9569         POSTING_READ(LCPLL_CTL);
9570
9571         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9572                 DRM_ERROR("LCPLL still locked\n");
9573
9574         val = hsw_read_dcomp(dev_priv);
9575         val |= D_COMP_COMP_DISABLE;
9576         hsw_write_dcomp(dev_priv, val);
9577         ndelay(100);
9578
9579         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9580                      1))
9581                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9582
9583         if (allow_power_down) {
9584                 val = I915_READ(LCPLL_CTL);
9585                 val |= LCPLL_POWER_DOWN_ALLOW;
9586                 I915_WRITE(LCPLL_CTL, val);
9587                 POSTING_READ(LCPLL_CTL);
9588         }
9589 }
9590
9591 /*
9592  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9593  * source.
9594  */
9595 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9596 {
9597         uint32_t val;
9598
9599         val = I915_READ(LCPLL_CTL);
9600
9601         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9602                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9603                 return;
9604
9605         /*
9606          * Make sure we're not on PC8 state before disabling PC8, otherwise
9607          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9608          */
9609         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9610
9611         if (val & LCPLL_POWER_DOWN_ALLOW) {
9612                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9613                 I915_WRITE(LCPLL_CTL, val);
9614                 POSTING_READ(LCPLL_CTL);
9615         }
9616
9617         val = hsw_read_dcomp(dev_priv);
9618         val |= D_COMP_COMP_FORCE;
9619         val &= ~D_COMP_COMP_DISABLE;
9620         hsw_write_dcomp(dev_priv, val);
9621
9622         val = I915_READ(LCPLL_CTL);
9623         val &= ~LCPLL_PLL_DISABLE;
9624         I915_WRITE(LCPLL_CTL, val);
9625
9626         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9627                 DRM_ERROR("LCPLL not locked yet\n");
9628
9629         if (val & LCPLL_CD_SOURCE_FCLK) {
9630                 val = I915_READ(LCPLL_CTL);
9631                 val &= ~LCPLL_CD_SOURCE_FCLK;
9632                 I915_WRITE(LCPLL_CTL, val);
9633
9634                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9635                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9636                         DRM_ERROR("Switching back to LCPLL failed\n");
9637         }
9638
9639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9640         intel_update_cdclk(dev_priv->dev);
9641 }
9642
9643 /*
9644  * Package states C8 and deeper are really deep PC states that can only be
9645  * reached when all the devices on the system allow it, so even if the graphics
9646  * device allows PC8+, it doesn't mean the system will actually get to these
9647  * states. Our driver only allows PC8+ when going into runtime PM.
9648  *
9649  * The requirements for PC8+ are that all the outputs are disabled, the power
9650  * well is disabled and most interrupts are disabled, and these are also
9651  * requirements for runtime PM. When these conditions are met, we manually do
9652  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9653  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9654  * hang the machine.
9655  *
9656  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9657  * the state of some registers, so when we come back from PC8+ we need to
9658  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9659  * need to take care of the registers kept by RC6. Notice that this happens even
9660  * if we don't put the device in PCI D3 state (which is what currently happens
9661  * because of the runtime PM support).
9662  *
9663  * For more, read "Display Sequences for Package C8" on the hardware
9664  * documentation.
9665  */
9666 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9667 {
9668         struct drm_device *dev = dev_priv->dev;
9669         uint32_t val;
9670
9671         DRM_DEBUG_KMS("Enabling package C8+\n");
9672
9673         if (HAS_PCH_LPT_LP(dev)) {
9674                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9675                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9676                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9677         }
9678
9679         lpt_disable_clkout_dp(dev);
9680         hsw_disable_lcpll(dev_priv, true, true);
9681 }
9682
9683 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9684 {
9685         struct drm_device *dev = dev_priv->dev;
9686         uint32_t val;
9687
9688         DRM_DEBUG_KMS("Disabling package C8+\n");
9689
9690         hsw_restore_lcpll(dev_priv);
9691         lpt_init_pch_refclk(dev);
9692
9693         if (HAS_PCH_LPT_LP(dev)) {
9694                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9695                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9696                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9697         }
9698 }
9699
9700 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9701 {
9702         struct drm_device *dev = old_state->dev;
9703         struct intel_atomic_state *old_intel_state =
9704                 to_intel_atomic_state(old_state);
9705         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9706
9707         bxt_set_cdclk(to_i915(dev), req_cdclk);
9708 }
9709
9710 /* compute the max rate for new configuration */
9711 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9712 {
9713         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9714         struct drm_i915_private *dev_priv = state->dev->dev_private;
9715         struct drm_crtc *crtc;
9716         struct drm_crtc_state *cstate;
9717         struct intel_crtc_state *crtc_state;
9718         unsigned max_pixel_rate = 0, i;
9719         enum pipe pipe;
9720
9721         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9722                sizeof(intel_state->min_pixclk));
9723
9724         for_each_crtc_in_state(state, crtc, cstate, i) {
9725                 int pixel_rate;
9726
9727                 crtc_state = to_intel_crtc_state(cstate);
9728                 if (!crtc_state->base.enable) {
9729                         intel_state->min_pixclk[i] = 0;
9730                         continue;
9731                 }
9732
9733                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9734
9735                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9736                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9737                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9738
9739                 intel_state->min_pixclk[i] = pixel_rate;
9740         }
9741
9742         for_each_pipe(dev_priv, pipe)
9743                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9744
9745         return max_pixel_rate;
9746 }
9747
9748 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9749 {
9750         struct drm_i915_private *dev_priv = dev->dev_private;
9751         uint32_t val, data;
9752         int ret;
9753
9754         if (WARN((I915_READ(LCPLL_CTL) &
9755                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9756                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9757                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9758                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9759                  "trying to change cdclk frequency with cdclk not enabled\n"))
9760                 return;
9761
9762         mutex_lock(&dev_priv->rps.hw_lock);
9763         ret = sandybridge_pcode_write(dev_priv,
9764                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9765         mutex_unlock(&dev_priv->rps.hw_lock);
9766         if (ret) {
9767                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9768                 return;
9769         }
9770
9771         val = I915_READ(LCPLL_CTL);
9772         val |= LCPLL_CD_SOURCE_FCLK;
9773         I915_WRITE(LCPLL_CTL, val);
9774
9775         if (wait_for_us(I915_READ(LCPLL_CTL) &
9776                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9777                 DRM_ERROR("Switching to FCLK failed\n");
9778
9779         val = I915_READ(LCPLL_CTL);
9780         val &= ~LCPLL_CLK_FREQ_MASK;
9781
9782         switch (cdclk) {
9783         case 450000:
9784                 val |= LCPLL_CLK_FREQ_450;
9785                 data = 0;
9786                 break;
9787         case 540000:
9788                 val |= LCPLL_CLK_FREQ_54O_BDW;
9789                 data = 1;
9790                 break;
9791         case 337500:
9792                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9793                 data = 2;
9794                 break;
9795         case 675000:
9796                 val |= LCPLL_CLK_FREQ_675_BDW;
9797                 data = 3;
9798                 break;
9799         default:
9800                 WARN(1, "invalid cdclk frequency\n");
9801                 return;
9802         }
9803
9804         I915_WRITE(LCPLL_CTL, val);
9805
9806         val = I915_READ(LCPLL_CTL);
9807         val &= ~LCPLL_CD_SOURCE_FCLK;
9808         I915_WRITE(LCPLL_CTL, val);
9809
9810         if (wait_for_us((I915_READ(LCPLL_CTL) &
9811                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9812                 DRM_ERROR("Switching back to LCPLL failed\n");
9813
9814         mutex_lock(&dev_priv->rps.hw_lock);
9815         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9816         mutex_unlock(&dev_priv->rps.hw_lock);
9817
9818         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9819
9820         intel_update_cdclk(dev);
9821
9822         WARN(cdclk != dev_priv->cdclk_freq,
9823              "cdclk requested %d kHz but got %d kHz\n",
9824              cdclk, dev_priv->cdclk_freq);
9825 }
9826
9827 static int broadwell_calc_cdclk(int max_pixclk)
9828 {
9829         if (max_pixclk > 540000)
9830                 return 675000;
9831         else if (max_pixclk > 450000)
9832                 return 540000;
9833         else if (max_pixclk > 337500)
9834                 return 450000;
9835         else
9836                 return 337500;
9837 }
9838
9839 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9840 {
9841         struct drm_i915_private *dev_priv = to_i915(state->dev);
9842         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9843         int max_pixclk = ilk_max_pixel_rate(state);
9844         int cdclk;
9845
9846         /*
9847          * FIXME should also account for plane ratio
9848          * once 64bpp pixel formats are supported.
9849          */
9850         cdclk = broadwell_calc_cdclk(max_pixclk);
9851
9852         if (cdclk > dev_priv->max_cdclk_freq) {
9853                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9854                               cdclk, dev_priv->max_cdclk_freq);
9855                 return -EINVAL;
9856         }
9857
9858         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9859         if (!intel_state->active_crtcs)
9860                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9861
9862         return 0;
9863 }
9864
9865 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9866 {
9867         struct drm_device *dev = old_state->dev;
9868         struct intel_atomic_state *old_intel_state =
9869                 to_intel_atomic_state(old_state);
9870         unsigned req_cdclk = old_intel_state->dev_cdclk;
9871
9872         broadwell_set_cdclk(dev, req_cdclk);
9873 }
9874
9875 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9876 {
9877         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9878         struct drm_i915_private *dev_priv = to_i915(state->dev);
9879         const int max_pixclk = ilk_max_pixel_rate(state);
9880         int vco = intel_state->cdclk_pll_vco;
9881         int cdclk;
9882
9883         /*
9884          * FIXME should also account for plane ratio
9885          * once 64bpp pixel formats are supported.
9886          */
9887         cdclk = skl_calc_cdclk(max_pixclk, vco);
9888
9889         /*
9890          * FIXME move the cdclk caclulation to
9891          * compute_config() so we can fail gracegully.
9892          */
9893         if (cdclk > dev_priv->max_cdclk_freq) {
9894                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9895                           cdclk, dev_priv->max_cdclk_freq);
9896                 cdclk = dev_priv->max_cdclk_freq;
9897         }
9898
9899         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9900         if (!intel_state->active_crtcs)
9901                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9902
9903         return 0;
9904 }
9905
9906 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9907 {
9908         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9909         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9910         unsigned int req_cdclk = intel_state->dev_cdclk;
9911         unsigned int req_vco = intel_state->cdclk_pll_vco;
9912
9913         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9914 }
9915
9916 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9917                                       struct intel_crtc_state *crtc_state)
9918 {
9919         struct intel_encoder *intel_encoder =
9920                 intel_ddi_get_crtc_new_encoder(crtc_state);
9921
9922         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9923                 if (!intel_ddi_pll_select(crtc, crtc_state))
9924                         return -EINVAL;
9925         }
9926
9927         crtc->lowfreq_avail = false;
9928
9929         return 0;
9930 }
9931
9932 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9933                                 enum port port,
9934                                 struct intel_crtc_state *pipe_config)
9935 {
9936         enum intel_dpll_id id;
9937
9938         switch (port) {
9939         case PORT_A:
9940                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9941                 id = DPLL_ID_SKL_DPLL0;
9942                 break;
9943         case PORT_B:
9944                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9945                 id = DPLL_ID_SKL_DPLL1;
9946                 break;
9947         case PORT_C:
9948                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9949                 id = DPLL_ID_SKL_DPLL2;
9950                 break;
9951         default:
9952                 DRM_ERROR("Incorrect port type\n");
9953                 return;
9954         }
9955
9956         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9957 }
9958
9959 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9960                                 enum port port,
9961                                 struct intel_crtc_state *pipe_config)
9962 {
9963         enum intel_dpll_id id;
9964         u32 temp;
9965
9966         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9967         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9968
9969         switch (pipe_config->ddi_pll_sel) {
9970         case SKL_DPLL0:
9971                 id = DPLL_ID_SKL_DPLL0;
9972                 break;
9973         case SKL_DPLL1:
9974                 id = DPLL_ID_SKL_DPLL1;
9975                 break;
9976         case SKL_DPLL2:
9977                 id = DPLL_ID_SKL_DPLL2;
9978                 break;
9979         case SKL_DPLL3:
9980                 id = DPLL_ID_SKL_DPLL3;
9981                 break;
9982         default:
9983                 MISSING_CASE(pipe_config->ddi_pll_sel);
9984                 return;
9985         }
9986
9987         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9988 }
9989
9990 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9991                                 enum port port,
9992                                 struct intel_crtc_state *pipe_config)
9993 {
9994         enum intel_dpll_id id;
9995
9996         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9997
9998         switch (pipe_config->ddi_pll_sel) {
9999         case PORT_CLK_SEL_WRPLL1:
10000                 id = DPLL_ID_WRPLL1;
10001                 break;
10002         case PORT_CLK_SEL_WRPLL2:
10003                 id = DPLL_ID_WRPLL2;
10004                 break;
10005         case PORT_CLK_SEL_SPLL:
10006                 id = DPLL_ID_SPLL;
10007                 break;
10008         case PORT_CLK_SEL_LCPLL_810:
10009                 id = DPLL_ID_LCPLL_810;
10010                 break;
10011         case PORT_CLK_SEL_LCPLL_1350:
10012                 id = DPLL_ID_LCPLL_1350;
10013                 break;
10014         case PORT_CLK_SEL_LCPLL_2700:
10015                 id = DPLL_ID_LCPLL_2700;
10016                 break;
10017         default:
10018                 MISSING_CASE(pipe_config->ddi_pll_sel);
10019                 /* fall through */
10020         case PORT_CLK_SEL_NONE:
10021                 return;
10022         }
10023
10024         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10025 }
10026
10027 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10028                                      struct intel_crtc_state *pipe_config,
10029                                      unsigned long *power_domain_mask)
10030 {
10031         struct drm_device *dev = crtc->base.dev;
10032         struct drm_i915_private *dev_priv = dev->dev_private;
10033         enum intel_display_power_domain power_domain;
10034         u32 tmp;
10035
10036         /*
10037          * The pipe->transcoder mapping is fixed with the exception of the eDP
10038          * transcoder handled below.
10039          */
10040         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10041
10042         /*
10043          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10044          * consistency and less surprising code; it's in always on power).
10045          */
10046         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10047         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10048                 enum pipe trans_edp_pipe;
10049                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10050                 default:
10051                         WARN(1, "unknown pipe linked to edp transcoder\n");
10052                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10053                 case TRANS_DDI_EDP_INPUT_A_ON:
10054                         trans_edp_pipe = PIPE_A;
10055                         break;
10056                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10057                         trans_edp_pipe = PIPE_B;
10058                         break;
10059                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10060                         trans_edp_pipe = PIPE_C;
10061                         break;
10062                 }
10063
10064                 if (trans_edp_pipe == crtc->pipe)
10065                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10066         }
10067
10068         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10069         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10070                 return false;
10071         *power_domain_mask |= BIT(power_domain);
10072
10073         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10074
10075         return tmp & PIPECONF_ENABLE;
10076 }
10077
10078 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10079                                          struct intel_crtc_state *pipe_config,
10080                                          unsigned long *power_domain_mask)
10081 {
10082         struct drm_device *dev = crtc->base.dev;
10083         struct drm_i915_private *dev_priv = dev->dev_private;
10084         enum intel_display_power_domain power_domain;
10085         enum port port;
10086         enum transcoder cpu_transcoder;
10087         u32 tmp;
10088
10089         pipe_config->has_dsi_encoder = false;
10090
10091         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10092                 if (port == PORT_A)
10093                         cpu_transcoder = TRANSCODER_DSI_A;
10094                 else
10095                         cpu_transcoder = TRANSCODER_DSI_C;
10096
10097                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10098                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10099                         continue;
10100                 *power_domain_mask |= BIT(power_domain);
10101
10102                 /*
10103                  * The PLL needs to be enabled with a valid divider
10104                  * configuration, otherwise accessing DSI registers will hang
10105                  * the machine. See BSpec North Display Engine
10106                  * registers/MIPI[BXT]. We can break out here early, since we
10107                  * need the same DSI PLL to be enabled for both DSI ports.
10108                  */
10109                 if (!intel_dsi_pll_is_enabled(dev_priv))
10110                         break;
10111
10112                 /* XXX: this works for video mode only */
10113                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10114                 if (!(tmp & DPI_ENABLE))
10115                         continue;
10116
10117                 tmp = I915_READ(MIPI_CTRL(port));
10118                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10119                         continue;
10120
10121                 pipe_config->cpu_transcoder = cpu_transcoder;
10122                 pipe_config->has_dsi_encoder = true;
10123                 break;
10124         }
10125
10126         return pipe_config->has_dsi_encoder;
10127 }
10128
10129 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10130                                        struct intel_crtc_state *pipe_config)
10131 {
10132         struct drm_device *dev = crtc->base.dev;
10133         struct drm_i915_private *dev_priv = dev->dev_private;
10134         struct intel_shared_dpll *pll;
10135         enum port port;
10136         uint32_t tmp;
10137
10138         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10139
10140         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10141
10142         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10143                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10144         else if (IS_BROXTON(dev))
10145                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10146         else
10147                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10148
10149         pll = pipe_config->shared_dpll;
10150         if (pll) {
10151                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10152                                                  &pipe_config->dpll_hw_state));
10153         }
10154
10155         /*
10156          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10157          * DDI E. So just check whether this pipe is wired to DDI E and whether
10158          * the PCH transcoder is on.
10159          */
10160         if (INTEL_INFO(dev)->gen < 9 &&
10161             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10162                 pipe_config->has_pch_encoder = true;
10163
10164                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10165                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10166                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10167
10168                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10169         }
10170 }
10171
10172 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10173                                     struct intel_crtc_state *pipe_config)
10174 {
10175         struct drm_device *dev = crtc->base.dev;
10176         struct drm_i915_private *dev_priv = dev->dev_private;
10177         enum intel_display_power_domain power_domain;
10178         unsigned long power_domain_mask;
10179         bool active;
10180
10181         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10182         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10183                 return false;
10184         power_domain_mask = BIT(power_domain);
10185
10186         pipe_config->shared_dpll = NULL;
10187
10188         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10189
10190         if (IS_BROXTON(dev_priv)) {
10191                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10192                                              &power_domain_mask);
10193                 WARN_ON(active && pipe_config->has_dsi_encoder);
10194                 if (pipe_config->has_dsi_encoder)
10195                         active = true;
10196         }
10197
10198         if (!active)
10199                 goto out;
10200
10201         if (!pipe_config->has_dsi_encoder) {
10202                 haswell_get_ddi_port_state(crtc, pipe_config);
10203                 intel_get_pipe_timings(crtc, pipe_config);
10204         }
10205
10206         intel_get_pipe_src_size(crtc, pipe_config);
10207
10208         pipe_config->gamma_mode =
10209                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10210
10211         if (INTEL_INFO(dev)->gen >= 9) {
10212                 skl_init_scalers(dev, crtc, pipe_config);
10213         }
10214
10215         if (INTEL_INFO(dev)->gen >= 9) {
10216                 pipe_config->scaler_state.scaler_id = -1;
10217                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10218         }
10219
10220         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10221         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10222                 power_domain_mask |= BIT(power_domain);
10223                 if (INTEL_INFO(dev)->gen >= 9)
10224                         skylake_get_pfit_config(crtc, pipe_config);
10225                 else
10226                         ironlake_get_pfit_config(crtc, pipe_config);
10227         }
10228
10229         if (IS_HASWELL(dev))
10230                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10231                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10232
10233         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10234             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10235                 pipe_config->pixel_multiplier =
10236                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10237         } else {
10238                 pipe_config->pixel_multiplier = 1;
10239         }
10240
10241 out:
10242         for_each_power_domain(power_domain, power_domain_mask)
10243                 intel_display_power_put(dev_priv, power_domain);
10244
10245         return active;
10246 }
10247
10248 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10249                                const struct intel_plane_state *plane_state)
10250 {
10251         struct drm_device *dev = crtc->dev;
10252         struct drm_i915_private *dev_priv = dev->dev_private;
10253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10254         uint32_t cntl = 0, size = 0;
10255
10256         if (plane_state && plane_state->visible) {
10257                 unsigned int width = plane_state->base.crtc_w;
10258                 unsigned int height = plane_state->base.crtc_h;
10259                 unsigned int stride = roundup_pow_of_two(width) * 4;
10260
10261                 switch (stride) {
10262                 default:
10263                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10264                                   width, stride);
10265                         stride = 256;
10266                         /* fallthrough */
10267                 case 256:
10268                 case 512:
10269                 case 1024:
10270                 case 2048:
10271                         break;
10272                 }
10273
10274                 cntl |= CURSOR_ENABLE |
10275                         CURSOR_GAMMA_ENABLE |
10276                         CURSOR_FORMAT_ARGB |
10277                         CURSOR_STRIDE(stride);
10278
10279                 size = (height << 12) | width;
10280         }
10281
10282         if (intel_crtc->cursor_cntl != 0 &&
10283             (intel_crtc->cursor_base != base ||
10284              intel_crtc->cursor_size != size ||
10285              intel_crtc->cursor_cntl != cntl)) {
10286                 /* On these chipsets we can only modify the base/size/stride
10287                  * whilst the cursor is disabled.
10288                  */
10289                 I915_WRITE(CURCNTR(PIPE_A), 0);
10290                 POSTING_READ(CURCNTR(PIPE_A));
10291                 intel_crtc->cursor_cntl = 0;
10292         }
10293
10294         if (intel_crtc->cursor_base != base) {
10295                 I915_WRITE(CURBASE(PIPE_A), base);
10296                 intel_crtc->cursor_base = base;
10297         }
10298
10299         if (intel_crtc->cursor_size != size) {
10300                 I915_WRITE(CURSIZE, size);
10301                 intel_crtc->cursor_size = size;
10302         }
10303
10304         if (intel_crtc->cursor_cntl != cntl) {
10305                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10306                 POSTING_READ(CURCNTR(PIPE_A));
10307                 intel_crtc->cursor_cntl = cntl;
10308         }
10309 }
10310
10311 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10312                                const struct intel_plane_state *plane_state)
10313 {
10314         struct drm_device *dev = crtc->dev;
10315         struct drm_i915_private *dev_priv = dev->dev_private;
10316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10317         int pipe = intel_crtc->pipe;
10318         uint32_t cntl = 0;
10319
10320         if (plane_state && plane_state->visible) {
10321                 cntl = MCURSOR_GAMMA_ENABLE;
10322                 switch (plane_state->base.crtc_w) {
10323                         case 64:
10324                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10325                                 break;
10326                         case 128:
10327                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10328                                 break;
10329                         case 256:
10330                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10331                                 break;
10332                         default:
10333                                 MISSING_CASE(plane_state->base.crtc_w);
10334                                 return;
10335                 }
10336                 cntl |= pipe << 28; /* Connect to correct pipe */
10337
10338                 if (HAS_DDI(dev))
10339                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10340
10341                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10342                         cntl |= CURSOR_ROTATE_180;
10343         }
10344
10345         if (intel_crtc->cursor_cntl != cntl) {
10346                 I915_WRITE(CURCNTR(pipe), cntl);
10347                 POSTING_READ(CURCNTR(pipe));
10348                 intel_crtc->cursor_cntl = cntl;
10349         }
10350
10351         /* and commit changes on next vblank */
10352         I915_WRITE(CURBASE(pipe), base);
10353         POSTING_READ(CURBASE(pipe));
10354
10355         intel_crtc->cursor_base = base;
10356 }
10357
10358 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10359 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10360                                      const struct intel_plane_state *plane_state)
10361 {
10362         struct drm_device *dev = crtc->dev;
10363         struct drm_i915_private *dev_priv = dev->dev_private;
10364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10365         int pipe = intel_crtc->pipe;
10366         u32 base = intel_crtc->cursor_addr;
10367         u32 pos = 0;
10368
10369         if (plane_state) {
10370                 int x = plane_state->base.crtc_x;
10371                 int y = plane_state->base.crtc_y;
10372
10373                 if (x < 0) {
10374                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10375                         x = -x;
10376                 }
10377                 pos |= x << CURSOR_X_SHIFT;
10378
10379                 if (y < 0) {
10380                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10381                         y = -y;
10382                 }
10383                 pos |= y << CURSOR_Y_SHIFT;
10384
10385                 /* ILK+ do this automagically */
10386                 if (HAS_GMCH_DISPLAY(dev) &&
10387                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10388                         base += (plane_state->base.crtc_h *
10389                                  plane_state->base.crtc_w - 1) * 4;
10390                 }
10391         }
10392
10393         I915_WRITE(CURPOS(pipe), pos);
10394
10395         if (IS_845G(dev) || IS_I865G(dev))
10396                 i845_update_cursor(crtc, base, plane_state);
10397         else
10398                 i9xx_update_cursor(crtc, base, plane_state);
10399 }
10400
10401 static bool cursor_size_ok(struct drm_device *dev,
10402                            uint32_t width, uint32_t height)
10403 {
10404         if (width == 0 || height == 0)
10405                 return false;
10406
10407         /*
10408          * 845g/865g are special in that they are only limited by
10409          * the width of their cursors, the height is arbitrary up to
10410          * the precision of the register. Everything else requires
10411          * square cursors, limited to a few power-of-two sizes.
10412          */
10413         if (IS_845G(dev) || IS_I865G(dev)) {
10414                 if ((width & 63) != 0)
10415                         return false;
10416
10417                 if (width > (IS_845G(dev) ? 64 : 512))
10418                         return false;
10419
10420                 if (height > 1023)
10421                         return false;
10422         } else {
10423                 switch (width | height) {
10424                 case 256:
10425                 case 128:
10426                         if (IS_GEN2(dev))
10427                                 return false;
10428                 case 64:
10429                         break;
10430                 default:
10431                         return false;
10432                 }
10433         }
10434
10435         return true;
10436 }
10437
10438 /* VESA 640x480x72Hz mode to set on the pipe */
10439 static struct drm_display_mode load_detect_mode = {
10440         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10441                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10442 };
10443
10444 struct drm_framebuffer *
10445 __intel_framebuffer_create(struct drm_device *dev,
10446                            struct drm_mode_fb_cmd2 *mode_cmd,
10447                            struct drm_i915_gem_object *obj)
10448 {
10449         struct intel_framebuffer *intel_fb;
10450         int ret;
10451
10452         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10453         if (!intel_fb)
10454                 return ERR_PTR(-ENOMEM);
10455
10456         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10457         if (ret)
10458                 goto err;
10459
10460         return &intel_fb->base;
10461
10462 err:
10463         kfree(intel_fb);
10464         return ERR_PTR(ret);
10465 }
10466
10467 static struct drm_framebuffer *
10468 intel_framebuffer_create(struct drm_device *dev,
10469                          struct drm_mode_fb_cmd2 *mode_cmd,
10470                          struct drm_i915_gem_object *obj)
10471 {
10472         struct drm_framebuffer *fb;
10473         int ret;
10474
10475         ret = i915_mutex_lock_interruptible(dev);
10476         if (ret)
10477                 return ERR_PTR(ret);
10478         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10479         mutex_unlock(&dev->struct_mutex);
10480
10481         return fb;
10482 }
10483
10484 static u32
10485 intel_framebuffer_pitch_for_width(int width, int bpp)
10486 {
10487         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10488         return ALIGN(pitch, 64);
10489 }
10490
10491 static u32
10492 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10493 {
10494         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10495         return PAGE_ALIGN(pitch * mode->vdisplay);
10496 }
10497
10498 static struct drm_framebuffer *
10499 intel_framebuffer_create_for_mode(struct drm_device *dev,
10500                                   struct drm_display_mode *mode,
10501                                   int depth, int bpp)
10502 {
10503         struct drm_framebuffer *fb;
10504         struct drm_i915_gem_object *obj;
10505         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10506
10507         obj = i915_gem_object_create(dev,
10508                                     intel_framebuffer_size_for_mode(mode, bpp));
10509         if (IS_ERR(obj))
10510                 return ERR_CAST(obj);
10511
10512         mode_cmd.width = mode->hdisplay;
10513         mode_cmd.height = mode->vdisplay;
10514         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10515                                                                 bpp);
10516         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10517
10518         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10519         if (IS_ERR(fb))
10520                 drm_gem_object_unreference_unlocked(&obj->base);
10521
10522         return fb;
10523 }
10524
10525 static struct drm_framebuffer *
10526 mode_fits_in_fbdev(struct drm_device *dev,
10527                    struct drm_display_mode *mode)
10528 {
10529 #ifdef CONFIG_DRM_FBDEV_EMULATION
10530         struct drm_i915_private *dev_priv = dev->dev_private;
10531         struct drm_i915_gem_object *obj;
10532         struct drm_framebuffer *fb;
10533
10534         if (!dev_priv->fbdev)
10535                 return NULL;
10536
10537         if (!dev_priv->fbdev->fb)
10538                 return NULL;
10539
10540         obj = dev_priv->fbdev->fb->obj;
10541         BUG_ON(!obj);
10542
10543         fb = &dev_priv->fbdev->fb->base;
10544         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10545                                                                fb->bits_per_pixel))
10546                 return NULL;
10547
10548         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10549                 return NULL;
10550
10551         drm_framebuffer_reference(fb);
10552         return fb;
10553 #else
10554         return NULL;
10555 #endif
10556 }
10557
10558 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10559                                            struct drm_crtc *crtc,
10560                                            struct drm_display_mode *mode,
10561                                            struct drm_framebuffer *fb,
10562                                            int x, int y)
10563 {
10564         struct drm_plane_state *plane_state;
10565         int hdisplay, vdisplay;
10566         int ret;
10567
10568         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10569         if (IS_ERR(plane_state))
10570                 return PTR_ERR(plane_state);
10571
10572         if (mode)
10573                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10574         else
10575                 hdisplay = vdisplay = 0;
10576
10577         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10578         if (ret)
10579                 return ret;
10580         drm_atomic_set_fb_for_plane(plane_state, fb);
10581         plane_state->crtc_x = 0;
10582         plane_state->crtc_y = 0;
10583         plane_state->crtc_w = hdisplay;
10584         plane_state->crtc_h = vdisplay;
10585         plane_state->src_x = x << 16;
10586         plane_state->src_y = y << 16;
10587         plane_state->src_w = hdisplay << 16;
10588         plane_state->src_h = vdisplay << 16;
10589
10590         return 0;
10591 }
10592
10593 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10594                                 struct drm_display_mode *mode,
10595                                 struct intel_load_detect_pipe *old,
10596                                 struct drm_modeset_acquire_ctx *ctx)
10597 {
10598         struct intel_crtc *intel_crtc;
10599         struct intel_encoder *intel_encoder =
10600                 intel_attached_encoder(connector);
10601         struct drm_crtc *possible_crtc;
10602         struct drm_encoder *encoder = &intel_encoder->base;
10603         struct drm_crtc *crtc = NULL;
10604         struct drm_device *dev = encoder->dev;
10605         struct drm_framebuffer *fb;
10606         struct drm_mode_config *config = &dev->mode_config;
10607         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10608         struct drm_connector_state *connector_state;
10609         struct intel_crtc_state *crtc_state;
10610         int ret, i = -1;
10611
10612         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10613                       connector->base.id, connector->name,
10614                       encoder->base.id, encoder->name);
10615
10616         old->restore_state = NULL;
10617
10618 retry:
10619         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10620         if (ret)
10621                 goto fail;
10622
10623         /*
10624          * Algorithm gets a little messy:
10625          *
10626          *   - if the connector already has an assigned crtc, use it (but make
10627          *     sure it's on first)
10628          *
10629          *   - try to find the first unused crtc that can drive this connector,
10630          *     and use that if we find one
10631          */
10632
10633         /* See if we already have a CRTC for this connector */
10634         if (connector->state->crtc) {
10635                 crtc = connector->state->crtc;
10636
10637                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10638                 if (ret)
10639                         goto fail;
10640
10641                 /* Make sure the crtc and connector are running */
10642                 goto found;
10643         }
10644
10645         /* Find an unused one (if possible) */
10646         for_each_crtc(dev, possible_crtc) {
10647                 i++;
10648                 if (!(encoder->possible_crtcs & (1 << i)))
10649                         continue;
10650
10651                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10652                 if (ret)
10653                         goto fail;
10654
10655                 if (possible_crtc->state->enable) {
10656                         drm_modeset_unlock(&possible_crtc->mutex);
10657                         continue;
10658                 }
10659
10660                 crtc = possible_crtc;
10661                 break;
10662         }
10663
10664         /*
10665          * If we didn't find an unused CRTC, don't use any.
10666          */
10667         if (!crtc) {
10668                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10669                 goto fail;
10670         }
10671
10672 found:
10673         intel_crtc = to_intel_crtc(crtc);
10674
10675         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10676         if (ret)
10677                 goto fail;
10678
10679         state = drm_atomic_state_alloc(dev);
10680         restore_state = drm_atomic_state_alloc(dev);
10681         if (!state || !restore_state) {
10682                 ret = -ENOMEM;
10683                 goto fail;
10684         }
10685
10686         state->acquire_ctx = ctx;
10687         restore_state->acquire_ctx = ctx;
10688
10689         connector_state = drm_atomic_get_connector_state(state, connector);
10690         if (IS_ERR(connector_state)) {
10691                 ret = PTR_ERR(connector_state);
10692                 goto fail;
10693         }
10694
10695         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10696         if (ret)
10697                 goto fail;
10698
10699         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10700         if (IS_ERR(crtc_state)) {
10701                 ret = PTR_ERR(crtc_state);
10702                 goto fail;
10703         }
10704
10705         crtc_state->base.active = crtc_state->base.enable = true;
10706
10707         if (!mode)
10708                 mode = &load_detect_mode;
10709
10710         /* We need a framebuffer large enough to accommodate all accesses
10711          * that the plane may generate whilst we perform load detection.
10712          * We can not rely on the fbcon either being present (we get called
10713          * during its initialisation to detect all boot displays, or it may
10714          * not even exist) or that it is large enough to satisfy the
10715          * requested mode.
10716          */
10717         fb = mode_fits_in_fbdev(dev, mode);
10718         if (fb == NULL) {
10719                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10720                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10721         } else
10722                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10723         if (IS_ERR(fb)) {
10724                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10725                 goto fail;
10726         }
10727
10728         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10729         if (ret)
10730                 goto fail;
10731
10732         drm_framebuffer_unreference(fb);
10733
10734         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10735         if (ret)
10736                 goto fail;
10737
10738         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10739         if (!ret)
10740                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10741         if (!ret)
10742                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10743         if (ret) {
10744                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10745                 goto fail;
10746         }
10747
10748         ret = drm_atomic_commit(state);
10749         if (ret) {
10750                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10751                 goto fail;
10752         }
10753
10754         old->restore_state = restore_state;
10755
10756         /* let the connector get through one full cycle before testing */
10757         intel_wait_for_vblank(dev, intel_crtc->pipe);
10758         return true;
10759
10760 fail:
10761         drm_atomic_state_free(state);
10762         drm_atomic_state_free(restore_state);
10763         restore_state = state = NULL;
10764
10765         if (ret == -EDEADLK) {
10766                 drm_modeset_backoff(ctx);
10767                 goto retry;
10768         }
10769
10770         return false;
10771 }
10772
10773 void intel_release_load_detect_pipe(struct drm_connector *connector,
10774                                     struct intel_load_detect_pipe *old,
10775                                     struct drm_modeset_acquire_ctx *ctx)
10776 {
10777         struct intel_encoder *intel_encoder =
10778                 intel_attached_encoder(connector);
10779         struct drm_encoder *encoder = &intel_encoder->base;
10780         struct drm_atomic_state *state = old->restore_state;
10781         int ret;
10782
10783         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10784                       connector->base.id, connector->name,
10785                       encoder->base.id, encoder->name);
10786
10787         if (!state)
10788                 return;
10789
10790         ret = drm_atomic_commit(state);
10791         if (ret) {
10792                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10793                 drm_atomic_state_free(state);
10794         }
10795 }
10796
10797 static int i9xx_pll_refclk(struct drm_device *dev,
10798                            const struct intel_crtc_state *pipe_config)
10799 {
10800         struct drm_i915_private *dev_priv = dev->dev_private;
10801         u32 dpll = pipe_config->dpll_hw_state.dpll;
10802
10803         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10804                 return dev_priv->vbt.lvds_ssc_freq;
10805         else if (HAS_PCH_SPLIT(dev))
10806                 return 120000;
10807         else if (!IS_GEN2(dev))
10808                 return 96000;
10809         else
10810                 return 48000;
10811 }
10812
10813 /* Returns the clock of the currently programmed mode of the given pipe. */
10814 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10815                                 struct intel_crtc_state *pipe_config)
10816 {
10817         struct drm_device *dev = crtc->base.dev;
10818         struct drm_i915_private *dev_priv = dev->dev_private;
10819         int pipe = pipe_config->cpu_transcoder;
10820         u32 dpll = pipe_config->dpll_hw_state.dpll;
10821         u32 fp;
10822         struct dpll clock;
10823         int port_clock;
10824         int refclk = i9xx_pll_refclk(dev, pipe_config);
10825
10826         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10827                 fp = pipe_config->dpll_hw_state.fp0;
10828         else
10829                 fp = pipe_config->dpll_hw_state.fp1;
10830
10831         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10832         if (IS_PINEVIEW(dev)) {
10833                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10834                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10835         } else {
10836                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10837                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10838         }
10839
10840         if (!IS_GEN2(dev)) {
10841                 if (IS_PINEVIEW(dev))
10842                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10843                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10844                 else
10845                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10846                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10847
10848                 switch (dpll & DPLL_MODE_MASK) {
10849                 case DPLLB_MODE_DAC_SERIAL:
10850                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10851                                 5 : 10;
10852                         break;
10853                 case DPLLB_MODE_LVDS:
10854                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10855                                 7 : 14;
10856                         break;
10857                 default:
10858                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10859                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10860                         return;
10861                 }
10862
10863                 if (IS_PINEVIEW(dev))
10864                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10865                 else
10866                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10867         } else {
10868                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10869                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10870
10871                 if (is_lvds) {
10872                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10873                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10874
10875                         if (lvds & LVDS_CLKB_POWER_UP)
10876                                 clock.p2 = 7;
10877                         else
10878                                 clock.p2 = 14;
10879                 } else {
10880                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10881                                 clock.p1 = 2;
10882                         else {
10883                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10884                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10885                         }
10886                         if (dpll & PLL_P2_DIVIDE_BY_4)
10887                                 clock.p2 = 4;
10888                         else
10889                                 clock.p2 = 2;
10890                 }
10891
10892                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10893         }
10894
10895         /*
10896          * This value includes pixel_multiplier. We will use
10897          * port_clock to compute adjusted_mode.crtc_clock in the
10898          * encoder's get_config() function.
10899          */
10900         pipe_config->port_clock = port_clock;
10901 }
10902
10903 int intel_dotclock_calculate(int link_freq,
10904                              const struct intel_link_m_n *m_n)
10905 {
10906         /*
10907          * The calculation for the data clock is:
10908          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10909          * But we want to avoid losing precison if possible, so:
10910          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10911          *
10912          * and the link clock is simpler:
10913          * link_clock = (m * link_clock) / n
10914          */
10915
10916         if (!m_n->link_n)
10917                 return 0;
10918
10919         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10920 }
10921
10922 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10923                                    struct intel_crtc_state *pipe_config)
10924 {
10925         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10926
10927         /* read out port_clock from the DPLL */
10928         i9xx_crtc_clock_get(crtc, pipe_config);
10929
10930         /*
10931          * In case there is an active pipe without active ports,
10932          * we may need some idea for the dotclock anyway.
10933          * Calculate one based on the FDI configuration.
10934          */
10935         pipe_config->base.adjusted_mode.crtc_clock =
10936                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10937                                          &pipe_config->fdi_m_n);
10938 }
10939
10940 /** Returns the currently programmed mode of the given pipe. */
10941 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10942                                              struct drm_crtc *crtc)
10943 {
10944         struct drm_i915_private *dev_priv = dev->dev_private;
10945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10946         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10947         struct drm_display_mode *mode;
10948         struct intel_crtc_state *pipe_config;
10949         int htot = I915_READ(HTOTAL(cpu_transcoder));
10950         int hsync = I915_READ(HSYNC(cpu_transcoder));
10951         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10952         int vsync = I915_READ(VSYNC(cpu_transcoder));
10953         enum pipe pipe = intel_crtc->pipe;
10954
10955         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10956         if (!mode)
10957                 return NULL;
10958
10959         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10960         if (!pipe_config) {
10961                 kfree(mode);
10962                 return NULL;
10963         }
10964
10965         /*
10966          * Construct a pipe_config sufficient for getting the clock info
10967          * back out of crtc_clock_get.
10968          *
10969          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10970          * to use a real value here instead.
10971          */
10972         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10973         pipe_config->pixel_multiplier = 1;
10974         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10975         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10976         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10977         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10978
10979         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10980         mode->hdisplay = (htot & 0xffff) + 1;
10981         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10982         mode->hsync_start = (hsync & 0xffff) + 1;
10983         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10984         mode->vdisplay = (vtot & 0xffff) + 1;
10985         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10986         mode->vsync_start = (vsync & 0xffff) + 1;
10987         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10988
10989         drm_mode_set_name(mode);
10990
10991         kfree(pipe_config);
10992
10993         return mode;
10994 }
10995
10996 void intel_mark_busy(struct drm_i915_private *dev_priv)
10997 {
10998         if (dev_priv->mm.busy)
10999                 return;
11000
11001         intel_runtime_pm_get(dev_priv);
11002         i915_update_gfx_val(dev_priv);
11003         if (INTEL_GEN(dev_priv) >= 6)
11004                 gen6_rps_busy(dev_priv);
11005         dev_priv->mm.busy = true;
11006 }
11007
11008 void intel_mark_idle(struct drm_i915_private *dev_priv)
11009 {
11010         if (!dev_priv->mm.busy)
11011                 return;
11012
11013         dev_priv->mm.busy = false;
11014
11015         if (INTEL_GEN(dev_priv) >= 6)
11016                 gen6_rps_idle(dev_priv);
11017
11018         intel_runtime_pm_put(dev_priv);
11019 }
11020
11021 static void intel_crtc_destroy(struct drm_crtc *crtc)
11022 {
11023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11024         struct drm_device *dev = crtc->dev;
11025         struct intel_flip_work *work;
11026
11027         spin_lock_irq(&dev->event_lock);
11028         work = intel_crtc->flip_work;
11029         intel_crtc->flip_work = NULL;
11030         spin_unlock_irq(&dev->event_lock);
11031
11032         if (work) {
11033                 cancel_work_sync(&work->mmio_work);
11034                 cancel_work_sync(&work->unpin_work);
11035                 kfree(work);
11036         }
11037
11038         drm_crtc_cleanup(crtc);
11039
11040         kfree(intel_crtc);
11041 }
11042
11043 static void intel_unpin_work_fn(struct work_struct *__work)
11044 {
11045         struct intel_flip_work *work =
11046                 container_of(__work, struct intel_flip_work, unpin_work);
11047         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11048         struct drm_device *dev = crtc->base.dev;
11049         struct drm_plane *primary = crtc->base.primary;
11050
11051         if (is_mmio_work(work))
11052                 flush_work(&work->mmio_work);
11053
11054         mutex_lock(&dev->struct_mutex);
11055         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11056         drm_gem_object_unreference(&work->pending_flip_obj->base);
11057
11058         if (work->flip_queued_req)
11059                 i915_gem_request_assign(&work->flip_queued_req, NULL);
11060         mutex_unlock(&dev->struct_mutex);
11061
11062         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11063         intel_fbc_post_update(crtc);
11064         drm_framebuffer_unreference(work->old_fb);
11065
11066         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11067         atomic_dec(&crtc->unpin_work_count);
11068
11069         kfree(work);
11070 }
11071
11072 /* Is 'a' after or equal to 'b'? */
11073 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11074 {
11075         return !((a - b) & 0x80000000);
11076 }
11077
11078 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11079                                    struct intel_flip_work *work)
11080 {
11081         struct drm_device *dev = crtc->base.dev;
11082         struct drm_i915_private *dev_priv = dev->dev_private;
11083         unsigned reset_counter;
11084
11085         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11086         if (crtc->reset_counter != reset_counter)
11087                 return true;
11088
11089         /*
11090          * The relevant registers doen't exist on pre-ctg.
11091          * As the flip done interrupt doesn't trigger for mmio
11092          * flips on gmch platforms, a flip count check isn't
11093          * really needed there. But since ctg has the registers,
11094          * include it in the check anyway.
11095          */
11096         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11097                 return true;
11098
11099         /*
11100          * BDW signals flip done immediately if the plane
11101          * is disabled, even if the plane enable is already
11102          * armed to occur at the next vblank :(
11103          */
11104
11105         /*
11106          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11107          * used the same base address. In that case the mmio flip might
11108          * have completed, but the CS hasn't even executed the flip yet.
11109          *
11110          * A flip count check isn't enough as the CS might have updated
11111          * the base address just after start of vblank, but before we
11112          * managed to process the interrupt. This means we'd complete the
11113          * CS flip too soon.
11114          *
11115          * Combining both checks should get us a good enough result. It may
11116          * still happen that the CS flip has been executed, but has not
11117          * yet actually completed. But in case the base address is the same
11118          * anyway, we don't really care.
11119          */
11120         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11121                 crtc->flip_work->gtt_offset &&
11122                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11123                                     crtc->flip_work->flip_count);
11124 }
11125
11126 static bool
11127 __pageflip_finished_mmio(struct intel_crtc *crtc,
11128                                struct intel_flip_work *work)
11129 {
11130         /*
11131          * MMIO work completes when vblank is different from
11132          * flip_queued_vblank.
11133          *
11134          * Reset counter value doesn't matter, this is handled by
11135          * i915_wait_request finishing early, so no need to handle
11136          * reset here.
11137          */
11138         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11139 }
11140
11141
11142 static bool pageflip_finished(struct intel_crtc *crtc,
11143                               struct intel_flip_work *work)
11144 {
11145         if (!atomic_read(&work->pending))
11146                 return false;
11147
11148         smp_rmb();
11149
11150         if (is_mmio_work(work))
11151                 return __pageflip_finished_mmio(crtc, work);
11152         else
11153                 return __pageflip_finished_cs(crtc, work);
11154 }
11155
11156 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11157 {
11158         struct drm_device *dev = dev_priv->dev;
11159         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11161         struct intel_flip_work *work;
11162         unsigned long flags;
11163
11164         /* Ignore early vblank irqs */
11165         if (!crtc)
11166                 return;
11167
11168         /*
11169          * This is called both by irq handlers and the reset code (to complete
11170          * lost pageflips) so needs the full irqsave spinlocks.
11171          */
11172         spin_lock_irqsave(&dev->event_lock, flags);
11173         work = intel_crtc->flip_work;
11174
11175         if (work != NULL &&
11176             !is_mmio_work(work) &&
11177             pageflip_finished(intel_crtc, work))
11178                 page_flip_completed(intel_crtc);
11179
11180         spin_unlock_irqrestore(&dev->event_lock, flags);
11181 }
11182
11183 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11184 {
11185         struct drm_device *dev = dev_priv->dev;
11186         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11188         struct intel_flip_work *work;
11189         unsigned long flags;
11190
11191         /* Ignore early vblank irqs */
11192         if (!crtc)
11193                 return;
11194
11195         /*
11196          * This is called both by irq handlers and the reset code (to complete
11197          * lost pageflips) so needs the full irqsave spinlocks.
11198          */
11199         spin_lock_irqsave(&dev->event_lock, flags);
11200         work = intel_crtc->flip_work;
11201
11202         if (work != NULL &&
11203             is_mmio_work(work) &&
11204             pageflip_finished(intel_crtc, work))
11205                 page_flip_completed(intel_crtc);
11206
11207         spin_unlock_irqrestore(&dev->event_lock, flags);
11208 }
11209
11210 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11211                                                struct intel_flip_work *work)
11212 {
11213         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11214
11215         /* Ensure that the work item is consistent when activating it ... */
11216         smp_mb__before_atomic();
11217         atomic_set(&work->pending, 1);
11218 }
11219
11220 static int intel_gen2_queue_flip(struct drm_device *dev,
11221                                  struct drm_crtc *crtc,
11222                                  struct drm_framebuffer *fb,
11223                                  struct drm_i915_gem_object *obj,
11224                                  struct drm_i915_gem_request *req,
11225                                  uint32_t flags)
11226 {
11227         struct intel_engine_cs *engine = req->engine;
11228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11229         u32 flip_mask;
11230         int ret;
11231
11232         ret = intel_ring_begin(req, 6);
11233         if (ret)
11234                 return ret;
11235
11236         /* Can't queue multiple flips, so wait for the previous
11237          * one to finish before executing the next.
11238          */
11239         if (intel_crtc->plane)
11240                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11241         else
11242                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11243         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11244         intel_ring_emit(engine, MI_NOOP);
11245         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11246                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11247         intel_ring_emit(engine, fb->pitches[0]);
11248         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11249         intel_ring_emit(engine, 0); /* aux display base address, unused */
11250
11251         return 0;
11252 }
11253
11254 static int intel_gen3_queue_flip(struct drm_device *dev,
11255                                  struct drm_crtc *crtc,
11256                                  struct drm_framebuffer *fb,
11257                                  struct drm_i915_gem_object *obj,
11258                                  struct drm_i915_gem_request *req,
11259                                  uint32_t flags)
11260 {
11261         struct intel_engine_cs *engine = req->engine;
11262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11263         u32 flip_mask;
11264         int ret;
11265
11266         ret = intel_ring_begin(req, 6);
11267         if (ret)
11268                 return ret;
11269
11270         if (intel_crtc->plane)
11271                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11272         else
11273                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11274         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11275         intel_ring_emit(engine, MI_NOOP);
11276         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11277                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11278         intel_ring_emit(engine, fb->pitches[0]);
11279         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11280         intel_ring_emit(engine, MI_NOOP);
11281
11282         return 0;
11283 }
11284
11285 static int intel_gen4_queue_flip(struct drm_device *dev,
11286                                  struct drm_crtc *crtc,
11287                                  struct drm_framebuffer *fb,
11288                                  struct drm_i915_gem_object *obj,
11289                                  struct drm_i915_gem_request *req,
11290                                  uint32_t flags)
11291 {
11292         struct intel_engine_cs *engine = req->engine;
11293         struct drm_i915_private *dev_priv = dev->dev_private;
11294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11295         uint32_t pf, pipesrc;
11296         int ret;
11297
11298         ret = intel_ring_begin(req, 4);
11299         if (ret)
11300                 return ret;
11301
11302         /* i965+ uses the linear or tiled offsets from the
11303          * Display Registers (which do not change across a page-flip)
11304          * so we need only reprogram the base address.
11305          */
11306         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11307                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11308         intel_ring_emit(engine, fb->pitches[0]);
11309         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11310                         obj->tiling_mode);
11311
11312         /* XXX Enabling the panel-fitter across page-flip is so far
11313          * untested on non-native modes, so ignore it for now.
11314          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11315          */
11316         pf = 0;
11317         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11318         intel_ring_emit(engine, pf | pipesrc);
11319
11320         return 0;
11321 }
11322
11323 static int intel_gen6_queue_flip(struct drm_device *dev,
11324                                  struct drm_crtc *crtc,
11325                                  struct drm_framebuffer *fb,
11326                                  struct drm_i915_gem_object *obj,
11327                                  struct drm_i915_gem_request *req,
11328                                  uint32_t flags)
11329 {
11330         struct intel_engine_cs *engine = req->engine;
11331         struct drm_i915_private *dev_priv = dev->dev_private;
11332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11333         uint32_t pf, pipesrc;
11334         int ret;
11335
11336         ret = intel_ring_begin(req, 4);
11337         if (ret)
11338                 return ret;
11339
11340         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11341                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11342         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11343         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11344
11345         /* Contrary to the suggestions in the documentation,
11346          * "Enable Panel Fitter" does not seem to be required when page
11347          * flipping with a non-native mode, and worse causes a normal
11348          * modeset to fail.
11349          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11350          */
11351         pf = 0;
11352         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11353         intel_ring_emit(engine, pf | pipesrc);
11354
11355         return 0;
11356 }
11357
11358 static int intel_gen7_queue_flip(struct drm_device *dev,
11359                                  struct drm_crtc *crtc,
11360                                  struct drm_framebuffer *fb,
11361                                  struct drm_i915_gem_object *obj,
11362                                  struct drm_i915_gem_request *req,
11363                                  uint32_t flags)
11364 {
11365         struct intel_engine_cs *engine = req->engine;
11366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11367         uint32_t plane_bit = 0;
11368         int len, ret;
11369
11370         switch (intel_crtc->plane) {
11371         case PLANE_A:
11372                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11373                 break;
11374         case PLANE_B:
11375                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11376                 break;
11377         case PLANE_C:
11378                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11379                 break;
11380         default:
11381                 WARN_ONCE(1, "unknown plane in flip command\n");
11382                 return -ENODEV;
11383         }
11384
11385         len = 4;
11386         if (engine->id == RCS) {
11387                 len += 6;
11388                 /*
11389                  * On Gen 8, SRM is now taking an extra dword to accommodate
11390                  * 48bits addresses, and we need a NOOP for the batch size to
11391                  * stay even.
11392                  */
11393                 if (IS_GEN8(dev))
11394                         len += 2;
11395         }
11396
11397         /*
11398          * BSpec MI_DISPLAY_FLIP for IVB:
11399          * "The full packet must be contained within the same cache line."
11400          *
11401          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11402          * cacheline, if we ever start emitting more commands before
11403          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11404          * then do the cacheline alignment, and finally emit the
11405          * MI_DISPLAY_FLIP.
11406          */
11407         ret = intel_ring_cacheline_align(req);
11408         if (ret)
11409                 return ret;
11410
11411         ret = intel_ring_begin(req, len);
11412         if (ret)
11413                 return ret;
11414
11415         /* Unmask the flip-done completion message. Note that the bspec says that
11416          * we should do this for both the BCS and RCS, and that we must not unmask
11417          * more than one flip event at any time (or ensure that one flip message
11418          * can be sent by waiting for flip-done prior to queueing new flips).
11419          * Experimentation says that BCS works despite DERRMR masking all
11420          * flip-done completion events and that unmasking all planes at once
11421          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11422          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11423          */
11424         if (engine->id == RCS) {
11425                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11426                 intel_ring_emit_reg(engine, DERRMR);
11427                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11428                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11429                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11430                 if (IS_GEN8(dev))
11431                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11432                                               MI_SRM_LRM_GLOBAL_GTT);
11433                 else
11434                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11435                                               MI_SRM_LRM_GLOBAL_GTT);
11436                 intel_ring_emit_reg(engine, DERRMR);
11437                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11438                 if (IS_GEN8(dev)) {
11439                         intel_ring_emit(engine, 0);
11440                         intel_ring_emit(engine, MI_NOOP);
11441                 }
11442         }
11443
11444         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11445         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11446         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11447         intel_ring_emit(engine, (MI_NOOP));
11448
11449         return 0;
11450 }
11451
11452 static bool use_mmio_flip(struct intel_engine_cs *engine,
11453                           struct drm_i915_gem_object *obj)
11454 {
11455         struct reservation_object *resv;
11456
11457         /*
11458          * This is not being used for older platforms, because
11459          * non-availability of flip done interrupt forces us to use
11460          * CS flips. Older platforms derive flip done using some clever
11461          * tricks involving the flip_pending status bits and vblank irqs.
11462          * So using MMIO flips there would disrupt this mechanism.
11463          */
11464
11465         if (engine == NULL)
11466                 return true;
11467
11468         if (INTEL_GEN(engine->i915) < 5)
11469                 return false;
11470
11471         if (i915.use_mmio_flip < 0)
11472                 return false;
11473         else if (i915.use_mmio_flip > 0)
11474                 return true;
11475         else if (i915.enable_execlists)
11476                 return true;
11477
11478         resv = i915_gem_object_get_dmabuf_resv(obj);
11479         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11480                 return true;
11481
11482         return engine != i915_gem_request_get_engine(obj->last_write_req);
11483 }
11484
11485 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11486                              unsigned int rotation,
11487                              struct intel_flip_work *work)
11488 {
11489         struct drm_device *dev = intel_crtc->base.dev;
11490         struct drm_i915_private *dev_priv = dev->dev_private;
11491         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11492         const enum pipe pipe = intel_crtc->pipe;
11493         u32 ctl, stride, tile_height;
11494
11495         ctl = I915_READ(PLANE_CTL(pipe, 0));
11496         ctl &= ~PLANE_CTL_TILED_MASK;
11497         switch (fb->modifier[0]) {
11498         case DRM_FORMAT_MOD_NONE:
11499                 break;
11500         case I915_FORMAT_MOD_X_TILED:
11501                 ctl |= PLANE_CTL_TILED_X;
11502                 break;
11503         case I915_FORMAT_MOD_Y_TILED:
11504                 ctl |= PLANE_CTL_TILED_Y;
11505                 break;
11506         case I915_FORMAT_MOD_Yf_TILED:
11507                 ctl |= PLANE_CTL_TILED_YF;
11508                 break;
11509         default:
11510                 MISSING_CASE(fb->modifier[0]);
11511         }
11512
11513         /*
11514          * The stride is either expressed as a multiple of 64 bytes chunks for
11515          * linear buffers or in number of tiles for tiled buffers.
11516          */
11517         if (intel_rotation_90_or_270(rotation)) {
11518                 /* stride = Surface height in tiles */
11519                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11520                 stride = DIV_ROUND_UP(fb->height, tile_height);
11521         } else {
11522                 stride = fb->pitches[0] /
11523                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11524                                                   fb->pixel_format);
11525         }
11526
11527         /*
11528          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11529          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11530          */
11531         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11532         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11533
11534         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11535         POSTING_READ(PLANE_SURF(pipe, 0));
11536 }
11537
11538 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11539                              struct intel_flip_work *work)
11540 {
11541         struct drm_device *dev = intel_crtc->base.dev;
11542         struct drm_i915_private *dev_priv = dev->dev_private;
11543         struct intel_framebuffer *intel_fb =
11544                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11545         struct drm_i915_gem_object *obj = intel_fb->obj;
11546         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11547         u32 dspcntr;
11548
11549         dspcntr = I915_READ(reg);
11550
11551         if (obj->tiling_mode != I915_TILING_NONE)
11552                 dspcntr |= DISPPLANE_TILED;
11553         else
11554                 dspcntr &= ~DISPPLANE_TILED;
11555
11556         I915_WRITE(reg, dspcntr);
11557
11558         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11559         POSTING_READ(DSPSURF(intel_crtc->plane));
11560 }
11561
11562 static void intel_mmio_flip_work_func(struct work_struct *w)
11563 {
11564         struct intel_flip_work *work =
11565                 container_of(w, struct intel_flip_work, mmio_work);
11566         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11567         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11568         struct intel_framebuffer *intel_fb =
11569                 to_intel_framebuffer(crtc->base.primary->fb);
11570         struct drm_i915_gem_object *obj = intel_fb->obj;
11571         struct reservation_object *resv;
11572
11573         if (work->flip_queued_req)
11574                 WARN_ON(__i915_wait_request(work->flip_queued_req,
11575                                             false, NULL,
11576                                             &dev_priv->rps.mmioflips));
11577
11578         /* For framebuffer backed by dmabuf, wait for fence */
11579         resv = i915_gem_object_get_dmabuf_resv(obj);
11580         if (resv)
11581                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11582                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11583
11584         intel_pipe_update_start(crtc);
11585
11586         if (INTEL_GEN(dev_priv) >= 9)
11587                 skl_do_mmio_flip(crtc, work->rotation, work);
11588         else
11589                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11590                 ilk_do_mmio_flip(crtc, work);
11591
11592         intel_pipe_update_end(crtc, work);
11593 }
11594
11595 static int intel_default_queue_flip(struct drm_device *dev,
11596                                     struct drm_crtc *crtc,
11597                                     struct drm_framebuffer *fb,
11598                                     struct drm_i915_gem_object *obj,
11599                                     struct drm_i915_gem_request *req,
11600                                     uint32_t flags)
11601 {
11602         return -ENODEV;
11603 }
11604
11605 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11606                                       struct intel_crtc *intel_crtc,
11607                                       struct intel_flip_work *work)
11608 {
11609         u32 addr, vblank;
11610
11611         if (!atomic_read(&work->pending))
11612                 return false;
11613
11614         smp_rmb();
11615
11616         vblank = intel_crtc_get_vblank_counter(intel_crtc);
11617         if (work->flip_ready_vblank == 0) {
11618                 if (work->flip_queued_req &&
11619                     !i915_gem_request_completed(work->flip_queued_req, true))
11620                         return false;
11621
11622                 work->flip_ready_vblank = vblank;
11623         }
11624
11625         if (vblank - work->flip_ready_vblank < 3)
11626                 return false;
11627
11628         /* Potential stall - if we see that the flip has happened,
11629          * assume a missed interrupt. */
11630         if (INTEL_GEN(dev_priv) >= 4)
11631                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11632         else
11633                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11634
11635         /* There is a potential issue here with a false positive after a flip
11636          * to the same address. We could address this by checking for a
11637          * non-incrementing frame counter.
11638          */
11639         return addr == work->gtt_offset;
11640 }
11641
11642 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11643 {
11644         struct drm_device *dev = dev_priv->dev;
11645         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11647         struct intel_flip_work *work;
11648
11649         WARN_ON(!in_interrupt());
11650
11651         if (crtc == NULL)
11652                 return;
11653
11654         spin_lock(&dev->event_lock);
11655         work = intel_crtc->flip_work;
11656
11657         if (work != NULL && !is_mmio_work(work) &&
11658             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11659                 WARN_ONCE(1,
11660                           "Kicking stuck page flip: queued at %d, now %d\n",
11661                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11662                 page_flip_completed(intel_crtc);
11663                 work = NULL;
11664         }
11665
11666         if (work != NULL && !is_mmio_work(work) &&
11667             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11668                 intel_queue_rps_boost_for_request(work->flip_queued_req);
11669         spin_unlock(&dev->event_lock);
11670 }
11671
11672 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11673                                 struct drm_framebuffer *fb,
11674                                 struct drm_pending_vblank_event *event,
11675                                 uint32_t page_flip_flags)
11676 {
11677         struct drm_device *dev = crtc->dev;
11678         struct drm_i915_private *dev_priv = dev->dev_private;
11679         struct drm_framebuffer *old_fb = crtc->primary->fb;
11680         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11682         struct drm_plane *primary = crtc->primary;
11683         enum pipe pipe = intel_crtc->pipe;
11684         struct intel_flip_work *work;
11685         struct intel_engine_cs *engine;
11686         bool mmio_flip;
11687         struct drm_i915_gem_request *request = NULL;
11688         int ret;
11689
11690         /*
11691          * drm_mode_page_flip_ioctl() should already catch this, but double
11692          * check to be safe.  In the future we may enable pageflipping from
11693          * a disabled primary plane.
11694          */
11695         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11696                 return -EBUSY;
11697
11698         /* Can't change pixel format via MI display flips. */
11699         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11700                 return -EINVAL;
11701
11702         /*
11703          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11704          * Note that pitch changes could also affect these register.
11705          */
11706         if (INTEL_INFO(dev)->gen > 3 &&
11707             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11708              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11709                 return -EINVAL;
11710
11711         if (i915_terminally_wedged(&dev_priv->gpu_error))
11712                 goto out_hang;
11713
11714         work = kzalloc(sizeof(*work), GFP_KERNEL);
11715         if (work == NULL)
11716                 return -ENOMEM;
11717
11718         work->event = event;
11719         work->crtc = crtc;
11720         work->old_fb = old_fb;
11721         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11722
11723         ret = drm_crtc_vblank_get(crtc);
11724         if (ret)
11725                 goto free_work;
11726
11727         /* We borrow the event spin lock for protecting flip_work */
11728         spin_lock_irq(&dev->event_lock);
11729         if (intel_crtc->flip_work) {
11730                 /* Before declaring the flip queue wedged, check if
11731                  * the hardware completed the operation behind our backs.
11732                  */
11733                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11734                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11735                         page_flip_completed(intel_crtc);
11736                 } else {
11737                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11738                         spin_unlock_irq(&dev->event_lock);
11739
11740                         drm_crtc_vblank_put(crtc);
11741                         kfree(work);
11742                         return -EBUSY;
11743                 }
11744         }
11745         intel_crtc->flip_work = work;
11746         spin_unlock_irq(&dev->event_lock);
11747
11748         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11749                 flush_workqueue(dev_priv->wq);
11750
11751         /* Reference the objects for the scheduled work. */
11752         drm_framebuffer_reference(work->old_fb);
11753         drm_gem_object_reference(&obj->base);
11754
11755         crtc->primary->fb = fb;
11756         update_state_fb(crtc->primary);
11757
11758         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11759                              to_intel_plane_state(primary->state));
11760
11761         work->pending_flip_obj = obj;
11762
11763         ret = i915_mutex_lock_interruptible(dev);
11764         if (ret)
11765                 goto cleanup;
11766
11767         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11768         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11769                 ret = -EIO;
11770                 goto cleanup;
11771         }
11772
11773         atomic_inc(&intel_crtc->unpin_work_count);
11774
11775         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11776                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11777
11778         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11779                 engine = &dev_priv->engine[BCS];
11780                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11781                         /* vlv: DISPLAY_FLIP fails to change tiling */
11782                         engine = NULL;
11783         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11784                 engine = &dev_priv->engine[BCS];
11785         } else if (INTEL_INFO(dev)->gen >= 7) {
11786                 engine = i915_gem_request_get_engine(obj->last_write_req);
11787                 if (engine == NULL || engine->id != RCS)
11788                         engine = &dev_priv->engine[BCS];
11789         } else {
11790                 engine = &dev_priv->engine[RCS];
11791         }
11792
11793         mmio_flip = use_mmio_flip(engine, obj);
11794
11795         /* When using CS flips, we want to emit semaphores between rings.
11796          * However, when using mmio flips we will create a task to do the
11797          * synchronisation, so all we want here is to pin the framebuffer
11798          * into the display plane and skip any waits.
11799          */
11800         if (!mmio_flip) {
11801                 ret = i915_gem_object_sync(obj, engine, &request);
11802                 if (!ret && !request) {
11803                         request = i915_gem_request_alloc(engine, NULL);
11804                         ret = PTR_ERR_OR_ZERO(request);
11805                 }
11806
11807                 if (ret)
11808                         goto cleanup_pending;
11809         }
11810
11811         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11812         if (ret)
11813                 goto cleanup_pending;
11814
11815         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11816                                                   obj, 0);
11817         work->gtt_offset += intel_crtc->dspaddr_offset;
11818         work->rotation = crtc->primary->state->rotation;
11819
11820         if (mmio_flip) {
11821                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11822
11823                 i915_gem_request_assign(&work->flip_queued_req,
11824                                         obj->last_write_req);
11825
11826                 schedule_work(&work->mmio_work);
11827         } else {
11828                 i915_gem_request_assign(&work->flip_queued_req, request);
11829                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11830                                                    page_flip_flags);
11831                 if (ret)
11832                         goto cleanup_unpin;
11833
11834                 intel_mark_page_flip_active(intel_crtc, work);
11835
11836                 i915_add_request_no_flush(request);
11837         }
11838
11839         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11840                           to_intel_plane(primary)->frontbuffer_bit);
11841         mutex_unlock(&dev->struct_mutex);
11842
11843         intel_frontbuffer_flip_prepare(dev,
11844                                        to_intel_plane(primary)->frontbuffer_bit);
11845
11846         trace_i915_flip_request(intel_crtc->plane, obj);
11847
11848         return 0;
11849
11850 cleanup_unpin:
11851         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11852 cleanup_pending:
11853         if (!IS_ERR_OR_NULL(request))
11854                 i915_add_request_no_flush(request);
11855         atomic_dec(&intel_crtc->unpin_work_count);
11856         mutex_unlock(&dev->struct_mutex);
11857 cleanup:
11858         crtc->primary->fb = old_fb;
11859         update_state_fb(crtc->primary);
11860
11861         drm_gem_object_unreference_unlocked(&obj->base);
11862         drm_framebuffer_unreference(work->old_fb);
11863
11864         spin_lock_irq(&dev->event_lock);
11865         intel_crtc->flip_work = NULL;
11866         spin_unlock_irq(&dev->event_lock);
11867
11868         drm_crtc_vblank_put(crtc);
11869 free_work:
11870         kfree(work);
11871
11872         if (ret == -EIO) {
11873                 struct drm_atomic_state *state;
11874                 struct drm_plane_state *plane_state;
11875
11876 out_hang:
11877                 state = drm_atomic_state_alloc(dev);
11878                 if (!state)
11879                         return -ENOMEM;
11880                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11881
11882 retry:
11883                 plane_state = drm_atomic_get_plane_state(state, primary);
11884                 ret = PTR_ERR_OR_ZERO(plane_state);
11885                 if (!ret) {
11886                         drm_atomic_set_fb_for_plane(plane_state, fb);
11887
11888                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11889                         if (!ret)
11890                                 ret = drm_atomic_commit(state);
11891                 }
11892
11893                 if (ret == -EDEADLK) {
11894                         drm_modeset_backoff(state->acquire_ctx);
11895                         drm_atomic_state_clear(state);
11896                         goto retry;
11897                 }
11898
11899                 if (ret)
11900                         drm_atomic_state_free(state);
11901
11902                 if (ret == 0 && event) {
11903                         spin_lock_irq(&dev->event_lock);
11904                         drm_crtc_send_vblank_event(crtc, event);
11905                         spin_unlock_irq(&dev->event_lock);
11906                 }
11907         }
11908         return ret;
11909 }
11910
11911
11912 /**
11913  * intel_wm_need_update - Check whether watermarks need updating
11914  * @plane: drm plane
11915  * @state: new plane state
11916  *
11917  * Check current plane state versus the new one to determine whether
11918  * watermarks need to be recalculated.
11919  *
11920  * Returns true or false.
11921  */
11922 static bool intel_wm_need_update(struct drm_plane *plane,
11923                                  struct drm_plane_state *state)
11924 {
11925         struct intel_plane_state *new = to_intel_plane_state(state);
11926         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11927
11928         /* Update watermarks on tiling or size changes. */
11929         if (new->visible != cur->visible)
11930                 return true;
11931
11932         if (!cur->base.fb || !new->base.fb)
11933                 return false;
11934
11935         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11936             cur->base.rotation != new->base.rotation ||
11937             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11938             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11939             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11940             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11941                 return true;
11942
11943         return false;
11944 }
11945
11946 static bool needs_scaling(struct intel_plane_state *state)
11947 {
11948         int src_w = drm_rect_width(&state->src) >> 16;
11949         int src_h = drm_rect_height(&state->src) >> 16;
11950         int dst_w = drm_rect_width(&state->dst);
11951         int dst_h = drm_rect_height(&state->dst);
11952
11953         return (src_w != dst_w || src_h != dst_h);
11954 }
11955
11956 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11957                                     struct drm_plane_state *plane_state)
11958 {
11959         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11960         struct drm_crtc *crtc = crtc_state->crtc;
11961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11962         struct drm_plane *plane = plane_state->plane;
11963         struct drm_device *dev = crtc->dev;
11964         struct drm_i915_private *dev_priv = to_i915(dev);
11965         struct intel_plane_state *old_plane_state =
11966                 to_intel_plane_state(plane->state);
11967         bool mode_changed = needs_modeset(crtc_state);
11968         bool was_crtc_enabled = crtc->state->active;
11969         bool is_crtc_enabled = crtc_state->active;
11970         bool turn_off, turn_on, visible, was_visible;
11971         struct drm_framebuffer *fb = plane_state->fb;
11972         int ret;
11973
11974         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11975             plane->type != DRM_PLANE_TYPE_CURSOR) {
11976                 ret = skl_update_scaler_plane(
11977                         to_intel_crtc_state(crtc_state),
11978                         to_intel_plane_state(plane_state));
11979                 if (ret)
11980                         return ret;
11981         }
11982
11983         was_visible = old_plane_state->visible;
11984         visible = to_intel_plane_state(plane_state)->visible;
11985
11986         if (!was_crtc_enabled && WARN_ON(was_visible))
11987                 was_visible = false;
11988
11989         /*
11990          * Visibility is calculated as if the crtc was on, but
11991          * after scaler setup everything depends on it being off
11992          * when the crtc isn't active.
11993          *
11994          * FIXME this is wrong for watermarks. Watermarks should also
11995          * be computed as if the pipe would be active. Perhaps move
11996          * per-plane wm computation to the .check_plane() hook, and
11997          * only combine the results from all planes in the current place?
11998          */
11999         if (!is_crtc_enabled)
12000                 to_intel_plane_state(plane_state)->visible = visible = false;
12001
12002         if (!was_visible && !visible)
12003                 return 0;
12004
12005         if (fb != old_plane_state->base.fb)
12006                 pipe_config->fb_changed = true;
12007
12008         turn_off = was_visible && (!visible || mode_changed);
12009         turn_on = visible && (!was_visible || mode_changed);
12010
12011         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12012                          intel_crtc->base.base.id,
12013                          intel_crtc->base.name,
12014                          plane->base.id, plane->name,
12015                          fb ? fb->base.id : -1);
12016
12017         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12018                          plane->base.id, plane->name,
12019                          was_visible, visible,
12020                          turn_off, turn_on, mode_changed);
12021
12022         if (turn_on) {
12023                 pipe_config->update_wm_pre = true;
12024
12025                 /* must disable cxsr around plane enable/disable */
12026                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12027                         pipe_config->disable_cxsr = true;
12028         } else if (turn_off) {
12029                 pipe_config->update_wm_post = true;
12030
12031                 /* must disable cxsr around plane enable/disable */
12032                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12033                         pipe_config->disable_cxsr = true;
12034         } else if (intel_wm_need_update(plane, plane_state)) {
12035                 /* FIXME bollocks */
12036                 pipe_config->update_wm_pre = true;
12037                 pipe_config->update_wm_post = true;
12038         }
12039
12040         /* Pre-gen9 platforms need two-step watermark updates */
12041         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12042             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12043                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12044
12045         if (visible || was_visible)
12046                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12047
12048         /*
12049          * WaCxSRDisabledForSpriteScaling:ivb
12050          *
12051          * cstate->update_wm was already set above, so this flag will
12052          * take effect when we commit and program watermarks.
12053          */
12054         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12055             needs_scaling(to_intel_plane_state(plane_state)) &&
12056             !needs_scaling(old_plane_state))
12057                 pipe_config->disable_lp_wm = true;
12058
12059         return 0;
12060 }
12061
12062 static bool encoders_cloneable(const struct intel_encoder *a,
12063                                const struct intel_encoder *b)
12064 {
12065         /* masks could be asymmetric, so check both ways */
12066         return a == b || (a->cloneable & (1 << b->type) &&
12067                           b->cloneable & (1 << a->type));
12068 }
12069
12070 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12071                                          struct intel_crtc *crtc,
12072                                          struct intel_encoder *encoder)
12073 {
12074         struct intel_encoder *source_encoder;
12075         struct drm_connector *connector;
12076         struct drm_connector_state *connector_state;
12077         int i;
12078
12079         for_each_connector_in_state(state, connector, connector_state, i) {
12080                 if (connector_state->crtc != &crtc->base)
12081                         continue;
12082
12083                 source_encoder =
12084                         to_intel_encoder(connector_state->best_encoder);
12085                 if (!encoders_cloneable(encoder, source_encoder))
12086                         return false;
12087         }
12088
12089         return true;
12090 }
12091
12092 static bool check_encoder_cloning(struct drm_atomic_state *state,
12093                                   struct intel_crtc *crtc)
12094 {
12095         struct intel_encoder *encoder;
12096         struct drm_connector *connector;
12097         struct drm_connector_state *connector_state;
12098         int i;
12099
12100         for_each_connector_in_state(state, connector, connector_state, i) {
12101                 if (connector_state->crtc != &crtc->base)
12102                         continue;
12103
12104                 encoder = to_intel_encoder(connector_state->best_encoder);
12105                 if (!check_single_encoder_cloning(state, crtc, encoder))
12106                         return false;
12107         }
12108
12109         return true;
12110 }
12111
12112 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12113                                    struct drm_crtc_state *crtc_state)
12114 {
12115         struct drm_device *dev = crtc->dev;
12116         struct drm_i915_private *dev_priv = dev->dev_private;
12117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12118         struct intel_crtc_state *pipe_config =
12119                 to_intel_crtc_state(crtc_state);
12120         struct drm_atomic_state *state = crtc_state->state;
12121         int ret;
12122         bool mode_changed = needs_modeset(crtc_state);
12123
12124         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12125                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12126                 return -EINVAL;
12127         }
12128
12129         if (mode_changed && !crtc_state->active)
12130                 pipe_config->update_wm_post = true;
12131
12132         if (mode_changed && crtc_state->enable &&
12133             dev_priv->display.crtc_compute_clock &&
12134             !WARN_ON(pipe_config->shared_dpll)) {
12135                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12136                                                            pipe_config);
12137                 if (ret)
12138                         return ret;
12139         }
12140
12141         if (crtc_state->color_mgmt_changed) {
12142                 ret = intel_color_check(crtc, crtc_state);
12143                 if (ret)
12144                         return ret;
12145         }
12146
12147         ret = 0;
12148         if (dev_priv->display.compute_pipe_wm) {
12149                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12150                 if (ret) {
12151                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12152                         return ret;
12153                 }
12154         }
12155
12156         if (dev_priv->display.compute_intermediate_wm &&
12157             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12158                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12159                         return 0;
12160
12161                 /*
12162                  * Calculate 'intermediate' watermarks that satisfy both the
12163                  * old state and the new state.  We can program these
12164                  * immediately.
12165                  */
12166                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12167                                                                 intel_crtc,
12168                                                                 pipe_config);
12169                 if (ret) {
12170                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12171                         return ret;
12172                 }
12173         } else if (dev_priv->display.compute_intermediate_wm) {
12174                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12175                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12176         }
12177
12178         if (INTEL_INFO(dev)->gen >= 9) {
12179                 if (mode_changed)
12180                         ret = skl_update_scaler_crtc(pipe_config);
12181
12182                 if (!ret)
12183                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12184                                                          pipe_config);
12185         }
12186
12187         return ret;
12188 }
12189
12190 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12191         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12192         .atomic_begin = intel_begin_crtc_commit,
12193         .atomic_flush = intel_finish_crtc_commit,
12194         .atomic_check = intel_crtc_atomic_check,
12195 };
12196
12197 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12198 {
12199         struct intel_connector *connector;
12200
12201         for_each_intel_connector(dev, connector) {
12202                 if (connector->base.state->crtc)
12203                         drm_connector_unreference(&connector->base);
12204
12205                 if (connector->base.encoder) {
12206                         connector->base.state->best_encoder =
12207                                 connector->base.encoder;
12208                         connector->base.state->crtc =
12209                                 connector->base.encoder->crtc;
12210
12211                         drm_connector_reference(&connector->base);
12212                 } else {
12213                         connector->base.state->best_encoder = NULL;
12214                         connector->base.state->crtc = NULL;
12215                 }
12216         }
12217 }
12218
12219 static void
12220 connected_sink_compute_bpp(struct intel_connector *connector,
12221                            struct intel_crtc_state *pipe_config)
12222 {
12223         int bpp = pipe_config->pipe_bpp;
12224
12225         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12226                 connector->base.base.id,
12227                 connector->base.name);
12228
12229         /* Don't use an invalid EDID bpc value */
12230         if (connector->base.display_info.bpc &&
12231             connector->base.display_info.bpc * 3 < bpp) {
12232                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12233                               bpp, connector->base.display_info.bpc*3);
12234                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12235         }
12236
12237         /* Clamp bpp to default limit on screens without EDID 1.4 */
12238         if (connector->base.display_info.bpc == 0) {
12239                 int type = connector->base.connector_type;
12240                 int clamp_bpp = 24;
12241
12242                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12243                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12244                     type == DRM_MODE_CONNECTOR_eDP)
12245                         clamp_bpp = 18;
12246
12247                 if (bpp > clamp_bpp) {
12248                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12249                                       bpp, clamp_bpp);
12250                         pipe_config->pipe_bpp = clamp_bpp;
12251                 }
12252         }
12253 }
12254
12255 static int
12256 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12257                           struct intel_crtc_state *pipe_config)
12258 {
12259         struct drm_device *dev = crtc->base.dev;
12260         struct drm_atomic_state *state;
12261         struct drm_connector *connector;
12262         struct drm_connector_state *connector_state;
12263         int bpp, i;
12264
12265         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12266                 bpp = 10*3;
12267         else if (INTEL_INFO(dev)->gen >= 5)
12268                 bpp = 12*3;
12269         else
12270                 bpp = 8*3;
12271
12272
12273         pipe_config->pipe_bpp = bpp;
12274
12275         state = pipe_config->base.state;
12276
12277         /* Clamp display bpp to EDID value */
12278         for_each_connector_in_state(state, connector, connector_state, i) {
12279                 if (connector_state->crtc != &crtc->base)
12280                         continue;
12281
12282                 connected_sink_compute_bpp(to_intel_connector(connector),
12283                                            pipe_config);
12284         }
12285
12286         return bpp;
12287 }
12288
12289 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12290 {
12291         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12292                         "type: 0x%x flags: 0x%x\n",
12293                 mode->crtc_clock,
12294                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12295                 mode->crtc_hsync_end, mode->crtc_htotal,
12296                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12297                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12298 }
12299
12300 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12301                                    struct intel_crtc_state *pipe_config,
12302                                    const char *context)
12303 {
12304         struct drm_device *dev = crtc->base.dev;
12305         struct drm_plane *plane;
12306         struct intel_plane *intel_plane;
12307         struct intel_plane_state *state;
12308         struct drm_framebuffer *fb;
12309
12310         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12311                       crtc->base.base.id, crtc->base.name,
12312                       context, pipe_config, pipe_name(crtc->pipe));
12313
12314         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12315         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12316                       pipe_config->pipe_bpp, pipe_config->dither);
12317         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12318                       pipe_config->has_pch_encoder,
12319                       pipe_config->fdi_lanes,
12320                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12321                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12322                       pipe_config->fdi_m_n.tu);
12323         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12324                       pipe_config->has_dp_encoder,
12325                       pipe_config->lane_count,
12326                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12327                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12328                       pipe_config->dp_m_n.tu);
12329
12330         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12331                       pipe_config->has_dp_encoder,
12332                       pipe_config->lane_count,
12333                       pipe_config->dp_m2_n2.gmch_m,
12334                       pipe_config->dp_m2_n2.gmch_n,
12335                       pipe_config->dp_m2_n2.link_m,
12336                       pipe_config->dp_m2_n2.link_n,
12337                       pipe_config->dp_m2_n2.tu);
12338
12339         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12340                       pipe_config->has_audio,
12341                       pipe_config->has_infoframe);
12342
12343         DRM_DEBUG_KMS("requested mode:\n");
12344         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12345         DRM_DEBUG_KMS("adjusted mode:\n");
12346         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12347         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12348         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12349         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12350                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12351         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12352                       crtc->num_scalers,
12353                       pipe_config->scaler_state.scaler_users,
12354                       pipe_config->scaler_state.scaler_id);
12355         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12356                       pipe_config->gmch_pfit.control,
12357                       pipe_config->gmch_pfit.pgm_ratios,
12358                       pipe_config->gmch_pfit.lvds_border_bits);
12359         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12360                       pipe_config->pch_pfit.pos,
12361                       pipe_config->pch_pfit.size,
12362                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12363         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12364         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12365
12366         if (IS_BROXTON(dev)) {
12367                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12368                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12369                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12370                               pipe_config->ddi_pll_sel,
12371                               pipe_config->dpll_hw_state.ebb0,
12372                               pipe_config->dpll_hw_state.ebb4,
12373                               pipe_config->dpll_hw_state.pll0,
12374                               pipe_config->dpll_hw_state.pll1,
12375                               pipe_config->dpll_hw_state.pll2,
12376                               pipe_config->dpll_hw_state.pll3,
12377                               pipe_config->dpll_hw_state.pll6,
12378                               pipe_config->dpll_hw_state.pll8,
12379                               pipe_config->dpll_hw_state.pll9,
12380                               pipe_config->dpll_hw_state.pll10,
12381                               pipe_config->dpll_hw_state.pcsdw12);
12382         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12383                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12384                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12385                               pipe_config->ddi_pll_sel,
12386                               pipe_config->dpll_hw_state.ctrl1,
12387                               pipe_config->dpll_hw_state.cfgcr1,
12388                               pipe_config->dpll_hw_state.cfgcr2);
12389         } else if (HAS_DDI(dev)) {
12390                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12391                               pipe_config->ddi_pll_sel,
12392                               pipe_config->dpll_hw_state.wrpll,
12393                               pipe_config->dpll_hw_state.spll);
12394         } else {
12395                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12396                               "fp0: 0x%x, fp1: 0x%x\n",
12397                               pipe_config->dpll_hw_state.dpll,
12398                               pipe_config->dpll_hw_state.dpll_md,
12399                               pipe_config->dpll_hw_state.fp0,
12400                               pipe_config->dpll_hw_state.fp1);
12401         }
12402
12403         DRM_DEBUG_KMS("planes on this crtc\n");
12404         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12405                 intel_plane = to_intel_plane(plane);
12406                 if (intel_plane->pipe != crtc->pipe)
12407                         continue;
12408
12409                 state = to_intel_plane_state(plane->state);
12410                 fb = state->base.fb;
12411                 if (!fb) {
12412                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12413                                       plane->base.id, plane->name, state->scaler_id);
12414                         continue;
12415                 }
12416
12417                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12418                               plane->base.id, plane->name);
12419                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12420                               fb->base.id, fb->width, fb->height,
12421                               drm_get_format_name(fb->pixel_format));
12422                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12423                               state->scaler_id,
12424                               state->src.x1 >> 16, state->src.y1 >> 16,
12425                               drm_rect_width(&state->src) >> 16,
12426                               drm_rect_height(&state->src) >> 16,
12427                               state->dst.x1, state->dst.y1,
12428                               drm_rect_width(&state->dst),
12429                               drm_rect_height(&state->dst));
12430         }
12431 }
12432
12433 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12434 {
12435         struct drm_device *dev = state->dev;
12436         struct drm_connector *connector;
12437         unsigned int used_ports = 0;
12438
12439         /*
12440          * Walk the connector list instead of the encoder
12441          * list to detect the problem on ddi platforms
12442          * where there's just one encoder per digital port.
12443          */
12444         drm_for_each_connector(connector, dev) {
12445                 struct drm_connector_state *connector_state;
12446                 struct intel_encoder *encoder;
12447
12448                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12449                 if (!connector_state)
12450                         connector_state = connector->state;
12451
12452                 if (!connector_state->best_encoder)
12453                         continue;
12454
12455                 encoder = to_intel_encoder(connector_state->best_encoder);
12456
12457                 WARN_ON(!connector_state->crtc);
12458
12459                 switch (encoder->type) {
12460                         unsigned int port_mask;
12461                 case INTEL_OUTPUT_UNKNOWN:
12462                         if (WARN_ON(!HAS_DDI(dev)))
12463                                 break;
12464                 case INTEL_OUTPUT_DISPLAYPORT:
12465                 case INTEL_OUTPUT_HDMI:
12466                 case INTEL_OUTPUT_EDP:
12467                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12468
12469                         /* the same port mustn't appear more than once */
12470                         if (used_ports & port_mask)
12471                                 return false;
12472
12473                         used_ports |= port_mask;
12474                 default:
12475                         break;
12476                 }
12477         }
12478
12479         return true;
12480 }
12481
12482 static void
12483 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12484 {
12485         struct drm_crtc_state tmp_state;
12486         struct intel_crtc_scaler_state scaler_state;
12487         struct intel_dpll_hw_state dpll_hw_state;
12488         struct intel_shared_dpll *shared_dpll;
12489         uint32_t ddi_pll_sel;
12490         bool force_thru;
12491
12492         /* FIXME: before the switch to atomic started, a new pipe_config was
12493          * kzalloc'd. Code that depends on any field being zero should be
12494          * fixed, so that the crtc_state can be safely duplicated. For now,
12495          * only fields that are know to not cause problems are preserved. */
12496
12497         tmp_state = crtc_state->base;
12498         scaler_state = crtc_state->scaler_state;
12499         shared_dpll = crtc_state->shared_dpll;
12500         dpll_hw_state = crtc_state->dpll_hw_state;
12501         ddi_pll_sel = crtc_state->ddi_pll_sel;
12502         force_thru = crtc_state->pch_pfit.force_thru;
12503
12504         memset(crtc_state, 0, sizeof *crtc_state);
12505
12506         crtc_state->base = tmp_state;
12507         crtc_state->scaler_state = scaler_state;
12508         crtc_state->shared_dpll = shared_dpll;
12509         crtc_state->dpll_hw_state = dpll_hw_state;
12510         crtc_state->ddi_pll_sel = ddi_pll_sel;
12511         crtc_state->pch_pfit.force_thru = force_thru;
12512 }
12513
12514 static int
12515 intel_modeset_pipe_config(struct drm_crtc *crtc,
12516                           struct intel_crtc_state *pipe_config)
12517 {
12518         struct drm_atomic_state *state = pipe_config->base.state;
12519         struct intel_encoder *encoder;
12520         struct drm_connector *connector;
12521         struct drm_connector_state *connector_state;
12522         int base_bpp, ret = -EINVAL;
12523         int i;
12524         bool retry = true;
12525
12526         clear_intel_crtc_state(pipe_config);
12527
12528         pipe_config->cpu_transcoder =
12529                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12530
12531         /*
12532          * Sanitize sync polarity flags based on requested ones. If neither
12533          * positive or negative polarity is requested, treat this as meaning
12534          * negative polarity.
12535          */
12536         if (!(pipe_config->base.adjusted_mode.flags &
12537               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12538                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12539
12540         if (!(pipe_config->base.adjusted_mode.flags &
12541               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12542                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12543
12544         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12545                                              pipe_config);
12546         if (base_bpp < 0)
12547                 goto fail;
12548
12549         /*
12550          * Determine the real pipe dimensions. Note that stereo modes can
12551          * increase the actual pipe size due to the frame doubling and
12552          * insertion of additional space for blanks between the frame. This
12553          * is stored in the crtc timings. We use the requested mode to do this
12554          * computation to clearly distinguish it from the adjusted mode, which
12555          * can be changed by the connectors in the below retry loop.
12556          */
12557         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12558                                &pipe_config->pipe_src_w,
12559                                &pipe_config->pipe_src_h);
12560
12561 encoder_retry:
12562         /* Ensure the port clock defaults are reset when retrying. */
12563         pipe_config->port_clock = 0;
12564         pipe_config->pixel_multiplier = 1;
12565
12566         /* Fill in default crtc timings, allow encoders to overwrite them. */
12567         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12568                               CRTC_STEREO_DOUBLE);
12569
12570         /* Pass our mode to the connectors and the CRTC to give them a chance to
12571          * adjust it according to limitations or connector properties, and also
12572          * a chance to reject the mode entirely.
12573          */
12574         for_each_connector_in_state(state, connector, connector_state, i) {
12575                 if (connector_state->crtc != crtc)
12576                         continue;
12577
12578                 encoder = to_intel_encoder(connector_state->best_encoder);
12579
12580                 if (!(encoder->compute_config(encoder, pipe_config))) {
12581                         DRM_DEBUG_KMS("Encoder config failure\n");
12582                         goto fail;
12583                 }
12584         }
12585
12586         /* Set default port clock if not overwritten by the encoder. Needs to be
12587          * done afterwards in case the encoder adjusts the mode. */
12588         if (!pipe_config->port_clock)
12589                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12590                         * pipe_config->pixel_multiplier;
12591
12592         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12593         if (ret < 0) {
12594                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12595                 goto fail;
12596         }
12597
12598         if (ret == RETRY) {
12599                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12600                         ret = -EINVAL;
12601                         goto fail;
12602                 }
12603
12604                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12605                 retry = false;
12606                 goto encoder_retry;
12607         }
12608
12609         /* Dithering seems to not pass-through bits correctly when it should, so
12610          * only enable it on 6bpc panels. */
12611         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12612         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12613                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12614
12615 fail:
12616         return ret;
12617 }
12618
12619 static void
12620 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12621 {
12622         struct drm_crtc *crtc;
12623         struct drm_crtc_state *crtc_state;
12624         int i;
12625
12626         /* Double check state. */
12627         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12628                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12629
12630                 /* Update hwmode for vblank functions */
12631                 if (crtc->state->active)
12632                         crtc->hwmode = crtc->state->adjusted_mode;
12633                 else
12634                         crtc->hwmode.crtc_clock = 0;
12635
12636                 /*
12637                  * Update legacy state to satisfy fbc code. This can
12638                  * be removed when fbc uses the atomic state.
12639                  */
12640                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12641                         struct drm_plane_state *plane_state = crtc->primary->state;
12642
12643                         crtc->primary->fb = plane_state->fb;
12644                         crtc->x = plane_state->src_x >> 16;
12645                         crtc->y = plane_state->src_y >> 16;
12646                 }
12647         }
12648 }
12649
12650 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12651 {
12652         int diff;
12653
12654         if (clock1 == clock2)
12655                 return true;
12656
12657         if (!clock1 || !clock2)
12658                 return false;
12659
12660         diff = abs(clock1 - clock2);
12661
12662         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12663                 return true;
12664
12665         return false;
12666 }
12667
12668 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12669         list_for_each_entry((intel_crtc), \
12670                             &(dev)->mode_config.crtc_list, \
12671                             base.head) \
12672                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12673
12674 static bool
12675 intel_compare_m_n(unsigned int m, unsigned int n,
12676                   unsigned int m2, unsigned int n2,
12677                   bool exact)
12678 {
12679         if (m == m2 && n == n2)
12680                 return true;
12681
12682         if (exact || !m || !n || !m2 || !n2)
12683                 return false;
12684
12685         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12686
12687         if (n > n2) {
12688                 while (n > n2) {
12689                         m2 <<= 1;
12690                         n2 <<= 1;
12691                 }
12692         } else if (n < n2) {
12693                 while (n < n2) {
12694                         m <<= 1;
12695                         n <<= 1;
12696                 }
12697         }
12698
12699         if (n != n2)
12700                 return false;
12701
12702         return intel_fuzzy_clock_check(m, m2);
12703 }
12704
12705 static bool
12706 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12707                        struct intel_link_m_n *m2_n2,
12708                        bool adjust)
12709 {
12710         if (m_n->tu == m2_n2->tu &&
12711             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12712                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12713             intel_compare_m_n(m_n->link_m, m_n->link_n,
12714                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12715                 if (adjust)
12716                         *m2_n2 = *m_n;
12717
12718                 return true;
12719         }
12720
12721         return false;
12722 }
12723
12724 static bool
12725 intel_pipe_config_compare(struct drm_device *dev,
12726                           struct intel_crtc_state *current_config,
12727                           struct intel_crtc_state *pipe_config,
12728                           bool adjust)
12729 {
12730         bool ret = true;
12731
12732 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12733         do { \
12734                 if (!adjust) \
12735                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12736                 else \
12737                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12738         } while (0)
12739
12740 #define PIPE_CONF_CHECK_X(name) \
12741         if (current_config->name != pipe_config->name) { \
12742                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12743                           "(expected 0x%08x, found 0x%08x)\n", \
12744                           current_config->name, \
12745                           pipe_config->name); \
12746                 ret = false; \
12747         }
12748
12749 #define PIPE_CONF_CHECK_I(name) \
12750         if (current_config->name != pipe_config->name) { \
12751                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12752                           "(expected %i, found %i)\n", \
12753                           current_config->name, \
12754                           pipe_config->name); \
12755                 ret = false; \
12756         }
12757
12758 #define PIPE_CONF_CHECK_P(name) \
12759         if (current_config->name != pipe_config->name) { \
12760                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12761                           "(expected %p, found %p)\n", \
12762                           current_config->name, \
12763                           pipe_config->name); \
12764                 ret = false; \
12765         }
12766
12767 #define PIPE_CONF_CHECK_M_N(name) \
12768         if (!intel_compare_link_m_n(&current_config->name, \
12769                                     &pipe_config->name,\
12770                                     adjust)) { \
12771                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12772                           "(expected tu %i gmch %i/%i link %i/%i, " \
12773                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12774                           current_config->name.tu, \
12775                           current_config->name.gmch_m, \
12776                           current_config->name.gmch_n, \
12777                           current_config->name.link_m, \
12778                           current_config->name.link_n, \
12779                           pipe_config->name.tu, \
12780                           pipe_config->name.gmch_m, \
12781                           pipe_config->name.gmch_n, \
12782                           pipe_config->name.link_m, \
12783                           pipe_config->name.link_n); \
12784                 ret = false; \
12785         }
12786
12787 /* This is required for BDW+ where there is only one set of registers for
12788  * switching between high and low RR.
12789  * This macro can be used whenever a comparison has to be made between one
12790  * hw state and multiple sw state variables.
12791  */
12792 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12793         if (!intel_compare_link_m_n(&current_config->name, \
12794                                     &pipe_config->name, adjust) && \
12795             !intel_compare_link_m_n(&current_config->alt_name, \
12796                                     &pipe_config->name, adjust)) { \
12797                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12798                           "(expected tu %i gmch %i/%i link %i/%i, " \
12799                           "or tu %i gmch %i/%i link %i/%i, " \
12800                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12801                           current_config->name.tu, \
12802                           current_config->name.gmch_m, \
12803                           current_config->name.gmch_n, \
12804                           current_config->name.link_m, \
12805                           current_config->name.link_n, \
12806                           current_config->alt_name.tu, \
12807                           current_config->alt_name.gmch_m, \
12808                           current_config->alt_name.gmch_n, \
12809                           current_config->alt_name.link_m, \
12810                           current_config->alt_name.link_n, \
12811                           pipe_config->name.tu, \
12812                           pipe_config->name.gmch_m, \
12813                           pipe_config->name.gmch_n, \
12814                           pipe_config->name.link_m, \
12815                           pipe_config->name.link_n); \
12816                 ret = false; \
12817         }
12818
12819 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12820         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12821                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12822                           "(expected %i, found %i)\n", \
12823                           current_config->name & (mask), \
12824                           pipe_config->name & (mask)); \
12825                 ret = false; \
12826         }
12827
12828 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12829         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12830                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12831                           "(expected %i, found %i)\n", \
12832                           current_config->name, \
12833                           pipe_config->name); \
12834                 ret = false; \
12835         }
12836
12837 #define PIPE_CONF_QUIRK(quirk)  \
12838         ((current_config->quirks | pipe_config->quirks) & (quirk))
12839
12840         PIPE_CONF_CHECK_I(cpu_transcoder);
12841
12842         PIPE_CONF_CHECK_I(has_pch_encoder);
12843         PIPE_CONF_CHECK_I(fdi_lanes);
12844         PIPE_CONF_CHECK_M_N(fdi_m_n);
12845
12846         PIPE_CONF_CHECK_I(has_dp_encoder);
12847         PIPE_CONF_CHECK_I(lane_count);
12848         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12849
12850         if (INTEL_INFO(dev)->gen < 8) {
12851                 PIPE_CONF_CHECK_M_N(dp_m_n);
12852
12853                 if (current_config->has_drrs)
12854                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12855         } else
12856                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12857
12858         PIPE_CONF_CHECK_I(has_dsi_encoder);
12859
12860         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12861         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12862         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12863         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12864         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12865         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12866
12867         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12868         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12869         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12870         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12871         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12872         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12873
12874         PIPE_CONF_CHECK_I(pixel_multiplier);
12875         PIPE_CONF_CHECK_I(has_hdmi_sink);
12876         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12877             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12878                 PIPE_CONF_CHECK_I(limited_color_range);
12879         PIPE_CONF_CHECK_I(has_infoframe);
12880
12881         PIPE_CONF_CHECK_I(has_audio);
12882
12883         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12884                               DRM_MODE_FLAG_INTERLACE);
12885
12886         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12887                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12888                                       DRM_MODE_FLAG_PHSYNC);
12889                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12890                                       DRM_MODE_FLAG_NHSYNC);
12891                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12892                                       DRM_MODE_FLAG_PVSYNC);
12893                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12894                                       DRM_MODE_FLAG_NVSYNC);
12895         }
12896
12897         PIPE_CONF_CHECK_X(gmch_pfit.control);
12898         /* pfit ratios are autocomputed by the hw on gen4+ */
12899         if (INTEL_INFO(dev)->gen < 4)
12900                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12901         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12902
12903         if (!adjust) {
12904                 PIPE_CONF_CHECK_I(pipe_src_w);
12905                 PIPE_CONF_CHECK_I(pipe_src_h);
12906
12907                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12908                 if (current_config->pch_pfit.enabled) {
12909                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12910                         PIPE_CONF_CHECK_X(pch_pfit.size);
12911                 }
12912
12913                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12914         }
12915
12916         /* BDW+ don't expose a synchronous way to read the state */
12917         if (IS_HASWELL(dev))
12918                 PIPE_CONF_CHECK_I(ips_enabled);
12919
12920         PIPE_CONF_CHECK_I(double_wide);
12921
12922         PIPE_CONF_CHECK_X(ddi_pll_sel);
12923
12924         PIPE_CONF_CHECK_P(shared_dpll);
12925         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12926         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12927         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12928         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12929         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12930         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12931         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12932         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12933         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12934
12935         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12936         PIPE_CONF_CHECK_X(dsi_pll.div);
12937
12938         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12939                 PIPE_CONF_CHECK_I(pipe_bpp);
12940
12941         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12942         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12943
12944 #undef PIPE_CONF_CHECK_X
12945 #undef PIPE_CONF_CHECK_I
12946 #undef PIPE_CONF_CHECK_P
12947 #undef PIPE_CONF_CHECK_FLAGS
12948 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12949 #undef PIPE_CONF_QUIRK
12950 #undef INTEL_ERR_OR_DBG_KMS
12951
12952         return ret;
12953 }
12954
12955 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12956                                            const struct intel_crtc_state *pipe_config)
12957 {
12958         if (pipe_config->has_pch_encoder) {
12959                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12960                                                             &pipe_config->fdi_m_n);
12961                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12962
12963                 /*
12964                  * FDI already provided one idea for the dotclock.
12965                  * Yell if the encoder disagrees.
12966                  */
12967                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12968                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12969                      fdi_dotclock, dotclock);
12970         }
12971 }
12972
12973 static void verify_wm_state(struct drm_crtc *crtc,
12974                             struct drm_crtc_state *new_state)
12975 {
12976         struct drm_device *dev = crtc->dev;
12977         struct drm_i915_private *dev_priv = dev->dev_private;
12978         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12979         struct skl_ddb_entry *hw_entry, *sw_entry;
12980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12981         const enum pipe pipe = intel_crtc->pipe;
12982         int plane;
12983
12984         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12985                 return;
12986
12987         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12988         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12989
12990         /* planes */
12991         for_each_plane(dev_priv, pipe, plane) {
12992                 hw_entry = &hw_ddb.plane[pipe][plane];
12993                 sw_entry = &sw_ddb->plane[pipe][plane];
12994
12995                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12996                         continue;
12997
12998                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12999                           "(expected (%u,%u), found (%u,%u))\n",
13000                           pipe_name(pipe), plane + 1,
13001                           sw_entry->start, sw_entry->end,
13002                           hw_entry->start, hw_entry->end);
13003         }
13004
13005         /* cursor */
13006         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13007         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13008
13009         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13010                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13011                           "(expected (%u,%u), found (%u,%u))\n",
13012                           pipe_name(pipe),
13013                           sw_entry->start, sw_entry->end,
13014                           hw_entry->start, hw_entry->end);
13015         }
13016 }
13017
13018 static void
13019 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13020 {
13021         struct drm_connector *connector;
13022
13023         drm_for_each_connector(connector, dev) {
13024                 struct drm_encoder *encoder = connector->encoder;
13025                 struct drm_connector_state *state = connector->state;
13026
13027                 if (state->crtc != crtc)
13028                         continue;
13029
13030                 intel_connector_verify_state(to_intel_connector(connector));
13031
13032                 I915_STATE_WARN(state->best_encoder != encoder,
13033                      "connector's atomic encoder doesn't match legacy encoder\n");
13034         }
13035 }
13036
13037 static void
13038 verify_encoder_state(struct drm_device *dev)
13039 {
13040         struct intel_encoder *encoder;
13041         struct intel_connector *connector;
13042
13043         for_each_intel_encoder(dev, encoder) {
13044                 bool enabled = false;
13045                 enum pipe pipe;
13046
13047                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13048                               encoder->base.base.id,
13049                               encoder->base.name);
13050
13051                 for_each_intel_connector(dev, connector) {
13052                         if (connector->base.state->best_encoder != &encoder->base)
13053                                 continue;
13054                         enabled = true;
13055
13056                         I915_STATE_WARN(connector->base.state->crtc !=
13057                                         encoder->base.crtc,
13058                              "connector's crtc doesn't match encoder crtc\n");
13059                 }
13060
13061                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13062                      "encoder's enabled state mismatch "
13063                      "(expected %i, found %i)\n",
13064                      !!encoder->base.crtc, enabled);
13065
13066                 if (!encoder->base.crtc) {
13067                         bool active;
13068
13069                         active = encoder->get_hw_state(encoder, &pipe);
13070                         I915_STATE_WARN(active,
13071                              "encoder detached but still enabled on pipe %c.\n",
13072                              pipe_name(pipe));
13073                 }
13074         }
13075 }
13076
13077 static void
13078 verify_crtc_state(struct drm_crtc *crtc,
13079                   struct drm_crtc_state *old_crtc_state,
13080                   struct drm_crtc_state *new_crtc_state)
13081 {
13082         struct drm_device *dev = crtc->dev;
13083         struct drm_i915_private *dev_priv = dev->dev_private;
13084         struct intel_encoder *encoder;
13085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13086         struct intel_crtc_state *pipe_config, *sw_config;
13087         struct drm_atomic_state *old_state;
13088         bool active;
13089
13090         old_state = old_crtc_state->state;
13091         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13092         pipe_config = to_intel_crtc_state(old_crtc_state);
13093         memset(pipe_config, 0, sizeof(*pipe_config));
13094         pipe_config->base.crtc = crtc;
13095         pipe_config->base.state = old_state;
13096
13097         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13098
13099         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13100
13101         /* hw state is inconsistent with the pipe quirk */
13102         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13103             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13104                 active = new_crtc_state->active;
13105
13106         I915_STATE_WARN(new_crtc_state->active != active,
13107              "crtc active state doesn't match with hw state "
13108              "(expected %i, found %i)\n", new_crtc_state->active, active);
13109
13110         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13111              "transitional active state does not match atomic hw state "
13112              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13113
13114         for_each_encoder_on_crtc(dev, crtc, encoder) {
13115                 enum pipe pipe;
13116
13117                 active = encoder->get_hw_state(encoder, &pipe);
13118                 I915_STATE_WARN(active != new_crtc_state->active,
13119                         "[ENCODER:%i] active %i with crtc active %i\n",
13120                         encoder->base.base.id, active, new_crtc_state->active);
13121
13122                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13123                                 "Encoder connected to wrong pipe %c\n",
13124                                 pipe_name(pipe));
13125
13126                 if (active)
13127                         encoder->get_config(encoder, pipe_config);
13128         }
13129
13130         if (!new_crtc_state->active)
13131                 return;
13132
13133         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13134
13135         sw_config = to_intel_crtc_state(crtc->state);
13136         if (!intel_pipe_config_compare(dev, sw_config,
13137                                        pipe_config, false)) {
13138                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13139                 intel_dump_pipe_config(intel_crtc, pipe_config,
13140                                        "[hw state]");
13141                 intel_dump_pipe_config(intel_crtc, sw_config,
13142                                        "[sw state]");
13143         }
13144 }
13145
13146 static void
13147 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13148                          struct intel_shared_dpll *pll,
13149                          struct drm_crtc *crtc,
13150                          struct drm_crtc_state *new_state)
13151 {
13152         struct intel_dpll_hw_state dpll_hw_state;
13153         unsigned crtc_mask;
13154         bool active;
13155
13156         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13157
13158         DRM_DEBUG_KMS("%s\n", pll->name);
13159
13160         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13161
13162         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13163                 I915_STATE_WARN(!pll->on && pll->active_mask,
13164                      "pll in active use but not on in sw tracking\n");
13165                 I915_STATE_WARN(pll->on && !pll->active_mask,
13166                      "pll is on but not used by any active crtc\n");
13167                 I915_STATE_WARN(pll->on != active,
13168                      "pll on state mismatch (expected %i, found %i)\n",
13169                      pll->on, active);
13170         }
13171
13172         if (!crtc) {
13173                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13174                                 "more active pll users than references: %x vs %x\n",
13175                                 pll->active_mask, pll->config.crtc_mask);
13176
13177                 return;
13178         }
13179
13180         crtc_mask = 1 << drm_crtc_index(crtc);
13181
13182         if (new_state->active)
13183                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13184                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13185                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13186         else
13187                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13188                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13189                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13190
13191         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13192                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13193                         crtc_mask, pll->config.crtc_mask);
13194
13195         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13196                                           &dpll_hw_state,
13197                                           sizeof(dpll_hw_state)),
13198                         "pll hw state mismatch\n");
13199 }
13200
13201 static void
13202 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13203                          struct drm_crtc_state *old_crtc_state,
13204                          struct drm_crtc_state *new_crtc_state)
13205 {
13206         struct drm_i915_private *dev_priv = dev->dev_private;
13207         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13208         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13209
13210         if (new_state->shared_dpll)
13211                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13212
13213         if (old_state->shared_dpll &&
13214             old_state->shared_dpll != new_state->shared_dpll) {
13215                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13216                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13217
13218                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13219                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13220                                 pipe_name(drm_crtc_index(crtc)));
13221                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13222                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13223                                 pipe_name(drm_crtc_index(crtc)));
13224         }
13225 }
13226
13227 static void
13228 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13229                          struct drm_crtc_state *old_state,
13230                          struct drm_crtc_state *new_state)
13231 {
13232         if (!needs_modeset(new_state) &&
13233             !to_intel_crtc_state(new_state)->update_pipe)
13234                 return;
13235
13236         verify_wm_state(crtc, new_state);
13237         verify_connector_state(crtc->dev, crtc);
13238         verify_crtc_state(crtc, old_state, new_state);
13239         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13240 }
13241
13242 static void
13243 verify_disabled_dpll_state(struct drm_device *dev)
13244 {
13245         struct drm_i915_private *dev_priv = dev->dev_private;
13246         int i;
13247
13248         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13249                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13250 }
13251
13252 static void
13253 intel_modeset_verify_disabled(struct drm_device *dev)
13254 {
13255         verify_encoder_state(dev);
13256         verify_connector_state(dev, NULL);
13257         verify_disabled_dpll_state(dev);
13258 }
13259
13260 static void update_scanline_offset(struct intel_crtc *crtc)
13261 {
13262         struct drm_device *dev = crtc->base.dev;
13263
13264         /*
13265          * The scanline counter increments at the leading edge of hsync.
13266          *
13267          * On most platforms it starts counting from vtotal-1 on the
13268          * first active line. That means the scanline counter value is
13269          * always one less than what we would expect. Ie. just after
13270          * start of vblank, which also occurs at start of hsync (on the
13271          * last active line), the scanline counter will read vblank_start-1.
13272          *
13273          * On gen2 the scanline counter starts counting from 1 instead
13274          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13275          * to keep the value positive), instead of adding one.
13276          *
13277          * On HSW+ the behaviour of the scanline counter depends on the output
13278          * type. For DP ports it behaves like most other platforms, but on HDMI
13279          * there's an extra 1 line difference. So we need to add two instead of
13280          * one to the value.
13281          */
13282         if (IS_GEN2(dev)) {
13283                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13284                 int vtotal;
13285
13286                 vtotal = adjusted_mode->crtc_vtotal;
13287                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13288                         vtotal /= 2;
13289
13290                 crtc->scanline_offset = vtotal - 1;
13291         } else if (HAS_DDI(dev) &&
13292                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13293                 crtc->scanline_offset = 2;
13294         } else
13295                 crtc->scanline_offset = 1;
13296 }
13297
13298 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13299 {
13300         struct drm_device *dev = state->dev;
13301         struct drm_i915_private *dev_priv = to_i915(dev);
13302         struct intel_shared_dpll_config *shared_dpll = NULL;
13303         struct drm_crtc *crtc;
13304         struct drm_crtc_state *crtc_state;
13305         int i;
13306
13307         if (!dev_priv->display.crtc_compute_clock)
13308                 return;
13309
13310         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13311                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13312                 struct intel_shared_dpll *old_dpll =
13313                         to_intel_crtc_state(crtc->state)->shared_dpll;
13314
13315                 if (!needs_modeset(crtc_state))
13316                         continue;
13317
13318                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13319
13320                 if (!old_dpll)
13321                         continue;
13322
13323                 if (!shared_dpll)
13324                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13325
13326                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13327         }
13328 }
13329
13330 /*
13331  * This implements the workaround described in the "notes" section of the mode
13332  * set sequence documentation. When going from no pipes or single pipe to
13333  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13334  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13335  */
13336 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13337 {
13338         struct drm_crtc_state *crtc_state;
13339         struct intel_crtc *intel_crtc;
13340         struct drm_crtc *crtc;
13341         struct intel_crtc_state *first_crtc_state = NULL;
13342         struct intel_crtc_state *other_crtc_state = NULL;
13343         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13344         int i;
13345
13346         /* look at all crtc's that are going to be enabled in during modeset */
13347         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13348                 intel_crtc = to_intel_crtc(crtc);
13349
13350                 if (!crtc_state->active || !needs_modeset(crtc_state))
13351                         continue;
13352
13353                 if (first_crtc_state) {
13354                         other_crtc_state = to_intel_crtc_state(crtc_state);
13355                         break;
13356                 } else {
13357                         first_crtc_state = to_intel_crtc_state(crtc_state);
13358                         first_pipe = intel_crtc->pipe;
13359                 }
13360         }
13361
13362         /* No workaround needed? */
13363         if (!first_crtc_state)
13364                 return 0;
13365
13366         /* w/a possibly needed, check how many crtc's are already enabled. */
13367         for_each_intel_crtc(state->dev, intel_crtc) {
13368                 struct intel_crtc_state *pipe_config;
13369
13370                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13371                 if (IS_ERR(pipe_config))
13372                         return PTR_ERR(pipe_config);
13373
13374                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13375
13376                 if (!pipe_config->base.active ||
13377                     needs_modeset(&pipe_config->base))
13378                         continue;
13379
13380                 /* 2 or more enabled crtcs means no need for w/a */
13381                 if (enabled_pipe != INVALID_PIPE)
13382                         return 0;
13383
13384                 enabled_pipe = intel_crtc->pipe;
13385         }
13386
13387         if (enabled_pipe != INVALID_PIPE)
13388                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13389         else if (other_crtc_state)
13390                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13391
13392         return 0;
13393 }
13394
13395 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13396 {
13397         struct drm_crtc *crtc;
13398         struct drm_crtc_state *crtc_state;
13399         int ret = 0;
13400
13401         /* add all active pipes to the state */
13402         for_each_crtc(state->dev, crtc) {
13403                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13404                 if (IS_ERR(crtc_state))
13405                         return PTR_ERR(crtc_state);
13406
13407                 if (!crtc_state->active || needs_modeset(crtc_state))
13408                         continue;
13409
13410                 crtc_state->mode_changed = true;
13411
13412                 ret = drm_atomic_add_affected_connectors(state, crtc);
13413                 if (ret)
13414                         break;
13415
13416                 ret = drm_atomic_add_affected_planes(state, crtc);
13417                 if (ret)
13418                         break;
13419         }
13420
13421         return ret;
13422 }
13423
13424 static int intel_modeset_checks(struct drm_atomic_state *state)
13425 {
13426         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13427         struct drm_i915_private *dev_priv = state->dev->dev_private;
13428         struct drm_crtc *crtc;
13429         struct drm_crtc_state *crtc_state;
13430         int ret = 0, i;
13431
13432         if (!check_digital_port_conflicts(state)) {
13433                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13434                 return -EINVAL;
13435         }
13436
13437         intel_state->modeset = true;
13438         intel_state->active_crtcs = dev_priv->active_crtcs;
13439
13440         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13441                 if (crtc_state->active)
13442                         intel_state->active_crtcs |= 1 << i;
13443                 else
13444                         intel_state->active_crtcs &= ~(1 << i);
13445
13446                 if (crtc_state->active != crtc->state->active)
13447                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13448         }
13449
13450         /*
13451          * See if the config requires any additional preparation, e.g.
13452          * to adjust global state with pipes off.  We need to do this
13453          * here so we can get the modeset_pipe updated config for the new
13454          * mode set on this crtc.  For other crtcs we need to use the
13455          * adjusted_mode bits in the crtc directly.
13456          */
13457         if (dev_priv->display.modeset_calc_cdclk) {
13458                 if (!intel_state->cdclk_pll_vco)
13459                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13460                 if (!intel_state->cdclk_pll_vco)
13461                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13462
13463                 ret = dev_priv->display.modeset_calc_cdclk(state);
13464                 if (ret < 0)
13465                         return ret;
13466
13467                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13468                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13469                         ret = intel_modeset_all_pipes(state);
13470
13471                 if (ret < 0)
13472                         return ret;
13473
13474                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13475                               intel_state->cdclk, intel_state->dev_cdclk);
13476         } else
13477                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13478
13479         intel_modeset_clear_plls(state);
13480
13481         if (IS_HASWELL(dev_priv))
13482                 return haswell_mode_set_planes_workaround(state);
13483
13484         return 0;
13485 }
13486
13487 /*
13488  * Handle calculation of various watermark data at the end of the atomic check
13489  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13490  * handlers to ensure that all derived state has been updated.
13491  */
13492 static int calc_watermark_data(struct drm_atomic_state *state)
13493 {
13494         struct drm_device *dev = state->dev;
13495         struct drm_i915_private *dev_priv = to_i915(dev);
13496
13497         /* Is there platform-specific watermark information to calculate? */
13498         if (dev_priv->display.compute_global_watermarks)
13499                 return dev_priv->display.compute_global_watermarks(state);
13500
13501         return 0;
13502 }
13503
13504 /**
13505  * intel_atomic_check - validate state object
13506  * @dev: drm device
13507  * @state: state to validate
13508  */
13509 static int intel_atomic_check(struct drm_device *dev,
13510                               struct drm_atomic_state *state)
13511 {
13512         struct drm_i915_private *dev_priv = to_i915(dev);
13513         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13514         struct drm_crtc *crtc;
13515         struct drm_crtc_state *crtc_state;
13516         int ret, i;
13517         bool any_ms = false;
13518
13519         ret = drm_atomic_helper_check_modeset(dev, state);
13520         if (ret)
13521                 return ret;
13522
13523         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13524                 struct intel_crtc_state *pipe_config =
13525                         to_intel_crtc_state(crtc_state);
13526
13527                 /* Catch I915_MODE_FLAG_INHERITED */
13528                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13529                         crtc_state->mode_changed = true;
13530
13531                 if (!needs_modeset(crtc_state))
13532                         continue;
13533
13534                 if (!crtc_state->enable) {
13535                         any_ms = true;
13536                         continue;
13537                 }
13538
13539                 /* FIXME: For only active_changed we shouldn't need to do any
13540                  * state recomputation at all. */
13541
13542                 ret = drm_atomic_add_affected_connectors(state, crtc);
13543                 if (ret)
13544                         return ret;
13545
13546                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13547                 if (ret) {
13548                         intel_dump_pipe_config(to_intel_crtc(crtc),
13549                                                pipe_config, "[failed]");
13550                         return ret;
13551                 }
13552
13553                 if (i915.fastboot &&
13554                     intel_pipe_config_compare(dev,
13555                                         to_intel_crtc_state(crtc->state),
13556                                         pipe_config, true)) {
13557                         crtc_state->mode_changed = false;
13558                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13559                 }
13560
13561                 if (needs_modeset(crtc_state))
13562                         any_ms = true;
13563
13564                 ret = drm_atomic_add_affected_planes(state, crtc);
13565                 if (ret)
13566                         return ret;
13567
13568                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13569                                        needs_modeset(crtc_state) ?
13570                                        "[modeset]" : "[fastset]");
13571         }
13572
13573         if (any_ms) {
13574                 ret = intel_modeset_checks(state);
13575
13576                 if (ret)
13577                         return ret;
13578         } else
13579                 intel_state->cdclk = dev_priv->cdclk_freq;
13580
13581         ret = drm_atomic_helper_check_planes(dev, state);
13582         if (ret)
13583                 return ret;
13584
13585         intel_fbc_choose_crtc(dev_priv, state);
13586         return calc_watermark_data(state);
13587 }
13588
13589 static int intel_atomic_prepare_commit(struct drm_device *dev,
13590                                        struct drm_atomic_state *state,
13591                                        bool nonblock)
13592 {
13593         struct drm_i915_private *dev_priv = dev->dev_private;
13594         struct drm_plane_state *plane_state;
13595         struct drm_crtc_state *crtc_state;
13596         struct drm_plane *plane;
13597         struct drm_crtc *crtc;
13598         int i, ret;
13599
13600         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13601                 if (state->legacy_cursor_update)
13602                         continue;
13603
13604                 ret = intel_crtc_wait_for_pending_flips(crtc);
13605                 if (ret)
13606                         return ret;
13607
13608                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13609                         flush_workqueue(dev_priv->wq);
13610         }
13611
13612         ret = mutex_lock_interruptible(&dev->struct_mutex);
13613         if (ret)
13614                 return ret;
13615
13616         ret = drm_atomic_helper_prepare_planes(dev, state);
13617         mutex_unlock(&dev->struct_mutex);
13618
13619         if (!ret && !nonblock) {
13620                 for_each_plane_in_state(state, plane, plane_state, i) {
13621                         struct intel_plane_state *intel_plane_state =
13622                                 to_intel_plane_state(plane_state);
13623
13624                         if (!intel_plane_state->wait_req)
13625                                 continue;
13626
13627                         ret = __i915_wait_request(intel_plane_state->wait_req,
13628                                                   true, NULL, NULL);
13629                         if (ret) {
13630                                 /* Any hang should be swallowed by the wait */
13631                                 WARN_ON(ret == -EIO);
13632                                 mutex_lock(&dev->struct_mutex);
13633                                 drm_atomic_helper_cleanup_planes(dev, state);
13634                                 mutex_unlock(&dev->struct_mutex);
13635                                 break;
13636                         }
13637                 }
13638         }
13639
13640         return ret;
13641 }
13642
13643 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13644 {
13645         struct drm_device *dev = crtc->base.dev;
13646
13647         if (!dev->max_vblank_count)
13648                 return drm_accurate_vblank_count(&crtc->base);
13649
13650         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13651 }
13652
13653 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13654                                           struct drm_i915_private *dev_priv,
13655                                           unsigned crtc_mask)
13656 {
13657         unsigned last_vblank_count[I915_MAX_PIPES];
13658         enum pipe pipe;
13659         int ret;
13660
13661         if (!crtc_mask)
13662                 return;
13663
13664         for_each_pipe(dev_priv, pipe) {
13665                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13666
13667                 if (!((1 << pipe) & crtc_mask))
13668                         continue;
13669
13670                 ret = drm_crtc_vblank_get(crtc);
13671                 if (WARN_ON(ret != 0)) {
13672                         crtc_mask &= ~(1 << pipe);
13673                         continue;
13674                 }
13675
13676                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13677         }
13678
13679         for_each_pipe(dev_priv, pipe) {
13680                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13681                 long lret;
13682
13683                 if (!((1 << pipe) & crtc_mask))
13684                         continue;
13685
13686                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13687                                 last_vblank_count[pipe] !=
13688                                         drm_crtc_vblank_count(crtc),
13689                                 msecs_to_jiffies(50));
13690
13691                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13692
13693                 drm_crtc_vblank_put(crtc);
13694         }
13695 }
13696
13697 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13698 {
13699         /* fb updated, need to unpin old fb */
13700         if (crtc_state->fb_changed)
13701                 return true;
13702
13703         /* wm changes, need vblank before final wm's */
13704         if (crtc_state->update_wm_post)
13705                 return true;
13706
13707         /*
13708          * cxsr is re-enabled after vblank.
13709          * This is already handled by crtc_state->update_wm_post,
13710          * but added for clarity.
13711          */
13712         if (crtc_state->disable_cxsr)
13713                 return true;
13714
13715         return false;
13716 }
13717
13718 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13719 {
13720         struct drm_device *dev = state->dev;
13721         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13722         struct drm_i915_private *dev_priv = dev->dev_private;
13723         struct drm_crtc_state *old_crtc_state;
13724         struct drm_crtc *crtc;
13725         struct intel_crtc_state *intel_cstate;
13726         struct drm_plane *plane;
13727         struct drm_plane_state *plane_state;
13728         bool hw_check = intel_state->modeset;
13729         unsigned long put_domains[I915_MAX_PIPES] = {};
13730         unsigned crtc_vblank_mask = 0;
13731         int i, ret;
13732
13733         for_each_plane_in_state(state, plane, plane_state, i) {
13734                 struct intel_plane_state *intel_plane_state =
13735                         to_intel_plane_state(plane_state);
13736
13737                 if (!intel_plane_state->wait_req)
13738                         continue;
13739
13740                 ret = __i915_wait_request(intel_plane_state->wait_req,
13741                                           true, NULL, NULL);
13742                 /* EIO should be eaten, and we can't get interrupted in the
13743                  * worker, and blocking commits have waited already. */
13744                 WARN_ON(ret);
13745         }
13746
13747         drm_atomic_helper_wait_for_dependencies(state);
13748
13749         if (intel_state->modeset) {
13750                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13751                        sizeof(intel_state->min_pixclk));
13752                 dev_priv->active_crtcs = intel_state->active_crtcs;
13753                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13754
13755                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13756         }
13757
13758         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13759                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13760
13761                 if (needs_modeset(crtc->state) ||
13762                     to_intel_crtc_state(crtc->state)->update_pipe) {
13763                         hw_check = true;
13764
13765                         put_domains[to_intel_crtc(crtc)->pipe] =
13766                                 modeset_get_crtc_power_domains(crtc,
13767                                         to_intel_crtc_state(crtc->state));
13768                 }
13769
13770                 if (!needs_modeset(crtc->state))
13771                         continue;
13772
13773                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13774
13775                 if (old_crtc_state->active) {
13776                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13777                         dev_priv->display.crtc_disable(crtc);
13778                         intel_crtc->active = false;
13779                         intel_fbc_disable(intel_crtc);
13780                         intel_disable_shared_dpll(intel_crtc);
13781
13782                         /*
13783                          * Underruns don't always raise
13784                          * interrupts, so check manually.
13785                          */
13786                         intel_check_cpu_fifo_underruns(dev_priv);
13787                         intel_check_pch_fifo_underruns(dev_priv);
13788
13789                         if (!crtc->state->active)
13790                                 intel_update_watermarks(crtc);
13791                 }
13792         }
13793
13794         /* Only after disabling all output pipelines that will be changed can we
13795          * update the the output configuration. */
13796         intel_modeset_update_crtc_state(state);
13797
13798         if (intel_state->modeset) {
13799                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13800
13801                 if (dev_priv->display.modeset_commit_cdclk &&
13802                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13803                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13804                         dev_priv->display.modeset_commit_cdclk(state);
13805
13806                 intel_modeset_verify_disabled(dev);
13807         }
13808
13809         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13810         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13811                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13812                 bool modeset = needs_modeset(crtc->state);
13813                 struct intel_crtc_state *pipe_config =
13814                         to_intel_crtc_state(crtc->state);
13815
13816                 if (modeset && crtc->state->active) {
13817                         update_scanline_offset(to_intel_crtc(crtc));
13818                         dev_priv->display.crtc_enable(crtc);
13819                 }
13820
13821                 /* Complete events for now disable pipes here. */
13822                 if (modeset && !crtc->state->active && crtc->state->event) {
13823                         spin_lock_irq(&dev->event_lock);
13824                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
13825                         spin_unlock_irq(&dev->event_lock);
13826
13827                         crtc->state->event = NULL;
13828                 }
13829
13830                 if (!modeset)
13831                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13832
13833                 if (crtc->state->active &&
13834                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13835                         intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13836
13837                 if (crtc->state->active)
13838                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13839
13840                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13841                         crtc_vblank_mask |= 1 << i;
13842         }
13843
13844         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13845          * already, but still need the state for the delayed optimization. To
13846          * fix this:
13847          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13848          * - schedule that vblank worker _before_ calling hw_done
13849          * - at the start of commit_tail, cancel it _synchrously
13850          * - switch over to the vblank wait helper in the core after that since
13851          *   we don't need out special handling any more.
13852          */
13853         if (!state->legacy_cursor_update)
13854                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13855
13856         /*
13857          * Now that the vblank has passed, we can go ahead and program the
13858          * optimal watermarks on platforms that need two-step watermark
13859          * programming.
13860          *
13861          * TODO: Move this (and other cleanup) to an async worker eventually.
13862          */
13863         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13864                 intel_cstate = to_intel_crtc_state(crtc->state);
13865
13866                 if (dev_priv->display.optimize_watermarks)
13867                         dev_priv->display.optimize_watermarks(intel_cstate);
13868         }
13869
13870         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13871                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13872
13873                 if (put_domains[i])
13874                         modeset_put_power_domains(dev_priv, put_domains[i]);
13875
13876                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13877         }
13878
13879         drm_atomic_helper_commit_hw_done(state);
13880
13881         if (intel_state->modeset)
13882                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13883
13884         mutex_lock(&dev->struct_mutex);
13885         drm_atomic_helper_cleanup_planes(dev, state);
13886         mutex_unlock(&dev->struct_mutex);
13887
13888         drm_atomic_helper_commit_cleanup_done(state);
13889
13890         drm_atomic_state_free(state);
13891
13892         /* As one of the primary mmio accessors, KMS has a high likelihood
13893          * of triggering bugs in unclaimed access. After we finish
13894          * modesetting, see if an error has been flagged, and if so
13895          * enable debugging for the next modeset - and hope we catch
13896          * the culprit.
13897          *
13898          * XXX note that we assume display power is on at this point.
13899          * This might hold true now but we need to add pm helper to check
13900          * unclaimed only when the hardware is on, as atomic commits
13901          * can happen also when the device is completely off.
13902          */
13903         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13904 }
13905
13906 static void intel_atomic_commit_work(struct work_struct *work)
13907 {
13908         struct drm_atomic_state *state = container_of(work,
13909                                                       struct drm_atomic_state,
13910                                                       commit_work);
13911         intel_atomic_commit_tail(state);
13912 }
13913
13914 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13915 {
13916         struct drm_plane_state *old_plane_state;
13917         struct drm_plane *plane;
13918         struct drm_i915_gem_object *obj, *old_obj;
13919         struct intel_plane *intel_plane;
13920         int i;
13921
13922         mutex_lock(&state->dev->struct_mutex);
13923         for_each_plane_in_state(state, plane, old_plane_state, i) {
13924                 obj = intel_fb_obj(plane->state->fb);
13925                 old_obj = intel_fb_obj(old_plane_state->fb);
13926                 intel_plane = to_intel_plane(plane);
13927
13928                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13929         }
13930         mutex_unlock(&state->dev->struct_mutex);
13931 }
13932
13933 /**
13934  * intel_atomic_commit - commit validated state object
13935  * @dev: DRM device
13936  * @state: the top-level driver state object
13937  * @nonblock: nonblocking commit
13938  *
13939  * This function commits a top-level state object that has been validated
13940  * with drm_atomic_helper_check().
13941  *
13942  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13943  * nonblocking commits are only safe for pure plane updates. Everything else
13944  * should work though.
13945  *
13946  * RETURNS
13947  * Zero for success or -errno.
13948  */
13949 static int intel_atomic_commit(struct drm_device *dev,
13950                                struct drm_atomic_state *state,
13951                                bool nonblock)
13952 {
13953         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13954         struct drm_i915_private *dev_priv = dev->dev_private;
13955         int ret = 0;
13956
13957         if (intel_state->modeset && nonblock) {
13958                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13959                 return -EINVAL;
13960         }
13961
13962         ret = drm_atomic_helper_setup_commit(state, nonblock);
13963         if (ret)
13964                 return ret;
13965
13966         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13967
13968         ret = intel_atomic_prepare_commit(dev, state, nonblock);
13969         if (ret) {
13970                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13971                 return ret;
13972         }
13973
13974         drm_atomic_helper_swap_state(state, true);
13975         dev_priv->wm.distrust_bios_wm = false;
13976         dev_priv->wm.skl_results = intel_state->wm_results;
13977         intel_shared_dpll_commit(state);
13978         intel_atomic_track_fbs(state);
13979
13980         if (nonblock)
13981                 queue_work(system_unbound_wq, &state->commit_work);
13982         else
13983                 intel_atomic_commit_tail(state);
13984
13985         return 0;
13986 }
13987
13988 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13989 {
13990         struct drm_device *dev = crtc->dev;
13991         struct drm_atomic_state *state;
13992         struct drm_crtc_state *crtc_state;
13993         int ret;
13994
13995         state = drm_atomic_state_alloc(dev);
13996         if (!state) {
13997                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13998                               crtc->base.id, crtc->name);
13999                 return;
14000         }
14001
14002         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14003
14004 retry:
14005         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14006         ret = PTR_ERR_OR_ZERO(crtc_state);
14007         if (!ret) {
14008                 if (!crtc_state->active)
14009                         goto out;
14010
14011                 crtc_state->mode_changed = true;
14012                 ret = drm_atomic_commit(state);
14013         }
14014
14015         if (ret == -EDEADLK) {
14016                 drm_atomic_state_clear(state);
14017                 drm_modeset_backoff(state->acquire_ctx);
14018                 goto retry;
14019         }
14020
14021         if (ret)
14022 out:
14023                 drm_atomic_state_free(state);
14024 }
14025
14026 #undef for_each_intel_crtc_masked
14027
14028 static const struct drm_crtc_funcs intel_crtc_funcs = {
14029         .gamma_set = drm_atomic_helper_legacy_gamma_set,
14030         .set_config = drm_atomic_helper_set_config,
14031         .set_property = drm_atomic_helper_crtc_set_property,
14032         .destroy = intel_crtc_destroy,
14033         .page_flip = intel_crtc_page_flip,
14034         .atomic_duplicate_state = intel_crtc_duplicate_state,
14035         .atomic_destroy_state = intel_crtc_destroy_state,
14036 };
14037
14038 /**
14039  * intel_prepare_plane_fb - Prepare fb for usage on plane
14040  * @plane: drm plane to prepare for
14041  * @fb: framebuffer to prepare for presentation
14042  *
14043  * Prepares a framebuffer for usage on a display plane.  Generally this
14044  * involves pinning the underlying object and updating the frontbuffer tracking
14045  * bits.  Some older platforms need special physical address handling for
14046  * cursor planes.
14047  *
14048  * Must be called with struct_mutex held.
14049  *
14050  * Returns 0 on success, negative error code on failure.
14051  */
14052 int
14053 intel_prepare_plane_fb(struct drm_plane *plane,
14054                        const struct drm_plane_state *new_state)
14055 {
14056         struct drm_device *dev = plane->dev;
14057         struct drm_framebuffer *fb = new_state->fb;
14058         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14059         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14060         struct reservation_object *resv;
14061         int ret = 0;
14062
14063         if (!obj && !old_obj)
14064                 return 0;
14065
14066         if (old_obj) {
14067                 struct drm_crtc_state *crtc_state =
14068                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14069
14070                 /* Big Hammer, we also need to ensure that any pending
14071                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14072                  * current scanout is retired before unpinning the old
14073                  * framebuffer. Note that we rely on userspace rendering
14074                  * into the buffer attached to the pipe they are waiting
14075                  * on. If not, userspace generates a GPU hang with IPEHR
14076                  * point to the MI_WAIT_FOR_EVENT.
14077                  *
14078                  * This should only fail upon a hung GPU, in which case we
14079                  * can safely continue.
14080                  */
14081                 if (needs_modeset(crtc_state))
14082                         ret = i915_gem_object_wait_rendering(old_obj, true);
14083                 if (ret) {
14084                         /* GPU hangs should have been swallowed by the wait */
14085                         WARN_ON(ret == -EIO);
14086                         return ret;
14087                 }
14088         }
14089
14090         if (!obj)
14091                 return 0;
14092
14093         /* For framebuffer backed by dmabuf, wait for fence */
14094         resv = i915_gem_object_get_dmabuf_resv(obj);
14095         if (resv) {
14096                 long lret;
14097
14098                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14099                                                            MAX_SCHEDULE_TIMEOUT);
14100                 if (lret == -ERESTARTSYS)
14101                         return lret;
14102
14103                 WARN(lret < 0, "waiting returns %li\n", lret);
14104         }
14105
14106         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14107             INTEL_INFO(dev)->cursor_needs_physical) {
14108                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14109                 ret = i915_gem_object_attach_phys(obj, align);
14110                 if (ret)
14111                         DRM_DEBUG_KMS("failed to attach phys object\n");
14112         } else {
14113                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14114         }
14115
14116         if (ret == 0) {
14117                 struct intel_plane_state *plane_state =
14118                         to_intel_plane_state(new_state);
14119
14120                 i915_gem_request_assign(&plane_state->wait_req,
14121                                         obj->last_write_req);
14122         }
14123
14124         return ret;
14125 }
14126
14127 /**
14128  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14129  * @plane: drm plane to clean up for
14130  * @fb: old framebuffer that was on plane
14131  *
14132  * Cleans up a framebuffer that has just been removed from a plane.
14133  *
14134  * Must be called with struct_mutex held.
14135  */
14136 void
14137 intel_cleanup_plane_fb(struct drm_plane *plane,
14138                        const struct drm_plane_state *old_state)
14139 {
14140         struct drm_device *dev = plane->dev;
14141         struct intel_plane_state *old_intel_state;
14142         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14143         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14144
14145         old_intel_state = to_intel_plane_state(old_state);
14146
14147         if (!obj && !old_obj)
14148                 return;
14149
14150         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14151             !INTEL_INFO(dev)->cursor_needs_physical))
14152                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14153
14154         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14155 }
14156
14157 int
14158 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14159 {
14160         int max_scale;
14161         struct drm_device *dev;
14162         struct drm_i915_private *dev_priv;
14163         int crtc_clock, cdclk;
14164
14165         if (!intel_crtc || !crtc_state->base.enable)
14166                 return DRM_PLANE_HELPER_NO_SCALING;
14167
14168         dev = intel_crtc->base.dev;
14169         dev_priv = dev->dev_private;
14170         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14171         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14172
14173         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14174                 return DRM_PLANE_HELPER_NO_SCALING;
14175
14176         /*
14177          * skl max scale is lower of:
14178          *    close to 3 but not 3, -1 is for that purpose
14179          *            or
14180          *    cdclk/crtc_clock
14181          */
14182         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14183
14184         return max_scale;
14185 }
14186
14187 static int
14188 intel_check_primary_plane(struct drm_plane *plane,
14189                           struct intel_crtc_state *crtc_state,
14190                           struct intel_plane_state *state)
14191 {
14192         struct drm_crtc *crtc = state->base.crtc;
14193         struct drm_framebuffer *fb = state->base.fb;
14194         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14195         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14196         bool can_position = false;
14197
14198         if (INTEL_INFO(plane->dev)->gen >= 9) {
14199                 /* use scaler when colorkey is not required */
14200                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14201                         min_scale = 1;
14202                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14203                 }
14204                 can_position = true;
14205         }
14206
14207         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14208                                              &state->dst, &state->clip,
14209                                              state->base.rotation,
14210                                              min_scale, max_scale,
14211                                              can_position, true,
14212                                              &state->visible);
14213 }
14214
14215 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14216                                     struct drm_crtc_state *old_crtc_state)
14217 {
14218         struct drm_device *dev = crtc->dev;
14219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14220         struct intel_crtc_state *old_intel_state =
14221                 to_intel_crtc_state(old_crtc_state);
14222         bool modeset = needs_modeset(crtc->state);
14223
14224         /* Perform vblank evasion around commit operation */
14225         intel_pipe_update_start(intel_crtc);
14226
14227         if (modeset)
14228                 return;
14229
14230         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14231                 intel_color_set_csc(crtc->state);
14232                 intel_color_load_luts(crtc->state);
14233         }
14234
14235         if (to_intel_crtc_state(crtc->state)->update_pipe)
14236                 intel_update_pipe_config(intel_crtc, old_intel_state);
14237         else if (INTEL_INFO(dev)->gen >= 9)
14238                 skl_detach_scalers(intel_crtc);
14239 }
14240
14241 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14242                                      struct drm_crtc_state *old_crtc_state)
14243 {
14244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14245
14246         intel_pipe_update_end(intel_crtc, NULL);
14247 }
14248
14249 /**
14250  * intel_plane_destroy - destroy a plane
14251  * @plane: plane to destroy
14252  *
14253  * Common destruction function for all types of planes (primary, cursor,
14254  * sprite).
14255  */
14256 void intel_plane_destroy(struct drm_plane *plane)
14257 {
14258         if (!plane)
14259                 return;
14260
14261         drm_plane_cleanup(plane);
14262         kfree(to_intel_plane(plane));
14263 }
14264
14265 const struct drm_plane_funcs intel_plane_funcs = {
14266         .update_plane = drm_atomic_helper_update_plane,
14267         .disable_plane = drm_atomic_helper_disable_plane,
14268         .destroy = intel_plane_destroy,
14269         .set_property = drm_atomic_helper_plane_set_property,
14270         .atomic_get_property = intel_plane_atomic_get_property,
14271         .atomic_set_property = intel_plane_atomic_set_property,
14272         .atomic_duplicate_state = intel_plane_duplicate_state,
14273         .atomic_destroy_state = intel_plane_destroy_state,
14274
14275 };
14276
14277 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14278                                                     int pipe)
14279 {
14280         struct intel_plane *primary = NULL;
14281         struct intel_plane_state *state = NULL;
14282         const uint32_t *intel_primary_formats;
14283         unsigned int num_formats;
14284         int ret;
14285
14286         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14287         if (!primary)
14288                 goto fail;
14289
14290         state = intel_create_plane_state(&primary->base);
14291         if (!state)
14292                 goto fail;
14293         primary->base.state = &state->base;
14294
14295         primary->can_scale = false;
14296         primary->max_downscale = 1;
14297         if (INTEL_INFO(dev)->gen >= 9) {
14298                 primary->can_scale = true;
14299                 state->scaler_id = -1;
14300         }
14301         primary->pipe = pipe;
14302         primary->plane = pipe;
14303         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14304         primary->check_plane = intel_check_primary_plane;
14305         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14306                 primary->plane = !pipe;
14307
14308         if (INTEL_INFO(dev)->gen >= 9) {
14309                 intel_primary_formats = skl_primary_formats;
14310                 num_formats = ARRAY_SIZE(skl_primary_formats);
14311
14312                 primary->update_plane = skylake_update_primary_plane;
14313                 primary->disable_plane = skylake_disable_primary_plane;
14314         } else if (HAS_PCH_SPLIT(dev)) {
14315                 intel_primary_formats = i965_primary_formats;
14316                 num_formats = ARRAY_SIZE(i965_primary_formats);
14317
14318                 primary->update_plane = ironlake_update_primary_plane;
14319                 primary->disable_plane = i9xx_disable_primary_plane;
14320         } else if (INTEL_INFO(dev)->gen >= 4) {
14321                 intel_primary_formats = i965_primary_formats;
14322                 num_formats = ARRAY_SIZE(i965_primary_formats);
14323
14324                 primary->update_plane = i9xx_update_primary_plane;
14325                 primary->disable_plane = i9xx_disable_primary_plane;
14326         } else {
14327                 intel_primary_formats = i8xx_primary_formats;
14328                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14329
14330                 primary->update_plane = i9xx_update_primary_plane;
14331                 primary->disable_plane = i9xx_disable_primary_plane;
14332         }
14333
14334         if (INTEL_INFO(dev)->gen >= 9)
14335                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14336                                                &intel_plane_funcs,
14337                                                intel_primary_formats, num_formats,
14338                                                DRM_PLANE_TYPE_PRIMARY,
14339                                                "plane 1%c", pipe_name(pipe));
14340         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14341                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14342                                                &intel_plane_funcs,
14343                                                intel_primary_formats, num_formats,
14344                                                DRM_PLANE_TYPE_PRIMARY,
14345                                                "primary %c", pipe_name(pipe));
14346         else
14347                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14348                                                &intel_plane_funcs,
14349                                                intel_primary_formats, num_formats,
14350                                                DRM_PLANE_TYPE_PRIMARY,
14351                                                "plane %c", plane_name(primary->plane));
14352         if (ret)
14353                 goto fail;
14354
14355         if (INTEL_INFO(dev)->gen >= 4)
14356                 intel_create_rotation_property(dev, primary);
14357
14358         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14359
14360         return &primary->base;
14361
14362 fail:
14363         kfree(state);
14364         kfree(primary);
14365
14366         return NULL;
14367 }
14368
14369 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14370 {
14371         if (!dev->mode_config.rotation_property) {
14372                 unsigned long flags = BIT(DRM_ROTATE_0) |
14373                         BIT(DRM_ROTATE_180);
14374
14375                 if (INTEL_INFO(dev)->gen >= 9)
14376                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14377
14378                 dev->mode_config.rotation_property =
14379                         drm_mode_create_rotation_property(dev, flags);
14380         }
14381         if (dev->mode_config.rotation_property)
14382                 drm_object_attach_property(&plane->base.base,
14383                                 dev->mode_config.rotation_property,
14384                                 plane->base.state->rotation);
14385 }
14386
14387 static int
14388 intel_check_cursor_plane(struct drm_plane *plane,
14389                          struct intel_crtc_state *crtc_state,
14390                          struct intel_plane_state *state)
14391 {
14392         struct drm_crtc *crtc = crtc_state->base.crtc;
14393         struct drm_framebuffer *fb = state->base.fb;
14394         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14395         enum pipe pipe = to_intel_plane(plane)->pipe;
14396         unsigned stride;
14397         int ret;
14398
14399         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14400                                             &state->dst, &state->clip,
14401                                             state->base.rotation,
14402                                             DRM_PLANE_HELPER_NO_SCALING,
14403                                             DRM_PLANE_HELPER_NO_SCALING,
14404                                             true, true, &state->visible);
14405         if (ret)
14406                 return ret;
14407
14408         /* if we want to turn off the cursor ignore width and height */
14409         if (!obj)
14410                 return 0;
14411
14412         /* Check for which cursor types we support */
14413         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14414                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14415                           state->base.crtc_w, state->base.crtc_h);
14416                 return -EINVAL;
14417         }
14418
14419         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14420         if (obj->base.size < stride * state->base.crtc_h) {
14421                 DRM_DEBUG_KMS("buffer is too small\n");
14422                 return -ENOMEM;
14423         }
14424
14425         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14426                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14427                 return -EINVAL;
14428         }
14429
14430         /*
14431          * There's something wrong with the cursor on CHV pipe C.
14432          * If it straddles the left edge of the screen then
14433          * moving it away from the edge or disabling it often
14434          * results in a pipe underrun, and often that can lead to
14435          * dead pipe (constant underrun reported, and it scans
14436          * out just a solid color). To recover from that, the
14437          * display power well must be turned off and on again.
14438          * Refuse the put the cursor into that compromised position.
14439          */
14440         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14441             state->visible && state->base.crtc_x < 0) {
14442                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14443                 return -EINVAL;
14444         }
14445
14446         return 0;
14447 }
14448
14449 static void
14450 intel_disable_cursor_plane(struct drm_plane *plane,
14451                            struct drm_crtc *crtc)
14452 {
14453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14454
14455         intel_crtc->cursor_addr = 0;
14456         intel_crtc_update_cursor(crtc, NULL);
14457 }
14458
14459 static void
14460 intel_update_cursor_plane(struct drm_plane *plane,
14461                           const struct intel_crtc_state *crtc_state,
14462                           const struct intel_plane_state *state)
14463 {
14464         struct drm_crtc *crtc = crtc_state->base.crtc;
14465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14466         struct drm_device *dev = plane->dev;
14467         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14468         uint32_t addr;
14469
14470         if (!obj)
14471                 addr = 0;
14472         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14473                 addr = i915_gem_obj_ggtt_offset(obj);
14474         else
14475                 addr = obj->phys_handle->busaddr;
14476
14477         intel_crtc->cursor_addr = addr;
14478         intel_crtc_update_cursor(crtc, state);
14479 }
14480
14481 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14482                                                    int pipe)
14483 {
14484         struct intel_plane *cursor = NULL;
14485         struct intel_plane_state *state = NULL;
14486         int ret;
14487
14488         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14489         if (!cursor)
14490                 goto fail;
14491
14492         state = intel_create_plane_state(&cursor->base);
14493         if (!state)
14494                 goto fail;
14495         cursor->base.state = &state->base;
14496
14497         cursor->can_scale = false;
14498         cursor->max_downscale = 1;
14499         cursor->pipe = pipe;
14500         cursor->plane = pipe;
14501         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14502         cursor->check_plane = intel_check_cursor_plane;
14503         cursor->update_plane = intel_update_cursor_plane;
14504         cursor->disable_plane = intel_disable_cursor_plane;
14505
14506         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14507                                        &intel_plane_funcs,
14508                                        intel_cursor_formats,
14509                                        ARRAY_SIZE(intel_cursor_formats),
14510                                        DRM_PLANE_TYPE_CURSOR,
14511                                        "cursor %c", pipe_name(pipe));
14512         if (ret)
14513                 goto fail;
14514
14515         if (INTEL_INFO(dev)->gen >= 4) {
14516                 if (!dev->mode_config.rotation_property)
14517                         dev->mode_config.rotation_property =
14518                                 drm_mode_create_rotation_property(dev,
14519                                                         BIT(DRM_ROTATE_0) |
14520                                                         BIT(DRM_ROTATE_180));
14521                 if (dev->mode_config.rotation_property)
14522                         drm_object_attach_property(&cursor->base.base,
14523                                 dev->mode_config.rotation_property,
14524                                 state->base.rotation);
14525         }
14526
14527         if (INTEL_INFO(dev)->gen >=9)
14528                 state->scaler_id = -1;
14529
14530         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14531
14532         return &cursor->base;
14533
14534 fail:
14535         kfree(state);
14536         kfree(cursor);
14537
14538         return NULL;
14539 }
14540
14541 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14542         struct intel_crtc_state *crtc_state)
14543 {
14544         int i;
14545         struct intel_scaler *intel_scaler;
14546         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14547
14548         for (i = 0; i < intel_crtc->num_scalers; i++) {
14549                 intel_scaler = &scaler_state->scalers[i];
14550                 intel_scaler->in_use = 0;
14551                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14552         }
14553
14554         scaler_state->scaler_id = -1;
14555 }
14556
14557 static void intel_crtc_init(struct drm_device *dev, int pipe)
14558 {
14559         struct drm_i915_private *dev_priv = dev->dev_private;
14560         struct intel_crtc *intel_crtc;
14561         struct intel_crtc_state *crtc_state = NULL;
14562         struct drm_plane *primary = NULL;
14563         struct drm_plane *cursor = NULL;
14564         int ret;
14565
14566         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14567         if (intel_crtc == NULL)
14568                 return;
14569
14570         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14571         if (!crtc_state)
14572                 goto fail;
14573         intel_crtc->config = crtc_state;
14574         intel_crtc->base.state = &crtc_state->base;
14575         crtc_state->base.crtc = &intel_crtc->base;
14576
14577         /* initialize shared scalers */
14578         if (INTEL_INFO(dev)->gen >= 9) {
14579                 if (pipe == PIPE_C)
14580                         intel_crtc->num_scalers = 1;
14581                 else
14582                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14583
14584                 skl_init_scalers(dev, intel_crtc, crtc_state);
14585         }
14586
14587         primary = intel_primary_plane_create(dev, pipe);
14588         if (!primary)
14589                 goto fail;
14590
14591         cursor = intel_cursor_plane_create(dev, pipe);
14592         if (!cursor)
14593                 goto fail;
14594
14595         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14596                                         cursor, &intel_crtc_funcs,
14597                                         "pipe %c", pipe_name(pipe));
14598         if (ret)
14599                 goto fail;
14600
14601         /*
14602          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14603          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14604          */
14605         intel_crtc->pipe = pipe;
14606         intel_crtc->plane = pipe;
14607         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14608                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14609                 intel_crtc->plane = !pipe;
14610         }
14611
14612         intel_crtc->cursor_base = ~0;
14613         intel_crtc->cursor_cntl = ~0;
14614         intel_crtc->cursor_size = ~0;
14615
14616         intel_crtc->wm.cxsr_allowed = true;
14617
14618         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14619                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14620         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14621         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14622
14623         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14624
14625         intel_color_init(&intel_crtc->base);
14626
14627         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14628         return;
14629
14630 fail:
14631         intel_plane_destroy(primary);
14632         intel_plane_destroy(cursor);
14633         kfree(crtc_state);
14634         kfree(intel_crtc);
14635 }
14636
14637 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14638 {
14639         struct drm_encoder *encoder = connector->base.encoder;
14640         struct drm_device *dev = connector->base.dev;
14641
14642         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14643
14644         if (!encoder || WARN_ON(!encoder->crtc))
14645                 return INVALID_PIPE;
14646
14647         return to_intel_crtc(encoder->crtc)->pipe;
14648 }
14649
14650 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14651                                 struct drm_file *file)
14652 {
14653         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14654         struct drm_crtc *drmmode_crtc;
14655         struct intel_crtc *crtc;
14656
14657         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14658         if (!drmmode_crtc)
14659                 return -ENOENT;
14660
14661         crtc = to_intel_crtc(drmmode_crtc);
14662         pipe_from_crtc_id->pipe = crtc->pipe;
14663
14664         return 0;
14665 }
14666
14667 static int intel_encoder_clones(struct intel_encoder *encoder)
14668 {
14669         struct drm_device *dev = encoder->base.dev;
14670         struct intel_encoder *source_encoder;
14671         int index_mask = 0;
14672         int entry = 0;
14673
14674         for_each_intel_encoder(dev, source_encoder) {
14675                 if (encoders_cloneable(encoder, source_encoder))
14676                         index_mask |= (1 << entry);
14677
14678                 entry++;
14679         }
14680
14681         return index_mask;
14682 }
14683
14684 static bool has_edp_a(struct drm_device *dev)
14685 {
14686         struct drm_i915_private *dev_priv = dev->dev_private;
14687
14688         if (!IS_MOBILE(dev))
14689                 return false;
14690
14691         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14692                 return false;
14693
14694         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14695                 return false;
14696
14697         return true;
14698 }
14699
14700 static bool intel_crt_present(struct drm_device *dev)
14701 {
14702         struct drm_i915_private *dev_priv = dev->dev_private;
14703
14704         if (INTEL_INFO(dev)->gen >= 9)
14705                 return false;
14706
14707         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14708                 return false;
14709
14710         if (IS_CHERRYVIEW(dev))
14711                 return false;
14712
14713         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14714                 return false;
14715
14716         /* DDI E can't be used if DDI A requires 4 lanes */
14717         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14718                 return false;
14719
14720         if (!dev_priv->vbt.int_crt_support)
14721                 return false;
14722
14723         return true;
14724 }
14725
14726 static void intel_setup_outputs(struct drm_device *dev)
14727 {
14728         struct drm_i915_private *dev_priv = dev->dev_private;
14729         struct intel_encoder *encoder;
14730         bool dpd_is_edp = false;
14731
14732         /*
14733          * intel_edp_init_connector() depends on this completing first, to
14734          * prevent the registeration of both eDP and LVDS and the incorrect
14735          * sharing of the PPS.
14736          */
14737         intel_lvds_init(dev);
14738
14739         if (intel_crt_present(dev))
14740                 intel_crt_init(dev);
14741
14742         if (IS_BROXTON(dev)) {
14743                 /*
14744                  * FIXME: Broxton doesn't support port detection via the
14745                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14746                  * detect the ports.
14747                  */
14748                 intel_ddi_init(dev, PORT_A);
14749                 intel_ddi_init(dev, PORT_B);
14750                 intel_ddi_init(dev, PORT_C);
14751
14752                 intel_dsi_init(dev);
14753         } else if (HAS_DDI(dev)) {
14754                 int found;
14755
14756                 /*
14757                  * Haswell uses DDI functions to detect digital outputs.
14758                  * On SKL pre-D0 the strap isn't connected, so we assume
14759                  * it's there.
14760                  */
14761                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14762                 /* WaIgnoreDDIAStrap: skl */
14763                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14764                         intel_ddi_init(dev, PORT_A);
14765
14766                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14767                  * register */
14768                 found = I915_READ(SFUSE_STRAP);
14769
14770                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14771                         intel_ddi_init(dev, PORT_B);
14772                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14773                         intel_ddi_init(dev, PORT_C);
14774                 if (found & SFUSE_STRAP_DDID_DETECTED)
14775                         intel_ddi_init(dev, PORT_D);
14776                 /*
14777                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14778                  */
14779                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14780                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14781                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14782                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14783                         intel_ddi_init(dev, PORT_E);
14784
14785         } else if (HAS_PCH_SPLIT(dev)) {
14786                 int found;
14787                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14788
14789                 if (has_edp_a(dev))
14790                         intel_dp_init(dev, DP_A, PORT_A);
14791
14792                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14793                         /* PCH SDVOB multiplex with HDMIB */
14794                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14795                         if (!found)
14796                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14797                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14798                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14799                 }
14800
14801                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14802                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14803
14804                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14805                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14806
14807                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14808                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14809
14810                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14811                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14812         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14813                 bool has_edp, has_port;
14814
14815                 /*
14816                  * The DP_DETECTED bit is the latched state of the DDC
14817                  * SDA pin at boot. However since eDP doesn't require DDC
14818                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14819                  * eDP ports may have been muxed to an alternate function.
14820                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14821                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14822                  * detect eDP ports.
14823                  *
14824                  * Sadly the straps seem to be missing sometimes even for HDMI
14825                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14826                  * and VBT for the presence of the port. Additionally we can't
14827                  * trust the port type the VBT declares as we've seen at least
14828                  * HDMI ports that the VBT claim are DP or eDP.
14829                  */
14830                 has_edp = intel_dp_is_edp(dev, PORT_B);
14831                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14832                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14833                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14834                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14835                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14836
14837                 has_edp = intel_dp_is_edp(dev, PORT_C);
14838                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14839                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14840                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14841                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14842                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14843
14844                 if (IS_CHERRYVIEW(dev)) {
14845                         /*
14846                          * eDP not supported on port D,
14847                          * so no need to worry about it
14848                          */
14849                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14850                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14851                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14852                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14853                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14854                 }
14855
14856                 intel_dsi_init(dev);
14857         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14858                 bool found = false;
14859
14860                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14861                         DRM_DEBUG_KMS("probing SDVOB\n");
14862                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14863                         if (!found && IS_G4X(dev)) {
14864                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14865                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14866                         }
14867
14868                         if (!found && IS_G4X(dev))
14869                                 intel_dp_init(dev, DP_B, PORT_B);
14870                 }
14871
14872                 /* Before G4X SDVOC doesn't have its own detect register */
14873
14874                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14875                         DRM_DEBUG_KMS("probing SDVOC\n");
14876                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14877                 }
14878
14879                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14880
14881                         if (IS_G4X(dev)) {
14882                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14883                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14884                         }
14885                         if (IS_G4X(dev))
14886                                 intel_dp_init(dev, DP_C, PORT_C);
14887                 }
14888
14889                 if (IS_G4X(dev) &&
14890                     (I915_READ(DP_D) & DP_DETECTED))
14891                         intel_dp_init(dev, DP_D, PORT_D);
14892         } else if (IS_GEN2(dev))
14893                 intel_dvo_init(dev);
14894
14895         if (SUPPORTS_TV(dev))
14896                 intel_tv_init(dev);
14897
14898         intel_psr_init(dev);
14899
14900         for_each_intel_encoder(dev, encoder) {
14901                 encoder->base.possible_crtcs = encoder->crtc_mask;
14902                 encoder->base.possible_clones =
14903                         intel_encoder_clones(encoder);
14904         }
14905
14906         intel_init_pch_refclk(dev);
14907
14908         drm_helper_move_panel_connectors_to_head(dev);
14909 }
14910
14911 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14912 {
14913         struct drm_device *dev = fb->dev;
14914         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14915
14916         drm_framebuffer_cleanup(fb);
14917         mutex_lock(&dev->struct_mutex);
14918         WARN_ON(!intel_fb->obj->framebuffer_references--);
14919         drm_gem_object_unreference(&intel_fb->obj->base);
14920         mutex_unlock(&dev->struct_mutex);
14921         kfree(intel_fb);
14922 }
14923
14924 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14925                                                 struct drm_file *file,
14926                                                 unsigned int *handle)
14927 {
14928         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14929         struct drm_i915_gem_object *obj = intel_fb->obj;
14930
14931         if (obj->userptr.mm) {
14932                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14933                 return -EINVAL;
14934         }
14935
14936         return drm_gem_handle_create(file, &obj->base, handle);
14937 }
14938
14939 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14940                                         struct drm_file *file,
14941                                         unsigned flags, unsigned color,
14942                                         struct drm_clip_rect *clips,
14943                                         unsigned num_clips)
14944 {
14945         struct drm_device *dev = fb->dev;
14946         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14947         struct drm_i915_gem_object *obj = intel_fb->obj;
14948
14949         mutex_lock(&dev->struct_mutex);
14950         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14951         mutex_unlock(&dev->struct_mutex);
14952
14953         return 0;
14954 }
14955
14956 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14957         .destroy = intel_user_framebuffer_destroy,
14958         .create_handle = intel_user_framebuffer_create_handle,
14959         .dirty = intel_user_framebuffer_dirty,
14960 };
14961
14962 static
14963 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14964                          uint32_t pixel_format)
14965 {
14966         u32 gen = INTEL_INFO(dev)->gen;
14967
14968         if (gen >= 9) {
14969                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14970
14971                 /* "The stride in bytes must not exceed the of the size of 8K
14972                  *  pixels and 32K bytes."
14973                  */
14974                 return min(8192 * cpp, 32768);
14975         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14976                 return 32*1024;
14977         } else if (gen >= 4) {
14978                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14979                         return 16*1024;
14980                 else
14981                         return 32*1024;
14982         } else if (gen >= 3) {
14983                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14984                         return 8*1024;
14985                 else
14986                         return 16*1024;
14987         } else {
14988                 /* XXX DSPC is limited to 4k tiled */
14989                 return 8*1024;
14990         }
14991 }
14992
14993 static int intel_framebuffer_init(struct drm_device *dev,
14994                                   struct intel_framebuffer *intel_fb,
14995                                   struct drm_mode_fb_cmd2 *mode_cmd,
14996                                   struct drm_i915_gem_object *obj)
14997 {
14998         struct drm_i915_private *dev_priv = to_i915(dev);
14999         unsigned int aligned_height;
15000         int ret;
15001         u32 pitch_limit, stride_alignment;
15002
15003         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15004
15005         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15006                 /* Enforce that fb modifier and tiling mode match, but only for
15007                  * X-tiled. This is needed for FBC. */
15008                 if (!!(obj->tiling_mode == I915_TILING_X) !=
15009                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
15010                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15011                         return -EINVAL;
15012                 }
15013         } else {
15014                 if (obj->tiling_mode == I915_TILING_X)
15015                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15016                 else if (obj->tiling_mode == I915_TILING_Y) {
15017                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15018                         return -EINVAL;
15019                 }
15020         }
15021
15022         /* Passed in modifier sanity checking. */
15023         switch (mode_cmd->modifier[0]) {
15024         case I915_FORMAT_MOD_Y_TILED:
15025         case I915_FORMAT_MOD_Yf_TILED:
15026                 if (INTEL_INFO(dev)->gen < 9) {
15027                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15028                                   mode_cmd->modifier[0]);
15029                         return -EINVAL;
15030                 }
15031         case DRM_FORMAT_MOD_NONE:
15032         case I915_FORMAT_MOD_X_TILED:
15033                 break;
15034         default:
15035                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15036                           mode_cmd->modifier[0]);
15037                 return -EINVAL;
15038         }
15039
15040         stride_alignment = intel_fb_stride_alignment(dev_priv,
15041                                                      mode_cmd->modifier[0],
15042                                                      mode_cmd->pixel_format);
15043         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15044                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15045                           mode_cmd->pitches[0], stride_alignment);
15046                 return -EINVAL;
15047         }
15048
15049         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15050                                            mode_cmd->pixel_format);
15051         if (mode_cmd->pitches[0] > pitch_limit) {
15052                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15053                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15054                           "tiled" : "linear",
15055                           mode_cmd->pitches[0], pitch_limit);
15056                 return -EINVAL;
15057         }
15058
15059         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
15060             mode_cmd->pitches[0] != obj->stride) {
15061                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15062                           mode_cmd->pitches[0], obj->stride);
15063                 return -EINVAL;
15064         }
15065
15066         /* Reject formats not supported by any plane early. */
15067         switch (mode_cmd->pixel_format) {
15068         case DRM_FORMAT_C8:
15069         case DRM_FORMAT_RGB565:
15070         case DRM_FORMAT_XRGB8888:
15071         case DRM_FORMAT_ARGB8888:
15072                 break;
15073         case DRM_FORMAT_XRGB1555:
15074                 if (INTEL_INFO(dev)->gen > 3) {
15075                         DRM_DEBUG("unsupported pixel format: %s\n",
15076                                   drm_get_format_name(mode_cmd->pixel_format));
15077                         return -EINVAL;
15078                 }
15079                 break;
15080         case DRM_FORMAT_ABGR8888:
15081                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15082                     INTEL_INFO(dev)->gen < 9) {
15083                         DRM_DEBUG("unsupported pixel format: %s\n",
15084                                   drm_get_format_name(mode_cmd->pixel_format));
15085                         return -EINVAL;
15086                 }
15087                 break;
15088         case DRM_FORMAT_XBGR8888:
15089         case DRM_FORMAT_XRGB2101010:
15090         case DRM_FORMAT_XBGR2101010:
15091                 if (INTEL_INFO(dev)->gen < 4) {
15092                         DRM_DEBUG("unsupported pixel format: %s\n",
15093                                   drm_get_format_name(mode_cmd->pixel_format));
15094                         return -EINVAL;
15095                 }
15096                 break;
15097         case DRM_FORMAT_ABGR2101010:
15098                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15099                         DRM_DEBUG("unsupported pixel format: %s\n",
15100                                   drm_get_format_name(mode_cmd->pixel_format));
15101                         return -EINVAL;
15102                 }
15103                 break;
15104         case DRM_FORMAT_YUYV:
15105         case DRM_FORMAT_UYVY:
15106         case DRM_FORMAT_YVYU:
15107         case DRM_FORMAT_VYUY:
15108                 if (INTEL_INFO(dev)->gen < 5) {
15109                         DRM_DEBUG("unsupported pixel format: %s\n",
15110                                   drm_get_format_name(mode_cmd->pixel_format));
15111                         return -EINVAL;
15112                 }
15113                 break;
15114         default:
15115                 DRM_DEBUG("unsupported pixel format: %s\n",
15116                           drm_get_format_name(mode_cmd->pixel_format));
15117                 return -EINVAL;
15118         }
15119
15120         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15121         if (mode_cmd->offsets[0] != 0)
15122                 return -EINVAL;
15123
15124         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15125                                                mode_cmd->pixel_format,
15126                                                mode_cmd->modifier[0]);
15127         /* FIXME drm helper for size checks (especially planar formats)? */
15128         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15129                 return -EINVAL;
15130
15131         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15132         intel_fb->obj = obj;
15133
15134         intel_fill_fb_info(dev_priv, &intel_fb->base);
15135
15136         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15137         if (ret) {
15138                 DRM_ERROR("framebuffer init failed %d\n", ret);
15139                 return ret;
15140         }
15141
15142         intel_fb->obj->framebuffer_references++;
15143
15144         return 0;
15145 }
15146
15147 static struct drm_framebuffer *
15148 intel_user_framebuffer_create(struct drm_device *dev,
15149                               struct drm_file *filp,
15150                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15151 {
15152         struct drm_framebuffer *fb;
15153         struct drm_i915_gem_object *obj;
15154         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15155
15156         obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15157         if (&obj->base == NULL)
15158                 return ERR_PTR(-ENOENT);
15159
15160         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15161         if (IS_ERR(fb))
15162                 drm_gem_object_unreference_unlocked(&obj->base);
15163
15164         return fb;
15165 }
15166
15167 #ifndef CONFIG_DRM_FBDEV_EMULATION
15168 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15169 {
15170 }
15171 #endif
15172
15173 static const struct drm_mode_config_funcs intel_mode_funcs = {
15174         .fb_create = intel_user_framebuffer_create,
15175         .output_poll_changed = intel_fbdev_output_poll_changed,
15176         .atomic_check = intel_atomic_check,
15177         .atomic_commit = intel_atomic_commit,
15178         .atomic_state_alloc = intel_atomic_state_alloc,
15179         .atomic_state_clear = intel_atomic_state_clear,
15180 };
15181
15182 /**
15183  * intel_init_display_hooks - initialize the display modesetting hooks
15184  * @dev_priv: device private
15185  */
15186 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15187 {
15188         if (INTEL_INFO(dev_priv)->gen >= 9) {
15189                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15190                 dev_priv->display.get_initial_plane_config =
15191                         skylake_get_initial_plane_config;
15192                 dev_priv->display.crtc_compute_clock =
15193                         haswell_crtc_compute_clock;
15194                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15195                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15196         } else if (HAS_DDI(dev_priv)) {
15197                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15198                 dev_priv->display.get_initial_plane_config =
15199                         ironlake_get_initial_plane_config;
15200                 dev_priv->display.crtc_compute_clock =
15201                         haswell_crtc_compute_clock;
15202                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15203                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15204         } else if (HAS_PCH_SPLIT(dev_priv)) {
15205                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15206                 dev_priv->display.get_initial_plane_config =
15207                         ironlake_get_initial_plane_config;
15208                 dev_priv->display.crtc_compute_clock =
15209                         ironlake_crtc_compute_clock;
15210                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15211                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15212         } else if (IS_CHERRYVIEW(dev_priv)) {
15213                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15214                 dev_priv->display.get_initial_plane_config =
15215                         i9xx_get_initial_plane_config;
15216                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15217                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15218                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15219         } else if (IS_VALLEYVIEW(dev_priv)) {
15220                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15221                 dev_priv->display.get_initial_plane_config =
15222                         i9xx_get_initial_plane_config;
15223                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15224                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15225                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15226         } else if (IS_G4X(dev_priv)) {
15227                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15228                 dev_priv->display.get_initial_plane_config =
15229                         i9xx_get_initial_plane_config;
15230                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15231                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15232                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15233         } else if (IS_PINEVIEW(dev_priv)) {
15234                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15235                 dev_priv->display.get_initial_plane_config =
15236                         i9xx_get_initial_plane_config;
15237                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15238                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15239                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15240         } else if (!IS_GEN2(dev_priv)) {
15241                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15242                 dev_priv->display.get_initial_plane_config =
15243                         i9xx_get_initial_plane_config;
15244                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15245                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15246                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15247         } else {
15248                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15249                 dev_priv->display.get_initial_plane_config =
15250                         i9xx_get_initial_plane_config;
15251                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15252                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15253                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15254         }
15255
15256         /* Returns the core display clock speed */
15257         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15258                 dev_priv->display.get_display_clock_speed =
15259                         skylake_get_display_clock_speed;
15260         else if (IS_BROXTON(dev_priv))
15261                 dev_priv->display.get_display_clock_speed =
15262                         broxton_get_display_clock_speed;
15263         else if (IS_BROADWELL(dev_priv))
15264                 dev_priv->display.get_display_clock_speed =
15265                         broadwell_get_display_clock_speed;
15266         else if (IS_HASWELL(dev_priv))
15267                 dev_priv->display.get_display_clock_speed =
15268                         haswell_get_display_clock_speed;
15269         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15270                 dev_priv->display.get_display_clock_speed =
15271                         valleyview_get_display_clock_speed;
15272         else if (IS_GEN5(dev_priv))
15273                 dev_priv->display.get_display_clock_speed =
15274                         ilk_get_display_clock_speed;
15275         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15276                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15277                 dev_priv->display.get_display_clock_speed =
15278                         i945_get_display_clock_speed;
15279         else if (IS_GM45(dev_priv))
15280                 dev_priv->display.get_display_clock_speed =
15281                         gm45_get_display_clock_speed;
15282         else if (IS_CRESTLINE(dev_priv))
15283                 dev_priv->display.get_display_clock_speed =
15284                         i965gm_get_display_clock_speed;
15285         else if (IS_PINEVIEW(dev_priv))
15286                 dev_priv->display.get_display_clock_speed =
15287                         pnv_get_display_clock_speed;
15288         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15289                 dev_priv->display.get_display_clock_speed =
15290                         g33_get_display_clock_speed;
15291         else if (IS_I915G(dev_priv))
15292                 dev_priv->display.get_display_clock_speed =
15293                         i915_get_display_clock_speed;
15294         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15295                 dev_priv->display.get_display_clock_speed =
15296                         i9xx_misc_get_display_clock_speed;
15297         else if (IS_I915GM(dev_priv))
15298                 dev_priv->display.get_display_clock_speed =
15299                         i915gm_get_display_clock_speed;
15300         else if (IS_I865G(dev_priv))
15301                 dev_priv->display.get_display_clock_speed =
15302                         i865_get_display_clock_speed;
15303         else if (IS_I85X(dev_priv))
15304                 dev_priv->display.get_display_clock_speed =
15305                         i85x_get_display_clock_speed;
15306         else { /* 830 */
15307                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15308                 dev_priv->display.get_display_clock_speed =
15309                         i830_get_display_clock_speed;
15310         }
15311
15312         if (IS_GEN5(dev_priv)) {
15313                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15314         } else if (IS_GEN6(dev_priv)) {
15315                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15316         } else if (IS_IVYBRIDGE(dev_priv)) {
15317                 /* FIXME: detect B0+ stepping and use auto training */
15318                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15319         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15320                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15321         }
15322
15323         if (IS_BROADWELL(dev_priv)) {
15324                 dev_priv->display.modeset_commit_cdclk =
15325                         broadwell_modeset_commit_cdclk;
15326                 dev_priv->display.modeset_calc_cdclk =
15327                         broadwell_modeset_calc_cdclk;
15328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15329                 dev_priv->display.modeset_commit_cdclk =
15330                         valleyview_modeset_commit_cdclk;
15331                 dev_priv->display.modeset_calc_cdclk =
15332                         valleyview_modeset_calc_cdclk;
15333         } else if (IS_BROXTON(dev_priv)) {
15334                 dev_priv->display.modeset_commit_cdclk =
15335                         bxt_modeset_commit_cdclk;
15336                 dev_priv->display.modeset_calc_cdclk =
15337                         bxt_modeset_calc_cdclk;
15338         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15339                 dev_priv->display.modeset_commit_cdclk =
15340                         skl_modeset_commit_cdclk;
15341                 dev_priv->display.modeset_calc_cdclk =
15342                         skl_modeset_calc_cdclk;
15343         }
15344
15345         switch (INTEL_INFO(dev_priv)->gen) {
15346         case 2:
15347                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15348                 break;
15349
15350         case 3:
15351                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15352                 break;
15353
15354         case 4:
15355         case 5:
15356                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15357                 break;
15358
15359         case 6:
15360                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15361                 break;
15362         case 7:
15363         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15364                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15365                 break;
15366         case 9:
15367                 /* Drop through - unsupported since execlist only. */
15368         default:
15369                 /* Default just returns -ENODEV to indicate unsupported */
15370                 dev_priv->display.queue_flip = intel_default_queue_flip;
15371         }
15372 }
15373
15374 /*
15375  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15376  * resume, or other times.  This quirk makes sure that's the case for
15377  * affected systems.
15378  */
15379 static void quirk_pipea_force(struct drm_device *dev)
15380 {
15381         struct drm_i915_private *dev_priv = dev->dev_private;
15382
15383         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15384         DRM_INFO("applying pipe a force quirk\n");
15385 }
15386
15387 static void quirk_pipeb_force(struct drm_device *dev)
15388 {
15389         struct drm_i915_private *dev_priv = dev->dev_private;
15390
15391         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15392         DRM_INFO("applying pipe b force quirk\n");
15393 }
15394
15395 /*
15396  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15397  */
15398 static void quirk_ssc_force_disable(struct drm_device *dev)
15399 {
15400         struct drm_i915_private *dev_priv = dev->dev_private;
15401         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15402         DRM_INFO("applying lvds SSC disable quirk\n");
15403 }
15404
15405 /*
15406  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15407  * brightness value
15408  */
15409 static void quirk_invert_brightness(struct drm_device *dev)
15410 {
15411         struct drm_i915_private *dev_priv = dev->dev_private;
15412         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15413         DRM_INFO("applying inverted panel brightness quirk\n");
15414 }
15415
15416 /* Some VBT's incorrectly indicate no backlight is present */
15417 static void quirk_backlight_present(struct drm_device *dev)
15418 {
15419         struct drm_i915_private *dev_priv = dev->dev_private;
15420         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15421         DRM_INFO("applying backlight present quirk\n");
15422 }
15423
15424 struct intel_quirk {
15425         int device;
15426         int subsystem_vendor;
15427         int subsystem_device;
15428         void (*hook)(struct drm_device *dev);
15429 };
15430
15431 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15432 struct intel_dmi_quirk {
15433         void (*hook)(struct drm_device *dev);
15434         const struct dmi_system_id (*dmi_id_list)[];
15435 };
15436
15437 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15438 {
15439         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15440         return 1;
15441 }
15442
15443 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15444         {
15445                 .dmi_id_list = &(const struct dmi_system_id[]) {
15446                         {
15447                                 .callback = intel_dmi_reverse_brightness,
15448                                 .ident = "NCR Corporation",
15449                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15450                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15451                                 },
15452                         },
15453                         { }  /* terminating entry */
15454                 },
15455                 .hook = quirk_invert_brightness,
15456         },
15457 };
15458
15459 static struct intel_quirk intel_quirks[] = {
15460         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15461         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15462
15463         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15464         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15465
15466         /* 830 needs to leave pipe A & dpll A up */
15467         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15468
15469         /* 830 needs to leave pipe B & dpll B up */
15470         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15471
15472         /* Lenovo U160 cannot use SSC on LVDS */
15473         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15474
15475         /* Sony Vaio Y cannot use SSC on LVDS */
15476         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15477
15478         /* Acer Aspire 5734Z must invert backlight brightness */
15479         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15480
15481         /* Acer/eMachines G725 */
15482         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15483
15484         /* Acer/eMachines e725 */
15485         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15486
15487         /* Acer/Packard Bell NCL20 */
15488         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15489
15490         /* Acer Aspire 4736Z */
15491         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15492
15493         /* Acer Aspire 5336 */
15494         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15495
15496         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15497         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15498
15499         /* Acer C720 Chromebook (Core i3 4005U) */
15500         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15501
15502         /* Apple Macbook 2,1 (Core 2 T7400) */
15503         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15504
15505         /* Apple Macbook 4,1 */
15506         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15507
15508         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15509         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15510
15511         /* HP Chromebook 14 (Celeron 2955U) */
15512         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15513
15514         /* Dell Chromebook 11 */
15515         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15516
15517         /* Dell Chromebook 11 (2015 version) */
15518         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15519 };
15520
15521 static void intel_init_quirks(struct drm_device *dev)
15522 {
15523         struct pci_dev *d = dev->pdev;
15524         int i;
15525
15526         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15527                 struct intel_quirk *q = &intel_quirks[i];
15528
15529                 if (d->device == q->device &&
15530                     (d->subsystem_vendor == q->subsystem_vendor ||
15531                      q->subsystem_vendor == PCI_ANY_ID) &&
15532                     (d->subsystem_device == q->subsystem_device ||
15533                      q->subsystem_device == PCI_ANY_ID))
15534                         q->hook(dev);
15535         }
15536         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15537                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15538                         intel_dmi_quirks[i].hook(dev);
15539         }
15540 }
15541
15542 /* Disable the VGA plane that we never use */
15543 static void i915_disable_vga(struct drm_device *dev)
15544 {
15545         struct drm_i915_private *dev_priv = dev->dev_private;
15546         u8 sr1;
15547         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15548
15549         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15550         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15551         outb(SR01, VGA_SR_INDEX);
15552         sr1 = inb(VGA_SR_DATA);
15553         outb(sr1 | 1<<5, VGA_SR_DATA);
15554         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15555         udelay(300);
15556
15557         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15558         POSTING_READ(vga_reg);
15559 }
15560
15561 void intel_modeset_init_hw(struct drm_device *dev)
15562 {
15563         struct drm_i915_private *dev_priv = dev->dev_private;
15564
15565         intel_update_cdclk(dev);
15566
15567         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15568
15569         intel_init_clock_gating(dev);
15570         intel_enable_gt_powersave(dev_priv);
15571 }
15572
15573 /*
15574  * Calculate what we think the watermarks should be for the state we've read
15575  * out of the hardware and then immediately program those watermarks so that
15576  * we ensure the hardware settings match our internal state.
15577  *
15578  * We can calculate what we think WM's should be by creating a duplicate of the
15579  * current state (which was constructed during hardware readout) and running it
15580  * through the atomic check code to calculate new watermark values in the
15581  * state object.
15582  */
15583 static void sanitize_watermarks(struct drm_device *dev)
15584 {
15585         struct drm_i915_private *dev_priv = to_i915(dev);
15586         struct drm_atomic_state *state;
15587         struct drm_crtc *crtc;
15588         struct drm_crtc_state *cstate;
15589         struct drm_modeset_acquire_ctx ctx;
15590         int ret;
15591         int i;
15592
15593         /* Only supported on platforms that use atomic watermark design */
15594         if (!dev_priv->display.optimize_watermarks)
15595                 return;
15596
15597         /*
15598          * We need to hold connection_mutex before calling duplicate_state so
15599          * that the connector loop is protected.
15600          */
15601         drm_modeset_acquire_init(&ctx, 0);
15602 retry:
15603         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15604         if (ret == -EDEADLK) {
15605                 drm_modeset_backoff(&ctx);
15606                 goto retry;
15607         } else if (WARN_ON(ret)) {
15608                 goto fail;
15609         }
15610
15611         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15612         if (WARN_ON(IS_ERR(state)))
15613                 goto fail;
15614
15615         /*
15616          * Hardware readout is the only time we don't want to calculate
15617          * intermediate watermarks (since we don't trust the current
15618          * watermarks).
15619          */
15620         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15621
15622         ret = intel_atomic_check(dev, state);
15623         if (ret) {
15624                 /*
15625                  * If we fail here, it means that the hardware appears to be
15626                  * programmed in a way that shouldn't be possible, given our
15627                  * understanding of watermark requirements.  This might mean a
15628                  * mistake in the hardware readout code or a mistake in the
15629                  * watermark calculations for a given platform.  Raise a WARN
15630                  * so that this is noticeable.
15631                  *
15632                  * If this actually happens, we'll have to just leave the
15633                  * BIOS-programmed watermarks untouched and hope for the best.
15634                  */
15635                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15636                 goto fail;
15637         }
15638
15639         /* Write calculated watermark values back */
15640         for_each_crtc_in_state(state, crtc, cstate, i) {
15641                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15642
15643                 cs->wm.need_postvbl_update = true;
15644                 dev_priv->display.optimize_watermarks(cs);
15645         }
15646
15647         drm_atomic_state_free(state);
15648 fail:
15649         drm_modeset_drop_locks(&ctx);
15650         drm_modeset_acquire_fini(&ctx);
15651 }
15652
15653 void intel_modeset_init(struct drm_device *dev)
15654 {
15655         struct drm_i915_private *dev_priv = to_i915(dev);
15656         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15657         int sprite, ret;
15658         enum pipe pipe;
15659         struct intel_crtc *crtc;
15660
15661         drm_mode_config_init(dev);
15662
15663         dev->mode_config.min_width = 0;
15664         dev->mode_config.min_height = 0;
15665
15666         dev->mode_config.preferred_depth = 24;
15667         dev->mode_config.prefer_shadow = 1;
15668
15669         dev->mode_config.allow_fb_modifiers = true;
15670
15671         dev->mode_config.funcs = &intel_mode_funcs;
15672
15673         intel_init_quirks(dev);
15674
15675         intel_init_pm(dev);
15676
15677         if (INTEL_INFO(dev)->num_pipes == 0)
15678                 return;
15679
15680         /*
15681          * There may be no VBT; and if the BIOS enabled SSC we can
15682          * just keep using it to avoid unnecessary flicker.  Whereas if the
15683          * BIOS isn't using it, don't assume it will work even if the VBT
15684          * indicates as much.
15685          */
15686         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15687                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15688                                             DREF_SSC1_ENABLE);
15689
15690                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15691                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15692                                      bios_lvds_use_ssc ? "en" : "dis",
15693                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15694                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15695                 }
15696         }
15697
15698         if (IS_GEN2(dev)) {
15699                 dev->mode_config.max_width = 2048;
15700                 dev->mode_config.max_height = 2048;
15701         } else if (IS_GEN3(dev)) {
15702                 dev->mode_config.max_width = 4096;
15703                 dev->mode_config.max_height = 4096;
15704         } else {
15705                 dev->mode_config.max_width = 8192;
15706                 dev->mode_config.max_height = 8192;
15707         }
15708
15709         if (IS_845G(dev) || IS_I865G(dev)) {
15710                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15711                 dev->mode_config.cursor_height = 1023;
15712         } else if (IS_GEN2(dev)) {
15713                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15714                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15715         } else {
15716                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15717                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15718         }
15719
15720         dev->mode_config.fb_base = ggtt->mappable_base;
15721
15722         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15723                       INTEL_INFO(dev)->num_pipes,
15724                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15725
15726         for_each_pipe(dev_priv, pipe) {
15727                 intel_crtc_init(dev, pipe);
15728                 for_each_sprite(dev_priv, pipe, sprite) {
15729                         ret = intel_plane_init(dev, pipe, sprite);
15730                         if (ret)
15731                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15732                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15733                 }
15734         }
15735
15736         intel_update_czclk(dev_priv);
15737         intel_update_cdclk(dev);
15738
15739         intel_shared_dpll_init(dev);
15740
15741         if (dev_priv->max_cdclk_freq == 0)
15742                 intel_update_max_cdclk(dev);
15743
15744         /* Just disable it once at startup */
15745         i915_disable_vga(dev);
15746         intel_setup_outputs(dev);
15747
15748         drm_modeset_lock_all(dev);
15749         intel_modeset_setup_hw_state(dev);
15750         drm_modeset_unlock_all(dev);
15751
15752         for_each_intel_crtc(dev, crtc) {
15753                 struct intel_initial_plane_config plane_config = {};
15754
15755                 if (!crtc->active)
15756                         continue;
15757
15758                 /*
15759                  * Note that reserving the BIOS fb up front prevents us
15760                  * from stuffing other stolen allocations like the ring
15761                  * on top.  This prevents some ugliness at boot time, and
15762                  * can even allow for smooth boot transitions if the BIOS
15763                  * fb is large enough for the active pipe configuration.
15764                  */
15765                 dev_priv->display.get_initial_plane_config(crtc,
15766                                                            &plane_config);
15767
15768                 /*
15769                  * If the fb is shared between multiple heads, we'll
15770                  * just get the first one.
15771                  */
15772                 intel_find_initial_plane_obj(crtc, &plane_config);
15773         }
15774
15775         /*
15776          * Make sure hardware watermarks really match the state we read out.
15777          * Note that we need to do this after reconstructing the BIOS fb's
15778          * since the watermark calculation done here will use pstate->fb.
15779          */
15780         sanitize_watermarks(dev);
15781 }
15782
15783 static void intel_enable_pipe_a(struct drm_device *dev)
15784 {
15785         struct intel_connector *connector;
15786         struct drm_connector *crt = NULL;
15787         struct intel_load_detect_pipe load_detect_temp;
15788         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15789
15790         /* We can't just switch on the pipe A, we need to set things up with a
15791          * proper mode and output configuration. As a gross hack, enable pipe A
15792          * by enabling the load detect pipe once. */
15793         for_each_intel_connector(dev, connector) {
15794                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15795                         crt = &connector->base;
15796                         break;
15797                 }
15798         }
15799
15800         if (!crt)
15801                 return;
15802
15803         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15804                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15805 }
15806
15807 static bool
15808 intel_check_plane_mapping(struct intel_crtc *crtc)
15809 {
15810         struct drm_device *dev = crtc->base.dev;
15811         struct drm_i915_private *dev_priv = dev->dev_private;
15812         u32 val;
15813
15814         if (INTEL_INFO(dev)->num_pipes == 1)
15815                 return true;
15816
15817         val = I915_READ(DSPCNTR(!crtc->plane));
15818
15819         if ((val & DISPLAY_PLANE_ENABLE) &&
15820             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15821                 return false;
15822
15823         return true;
15824 }
15825
15826 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15827 {
15828         struct drm_device *dev = crtc->base.dev;
15829         struct intel_encoder *encoder;
15830
15831         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15832                 return true;
15833
15834         return false;
15835 }
15836
15837 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15838 {
15839         struct drm_device *dev = encoder->base.dev;
15840         struct intel_connector *connector;
15841
15842         for_each_connector_on_encoder(dev, &encoder->base, connector)
15843                 return true;
15844
15845         return false;
15846 }
15847
15848 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15849 {
15850         struct drm_device *dev = crtc->base.dev;
15851         struct drm_i915_private *dev_priv = dev->dev_private;
15852         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15853
15854         /* Clear any frame start delays used for debugging left by the BIOS */
15855         if (!transcoder_is_dsi(cpu_transcoder)) {
15856                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15857
15858                 I915_WRITE(reg,
15859                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15860         }
15861
15862         /* restore vblank interrupts to correct state */
15863         drm_crtc_vblank_reset(&crtc->base);
15864         if (crtc->active) {
15865                 struct intel_plane *plane;
15866
15867                 drm_crtc_vblank_on(&crtc->base);
15868
15869                 /* Disable everything but the primary plane */
15870                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15871                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15872                                 continue;
15873
15874                         plane->disable_plane(&plane->base, &crtc->base);
15875                 }
15876         }
15877
15878         /* We need to sanitize the plane -> pipe mapping first because this will
15879          * disable the crtc (and hence change the state) if it is wrong. Note
15880          * that gen4+ has a fixed plane -> pipe mapping.  */
15881         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15882                 bool plane;
15883
15884                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15885                               crtc->base.base.id, crtc->base.name);
15886
15887                 /* Pipe has the wrong plane attached and the plane is active.
15888                  * Temporarily change the plane mapping and disable everything
15889                  * ...  */
15890                 plane = crtc->plane;
15891                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15892                 crtc->plane = !plane;
15893                 intel_crtc_disable_noatomic(&crtc->base);
15894                 crtc->plane = plane;
15895         }
15896
15897         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15898             crtc->pipe == PIPE_A && !crtc->active) {
15899                 /* BIOS forgot to enable pipe A, this mostly happens after
15900                  * resume. Force-enable the pipe to fix this, the update_dpms
15901                  * call below we restore the pipe to the right state, but leave
15902                  * the required bits on. */
15903                 intel_enable_pipe_a(dev);
15904         }
15905
15906         /* Adjust the state of the output pipe according to whether we
15907          * have active connectors/encoders. */
15908         if (crtc->active && !intel_crtc_has_encoders(crtc))
15909                 intel_crtc_disable_noatomic(&crtc->base);
15910
15911         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15912                 /*
15913                  * We start out with underrun reporting disabled to avoid races.
15914                  * For correct bookkeeping mark this on active crtcs.
15915                  *
15916                  * Also on gmch platforms we dont have any hardware bits to
15917                  * disable the underrun reporting. Which means we need to start
15918                  * out with underrun reporting disabled also on inactive pipes,
15919                  * since otherwise we'll complain about the garbage we read when
15920                  * e.g. coming up after runtime pm.
15921                  *
15922                  * No protection against concurrent access is required - at
15923                  * worst a fifo underrun happens which also sets this to false.
15924                  */
15925                 crtc->cpu_fifo_underrun_disabled = true;
15926                 crtc->pch_fifo_underrun_disabled = true;
15927         }
15928 }
15929
15930 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15931 {
15932         struct intel_connector *connector;
15933         struct drm_device *dev = encoder->base.dev;
15934
15935         /* We need to check both for a crtc link (meaning that the
15936          * encoder is active and trying to read from a pipe) and the
15937          * pipe itself being active. */
15938         bool has_active_crtc = encoder->base.crtc &&
15939                 to_intel_crtc(encoder->base.crtc)->active;
15940
15941         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15942                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15943                               encoder->base.base.id,
15944                               encoder->base.name);
15945
15946                 /* Connector is active, but has no active pipe. This is
15947                  * fallout from our resume register restoring. Disable
15948                  * the encoder manually again. */
15949                 if (encoder->base.crtc) {
15950                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15951                                       encoder->base.base.id,
15952                                       encoder->base.name);
15953                         encoder->disable(encoder);
15954                         if (encoder->post_disable)
15955                                 encoder->post_disable(encoder);
15956                 }
15957                 encoder->base.crtc = NULL;
15958
15959                 /* Inconsistent output/port/pipe state happens presumably due to
15960                  * a bug in one of the get_hw_state functions. Or someplace else
15961                  * in our code, like the register restore mess on resume. Clamp
15962                  * things to off as a safer default. */
15963                 for_each_intel_connector(dev, connector) {
15964                         if (connector->encoder != encoder)
15965                                 continue;
15966                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15967                         connector->base.encoder = NULL;
15968                 }
15969         }
15970         /* Enabled encoders without active connectors will be fixed in
15971          * the crtc fixup. */
15972 }
15973
15974 void i915_redisable_vga_power_on(struct drm_device *dev)
15975 {
15976         struct drm_i915_private *dev_priv = dev->dev_private;
15977         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15978
15979         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15980                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15981                 i915_disable_vga(dev);
15982         }
15983 }
15984
15985 void i915_redisable_vga(struct drm_device *dev)
15986 {
15987         struct drm_i915_private *dev_priv = dev->dev_private;
15988
15989         /* This function can be called both from intel_modeset_setup_hw_state or
15990          * at a very early point in our resume sequence, where the power well
15991          * structures are not yet restored. Since this function is at a very
15992          * paranoid "someone might have enabled VGA while we were not looking"
15993          * level, just check if the power well is enabled instead of trying to
15994          * follow the "don't touch the power well if we don't need it" policy
15995          * the rest of the driver uses. */
15996         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15997                 return;
15998
15999         i915_redisable_vga_power_on(dev);
16000
16001         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16002 }
16003
16004 static bool primary_get_hw_state(struct intel_plane *plane)
16005 {
16006         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16007
16008         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16009 }
16010
16011 /* FIXME read out full plane state for all planes */
16012 static void readout_plane_state(struct intel_crtc *crtc)
16013 {
16014         struct drm_plane *primary = crtc->base.primary;
16015         struct intel_plane_state *plane_state =
16016                 to_intel_plane_state(primary->state);
16017
16018         plane_state->visible = crtc->active &&
16019                 primary_get_hw_state(to_intel_plane(primary));
16020
16021         if (plane_state->visible)
16022                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16023 }
16024
16025 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16026 {
16027         struct drm_i915_private *dev_priv = dev->dev_private;
16028         enum pipe pipe;
16029         struct intel_crtc *crtc;
16030         struct intel_encoder *encoder;
16031         struct intel_connector *connector;
16032         int i;
16033
16034         dev_priv->active_crtcs = 0;
16035
16036         for_each_intel_crtc(dev, crtc) {
16037                 struct intel_crtc_state *crtc_state = crtc->config;
16038                 int pixclk = 0;
16039
16040                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16041                 memset(crtc_state, 0, sizeof(*crtc_state));
16042                 crtc_state->base.crtc = &crtc->base;
16043
16044                 crtc_state->base.active = crtc_state->base.enable =
16045                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16046
16047                 crtc->base.enabled = crtc_state->base.enable;
16048                 crtc->active = crtc_state->base.active;
16049
16050                 if (crtc_state->base.active) {
16051                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16052
16053                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16054                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16055                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16056                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16057                         else
16058                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16059
16060                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16061                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16062                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16063                 }
16064
16065                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16066
16067                 readout_plane_state(crtc);
16068
16069                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16070                               crtc->base.base.id, crtc->base.name,
16071                               crtc->active ? "enabled" : "disabled");
16072         }
16073
16074         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16075                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16076
16077                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16078                                                   &pll->config.hw_state);
16079                 pll->config.crtc_mask = 0;
16080                 for_each_intel_crtc(dev, crtc) {
16081                         if (crtc->active && crtc->config->shared_dpll == pll)
16082                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16083                 }
16084                 pll->active_mask = pll->config.crtc_mask;
16085
16086                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16087                               pll->name, pll->config.crtc_mask, pll->on);
16088         }
16089
16090         for_each_intel_encoder(dev, encoder) {
16091                 pipe = 0;
16092
16093                 if (encoder->get_hw_state(encoder, &pipe)) {
16094                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16095                         encoder->base.crtc = &crtc->base;
16096                         encoder->get_config(encoder, crtc->config);
16097                 } else {
16098                         encoder->base.crtc = NULL;
16099                 }
16100
16101                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16102                               encoder->base.base.id,
16103                               encoder->base.name,
16104                               encoder->base.crtc ? "enabled" : "disabled",
16105                               pipe_name(pipe));
16106         }
16107
16108         for_each_intel_connector(dev, connector) {
16109                 if (connector->get_hw_state(connector)) {
16110                         connector->base.dpms = DRM_MODE_DPMS_ON;
16111
16112                         encoder = connector->encoder;
16113                         connector->base.encoder = &encoder->base;
16114
16115                         if (encoder->base.crtc &&
16116                             encoder->base.crtc->state->active) {
16117                                 /*
16118                                  * This has to be done during hardware readout
16119                                  * because anything calling .crtc_disable may
16120                                  * rely on the connector_mask being accurate.
16121                                  */
16122                                 encoder->base.crtc->state->connector_mask |=
16123                                         1 << drm_connector_index(&connector->base);
16124                                 encoder->base.crtc->state->encoder_mask |=
16125                                         1 << drm_encoder_index(&encoder->base);
16126                         }
16127
16128                 } else {
16129                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16130                         connector->base.encoder = NULL;
16131                 }
16132                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16133                               connector->base.base.id,
16134                               connector->base.name,
16135                               connector->base.encoder ? "enabled" : "disabled");
16136         }
16137
16138         for_each_intel_crtc(dev, crtc) {
16139                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16140
16141                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16142                 if (crtc->base.state->active) {
16143                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16144                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16145                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16146
16147                         /*
16148                          * The initial mode needs to be set in order to keep
16149                          * the atomic core happy. It wants a valid mode if the
16150                          * crtc's enabled, so we do the above call.
16151                          *
16152                          * At this point some state updated by the connectors
16153                          * in their ->detect() callback has not run yet, so
16154                          * no recalculation can be done yet.
16155                          *
16156                          * Even if we could do a recalculation and modeset
16157                          * right now it would cause a double modeset if
16158                          * fbdev or userspace chooses a different initial mode.
16159                          *
16160                          * If that happens, someone indicated they wanted a
16161                          * mode change, which means it's safe to do a full
16162                          * recalculation.
16163                          */
16164                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16165
16166                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16167                         update_scanline_offset(crtc);
16168                 }
16169
16170                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16171         }
16172 }
16173
16174 /* Scan out the current hw modeset state,
16175  * and sanitizes it to the current state
16176  */
16177 static void
16178 intel_modeset_setup_hw_state(struct drm_device *dev)
16179 {
16180         struct drm_i915_private *dev_priv = dev->dev_private;
16181         enum pipe pipe;
16182         struct intel_crtc *crtc;
16183         struct intel_encoder *encoder;
16184         int i;
16185
16186         intel_modeset_readout_hw_state(dev);
16187
16188         /* HW state is read out, now we need to sanitize this mess. */
16189         for_each_intel_encoder(dev, encoder) {
16190                 intel_sanitize_encoder(encoder);
16191         }
16192
16193         for_each_pipe(dev_priv, pipe) {
16194                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16195                 intel_sanitize_crtc(crtc);
16196                 intel_dump_pipe_config(crtc, crtc->config,
16197                                        "[setup_hw_state]");
16198         }
16199
16200         intel_modeset_update_connector_atomic_state(dev);
16201
16202         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16203                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16204
16205                 if (!pll->on || pll->active_mask)
16206                         continue;
16207
16208                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16209
16210                 pll->funcs.disable(dev_priv, pll);
16211                 pll->on = false;
16212         }
16213
16214         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16215                 vlv_wm_get_hw_state(dev);
16216         else if (IS_GEN9(dev))
16217                 skl_wm_get_hw_state(dev);
16218         else if (HAS_PCH_SPLIT(dev))
16219                 ilk_wm_get_hw_state(dev);
16220
16221         for_each_intel_crtc(dev, crtc) {
16222                 unsigned long put_domains;
16223
16224                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16225                 if (WARN_ON(put_domains))
16226                         modeset_put_power_domains(dev_priv, put_domains);
16227         }
16228         intel_display_set_init_power(dev_priv, false);
16229
16230         intel_fbc_init_pipe_state(dev_priv);
16231 }
16232
16233 void intel_display_resume(struct drm_device *dev)
16234 {
16235         struct drm_i915_private *dev_priv = to_i915(dev);
16236         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16237         struct drm_modeset_acquire_ctx ctx;
16238         int ret;
16239         bool setup = false;
16240
16241         dev_priv->modeset_restore_state = NULL;
16242
16243         /*
16244          * This is a cludge because with real atomic modeset mode_config.mutex
16245          * won't be taken. Unfortunately some probed state like
16246          * audio_codec_enable is still protected by mode_config.mutex, so lock
16247          * it here for now.
16248          */
16249         mutex_lock(&dev->mode_config.mutex);
16250         drm_modeset_acquire_init(&ctx, 0);
16251
16252 retry:
16253         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16254
16255         if (ret == 0 && !setup) {
16256                 setup = true;
16257
16258                 intel_modeset_setup_hw_state(dev);
16259                 i915_redisable_vga(dev);
16260         }
16261
16262         if (ret == 0 && state) {
16263                 struct drm_crtc_state *crtc_state;
16264                 struct drm_crtc *crtc;
16265                 int i;
16266
16267                 state->acquire_ctx = &ctx;
16268
16269                 /* ignore any reset values/BIOS leftovers in the WM registers */
16270                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16271
16272                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16273                         /*
16274                          * Force recalculation even if we restore
16275                          * current state. With fast modeset this may not result
16276                          * in a modeset when the state is compatible.
16277                          */
16278                         crtc_state->mode_changed = true;
16279                 }
16280
16281                 ret = drm_atomic_commit(state);
16282         }
16283
16284         if (ret == -EDEADLK) {
16285                 drm_modeset_backoff(&ctx);
16286                 goto retry;
16287         }
16288
16289         drm_modeset_drop_locks(&ctx);
16290         drm_modeset_acquire_fini(&ctx);
16291         mutex_unlock(&dev->mode_config.mutex);
16292
16293         if (ret) {
16294                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16295                 drm_atomic_state_free(state);
16296         }
16297 }
16298
16299 void intel_modeset_gem_init(struct drm_device *dev)
16300 {
16301         struct drm_i915_private *dev_priv = to_i915(dev);
16302         struct drm_crtc *c;
16303         struct drm_i915_gem_object *obj;
16304         int ret;
16305
16306         intel_init_gt_powersave(dev_priv);
16307
16308         intel_modeset_init_hw(dev);
16309
16310         intel_setup_overlay(dev_priv);
16311
16312         /*
16313          * Make sure any fbs we allocated at startup are properly
16314          * pinned & fenced.  When we do the allocation it's too early
16315          * for this.
16316          */
16317         for_each_crtc(dev, c) {
16318                 obj = intel_fb_obj(c->primary->fb);
16319                 if (obj == NULL)
16320                         continue;
16321
16322                 mutex_lock(&dev->struct_mutex);
16323                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16324                                                  c->primary->state->rotation);
16325                 mutex_unlock(&dev->struct_mutex);
16326                 if (ret) {
16327                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16328                                   to_intel_crtc(c)->pipe);
16329                         drm_framebuffer_unreference(c->primary->fb);
16330                         c->primary->fb = NULL;
16331                         c->primary->crtc = c->primary->state->crtc = NULL;
16332                         update_state_fb(c->primary);
16333                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16334                 }
16335         }
16336 }
16337
16338 int intel_connector_register(struct drm_connector *connector)
16339 {
16340         struct intel_connector *intel_connector = to_intel_connector(connector);
16341         int ret;
16342
16343         ret = intel_backlight_device_register(intel_connector);
16344         if (ret)
16345                 goto err;
16346
16347         return 0;
16348
16349 err:
16350         return ret;
16351 }
16352
16353 void intel_connector_unregister(struct drm_connector *connector)
16354 {
16355         struct intel_connector *intel_connector = to_intel_connector(connector);
16356
16357         intel_backlight_device_unregister(intel_connector);
16358         intel_panel_destroy_backlight(connector);
16359 }
16360
16361 void intel_modeset_cleanup(struct drm_device *dev)
16362 {
16363         struct drm_i915_private *dev_priv = dev->dev_private;
16364
16365         intel_disable_gt_powersave(dev_priv);
16366
16367         /*
16368          * Interrupts and polling as the first thing to avoid creating havoc.
16369          * Too much stuff here (turning of connectors, ...) would
16370          * experience fancy races otherwise.
16371          */
16372         intel_irq_uninstall(dev_priv);
16373
16374         /*
16375          * Due to the hpd irq storm handling the hotplug work can re-arm the
16376          * poll handlers. Hence disable polling after hpd handling is shut down.
16377          */
16378         drm_kms_helper_poll_fini(dev);
16379
16380         intel_unregister_dsm_handler();
16381
16382         intel_fbc_global_disable(dev_priv);
16383
16384         /* flush any delayed tasks or pending work */
16385         flush_scheduled_work();
16386
16387         drm_mode_config_cleanup(dev);
16388
16389         intel_cleanup_overlay(dev_priv);
16390
16391         intel_cleanup_gt_powersave(dev_priv);
16392
16393         intel_teardown_gmbus(dev);
16394 }
16395
16396 void intel_connector_attach_encoder(struct intel_connector *connector,
16397                                     struct intel_encoder *encoder)
16398 {
16399         connector->encoder = encoder;
16400         drm_mode_connector_attach_encoder(&connector->base,
16401                                           &encoder->base);
16402 }
16403
16404 /*
16405  * set vga decode state - true == enable VGA decode
16406  */
16407 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16408 {
16409         struct drm_i915_private *dev_priv = dev->dev_private;
16410         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16411         u16 gmch_ctrl;
16412
16413         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16414                 DRM_ERROR("failed to read control word\n");
16415                 return -EIO;
16416         }
16417
16418         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16419                 return 0;
16420
16421         if (state)
16422                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16423         else
16424                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16425
16426         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16427                 DRM_ERROR("failed to write control word\n");
16428                 return -EIO;
16429         }
16430
16431         return 0;
16432 }
16433
16434 struct intel_display_error_state {
16435
16436         u32 power_well_driver;
16437
16438         int num_transcoders;
16439
16440         struct intel_cursor_error_state {
16441                 u32 control;
16442                 u32 position;
16443                 u32 base;
16444                 u32 size;
16445         } cursor[I915_MAX_PIPES];
16446
16447         struct intel_pipe_error_state {
16448                 bool power_domain_on;
16449                 u32 source;
16450                 u32 stat;
16451         } pipe[I915_MAX_PIPES];
16452
16453         struct intel_plane_error_state {
16454                 u32 control;
16455                 u32 stride;
16456                 u32 size;
16457                 u32 pos;
16458                 u32 addr;
16459                 u32 surface;
16460                 u32 tile_offset;
16461         } plane[I915_MAX_PIPES];
16462
16463         struct intel_transcoder_error_state {
16464                 bool power_domain_on;
16465                 enum transcoder cpu_transcoder;
16466
16467                 u32 conf;
16468
16469                 u32 htotal;
16470                 u32 hblank;
16471                 u32 hsync;
16472                 u32 vtotal;
16473                 u32 vblank;
16474                 u32 vsync;
16475         } transcoder[4];
16476 };
16477
16478 struct intel_display_error_state *
16479 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16480 {
16481         struct intel_display_error_state *error;
16482         int transcoders[] = {
16483                 TRANSCODER_A,
16484                 TRANSCODER_B,
16485                 TRANSCODER_C,
16486                 TRANSCODER_EDP,
16487         };
16488         int i;
16489
16490         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16491                 return NULL;
16492
16493         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16494         if (error == NULL)
16495                 return NULL;
16496
16497         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16498                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16499
16500         for_each_pipe(dev_priv, i) {
16501                 error->pipe[i].power_domain_on =
16502                         __intel_display_power_is_enabled(dev_priv,
16503                                                          POWER_DOMAIN_PIPE(i));
16504                 if (!error->pipe[i].power_domain_on)
16505                         continue;
16506
16507                 error->cursor[i].control = I915_READ(CURCNTR(i));
16508                 error->cursor[i].position = I915_READ(CURPOS(i));
16509                 error->cursor[i].base = I915_READ(CURBASE(i));
16510
16511                 error->plane[i].control = I915_READ(DSPCNTR(i));
16512                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16513                 if (INTEL_GEN(dev_priv) <= 3) {
16514                         error->plane[i].size = I915_READ(DSPSIZE(i));
16515                         error->plane[i].pos = I915_READ(DSPPOS(i));
16516                 }
16517                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16518                         error->plane[i].addr = I915_READ(DSPADDR(i));
16519                 if (INTEL_GEN(dev_priv) >= 4) {
16520                         error->plane[i].surface = I915_READ(DSPSURF(i));
16521                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16522                 }
16523
16524                 error->pipe[i].source = I915_READ(PIPESRC(i));
16525
16526                 if (HAS_GMCH_DISPLAY(dev_priv))
16527                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16528         }
16529
16530         /* Note: this does not include DSI transcoders. */
16531         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16532         if (HAS_DDI(dev_priv))
16533                 error->num_transcoders++; /* Account for eDP. */
16534
16535         for (i = 0; i < error->num_transcoders; i++) {
16536                 enum transcoder cpu_transcoder = transcoders[i];
16537
16538                 error->transcoder[i].power_domain_on =
16539                         __intel_display_power_is_enabled(dev_priv,
16540                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16541                 if (!error->transcoder[i].power_domain_on)
16542                         continue;
16543
16544                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16545
16546                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16547                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16548                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16549                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16550                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16551                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16552                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16553         }
16554
16555         return error;
16556 }
16557
16558 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16559
16560 void
16561 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16562                                 struct drm_device *dev,
16563                                 struct intel_display_error_state *error)
16564 {
16565         struct drm_i915_private *dev_priv = dev->dev_private;
16566         int i;
16567
16568         if (!error)
16569                 return;
16570
16571         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16572         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16573                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16574                            error->power_well_driver);
16575         for_each_pipe(dev_priv, i) {
16576                 err_printf(m, "Pipe [%d]:\n", i);
16577                 err_printf(m, "  Power: %s\n",
16578                            onoff(error->pipe[i].power_domain_on));
16579                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16580                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16581
16582                 err_printf(m, "Plane [%d]:\n", i);
16583                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16584                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16585                 if (INTEL_INFO(dev)->gen <= 3) {
16586                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16587                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16588                 }
16589                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16590                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16591                 if (INTEL_INFO(dev)->gen >= 4) {
16592                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16593                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16594                 }
16595
16596                 err_printf(m, "Cursor [%d]:\n", i);
16597                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16598                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16599                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16600         }
16601
16602         for (i = 0; i < error->num_transcoders; i++) {
16603                 err_printf(m, "CPU transcoder: %s\n",
16604                            transcoder_name(error->transcoder[i].cpu_transcoder));
16605                 err_printf(m, "  Power: %s\n",
16606                            onoff(error->transcoder[i].power_domain_on));
16607                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16608                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16609                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16610                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16611                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16612                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16613                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16614         }
16615 }