drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "intel_dsi.h"
  40 #include "i915_trace.h"
  41 #include <drm/drm_atomic.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_dp_helper.h>
  44 #include <drm/drm_crtc_helper.h>
  45 #include <drm/drm_plane_helper.h>
  46 #include <drm/drm_rect.h>
  47 #include <linux/dma_remapping.h>
  48 #include <linux/reservation.h>
  49 #include <linux/dma-buf.h>
  50
  51 /* Primary plane formats for gen <= 3 */
  52 static const uint32_t i8xx_primary_formats[] = {
  53         DRM_FORMAT_C8,
  54         DRM_FORMAT_RGB565,
  55         DRM_FORMAT_XRGB1555,
  56         DRM_FORMAT_XRGB8888,
  57 };
  58
  59 /* Primary plane formats for gen >= 4 */
  60 static const uint32_t i965_primary_formats[] = {
  61         DRM_FORMAT_C8,
  62         DRM_FORMAT_RGB565,
  63         DRM_FORMAT_XRGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_XBGR2101010,
  67 };
  68
  69 static const uint32_t skl_primary_formats[] = {
  70         DRM_FORMAT_C8,
  71         DRM_FORMAT_RGB565,
  72         DRM_FORMAT_XRGB8888,
  73         DRM_FORMAT_XBGR8888,
  74         DRM_FORMAT_ARGB8888,
  75         DRM_FORMAT_ABGR8888,
  76         DRM_FORMAT_XRGB2101010,
  77         DRM_FORMAT_XBGR2101010,
  78         DRM_FORMAT_YUYV,
  79         DRM_FORMAT_YVYU,
  80         DRM_FORMAT_UYVY,
  81         DRM_FORMAT_VYUY,
  82 };
  83
  84 /* Cursor formats */
  85 static const uint32_t intel_cursor_formats[] = {
  86         DRM_FORMAT_ARGB8888,
  87 };
  88
  89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  90                                 struct intel_crtc_state *pipe_config);
  91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  92                                    struct intel_crtc_state *pipe_config);
  93
  94 static int intel_framebuffer_init(struct drm_device *dev,
  95                                   struct intel_framebuffer *ifb,
  96                                   struct drm_mode_fb_cmd2 *mode_cmd,
  97                                   struct drm_i915_gem_object *obj);
  98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 114         struct intel_crtc_state *crtc_state);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 151                       const char *name, u32 reg, int ref_freq)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         mutex_lock(&dev_priv->sb_lock);
 157         val = vlv_cck_read(dev_priv, reg);
 158         mutex_unlock(&dev_priv->sb_lock);
 159
 160         divider = val & CCK_FREQUENCY_VALUES;
 161
 162         WARN((val & CCK_FREQUENCY_STATUS) !=
 163              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 164              "%s change in progress\n", name);
 165
 166         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 167 }
 168
 169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 170                                   const char *name, u32 reg)
 171 {
 172         if (dev_priv->hpll_freq == 0)
 173                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 174
 175         return vlv_get_cck_clock(dev_priv, name, reg,
 176                                  dev_priv->hpll_freq);
 177 }
 178
 179 static int
 180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 181 {
 182         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 183 }
 184
 185 static int
 186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 187 {
 188         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 189                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 190 }
 191
 192 static int
 193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 194 {
 195         uint32_t clkcfg;
 196
 197         /* hrawclock is 1/4 the FSB frequency */
 198         clkcfg = I915_READ(CLKCFG);
 199         switch (clkcfg & CLKCFG_FSB_MASK) {
 200         case CLKCFG_FSB_400:
 201                 return 100000;
 202         case CLKCFG_FSB_533:
 203                 return 133333;
 204         case CLKCFG_FSB_667:
 205                 return 166667;
 206         case CLKCFG_FSB_800:
 207                 return 200000;
 208         case CLKCFG_FSB_1067:
 209                 return 266667;
 210         case CLKCFG_FSB_1333:
 211                 return 333333;
 212         /* these two are just a guess; one of them might be right */
 213         case CLKCFG_FSB_1600:
 214         case CLKCFG_FSB_1600_ALT:
 215                 return 400000;
 216         default:
 217                 return 133333;
 218         }
 219 }
 220
 221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 222 {
 223         if (HAS_PCH_SPLIT(dev_priv))
 224                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 225         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 226                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 227         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 228                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 229         else
 230                 return; /* no rawclk on other platforms, or no need to know it */
 231
 232         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 233 }
 234
 235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 236 {
 237         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 238                 return;
 239
 240         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 241                                                       CCK_CZ_CLOCK_CONTROL);
 242
 243         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 244 }
 245
 246 static inline u32 /* units of 100MHz */
 247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 248                     const struct intel_crtc_state *pipe_config)
 249 {
 250         if (HAS_DDI(dev_priv))
 251                 return pipe_config->port_clock; /* SPLL */
 252         else if (IS_GEN5(dev_priv))
 253                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 254         else
 255                 return 270000;
 256 }
 257
 258 static const intel_limit_t intel_limits_i8xx_dac = {
 259         .dot = { .min = 25000, .max = 350000 },
 260         .vco = { .min = 908000, .max = 1512000 },
 261         .n = { .min = 2, .max = 16 },
 262         .m = { .min = 96, .max = 140 },
 263         .m1 = { .min = 18, .max = 26 },
 264         .m2 = { .min = 6, .max = 16 },
 265         .p = { .min = 4, .max = 128 },
 266         .p1 = { .min = 2, .max = 33 },
 267         .p2 = { .dot_limit = 165000,
 268                 .p2_slow = 4, .p2_fast = 2 },
 269 };
 270
 271 static const intel_limit_t intel_limits_i8xx_dvo = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 908000, .max = 1512000 },
 274         .n = { .min = 2, .max = 16 },
 275         .m = { .min = 96, .max = 140 },
 276         .m1 = { .min = 18, .max = 26 },
 277         .m2 = { .min = 6, .max = 16 },
 278         .p = { .min = 4, .max = 128 },
 279         .p1 = { .min = 2, .max = 33 },
 280         .p2 = { .dot_limit = 165000,
 281                 .p2_slow = 4, .p2_fast = 4 },
 282 };
 283
 284 static const intel_limit_t intel_limits_i8xx_lvds = {
 285         .dot = { .min = 25000, .max = 350000 },
 286         .vco = { .min = 908000, .max = 1512000 },
 287         .n = { .min = 2, .max = 16 },
 288         .m = { .min = 96, .max = 140 },
 289         .m1 = { .min = 18, .max = 26 },
 290         .m2 = { .min = 6, .max = 16 },
 291         .p = { .min = 4, .max = 128 },
 292         .p1 = { .min = 1, .max = 6 },
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 14, .p2_fast = 7 },
 295 };
 296
 297 static const intel_limit_t intel_limits_i9xx_sdvo = {
 298         .dot = { .min = 20000, .max = 400000 },
 299         .vco = { .min = 1400000, .max = 2800000 },
 300         .n = { .min = 1, .max = 6 },
 301         .m = { .min = 70, .max = 120 },
 302         .m1 = { .min = 8, .max = 18 },
 303         .m2 = { .min = 3, .max = 7 },
 304         .p = { .min = 5, .max = 80 },
 305         .p1 = { .min = 1, .max = 8 },
 306         .p2 = { .dot_limit = 200000,
 307                 .p2_slow = 10, .p2_fast = 5 },
 308 };
 309
 310 static const intel_limit_t intel_limits_i9xx_lvds = {
 311         .dot = { .min = 20000, .max = 400000 },
 312         .vco = { .min = 1400000, .max = 2800000 },
 313         .n = { .min = 1, .max = 6 },
 314         .m = { .min = 70, .max = 120 },
 315         .m1 = { .min = 8, .max = 18 },
 316         .m2 = { .min = 3, .max = 7 },
 317         .p = { .min = 7, .max = 98 },
 318         .p1 = { .min = 1, .max = 8 },
 319         .p2 = { .dot_limit = 112000,
 320                 .p2_slow = 14, .p2_fast = 7 },
 321 };
 322
 323
 324 static const intel_limit_t intel_limits_g4x_sdvo = {
 325         .dot = { .min = 25000, .max = 270000 },
 326         .vco = { .min = 1750000, .max = 3500000},
 327         .n = { .min = 1, .max = 4 },
 328         .m = { .min = 104, .max = 138 },
 329         .m1 = { .min = 17, .max = 23 },
 330         .m2 = { .min = 5, .max = 11 },
 331         .p = { .min = 10, .max = 30 },
 332         .p1 = { .min = 1, .max = 3},
 333         .p2 = { .dot_limit = 270000,
 334                 .p2_slow = 10,
 335                 .p2_fast = 10
 336         },
 337 };
 338
 339 static const intel_limit_t intel_limits_g4x_hdmi = {
 340         .dot = { .min = 22000, .max = 400000 },
 341         .vco = { .min = 1750000, .max = 3500000},
 342         .n = { .min = 1, .max = 4 },
 343         .m = { .min = 104, .max = 138 },
 344         .m1 = { .min = 16, .max = 23 },
 345         .m2 = { .min = 5, .max = 11 },
 346         .p = { .min = 5, .max = 80 },
 347         .p1 = { .min = 1, .max = 8},
 348         .p2 = { .dot_limit = 165000,
 349                 .p2_slow = 10, .p2_fast = 5 },
 350 };
 351
 352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 353         .dot = { .min = 20000, .max = 115000 },
 354         .vco = { .min = 1750000, .max = 3500000 },
 355         .n = { .min = 1, .max = 3 },
 356         .m = { .min = 104, .max = 138 },
 357         .m1 = { .min = 17, .max = 23 },
 358         .m2 = { .min = 5, .max = 11 },
 359         .p = { .min = 28, .max = 112 },
 360         .p1 = { .min = 2, .max = 8 },
 361         .p2 = { .dot_limit = 0,
 362                 .p2_slow = 14, .p2_fast = 14
 363         },
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 367         .dot = { .min = 80000, .max = 224000 },
 368         .vco = { .min = 1750000, .max = 3500000 },
 369         .n = { .min = 1, .max = 3 },
 370         .m = { .min = 104, .max = 138 },
 371         .m1 = { .min = 17, .max = 23 },
 372         .m2 = { .min = 5, .max = 11 },
 373         .p = { .min = 14, .max = 42 },
 374         .p1 = { .min = 2, .max = 6 },
 375         .p2 = { .dot_limit = 0,
 376                 .p2_slow = 7, .p2_fast = 7
 377         },
 378 };
 379
 380 static const intel_limit_t intel_limits_pineview_sdvo = {
 381         .dot = { .min = 20000, .max = 400000},
 382         .vco = { .min = 1700000, .max = 3500000 },
 383         /* Pineview's Ncounter is a ring counter */
 384         .n = { .min = 3, .max = 6 },
 385         .m = { .min = 2, .max = 256 },
 386         /* Pineview only has one combined m divider, which we treat as m2. */
 387         .m1 = { .min = 0, .max = 0 },
 388         .m2 = { .min = 0, .max = 254 },
 389         .p = { .min = 5, .max = 80 },
 390         .p1 = { .min = 1, .max = 8 },
 391         .p2 = { .dot_limit = 200000,
 392                 .p2_slow = 10, .p2_fast = 5 },
 393 };
 394
 395 static const intel_limit_t intel_limits_pineview_lvds = {
 396         .dot = { .min = 20000, .max = 400000 },
 397         .vco = { .min = 1700000, .max = 3500000 },
 398         .n = { .min = 3, .max = 6 },
 399         .m = { .min = 2, .max = 256 },
 400         .m1 = { .min = 0, .max = 0 },
 401         .m2 = { .min = 0, .max = 254 },
 402         .p = { .min = 7, .max = 112 },
 403         .p1 = { .min = 1, .max = 8 },
 404         .p2 = { .dot_limit = 112000,
 405                 .p2_slow = 14, .p2_fast = 14 },
 406 };
 407
 408 /* Ironlake / Sandybridge
 409  *
 410  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 411  * the range value for them is (actual_value - 2).
 412  */
 413 static const intel_limit_t intel_limits_ironlake_dac = {
 414         .dot = { .min = 25000, .max = 350000 },
 415         .vco = { .min = 1760000, .max = 3510000 },
 416         .n = { .min = 1, .max = 5 },
 417         .m = { .min = 79, .max = 127 },
 418         .m1 = { .min = 12, .max = 22 },
 419         .m2 = { .min = 5, .max = 9 },
 420         .p = { .min = 5, .max = 80 },
 421         .p1 = { .min = 1, .max = 8 },
 422         .p2 = { .dot_limit = 225000,
 423                 .p2_slow = 10, .p2_fast = 5 },
 424 };
 425
 426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 427         .dot = { .min = 25000, .max = 350000 },
 428         .vco = { .min = 1760000, .max = 3510000 },
 429         .n = { .min = 1, .max = 3 },
 430         .m = { .min = 79, .max = 118 },
 431         .m1 = { .min = 12, .max = 22 },
 432         .m2 = { .min = 5, .max = 9 },
 433         .p = { .min = 28, .max = 112 },
 434         .p1 = { .min = 2, .max = 8 },
 435         .p2 = { .dot_limit = 225000,
 436                 .p2_slow = 14, .p2_fast = 14 },
 437 };
 438
 439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 440         .dot = { .min = 25000, .max = 350000 },
 441         .vco = { .min = 1760000, .max = 3510000 },
 442         .n = { .min = 1, .max = 3 },
 443         .m = { .min = 79, .max = 127 },
 444         .m1 = { .min = 12, .max = 22 },
 445         .m2 = { .min = 5, .max = 9 },
 446         .p = { .min = 14, .max = 56 },
 447         .p1 = { .min = 2, .max = 8 },
 448         .p2 = { .dot_limit = 225000,
 449                 .p2_slow = 7, .p2_fast = 7 },
 450 };
 451
 452 /* LVDS 100mhz refclk limits. */
 453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 454         .dot = { .min = 25000, .max = 350000 },
 455         .vco = { .min = 1760000, .max = 3510000 },
 456         .n = { .min = 1, .max = 2 },
 457         .m = { .min = 79, .max = 126 },
 458         .m1 = { .min = 12, .max = 22 },
 459         .m2 = { .min = 5, .max = 9 },
 460         .p = { .min = 28, .max = 112 },
 461         .p1 = { .min = 2, .max = 8 },
 462         .p2 = { .dot_limit = 225000,
 463                 .p2_slow = 14, .p2_fast = 14 },
 464 };
 465
 466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 467         .dot = { .min = 25000, .max = 350000 },
 468         .vco = { .min = 1760000, .max = 3510000 },
 469         .n = { .min = 1, .max = 3 },
 470         .m = { .min = 79, .max = 126 },
 471         .m1 = { .min = 12, .max = 22 },
 472         .m2 = { .min = 5, .max = 9 },
 473         .p = { .min = 14, .max = 42 },
 474         .p1 = { .min = 2, .max = 6 },
 475         .p2 = { .dot_limit = 225000,
 476                 .p2_slow = 7, .p2_fast = 7 },
 477 };
 478
 479 static const intel_limit_t intel_limits_vlv = {
 480          /*
 481           * These are the data rate limits (measured in fast clocks)
 482           * since those are the strictest limits we have. The fast
 483           * clock and actual rate limits are more relaxed, so checking
 484           * them would make no difference.
 485           */
 486         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 487         .vco = { .min = 4000000, .max = 6000000 },
 488         .n = { .min = 1, .max = 7 },
 489         .m1 = { .min = 2, .max = 3 },
 490         .m2 = { .min = 11, .max = 156 },
 491         .p1 = { .min = 2, .max = 3 },
 492         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 493 };
 494
 495 static const intel_limit_t intel_limits_chv = {
 496         /*
 497          * These are the data rate limits (measured in fast clocks)
 498          * since those are the strictest limits we have.  The fast
 499          * clock and actual rate limits are more relaxed, so checking
 500          * them would make no difference.
 501          */
 502         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 503         .vco = { .min = 4800000, .max = 6480000 },
 504         .n = { .min = 1, .max = 1 },
 505         .m1 = { .min = 2, .max = 2 },
 506         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 507         .p1 = { .min = 2, .max = 4 },
 508         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 509 };
 510
 511 static const intel_limit_t intel_limits_bxt = {
 512         /* FIXME: find real dot limits */
 513         .dot = { .min = 0, .max = INT_MAX },
 514         .vco = { .min = 4800000, .max = 6700000 },
 515         .n = { .min = 1, .max = 1 },
 516         .m1 = { .min = 2, .max = 2 },
 517         /* FIXME: find real m2 limits */
 518         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 519         .p1 = { .min = 2, .max = 4 },
 520         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 521 };
 522
 523 static bool
 524 needs_modeset(struct drm_crtc_state *state)
 525 {
 526         return drm_atomic_crtc_needs_modeset(state);
 527 }
 528
 529 /**
 530  * Returns whether any output on the specified pipe is of the specified type
 531  */
 532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 533 {
 534         struct drm_device *dev = crtc->base.dev;
 535         struct intel_encoder *encoder;
 536
 537         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 538                 if (encoder->type == type)
 539                         return true;
 540
 541         return false;
 542 }
 543
 544 /**
 545  * Returns whether any output on the specified pipe will have the specified
 546  * type after a staged modeset is complete, i.e., the same as
 547  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 548  * encoder->crtc.
 549  */
 550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 551                                       int type)
 552 {
 553         struct drm_atomic_state *state = crtc_state->base.state;
 554         struct drm_connector *connector;
 555         struct drm_connector_state *connector_state;
 556         struct intel_encoder *encoder;
 557         int i, num_connectors = 0;
 558
 559         for_each_connector_in_state(state, connector, connector_state, i) {
 560                 if (connector_state->crtc != crtc_state->base.crtc)
 561                         continue;
 562
 563                 num_connectors++;
 564
 565                 encoder = to_intel_encoder(connector_state->best_encoder);
 566                 if (encoder->type == type)
 567                         return true;
 568         }
 569
 570         WARN_ON(num_connectors == 0);
 571
 572         return false;
 573 }
 574
 575 /*
 576  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 577  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 578  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 579  * The helpers' return value is the rate of the clock that is fed to the
 580  * display engine's pipe which can be the above fast dot clock rate or a
 581  * divided-down version of it.
 582  */
 583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 592
 593         return clock->dot;
 594 }
 595
 596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 597 {
 598         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 599 }
 600
 601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 602 {
 603         clock->m = i9xx_dpll_compute_m(clock);
 604         clock->p = clock->p1 * clock->p2;
 605         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 606                 return 0;
 607         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 608         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 609
 610         return clock->dot;
 611 }
 612
 613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 614 {
 615         clock->m = clock->m1 * clock->m2;
 616         clock->p = clock->p1 * clock->p2;
 617         if (WARN_ON(clock->n == 0 || clock->p == 0))
 618                 return 0;
 619         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 620         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 621
 622         return clock->dot / 5;
 623 }
 624
 625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 626 {
 627         clock->m = clock->m1 * clock->m2;
 628         clock->p = clock->p1 * clock->p2;
 629         if (WARN_ON(clock->n == 0 || clock->p == 0))
 630                 return 0;
 631         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 632                         clock->n << 22);
 633         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 634
 635         return clock->dot / 5;
 636 }
 637
 638 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 639 /**
 640  * Returns whether the given set of divisors are valid for a given refclk with
 641  * the given connectors.
 642  */
 643
 644 static bool intel_PLL_is_valid(struct drm_device *dev,
 645                                const intel_limit_t *limit,
 646                                const intel_clock_t *clock)
 647 {
 648         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 649                 INTELPllInvalid("n out of range\n");
 650         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 651                 INTELPllInvalid("p1 out of range\n");
 652         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 653                 INTELPllInvalid("m2 out of range\n");
 654         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 655                 INTELPllInvalid("m1 out of range\n");
 656
 657         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 658             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 659                 if (clock->m1 <= clock->m2)
 660                         INTELPllInvalid("m1 <= m2\n");
 661
 662         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 663                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 664                         INTELPllInvalid("p out of range\n");
 665                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 666                         INTELPllInvalid("m out of range\n");
 667         }
 668
 669         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 670                 INTELPllInvalid("vco out of range\n");
 671         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 672          * connector, etc., rather than just a single range.
 673          */
 674         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 675                 INTELPllInvalid("dot out of range\n");
 676
 677         return true;
 678 }
 679
 680 static int
 681 i9xx_select_p2_div(const intel_limit_t *limit,
 682                    const struct intel_crtc_state *crtc_state,
 683                    int target)
 684 {
 685         struct drm_device *dev = crtc_state->base.crtc->dev;
 686
 687         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 688                 /*
 689                  * For LVDS just rely on its current settings for dual-channel.
 690                  * We haven't figured out how to reliably set up different
 691                  * single/dual channel state, if we even can.
 692                  */
 693                 if (intel_is_dual_link_lvds(dev))
 694                         return limit->p2.p2_fast;
 695                 else
 696                         return limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         return limit->p2.p2_slow;
 700                 else
 701                         return limit->p2.p2_fast;
 702         }
 703 }
 704
 705 /*
 706  * Returns a set of divisors for the desired target clock with the given
 707  * refclk, or FALSE.  The returned values represent the clock equation:
 708  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 709  *
 710  * Target and reference clocks are specified in kHz.
 711  *
 712  * If match_clock is provided, then best_clock P divider must match the P
 713  * divider from @match_clock used for LVDS downclocking.
 714  */
 715 static bool
 716 i9xx_find_best_dpll(const intel_limit_t *limit,
 717                     struct intel_crtc_state *crtc_state,
 718                     int target, int refclk, intel_clock_t *match_clock,
 719                     intel_clock_t *best_clock)
 720 {
 721         struct drm_device *dev = crtc_state->base.crtc->dev;
 722         intel_clock_t clock;
 723         int err = target;
 724
 725         memset(best_clock, 0, sizeof(*best_clock));
 726
 727         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 728
 729         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 730              clock.m1++) {
 731                 for (clock.m2 = limit->m2.min;
 732                      clock.m2 <= limit->m2.max; clock.m2++) {
 733                         if (clock.m2 >= clock.m1)
 734                                 break;
 735                         for (clock.n = limit->n.min;
 736                              clock.n <= limit->n.max; clock.n++) {
 737                                 for (clock.p1 = limit->p1.min;
 738                                         clock.p1 <= limit->p1.max; clock.p1++) {
 739                                         int this_err;
 740
 741                                         i9xx_calc_dpll_params(refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745                                         if (match_clock &&
 746                                             clock.p != match_clock->p)
 747                                                 continue;
 748
 749                                         this_err = abs(clock.dot - target);
 750                                         if (this_err < err) {
 751                                                 *best_clock = clock;
 752                                                 err = this_err;
 753                                         }
 754                                 }
 755                         }
 756                 }
 757         }
 758
 759         return (err != target);
 760 }
 761
 762 /*
 763  * Returns a set of divisors for the desired target clock with the given
 764  * refclk, or FALSE.  The returned values represent the clock equation:
 765  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 766  *
 767  * Target and reference clocks are specified in kHz.
 768  *
 769  * If match_clock is provided, then best_clock P divider must match the P
 770  * divider from @match_clock used for LVDS downclocking.
 771  */
 772 static bool
 773 pnv_find_best_dpll(const intel_limit_t *limit,
 774                    struct intel_crtc_state *crtc_state,
 775                    int target, int refclk, intel_clock_t *match_clock,
 776                    intel_clock_t *best_clock)
 777 {
 778         struct drm_device *dev = crtc_state->base.crtc->dev;
 779         intel_clock_t clock;
 780         int err = target;
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 787              clock.m1++) {
 788                 for (clock.m2 = limit->m2.min;
 789                      clock.m2 <= limit->m2.max; clock.m2++) {
 790                         for (clock.n = limit->n.min;
 791                              clock.n <= limit->n.max; clock.n++) {
 792                                 for (clock.p1 = limit->p1.min;
 793                                         clock.p1 <= limit->p1.max; clock.p1++) {
 794                                         int this_err;
 795
 796                                         pnv_calc_dpll_params(refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err) {
 806                                                 *best_clock = clock;
 807                                                 err = this_err;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813
 814         return (err != target);
 815 }
 816
 817 /*
 818  * Returns a set of divisors for the desired target clock with the given
 819  * refclk, or FALSE.  The returned values represent the clock equation:
 820  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 821  *
 822  * Target and reference clocks are specified in kHz.
 823  *
 824  * If match_clock is provided, then best_clock P divider must match the P
 825  * divider from @match_clock used for LVDS downclocking.
 826  */
 827 static bool
 828 g4x_find_best_dpll(const intel_limit_t *limit,
 829                    struct intel_crtc_state *crtc_state,
 830                    int target, int refclk, intel_clock_t *match_clock,
 831                    intel_clock_t *best_clock)
 832 {
 833         struct drm_device *dev = crtc_state->base.crtc->dev;
 834         intel_clock_t clock;
 835         int max_n;
 836         bool found = false;
 837         /* approximately equals target * 0.00585 */
 838         int err_most = (target >> 8) + (target >> 9);
 839
 840         memset(best_clock, 0, sizeof(*best_clock));
 841
 842         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 843
 844         max_n = limit->n.max;
 845         /* based on hardware requirement, prefer smaller n to precision */
 846         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 847                 /* based on hardware requirement, prefere larger m1,m2 */
 848                 for (clock.m1 = limit->m1.max;
 849                      clock.m1 >= limit->m1.min; clock.m1--) {
 850                         for (clock.m2 = limit->m2.max;
 851                              clock.m2 >= limit->m2.min; clock.m2--) {
 852                                 for (clock.p1 = limit->p1.max;
 853                                      clock.p1 >= limit->p1.min; clock.p1--) {
 854                                         int this_err;
 855
 856                                         i9xx_calc_dpll_params(refclk, &clock);
 857                                         if (!intel_PLL_is_valid(dev, limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         this_err = abs(clock.dot - target);
 862                                         if (this_err < err_most) {
 863                                                 *best_clock = clock;
 864                                                 err_most = this_err;
 865                                                 max_n = clock.n;
 866                                                 found = true;
 867                                         }
 868                                 }
 869                         }
 870                 }
 871         }
 872         return found;
 873 }
 874
 875 /*
 876  * Check if the calculated PLL configuration is more optimal compared to the
 877  * best configuration and error found so far. Return the calculated error.
 878  */
 879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 880                                const intel_clock_t *calculated_clock,
 881                                const intel_clock_t *best_clock,
 882                                unsigned int best_error_ppm,
 883                                unsigned int *error_ppm)
 884 {
 885         /*
 886          * For CHV ignore the error and consider only the P value.
 887          * Prefer a bigger P value based on HW requirements.
 888          */
 889         if (IS_CHERRYVIEW(dev)) {
 890                 *error_ppm = 0;
 891
 892                 return calculated_clock->p > best_clock->p;
 893         }
 894
 895         if (WARN_ON_ONCE(!target_freq))
 896                 return false;
 897
 898         *error_ppm = div_u64(1000000ULL *
 899                                 abs(target_freq - calculated_clock->dot),
 900                              target_freq);
 901         /*
 902          * Prefer a better P value over a better (smaller) error if the error
 903          * is small. Ensure this preference for future configurations too by
 904          * setting the error to 0.
 905          */
 906         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 907                 *error_ppm = 0;
 908
 909                 return true;
 910         }
 911
 912         return *error_ppm + 10 < best_error_ppm;
 913 }
 914
 915 /*
 916  * Returns a set of divisors for the desired target clock with the given
 917  * refclk, or FALSE.  The returned values represent the clock equation:
 918  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 919  */
 920 static bool
 921 vlv_find_best_dpll(const intel_limit_t *limit,
 922                    struct intel_crtc_state *crtc_state,
 923                    int target, int refclk, intel_clock_t *match_clock,
 924                    intel_clock_t *best_clock)
 925 {
 926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 927         struct drm_device *dev = crtc->base.dev;
 928         intel_clock_t clock;
 929         unsigned int bestppm = 1000000;
 930         /* min update 19.2 MHz */
 931         int max_n = min(limit->n.max, refclk / 19200);
 932         bool found = false;
 933
 934         target *= 5; /* fast clock */
 935
 936         memset(best_clock, 0, sizeof(*best_clock));
 937
 938         /* based on hardware requirement, prefer smaller n to precision */
 939         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 940                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 941                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 942                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 943                                 clock.p = clock.p1 * clock.p2;
 944                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 945                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 946                                         unsigned int ppm;
 947
 948                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 949                                                                      refclk * clock.m1);
 950
 951                                         vlv_calc_dpll_params(refclk, &clock);
 952
 953                                         if (!intel_PLL_is_valid(dev, limit,
 954                                                                 &clock))
 955                                                 continue;
 956
 957                                         if (!vlv_PLL_is_optimal(dev, target,
 958                                                                 &clock,
 959                                                                 best_clock,
 960                                                                 bestppm, &ppm))
 961                                                 continue;
 962
 963                                         *best_clock = clock;
 964                                         bestppm = ppm;
 965                                         found = true;
 966                                 }
 967                         }
 968                 }
 969         }
 970
 971         return found;
 972 }
 973
 974 /*
 975  * Returns a set of divisors for the desired target clock with the given
 976  * refclk, or FALSE.  The returned values represent the clock equation:
 977  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 978  */
 979 static bool
 980 chv_find_best_dpll(const intel_limit_t *limit,
 981                    struct intel_crtc_state *crtc_state,
 982                    int target, int refclk, intel_clock_t *match_clock,
 983                    intel_clock_t *best_clock)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 986         struct drm_device *dev = crtc->base.dev;
 987         unsigned int best_error_ppm;
 988         intel_clock_t clock;
 989         uint64_t m2;
 990         int found = false;
 991
 992         memset(best_clock, 0, sizeof(*best_clock));
 993         best_error_ppm = 1000000;
 994
 995         /*
 996          * Based on hardware doc, the n always set to 1, and m1 always
 997          * set to 2.  If requires to support 200Mhz refclk, we need to
 998          * revisit this because n may not 1 anymore.
 999          */
1000         clock.n = 1, clock.m1 = 2;
1001         target *= 5;    /* fast clock */
1002
1003         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004                 for (clock.p2 = limit->p2.p2_fast;
1005                                 clock.p2 >= limit->p2.p2_slow;
1006                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007                         unsigned int error_ppm;
1008
1009                         clock.p = clock.p1 * clock.p2;
1010
1011                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012                                         clock.n) << 22, refclk * clock.m1);
1013
1014                         if (m2 > INT_MAX/clock.m1)
1015                                 continue;
1016
1017                         clock.m2 = m2;
1018
1019                         chv_calc_dpll_params(refclk, &clock);
1020
1021                         if (!intel_PLL_is_valid(dev, limit, &clock))
1022                                 continue;
1023
1024                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025                                                 best_error_ppm, &error_ppm))
1026                                 continue;
1027
1028                         *best_clock = clock;
1029                         best_error_ppm = error_ppm;
1030                         found = true;
1031                 }
1032         }
1033
1034         return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038                         intel_clock_t *best_clock)
1039 {
1040         int refclk = 100000;
1041         const intel_limit_t *limit = &intel_limits_bxt;
1042
1043         return chv_find_best_dpll(limit, crtc_state,
1044                                   target_clock, refclk, NULL, best_clock);
1045 }
1046
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050
1051         /* Be paranoid as we can arrive here with only partial
1052          * state retrieved from the hardware during setup.
1053          *
1054          * We can ditch the adjusted_mode.crtc_clock check as soon
1055          * as Haswell has gained clock readout/fastboot support.
1056          *
1057          * We can ditch the crtc->primary->fb check as soon as we can
1058          * properly reconstruct framebuffers.
1059          *
1060          * FIXME: The intel_crtc->active here should be switched to
1061          * crtc->state->active once we have proper CRTC states wired up
1062          * for atomic.
1063          */
1064         return intel_crtc->active && crtc->primary->state->fb &&
1065                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069                                              enum pipe pipe)
1070 {
1071         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073
1074         return intel_crtc->config->cpu_transcoder;
1075 }
1076
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         i915_reg_t reg = PIPEDSL(pipe);
1081         u32 line1, line2;
1082         u32 line_mask;
1083
1084         if (IS_GEN2(dev))
1085                 line_mask = DSL_LINEMASK_GEN2;
1086         else
1087                 line_mask = DSL_LINEMASK_GEN3;
1088
1089         line1 = I915_READ(reg) & line_mask;
1090         msleep(5);
1091         line2 = I915_READ(reg) & line_mask;
1092
1093         return line1 == line2;
1094 }
1095
1096 /*
1097  * intel_wait_for_pipe_off - wait for pipe to turn off
1098  * @crtc: crtc whose pipe to wait for
1099  *
1100  * After disabling a pipe, we can't wait for vblank in the usual way,
1101  * spinning on the vblank interrupt status bit, since we won't actually
1102  * see an interrupt when the pipe is disabled.
1103  *
1104  * On Gen4 and above:
1105  *   wait for the pipe register state bit to turn off
1106  *
1107  * Otherwise:
1108  *   wait for the display line value to settle (it usually
1109  *   ends up stopping at the start of the next frame).
1110  *
1111  */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114         struct drm_device *dev = crtc->base.dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117         enum pipe pipe = crtc->pipe;
1118
1119         if (INTEL_INFO(dev)->gen >= 4) {
1120                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121
1122                 /* Wait for the Pipe State to go off */
1123                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124                              100))
1125                         WARN(1, "pipe_off wait timed out\n");
1126         } else {
1127                 /* Wait for the display line to settle */
1128                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129                         WARN(1, "pipe_off wait timed out\n");
1130         }
1131 }
1132
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135                 enum pipe pipe, bool state)
1136 {
1137         u32 val;
1138         bool cur_state;
1139
1140         val = I915_READ(DPLL(pipe));
1141         cur_state = !!(val & DPLL_VCO_ENABLE);
1142         I915_STATE_WARN(cur_state != state,
1143              "PLL state assertion failure (expected %s, current %s)\n",
1144                         onoff(state), onoff(cur_state));
1145 }
1146
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150         u32 val;
1151         bool cur_state;
1152
1153         mutex_lock(&dev_priv->sb_lock);
1154         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155         mutex_unlock(&dev_priv->sb_lock);
1156
1157         cur_state = val & DSI_PLL_VCO_EN;
1158         I915_STATE_WARN(cur_state != state,
1159              "DSI PLL state assertion failure (expected %s, current %s)\n",
1160                         onoff(state), onoff(cur_state));
1161 }
1162
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164                           enum pipe pipe, bool state)
1165 {
1166         bool cur_state;
1167         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168                                                                       pipe);
1169
1170         if (HAS_DDI(dev_priv)) {
1171                 /* DDI does not have a specific FDI_TX register */
1172                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174         } else {
1175                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176                 cur_state = !!(val & FDI_TX_ENABLE);
1177         }
1178         I915_STATE_WARN(cur_state != state,
1179              "FDI TX state assertion failure (expected %s, current %s)\n",
1180                         onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         u32 val;
1189         bool cur_state;
1190
1191         val = I915_READ(FDI_RX_CTL(pipe));
1192         cur_state = !!(val & FDI_RX_ENABLE);
1193         I915_STATE_WARN(cur_state != state,
1194              "FDI RX state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201                                       enum pipe pipe)
1202 {
1203         u32 val;
1204
1205         /* ILK FDI PLL is always enabled */
1206         if (INTEL_INFO(dev_priv)->gen == 5)
1207                 return;
1208
1209         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210         if (HAS_DDI(dev_priv))
1211                 return;
1212
1213         val = I915_READ(FDI_TX_CTL(pipe));
1214         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218                        enum pipe pipe, bool state)
1219 {
1220         u32 val;
1221         bool cur_state;
1222
1223         val = I915_READ(FDI_RX_CTL(pipe));
1224         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225         I915_STATE_WARN(cur_state != state,
1226              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227                         onoff(state), onoff(cur_state));
1228 }
1229
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231                            enum pipe pipe)
1232 {
1233         struct drm_device *dev = dev_priv->dev;
1234         i915_reg_t pp_reg;
1235         u32 val;
1236         enum pipe panel_pipe = PIPE_A;
1237         bool locked = true;
1238
1239         if (WARN_ON(HAS_DDI(dev)))
1240                 return;
1241
1242         if (HAS_PCH_SPLIT(dev)) {
1243                 u32 port_sel;
1244
1245                 pp_reg = PCH_PP_CONTROL;
1246                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247
1248                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250                         panel_pipe = PIPE_B;
1251                 /* XXX: else fix for eDP */
1252         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253                 /* presumably write lock depends on pipe, not port select */
1254                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255                 panel_pipe = pipe;
1256         } else {
1257                 pp_reg = PP_CONTROL;
1258                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259                         panel_pipe = PIPE_B;
1260         }
1261
1262         val = I915_READ(pp_reg);
1263         if (!(val & PANEL_POWER_ON) ||
1264             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265                 locked = false;
1266
1267         I915_STATE_WARN(panel_pipe == pipe && locked,
1268              "panel assertion failure, pipe %c regs locked\n",
1269              pipe_name(pipe));
1270 }
1271
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273                           enum pipe pipe, bool state)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         bool cur_state;
1277
1278         if (IS_845G(dev) || IS_I865G(dev))
1279                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280         else
1281                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282
1283         I915_STATE_WARN(cur_state != state,
1284              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285                         pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291                  enum pipe pipe, bool state)
1292 {
1293         bool cur_state;
1294         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295                                                                       pipe);
1296         enum intel_display_power_domain power_domain;
1297
1298         /* if we need the pipe quirk it must be always on */
1299         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301                 state = true;
1302
1303         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306                 cur_state = !!(val & PIPECONF_ENABLE);
1307
1308                 intel_display_power_put(dev_priv, power_domain);
1309         } else {
1310                 cur_state = false;
1311         }
1312
1313         I915_STATE_WARN(cur_state != state,
1314              "pipe %c assertion failure (expected %s, current %s)\n",
1315                         pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319                          enum plane plane, bool state)
1320 {
1321         u32 val;
1322         bool cur_state;
1323
1324         val = I915_READ(DSPCNTR(plane));
1325         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326         I915_STATE_WARN(cur_state != state,
1327              "plane %c assertion failure (expected %s, current %s)\n",
1328                         plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335                                    enum pipe pipe)
1336 {
1337         struct drm_device *dev = dev_priv->dev;
1338         int i;
1339
1340         /* Primary planes are fixed to pipes on gen4+ */
1341         if (INTEL_INFO(dev)->gen >= 4) {
1342                 u32 val = I915_READ(DSPCNTR(pipe));
1343                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344                      "plane %c assertion failure, should be disabled but not\n",
1345                      plane_name(pipe));
1346                 return;
1347         }
1348
1349         /* Need to check both planes against the pipe */
1350         for_each_pipe(dev_priv, i) {
1351                 u32 val = I915_READ(DSPCNTR(i));
1352                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353                         DISPPLANE_SEL_PIPE_SHIFT;
1354                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356                      plane_name(i), pipe_name(pipe));
1357         }
1358 }
1359
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361                                     enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int sprite;
1365
1366         if (INTEL_INFO(dev)->gen >= 9) {
1367                 for_each_sprite(dev_priv, pipe, sprite) {
1368                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371                              sprite, pipe_name(pipe));
1372                 }
1373         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374                 for_each_sprite(dev_priv, pipe, sprite) {
1375                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1376                         I915_STATE_WARN(val & SP_ENABLE,
1377                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378                              sprite_name(pipe, sprite), pipe_name(pipe));
1379                 }
1380         } else if (INTEL_INFO(dev)->gen >= 7) {
1381                 u32 val = I915_READ(SPRCTL(pipe));
1382                 I915_STATE_WARN(val & SPRITE_ENABLE,
1383                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384                      plane_name(pipe), pipe_name(pipe));
1385         } else if (INTEL_INFO(dev)->gen >= 5) {
1386                 u32 val = I915_READ(DVSCNTR(pipe));
1387                 I915_STATE_WARN(val & DVS_ENABLE,
1388                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(pipe), pipe_name(pipe));
1390         }
1391 }
1392
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396                 drm_crtc_vblank_put(crtc);
1397 }
1398
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400                                     enum pipe pipe)
1401 {
1402         u32 val;
1403         bool enabled;
1404
1405         val = I915_READ(PCH_TRANSCONF(pipe));
1406         enabled = !!(val & TRANS_ENABLE);
1407         I915_STATE_WARN(enabled,
1408              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409              pipe_name(pipe));
1410 }
1411
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413                             enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415         if ((val & DP_PORT_EN) == 0)
1416                 return false;
1417
1418         if (HAS_PCH_CPT(dev_priv)) {
1419                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421                         return false;
1422         } else if (IS_CHERRYVIEW(dev_priv)) {
1423                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424                         return false;
1425         } else {
1426                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427                         return false;
1428         }
1429         return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433                               enum pipe pipe, u32 val)
1434 {
1435         if ((val & SDVO_ENABLE) == 0)
1436                 return false;
1437
1438         if (HAS_PCH_CPT(dev_priv)) {
1439                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440                         return false;
1441         } else if (IS_CHERRYVIEW(dev_priv)) {
1442                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443                         return false;
1444         } else {
1445                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446                         return false;
1447         }
1448         return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452                               enum pipe pipe, u32 val)
1453 {
1454         if ((val & LVDS_PORT_EN) == 0)
1455                 return false;
1456
1457         if (HAS_PCH_CPT(dev_priv)) {
1458                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459                         return false;
1460         } else {
1461                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462                         return false;
1463         }
1464         return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468                               enum pipe pipe, u32 val)
1469 {
1470         if ((val & ADPA_DAC_ENABLE) == 0)
1471                 return false;
1472         if (HAS_PCH_CPT(dev_priv)) {
1473                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483                                    enum pipe pipe, i915_reg_t reg,
1484                                    u32 port_sel)
1485 {
1486         u32 val = I915_READ(reg);
1487         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489              i915_mmio_reg_offset(reg), pipe_name(pipe));
1490
1491         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1492              && (val & DP_PIPEB_SELECT),
1493              "IBX PCH dp port still using transcoder B\n");
1494 }
1495
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497                                      enum pipe pipe, i915_reg_t reg)
1498 {
1499         u32 val = I915_READ(reg);
1500         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502              i915_mmio_reg_offset(reg), pipe_name(pipe));
1503
1504         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1505              && (val & SDVO_PIPE_B_SELECT),
1506              "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510                                       enum pipe pipe)
1511 {
1512         u32 val;
1513
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518         val = I915_READ(PCH_ADPA);
1519         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520              "PCH VGA enabled on transcoder %c, should be disabled\n",
1521              pipe_name(pipe));
1522
1523         val = I915_READ(PCH_LVDS);
1524         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526              pipe_name(pipe));
1527
1528         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc,
1534                            const struct intel_crtc_state *pipe_config)
1535 {
1536         struct drm_device *dev = crtc->base.dev;
1537         struct drm_i915_private *dev_priv = dev->dev_private;
1538         enum pipe pipe = crtc->pipe;
1539         i915_reg_t reg = DPLL(pipe);
1540         u32 dpll = pipe_config->dpll_hw_state.dpll;
1541
1542         assert_pipe_disabled(dev_priv, pipe);
1543
1544         /* PLL is protected by panel, make sure we can write it */
1545         assert_panel_unlocked(dev_priv, pipe);
1546
1547         I915_WRITE(reg, dpll);
1548         POSTING_READ(reg);
1549         udelay(150);
1550
1551         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1553
1554         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1555         POSTING_READ(DPLL_MD(pipe));
1556 }
1557
1558 static void chv_enable_pll(struct intel_crtc *crtc,
1559                            const struct intel_crtc_state *pipe_config)
1560 {
1561         struct drm_device *dev = crtc->base.dev;
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         enum pipe pipe = crtc->pipe;
1564         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1565         u32 tmp;
1566
1567         assert_pipe_disabled(dev_priv, pipe);
1568
1569         /* PLL is protected by panel, make sure we can write it */
1570         assert_panel_unlocked(dev_priv, pipe);
1571
1572         mutex_lock(&dev_priv->sb_lock);
1573
1574         /* Enable back the 10bit clock to display controller */
1575         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576         tmp |= DPIO_DCLKP_EN;
1577         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579         mutex_unlock(&dev_priv->sb_lock);
1580
1581         /*
1582          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583          */
1584         udelay(1);
1585
1586         /* Enable PLL */
1587         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589         /* Check PLL is locked */
1590         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592
1593         if (pipe != PIPE_A) {
1594                 /*
1595                  * WaPixelRepeatModeFixForC0:chv
1596                  *
1597                  * DPLLCMD is AWOL. Use chicken bits to propagate
1598                  * the value from DPLLBMD to either pipe B or C.
1599                  */
1600                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1601                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1602                 I915_WRITE(CBR4_VLV, 0);
1603                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1604
1605                 /*
1606                  * DPLLB VGA mode also seems to cause problems.
1607                  * We should always have it disabled.
1608                  */
1609                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1610         } else {
1611                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1612                 POSTING_READ(DPLL_MD(pipe));
1613         }
1614 }
1615
1616 static int intel_num_dvo_pipes(struct drm_device *dev)
1617 {
1618         struct intel_crtc *crtc;
1619         int count = 0;
1620
1621         for_each_intel_crtc(dev, crtc)
1622                 count += crtc->base.state->active &&
1623                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1624
1625         return count;
1626 }
1627
1628 static void i9xx_enable_pll(struct intel_crtc *crtc)
1629 {
1630         struct drm_device *dev = crtc->base.dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         i915_reg_t reg = DPLL(crtc->pipe);
1633         u32 dpll = crtc->config->dpll_hw_state.dpll;
1634
1635         assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637         /* PLL is protected by panel, make sure we can write it */
1638         if (IS_MOBILE(dev) && !IS_I830(dev))
1639                 assert_panel_unlocked(dev_priv, crtc->pipe);
1640
1641         /* Enable DVO 2x clock on both PLLs if necessary */
1642         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1643                 /*
1644                  * It appears to be important that we don't enable this
1645                  * for the current pipe before otherwise configuring the
1646                  * PLL. No idea how this should be handled if multiple
1647                  * DVO outputs are enabled simultaneosly.
1648                  */
1649                 dpll |= DPLL_DVO_2X_MODE;
1650                 I915_WRITE(DPLL(!crtc->pipe),
1651                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1652         }
1653
1654         /*
1655          * Apparently we need to have VGA mode enabled prior to changing
1656          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1657          * dividers, even though the register value does change.
1658          */
1659         I915_WRITE(reg, 0);
1660
1661         I915_WRITE(reg, dpll);
1662
1663         /* Wait for the clocks to stabilize. */
1664         POSTING_READ(reg);
1665         udelay(150);
1666
1667         if (INTEL_INFO(dev)->gen >= 4) {
1668                 I915_WRITE(DPLL_MD(crtc->pipe),
1669                            crtc->config->dpll_hw_state.dpll_md);
1670         } else {
1671                 /* The pixel multiplier can only be updated once the
1672                  * DPLL is enabled and the clocks are stable.
1673                  *
1674                  * So write it again.
1675                  */
1676                 I915_WRITE(reg, dpll);
1677         }
1678
1679         /* We do this three times for luck */
1680         I915_WRITE(reg, dpll);
1681         POSTING_READ(reg);
1682         udelay(150); /* wait for warmup */
1683         I915_WRITE(reg, dpll);
1684         POSTING_READ(reg);
1685         udelay(150); /* wait for warmup */
1686         I915_WRITE(reg, dpll);
1687         POSTING_READ(reg);
1688         udelay(150); /* wait for warmup */
1689 }
1690
1691 /**
1692  * i9xx_disable_pll - disable a PLL
1693  * @dev_priv: i915 private structure
1694  * @pipe: pipe PLL to disable
1695  *
1696  * Disable the PLL for @pipe, making sure the pipe is off first.
1697  *
1698  * Note!  This is for pre-ILK only.
1699  */
1700 static void i9xx_disable_pll(struct intel_crtc *crtc)
1701 {
1702         struct drm_device *dev = crtc->base.dev;
1703         struct drm_i915_private *dev_priv = dev->dev_private;
1704         enum pipe pipe = crtc->pipe;
1705
1706         /* Disable DVO 2x clock on both PLLs if necessary */
1707         if (IS_I830(dev) &&
1708             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1709             !intel_num_dvo_pipes(dev)) {
1710                 I915_WRITE(DPLL(PIPE_B),
1711                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1712                 I915_WRITE(DPLL(PIPE_A),
1713                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1714         }
1715
1716         /* Don't disable pipe or pipe PLLs if needed */
1717         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1718             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1719                 return;
1720
1721         /* Make sure the pipe isn't still relying on us */
1722         assert_pipe_disabled(dev_priv, pipe);
1723
1724         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         u32 val;
1731
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734
1735         val = DPLL_INTEGRATED_REF_CLK_VLV |
1736                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737         if (pipe != PIPE_A)
1738                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740         I915_WRITE(DPLL(pipe), val);
1741         POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1747         u32 val;
1748
1749         /* Make sure the pipe isn't still relying on us */
1750         assert_pipe_disabled(dev_priv, pipe);
1751
1752         val = DPLL_SSC_REF_CLK_CHV |
1753                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754         if (pipe != PIPE_A)
1755                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756
1757         I915_WRITE(DPLL(pipe), val);
1758         POSTING_READ(DPLL(pipe));
1759
1760         mutex_lock(&dev_priv->sb_lock);
1761
1762         /* Disable 10bit clock to display controller */
1763         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1764         val &= ~DPIO_DCLKP_EN;
1765         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1766
1767         mutex_unlock(&dev_priv->sb_lock);
1768 }
1769
1770 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1771                          struct intel_digital_port *dport,
1772                          unsigned int expected_mask)
1773 {
1774         u32 port_mask;
1775         i915_reg_t dpll_reg;
1776
1777         switch (dport->port) {
1778         case PORT_B:
1779                 port_mask = DPLL_PORTB_READY_MASK;
1780                 dpll_reg = DPLL(0);
1781                 break;
1782         case PORT_C:
1783                 port_mask = DPLL_PORTC_READY_MASK;
1784                 dpll_reg = DPLL(0);
1785                 expected_mask <<= 4;
1786                 break;
1787         case PORT_D:
1788                 port_mask = DPLL_PORTD_READY_MASK;
1789                 dpll_reg = DPIO_PHY_STATUS;
1790                 break;
1791         default:
1792                 BUG();
1793         }
1794
1795         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1796                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1797                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1798 }
1799
1800 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1801                                            enum pipe pipe)
1802 {
1803         struct drm_device *dev = dev_priv->dev;
1804         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806         i915_reg_t reg;
1807         uint32_t val, pipeconf_val;
1808
1809         /* Make sure PCH DPLL is enabled */
1810         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1811
1812         /* FDI must be feeding us bits for PCH ports */
1813         assert_fdi_tx_enabled(dev_priv, pipe);
1814         assert_fdi_rx_enabled(dev_priv, pipe);
1815
1816         if (HAS_PCH_CPT(dev)) {
1817                 /* Workaround: Set the timing override bit before enabling the
1818                  * pch transcoder. */
1819                 reg = TRANS_CHICKEN2(pipe);
1820                 val = I915_READ(reg);
1821                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1822                 I915_WRITE(reg, val);
1823         }
1824
1825         reg = PCH_TRANSCONF(pipe);
1826         val = I915_READ(reg);
1827         pipeconf_val = I915_READ(PIPECONF(pipe));
1828
1829         if (HAS_PCH_IBX(dev_priv)) {
1830                 /*
1831                  * Make the BPC in transcoder be consistent with
1832                  * that in pipeconf reg. For HDMI we must use 8bpc
1833                  * here for both 8bpc and 12bpc.
1834                  */
1835                 val &= ~PIPECONF_BPC_MASK;
1836                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1837                         val |= PIPECONF_8BPC;
1838                 else
1839                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1840         }
1841
1842         val &= ~TRANS_INTERLACE_MASK;
1843         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1844                 if (HAS_PCH_IBX(dev_priv) &&
1845                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1846                         val |= TRANS_LEGACY_INTERLACED_ILK;
1847                 else
1848                         val |= TRANS_INTERLACED;
1849         else
1850                 val |= TRANS_PROGRESSIVE;
1851
1852         I915_WRITE(reg, val | TRANS_ENABLE);
1853         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1854                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1855 }
1856
1857 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1858                                       enum transcoder cpu_transcoder)
1859 {
1860         u32 val, pipeconf_val;
1861
1862         /* FDI must be feeding us bits for PCH ports */
1863         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1864         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1865
1866         /* Workaround: set timing override bit. */
1867         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1869         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870
1871         val = TRANS_ENABLE;
1872         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1873
1874         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1875             PIPECONF_INTERLACED_ILK)
1876                 val |= TRANS_INTERLACED;
1877         else
1878                 val |= TRANS_PROGRESSIVE;
1879
1880         I915_WRITE(LPT_TRANSCONF, val);
1881         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1882                 DRM_ERROR("Failed to enable PCH transcoder\n");
1883 }
1884
1885 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1886                                             enum pipe pipe)
1887 {
1888         struct drm_device *dev = dev_priv->dev;
1889         i915_reg_t reg;
1890         uint32_t val;
1891
1892         /* FDI relies on the transcoder */
1893         assert_fdi_tx_disabled(dev_priv, pipe);
1894         assert_fdi_rx_disabled(dev_priv, pipe);
1895
1896         /* Ports must be off as well */
1897         assert_pch_ports_disabled(dev_priv, pipe);
1898
1899         reg = PCH_TRANSCONF(pipe);
1900         val = I915_READ(reg);
1901         val &= ~TRANS_ENABLE;
1902         I915_WRITE(reg, val);
1903         /* wait for PCH transcoder off, transcoder state */
1904         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1905                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1906
1907         if (HAS_PCH_CPT(dev)) {
1908                 /* Workaround: Clear the timing override chicken bit again. */
1909                 reg = TRANS_CHICKEN2(pipe);
1910                 val = I915_READ(reg);
1911                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1912                 I915_WRITE(reg, val);
1913         }
1914 }
1915
1916 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1917 {
1918         u32 val;
1919
1920         val = I915_READ(LPT_TRANSCONF);
1921         val &= ~TRANS_ENABLE;
1922         I915_WRITE(LPT_TRANSCONF, val);
1923         /* wait for PCH transcoder off, transcoder state */
1924         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1925                 DRM_ERROR("Failed to disable PCH transcoder\n");
1926
1927         /* Workaround: clear timing override bit. */
1928         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1929         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1931 }
1932
1933 /**
1934  * intel_enable_pipe - enable a pipe, asserting requirements
1935  * @crtc: crtc responsible for the pipe
1936  *
1937  * Enable @crtc's pipe, making sure that various hardware specific requirements
1938  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939  */
1940 static void intel_enable_pipe(struct intel_crtc *crtc)
1941 {
1942         struct drm_device *dev = crtc->base.dev;
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         enum pipe pipe = crtc->pipe;
1945         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1946         enum pipe pch_transcoder;
1947         i915_reg_t reg;
1948         u32 val;
1949
1950         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1951
1952         assert_planes_disabled(dev_priv, pipe);
1953         assert_cursor_disabled(dev_priv, pipe);
1954         assert_sprites_disabled(dev_priv, pipe);
1955
1956         if (HAS_PCH_LPT(dev_priv))
1957                 pch_transcoder = TRANSCODER_A;
1958         else
1959                 pch_transcoder = pipe;
1960
1961         /*
1962          * A pipe without a PLL won't actually be able to drive bits from
1963          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1964          * need the check.
1965          */
1966         if (HAS_GMCH_DISPLAY(dev_priv))
1967                 if (crtc->config->has_dsi_encoder)
1968                         assert_dsi_pll_enabled(dev_priv);
1969                 else
1970                         assert_pll_enabled(dev_priv, pipe);
1971         else {
1972                 if (crtc->config->has_pch_encoder) {
1973                         /* if driving the PCH, we need FDI enabled */
1974                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1975                         assert_fdi_tx_pll_enabled(dev_priv,
1976                                                   (enum pipe) cpu_transcoder);
1977                 }
1978                 /* FIXME: assert CPU port conditions for SNB+ */
1979         }
1980
1981         reg = PIPECONF(cpu_transcoder);
1982         val = I915_READ(reg);
1983         if (val & PIPECONF_ENABLE) {
1984                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1985                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1986                 return;
1987         }
1988
1989         I915_WRITE(reg, val | PIPECONF_ENABLE);
1990         POSTING_READ(reg);
1991
1992         /*
1993          * Until the pipe starts DSL will read as 0, which would cause
1994          * an apparent vblank timestamp jump, which messes up also the
1995          * frame count when it's derived from the timestamps. So let's
1996          * wait for the pipe to start properly before we call
1997          * drm_crtc_vblank_on()
1998          */
1999         if (dev->max_vblank_count == 0 &&
2000             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2001                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2002 }
2003
2004 /**
2005  * intel_disable_pipe - disable a pipe, asserting requirements
2006  * @crtc: crtc whose pipes is to be disabled
2007  *
2008  * Disable the pipe of @crtc, making sure that various hardware
2009  * specific requirements are met, if applicable, e.g. plane
2010  * disabled, panel fitter off, etc.
2011  *
2012  * Will wait until the pipe has shut down before returning.
2013  */
2014 static void intel_disable_pipe(struct intel_crtc *crtc)
2015 {
2016         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2017         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2018         enum pipe pipe = crtc->pipe;
2019         i915_reg_t reg;
2020         u32 val;
2021
2022         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2023
2024         /*
2025          * Make sure planes won't keep trying to pump pixels to us,
2026          * or we might hang the display.
2027          */
2028         assert_planes_disabled(dev_priv, pipe);
2029         assert_cursor_disabled(dev_priv, pipe);
2030         assert_sprites_disabled(dev_priv, pipe);
2031
2032         reg = PIPECONF(cpu_transcoder);
2033         val = I915_READ(reg);
2034         if ((val & PIPECONF_ENABLE) == 0)
2035                 return;
2036
2037         /*
2038          * Double wide has implications for planes
2039          * so best keep it disabled when not needed.
2040          */
2041         if (crtc->config->double_wide)
2042                 val &= ~PIPECONF_DOUBLE_WIDE;
2043
2044         /* Don't disable pipe or pipe PLLs if needed */
2045         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2046             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2047                 val &= ~PIPECONF_ENABLE;
2048
2049         I915_WRITE(reg, val);
2050         if ((val & PIPECONF_ENABLE) == 0)
2051                 intel_wait_for_pipe_off(crtc);
2052 }
2053
2054 static bool need_vtd_wa(struct drm_device *dev)
2055 {
2056 #ifdef CONFIG_INTEL_IOMMU
2057         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2058                 return true;
2059 #endif
2060         return false;
2061 }
2062
2063 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2064 {
2065         return IS_GEN2(dev_priv) ? 2048 : 4096;
2066 }
2067
2068 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2069                                            uint64_t fb_modifier, unsigned int cpp)
2070 {
2071         switch (fb_modifier) {
2072         case DRM_FORMAT_MOD_NONE:
2073                 return cpp;
2074         case I915_FORMAT_MOD_X_TILED:
2075                 if (IS_GEN2(dev_priv))
2076                         return 128;
2077                 else
2078                         return 512;
2079         case I915_FORMAT_MOD_Y_TILED:
2080                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2081                         return 128;
2082                 else
2083                         return 512;
2084         case I915_FORMAT_MOD_Yf_TILED:
2085                 switch (cpp) {
2086                 case 1:
2087                         return 64;
2088                 case 2:
2089                 case 4:
2090                         return 128;
2091                 case 8:
2092                 case 16:
2093                         return 256;
2094                 default:
2095                         MISSING_CASE(cpp);
2096                         return cpp;
2097                 }
2098                 break;
2099         default:
2100                 MISSING_CASE(fb_modifier);
2101                 return cpp;
2102         }
2103 }
2104
2105 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2106                                uint64_t fb_modifier, unsigned int cpp)
2107 {
2108         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2109                 return 1;
2110         else
2111                 return intel_tile_size(dev_priv) /
2112                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2113 }
2114
2115 /* Return the tile dimensions in pixel units */
2116 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2117                             unsigned int *tile_width,
2118                             unsigned int *tile_height,
2119                             uint64_t fb_modifier,
2120                             unsigned int cpp)
2121 {
2122         unsigned int tile_width_bytes =
2123                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2124
2125         *tile_width = tile_width_bytes / cpp;
2126         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2127 }
2128
2129 unsigned int
2130 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2131                       uint32_t pixel_format, uint64_t fb_modifier)
2132 {
2133         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2134         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2135
2136         return ALIGN(height, tile_height);
2137 }
2138
2139 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2140 {
2141         unsigned int size = 0;
2142         int i;
2143
2144         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2145                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2146
2147         return size;
2148 }
2149
2150 static void
2151 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2152                         const struct drm_framebuffer *fb,
2153                         unsigned int rotation)
2154 {
2155         if (intel_rotation_90_or_270(rotation)) {
2156                 *view = i915_ggtt_view_rotated;
2157                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2158         } else {
2159                 *view = i915_ggtt_view_normal;
2160         }
2161 }
2162
2163 static void
2164 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2165                    struct drm_framebuffer *fb)
2166 {
2167         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2168         unsigned int tile_size, tile_width, tile_height, cpp;
2169
2170         tile_size = intel_tile_size(dev_priv);
2171
2172         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2173         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2174                         fb->modifier[0], cpp);
2175
2176         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2177         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2178
2179         if (info->pixel_format == DRM_FORMAT_NV12) {
2180                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2181                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2182                                 fb->modifier[1], cpp);
2183
2184                 info->uv_offset = fb->offsets[1];
2185                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2186                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2187         }
2188 }
2189
2190 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2191 {
2192         if (INTEL_INFO(dev_priv)->gen >= 9)
2193                 return 256 * 1024;
2194         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2195                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2196                 return 128 * 1024;
2197         else if (INTEL_INFO(dev_priv)->gen >= 4)
2198                 return 4 * 1024;
2199         else
2200                 return 0;
2201 }
2202
2203 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2204                                          uint64_t fb_modifier)
2205 {
2206         switch (fb_modifier) {
2207         case DRM_FORMAT_MOD_NONE:
2208                 return intel_linear_alignment(dev_priv);
2209         case I915_FORMAT_MOD_X_TILED:
2210                 if (INTEL_INFO(dev_priv)->gen >= 9)
2211                         return 256 * 1024;
2212                 return 0;
2213         case I915_FORMAT_MOD_Y_TILED:
2214         case I915_FORMAT_MOD_Yf_TILED:
2215                 return 1 * 1024 * 1024;
2216         default:
2217                 MISSING_CASE(fb_modifier);
2218                 return 0;
2219         }
2220 }
2221
2222 int
2223 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2224                            unsigned int rotation)
2225 {
2226         struct drm_device *dev = fb->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2229         struct i915_ggtt_view view;
2230         u32 alignment;
2231         int ret;
2232
2233         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2234
2235         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2236
2237         intel_fill_fb_ggtt_view(&view, fb, rotation);
2238
2239         /* Note that the w/a also requires 64 PTE of padding following the
2240          * bo. We currently fill all unused PTE with the shadow page and so
2241          * we should always have valid PTE following the scanout preventing
2242          * the VT-d warning.
2243          */
2244         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245                 alignment = 256 * 1024;
2246
2247         /*
2248          * Global gtt pte registers are special registers which actually forward
2249          * writes to a chunk of system memory. Which means that there is no risk
2250          * that the register values disappear as soon as we call
2251          * intel_runtime_pm_put(), so it is correct to wrap only the
2252          * pin/unpin/fence and not more.
2253          */
2254         intel_runtime_pm_get(dev_priv);
2255
2256         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2257                                                    &view);
2258         if (ret)
2259                 goto err_pm;
2260
2261         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262          * fence, whereas 965+ only requires a fence if using
2263          * framebuffer compression.  For simplicity, we always install
2264          * a fence as the cost is not that onerous.
2265          */
2266         if (view.type == I915_GGTT_VIEW_NORMAL) {
2267                 ret = i915_gem_object_get_fence(obj);
2268                 if (ret == -EDEADLK) {
2269                         /*
2270                          * -EDEADLK means there are no free fences
2271                          * no pending flips.
2272                          *
2273                          * This is propagated to atomic, but it uses
2274                          * -EDEADLK to force a locking recovery, so
2275                          * change the returned error to -EBUSY.
2276                          */
2277                         ret = -EBUSY;
2278                         goto err_unpin;
2279                 } else if (ret)
2280                         goto err_unpin;
2281
2282                 i915_gem_object_pin_fence(obj);
2283         }
2284
2285         intel_runtime_pm_put(dev_priv);
2286         return 0;
2287
2288 err_unpin:
2289         i915_gem_object_unpin_from_display_plane(obj, &view);
2290 err_pm:
2291         intel_runtime_pm_put(dev_priv);
2292         return ret;
2293 }
2294
2295 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2296 {
2297         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2298         struct i915_ggtt_view view;
2299
2300         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2301
2302         intel_fill_fb_ggtt_view(&view, fb, rotation);
2303
2304         if (view.type == I915_GGTT_VIEW_NORMAL)
2305                 i915_gem_object_unpin_fence(obj);
2306
2307         i915_gem_object_unpin_from_display_plane(obj, &view);
2308 }
2309
2310 /*
2311  * Adjust the tile offset by moving the difference into
2312  * the x/y offsets.
2313  *
2314  * Input tile dimensions and pitch must already be
2315  * rotated to match x and y, and in pixel units.
2316  */
2317 static u32 intel_adjust_tile_offset(int *x, int *y,
2318                                     unsigned int tile_width,
2319                                     unsigned int tile_height,
2320                                     unsigned int tile_size,
2321                                     unsigned int pitch_tiles,
2322                                     u32 old_offset,
2323                                     u32 new_offset)
2324 {
2325         unsigned int tiles;
2326
2327         WARN_ON(old_offset & (tile_size - 1));
2328         WARN_ON(new_offset & (tile_size - 1));
2329         WARN_ON(new_offset > old_offset);
2330
2331         tiles = (old_offset - new_offset) / tile_size;
2332
2333         *y += tiles / pitch_tiles * tile_height;
2334         *x += tiles % pitch_tiles * tile_width;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Computes the linear offset to the base tile and adjusts
2341  * x, y. bytes per pixel is assumed to be a power-of-two.
2342  *
2343  * In the 90/270 rotated case, x and y are assumed
2344  * to be already rotated to match the rotated GTT view, and
2345  * pitch is the tile_height aligned framebuffer height.
2346  */
2347 u32 intel_compute_tile_offset(int *x, int *y,
2348                               const struct drm_framebuffer *fb, int plane,
2349                               unsigned int pitch,
2350                               unsigned int rotation)
2351 {
2352         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2353         uint64_t fb_modifier = fb->modifier[plane];
2354         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2355         u32 offset, offset_aligned, alignment;
2356
2357         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2358         if (alignment)
2359                 alignment--;
2360
2361         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2362                 unsigned int tile_size, tile_width, tile_height;
2363                 unsigned int tile_rows, tiles, pitch_tiles;
2364
2365                 tile_size = intel_tile_size(dev_priv);
2366                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2367                                 fb_modifier, cpp);
2368
2369                 if (intel_rotation_90_or_270(rotation)) {
2370                         pitch_tiles = pitch / tile_height;
2371                         swap(tile_width, tile_height);
2372                 } else {
2373                         pitch_tiles = pitch / (tile_width * cpp);
2374                 }
2375
2376                 tile_rows = *y / tile_height;
2377                 *y %= tile_height;
2378
2379                 tiles = *x / tile_width;
2380                 *x %= tile_width;
2381
2382                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2383                 offset_aligned = offset & ~alignment;
2384
2385                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2386                                          tile_size, pitch_tiles,
2387                                          offset, offset_aligned);
2388         } else {
2389                 offset = *y * pitch + *x * cpp;
2390                 offset_aligned = offset & ~alignment;
2391
2392                 *y = (offset & alignment) / pitch;
2393                 *x = ((offset & alignment) - *y * pitch) / cpp;
2394         }
2395
2396         return offset_aligned;
2397 }
2398
2399 static int i9xx_format_to_fourcc(int format)
2400 {
2401         switch (format) {
2402         case DISPPLANE_8BPP:
2403                 return DRM_FORMAT_C8;
2404         case DISPPLANE_BGRX555:
2405                 return DRM_FORMAT_XRGB1555;
2406         case DISPPLANE_BGRX565:
2407                 return DRM_FORMAT_RGB565;
2408         default:
2409         case DISPPLANE_BGRX888:
2410                 return DRM_FORMAT_XRGB8888;
2411         case DISPPLANE_RGBX888:
2412                 return DRM_FORMAT_XBGR8888;
2413         case DISPPLANE_BGRX101010:
2414                 return DRM_FORMAT_XRGB2101010;
2415         case DISPPLANE_RGBX101010:
2416                 return DRM_FORMAT_XBGR2101010;
2417         }
2418 }
2419
2420 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2421 {
2422         switch (format) {
2423         case PLANE_CTL_FORMAT_RGB_565:
2424                 return DRM_FORMAT_RGB565;
2425         default:
2426         case PLANE_CTL_FORMAT_XRGB_8888:
2427                 if (rgb_order) {
2428                         if (alpha)
2429                                 return DRM_FORMAT_ABGR8888;
2430                         else
2431                                 return DRM_FORMAT_XBGR8888;
2432                 } else {
2433                         if (alpha)
2434                                 return DRM_FORMAT_ARGB8888;
2435                         else
2436                                 return DRM_FORMAT_XRGB8888;
2437                 }
2438         case PLANE_CTL_FORMAT_XRGB_2101010:
2439                 if (rgb_order)
2440                         return DRM_FORMAT_XBGR2101010;
2441                 else
2442                         return DRM_FORMAT_XRGB2101010;
2443         }
2444 }
2445
2446 static bool
2447 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2448                               struct intel_initial_plane_config *plane_config)
2449 {
2450         struct drm_device *dev = crtc->base.dev;
2451         struct drm_i915_private *dev_priv = to_i915(dev);
2452         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2453         struct drm_i915_gem_object *obj = NULL;
2454         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2455         struct drm_framebuffer *fb = &plane_config->fb->base;
2456         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2457         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2458                                     PAGE_SIZE);
2459
2460         size_aligned -= base_aligned;
2461
2462         if (plane_config->size == 0)
2463                 return false;
2464
2465         /* If the FB is too big, just don't use it since fbdev is not very
2466          * important and we should probably use that space with FBC or other
2467          * features. */
2468         if (size_aligned * 2 > ggtt->stolen_usable_size)
2469                 return false;
2470
2471         mutex_lock(&dev->struct_mutex);
2472
2473         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2474                                                              base_aligned,
2475                                                              base_aligned,
2476                                                              size_aligned);
2477         if (!obj) {
2478                 mutex_unlock(&dev->struct_mutex);
2479                 return false;
2480         }
2481
2482         obj->tiling_mode = plane_config->tiling;
2483         if (obj->tiling_mode == I915_TILING_X)
2484                 obj->stride = fb->pitches[0];
2485
2486         mode_cmd.pixel_format = fb->pixel_format;
2487         mode_cmd.width = fb->width;
2488         mode_cmd.height = fb->height;
2489         mode_cmd.pitches[0] = fb->pitches[0];
2490         mode_cmd.modifier[0] = fb->modifier[0];
2491         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2492
2493         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2494                                    &mode_cmd, obj)) {
2495                 DRM_DEBUG_KMS("intel fb init failed\n");
2496                 goto out_unref_obj;
2497         }
2498
2499         mutex_unlock(&dev->struct_mutex);
2500
2501         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2502         return true;
2503
2504 out_unref_obj:
2505         drm_gem_object_unreference(&obj->base);
2506         mutex_unlock(&dev->struct_mutex);
2507         return false;
2508 }
2509
2510 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2511 static void
2512 update_state_fb(struct drm_plane *plane)
2513 {
2514         if (plane->fb == plane->state->fb)
2515                 return;
2516
2517         if (plane->state->fb)
2518                 drm_framebuffer_unreference(plane->state->fb);
2519         plane->state->fb = plane->fb;
2520         if (plane->state->fb)
2521                 drm_framebuffer_reference(plane->state->fb);
2522 }
2523
2524 static void
2525 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2526                              struct intel_initial_plane_config *plane_config)
2527 {
2528         struct drm_device *dev = intel_crtc->base.dev;
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         struct drm_crtc *c;
2531         struct intel_crtc *i;
2532         struct drm_i915_gem_object *obj;
2533         struct drm_plane *primary = intel_crtc->base.primary;
2534         struct drm_plane_state *plane_state = primary->state;
2535         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2536         struct intel_plane *intel_plane = to_intel_plane(primary);
2537         struct intel_plane_state *intel_state =
2538                 to_intel_plane_state(plane_state);
2539         struct drm_framebuffer *fb;
2540
2541         if (!plane_config->fb)
2542                 return;
2543
2544         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2545                 fb = &plane_config->fb->base;
2546                 goto valid_fb;
2547         }
2548
2549         kfree(plane_config->fb);
2550
2551         /*
2552          * Failed to alloc the obj, check to see if we should share
2553          * an fb with another CRTC instead
2554          */
2555         for_each_crtc(dev, c) {
2556                 i = to_intel_crtc(c);
2557
2558                 if (c == &intel_crtc->base)
2559                         continue;
2560
2561                 if (!i->active)
2562                         continue;
2563
2564                 fb = c->primary->fb;
2565                 if (!fb)
2566                         continue;
2567
2568                 obj = intel_fb_obj(fb);
2569                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2570                         drm_framebuffer_reference(fb);
2571                         goto valid_fb;
2572                 }
2573         }
2574
2575         /*
2576          * We've failed to reconstruct the BIOS FB.  Current display state
2577          * indicates that the primary plane is visible, but has a NULL FB,
2578          * which will lead to problems later if we don't fix it up.  The
2579          * simplest solution is to just disable the primary plane now and
2580          * pretend the BIOS never had it enabled.
2581          */
2582         to_intel_plane_state(plane_state)->visible = false;
2583         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2584         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2585         intel_plane->disable_plane(primary, &intel_crtc->base);
2586
2587         return;
2588
2589 valid_fb:
2590         plane_state->src_x = 0;
2591         plane_state->src_y = 0;
2592         plane_state->src_w = fb->width << 16;
2593         plane_state->src_h = fb->height << 16;
2594
2595         plane_state->crtc_x = 0;
2596         plane_state->crtc_y = 0;
2597         plane_state->crtc_w = fb->width;
2598         plane_state->crtc_h = fb->height;
2599
2600         intel_state->src.x1 = plane_state->src_x;
2601         intel_state->src.y1 = plane_state->src_y;
2602         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2603         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2604         intel_state->dst.x1 = plane_state->crtc_x;
2605         intel_state->dst.y1 = plane_state->crtc_y;
2606         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2607         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2608
2609         obj = intel_fb_obj(fb);
2610         if (obj->tiling_mode != I915_TILING_NONE)
2611                 dev_priv->preserve_bios_swizzle = true;
2612
2613         drm_framebuffer_reference(fb);
2614         primary->fb = primary->state->fb = fb;
2615         primary->crtc = primary->state->crtc = &intel_crtc->base;
2616         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2617         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2618 }
2619
2620 static void i9xx_update_primary_plane(struct drm_plane *primary,
2621                                       const struct intel_crtc_state *crtc_state,
2622                                       const struct intel_plane_state *plane_state)
2623 {
2624         struct drm_device *dev = primary->dev;
2625         struct drm_i915_private *dev_priv = dev->dev_private;
2626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2627         struct drm_framebuffer *fb = plane_state->base.fb;
2628         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2629         int plane = intel_crtc->plane;
2630         u32 linear_offset;
2631         u32 dspcntr;
2632         i915_reg_t reg = DSPCNTR(plane);
2633         unsigned int rotation = plane_state->base.rotation;
2634         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2635         int x = plane_state->src.x1 >> 16;
2636         int y = plane_state->src.y1 >> 16;
2637
2638         dspcntr = DISPPLANE_GAMMA_ENABLE;
2639
2640         dspcntr |= DISPLAY_PLANE_ENABLE;
2641
2642         if (INTEL_INFO(dev)->gen < 4) {
2643                 if (intel_crtc->pipe == PIPE_B)
2644                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2645
2646                 /* pipesrc and dspsize control the size that is scaled from,
2647                  * which should always be the user's requested size.
2648                  */
2649                 I915_WRITE(DSPSIZE(plane),
2650                            ((crtc_state->pipe_src_h - 1) << 16) |
2651                            (crtc_state->pipe_src_w - 1));
2652                 I915_WRITE(DSPPOS(plane), 0);
2653         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2654                 I915_WRITE(PRIMSIZE(plane),
2655                            ((crtc_state->pipe_src_h - 1) << 16) |
2656                            (crtc_state->pipe_src_w - 1));
2657                 I915_WRITE(PRIMPOS(plane), 0);
2658                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2659         }
2660
2661         switch (fb->pixel_format) {
2662         case DRM_FORMAT_C8:
2663                 dspcntr |= DISPPLANE_8BPP;
2664                 break;
2665         case DRM_FORMAT_XRGB1555:
2666                 dspcntr |= DISPPLANE_BGRX555;
2667                 break;
2668         case DRM_FORMAT_RGB565:
2669                 dspcntr |= DISPPLANE_BGRX565;
2670                 break;
2671         case DRM_FORMAT_XRGB8888:
2672                 dspcntr |= DISPPLANE_BGRX888;
2673                 break;
2674         case DRM_FORMAT_XBGR8888:
2675                 dspcntr |= DISPPLANE_RGBX888;
2676                 break;
2677         case DRM_FORMAT_XRGB2101010:
2678                 dspcntr |= DISPPLANE_BGRX101010;
2679                 break;
2680         case DRM_FORMAT_XBGR2101010:
2681                 dspcntr |= DISPPLANE_RGBX101010;
2682                 break;
2683         default:
2684                 BUG();
2685         }
2686
2687         if (INTEL_INFO(dev)->gen >= 4 &&
2688             obj->tiling_mode != I915_TILING_NONE)
2689                 dspcntr |= DISPPLANE_TILED;
2690
2691         if (IS_G4X(dev))
2692                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2693
2694         linear_offset = y * fb->pitches[0] + x * cpp;
2695
2696         if (INTEL_INFO(dev)->gen >= 4) {
2697                 intel_crtc->dspaddr_offset =
2698                         intel_compute_tile_offset(&x, &y, fb, 0,
2699                                                   fb->pitches[0], rotation);
2700                 linear_offset -= intel_crtc->dspaddr_offset;
2701         } else {
2702                 intel_crtc->dspaddr_offset = linear_offset;
2703         }
2704
2705         if (rotation == BIT(DRM_ROTATE_180)) {
2706                 dspcntr |= DISPPLANE_ROTATE_180;
2707
2708                 x += (crtc_state->pipe_src_w - 1);
2709                 y += (crtc_state->pipe_src_h - 1);
2710
2711                 /* Finding the last pixel of the last line of the display
2712                 data and adding to linear_offset*/
2713                 linear_offset +=
2714                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2715                         (crtc_state->pipe_src_w - 1) * cpp;
2716         }
2717
2718         intel_crtc->adjusted_x = x;
2719         intel_crtc->adjusted_y = y;
2720
2721         I915_WRITE(reg, dspcntr);
2722
2723         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2724         if (INTEL_INFO(dev)->gen >= 4) {
2725                 I915_WRITE(DSPSURF(plane),
2726                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2727                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2728                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2729         } else
2730                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2731         POSTING_READ(reg);
2732 }
2733
2734 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2735                                        struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int plane = intel_crtc->plane;
2741
2742         I915_WRITE(DSPCNTR(plane), 0);
2743         if (INTEL_INFO(dev_priv)->gen >= 4)
2744                 I915_WRITE(DSPSURF(plane), 0);
2745         else
2746                 I915_WRITE(DSPADDR(plane), 0);
2747         POSTING_READ(DSPCNTR(plane));
2748 }
2749
2750 static void ironlake_update_primary_plane(struct drm_plane *primary,
2751                                           const struct intel_crtc_state *crtc_state,
2752                                           const struct intel_plane_state *plane_state)
2753 {
2754         struct drm_device *dev = primary->dev;
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2757         struct drm_framebuffer *fb = plane_state->base.fb;
2758         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2759         int plane = intel_crtc->plane;
2760         u32 linear_offset;
2761         u32 dspcntr;
2762         i915_reg_t reg = DSPCNTR(plane);
2763         unsigned int rotation = plane_state->base.rotation;
2764         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2765         int x = plane_state->src.x1 >> 16;
2766         int y = plane_state->src.y1 >> 16;
2767
2768         dspcntr = DISPPLANE_GAMMA_ENABLE;
2769         dspcntr |= DISPLAY_PLANE_ENABLE;
2770
2771         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2772                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2773
2774         switch (fb->pixel_format) {
2775         case DRM_FORMAT_C8:
2776                 dspcntr |= DISPPLANE_8BPP;
2777                 break;
2778         case DRM_FORMAT_RGB565:
2779                 dspcntr |= DISPPLANE_BGRX565;
2780                 break;
2781         case DRM_FORMAT_XRGB8888:
2782                 dspcntr |= DISPPLANE_BGRX888;
2783                 break;
2784         case DRM_FORMAT_XBGR8888:
2785                 dspcntr |= DISPPLANE_RGBX888;
2786                 break;
2787         case DRM_FORMAT_XRGB2101010:
2788                 dspcntr |= DISPPLANE_BGRX101010;
2789                 break;
2790         case DRM_FORMAT_XBGR2101010:
2791                 dspcntr |= DISPPLANE_RGBX101010;
2792                 break;
2793         default:
2794                 BUG();
2795         }
2796
2797         if (obj->tiling_mode != I915_TILING_NONE)
2798                 dspcntr |= DISPPLANE_TILED;
2799
2800         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2801                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2802
2803         linear_offset = y * fb->pitches[0] + x * cpp;
2804         intel_crtc->dspaddr_offset =
2805                 intel_compute_tile_offset(&x, &y, fb, 0,
2806                                           fb->pitches[0], rotation);
2807         linear_offset -= intel_crtc->dspaddr_offset;
2808         if (rotation == BIT(DRM_ROTATE_180)) {
2809                 dspcntr |= DISPPLANE_ROTATE_180;
2810
2811                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2812                         x += (crtc_state->pipe_src_w - 1);
2813                         y += (crtc_state->pipe_src_h - 1);
2814
2815                         /* Finding the last pixel of the last line of the display
2816                         data and adding to linear_offset*/
2817                         linear_offset +=
2818                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2819                                 (crtc_state->pipe_src_w - 1) * cpp;
2820                 }
2821         }
2822
2823         intel_crtc->adjusted_x = x;
2824         intel_crtc->adjusted_y = y;
2825
2826         I915_WRITE(reg, dspcntr);
2827
2828         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2829         I915_WRITE(DSPSURF(plane),
2830                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2831         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2832                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2833         } else {
2834                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2835                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2836         }
2837         POSTING_READ(reg);
2838 }
2839
2840 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2841                               uint64_t fb_modifier, uint32_t pixel_format)
2842 {
2843         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2844                 return 64;
2845         } else {
2846                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2847
2848                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2849         }
2850 }
2851
2852 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2853                            struct drm_i915_gem_object *obj,
2854                            unsigned int plane)
2855 {
2856         struct i915_ggtt_view view;
2857         struct i915_vma *vma;
2858         u64 offset;
2859
2860         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2861                                 intel_plane->base.state->rotation);
2862
2863         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2864         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2865                 view.type))
2866                 return -1;
2867
2868         offset = vma->node.start;
2869
2870         if (plane == 1) {
2871                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2872                           PAGE_SIZE;
2873         }
2874
2875         WARN_ON(upper_32_bits(offset));
2876
2877         return lower_32_bits(offset);
2878 }
2879
2880 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2881 {
2882         struct drm_device *dev = intel_crtc->base.dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884
2885         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2886         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2887         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2888 }
2889
2890 /*
2891  * This function detaches (aka. unbinds) unused scalers in hardware
2892  */
2893 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2894 {
2895         struct intel_crtc_scaler_state *scaler_state;
2896         int i;
2897
2898         scaler_state = &intel_crtc->config->scaler_state;
2899
2900         /* loop through and disable scalers that aren't in use */
2901         for (i = 0; i < intel_crtc->num_scalers; i++) {
2902                 if (!scaler_state->scalers[i].in_use)
2903                         skl_detach_scaler(intel_crtc, i);
2904         }
2905 }
2906
2907 u32 skl_plane_ctl_format(uint32_t pixel_format)
2908 {
2909         switch (pixel_format) {
2910         case DRM_FORMAT_C8:
2911                 return PLANE_CTL_FORMAT_INDEXED;
2912         case DRM_FORMAT_RGB565:
2913                 return PLANE_CTL_FORMAT_RGB_565;
2914         case DRM_FORMAT_XBGR8888:
2915                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2916         case DRM_FORMAT_XRGB8888:
2917                 return PLANE_CTL_FORMAT_XRGB_8888;
2918         /*
2919          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2920          * to be already pre-multiplied. We need to add a knob (or a different
2921          * DRM_FORMAT) for user-space to configure that.
2922          */
2923         case DRM_FORMAT_ABGR8888:
2924                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2925                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2926         case DRM_FORMAT_ARGB8888:
2927                 return PLANE_CTL_FORMAT_XRGB_8888 |
2928                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2929         case DRM_FORMAT_XRGB2101010:
2930                 return PLANE_CTL_FORMAT_XRGB_2101010;
2931         case DRM_FORMAT_XBGR2101010:
2932                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2933         case DRM_FORMAT_YUYV:
2934                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2935         case DRM_FORMAT_YVYU:
2936                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2937         case DRM_FORMAT_UYVY:
2938                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2939         case DRM_FORMAT_VYUY:
2940                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2941         default:
2942                 MISSING_CASE(pixel_format);
2943         }
2944
2945         return 0;
2946 }
2947
2948 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2949 {
2950         switch (fb_modifier) {
2951         case DRM_FORMAT_MOD_NONE:
2952                 break;
2953         case I915_FORMAT_MOD_X_TILED:
2954                 return PLANE_CTL_TILED_X;
2955         case I915_FORMAT_MOD_Y_TILED:
2956                 return PLANE_CTL_TILED_Y;
2957         case I915_FORMAT_MOD_Yf_TILED:
2958                 return PLANE_CTL_TILED_YF;
2959         default:
2960                 MISSING_CASE(fb_modifier);
2961         }
2962
2963         return 0;
2964 }
2965
2966 u32 skl_plane_ctl_rotation(unsigned int rotation)
2967 {
2968         switch (rotation) {
2969         case BIT(DRM_ROTATE_0):
2970                 break;
2971         /*
2972          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2973          * while i915 HW rotation is clockwise, thats why this swapping.
2974          */
2975         case BIT(DRM_ROTATE_90):
2976                 return PLANE_CTL_ROTATE_270;
2977         case BIT(DRM_ROTATE_180):
2978                 return PLANE_CTL_ROTATE_180;
2979         case BIT(DRM_ROTATE_270):
2980                 return PLANE_CTL_ROTATE_90;
2981         default:
2982                 MISSING_CASE(rotation);
2983         }
2984
2985         return 0;
2986 }
2987
2988 static void skylake_update_primary_plane(struct drm_plane *plane,
2989                                          const struct intel_crtc_state *crtc_state,
2990                                          const struct intel_plane_state *plane_state)
2991 {
2992         struct drm_device *dev = plane->dev;
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2995         struct drm_framebuffer *fb = plane_state->base.fb;
2996         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2997         int pipe = intel_crtc->pipe;
2998         u32 plane_ctl, stride_div, stride;
2999         u32 tile_height, plane_offset, plane_size;
3000         unsigned int rotation = plane_state->base.rotation;
3001         int x_offset, y_offset;
3002         u32 surf_addr;
3003         int scaler_id = plane_state->scaler_id;
3004         int src_x = plane_state->src.x1 >> 16;
3005         int src_y = plane_state->src.y1 >> 16;
3006         int src_w = drm_rect_width(&plane_state->src) >> 16;
3007         int src_h = drm_rect_height(&plane_state->src) >> 16;
3008         int dst_x = plane_state->dst.x1;
3009         int dst_y = plane_state->dst.y1;
3010         int dst_w = drm_rect_width(&plane_state->dst);
3011         int dst_h = drm_rect_height(&plane_state->dst);
3012
3013         plane_ctl = PLANE_CTL_ENABLE |
3014                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3015                     PLANE_CTL_PIPE_CSC_ENABLE;
3016
3017         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3018         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3019         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3020         plane_ctl |= skl_plane_ctl_rotation(rotation);
3021
3022         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3023                                                fb->pixel_format);
3024         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3025
3026         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3027
3028         if (intel_rotation_90_or_270(rotation)) {
3029                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3030
3031                 /* stride = Surface height in tiles */
3032                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3033                 stride = DIV_ROUND_UP(fb->height, tile_height);
3034                 x_offset = stride * tile_height - src_y - src_h;
3035                 y_offset = src_x;
3036                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3037         } else {
3038                 stride = fb->pitches[0] / stride_div;
3039                 x_offset = src_x;
3040                 y_offset = src_y;
3041                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3042         }
3043         plane_offset = y_offset << 16 | x_offset;
3044
3045         intel_crtc->adjusted_x = x_offset;
3046         intel_crtc->adjusted_y = y_offset;
3047
3048         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3049         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3050         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3051         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3052
3053         if (scaler_id >= 0) {
3054                 uint32_t ps_ctrl = 0;
3055
3056                 WARN_ON(!dst_w || !dst_h);
3057                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3058                         crtc_state->scaler_state.scalers[scaler_id].mode;
3059                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3060                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3061                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3062                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3063                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3064         } else {
3065                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3066         }
3067
3068         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3069
3070         POSTING_READ(PLANE_SURF(pipe, 0));
3071 }
3072
3073 static void skylake_disable_primary_plane(struct drm_plane *primary,
3074                                           struct drm_crtc *crtc)
3075 {
3076         struct drm_device *dev = crtc->dev;
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         int pipe = to_intel_crtc(crtc)->pipe;
3079
3080         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082         POSTING_READ(PLANE_SURF(pipe, 0));
3083 }
3084
3085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3086 static int
3087 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3088                            int x, int y, enum mode_set_atomic state)
3089 {
3090         /* Support for kgdboc is disabled, this needs a major rework. */
3091         DRM_ERROR("legacy panic handler not supported any more.\n");
3092
3093         return -ENODEV;
3094 }
3095
3096 static void intel_complete_page_flips(struct drm_device *dev)
3097 {
3098         struct drm_crtc *crtc;
3099
3100         for_each_crtc(dev, crtc) {
3101                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102                 enum plane plane = intel_crtc->plane;
3103
3104                 intel_prepare_page_flip(dev, plane);
3105                 intel_finish_page_flip_plane(dev, plane);
3106         }
3107 }
3108
3109 static void intel_update_primary_planes(struct drm_device *dev)
3110 {
3111         struct drm_crtc *crtc;
3112
3113         for_each_crtc(dev, crtc) {
3114                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3115                 struct intel_plane_state *plane_state;
3116
3117                 drm_modeset_lock_crtc(crtc, &plane->base);
3118                 plane_state = to_intel_plane_state(plane->base.state);
3119
3120                 if (plane_state->visible)
3121                         plane->update_plane(&plane->base,
3122                                             to_intel_crtc_state(crtc->state),
3123                                             plane_state);
3124
3125                 drm_modeset_unlock_crtc(crtc);
3126         }
3127 }
3128
3129 void intel_prepare_reset(struct drm_device *dev)
3130 {
3131         /* no reset support for gen2 */
3132         if (IS_GEN2(dev))
3133                 return;
3134
3135         /* reset doesn't touch the display */
3136         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3137                 return;
3138
3139         drm_modeset_lock_all(dev);
3140         /*
3141          * Disabling the crtcs gracefully seems nicer. Also the
3142          * g33 docs say we should at least disable all the planes.
3143          */
3144         intel_display_suspend(dev);
3145 }
3146
3147 void intel_finish_reset(struct drm_device *dev)
3148 {
3149         struct drm_i915_private *dev_priv = to_i915(dev);
3150
3151         /*
3152          * Flips in the rings will be nuked by the reset,
3153          * so complete all pending flips so that user space
3154          * will get its events and not get stuck.
3155          */
3156         intel_complete_page_flips(dev);
3157
3158         /* no reset support for gen2 */
3159         if (IS_GEN2(dev))
3160                 return;
3161
3162         /* reset doesn't touch the display */
3163         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3164                 /*
3165                  * Flips in the rings have been nuked by the reset,
3166                  * so update the base address of all primary
3167                  * planes to the the last fb to make sure we're
3168                  * showing the correct fb after a reset.
3169                  *
3170                  * FIXME: Atomic will make this obsolete since we won't schedule
3171                  * CS-based flips (which might get lost in gpu resets) any more.
3172                  */
3173                 intel_update_primary_planes(dev);
3174                 return;
3175         }
3176
3177         /*
3178          * The display has been reset as well,
3179          * so need a full re-initialization.
3180          */
3181         intel_runtime_pm_disable_interrupts(dev_priv);
3182         intel_runtime_pm_enable_interrupts(dev_priv);
3183
3184         intel_modeset_init_hw(dev);
3185
3186         spin_lock_irq(&dev_priv->irq_lock);
3187         if (dev_priv->display.hpd_irq_setup)
3188                 dev_priv->display.hpd_irq_setup(dev);
3189         spin_unlock_irq(&dev_priv->irq_lock);
3190
3191         intel_display_resume(dev);
3192
3193         intel_hpd_init(dev_priv);
3194
3195         drm_modeset_unlock_all(dev);
3196 }
3197
3198 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3199 {
3200         struct drm_device *dev = crtc->dev;
3201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3202         unsigned reset_counter;
3203         bool pending;
3204
3205         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3206         if (intel_crtc->reset_counter != reset_counter)
3207                 return false;
3208
3209         spin_lock_irq(&dev->event_lock);
3210         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3211         spin_unlock_irq(&dev->event_lock);
3212
3213         return pending;
3214 }
3215
3216 static void intel_update_pipe_config(struct intel_crtc *crtc,
3217                                      struct intel_crtc_state *old_crtc_state)
3218 {
3219         struct drm_device *dev = crtc->base.dev;
3220         struct drm_i915_private *dev_priv = dev->dev_private;
3221         struct intel_crtc_state *pipe_config =
3222                 to_intel_crtc_state(crtc->base.state);
3223
3224         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3225         crtc->base.mode = crtc->base.state->mode;
3226
3227         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3228                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3229                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3230
3231         /*
3232          * Update pipe size and adjust fitter if needed: the reason for this is
3233          * that in compute_mode_changes we check the native mode (not the pfit
3234          * mode) to see if we can flip rather than do a full mode set. In the
3235          * fastboot case, we'll flip, but if we don't update the pipesrc and
3236          * pfit state, we'll end up with a big fb scanned out into the wrong
3237          * sized surface.
3238          */
3239
3240         I915_WRITE(PIPESRC(crtc->pipe),
3241                    ((pipe_config->pipe_src_w - 1) << 16) |
3242                    (pipe_config->pipe_src_h - 1));
3243
3244         /* on skylake this is done by detaching scalers */
3245         if (INTEL_INFO(dev)->gen >= 9) {
3246                 skl_detach_scalers(crtc);
3247
3248                 if (pipe_config->pch_pfit.enabled)
3249                         skylake_pfit_enable(crtc);
3250         } else if (HAS_PCH_SPLIT(dev)) {
3251                 if (pipe_config->pch_pfit.enabled)
3252                         ironlake_pfit_enable(crtc);
3253                 else if (old_crtc_state->pch_pfit.enabled)
3254                         ironlake_pfit_disable(crtc, true);
3255         }
3256 }
3257
3258 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3259 {
3260         struct drm_device *dev = crtc->dev;
3261         struct drm_i915_private *dev_priv = dev->dev_private;
3262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263         int pipe = intel_crtc->pipe;
3264         i915_reg_t reg;
3265         u32 temp;
3266
3267         /* enable normal train */
3268         reg = FDI_TX_CTL(pipe);
3269         temp = I915_READ(reg);
3270         if (IS_IVYBRIDGE(dev)) {
3271                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3272                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3273         } else {
3274                 temp &= ~FDI_LINK_TRAIN_NONE;
3275                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3276         }
3277         I915_WRITE(reg, temp);
3278
3279         reg = FDI_RX_CTL(pipe);
3280         temp = I915_READ(reg);
3281         if (HAS_PCH_CPT(dev)) {
3282                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3283                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3284         } else {
3285                 temp &= ~FDI_LINK_TRAIN_NONE;
3286                 temp |= FDI_LINK_TRAIN_NONE;
3287         }
3288         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3289
3290         /* wait one idle pattern time */
3291         POSTING_READ(reg);
3292         udelay(1000);
3293
3294         /* IVB wants error correction enabled */
3295         if (IS_IVYBRIDGE(dev))
3296                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3297                            FDI_FE_ERRC_ENABLE);
3298 }
3299
3300 /* The FDI link training functions for ILK/Ibexpeak. */
3301 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         int pipe = intel_crtc->pipe;
3307         i915_reg_t reg;
3308         u32 temp, tries;
3309
3310         /* FDI needs bits from pipe first */
3311         assert_pipe_enabled(dev_priv, pipe);
3312
3313         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3314            for train result */
3315         reg = FDI_RX_IMR(pipe);
3316         temp = I915_READ(reg);
3317         temp &= ~FDI_RX_SYMBOL_LOCK;
3318         temp &= ~FDI_RX_BIT_LOCK;
3319         I915_WRITE(reg, temp);
3320         I915_READ(reg);
3321         udelay(150);
3322
3323         /* enable CPU FDI TX and PCH FDI RX */
3324         reg = FDI_TX_CTL(pipe);
3325         temp = I915_READ(reg);
3326         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3327         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3328         temp &= ~FDI_LINK_TRAIN_NONE;
3329         temp |= FDI_LINK_TRAIN_PATTERN_1;
3330         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3331
3332         reg = FDI_RX_CTL(pipe);
3333         temp = I915_READ(reg);
3334         temp &= ~FDI_LINK_TRAIN_NONE;
3335         temp |= FDI_LINK_TRAIN_PATTERN_1;
3336         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3337
3338         POSTING_READ(reg);
3339         udelay(150);
3340
3341         /* Ironlake workaround, enable clock pointer after FDI enable*/
3342         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3343         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3344                    FDI_RX_PHASE_SYNC_POINTER_EN);
3345
3346         reg = FDI_RX_IIR(pipe);
3347         for (tries = 0; tries < 5; tries++) {
3348                 temp = I915_READ(reg);
3349                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350
3351                 if ((temp & FDI_RX_BIT_LOCK)) {
3352                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3353                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3354                         break;
3355                 }
3356         }
3357         if (tries == 5)
3358                 DRM_ERROR("FDI train 1 fail!\n");
3359
3360         /* Train 2 */
3361         reg = FDI_TX_CTL(pipe);
3362         temp = I915_READ(reg);
3363         temp &= ~FDI_LINK_TRAIN_NONE;
3364         temp |= FDI_LINK_TRAIN_PATTERN_2;
3365         I915_WRITE(reg, temp);
3366
3367         reg = FDI_RX_CTL(pipe);
3368         temp = I915_READ(reg);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_2;
3371         I915_WRITE(reg, temp);
3372
3373         POSTING_READ(reg);
3374         udelay(150);
3375
3376         reg = FDI_RX_IIR(pipe);
3377         for (tries = 0; tries < 5; tries++) {
3378                 temp = I915_READ(reg);
3379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3380
3381                 if (temp & FDI_RX_SYMBOL_LOCK) {
3382                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3383                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3384                         break;
3385                 }
3386         }
3387         if (tries == 5)
3388                 DRM_ERROR("FDI train 2 fail!\n");
3389
3390         DRM_DEBUG_KMS("FDI train done\n");
3391
3392 }
3393
3394 static const int snb_b_fdi_train_param[] = {
3395         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3396         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3397         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3398         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3399 };
3400
3401 /* The FDI link training functions for SNB/Cougarpoint. */
3402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404         struct drm_device *dev = crtc->dev;
3405         struct drm_i915_private *dev_priv = dev->dev_private;
3406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407         int pipe = intel_crtc->pipe;
3408         i915_reg_t reg;
3409         u32 temp, i, retry;
3410
3411         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3412            for train result */
3413         reg = FDI_RX_IMR(pipe);
3414         temp = I915_READ(reg);
3415         temp &= ~FDI_RX_SYMBOL_LOCK;
3416         temp &= ~FDI_RX_BIT_LOCK;
3417         I915_WRITE(reg, temp);
3418
3419         POSTING_READ(reg);
3420         udelay(150);
3421
3422         /* enable CPU FDI TX and PCH FDI RX */
3423         reg = FDI_TX_CTL(pipe);
3424         temp = I915_READ(reg);
3425         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3426         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3427         temp &= ~FDI_LINK_TRAIN_NONE;
3428         temp |= FDI_LINK_TRAIN_PATTERN_1;
3429         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3430         /* SNB-B */
3431         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3432         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3433
3434         I915_WRITE(FDI_RX_MISC(pipe),
3435                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3436
3437         reg = FDI_RX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         if (HAS_PCH_CPT(dev)) {
3440                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3441                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3442         } else {
3443                 temp &= ~FDI_LINK_TRAIN_NONE;
3444                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3445         }
3446         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3447
3448         POSTING_READ(reg);
3449         udelay(150);
3450
3451         for (i = 0; i < 4; i++) {
3452                 reg = FDI_TX_CTL(pipe);
3453                 temp = I915_READ(reg);
3454                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3455                 temp |= snb_b_fdi_train_param[i];
3456                 I915_WRITE(reg, temp);
3457
3458                 POSTING_READ(reg);
3459                 udelay(500);
3460
3461                 for (retry = 0; retry < 5; retry++) {
3462                         reg = FDI_RX_IIR(pipe);
3463                         temp = I915_READ(reg);
3464                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465                         if (temp & FDI_RX_BIT_LOCK) {
3466                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3467                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3468                                 break;
3469                         }
3470                         udelay(50);
3471                 }
3472                 if (retry < 5)
3473                         break;
3474         }
3475         if (i == 4)
3476                 DRM_ERROR("FDI train 1 fail!\n");
3477
3478         /* Train 2 */
3479         reg = FDI_TX_CTL(pipe);
3480         temp = I915_READ(reg);
3481         temp &= ~FDI_LINK_TRAIN_NONE;
3482         temp |= FDI_LINK_TRAIN_PATTERN_2;
3483         if (IS_GEN6(dev)) {
3484                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3485                 /* SNB-B */
3486                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3487         }
3488         I915_WRITE(reg, temp);
3489
3490         reg = FDI_RX_CTL(pipe);
3491         temp = I915_READ(reg);
3492         if (HAS_PCH_CPT(dev)) {
3493                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3495         } else {
3496                 temp &= ~FDI_LINK_TRAIN_NONE;
3497                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3498         }
3499         I915_WRITE(reg, temp);
3500
3501         POSTING_READ(reg);
3502         udelay(150);
3503
3504         for (i = 0; i < 4; i++) {
3505                 reg = FDI_TX_CTL(pipe);
3506                 temp = I915_READ(reg);
3507                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508                 temp |= snb_b_fdi_train_param[i];
3509                 I915_WRITE(reg, temp);
3510
3511                 POSTING_READ(reg);
3512                 udelay(500);
3513
3514                 for (retry = 0; retry < 5; retry++) {
3515                         reg = FDI_RX_IIR(pipe);
3516                         temp = I915_READ(reg);
3517                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518                         if (temp & FDI_RX_SYMBOL_LOCK) {
3519                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3521                                 break;
3522                         }
3523                         udelay(50);
3524                 }
3525                 if (retry < 5)
3526                         break;
3527         }
3528         if (i == 4)
3529                 DRM_ERROR("FDI train 2 fail!\n");
3530
3531         DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 /* Manual link training for Ivy Bridge A0 parts */
3535 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3536 {
3537         struct drm_device *dev = crtc->dev;
3538         struct drm_i915_private *dev_priv = dev->dev_private;
3539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540         int pipe = intel_crtc->pipe;
3541         i915_reg_t reg;
3542         u32 temp, i, j;
3543
3544         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3545            for train result */
3546         reg = FDI_RX_IMR(pipe);
3547         temp = I915_READ(reg);
3548         temp &= ~FDI_RX_SYMBOL_LOCK;
3549         temp &= ~FDI_RX_BIT_LOCK;
3550         I915_WRITE(reg, temp);
3551
3552         POSTING_READ(reg);
3553         udelay(150);
3554
3555         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556                       I915_READ(FDI_RX_IIR(pipe)));
3557
3558         /* Try each vswing and preemphasis setting twice before moving on */
3559         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3560                 /* disable first in case we need to retry */
3561                 reg = FDI_TX_CTL(pipe);
3562                 temp = I915_READ(reg);
3563                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3564                 temp &= ~FDI_TX_ENABLE;
3565                 I915_WRITE(reg, temp);
3566
3567                 reg = FDI_RX_CTL(pipe);
3568                 temp = I915_READ(reg);
3569                 temp &= ~FDI_LINK_TRAIN_AUTO;
3570                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571                 temp &= ~FDI_RX_ENABLE;
3572                 I915_WRITE(reg, temp);
3573
3574                 /* enable CPU FDI TX and PCH FDI RX */
3575                 reg = FDI_TX_CTL(pipe);
3576                 temp = I915_READ(reg);
3577                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3578                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3579                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3580                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3581                 temp |= snb_b_fdi_train_param[j/2];
3582                 temp |= FDI_COMPOSITE_SYNC;
3583                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3584
3585                 I915_WRITE(FDI_RX_MISC(pipe),
3586                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3587
3588                 reg = FDI_RX_CTL(pipe);
3589                 temp = I915_READ(reg);
3590                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3591                 temp |= FDI_COMPOSITE_SYNC;
3592                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3593
3594                 POSTING_READ(reg);
3595                 udelay(1); /* should be 0.5us */
3596
3597                 for (i = 0; i < 4; i++) {
3598                         reg = FDI_RX_IIR(pipe);
3599                         temp = I915_READ(reg);
3600                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3601
3602                         if (temp & FDI_RX_BIT_LOCK ||
3603                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3604                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3606                                               i);
3607                                 break;
3608                         }
3609                         udelay(1); /* should be 0.5us */
3610                 }
3611                 if (i == 4) {
3612                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3613                         continue;
3614                 }
3615
3616                 /* Train 2 */
3617                 reg = FDI_TX_CTL(pipe);
3618                 temp = I915_READ(reg);
3619                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3620                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3621                 I915_WRITE(reg, temp);
3622
3623                 reg = FDI_RX_CTL(pipe);
3624                 temp = I915_READ(reg);
3625                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3626                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3627                 I915_WRITE(reg, temp);
3628
3629                 POSTING_READ(reg);
3630                 udelay(2); /* should be 1.5us */
3631
3632                 for (i = 0; i < 4; i++) {
3633                         reg = FDI_RX_IIR(pipe);
3634                         temp = I915_READ(reg);
3635                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3636
3637                         if (temp & FDI_RX_SYMBOL_LOCK ||
3638                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3639                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3641                                               i);
3642                                 goto train_done;
3643                         }
3644                         udelay(2); /* should be 1.5us */
3645                 }
3646                 if (i == 4)
3647                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3648         }
3649
3650 train_done:
3651         DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3655 {
3656         struct drm_device *dev = intel_crtc->base.dev;
3657         struct drm_i915_private *dev_priv = dev->dev_private;
3658         int pipe = intel_crtc->pipe;
3659         i915_reg_t reg;
3660         u32 temp;
3661
3662         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663         reg = FDI_RX_CTL(pipe);
3664         temp = I915_READ(reg);
3665         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3666         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3668         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3669
3670         POSTING_READ(reg);
3671         udelay(200);
3672
3673         /* Switch from Rawclk to PCDclk */
3674         temp = I915_READ(reg);
3675         I915_WRITE(reg, temp | FDI_PCDCLK);
3676
3677         POSTING_READ(reg);
3678         udelay(200);
3679
3680         /* Enable CPU FDI TX PLL, always on for Ironlake */
3681         reg = FDI_TX_CTL(pipe);
3682         temp = I915_READ(reg);
3683         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3684                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3685
3686                 POSTING_READ(reg);
3687                 udelay(100);
3688         }
3689 }
3690
3691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3692 {
3693         struct drm_device *dev = intel_crtc->base.dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         int pipe = intel_crtc->pipe;
3696         i915_reg_t reg;
3697         u32 temp;
3698
3699         /* Switch from PCDclk to Rawclk */
3700         reg = FDI_RX_CTL(pipe);
3701         temp = I915_READ(reg);
3702         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3703
3704         /* Disable CPU FDI TX PLL */
3705         reg = FDI_TX_CTL(pipe);
3706         temp = I915_READ(reg);
3707         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3708
3709         POSTING_READ(reg);
3710         udelay(100);
3711
3712         reg = FDI_RX_CTL(pipe);
3713         temp = I915_READ(reg);
3714         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3715
3716         /* Wait for the clocks to turn off. */
3717         POSTING_READ(reg);
3718         udelay(100);
3719 }
3720
3721 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3722 {
3723         struct drm_device *dev = crtc->dev;
3724         struct drm_i915_private *dev_priv = dev->dev_private;
3725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726         int pipe = intel_crtc->pipe;
3727         i915_reg_t reg;
3728         u32 temp;
3729
3730         /* disable CPU FDI tx and PCH FDI rx */
3731         reg = FDI_TX_CTL(pipe);
3732         temp = I915_READ(reg);
3733         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3734         POSTING_READ(reg);
3735
3736         reg = FDI_RX_CTL(pipe);
3737         temp = I915_READ(reg);
3738         temp &= ~(0x7 << 16);
3739         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3740         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3741
3742         POSTING_READ(reg);
3743         udelay(100);
3744
3745         /* Ironlake workaround, disable clock pointer after downing FDI */
3746         if (HAS_PCH_IBX(dev))
3747                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3748
3749         /* still set train pattern 1 */
3750         reg = FDI_TX_CTL(pipe);
3751         temp = I915_READ(reg);
3752         temp &= ~FDI_LINK_TRAIN_NONE;
3753         temp |= FDI_LINK_TRAIN_PATTERN_1;
3754         I915_WRITE(reg, temp);
3755
3756         reg = FDI_RX_CTL(pipe);
3757         temp = I915_READ(reg);
3758         if (HAS_PCH_CPT(dev)) {
3759                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3760                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3761         } else {
3762                 temp &= ~FDI_LINK_TRAIN_NONE;
3763                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3764         }
3765         /* BPC in FDI rx is consistent with that in PIPECONF */
3766         temp &= ~(0x07 << 16);
3767         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3768         I915_WRITE(reg, temp);
3769
3770         POSTING_READ(reg);
3771         udelay(100);
3772 }
3773
3774 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3775 {
3776         struct intel_crtc *crtc;
3777
3778         /* Note that we don't need to be called with mode_config.lock here
3779          * as our list of CRTC objects is static for the lifetime of the
3780          * device and so cannot disappear as we iterate. Similarly, we can
3781          * happily treat the predicates as racy, atomic checks as userspace
3782          * cannot claim and pin a new fb without at least acquring the
3783          * struct_mutex and so serialising with us.
3784          */
3785         for_each_intel_crtc(dev, crtc) {
3786                 if (atomic_read(&crtc->unpin_work_count) == 0)
3787                         continue;
3788
3789                 if (crtc->unpin_work)
3790                         intel_wait_for_vblank(dev, crtc->pipe);
3791
3792                 return true;
3793         }
3794
3795         return false;
3796 }
3797
3798 static void page_flip_completed(struct intel_crtc *intel_crtc)
3799 {
3800         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3801         struct intel_unpin_work *work = intel_crtc->unpin_work;
3802
3803         /* ensure that the unpin work is consistent wrt ->pending. */
3804         smp_rmb();
3805         intel_crtc->unpin_work = NULL;
3806
3807         if (work->event)
3808                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3809
3810         drm_crtc_vblank_put(&intel_crtc->base);
3811
3812         wake_up_all(&dev_priv->pending_flip_queue);
3813         queue_work(dev_priv->wq, &work->work);
3814
3815         trace_i915_flip_complete(intel_crtc->plane,
3816                                  work->pending_flip_obj);
3817 }
3818
3819 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         long ret;
3824
3825         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3826
3827         ret = wait_event_interruptible_timeout(
3828                                         dev_priv->pending_flip_queue,
3829                                         !intel_crtc_has_pending_flip(crtc),
3830                                         60*HZ);
3831
3832         if (ret < 0)
3833                 return ret;
3834
3835         if (ret == 0) {
3836                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3837
3838                 spin_lock_irq(&dev->event_lock);
3839                 if (intel_crtc->unpin_work) {
3840                         WARN_ONCE(1, "Removing stuck page flip\n");
3841                         page_flip_completed(intel_crtc);
3842                 }
3843                 spin_unlock_irq(&dev->event_lock);
3844         }
3845
3846         return 0;
3847 }
3848
3849 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3850 {
3851         u32 temp;
3852
3853         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3854
3855         mutex_lock(&dev_priv->sb_lock);
3856
3857         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3858         temp |= SBI_SSCCTL_DISABLE;
3859         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3860
3861         mutex_unlock(&dev_priv->sb_lock);
3862 }
3863
3864 /* Program iCLKIP clock to the desired frequency */
3865 static void lpt_program_iclkip(struct drm_crtc *crtc)
3866 {
3867         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3868         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3869         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3870         u32 temp;
3871
3872         lpt_disable_iclkip(dev_priv);
3873
3874         /* The iCLK virtual clock root frequency is in MHz,
3875          * but the adjusted_mode->crtc_clock in in KHz. To get the
3876          * divisors, it is necessary to divide one by another, so we
3877          * convert the virtual clock precision to KHz here for higher
3878          * precision.
3879          */
3880         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3881                 u32 iclk_virtual_root_freq = 172800 * 1000;
3882                 u32 iclk_pi_range = 64;
3883                 u32 desired_divisor;
3884
3885                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3886                                                     clock << auxdiv);
3887                 divsel = (desired_divisor / iclk_pi_range) - 2;
3888                 phaseinc = desired_divisor % iclk_pi_range;
3889
3890                 /*
3891                  * Near 20MHz is a corner case which is
3892                  * out of range for the 7-bit divisor
3893                  */
3894                 if (divsel <= 0x7f)
3895                         break;
3896         }
3897
3898         /* This should not happen with any sane values */
3899         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3900                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3901         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3902                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3903
3904         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3905                         clock,
3906                         auxdiv,
3907                         divsel,
3908                         phasedir,
3909                         phaseinc);
3910
3911         mutex_lock(&dev_priv->sb_lock);
3912
3913         /* Program SSCDIVINTPHASE6 */
3914         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3915         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3916         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3917         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3918         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3919         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3920         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3921         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3922
3923         /* Program SSCAUXDIV */
3924         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3925         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3926         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3927         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3928
3929         /* Enable modulator and associated divider */
3930         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3931         temp &= ~SBI_SSCCTL_DISABLE;
3932         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3933
3934         mutex_unlock(&dev_priv->sb_lock);
3935
3936         /* Wait for initialization time */
3937         udelay(24);
3938
3939         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3940 }
3941
3942 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3943 {
3944         u32 divsel, phaseinc, auxdiv;
3945         u32 iclk_virtual_root_freq = 172800 * 1000;
3946         u32 iclk_pi_range = 64;
3947         u32 desired_divisor;
3948         u32 temp;
3949
3950         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3951                 return 0;
3952
3953         mutex_lock(&dev_priv->sb_lock);
3954
3955         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3956         if (temp & SBI_SSCCTL_DISABLE) {
3957                 mutex_unlock(&dev_priv->sb_lock);
3958                 return 0;
3959         }
3960
3961         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3962         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3963                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3964         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3965                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3966
3967         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3968         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3969                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3970
3971         mutex_unlock(&dev_priv->sb_lock);
3972
3973         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3974
3975         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3976                                  desired_divisor << auxdiv);
3977 }
3978
3979 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3980                                                 enum pipe pch_transcoder)
3981 {
3982         struct drm_device *dev = crtc->base.dev;
3983         struct drm_i915_private *dev_priv = dev->dev_private;
3984         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3985
3986         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3987                    I915_READ(HTOTAL(cpu_transcoder)));
3988         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3989                    I915_READ(HBLANK(cpu_transcoder)));
3990         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3991                    I915_READ(HSYNC(cpu_transcoder)));
3992
3993         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3994                    I915_READ(VTOTAL(cpu_transcoder)));
3995         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3996                    I915_READ(VBLANK(cpu_transcoder)));
3997         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3998                    I915_READ(VSYNC(cpu_transcoder)));
3999         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4000                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4001 }
4002
4003 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4004 {
4005         struct drm_i915_private *dev_priv = dev->dev_private;
4006         uint32_t temp;
4007
4008         temp = I915_READ(SOUTH_CHICKEN1);
4009         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4010                 return;
4011
4012         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4013         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4014
4015         temp &= ~FDI_BC_BIFURCATION_SELECT;
4016         if (enable)
4017                 temp |= FDI_BC_BIFURCATION_SELECT;
4018
4019         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4020         I915_WRITE(SOUTH_CHICKEN1, temp);
4021         POSTING_READ(SOUTH_CHICKEN1);
4022 }
4023
4024 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4025 {
4026         struct drm_device *dev = intel_crtc->base.dev;
4027
4028         switch (intel_crtc->pipe) {
4029         case PIPE_A:
4030                 break;
4031         case PIPE_B:
4032                 if (intel_crtc->config->fdi_lanes > 2)
4033                         cpt_set_fdi_bc_bifurcation(dev, false);
4034                 else
4035                         cpt_set_fdi_bc_bifurcation(dev, true);
4036
4037                 break;
4038         case PIPE_C:
4039                 cpt_set_fdi_bc_bifurcation(dev, true);
4040
4041                 break;
4042         default:
4043                 BUG();
4044         }
4045 }
4046
4047 /* Return which DP Port should be selected for Transcoder DP control */
4048 static enum port
4049 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4050 {
4051         struct drm_device *dev = crtc->dev;
4052         struct intel_encoder *encoder;
4053
4054         for_each_encoder_on_crtc(dev, crtc, encoder) {
4055                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4056                     encoder->type == INTEL_OUTPUT_EDP)
4057                         return enc_to_dig_port(&encoder->base)->port;
4058         }
4059
4060         return -1;
4061 }
4062
4063 /*
4064  * Enable PCH resources required for PCH ports:
4065  *   - PCH PLLs
4066  *   - FDI training & RX/TX
4067  *   - update transcoder timings
4068  *   - DP transcoding bits
4069  *   - transcoder
4070  */
4071 static void ironlake_pch_enable(struct drm_crtc *crtc)
4072 {
4073         struct drm_device *dev = crtc->dev;
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4076         int pipe = intel_crtc->pipe;
4077         u32 temp;
4078
4079         assert_pch_transcoder_disabled(dev_priv, pipe);
4080
4081         if (IS_IVYBRIDGE(dev))
4082                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4083
4084         /* Write the TU size bits before fdi link training, so that error
4085          * detection works. */
4086         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4087                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4088
4089         /* For PCH output, training FDI link */
4090         dev_priv->display.fdi_link_train(crtc);
4091
4092         /* We need to program the right clock selection before writing the pixel
4093          * mutliplier into the DPLL. */
4094         if (HAS_PCH_CPT(dev)) {
4095                 u32 sel;
4096
4097                 temp = I915_READ(PCH_DPLL_SEL);
4098                 temp |= TRANS_DPLL_ENABLE(pipe);
4099                 sel = TRANS_DPLLB_SEL(pipe);
4100                 if (intel_crtc->config->shared_dpll ==
4101                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4102                         temp |= sel;
4103                 else
4104                         temp &= ~sel;
4105                 I915_WRITE(PCH_DPLL_SEL, temp);
4106         }
4107
4108         /* XXX: pch pll's can be enabled any time before we enable the PCH
4109          * transcoder, and we actually should do this to not upset any PCH
4110          * transcoder that already use the clock when we share it.
4111          *
4112          * Note that enable_shared_dpll tries to do the right thing, but
4113          * get_shared_dpll unconditionally resets the pll - we need that to have
4114          * the right LVDS enable sequence. */
4115         intel_enable_shared_dpll(intel_crtc);
4116
4117         /* set transcoder timing, panel must allow it */
4118         assert_panel_unlocked(dev_priv, pipe);
4119         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4120
4121         intel_fdi_normal_train(crtc);
4122
4123         /* For PCH DP, enable TRANS_DP_CTL */
4124         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4125                 const struct drm_display_mode *adjusted_mode =
4126                         &intel_crtc->config->base.adjusted_mode;
4127                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4128                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4129                 temp = I915_READ(reg);
4130                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4131                           TRANS_DP_SYNC_MASK |
4132                           TRANS_DP_BPC_MASK);
4133                 temp |= TRANS_DP_OUTPUT_ENABLE;
4134                 temp |= bpc << 9; /* same format but at 11:9 */
4135
4136                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4137                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4138                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4139                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4140
4141                 switch (intel_trans_dp_port_sel(crtc)) {
4142                 case PORT_B:
4143                         temp |= TRANS_DP_PORT_SEL_B;
4144                         break;
4145                 case PORT_C:
4146                         temp |= TRANS_DP_PORT_SEL_C;
4147                         break;
4148                 case PORT_D:
4149                         temp |= TRANS_DP_PORT_SEL_D;
4150                         break;
4151                 default:
4152                         BUG();
4153                 }
4154
4155                 I915_WRITE(reg, temp);
4156         }
4157
4158         ironlake_enable_pch_transcoder(dev_priv, pipe);
4159 }
4160
4161 static void lpt_pch_enable(struct drm_crtc *crtc)
4162 {
4163         struct drm_device *dev = crtc->dev;
4164         struct drm_i915_private *dev_priv = dev->dev_private;
4165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4166         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4167
4168         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4169
4170         lpt_program_iclkip(crtc);
4171
4172         /* Set transcoder timing. */
4173         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4174
4175         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4176 }
4177
4178 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4179 {
4180         struct drm_i915_private *dev_priv = dev->dev_private;
4181         i915_reg_t dslreg = PIPEDSL(pipe);
4182         u32 temp;
4183
4184         temp = I915_READ(dslreg);
4185         udelay(500);
4186         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4187                 if (wait_for(I915_READ(dslreg) != temp, 5))
4188                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4189         }
4190 }
4191
4192 static int
4193 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4194                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4195                   int src_w, int src_h, int dst_w, int dst_h)
4196 {
4197         struct intel_crtc_scaler_state *scaler_state =
4198                 &crtc_state->scaler_state;
4199         struct intel_crtc *intel_crtc =
4200                 to_intel_crtc(crtc_state->base.crtc);
4201         int need_scaling;
4202
4203         need_scaling = intel_rotation_90_or_270(rotation) ?
4204                 (src_h != dst_w || src_w != dst_h):
4205                 (src_w != dst_w || src_h != dst_h);
4206
4207         /*
4208          * if plane is being disabled or scaler is no more required or force detach
4209          *  - free scaler binded to this plane/crtc
4210          *  - in order to do this, update crtc->scaler_usage
4211          *
4212          * Here scaler state in crtc_state is set free so that
4213          * scaler can be assigned to other user. Actual register
4214          * update to free the scaler is done in plane/panel-fit programming.
4215          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4216          */
4217         if (force_detach || !need_scaling) {
4218                 if (*scaler_id >= 0) {
4219                         scaler_state->scaler_users &= ~(1 << scaler_user);
4220                         scaler_state->scalers[*scaler_id].in_use = 0;
4221
4222                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4223                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4224                                 intel_crtc->pipe, scaler_user, *scaler_id,
4225                                 scaler_state->scaler_users);
4226                         *scaler_id = -1;
4227                 }
4228                 return 0;
4229         }
4230
4231         /* range checks */
4232         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4233                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4234
4235                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4236                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4237                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4238                         "size is out of scaler range\n",
4239                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4240                 return -EINVAL;
4241         }
4242
4243         /* mark this plane as a scaler user in crtc_state */
4244         scaler_state->scaler_users |= (1 << scaler_user);
4245         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4246                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4247                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4248                 scaler_state->scaler_users);
4249
4250         return 0;
4251 }
4252
4253 /**
4254  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4255  *
4256  * @state: crtc's scaler state
4257  *
4258  * Return
4259  *     0 - scaler_usage updated successfully
4260  *    error - requested scaling cannot be supported or other error condition
4261  */
4262 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4263 {
4264         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4265         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4266
4267         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4268                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4269
4270         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4271                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4272                 state->pipe_src_w, state->pipe_src_h,
4273                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4274 }
4275
4276 /**
4277  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4278  *
4279  * @state: crtc's scaler state
4280  * @plane_state: atomic plane state to update
4281  *
4282  * Return
4283  *     0 - scaler_usage updated successfully
4284  *    error - requested scaling cannot be supported or other error condition
4285  */
4286 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4287                                    struct intel_plane_state *plane_state)
4288 {
4289
4290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4291         struct intel_plane *intel_plane =
4292                 to_intel_plane(plane_state->base.plane);
4293         struct drm_framebuffer *fb = plane_state->base.fb;
4294         int ret;
4295
4296         bool force_detach = !fb || !plane_state->visible;
4297
4298         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4299                       intel_plane->base.base.id, intel_crtc->pipe,
4300                       drm_plane_index(&intel_plane->base));
4301
4302         ret = skl_update_scaler(crtc_state, force_detach,
4303                                 drm_plane_index(&intel_plane->base),
4304                                 &plane_state->scaler_id,
4305                                 plane_state->base.rotation,
4306                                 drm_rect_width(&plane_state->src) >> 16,
4307                                 drm_rect_height(&plane_state->src) >> 16,
4308                                 drm_rect_width(&plane_state->dst),
4309                                 drm_rect_height(&plane_state->dst));
4310
4311         if (ret || plane_state->scaler_id < 0)
4312                 return ret;
4313
4314         /* check colorkey */
4315         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4316                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4317                               intel_plane->base.base.id);
4318                 return -EINVAL;
4319         }
4320
4321         /* Check src format */
4322         switch (fb->pixel_format) {
4323         case DRM_FORMAT_RGB565:
4324         case DRM_FORMAT_XBGR8888:
4325         case DRM_FORMAT_XRGB8888:
4326         case DRM_FORMAT_ABGR8888:
4327         case DRM_FORMAT_ARGB8888:
4328         case DRM_FORMAT_XRGB2101010:
4329         case DRM_FORMAT_XBGR2101010:
4330         case DRM_FORMAT_YUYV:
4331         case DRM_FORMAT_YVYU:
4332         case DRM_FORMAT_UYVY:
4333         case DRM_FORMAT_VYUY:
4334                 break;
4335         default:
4336                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4337                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4338                 return -EINVAL;
4339         }
4340
4341         return 0;
4342 }
4343
4344 static void skylake_scaler_disable(struct intel_crtc *crtc)
4345 {
4346         int i;
4347
4348         for (i = 0; i < crtc->num_scalers; i++)
4349                 skl_detach_scaler(crtc, i);
4350 }
4351
4352 static void skylake_pfit_enable(struct intel_crtc *crtc)
4353 {
4354         struct drm_device *dev = crtc->base.dev;
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         int pipe = crtc->pipe;
4357         struct intel_crtc_scaler_state *scaler_state =
4358                 &crtc->config->scaler_state;
4359
4360         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4361
4362         if (crtc->config->pch_pfit.enabled) {
4363                 int id;
4364
4365                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4366                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4367                         return;
4368                 }
4369
4370                 id = scaler_state->scaler_id;
4371                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4372                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4373                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4374                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4375
4376                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4377         }
4378 }
4379
4380 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4381 {
4382         struct drm_device *dev = crtc->base.dev;
4383         struct drm_i915_private *dev_priv = dev->dev_private;
4384         int pipe = crtc->pipe;
4385
4386         if (crtc->config->pch_pfit.enabled) {
4387                 /* Force use of hard-coded filter coefficients
4388                  * as some pre-programmed values are broken,
4389                  * e.g. x201.
4390                  */
4391                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4392                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4393                                                  PF_PIPE_SEL_IVB(pipe));
4394                 else
4395                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4396                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4397                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4398         }
4399 }
4400
4401 void hsw_enable_ips(struct intel_crtc *crtc)
4402 {
4403         struct drm_device *dev = crtc->base.dev;
4404         struct drm_i915_private *dev_priv = dev->dev_private;
4405
4406         if (!crtc->config->ips_enabled)
4407                 return;
4408
4409         /*
4410          * We can only enable IPS after we enable a plane and wait for a vblank
4411          * This function is called from post_plane_update, which is run after
4412          * a vblank wait.
4413          */
4414
4415         assert_plane_enabled(dev_priv, crtc->plane);
4416         if (IS_BROADWELL(dev)) {
4417                 mutex_lock(&dev_priv->rps.hw_lock);
4418                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4419                 mutex_unlock(&dev_priv->rps.hw_lock);
4420                 /* Quoting Art Runyan: "its not safe to expect any particular
4421                  * value in IPS_CTL bit 31 after enabling IPS through the
4422                  * mailbox." Moreover, the mailbox may return a bogus state,
4423                  * so we need to just enable it and continue on.
4424                  */
4425         } else {
4426                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4427                 /* The bit only becomes 1 in the next vblank, so this wait here
4428                  * is essentially intel_wait_for_vblank. If we don't have this
4429                  * and don't wait for vblanks until the end of crtc_enable, then
4430                  * the HW state readout code will complain that the expected
4431                  * IPS_CTL value is not the one we read. */
4432                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4433                         DRM_ERROR("Timed out waiting for IPS enable\n");
4434         }
4435 }
4436
4437 void hsw_disable_ips(struct intel_crtc *crtc)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = dev->dev_private;
4441
4442         if (!crtc->config->ips_enabled)
4443                 return;
4444
4445         assert_plane_enabled(dev_priv, crtc->plane);
4446         if (IS_BROADWELL(dev)) {
4447                 mutex_lock(&dev_priv->rps.hw_lock);
4448                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4449                 mutex_unlock(&dev_priv->rps.hw_lock);
4450                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4451                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4452                         DRM_ERROR("Timed out waiting for IPS disable\n");
4453         } else {
4454                 I915_WRITE(IPS_CTL, 0);
4455                 POSTING_READ(IPS_CTL);
4456         }
4457
4458         /* We need to wait for a vblank before we can disable the plane. */
4459         intel_wait_for_vblank(dev, crtc->pipe);
4460 }
4461
4462 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4463 {
4464         if (intel_crtc->overlay) {
4465                 struct drm_device *dev = intel_crtc->base.dev;
4466                 struct drm_i915_private *dev_priv = dev->dev_private;
4467
4468                 mutex_lock(&dev->struct_mutex);
4469                 dev_priv->mm.interruptible = false;
4470                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4471                 dev_priv->mm.interruptible = true;
4472                 mutex_unlock(&dev->struct_mutex);
4473         }
4474
4475         /* Let userspace switch the overlay on again. In most cases userspace
4476          * has to recompute where to put it anyway.
4477          */
4478 }
4479
4480 /**
4481  * intel_post_enable_primary - Perform operations after enabling primary plane
4482  * @crtc: the CRTC whose primary plane was just enabled
4483  *
4484  * Performs potentially sleeping operations that must be done after the primary
4485  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4486  * called due to an explicit primary plane update, or due to an implicit
4487  * re-enable that is caused when a sprite plane is updated to no longer
4488  * completely hide the primary plane.
4489  */
4490 static void
4491 intel_post_enable_primary(struct drm_crtc *crtc)
4492 {
4493         struct drm_device *dev = crtc->dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496         int pipe = intel_crtc->pipe;
4497
4498         /*
4499          * FIXME IPS should be fine as long as one plane is
4500          * enabled, but in practice it seems to have problems
4501          * when going from primary only to sprite only and vice
4502          * versa.
4503          */
4504         hsw_enable_ips(intel_crtc);
4505
4506         /*
4507          * Gen2 reports pipe underruns whenever all planes are disabled.
4508          * So don't enable underrun reporting before at least some planes
4509          * are enabled.
4510          * FIXME: Need to fix the logic to work when we turn off all planes
4511          * but leave the pipe running.
4512          */
4513         if (IS_GEN2(dev))
4514                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4515
4516         /* Underruns don't always raise interrupts, so check manually. */
4517         intel_check_cpu_fifo_underruns(dev_priv);
4518         intel_check_pch_fifo_underruns(dev_priv);
4519 }
4520
4521 /* FIXME move all this to pre_plane_update() with proper state tracking */
4522 static void
4523 intel_pre_disable_primary(struct drm_crtc *crtc)
4524 {
4525         struct drm_device *dev = crtc->dev;
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528         int pipe = intel_crtc->pipe;
4529
4530         /*
4531          * Gen2 reports pipe underruns whenever all planes are disabled.
4532          * So diasble underrun reporting before all the planes get disabled.
4533          * FIXME: Need to fix the logic to work when we turn off all planes
4534          * but leave the pipe running.
4535          */
4536         if (IS_GEN2(dev))
4537                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4538
4539         /*
4540          * FIXME IPS should be fine as long as one plane is
4541          * enabled, but in practice it seems to have problems
4542          * when going from primary only to sprite only and vice
4543          * versa.
4544          */
4545         hsw_disable_ips(intel_crtc);
4546 }
4547
4548 /* FIXME get rid of this and use pre_plane_update */
4549 static void
4550 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4551 {
4552         struct drm_device *dev = crtc->dev;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4555         int pipe = intel_crtc->pipe;
4556
4557         intel_pre_disable_primary(crtc);
4558
4559         /*
4560          * Vblank time updates from the shadow to live plane control register
4561          * are blocked if the memory self-refresh mode is active at that
4562          * moment. So to make sure the plane gets truly disabled, disable
4563          * first the self-refresh mode. The self-refresh enable bit in turn
4564          * will be checked/applied by the HW only at the next frame start
4565          * event which is after the vblank start event, so we need to have a
4566          * wait-for-vblank between disabling the plane and the pipe.
4567          */
4568         if (HAS_GMCH_DISPLAY(dev)) {
4569                 intel_set_memory_cxsr(dev_priv, false);
4570                 dev_priv->wm.vlv.cxsr = false;
4571                 intel_wait_for_vblank(dev, pipe);
4572         }
4573 }
4574
4575 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4576 {
4577         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4578         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4579         struct intel_crtc_state *pipe_config =
4580                 to_intel_crtc_state(crtc->base.state);
4581         struct drm_device *dev = crtc->base.dev;
4582         struct drm_plane *primary = crtc->base.primary;
4583         struct drm_plane_state *old_pri_state =
4584                 drm_atomic_get_existing_plane_state(old_state, primary);
4585
4586         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4587
4588         crtc->wm.cxsr_allowed = true;
4589
4590         if (pipe_config->update_wm_post && pipe_config->base.active)
4591                 intel_update_watermarks(&crtc->base);
4592
4593         if (old_pri_state) {
4594                 struct intel_plane_state *primary_state =
4595                         to_intel_plane_state(primary->state);
4596                 struct intel_plane_state *old_primary_state =
4597                         to_intel_plane_state(old_pri_state);
4598
4599                 intel_fbc_post_update(crtc);
4600
4601                 if (primary_state->visible &&
4602                     (needs_modeset(&pipe_config->base) ||
4603                      !old_primary_state->visible))
4604                         intel_post_enable_primary(&crtc->base);
4605         }
4606 }
4607
4608 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4609 {
4610         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4611         struct drm_device *dev = crtc->base.dev;
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613         struct intel_crtc_state *pipe_config =
4614                 to_intel_crtc_state(crtc->base.state);
4615         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4616         struct drm_plane *primary = crtc->base.primary;
4617         struct drm_plane_state *old_pri_state =
4618                 drm_atomic_get_existing_plane_state(old_state, primary);
4619         bool modeset = needs_modeset(&pipe_config->base);
4620
4621         if (old_pri_state) {
4622                 struct intel_plane_state *primary_state =
4623                         to_intel_plane_state(primary->state);
4624                 struct intel_plane_state *old_primary_state =
4625                         to_intel_plane_state(old_pri_state);
4626
4627                 intel_fbc_pre_update(crtc);
4628
4629                 if (old_primary_state->visible &&
4630                     (modeset || !primary_state->visible))
4631                         intel_pre_disable_primary(&crtc->base);
4632         }
4633
4634         if (pipe_config->disable_cxsr) {
4635                 crtc->wm.cxsr_allowed = false;
4636
4637                 /*
4638                  * Vblank time updates from the shadow to live plane control register
4639                  * are blocked if the memory self-refresh mode is active at that
4640                  * moment. So to make sure the plane gets truly disabled, disable
4641                  * first the self-refresh mode. The self-refresh enable bit in turn
4642                  * will be checked/applied by the HW only at the next frame start
4643                  * event which is after the vblank start event, so we need to have a
4644                  * wait-for-vblank between disabling the plane and the pipe.
4645                  */
4646                 if (old_crtc_state->base.active) {
4647                         intel_set_memory_cxsr(dev_priv, false);
4648                         dev_priv->wm.vlv.cxsr = false;
4649                         intel_wait_for_vblank(dev, crtc->pipe);
4650                 }
4651         }
4652
4653         /*
4654          * IVB workaround: must disable low power watermarks for at least
4655          * one frame before enabling scaling.  LP watermarks can be re-enabled
4656          * when scaling is disabled.
4657          *
4658          * WaCxSRDisabledForSpriteScaling:ivb
4659          */
4660         if (pipe_config->disable_lp_wm) {
4661                 ilk_disable_lp_wm(dev);
4662                 intel_wait_for_vblank(dev, crtc->pipe);
4663         }
4664
4665         /*
4666          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4667          * watermark programming here.
4668          */
4669         if (needs_modeset(&pipe_config->base))
4670                 return;
4671
4672         /*
4673          * For platforms that support atomic watermarks, program the
4674          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4675          * will be the intermediate values that are safe for both pre- and
4676          * post- vblank; when vblank happens, the 'active' values will be set
4677          * to the final 'target' values and we'll do this again to get the
4678          * optimal watermarks.  For gen9+ platforms, the values we program here
4679          * will be the final target values which will get automatically latched
4680          * at vblank time; no further programming will be necessary.
4681          *
4682          * If a platform hasn't been transitioned to atomic watermarks yet,
4683          * we'll continue to update watermarks the old way, if flags tell
4684          * us to.
4685          */
4686         if (dev_priv->display.initial_watermarks != NULL)
4687                 dev_priv->display.initial_watermarks(pipe_config);
4688         else if (pipe_config->update_wm_pre)
4689                 intel_update_watermarks(&crtc->base);
4690 }
4691
4692 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4693 {
4694         struct drm_device *dev = crtc->dev;
4695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4696         struct drm_plane *p;
4697         int pipe = intel_crtc->pipe;
4698
4699         intel_crtc_dpms_overlay_disable(intel_crtc);
4700
4701         drm_for_each_plane_mask(p, dev, plane_mask)
4702                 to_intel_plane(p)->disable_plane(p, crtc);
4703
4704         /*
4705          * FIXME: Once we grow proper nuclear flip support out of this we need
4706          * to compute the mask of flip planes precisely. For the time being
4707          * consider this a flip to a NULL plane.
4708          */
4709         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4710 }
4711
4712 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4713 {
4714         struct drm_device *dev = crtc->dev;
4715         struct drm_i915_private *dev_priv = dev->dev_private;
4716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717         struct intel_encoder *encoder;
4718         int pipe = intel_crtc->pipe;
4719         struct intel_crtc_state *pipe_config =
4720                 to_intel_crtc_state(crtc->state);
4721
4722         if (WARN_ON(intel_crtc->active))
4723                 return;
4724
4725         /*
4726          * Sometimes spurious CPU pipe underruns happen during FDI
4727          * training, at least with VGA+HDMI cloning. Suppress them.
4728          *
4729          * On ILK we get an occasional spurious CPU pipe underruns
4730          * between eDP port A enable and vdd enable. Also PCH port
4731          * enable seems to result in the occasional CPU pipe underrun.
4732          *
4733          * Spurious PCH underruns also occur during PCH enabling.
4734          */
4735         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4736                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4737         if (intel_crtc->config->has_pch_encoder)
4738                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4739
4740         if (intel_crtc->config->has_pch_encoder)
4741                 intel_prepare_shared_dpll(intel_crtc);
4742
4743         if (intel_crtc->config->has_dp_encoder)
4744                 intel_dp_set_m_n(intel_crtc, M1_N1);
4745
4746         intel_set_pipe_timings(intel_crtc);
4747         intel_set_pipe_src_size(intel_crtc);
4748
4749         if (intel_crtc->config->has_pch_encoder) {
4750                 intel_cpu_transcoder_set_m_n(intel_crtc,
4751                                      &intel_crtc->config->fdi_m_n, NULL);
4752         }
4753
4754         ironlake_set_pipeconf(crtc);
4755
4756         intel_crtc->active = true;
4757
4758         for_each_encoder_on_crtc(dev, crtc, encoder)
4759                 if (encoder->pre_enable)
4760                         encoder->pre_enable(encoder);
4761
4762         if (intel_crtc->config->has_pch_encoder) {
4763                 /* Note: FDI PLL enabling _must_ be done before we enable the
4764                  * cpu pipes, hence this is separate from all the other fdi/pch
4765                  * enabling. */
4766                 ironlake_fdi_pll_enable(intel_crtc);
4767         } else {
4768                 assert_fdi_tx_disabled(dev_priv, pipe);
4769                 assert_fdi_rx_disabled(dev_priv, pipe);
4770         }
4771
4772         ironlake_pfit_enable(intel_crtc);
4773
4774         /*
4775          * On ILK+ LUT must be loaded before the pipe is running but with
4776          * clocks enabled
4777          */
4778         intel_color_load_luts(&pipe_config->base);
4779
4780         if (dev_priv->display.initial_watermarks != NULL)
4781                 dev_priv->display.initial_watermarks(intel_crtc->config);
4782         intel_enable_pipe(intel_crtc);
4783
4784         if (intel_crtc->config->has_pch_encoder)
4785                 ironlake_pch_enable(crtc);
4786
4787         assert_vblank_disabled(crtc);
4788         drm_crtc_vblank_on(crtc);
4789
4790         for_each_encoder_on_crtc(dev, crtc, encoder)
4791                 encoder->enable(encoder);
4792
4793         if (HAS_PCH_CPT(dev))
4794                 cpt_verify_modeset(dev, intel_crtc->pipe);
4795
4796         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4797         if (intel_crtc->config->has_pch_encoder)
4798                 intel_wait_for_vblank(dev, pipe);
4799         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4800         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4801 }
4802
4803 /* IPS only exists on ULT machines and is tied to pipe A. */
4804 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4805 {
4806         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4807 }
4808
4809 static void haswell_crtc_enable(struct drm_crtc *crtc)
4810 {
4811         struct drm_device *dev = crtc->dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814         struct intel_encoder *encoder;
4815         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4816         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4817         struct intel_crtc_state *pipe_config =
4818                 to_intel_crtc_state(crtc->state);
4819
4820         if (WARN_ON(intel_crtc->active))
4821                 return;
4822
4823         if (intel_crtc->config->has_pch_encoder)
4824                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4825                                                       false);
4826
4827         if (intel_crtc->config->shared_dpll)
4828                 intel_enable_shared_dpll(intel_crtc);
4829
4830         if (intel_crtc->config->has_dp_encoder)
4831                 intel_dp_set_m_n(intel_crtc, M1_N1);
4832
4833         if (!intel_crtc->config->has_dsi_encoder)
4834                 intel_set_pipe_timings(intel_crtc);
4835
4836         intel_set_pipe_src_size(intel_crtc);
4837
4838         if (cpu_transcoder != TRANSCODER_EDP &&
4839             !transcoder_is_dsi(cpu_transcoder)) {
4840                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4841                            intel_crtc->config->pixel_multiplier - 1);
4842         }
4843
4844         if (intel_crtc->config->has_pch_encoder) {
4845                 intel_cpu_transcoder_set_m_n(intel_crtc,
4846                                      &intel_crtc->config->fdi_m_n, NULL);
4847         }
4848
4849         if (!intel_crtc->config->has_dsi_encoder)
4850                 haswell_set_pipeconf(crtc);
4851
4852         haswell_set_pipemisc(crtc);
4853
4854         intel_color_set_csc(&pipe_config->base);
4855
4856         intel_crtc->active = true;
4857
4858         if (intel_crtc->config->has_pch_encoder)
4859                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4860         else
4861                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4862
4863         for_each_encoder_on_crtc(dev, crtc, encoder) {
4864                 if (encoder->pre_enable)
4865                         encoder->pre_enable(encoder);
4866         }
4867
4868         if (intel_crtc->config->has_pch_encoder)
4869                 dev_priv->display.fdi_link_train(crtc);
4870
4871         if (!intel_crtc->config->has_dsi_encoder)
4872                 intel_ddi_enable_pipe_clock(intel_crtc);
4873
4874         if (INTEL_INFO(dev)->gen >= 9)
4875                 skylake_pfit_enable(intel_crtc);
4876         else
4877                 ironlake_pfit_enable(intel_crtc);
4878
4879         /*
4880          * On ILK+ LUT must be loaded before the pipe is running but with
4881          * clocks enabled
4882          */
4883         intel_color_load_luts(&pipe_config->base);
4884
4885         intel_ddi_set_pipe_settings(crtc);
4886         if (!intel_crtc->config->has_dsi_encoder)
4887                 intel_ddi_enable_transcoder_func(crtc);
4888
4889         if (dev_priv->display.initial_watermarks != NULL)
4890                 dev_priv->display.initial_watermarks(pipe_config);
4891         else
4892                 intel_update_watermarks(crtc);
4893
4894         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4895         if (!intel_crtc->config->has_dsi_encoder)
4896                 intel_enable_pipe(intel_crtc);
4897
4898         if (intel_crtc->config->has_pch_encoder)
4899                 lpt_pch_enable(crtc);
4900
4901         if (intel_crtc->config->dp_encoder_is_mst)
4902                 intel_ddi_set_vc_payload_alloc(crtc, true);
4903
4904         assert_vblank_disabled(crtc);
4905         drm_crtc_vblank_on(crtc);
4906
4907         for_each_encoder_on_crtc(dev, crtc, encoder) {
4908                 encoder->enable(encoder);
4909                 intel_opregion_notify_encoder(encoder, true);
4910         }
4911
4912         if (intel_crtc->config->has_pch_encoder) {
4913                 intel_wait_for_vblank(dev, pipe);
4914                 intel_wait_for_vblank(dev, pipe);
4915                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4916                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4917                                                       true);
4918         }
4919
4920         /* If we change the relative order between pipe/planes enabling, we need
4921          * to change the workaround. */
4922         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4923         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4924                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4925                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4926         }
4927 }
4928
4929 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4930 {
4931         struct drm_device *dev = crtc->base.dev;
4932         struct drm_i915_private *dev_priv = dev->dev_private;
4933         int pipe = crtc->pipe;
4934
4935         /* To avoid upsetting the power well on haswell only disable the pfit if
4936          * it's in use. The hw state code will make sure we get this right. */
4937         if (force || crtc->config->pch_pfit.enabled) {
4938                 I915_WRITE(PF_CTL(pipe), 0);
4939                 I915_WRITE(PF_WIN_POS(pipe), 0);
4940                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4941         }
4942 }
4943
4944 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4945 {
4946         struct drm_device *dev = crtc->dev;
4947         struct drm_i915_private *dev_priv = dev->dev_private;
4948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949         struct intel_encoder *encoder;
4950         int pipe = intel_crtc->pipe;
4951
4952         /*
4953          * Sometimes spurious CPU pipe underruns happen when the
4954          * pipe is already disabled, but FDI RX/TX is still enabled.
4955          * Happens at least with VGA+HDMI cloning. Suppress them.
4956          */
4957         if (intel_crtc->config->has_pch_encoder) {
4958                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4959                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4960         }
4961
4962         for_each_encoder_on_crtc(dev, crtc, encoder)
4963                 encoder->disable(encoder);
4964
4965         drm_crtc_vblank_off(crtc);
4966         assert_vblank_disabled(crtc);
4967
4968         intel_disable_pipe(intel_crtc);
4969
4970         ironlake_pfit_disable(intel_crtc, false);
4971
4972         if (intel_crtc->config->has_pch_encoder)
4973                 ironlake_fdi_disable(crtc);
4974
4975         for_each_encoder_on_crtc(dev, crtc, encoder)
4976                 if (encoder->post_disable)
4977                         encoder->post_disable(encoder);
4978
4979         if (intel_crtc->config->has_pch_encoder) {
4980                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4981
4982                 if (HAS_PCH_CPT(dev)) {
4983                         i915_reg_t reg;
4984                         u32 temp;
4985
4986                         /* disable TRANS_DP_CTL */
4987                         reg = TRANS_DP_CTL(pipe);
4988                         temp = I915_READ(reg);
4989                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4990                                   TRANS_DP_PORT_SEL_MASK);
4991                         temp |= TRANS_DP_PORT_SEL_NONE;
4992                         I915_WRITE(reg, temp);
4993
4994                         /* disable DPLL_SEL */
4995                         temp = I915_READ(PCH_DPLL_SEL);
4996                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4997                         I915_WRITE(PCH_DPLL_SEL, temp);
4998                 }
4999
5000                 ironlake_fdi_pll_disable(intel_crtc);
5001         }
5002
5003         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5004         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5005 }
5006
5007 static void haswell_crtc_disable(struct drm_crtc *crtc)
5008 {
5009         struct drm_device *dev = crtc->dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012         struct intel_encoder *encoder;
5013         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5014
5015         if (intel_crtc->config->has_pch_encoder)
5016                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5017                                                       false);
5018
5019         for_each_encoder_on_crtc(dev, crtc, encoder) {
5020                 intel_opregion_notify_encoder(encoder, false);
5021                 encoder->disable(encoder);
5022         }
5023
5024         drm_crtc_vblank_off(crtc);
5025         assert_vblank_disabled(crtc);
5026
5027         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5028         if (!intel_crtc->config->has_dsi_encoder)
5029                 intel_disable_pipe(intel_crtc);
5030
5031         if (intel_crtc->config->dp_encoder_is_mst)
5032                 intel_ddi_set_vc_payload_alloc(crtc, false);
5033
5034         if (!intel_crtc->config->has_dsi_encoder)
5035                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5036
5037         if (INTEL_INFO(dev)->gen >= 9)
5038                 skylake_scaler_disable(intel_crtc);
5039         else
5040                 ironlake_pfit_disable(intel_crtc, false);
5041
5042         if (!intel_crtc->config->has_dsi_encoder)
5043                 intel_ddi_disable_pipe_clock(intel_crtc);
5044
5045         for_each_encoder_on_crtc(dev, crtc, encoder)
5046                 if (encoder->post_disable)
5047                         encoder->post_disable(encoder);
5048
5049         if (intel_crtc->config->has_pch_encoder) {
5050                 lpt_disable_pch_transcoder(dev_priv);
5051                 lpt_disable_iclkip(dev_priv);
5052                 intel_ddi_fdi_disable(crtc);
5053
5054                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5055                                                       true);
5056         }
5057 }
5058
5059 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5060 {
5061         struct drm_device *dev = crtc->base.dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         struct intel_crtc_state *pipe_config = crtc->config;
5064
5065         if (!pipe_config->gmch_pfit.control)
5066                 return;
5067
5068         /*
5069          * The panel fitter should only be adjusted whilst the pipe is disabled,
5070          * according to register description and PRM.
5071          */
5072         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5073         assert_pipe_disabled(dev_priv, crtc->pipe);
5074
5075         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5076         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5077
5078         /* Border color in case we don't scale up to the full screen. Black by
5079          * default, change to something else for debugging. */
5080         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5081 }
5082
5083 static enum intel_display_power_domain port_to_power_domain(enum port port)
5084 {
5085         switch (port) {
5086         case PORT_A:
5087                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5088         case PORT_B:
5089                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5090         case PORT_C:
5091                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5092         case PORT_D:
5093                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5094         case PORT_E:
5095                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5096         default:
5097                 MISSING_CASE(port);
5098                 return POWER_DOMAIN_PORT_OTHER;
5099         }
5100 }
5101
5102 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5103 {
5104         switch (port) {
5105         case PORT_A:
5106                 return POWER_DOMAIN_AUX_A;
5107         case PORT_B:
5108                 return POWER_DOMAIN_AUX_B;
5109         case PORT_C:
5110                 return POWER_DOMAIN_AUX_C;
5111         case PORT_D:
5112                 return POWER_DOMAIN_AUX_D;
5113         case PORT_E:
5114                 /* FIXME: Check VBT for actual wiring of PORT E */
5115                 return POWER_DOMAIN_AUX_D;
5116         default:
5117                 MISSING_CASE(port);
5118                 return POWER_DOMAIN_AUX_A;
5119         }
5120 }
5121
5122 enum intel_display_power_domain
5123 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5124 {
5125         struct drm_device *dev = intel_encoder->base.dev;
5126         struct intel_digital_port *intel_dig_port;
5127
5128         switch (intel_encoder->type) {
5129         case INTEL_OUTPUT_UNKNOWN:
5130                 /* Only DDI platforms should ever use this output type */
5131                 WARN_ON_ONCE(!HAS_DDI(dev));
5132         case INTEL_OUTPUT_DISPLAYPORT:
5133         case INTEL_OUTPUT_HDMI:
5134         case INTEL_OUTPUT_EDP:
5135                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5136                 return port_to_power_domain(intel_dig_port->port);
5137         case INTEL_OUTPUT_DP_MST:
5138                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5139                 return port_to_power_domain(intel_dig_port->port);
5140         case INTEL_OUTPUT_ANALOG:
5141                 return POWER_DOMAIN_PORT_CRT;
5142         case INTEL_OUTPUT_DSI:
5143                 return POWER_DOMAIN_PORT_DSI;
5144         default:
5145                 return POWER_DOMAIN_PORT_OTHER;
5146         }
5147 }
5148
5149 enum intel_display_power_domain
5150 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5151 {
5152         struct drm_device *dev = intel_encoder->base.dev;
5153         struct intel_digital_port *intel_dig_port;
5154
5155         switch (intel_encoder->type) {
5156         case INTEL_OUTPUT_UNKNOWN:
5157         case INTEL_OUTPUT_HDMI:
5158                 /*
5159                  * Only DDI platforms should ever use these output types.
5160                  * We can get here after the HDMI detect code has already set
5161                  * the type of the shared encoder. Since we can't be sure
5162                  * what's the status of the given connectors, play safe and
5163                  * run the DP detection too.
5164                  */
5165                 WARN_ON_ONCE(!HAS_DDI(dev));
5166         case INTEL_OUTPUT_DISPLAYPORT:
5167         case INTEL_OUTPUT_EDP:
5168                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5169                 return port_to_aux_power_domain(intel_dig_port->port);
5170         case INTEL_OUTPUT_DP_MST:
5171                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5172                 return port_to_aux_power_domain(intel_dig_port->port);
5173         default:
5174                 MISSING_CASE(intel_encoder->type);
5175                 return POWER_DOMAIN_AUX_A;
5176         }
5177 }
5178
5179 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5180                                             struct intel_crtc_state *crtc_state)
5181 {
5182         struct drm_device *dev = crtc->dev;
5183         struct drm_encoder *encoder;
5184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5185         enum pipe pipe = intel_crtc->pipe;
5186         unsigned long mask;
5187         enum transcoder transcoder = crtc_state->cpu_transcoder;
5188
5189         if (!crtc_state->base.active)
5190                 return 0;
5191
5192         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5193         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5194         if (crtc_state->pch_pfit.enabled ||
5195             crtc_state->pch_pfit.force_thru)
5196                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5197
5198         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5199                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5200
5201                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5202         }
5203
5204         if (crtc_state->shared_dpll)
5205                 mask |= BIT(POWER_DOMAIN_PLLS);
5206
5207         return mask;
5208 }
5209
5210 static unsigned long
5211 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5212                                struct intel_crtc_state *crtc_state)
5213 {
5214         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216         enum intel_display_power_domain domain;
5217         unsigned long domains, new_domains, old_domains;
5218
5219         old_domains = intel_crtc->enabled_power_domains;
5220         intel_crtc->enabled_power_domains = new_domains =
5221                 get_crtc_power_domains(crtc, crtc_state);
5222
5223         domains = new_domains & ~old_domains;
5224
5225         for_each_power_domain(domain, domains)
5226                 intel_display_power_get(dev_priv, domain);
5227
5228         return old_domains & ~new_domains;
5229 }
5230
5231 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5232                                       unsigned long domains)
5233 {
5234         enum intel_display_power_domain domain;
5235
5236         for_each_power_domain(domain, domains)
5237                 intel_display_power_put(dev_priv, domain);
5238 }
5239
5240 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5241 {
5242         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5243
5244         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5245             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5246                 return max_cdclk_freq;
5247         else if (IS_CHERRYVIEW(dev_priv))
5248                 return max_cdclk_freq*95/100;
5249         else if (INTEL_INFO(dev_priv)->gen < 4)
5250                 return 2*max_cdclk_freq*90/100;
5251         else
5252                 return max_cdclk_freq*90/100;
5253 }
5254
5255 static void intel_update_max_cdclk(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258
5259         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5260                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5261
5262                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5263                         dev_priv->max_cdclk_freq = 675000;
5264                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5265                         dev_priv->max_cdclk_freq = 540000;
5266                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5267                         dev_priv->max_cdclk_freq = 450000;
5268                 else
5269                         dev_priv->max_cdclk_freq = 337500;
5270         } else if (IS_BROXTON(dev)) {
5271                 dev_priv->max_cdclk_freq = 624000;
5272         } else if (IS_BROADWELL(dev))  {
5273                 /*
5274                  * FIXME with extra cooling we can allow
5275                  * 540 MHz for ULX and 675 Mhz for ULT.
5276                  * How can we know if extra cooling is
5277                  * available? PCI ID, VTB, something else?
5278                  */
5279                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5280                         dev_priv->max_cdclk_freq = 450000;
5281                 else if (IS_BDW_ULX(dev))
5282                         dev_priv->max_cdclk_freq = 450000;
5283                 else if (IS_BDW_ULT(dev))
5284                         dev_priv->max_cdclk_freq = 540000;
5285                 else
5286                         dev_priv->max_cdclk_freq = 675000;
5287         } else if (IS_CHERRYVIEW(dev)) {
5288                 dev_priv->max_cdclk_freq = 320000;
5289         } else if (IS_VALLEYVIEW(dev)) {
5290                 dev_priv->max_cdclk_freq = 400000;
5291         } else {
5292                 /* otherwise assume cdclk is fixed */
5293                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5294         }
5295
5296         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5297
5298         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5299                          dev_priv->max_cdclk_freq);
5300
5301         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5302                          dev_priv->max_dotclk_freq);
5303 }
5304
5305 static void intel_update_cdclk(struct drm_device *dev)
5306 {
5307         struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311                          dev_priv->cdclk_freq);
5312
5313         /*
5314          * Program the gmbus_freq based on the cdclk frequency.
5315          * BSpec erroneously claims we should aim for 4MHz, but
5316          * in fact 1MHz is the correct frequency.
5317          */
5318         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5319                 /*
5320                  * Program the gmbus_freq based on the cdclk frequency.
5321                  * BSpec erroneously claims we should aim for 4MHz, but
5322                  * in fact 1MHz is the correct frequency.
5323                  */
5324                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5325         }
5326
5327         if (dev_priv->max_cdclk_freq == 0)
5328                 intel_update_max_cdclk(dev);
5329 }
5330
5331 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5332 {
5333         struct drm_i915_private *dev_priv = dev->dev_private;
5334         uint32_t divider;
5335         uint32_t ratio;
5336         uint32_t current_freq;
5337         int ret;
5338
5339         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5340         switch (frequency) {
5341         case 144000:
5342                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5343                 ratio = BXT_DE_PLL_RATIO(60);
5344                 break;
5345         case 288000:
5346                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5347                 ratio = BXT_DE_PLL_RATIO(60);
5348                 break;
5349         case 384000:
5350                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5351                 ratio = BXT_DE_PLL_RATIO(60);
5352                 break;
5353         case 576000:
5354                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5355                 ratio = BXT_DE_PLL_RATIO(60);
5356                 break;
5357         case 624000:
5358                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5359                 ratio = BXT_DE_PLL_RATIO(65);
5360                 break;
5361         case 19200:
5362                 /*
5363                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5364                  * to suppress GCC warning.
5365                  */
5366                 ratio = 0;
5367                 divider = 0;
5368                 break;
5369         default:
5370                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5371
5372                 return;
5373         }
5374
5375         mutex_lock(&dev_priv->rps.hw_lock);
5376         /* Inform power controller of upcoming frequency change */
5377         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5378                                       0x80000000);
5379         mutex_unlock(&dev_priv->rps.hw_lock);
5380
5381         if (ret) {
5382                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5383                           ret, frequency);
5384                 return;
5385         }
5386
5387         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5388         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5389         current_freq = current_freq * 500 + 1000;
5390
5391         /*
5392          * DE PLL has to be disabled when
5393          * - setting to 19.2MHz (bypass, PLL isn't used)
5394          * - before setting to 624MHz (PLL needs toggling)
5395          * - before setting to any frequency from 624MHz (PLL needs toggling)
5396          */
5397         if (frequency == 19200 || frequency == 624000 ||
5398             current_freq == 624000) {
5399                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5400                 /* Timeout 200us */
5401                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5402                              1))
5403                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5404         }
5405
5406         if (frequency != 19200) {
5407                 uint32_t val;
5408
5409                 val = I915_READ(BXT_DE_PLL_CTL);
5410                 val &= ~BXT_DE_PLL_RATIO_MASK;
5411                 val |= ratio;
5412                 I915_WRITE(BXT_DE_PLL_CTL, val);
5413
5414                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415                 /* Timeout 200us */
5416                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5417                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5418
5419                 val = I915_READ(CDCLK_CTL);
5420                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5421                 val |= divider;
5422                 /*
5423                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5424                  * enable otherwise.
5425                  */
5426                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427                 if (frequency >= 500000)
5428                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429
5430                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5431                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5432                 val |= (frequency - 1000) / 500;
5433                 I915_WRITE(CDCLK_CTL, val);
5434         }
5435
5436         mutex_lock(&dev_priv->rps.hw_lock);
5437         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5438                                       DIV_ROUND_UP(frequency, 25000));
5439         mutex_unlock(&dev_priv->rps.hw_lock);
5440
5441         if (ret) {
5442                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5443                           ret, frequency);
5444                 return;
5445         }
5446
5447         intel_update_cdclk(dev);
5448 }
5449
5450 void broxton_init_cdclk(struct drm_device *dev)
5451 {
5452         struct drm_i915_private *dev_priv = dev->dev_private;
5453         uint32_t val;
5454
5455         /*
5456          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5457          * or else the reset will hang because there is no PCH to respond.
5458          * Move the handshake programming to initialization sequence.
5459          * Previously was left up to BIOS.
5460          */
5461         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5462         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5463         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5464
5465         /* Enable PG1 for cdclk */
5466         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5467
5468         /* check if cd clock is enabled */
5469         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5470                 DRM_DEBUG_KMS("Display already initialized\n");
5471                 return;
5472         }
5473
5474         /*
5475          * FIXME:
5476          * - The initial CDCLK needs to be read from VBT.
5477          *   Need to make this change after VBT has changes for BXT.
5478          * - check if setting the max (or any) cdclk freq is really necessary
5479          *   here, it belongs to modeset time
5480          */
5481         broxton_set_cdclk(dev, 624000);
5482
5483         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5484         POSTING_READ(DBUF_CTL);
5485
5486         udelay(10);
5487
5488         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5489                 DRM_ERROR("DBuf power enable timeout!\n");
5490 }
5491
5492 void broxton_uninit_cdclk(struct drm_device *dev)
5493 {
5494         struct drm_i915_private *dev_priv = dev->dev_private;
5495
5496         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5497         POSTING_READ(DBUF_CTL);
5498
5499         udelay(10);
5500
5501         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5502                 DRM_ERROR("DBuf power disable timeout!\n");
5503
5504         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5505         broxton_set_cdclk(dev, 19200);
5506
5507         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5508 }
5509
5510 static const struct skl_cdclk_entry {
5511         unsigned int freq;
5512         unsigned int vco;
5513 } skl_cdclk_frequencies[] = {
5514         { .freq = 308570, .vco = 8640 },
5515         { .freq = 337500, .vco = 8100 },
5516         { .freq = 432000, .vco = 8640 },
5517         { .freq = 450000, .vco = 8100 },
5518         { .freq = 540000, .vco = 8100 },
5519         { .freq = 617140, .vco = 8640 },
5520         { .freq = 675000, .vco = 8100 },
5521 };
5522
5523 static unsigned int skl_cdclk_decimal(unsigned int freq)
5524 {
5525         return (freq - 1000) / 500;
5526 }
5527
5528 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5529 {
5530         unsigned int i;
5531
5532         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5533                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5534
5535                 if (e->freq == freq)
5536                         return e->vco;
5537         }
5538
5539         return 8100;
5540 }
5541
5542 static void
5543 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5544 {
5545         unsigned int min_freq;
5546         u32 val;
5547
5548         /* select the minimum CDCLK before enabling DPLL 0 */
5549         val = I915_READ(CDCLK_CTL);
5550         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5551         val |= CDCLK_FREQ_337_308;
5552
5553         if (required_vco == 8640)
5554                 min_freq = 308570;
5555         else
5556                 min_freq = 337500;
5557
5558         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5559
5560         I915_WRITE(CDCLK_CTL, val);
5561         POSTING_READ(CDCLK_CTL);
5562
5563         /*
5564          * We always enable DPLL0 with the lowest link rate possible, but still
5565          * taking into account the VCO required to operate the eDP panel at the
5566          * desired frequency. The usual DP link rates operate with a VCO of
5567          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5568          * The modeset code is responsible for the selection of the exact link
5569          * rate later on, with the constraint of choosing a frequency that
5570          * works with required_vco.
5571          */
5572         val = I915_READ(DPLL_CTRL1);
5573
5574         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5575                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5576         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5577         if (required_vco == 8640)
5578                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5579                                             SKL_DPLL0);
5580         else
5581                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5582                                             SKL_DPLL0);
5583
5584         I915_WRITE(DPLL_CTRL1, val);
5585         POSTING_READ(DPLL_CTRL1);
5586
5587         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5588
5589         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5590                 DRM_ERROR("DPLL0 not locked\n");
5591 }
5592
5593 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5594 {
5595         int ret;
5596         u32 val;
5597
5598         /* inform PCU we want to change CDCLK */
5599         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5600         mutex_lock(&dev_priv->rps.hw_lock);
5601         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5602         mutex_unlock(&dev_priv->rps.hw_lock);
5603
5604         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5605 }
5606
5607 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5608 {
5609         unsigned int i;
5610
5611         for (i = 0; i < 15; i++) {
5612                 if (skl_cdclk_pcu_ready(dev_priv))
5613                         return true;
5614                 udelay(10);
5615         }
5616
5617         return false;
5618 }
5619
5620 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5621 {
5622         struct drm_device *dev = dev_priv->dev;
5623         u32 freq_select, pcu_ack;
5624
5625         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5626
5627         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5628                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5629                 return;
5630         }
5631
5632         /* set CDCLK_CTL */
5633         switch(freq) {
5634         case 450000:
5635         case 432000:
5636                 freq_select = CDCLK_FREQ_450_432;
5637                 pcu_ack = 1;
5638                 break;
5639         case 540000:
5640                 freq_select = CDCLK_FREQ_540;
5641                 pcu_ack = 2;
5642                 break;
5643         case 308570:
5644         case 337500:
5645         default:
5646                 freq_select = CDCLK_FREQ_337_308;
5647                 pcu_ack = 0;
5648                 break;
5649         case 617140:
5650         case 675000:
5651                 freq_select = CDCLK_FREQ_675_617;
5652                 pcu_ack = 3;
5653                 break;
5654         }
5655
5656         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5657         POSTING_READ(CDCLK_CTL);
5658
5659         /* inform PCU of the change */
5660         mutex_lock(&dev_priv->rps.hw_lock);
5661         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5662         mutex_unlock(&dev_priv->rps.hw_lock);
5663
5664         intel_update_cdclk(dev);
5665 }
5666
5667 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5668 {
5669         /* disable DBUF power */
5670         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5671         POSTING_READ(DBUF_CTL);
5672
5673         udelay(10);
5674
5675         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5676                 DRM_ERROR("DBuf power disable timeout\n");
5677
5678         /* disable DPLL0 */
5679         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5680         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5681                 DRM_ERROR("Couldn't disable DPLL0\n");
5682 }
5683
5684 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5685 {
5686         unsigned int required_vco;
5687
5688         /* DPLL0 not enabled (happens on early BIOS versions) */
5689         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5690                 /* enable DPLL0 */
5691                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5692                 skl_dpll0_enable(dev_priv, required_vco);
5693         }
5694
5695         /* set CDCLK to the frequency the BIOS chose */
5696         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5697
5698         /* enable DBUF power */
5699         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5700         POSTING_READ(DBUF_CTL);
5701
5702         udelay(10);
5703
5704         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5705                 DRM_ERROR("DBuf power enable timeout\n");
5706 }
5707
5708 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5709 {
5710         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5711         uint32_t cdctl = I915_READ(CDCLK_CTL);
5712         int freq = dev_priv->skl_boot_cdclk;
5713
5714         /*
5715          * check if the pre-os intialized the display
5716          * There is SWF18 scratchpad register defined which is set by the
5717          * pre-os which can be used by the OS drivers to check the status
5718          */
5719         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5720                 goto sanitize;
5721
5722         /* Is PLL enabled and locked ? */
5723         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5724                 goto sanitize;
5725
5726         /* DPLL okay; verify the cdclock
5727          *
5728          * Noticed in some instances that the freq selection is correct but
5729          * decimal part is programmed wrong from BIOS where pre-os does not
5730          * enable display. Verify the same as well.
5731          */
5732         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5733                 /* All well; nothing to sanitize */
5734                 return false;
5735 sanitize:
5736         /*
5737          * As of now initialize with max cdclk till
5738          * we get dynamic cdclk support
5739          * */
5740         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5741         skl_init_cdclk(dev_priv);
5742
5743         /* we did have to sanitize */
5744         return true;
5745 }
5746
5747 /* Adjust CDclk dividers to allow high res or save power if possible */
5748 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5749 {
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751         u32 val, cmd;
5752
5753         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5754                                         != dev_priv->cdclk_freq);
5755
5756         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5757                 cmd = 2;
5758         else if (cdclk == 266667)
5759                 cmd = 1;
5760         else
5761                 cmd = 0;
5762
5763         mutex_lock(&dev_priv->rps.hw_lock);
5764         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5765         val &= ~DSPFREQGUAR_MASK;
5766         val |= (cmd << DSPFREQGUAR_SHIFT);
5767         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5768         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5769                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5770                      50)) {
5771                 DRM_ERROR("timed out waiting for CDclk change\n");
5772         }
5773         mutex_unlock(&dev_priv->rps.hw_lock);
5774
5775         mutex_lock(&dev_priv->sb_lock);
5776
5777         if (cdclk == 400000) {
5778                 u32 divider;
5779
5780                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5781
5782                 /* adjust cdclk divider */
5783                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5784                 val &= ~CCK_FREQUENCY_VALUES;
5785                 val |= divider;
5786                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5787
5788                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5789                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5790                              50))
5791                         DRM_ERROR("timed out waiting for CDclk change\n");
5792         }
5793
5794         /* adjust self-refresh exit latency value */
5795         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5796         val &= ~0x7f;
5797
5798         /*
5799          * For high bandwidth configs, we set a higher latency in the bunit
5800          * so that the core display fetch happens in time to avoid underruns.
5801          */
5802         if (cdclk == 400000)
5803                 val |= 4500 / 250; /* 4.5 usec */
5804         else
5805                 val |= 3000 / 250; /* 3.0 usec */
5806         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5807
5808         mutex_unlock(&dev_priv->sb_lock);
5809
5810         intel_update_cdclk(dev);
5811 }
5812
5813 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5814 {
5815         struct drm_i915_private *dev_priv = dev->dev_private;
5816         u32 val, cmd;
5817
5818         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5819                                                 != dev_priv->cdclk_freq);
5820
5821         switch (cdclk) {
5822         case 333333:
5823         case 320000:
5824         case 266667:
5825         case 200000:
5826                 break;
5827         default:
5828                 MISSING_CASE(cdclk);
5829                 return;
5830         }
5831
5832         /*
5833          * Specs are full of misinformation, but testing on actual
5834          * hardware has shown that we just need to write the desired
5835          * CCK divider into the Punit register.
5836          */
5837         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5838
5839         mutex_lock(&dev_priv->rps.hw_lock);
5840         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5841         val &= ~DSPFREQGUAR_MASK_CHV;
5842         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5843         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5844         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5845                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5846                      50)) {
5847                 DRM_ERROR("timed out waiting for CDclk change\n");
5848         }
5849         mutex_unlock(&dev_priv->rps.hw_lock);
5850
5851         intel_update_cdclk(dev);
5852 }
5853
5854 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5855                                  int max_pixclk)
5856 {
5857         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5858         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5859
5860         /*
5861          * Really only a few cases to deal with, as only 4 CDclks are supported:
5862          *   200MHz
5863          *   267MHz
5864          *   320/333MHz (depends on HPLL freq)
5865          *   400MHz (VLV only)
5866          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5867          * of the lower bin and adjust if needed.
5868          *
5869          * We seem to get an unstable or solid color picture at 200MHz.
5870          * Not sure what's wrong. For now use 200MHz only when all pipes
5871          * are off.
5872          */
5873         if (!IS_CHERRYVIEW(dev_priv) &&
5874             max_pixclk > freq_320*limit/100)
5875                 return 400000;
5876         else if (max_pixclk > 266667*limit/100)
5877                 return freq_320;
5878         else if (max_pixclk > 0)
5879                 return 266667;
5880         else
5881                 return 200000;
5882 }
5883
5884 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5885                               int max_pixclk)
5886 {
5887         /*
5888          * FIXME:
5889          * - remove the guardband, it's not needed on BXT
5890          * - set 19.2MHz bypass frequency if there are no active pipes
5891          */
5892         if (max_pixclk > 576000*9/10)
5893                 return 624000;
5894         else if (max_pixclk > 384000*9/10)
5895                 return 576000;
5896         else if (max_pixclk > 288000*9/10)
5897                 return 384000;
5898         else if (max_pixclk > 144000*9/10)
5899                 return 288000;
5900         else
5901                 return 144000;
5902 }
5903
5904 /* Compute the max pixel clock for new configuration. */
5905 static int intel_mode_max_pixclk(struct drm_device *dev,
5906                                  struct drm_atomic_state *state)
5907 {
5908         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5909         struct drm_i915_private *dev_priv = dev->dev_private;
5910         struct drm_crtc *crtc;
5911         struct drm_crtc_state *crtc_state;
5912         unsigned max_pixclk = 0, i;
5913         enum pipe pipe;
5914
5915         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5916                sizeof(intel_state->min_pixclk));
5917
5918         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5919                 int pixclk = 0;
5920
5921                 if (crtc_state->enable)
5922                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5923
5924                 intel_state->min_pixclk[i] = pixclk;
5925         }
5926
5927         for_each_pipe(dev_priv, pipe)
5928                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5929
5930         return max_pixclk;
5931 }
5932
5933 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5934 {
5935         struct drm_device *dev = state->dev;
5936         struct drm_i915_private *dev_priv = dev->dev_private;
5937         int max_pixclk = intel_mode_max_pixclk(dev, state);
5938         struct intel_atomic_state *intel_state =
5939                 to_intel_atomic_state(state);
5940
5941         if (max_pixclk < 0)
5942                 return max_pixclk;
5943
5944         intel_state->cdclk = intel_state->dev_cdclk =
5945                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5946
5947         if (!intel_state->active_crtcs)
5948                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5949
5950         return 0;
5951 }
5952
5953 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5954 {
5955         struct drm_device *dev = state->dev;
5956         struct drm_i915_private *dev_priv = dev->dev_private;
5957         int max_pixclk = intel_mode_max_pixclk(dev, state);
5958         struct intel_atomic_state *intel_state =
5959                 to_intel_atomic_state(state);
5960
5961         if (max_pixclk < 0)
5962                 return max_pixclk;
5963
5964         intel_state->cdclk = intel_state->dev_cdclk =
5965                 broxton_calc_cdclk(dev_priv, max_pixclk);
5966
5967         if (!intel_state->active_crtcs)
5968                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5969
5970         return 0;
5971 }
5972
5973 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5974 {
5975         unsigned int credits, default_credits;
5976
5977         if (IS_CHERRYVIEW(dev_priv))
5978                 default_credits = PFI_CREDIT(12);
5979         else
5980                 default_credits = PFI_CREDIT(8);
5981
5982         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5983                 /* CHV suggested value is 31 or 63 */
5984                 if (IS_CHERRYVIEW(dev_priv))
5985                         credits = PFI_CREDIT_63;
5986                 else
5987                         credits = PFI_CREDIT(15);
5988         } else {
5989                 credits = default_credits;
5990         }
5991
5992         /*
5993          * WA - write default credits before re-programming
5994          * FIXME: should we also set the resend bit here?
5995          */
5996         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5997                    default_credits);
5998
5999         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6000                    credits | PFI_CREDIT_RESEND);
6001
6002         /*
6003          * FIXME is this guaranteed to clear
6004          * immediately or should we poll for it?
6005          */
6006         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6007 }
6008
6009 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6010 {
6011         struct drm_device *dev = old_state->dev;
6012         struct drm_i915_private *dev_priv = dev->dev_private;
6013         struct intel_atomic_state *old_intel_state =
6014                 to_intel_atomic_state(old_state);
6015         unsigned req_cdclk = old_intel_state->dev_cdclk;
6016
6017         /*
6018          * FIXME: We can end up here with all power domains off, yet
6019          * with a CDCLK frequency other than the minimum. To account
6020          * for this take the PIPE-A power domain, which covers the HW
6021          * blocks needed for the following programming. This can be
6022          * removed once it's guaranteed that we get here either with
6023          * the minimum CDCLK set, or the required power domains
6024          * enabled.
6025          */
6026         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6027
6028         if (IS_CHERRYVIEW(dev))
6029                 cherryview_set_cdclk(dev, req_cdclk);
6030         else
6031                 valleyview_set_cdclk(dev, req_cdclk);
6032
6033         vlv_program_pfi_credits(dev_priv);
6034
6035         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6036 }
6037
6038 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6039 {
6040         struct drm_device *dev = crtc->dev;
6041         struct drm_i915_private *dev_priv = to_i915(dev);
6042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6043         struct intel_encoder *encoder;
6044         struct intel_crtc_state *pipe_config =
6045                 to_intel_crtc_state(crtc->state);
6046         int pipe = intel_crtc->pipe;
6047
6048         if (WARN_ON(intel_crtc->active))
6049                 return;
6050
6051         if (intel_crtc->config->has_dp_encoder)
6052                 intel_dp_set_m_n(intel_crtc, M1_N1);
6053
6054         intel_set_pipe_timings(intel_crtc);
6055         intel_set_pipe_src_size(intel_crtc);
6056
6057         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6058                 struct drm_i915_private *dev_priv = dev->dev_private;
6059
6060                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6061                 I915_WRITE(CHV_CANVAS(pipe), 0);
6062         }
6063
6064         i9xx_set_pipeconf(intel_crtc);
6065
6066         intel_crtc->active = true;
6067
6068         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6069
6070         for_each_encoder_on_crtc(dev, crtc, encoder)
6071                 if (encoder->pre_pll_enable)
6072                         encoder->pre_pll_enable(encoder);
6073
6074         if (!intel_crtc->config->has_dsi_encoder) {
6075                 if (IS_CHERRYVIEW(dev)) {
6076                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6077                         chv_enable_pll(intel_crtc, intel_crtc->config);
6078                 } else {
6079                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6080                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6081                 }
6082         }
6083
6084         for_each_encoder_on_crtc(dev, crtc, encoder)
6085                 if (encoder->pre_enable)
6086                         encoder->pre_enable(encoder);
6087
6088         i9xx_pfit_enable(intel_crtc);
6089
6090         intel_color_load_luts(&pipe_config->base);
6091
6092         intel_update_watermarks(crtc);
6093         intel_enable_pipe(intel_crtc);
6094
6095         assert_vblank_disabled(crtc);
6096         drm_crtc_vblank_on(crtc);
6097
6098         for_each_encoder_on_crtc(dev, crtc, encoder)
6099                 encoder->enable(encoder);
6100 }
6101
6102 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6103 {
6104         struct drm_device *dev = crtc->base.dev;
6105         struct drm_i915_private *dev_priv = dev->dev_private;
6106
6107         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6108         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6109 }
6110
6111 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6112 {
6113         struct drm_device *dev = crtc->dev;
6114         struct drm_i915_private *dev_priv = to_i915(dev);
6115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6116         struct intel_encoder *encoder;
6117         struct intel_crtc_state *pipe_config =
6118                 to_intel_crtc_state(crtc->state);
6119         int pipe = intel_crtc->pipe;
6120
6121         if (WARN_ON(intel_crtc->active))
6122                 return;
6123
6124         i9xx_set_pll_dividers(intel_crtc);
6125
6126         if (intel_crtc->config->has_dp_encoder)
6127                 intel_dp_set_m_n(intel_crtc, M1_N1);
6128
6129         intel_set_pipe_timings(intel_crtc);
6130         intel_set_pipe_src_size(intel_crtc);
6131
6132         i9xx_set_pipeconf(intel_crtc);
6133
6134         intel_crtc->active = true;
6135
6136         if (!IS_GEN2(dev))
6137                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6138
6139         for_each_encoder_on_crtc(dev, crtc, encoder)
6140                 if (encoder->pre_enable)
6141                         encoder->pre_enable(encoder);
6142
6143         i9xx_enable_pll(intel_crtc);
6144
6145         i9xx_pfit_enable(intel_crtc);
6146
6147         intel_color_load_luts(&pipe_config->base);
6148
6149         intel_update_watermarks(crtc);
6150         intel_enable_pipe(intel_crtc);
6151
6152         assert_vblank_disabled(crtc);
6153         drm_crtc_vblank_on(crtc);
6154
6155         for_each_encoder_on_crtc(dev, crtc, encoder)
6156                 encoder->enable(encoder);
6157 }
6158
6159 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6160 {
6161         struct drm_device *dev = crtc->base.dev;
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163
6164         if (!crtc->config->gmch_pfit.control)
6165                 return;
6166
6167         assert_pipe_disabled(dev_priv, crtc->pipe);
6168
6169         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6170                          I915_READ(PFIT_CONTROL));
6171         I915_WRITE(PFIT_CONTROL, 0);
6172 }
6173
6174 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6175 {
6176         struct drm_device *dev = crtc->dev;
6177         struct drm_i915_private *dev_priv = dev->dev_private;
6178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6179         struct intel_encoder *encoder;
6180         int pipe = intel_crtc->pipe;
6181
6182         /*
6183          * On gen2 planes are double buffered but the pipe isn't, so we must
6184          * wait for planes to fully turn off before disabling the pipe.
6185          */
6186         if (IS_GEN2(dev))
6187                 intel_wait_for_vblank(dev, pipe);
6188
6189         for_each_encoder_on_crtc(dev, crtc, encoder)
6190                 encoder->disable(encoder);
6191
6192         drm_crtc_vblank_off(crtc);
6193         assert_vblank_disabled(crtc);
6194
6195         intel_disable_pipe(intel_crtc);
6196
6197         i9xx_pfit_disable(intel_crtc);
6198
6199         for_each_encoder_on_crtc(dev, crtc, encoder)
6200                 if (encoder->post_disable)
6201                         encoder->post_disable(encoder);
6202
6203         if (!intel_crtc->config->has_dsi_encoder) {
6204                 if (IS_CHERRYVIEW(dev))
6205                         chv_disable_pll(dev_priv, pipe);
6206                 else if (IS_VALLEYVIEW(dev))
6207                         vlv_disable_pll(dev_priv, pipe);
6208                 else
6209                         i9xx_disable_pll(intel_crtc);
6210         }
6211
6212         for_each_encoder_on_crtc(dev, crtc, encoder)
6213                 if (encoder->post_pll_disable)
6214                         encoder->post_pll_disable(encoder);
6215
6216         if (!IS_GEN2(dev))
6217                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6218 }
6219
6220 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6221 {
6222         struct intel_encoder *encoder;
6223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6225         enum intel_display_power_domain domain;
6226         unsigned long domains;
6227
6228         if (!intel_crtc->active)
6229                 return;
6230
6231         if (to_intel_plane_state(crtc->primary->state)->visible) {
6232                 WARN_ON(intel_crtc->unpin_work);
6233
6234                 intel_pre_disable_primary_noatomic(crtc);
6235
6236                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6237                 to_intel_plane_state(crtc->primary->state)->visible = false;
6238         }
6239
6240         dev_priv->display.crtc_disable(crtc);
6241
6242         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6243                       crtc->base.id);
6244
6245         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6246         crtc->state->active = false;
6247         intel_crtc->active = false;
6248         crtc->enabled = false;
6249         crtc->state->connector_mask = 0;
6250         crtc->state->encoder_mask = 0;
6251
6252         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6253                 encoder->base.crtc = NULL;
6254
6255         intel_fbc_disable(intel_crtc);
6256         intel_update_watermarks(crtc);
6257         intel_disable_shared_dpll(intel_crtc);
6258
6259         domains = intel_crtc->enabled_power_domains;
6260         for_each_power_domain(domain, domains)
6261                 intel_display_power_put(dev_priv, domain);
6262         intel_crtc->enabled_power_domains = 0;
6263
6264         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6265         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6266 }
6267
6268 /*
6269  * turn all crtc's off, but do not adjust state
6270  * This has to be paired with a call to intel_modeset_setup_hw_state.
6271  */
6272 int intel_display_suspend(struct drm_device *dev)
6273 {
6274         struct drm_i915_private *dev_priv = to_i915(dev);
6275         struct drm_atomic_state *state;
6276         int ret;
6277
6278         state = drm_atomic_helper_suspend(dev);
6279         ret = PTR_ERR_OR_ZERO(state);
6280         if (ret)
6281                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6282         else
6283                 dev_priv->modeset_restore_state = state;
6284         return ret;
6285 }
6286
6287 void intel_encoder_destroy(struct drm_encoder *encoder)
6288 {
6289         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6290
6291         drm_encoder_cleanup(encoder);
6292         kfree(intel_encoder);
6293 }
6294
6295 /* Cross check the actual hw state with our own modeset state tracking (and it's
6296  * internal consistency). */
6297 static void intel_connector_verify_state(struct intel_connector *connector)
6298 {
6299         struct drm_crtc *crtc = connector->base.state->crtc;
6300
6301         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6302                       connector->base.base.id,
6303                       connector->base.name);
6304
6305         if (connector->get_hw_state(connector)) {
6306                 struct intel_encoder *encoder = connector->encoder;
6307                 struct drm_connector_state *conn_state = connector->base.state;
6308
6309                 I915_STATE_WARN(!crtc,
6310                          "connector enabled without attached crtc\n");
6311
6312                 if (!crtc)
6313                         return;
6314
6315                 I915_STATE_WARN(!crtc->state->active,
6316                       "connector is active, but attached crtc isn't\n");
6317
6318                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6319                         return;
6320
6321                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6322                         "atomic encoder doesn't match attached encoder\n");
6323
6324                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6325                         "attached encoder crtc differs from connector crtc\n");
6326         } else {
6327                 I915_STATE_WARN(crtc && crtc->state->active,
6328                         "attached crtc is active, but connector isn't\n");
6329                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6330                         "best encoder set without crtc!\n");
6331         }
6332 }
6333
6334 int intel_connector_init(struct intel_connector *connector)
6335 {
6336         drm_atomic_helper_connector_reset(&connector->base);
6337
6338         if (!connector->base.state)
6339                 return -ENOMEM;
6340
6341         return 0;
6342 }
6343
6344 struct intel_connector *intel_connector_alloc(void)
6345 {
6346         struct intel_connector *connector;
6347
6348         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6349         if (!connector)
6350                 return NULL;
6351
6352         if (intel_connector_init(connector) < 0) {
6353                 kfree(connector);
6354                 return NULL;
6355         }
6356
6357         return connector;
6358 }
6359
6360 /* Simple connector->get_hw_state implementation for encoders that support only
6361  * one connector and no cloning and hence the encoder state determines the state
6362  * of the connector. */
6363 bool intel_connector_get_hw_state(struct intel_connector *connector)
6364 {
6365         enum pipe pipe = 0;
6366         struct intel_encoder *encoder = connector->encoder;
6367
6368         return encoder->get_hw_state(encoder, &pipe);
6369 }
6370
6371 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6372 {
6373         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6374                 return crtc_state->fdi_lanes;
6375
6376         return 0;
6377 }
6378
6379 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6380                                      struct intel_crtc_state *pipe_config)
6381 {
6382         struct drm_atomic_state *state = pipe_config->base.state;
6383         struct intel_crtc *other_crtc;
6384         struct intel_crtc_state *other_crtc_state;
6385
6386         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6387                       pipe_name(pipe), pipe_config->fdi_lanes);
6388         if (pipe_config->fdi_lanes > 4) {
6389                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6390                               pipe_name(pipe), pipe_config->fdi_lanes);
6391                 return -EINVAL;
6392         }
6393
6394         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6395                 if (pipe_config->fdi_lanes > 2) {
6396                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6397                                       pipe_config->fdi_lanes);
6398                         return -EINVAL;
6399                 } else {
6400                         return 0;
6401                 }
6402         }
6403
6404         if (INTEL_INFO(dev)->num_pipes == 2)
6405                 return 0;
6406
6407         /* Ivybridge 3 pipe is really complicated */
6408         switch (pipe) {
6409         case PIPE_A:
6410                 return 0;
6411         case PIPE_B:
6412                 if (pipe_config->fdi_lanes <= 2)
6413                         return 0;
6414
6415                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6416                 other_crtc_state =
6417                         intel_atomic_get_crtc_state(state, other_crtc);
6418                 if (IS_ERR(other_crtc_state))
6419                         return PTR_ERR(other_crtc_state);
6420
6421                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6422                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6423                                       pipe_name(pipe), pipe_config->fdi_lanes);
6424                         return -EINVAL;
6425                 }
6426                 return 0;
6427         case PIPE_C:
6428                 if (pipe_config->fdi_lanes > 2) {
6429                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6430                                       pipe_name(pipe), pipe_config->fdi_lanes);
6431                         return -EINVAL;
6432                 }
6433
6434                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6435                 other_crtc_state =
6436                         intel_atomic_get_crtc_state(state, other_crtc);
6437                 if (IS_ERR(other_crtc_state))
6438                         return PTR_ERR(other_crtc_state);
6439
6440                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6441                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6442                         return -EINVAL;
6443                 }
6444                 return 0;
6445         default:
6446                 BUG();
6447         }
6448 }
6449
6450 #define RETRY 1
6451 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6452                                        struct intel_crtc_state *pipe_config)
6453 {
6454         struct drm_device *dev = intel_crtc->base.dev;
6455         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6456         int lane, link_bw, fdi_dotclock, ret;
6457         bool needs_recompute = false;
6458
6459 retry:
6460         /* FDI is a binary signal running at ~2.7GHz, encoding
6461          * each output octet as 10 bits. The actual frequency
6462          * is stored as a divider into a 100MHz clock, and the
6463          * mode pixel clock is stored in units of 1KHz.
6464          * Hence the bw of each lane in terms of the mode signal
6465          * is:
6466          */
6467         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6468
6469         fdi_dotclock = adjusted_mode->crtc_clock;
6470
6471         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6472                                            pipe_config->pipe_bpp);
6473
6474         pipe_config->fdi_lanes = lane;
6475
6476         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6477                                link_bw, &pipe_config->fdi_m_n);
6478
6479         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6480         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6481                 pipe_config->pipe_bpp -= 2*3;
6482                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6483                               pipe_config->pipe_bpp);
6484                 needs_recompute = true;
6485                 pipe_config->bw_constrained = true;
6486
6487                 goto retry;
6488         }
6489
6490         if (needs_recompute)
6491                 return RETRY;
6492
6493         return ret;
6494 }
6495
6496 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6497                                      struct intel_crtc_state *pipe_config)
6498 {
6499         if (pipe_config->pipe_bpp > 24)
6500                 return false;
6501
6502         /* HSW can handle pixel rate up to cdclk? */
6503         if (IS_HASWELL(dev_priv))
6504                 return true;
6505
6506         /*
6507          * We compare against max which means we must take
6508          * the increased cdclk requirement into account when
6509          * calculating the new cdclk.
6510          *
6511          * Should measure whether using a lower cdclk w/o IPS
6512          */
6513         return ilk_pipe_pixel_rate(pipe_config) <=
6514                 dev_priv->max_cdclk_freq * 95 / 100;
6515 }
6516
6517 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6518                                    struct intel_crtc_state *pipe_config)
6519 {
6520         struct drm_device *dev = crtc->base.dev;
6521         struct drm_i915_private *dev_priv = dev->dev_private;
6522
6523         pipe_config->ips_enabled = i915.enable_ips &&
6524                 hsw_crtc_supports_ips(crtc) &&
6525                 pipe_config_supports_ips(dev_priv, pipe_config);
6526 }
6527
6528 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6529 {
6530         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6531
6532         /* GDG double wide on either pipe, otherwise pipe A only */
6533         return INTEL_INFO(dev_priv)->gen < 4 &&
6534                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6535 }
6536
6537 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6538                                      struct intel_crtc_state *pipe_config)
6539 {
6540         struct drm_device *dev = crtc->base.dev;
6541         struct drm_i915_private *dev_priv = dev->dev_private;
6542         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6543
6544         /* FIXME should check pixel clock limits on all platforms */
6545         if (INTEL_INFO(dev)->gen < 4) {
6546                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6547
6548                 /*
6549                  * Enable double wide mode when the dot clock
6550                  * is > 90% of the (display) core speed.
6551                  */
6552                 if (intel_crtc_supports_double_wide(crtc) &&
6553                     adjusted_mode->crtc_clock > clock_limit) {
6554                         clock_limit *= 2;
6555                         pipe_config->double_wide = true;
6556                 }
6557
6558                 if (adjusted_mode->crtc_clock > clock_limit) {
6559                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6560                                       adjusted_mode->crtc_clock, clock_limit,
6561                                       yesno(pipe_config->double_wide));
6562                         return -EINVAL;
6563                 }
6564         }
6565
6566         /*
6567          * Pipe horizontal size must be even in:
6568          * - DVO ganged mode
6569          * - LVDS dual channel mode
6570          * - Double wide pipe
6571          */
6572         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6573              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6574                 pipe_config->pipe_src_w &= ~1;
6575
6576         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6577          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6578          */
6579         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6580                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6581                 return -EINVAL;
6582
6583         if (HAS_IPS(dev))
6584                 hsw_compute_ips_config(crtc, pipe_config);
6585
6586         if (pipe_config->has_pch_encoder)
6587                 return ironlake_fdi_compute_config(crtc, pipe_config);
6588
6589         return 0;
6590 }
6591
6592 static int skylake_get_display_clock_speed(struct drm_device *dev)
6593 {
6594         struct drm_i915_private *dev_priv = to_i915(dev);
6595         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6596         uint32_t cdctl = I915_READ(CDCLK_CTL);
6597         uint32_t linkrate;
6598
6599         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6600                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6601
6602         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6603                 return 540000;
6604
6605         linkrate = (I915_READ(DPLL_CTRL1) &
6606                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6607
6608         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6609             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6610                 /* vco 8640 */
6611                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6612                 case CDCLK_FREQ_450_432:
6613                         return 432000;
6614                 case CDCLK_FREQ_337_308:
6615                         return 308570;
6616                 case CDCLK_FREQ_675_617:
6617                         return 617140;
6618                 default:
6619                         WARN(1, "Unknown cd freq selection\n");
6620                 }
6621         } else {
6622                 /* vco 8100 */
6623                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6624                 case CDCLK_FREQ_450_432:
6625                         return 450000;
6626                 case CDCLK_FREQ_337_308:
6627                         return 337500;
6628                 case CDCLK_FREQ_675_617:
6629                         return 675000;
6630                 default:
6631                         WARN(1, "Unknown cd freq selection\n");
6632                 }
6633         }
6634
6635         /* error case, do as if DPLL0 isn't enabled */
6636         return 24000;
6637 }
6638
6639 static int broxton_get_display_clock_speed(struct drm_device *dev)
6640 {
6641         struct drm_i915_private *dev_priv = to_i915(dev);
6642         uint32_t cdctl = I915_READ(CDCLK_CTL);
6643         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6644         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6645         int cdclk;
6646
6647         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6648                 return 19200;
6649
6650         cdclk = 19200 * pll_ratio / 2;
6651
6652         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6653         case BXT_CDCLK_CD2X_DIV_SEL_1:
6654                 return cdclk;  /* 576MHz or 624MHz */
6655         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6656                 return cdclk * 2 / 3; /* 384MHz */
6657         case BXT_CDCLK_CD2X_DIV_SEL_2:
6658                 return cdclk / 2; /* 288MHz */
6659         case BXT_CDCLK_CD2X_DIV_SEL_4:
6660                 return cdclk / 4; /* 144MHz */
6661         }
6662
6663         /* error case, do as if DE PLL isn't enabled */
6664         return 19200;
6665 }
6666
6667 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6668 {
6669         struct drm_i915_private *dev_priv = dev->dev_private;
6670         uint32_t lcpll = I915_READ(LCPLL_CTL);
6671         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6672
6673         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6674                 return 800000;
6675         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6676                 return 450000;
6677         else if (freq == LCPLL_CLK_FREQ_450)
6678                 return 450000;
6679         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6680                 return 540000;
6681         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6682                 return 337500;
6683         else
6684                 return 675000;
6685 }
6686
6687 static int haswell_get_display_clock_speed(struct drm_device *dev)
6688 {
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         uint32_t lcpll = I915_READ(LCPLL_CTL);
6691         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6692
6693         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6694                 return 800000;
6695         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6696                 return 450000;
6697         else if (freq == LCPLL_CLK_FREQ_450)
6698                 return 450000;
6699         else if (IS_HSW_ULT(dev))
6700                 return 337500;
6701         else
6702                 return 540000;
6703 }
6704
6705 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6706 {
6707         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6708                                       CCK_DISPLAY_CLOCK_CONTROL);
6709 }
6710
6711 static int ilk_get_display_clock_speed(struct drm_device *dev)
6712 {
6713         return 450000;
6714 }
6715
6716 static int i945_get_display_clock_speed(struct drm_device *dev)
6717 {
6718         return 400000;
6719 }
6720
6721 static int i915_get_display_clock_speed(struct drm_device *dev)
6722 {
6723         return 333333;
6724 }
6725
6726 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6727 {
6728         return 200000;
6729 }
6730
6731 static int pnv_get_display_clock_speed(struct drm_device *dev)
6732 {
6733         u16 gcfgc = 0;
6734
6735         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6736
6737         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6738         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6739                 return 266667;
6740         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6741                 return 333333;
6742         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6743                 return 444444;
6744         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6745                 return 200000;
6746         default:
6747                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6748         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6749                 return 133333;
6750         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6751                 return 166667;
6752         }
6753 }
6754
6755 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6756 {
6757         u16 gcfgc = 0;
6758
6759         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6760
6761         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6762                 return 133333;
6763         else {
6764                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6765                 case GC_DISPLAY_CLOCK_333_MHZ:
6766                         return 333333;
6767                 default:
6768                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6769                         return 190000;
6770                 }
6771         }
6772 }
6773
6774 static int i865_get_display_clock_speed(struct drm_device *dev)
6775 {
6776         return 266667;
6777 }
6778
6779 static int i85x_get_display_clock_speed(struct drm_device *dev)
6780 {
6781         u16 hpllcc = 0;
6782
6783         /*
6784          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6785          * encoding is different :(
6786          * FIXME is this the right way to detect 852GM/852GMV?
6787          */
6788         if (dev->pdev->revision == 0x1)
6789                 return 133333;
6790
6791         pci_bus_read_config_word(dev->pdev->bus,
6792                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6793
6794         /* Assume that the hardware is in the high speed state.  This
6795          * should be the default.
6796          */
6797         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6798         case GC_CLOCK_133_200:
6799         case GC_CLOCK_133_200_2:
6800         case GC_CLOCK_100_200:
6801                 return 200000;
6802         case GC_CLOCK_166_250:
6803                 return 250000;
6804         case GC_CLOCK_100_133:
6805                 return 133333;
6806         case GC_CLOCK_133_266:
6807         case GC_CLOCK_133_266_2:
6808         case GC_CLOCK_166_266:
6809                 return 266667;
6810         }
6811
6812         /* Shouldn't happen */
6813         return 0;
6814 }
6815
6816 static int i830_get_display_clock_speed(struct drm_device *dev)
6817 {
6818         return 133333;
6819 }
6820
6821 static unsigned int intel_hpll_vco(struct drm_device *dev)
6822 {
6823         struct drm_i915_private *dev_priv = dev->dev_private;
6824         static const unsigned int blb_vco[8] = {
6825                 [0] = 3200000,
6826                 [1] = 4000000,
6827                 [2] = 5333333,
6828                 [3] = 4800000,
6829                 [4] = 6400000,
6830         };
6831         static const unsigned int pnv_vco[8] = {
6832                 [0] = 3200000,
6833                 [1] = 4000000,
6834                 [2] = 5333333,
6835                 [3] = 4800000,
6836                 [4] = 2666667,
6837         };
6838         static const unsigned int cl_vco[8] = {
6839                 [0] = 3200000,
6840                 [1] = 4000000,
6841                 [2] = 5333333,
6842                 [3] = 6400000,
6843                 [4] = 3333333,
6844                 [5] = 3566667,
6845                 [6] = 4266667,
6846         };
6847         static const unsigned int elk_vco[8] = {
6848                 [0] = 3200000,
6849                 [1] = 4000000,
6850                 [2] = 5333333,
6851                 [3] = 4800000,
6852         };
6853         static const unsigned int ctg_vco[8] = {
6854                 [0] = 3200000,
6855                 [1] = 4000000,
6856                 [2] = 5333333,
6857                 [3] = 6400000,
6858                 [4] = 2666667,
6859                 [5] = 4266667,
6860         };
6861         const unsigned int *vco_table;
6862         unsigned int vco;
6863         uint8_t tmp = 0;
6864
6865         /* FIXME other chipsets? */
6866         if (IS_GM45(dev))
6867                 vco_table = ctg_vco;
6868         else if (IS_G4X(dev))
6869                 vco_table = elk_vco;
6870         else if (IS_CRESTLINE(dev))
6871                 vco_table = cl_vco;
6872         else if (IS_PINEVIEW(dev))
6873                 vco_table = pnv_vco;
6874         else if (IS_G33(dev))
6875                 vco_table = blb_vco;
6876         else
6877                 return 0;
6878
6879         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6880
6881         vco = vco_table[tmp & 0x7];
6882         if (vco == 0)
6883                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6884         else
6885                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6886
6887         return vco;
6888 }
6889
6890 static int gm45_get_display_clock_speed(struct drm_device *dev)
6891 {
6892         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6893         uint16_t tmp = 0;
6894
6895         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6896
6897         cdclk_sel = (tmp >> 12) & 0x1;
6898
6899         switch (vco) {
6900         case 2666667:
6901         case 4000000:
6902         case 5333333:
6903                 return cdclk_sel ? 333333 : 222222;
6904         case 3200000:
6905                 return cdclk_sel ? 320000 : 228571;
6906         default:
6907                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6908                 return 222222;
6909         }
6910 }
6911
6912 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6913 {
6914         static const uint8_t div_3200[] = { 16, 10,  8 };
6915         static const uint8_t div_4000[] = { 20, 12, 10 };
6916         static const uint8_t div_5333[] = { 24, 16, 14 };
6917         const uint8_t *div_table;
6918         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6919         uint16_t tmp = 0;
6920
6921         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6922
6923         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6924
6925         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6926                 goto fail;
6927
6928         switch (vco) {
6929         case 3200000:
6930                 div_table = div_3200;
6931                 break;
6932         case 4000000:
6933                 div_table = div_4000;
6934                 break;
6935         case 5333333:
6936                 div_table = div_5333;
6937                 break;
6938         default:
6939                 goto fail;
6940         }
6941
6942         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6943
6944 fail:
6945         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6946         return 200000;
6947 }
6948
6949 static int g33_get_display_clock_speed(struct drm_device *dev)
6950 {
6951         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6952         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6953         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6954         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6955         const uint8_t *div_table;
6956         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6957         uint16_t tmp = 0;
6958
6959         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6960
6961         cdclk_sel = (tmp >> 4) & 0x7;
6962
6963         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6964                 goto fail;
6965
6966         switch (vco) {
6967         case 3200000:
6968                 div_table = div_3200;
6969                 break;
6970         case 4000000:
6971                 div_table = div_4000;
6972                 break;
6973         case 4800000:
6974                 div_table = div_4800;
6975                 break;
6976         case 5333333:
6977                 div_table = div_5333;
6978                 break;
6979         default:
6980                 goto fail;
6981         }
6982
6983         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6984
6985 fail:
6986         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6987         return 190476;
6988 }
6989
6990 static void
6991 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6992 {
6993         while (*num > DATA_LINK_M_N_MASK ||
6994                *den > DATA_LINK_M_N_MASK) {
6995                 *num >>= 1;
6996                 *den >>= 1;
6997         }
6998 }
6999
7000 static void compute_m_n(unsigned int m, unsigned int n,
7001                         uint32_t *ret_m, uint32_t *ret_n)
7002 {
7003         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7004         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7005         intel_reduce_m_n_ratio(ret_m, ret_n);
7006 }
7007
7008 void
7009 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7010                        int pixel_clock, int link_clock,
7011                        struct intel_link_m_n *m_n)
7012 {
7013         m_n->tu = 64;
7014
7015         compute_m_n(bits_per_pixel * pixel_clock,
7016                     link_clock * nlanes * 8,
7017                     &m_n->gmch_m, &m_n->gmch_n);
7018
7019         compute_m_n(pixel_clock, link_clock,
7020                     &m_n->link_m, &m_n->link_n);
7021 }
7022
7023 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7024 {
7025         if (i915.panel_use_ssc >= 0)
7026                 return i915.panel_use_ssc != 0;
7027         return dev_priv->vbt.lvds_use_ssc
7028                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7029 }
7030
7031 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7032 {
7033         return (1 << dpll->n) << 16 | dpll->m2;
7034 }
7035
7036 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7037 {
7038         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7039 }
7040
7041 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7042                                      struct intel_crtc_state *crtc_state,
7043                                      intel_clock_t *reduced_clock)
7044 {
7045         struct drm_device *dev = crtc->base.dev;
7046         u32 fp, fp2 = 0;
7047
7048         if (IS_PINEVIEW(dev)) {
7049                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7050                 if (reduced_clock)
7051                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7052         } else {
7053                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7054                 if (reduced_clock)
7055                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7056         }
7057
7058         crtc_state->dpll_hw_state.fp0 = fp;
7059
7060         crtc->lowfreq_avail = false;
7061         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7062             reduced_clock) {
7063                 crtc_state->dpll_hw_state.fp1 = fp2;
7064                 crtc->lowfreq_avail = true;
7065         } else {
7066                 crtc_state->dpll_hw_state.fp1 = fp;
7067         }
7068 }
7069
7070 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7071                 pipe)
7072 {
7073         u32 reg_val;
7074
7075         /*
7076          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7077          * and set it to a reasonable value instead.
7078          */
7079         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7080         reg_val &= 0xffffff00;
7081         reg_val |= 0x00000030;
7082         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7083
7084         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7085         reg_val &= 0x8cffffff;
7086         reg_val = 0x8c000000;
7087         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7088
7089         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7090         reg_val &= 0xffffff00;
7091         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7092
7093         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7094         reg_val &= 0x00ffffff;
7095         reg_val |= 0xb0000000;
7096         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7097 }
7098
7099 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7100                                          struct intel_link_m_n *m_n)
7101 {
7102         struct drm_device *dev = crtc->base.dev;
7103         struct drm_i915_private *dev_priv = dev->dev_private;
7104         int pipe = crtc->pipe;
7105
7106         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7107         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7108         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7109         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7110 }
7111
7112 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7113                                          struct intel_link_m_n *m_n,
7114                                          struct intel_link_m_n *m2_n2)
7115 {
7116         struct drm_device *dev = crtc->base.dev;
7117         struct drm_i915_private *dev_priv = dev->dev_private;
7118         int pipe = crtc->pipe;
7119         enum transcoder transcoder = crtc->config->cpu_transcoder;
7120
7121         if (INTEL_INFO(dev)->gen >= 5) {
7122                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7123                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7124                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7125                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7126                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7127                  * for gen < 8) and if DRRS is supported (to make sure the
7128                  * registers are not unnecessarily accessed).
7129                  */
7130                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7131                         crtc->config->has_drrs) {
7132                         I915_WRITE(PIPE_DATA_M2(transcoder),
7133                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7134                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7135                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7136                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7137                 }
7138         } else {
7139                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7140                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7141                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7142                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7143         }
7144 }
7145
7146 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7147 {
7148         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7149
7150         if (m_n == M1_N1) {
7151                 dp_m_n = &crtc->config->dp_m_n;
7152                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7153         } else if (m_n == M2_N2) {
7154
7155                 /*
7156                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7157                  * needs to be programmed into M1_N1.
7158                  */
7159                 dp_m_n = &crtc->config->dp_m2_n2;
7160         } else {
7161                 DRM_ERROR("Unsupported divider value\n");
7162                 return;
7163         }
7164
7165         if (crtc->config->has_pch_encoder)
7166                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7167         else
7168                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7169 }
7170
7171 static void vlv_compute_dpll(struct intel_crtc *crtc,
7172                              struct intel_crtc_state *pipe_config)
7173 {
7174         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7175                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7176                 DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
7177         if (crtc->pipe != PIPE_A)
7178                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7179
7180         pipe_config->dpll_hw_state.dpll_md =
7181                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7182 }
7183
7184 static void chv_compute_dpll(struct intel_crtc *crtc,
7185                              struct intel_crtc_state *pipe_config)
7186 {
7187         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7188                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7189                 DPLL_VCO_ENABLE;
7190         if (crtc->pipe != PIPE_A)
7191                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7192
7193         pipe_config->dpll_hw_state.dpll_md =
7194                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7195 }
7196
7197 static void vlv_prepare_pll(struct intel_crtc *crtc,
7198                             const struct intel_crtc_state *pipe_config)
7199 {
7200         struct drm_device *dev = crtc->base.dev;
7201         struct drm_i915_private *dev_priv = dev->dev_private;
7202         int pipe = crtc->pipe;
7203         u32 mdiv;
7204         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7205         u32 coreclk, reg_val;
7206
7207         mutex_lock(&dev_priv->sb_lock);
7208
7209         bestn = pipe_config->dpll.n;
7210         bestm1 = pipe_config->dpll.m1;
7211         bestm2 = pipe_config->dpll.m2;
7212         bestp1 = pipe_config->dpll.p1;
7213         bestp2 = pipe_config->dpll.p2;
7214
7215         /* See eDP HDMI DPIO driver vbios notes doc */
7216
7217         /* PLL B needs special handling */
7218         if (pipe == PIPE_B)
7219                 vlv_pllb_recal_opamp(dev_priv, pipe);
7220
7221         /* Set up Tx target for periodic Rcomp update */
7222         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7223
7224         /* Disable target IRef on PLL */
7225         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7226         reg_val &= 0x00ffffff;
7227         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7228
7229         /* Disable fast lock */
7230         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7231
7232         /* Set idtafcrecal before PLL is enabled */
7233         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7234         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7235         mdiv |= ((bestn << DPIO_N_SHIFT));
7236         mdiv |= (1 << DPIO_K_SHIFT);
7237
7238         /*
7239          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7240          * but we don't support that).
7241          * Note: don't use the DAC post divider as it seems unstable.
7242          */
7243         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7244         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7245
7246         mdiv |= DPIO_ENABLE_CALIBRATION;
7247         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7248
7249         /* Set HBR and RBR LPF coefficients */
7250         if (pipe_config->port_clock == 162000 ||
7251             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7252             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7253                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7254                                  0x009f0003);
7255         else
7256                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7257                                  0x00d0000f);
7258
7259         if (pipe_config->has_dp_encoder) {
7260                 /* Use SSC source */
7261                 if (pipe == PIPE_A)
7262                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7263                                          0x0df40000);
7264                 else
7265                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7266                                          0x0df70000);
7267         } else { /* HDMI or VGA */
7268                 /* Use bend source */
7269                 if (pipe == PIPE_A)
7270                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7271                                          0x0df70000);
7272                 else
7273                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7274                                          0x0df40000);
7275         }
7276
7277         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7278         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7279         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7280             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7281                 coreclk |= 0x01000000;
7282         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7283
7284         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7285         mutex_unlock(&dev_priv->sb_lock);
7286 }
7287
7288 static void chv_prepare_pll(struct intel_crtc *crtc,
7289                             const struct intel_crtc_state *pipe_config)
7290 {
7291         struct drm_device *dev = crtc->base.dev;
7292         struct drm_i915_private *dev_priv = dev->dev_private;
7293         int pipe = crtc->pipe;
7294         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7295         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7296         u32 loopfilter, tribuf_calcntr;
7297         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7298         u32 dpio_val;
7299         int vco;
7300
7301         bestn = pipe_config->dpll.n;
7302         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7303         bestm1 = pipe_config->dpll.m1;
7304         bestm2 = pipe_config->dpll.m2 >> 22;
7305         bestp1 = pipe_config->dpll.p1;
7306         bestp2 = pipe_config->dpll.p2;
7307         vco = pipe_config->dpll.vco;
7308         dpio_val = 0;
7309         loopfilter = 0;
7310
7311         /*
7312          * Enable Refclk and SSC
7313          */
7314         I915_WRITE(dpll_reg,
7315                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7316
7317         mutex_lock(&dev_priv->sb_lock);
7318
7319         /* p1 and p2 divider */
7320         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7321                         5 << DPIO_CHV_S1_DIV_SHIFT |
7322                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7323                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7324                         1 << DPIO_CHV_K_DIV_SHIFT);
7325
7326         /* Feedback post-divider - m2 */
7327         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7328
7329         /* Feedback refclk divider - n and m1 */
7330         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7331                         DPIO_CHV_M1_DIV_BY_2 |
7332                         1 << DPIO_CHV_N_DIV_SHIFT);
7333
7334         /* M2 fraction division */
7335         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7336
7337         /* M2 fraction division enable */
7338         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7339         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7340         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7341         if (bestm2_frac)
7342                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7343         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7344
7345         /* Program digital lock detect threshold */
7346         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7347         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7348                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7349         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7350         if (!bestm2_frac)
7351                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7352         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7353
7354         /* Loop filter */
7355         if (vco == 5400000) {
7356                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7357                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7358                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7359                 tribuf_calcntr = 0x9;
7360         } else if (vco <= 6200000) {
7361                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7362                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7363                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7364                 tribuf_calcntr = 0x9;
7365         } else if (vco <= 6480000) {
7366                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7367                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7368                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7369                 tribuf_calcntr = 0x8;
7370         } else {
7371                 /* Not supported. Apply the same limits as in the max case */
7372                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7373                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7374                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7375                 tribuf_calcntr = 0;
7376         }
7377         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7378
7379         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7380         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7381         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7382         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7383
7384         /* AFC Recal */
7385         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7386                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7387                         DPIO_AFC_RECAL);
7388
7389         mutex_unlock(&dev_priv->sb_lock);
7390 }
7391
7392 /**
7393  * vlv_force_pll_on - forcibly enable just the PLL
7394  * @dev_priv: i915 private structure
7395  * @pipe: pipe PLL to enable
7396  * @dpll: PLL configuration
7397  *
7398  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7399  * in cases where we need the PLL enabled even when @pipe is not going to
7400  * be enabled.
7401  */
7402 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7403                      const struct dpll *dpll)
7404 {
7405         struct intel_crtc *crtc =
7406                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7407         struct intel_crtc_state *pipe_config;
7408
7409         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7410         if (!pipe_config)
7411                 return -ENOMEM;
7412
7413         pipe_config->base.crtc = &crtc->base;
7414         pipe_config->pixel_multiplier = 1;
7415         pipe_config->dpll = *dpll;
7416
7417         if (IS_CHERRYVIEW(dev)) {
7418                 chv_compute_dpll(crtc, pipe_config);
7419                 chv_prepare_pll(crtc, pipe_config);
7420                 chv_enable_pll(crtc, pipe_config);
7421         } else {
7422                 vlv_compute_dpll(crtc, pipe_config);
7423                 vlv_prepare_pll(crtc, pipe_config);
7424                 vlv_enable_pll(crtc, pipe_config);
7425         }
7426
7427         kfree(pipe_config);
7428
7429         return 0;
7430 }
7431
7432 /**
7433  * vlv_force_pll_off - forcibly disable just the PLL
7434  * @dev_priv: i915 private structure
7435  * @pipe: pipe PLL to disable
7436  *
7437  * Disable the PLL for @pipe. To be used in cases where we need
7438  * the PLL enabled even when @pipe is not going to be enabled.
7439  */
7440 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7441 {
7442         if (IS_CHERRYVIEW(dev))
7443                 chv_disable_pll(to_i915(dev), pipe);
7444         else
7445                 vlv_disable_pll(to_i915(dev), pipe);
7446 }
7447
7448 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7449                               struct intel_crtc_state *crtc_state,
7450                               intel_clock_t *reduced_clock)
7451 {
7452         struct drm_device *dev = crtc->base.dev;
7453         struct drm_i915_private *dev_priv = dev->dev_private;
7454         u32 dpll;
7455         bool is_sdvo;
7456         struct dpll *clock = &crtc_state->dpll;
7457
7458         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7459
7460         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7461                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7462
7463         dpll = DPLL_VGA_MODE_DIS;
7464
7465         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7466                 dpll |= DPLLB_MODE_LVDS;
7467         else
7468                 dpll |= DPLLB_MODE_DAC_SERIAL;
7469
7470         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7471                 dpll |= (crtc_state->pixel_multiplier - 1)
7472                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7473         }
7474
7475         if (is_sdvo)
7476                 dpll |= DPLL_SDVO_HIGH_SPEED;
7477
7478         if (crtc_state->has_dp_encoder)
7479                 dpll |= DPLL_SDVO_HIGH_SPEED;
7480
7481         /* compute bitmask from p1 value */
7482         if (IS_PINEVIEW(dev))
7483                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7484         else {
7485                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7486                 if (IS_G4X(dev) && reduced_clock)
7487                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7488         }
7489         switch (clock->p2) {
7490         case 5:
7491                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7492                 break;
7493         case 7:
7494                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7495                 break;
7496         case 10:
7497                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7498                 break;
7499         case 14:
7500                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7501                 break;
7502         }
7503         if (INTEL_INFO(dev)->gen >= 4)
7504                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7505
7506         if (crtc_state->sdvo_tv_clock)
7507                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7508         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7509                  intel_panel_use_ssc(dev_priv))
7510                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7511         else
7512                 dpll |= PLL_REF_INPUT_DREFCLK;
7513
7514         dpll |= DPLL_VCO_ENABLE;
7515         crtc_state->dpll_hw_state.dpll = dpll;
7516
7517         if (INTEL_INFO(dev)->gen >= 4) {
7518                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7519                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7520                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7521         }
7522 }
7523
7524 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7525                               struct intel_crtc_state *crtc_state,
7526                               intel_clock_t *reduced_clock)
7527 {
7528         struct drm_device *dev = crtc->base.dev;
7529         struct drm_i915_private *dev_priv = dev->dev_private;
7530         u32 dpll;
7531         struct dpll *clock = &crtc_state->dpll;
7532
7533         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7534
7535         dpll = DPLL_VGA_MODE_DIS;
7536
7537         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7538                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7539         } else {
7540                 if (clock->p1 == 2)
7541                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7542                 else
7543                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7544                 if (clock->p2 == 4)
7545                         dpll |= PLL_P2_DIVIDE_BY_4;
7546         }
7547
7548         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7549                 dpll |= DPLL_DVO_2X_MODE;
7550
7551         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7552             intel_panel_use_ssc(dev_priv))
7553                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7554         else
7555                 dpll |= PLL_REF_INPUT_DREFCLK;
7556
7557         dpll |= DPLL_VCO_ENABLE;
7558         crtc_state->dpll_hw_state.dpll = dpll;
7559 }
7560
7561 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7562 {
7563         struct drm_device *dev = intel_crtc->base.dev;
7564         struct drm_i915_private *dev_priv = dev->dev_private;
7565         enum pipe pipe = intel_crtc->pipe;
7566         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7567         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7568         uint32_t crtc_vtotal, crtc_vblank_end;
7569         int vsyncshift = 0;
7570
7571         /* We need to be careful not to changed the adjusted mode, for otherwise
7572          * the hw state checker will get angry at the mismatch. */
7573         crtc_vtotal = adjusted_mode->crtc_vtotal;
7574         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7575
7576         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7577                 /* the chip adds 2 halflines automatically */
7578                 crtc_vtotal -= 1;
7579                 crtc_vblank_end -= 1;
7580
7581                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7582                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7583                 else
7584                         vsyncshift = adjusted_mode->crtc_hsync_start -
7585                                 adjusted_mode->crtc_htotal / 2;
7586                 if (vsyncshift < 0)
7587                         vsyncshift += adjusted_mode->crtc_htotal;
7588         }
7589
7590         if (INTEL_INFO(dev)->gen > 3)
7591                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7592
7593         I915_WRITE(HTOTAL(cpu_transcoder),
7594                    (adjusted_mode->crtc_hdisplay - 1) |
7595                    ((adjusted_mode->crtc_htotal - 1) << 16));
7596         I915_WRITE(HBLANK(cpu_transcoder),
7597                    (adjusted_mode->crtc_hblank_start - 1) |
7598                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7599         I915_WRITE(HSYNC(cpu_transcoder),
7600                    (adjusted_mode->crtc_hsync_start - 1) |
7601                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7602
7603         I915_WRITE(VTOTAL(cpu_transcoder),
7604                    (adjusted_mode->crtc_vdisplay - 1) |
7605                    ((crtc_vtotal - 1) << 16));
7606         I915_WRITE(VBLANK(cpu_transcoder),
7607                    (adjusted_mode->crtc_vblank_start - 1) |
7608                    ((crtc_vblank_end - 1) << 16));
7609         I915_WRITE(VSYNC(cpu_transcoder),
7610                    (adjusted_mode->crtc_vsync_start - 1) |
7611                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7612
7613         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7614          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7615          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7616          * bits. */
7617         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7618             (pipe == PIPE_B || pipe == PIPE_C))
7619                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7620
7621 }
7622
7623 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7624 {
7625         struct drm_device *dev = intel_crtc->base.dev;
7626         struct drm_i915_private *dev_priv = dev->dev_private;
7627         enum pipe pipe = intel_crtc->pipe;
7628
7629         /* pipesrc controls the size that is scaled from, which should
7630          * always be the user's requested size.
7631          */
7632         I915_WRITE(PIPESRC(pipe),
7633                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7634                    (intel_crtc->config->pipe_src_h - 1));
7635 }
7636
7637 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7638                                    struct intel_crtc_state *pipe_config)
7639 {
7640         struct drm_device *dev = crtc->base.dev;
7641         struct drm_i915_private *dev_priv = dev->dev_private;
7642         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7643         uint32_t tmp;
7644
7645         tmp = I915_READ(HTOTAL(cpu_transcoder));
7646         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7647         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7648         tmp = I915_READ(HBLANK(cpu_transcoder));
7649         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7650         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7651         tmp = I915_READ(HSYNC(cpu_transcoder));
7652         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7653         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7654
7655         tmp = I915_READ(VTOTAL(cpu_transcoder));
7656         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7657         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7658         tmp = I915_READ(VBLANK(cpu_transcoder));
7659         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7660         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7661         tmp = I915_READ(VSYNC(cpu_transcoder));
7662         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7663         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7664
7665         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7666                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7667                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7668                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7669         }
7670 }
7671
7672 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7673                                     struct intel_crtc_state *pipe_config)
7674 {
7675         struct drm_device *dev = crtc->base.dev;
7676         struct drm_i915_private *dev_priv = dev->dev_private;
7677         u32 tmp;
7678
7679         tmp = I915_READ(PIPESRC(crtc->pipe));
7680         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7681         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7682
7683         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7684         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7685 }
7686
7687 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7688                                  struct intel_crtc_state *pipe_config)
7689 {
7690         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7691         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7692         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7693         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7694
7695         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7696         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7697         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7698         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7699
7700         mode->flags = pipe_config->base.adjusted_mode.flags;
7701         mode->type = DRM_MODE_TYPE_DRIVER;
7702
7703         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7704         mode->flags |= pipe_config->base.adjusted_mode.flags;
7705
7706         mode->hsync = drm_mode_hsync(mode);
7707         mode->vrefresh = drm_mode_vrefresh(mode);
7708         drm_mode_set_name(mode);
7709 }
7710
7711 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7712 {
7713         struct drm_device *dev = intel_crtc->base.dev;
7714         struct drm_i915_private *dev_priv = dev->dev_private;
7715         uint32_t pipeconf;
7716
7717         pipeconf = 0;
7718
7719         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7720             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7721                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7722
7723         if (intel_crtc->config->double_wide)
7724                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7725
7726         /* only g4x and later have fancy bpc/dither controls */
7727         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7728                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7729                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7730                         pipeconf |= PIPECONF_DITHER_EN |
7731                                     PIPECONF_DITHER_TYPE_SP;
7732
7733                 switch (intel_crtc->config->pipe_bpp) {
7734                 case 18:
7735                         pipeconf |= PIPECONF_6BPC;
7736                         break;
7737                 case 24:
7738                         pipeconf |= PIPECONF_8BPC;
7739                         break;
7740                 case 30:
7741                         pipeconf |= PIPECONF_10BPC;
7742                         break;
7743                 default:
7744                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7745                         BUG();
7746                 }
7747         }
7748
7749         if (HAS_PIPE_CXSR(dev)) {
7750                 if (intel_crtc->lowfreq_avail) {
7751                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7752                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7753                 } else {
7754                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7755                 }
7756         }
7757
7758         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7759                 if (INTEL_INFO(dev)->gen < 4 ||
7760                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7761                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7762                 else
7763                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7764         } else
7765                 pipeconf |= PIPECONF_PROGRESSIVE;
7766
7767         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7768              intel_crtc->config->limited_color_range)
7769                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7770
7771         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7772         POSTING_READ(PIPECONF(intel_crtc->pipe));
7773 }
7774
7775 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7776                                    struct intel_crtc_state *crtc_state)
7777 {
7778         struct drm_device *dev = crtc->base.dev;
7779         struct drm_i915_private *dev_priv = dev->dev_private;
7780         const intel_limit_t *limit;
7781         int refclk = 48000;
7782
7783         memset(&crtc_state->dpll_hw_state, 0,
7784                sizeof(crtc_state->dpll_hw_state));
7785
7786         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7787                 if (intel_panel_use_ssc(dev_priv)) {
7788                         refclk = dev_priv->vbt.lvds_ssc_freq;
7789                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7790                 }
7791
7792                 limit = &intel_limits_i8xx_lvds;
7793         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7794                 limit = &intel_limits_i8xx_dvo;
7795         } else {
7796                 limit = &intel_limits_i8xx_dac;
7797         }
7798
7799         if (!crtc_state->clock_set &&
7800             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7801                                  refclk, NULL, &crtc_state->dpll)) {
7802                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7803                 return -EINVAL;
7804         }
7805
7806         i8xx_compute_dpll(crtc, crtc_state, NULL);
7807
7808         return 0;
7809 }
7810
7811 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7812                                   struct intel_crtc_state *crtc_state)
7813 {
7814         struct drm_device *dev = crtc->base.dev;
7815         struct drm_i915_private *dev_priv = dev->dev_private;
7816         const intel_limit_t *limit;
7817         int refclk = 96000;
7818
7819         memset(&crtc_state->dpll_hw_state, 0,
7820                sizeof(crtc_state->dpll_hw_state));
7821
7822         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7823                 if (intel_panel_use_ssc(dev_priv)) {
7824                         refclk = dev_priv->vbt.lvds_ssc_freq;
7825                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7826                 }
7827
7828                 if (intel_is_dual_link_lvds(dev))
7829                         limit = &intel_limits_g4x_dual_channel_lvds;
7830                 else
7831                         limit = &intel_limits_g4x_single_channel_lvds;
7832         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7833                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7834                 limit = &intel_limits_g4x_hdmi;
7835         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7836                 limit = &intel_limits_g4x_sdvo;
7837         } else {
7838                 /* The option is for other outputs */
7839                 limit = &intel_limits_i9xx_sdvo;
7840         }
7841
7842         if (!crtc_state->clock_set &&
7843             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7844                                 refclk, NULL, &crtc_state->dpll)) {
7845                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7846                 return -EINVAL;
7847         }
7848
7849         i9xx_compute_dpll(crtc, crtc_state, NULL);
7850
7851         return 0;
7852 }
7853
7854 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7855                                   struct intel_crtc_state *crtc_state)
7856 {
7857         struct drm_device *dev = crtc->base.dev;
7858         struct drm_i915_private *dev_priv = dev->dev_private;
7859         const intel_limit_t *limit;
7860         int refclk = 96000;
7861
7862         memset(&crtc_state->dpll_hw_state, 0,
7863                sizeof(crtc_state->dpll_hw_state));
7864
7865         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7866                 if (intel_panel_use_ssc(dev_priv)) {
7867                         refclk = dev_priv->vbt.lvds_ssc_freq;
7868                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7869                 }
7870
7871                 limit = &intel_limits_pineview_lvds;
7872         } else {
7873                 limit = &intel_limits_pineview_sdvo;
7874         }
7875
7876         if (!crtc_state->clock_set &&
7877             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7878                                 refclk, NULL, &crtc_state->dpll)) {
7879                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7880                 return -EINVAL;
7881         }
7882
7883         i9xx_compute_dpll(crtc, crtc_state, NULL);
7884
7885         return 0;
7886 }
7887
7888 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7889                                    struct intel_crtc_state *crtc_state)
7890 {
7891         struct drm_device *dev = crtc->base.dev;
7892         struct drm_i915_private *dev_priv = dev->dev_private;
7893         const intel_limit_t *limit;
7894         int refclk = 96000;
7895
7896         memset(&crtc_state->dpll_hw_state, 0,
7897                sizeof(crtc_state->dpll_hw_state));
7898
7899         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7900                 if (intel_panel_use_ssc(dev_priv)) {
7901                         refclk = dev_priv->vbt.lvds_ssc_freq;
7902                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7903                 }
7904
7905                 limit = &intel_limits_i9xx_lvds;
7906         } else {
7907                 limit = &intel_limits_i9xx_sdvo;
7908         }
7909
7910         if (!crtc_state->clock_set &&
7911             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7912                                  refclk, NULL, &crtc_state->dpll)) {
7913                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7914                 return -EINVAL;
7915         }
7916
7917         i9xx_compute_dpll(crtc, crtc_state, NULL);
7918
7919         return 0;
7920 }
7921
7922 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7923                                   struct intel_crtc_state *crtc_state)
7924 {
7925         int refclk = 100000;
7926         const intel_limit_t *limit = &intel_limits_chv;
7927
7928         memset(&crtc_state->dpll_hw_state, 0,
7929                sizeof(crtc_state->dpll_hw_state));
7930
7931         if (crtc_state->has_dsi_encoder)
7932                 return 0;
7933
7934         if (!crtc_state->clock_set &&
7935             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7936                                 refclk, NULL, &crtc_state->dpll)) {
7937                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7938                 return -EINVAL;
7939         }
7940
7941         chv_compute_dpll(crtc, crtc_state);
7942
7943         return 0;
7944 }
7945
7946 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7947                                   struct intel_crtc_state *crtc_state)
7948 {
7949         int refclk = 100000;
7950         const intel_limit_t *limit = &intel_limits_vlv;
7951
7952         memset(&crtc_state->dpll_hw_state, 0,
7953                sizeof(crtc_state->dpll_hw_state));
7954
7955         if (crtc_state->has_dsi_encoder)
7956                 return 0;
7957
7958         if (!crtc_state->clock_set &&
7959             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7960                                 refclk, NULL, &crtc_state->dpll)) {
7961                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7962                 return -EINVAL;
7963         }
7964
7965         vlv_compute_dpll(crtc, crtc_state);
7966
7967         return 0;
7968 }
7969
7970 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7971                                  struct intel_crtc_state *pipe_config)
7972 {
7973         struct drm_device *dev = crtc->base.dev;
7974         struct drm_i915_private *dev_priv = dev->dev_private;
7975         uint32_t tmp;
7976
7977         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7978                 return;
7979
7980         tmp = I915_READ(PFIT_CONTROL);
7981         if (!(tmp & PFIT_ENABLE))
7982                 return;
7983
7984         /* Check whether the pfit is attached to our pipe. */
7985         if (INTEL_INFO(dev)->gen < 4) {
7986                 if (crtc->pipe != PIPE_B)
7987                         return;
7988         } else {
7989                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7990                         return;
7991         }
7992
7993         pipe_config->gmch_pfit.control = tmp;
7994         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7995         if (INTEL_INFO(dev)->gen < 5)
7996                 pipe_config->gmch_pfit.lvds_border_bits =
7997                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7998 }
7999
8000 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8001                                struct intel_crtc_state *pipe_config)
8002 {
8003         struct drm_device *dev = crtc->base.dev;
8004         struct drm_i915_private *dev_priv = dev->dev_private;
8005         int pipe = pipe_config->cpu_transcoder;
8006         intel_clock_t clock;
8007         u32 mdiv;
8008         int refclk = 100000;
8009
8010         /* In case of DSI, DPLL will not be used */
8011         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8012                 return;
8013
8014         mutex_lock(&dev_priv->sb_lock);
8015         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8016         mutex_unlock(&dev_priv->sb_lock);
8017
8018         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8019         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8020         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8021         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8022         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8023
8024         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8025 }
8026
8027 static void
8028 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8029                               struct intel_initial_plane_config *plane_config)
8030 {
8031         struct drm_device *dev = crtc->base.dev;
8032         struct drm_i915_private *dev_priv = dev->dev_private;
8033         u32 val, base, offset;
8034         int pipe = crtc->pipe, plane = crtc->plane;
8035         int fourcc, pixel_format;
8036         unsigned int aligned_height;
8037         struct drm_framebuffer *fb;
8038         struct intel_framebuffer *intel_fb;
8039
8040         val = I915_READ(DSPCNTR(plane));
8041         if (!(val & DISPLAY_PLANE_ENABLE))
8042                 return;
8043
8044         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8045         if (!intel_fb) {
8046                 DRM_DEBUG_KMS("failed to alloc fb\n");
8047                 return;
8048         }
8049
8050         fb = &intel_fb->base;
8051
8052         if (INTEL_INFO(dev)->gen >= 4) {
8053                 if (val & DISPPLANE_TILED) {
8054                         plane_config->tiling = I915_TILING_X;
8055                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8056                 }
8057         }
8058
8059         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8060         fourcc = i9xx_format_to_fourcc(pixel_format);
8061         fb->pixel_format = fourcc;
8062         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8063
8064         if (INTEL_INFO(dev)->gen >= 4) {
8065                 if (plane_config->tiling)
8066                         offset = I915_READ(DSPTILEOFF(plane));
8067                 else
8068                         offset = I915_READ(DSPLINOFF(plane));
8069                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8070         } else {
8071                 base = I915_READ(DSPADDR(plane));
8072         }
8073         plane_config->base = base;
8074
8075         val = I915_READ(PIPESRC(pipe));
8076         fb->width = ((val >> 16) & 0xfff) + 1;
8077         fb->height = ((val >> 0) & 0xfff) + 1;
8078
8079         val = I915_READ(DSPSTRIDE(pipe));
8080         fb->pitches[0] = val & 0xffffffc0;
8081
8082         aligned_height = intel_fb_align_height(dev, fb->height,
8083                                                fb->pixel_format,
8084                                                fb->modifier[0]);
8085
8086         plane_config->size = fb->pitches[0] * aligned_height;
8087
8088         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8089                       pipe_name(pipe), plane, fb->width, fb->height,
8090                       fb->bits_per_pixel, base, fb->pitches[0],
8091                       plane_config->size);
8092
8093         plane_config->fb = intel_fb;
8094 }
8095
8096 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8097                                struct intel_crtc_state *pipe_config)
8098 {
8099         struct drm_device *dev = crtc->base.dev;
8100         struct drm_i915_private *dev_priv = dev->dev_private;
8101         int pipe = pipe_config->cpu_transcoder;
8102         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8103         intel_clock_t clock;
8104         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8105         int refclk = 100000;
8106
8107         /* In case of DSI, DPLL will not be used */
8108         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8109                 return;
8110
8111         mutex_lock(&dev_priv->sb_lock);
8112         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8113         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8114         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8115         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8116         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8117         mutex_unlock(&dev_priv->sb_lock);
8118
8119         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8120         clock.m2 = (pll_dw0 & 0xff) << 22;
8121         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8122                 clock.m2 |= pll_dw2 & 0x3fffff;
8123         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8124         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8125         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8126
8127         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8128 }
8129
8130 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8131                                  struct intel_crtc_state *pipe_config)
8132 {
8133         struct drm_device *dev = crtc->base.dev;
8134         struct drm_i915_private *dev_priv = dev->dev_private;
8135         enum intel_display_power_domain power_domain;
8136         uint32_t tmp;
8137         bool ret;
8138
8139         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8140         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8141                 return false;
8142
8143         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8144         pipe_config->shared_dpll = NULL;
8145
8146         ret = false;
8147
8148         tmp = I915_READ(PIPECONF(crtc->pipe));
8149         if (!(tmp & PIPECONF_ENABLE))
8150                 goto out;
8151
8152         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8153                 switch (tmp & PIPECONF_BPC_MASK) {
8154                 case PIPECONF_6BPC:
8155                         pipe_config->pipe_bpp = 18;
8156                         break;
8157                 case PIPECONF_8BPC:
8158                         pipe_config->pipe_bpp = 24;
8159                         break;
8160                 case PIPECONF_10BPC:
8161                         pipe_config->pipe_bpp = 30;
8162                         break;
8163                 default:
8164                         break;
8165                 }
8166         }
8167
8168         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8169             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8170                 pipe_config->limited_color_range = true;
8171
8172         if (INTEL_INFO(dev)->gen < 4)
8173                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8174
8175         intel_get_pipe_timings(crtc, pipe_config);
8176         intel_get_pipe_src_size(crtc, pipe_config);
8177
8178         i9xx_get_pfit_config(crtc, pipe_config);
8179
8180         if (INTEL_INFO(dev)->gen >= 4) {
8181                 /* No way to read it out on pipes B and C */
8182                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8183                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8184                 else
8185                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8186                 pipe_config->pixel_multiplier =
8187                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8188                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8189                 pipe_config->dpll_hw_state.dpll_md = tmp;
8190         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8191                 tmp = I915_READ(DPLL(crtc->pipe));
8192                 pipe_config->pixel_multiplier =
8193                         ((tmp & SDVO_MULTIPLIER_MASK)
8194                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8195         } else {
8196                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8197                  * port and will be fixed up in the encoder->get_config
8198                  * function. */
8199                 pipe_config->pixel_multiplier = 1;
8200         }
8201         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8202         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8203                 /*
8204                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8205                  * on 830. Filter it out here so that we don't
8206                  * report errors due to that.
8207                  */
8208                 if (IS_I830(dev))
8209                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8210
8211                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8212                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8213         } else {
8214                 /* Mask out read-only status bits. */
8215                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8216                                                      DPLL_PORTC_READY_MASK |
8217                                                      DPLL_PORTB_READY_MASK);
8218         }
8219
8220         if (IS_CHERRYVIEW(dev))
8221                 chv_crtc_clock_get(crtc, pipe_config);
8222         else if (IS_VALLEYVIEW(dev))
8223                 vlv_crtc_clock_get(crtc, pipe_config);
8224         else
8225                 i9xx_crtc_clock_get(crtc, pipe_config);
8226
8227         /*
8228          * Normally the dotclock is filled in by the encoder .get_config()
8229          * but in case the pipe is enabled w/o any ports we need a sane
8230          * default.
8231          */
8232         pipe_config->base.adjusted_mode.crtc_clock =
8233                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8234
8235         ret = true;
8236
8237 out:
8238         intel_display_power_put(dev_priv, power_domain);
8239
8240         return ret;
8241 }
8242
8243 static void ironlake_init_pch_refclk(struct drm_device *dev)
8244 {
8245         struct drm_i915_private *dev_priv = dev->dev_private;
8246         struct intel_encoder *encoder;
8247         u32 val, final;
8248         bool has_lvds = false;
8249         bool has_cpu_edp = false;
8250         bool has_panel = false;
8251         bool has_ck505 = false;
8252         bool can_ssc = false;
8253
8254         /* We need to take the global config into account */
8255         for_each_intel_encoder(dev, encoder) {
8256                 switch (encoder->type) {
8257                 case INTEL_OUTPUT_LVDS:
8258                         has_panel = true;
8259                         has_lvds = true;
8260                         break;
8261                 case INTEL_OUTPUT_EDP:
8262                         has_panel = true;
8263                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8264                                 has_cpu_edp = true;
8265                         break;
8266                 default:
8267                         break;
8268                 }
8269         }
8270
8271         if (HAS_PCH_IBX(dev)) {
8272                 has_ck505 = dev_priv->vbt.display_clock_mode;
8273                 can_ssc = has_ck505;
8274         } else {
8275                 has_ck505 = false;
8276                 can_ssc = true;
8277         }
8278
8279         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8280                       has_panel, has_lvds, has_ck505);
8281
8282         /* Ironlake: try to setup display ref clock before DPLL
8283          * enabling. This is only under driver's control after
8284          * PCH B stepping, previous chipset stepping should be
8285          * ignoring this setting.
8286          */
8287         val = I915_READ(PCH_DREF_CONTROL);
8288
8289         /* As we must carefully and slowly disable/enable each source in turn,
8290          * compute the final state we want first and check if we need to
8291          * make any changes at all.
8292          */
8293         final = val;
8294         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8295         if (has_ck505)
8296                 final |= DREF_NONSPREAD_CK505_ENABLE;
8297         else
8298                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8299
8300         final &= ~DREF_SSC_SOURCE_MASK;
8301         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8302         final &= ~DREF_SSC1_ENABLE;
8303
8304         if (has_panel) {
8305                 final |= DREF_SSC_SOURCE_ENABLE;
8306
8307                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8308                         final |= DREF_SSC1_ENABLE;
8309
8310                 if (has_cpu_edp) {
8311                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8312                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8313                         else
8314                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8315                 } else
8316                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8317         } else {
8318                 final |= DREF_SSC_SOURCE_DISABLE;
8319                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8320         }
8321
8322         if (final == val)
8323                 return;
8324
8325         /* Always enable nonspread source */
8326         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8327
8328         if (has_ck505)
8329                 val |= DREF_NONSPREAD_CK505_ENABLE;
8330         else
8331                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8332
8333         if (has_panel) {
8334                 val &= ~DREF_SSC_SOURCE_MASK;
8335                 val |= DREF_SSC_SOURCE_ENABLE;
8336
8337                 /* SSC must be turned on before enabling the CPU output  */
8338                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8339                         DRM_DEBUG_KMS("Using SSC on panel\n");
8340                         val |= DREF_SSC1_ENABLE;
8341                 } else
8342                         val &= ~DREF_SSC1_ENABLE;
8343
8344                 /* Get SSC going before enabling the outputs */
8345                 I915_WRITE(PCH_DREF_CONTROL, val);
8346                 POSTING_READ(PCH_DREF_CONTROL);
8347                 udelay(200);
8348
8349                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8350
8351                 /* Enable CPU source on CPU attached eDP */
8352                 if (has_cpu_edp) {
8353                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8354                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8355                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8356                         } else
8357                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8358                 } else
8359                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8360
8361                 I915_WRITE(PCH_DREF_CONTROL, val);
8362                 POSTING_READ(PCH_DREF_CONTROL);
8363                 udelay(200);
8364         } else {
8365                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8366
8367                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8368
8369                 /* Turn off CPU output */
8370                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8371
8372                 I915_WRITE(PCH_DREF_CONTROL, val);
8373                 POSTING_READ(PCH_DREF_CONTROL);
8374                 udelay(200);
8375
8376                 /* Turn off the SSC source */
8377                 val &= ~DREF_SSC_SOURCE_MASK;
8378                 val |= DREF_SSC_SOURCE_DISABLE;
8379
8380                 /* Turn off SSC1 */
8381                 val &= ~DREF_SSC1_ENABLE;
8382
8383                 I915_WRITE(PCH_DREF_CONTROL, val);
8384                 POSTING_READ(PCH_DREF_CONTROL);
8385                 udelay(200);
8386         }
8387
8388         BUG_ON(val != final);
8389 }
8390
8391 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8392 {
8393         uint32_t tmp;
8394
8395         tmp = I915_READ(SOUTH_CHICKEN2);
8396         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8397         I915_WRITE(SOUTH_CHICKEN2, tmp);
8398
8399         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8400                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8401                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8402
8403         tmp = I915_READ(SOUTH_CHICKEN2);
8404         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8405         I915_WRITE(SOUTH_CHICKEN2, tmp);
8406
8407         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8408                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8409                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8410 }
8411
8412 /* WaMPhyProgramming:hsw */
8413 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8414 {
8415         uint32_t tmp;
8416
8417         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8418         tmp &= ~(0xFF << 24);
8419         tmp |= (0x12 << 24);
8420         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8421
8422         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8423         tmp |= (1 << 11);
8424         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8425
8426         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8427         tmp |= (1 << 11);
8428         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8429
8430         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8431         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8432         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8433
8434         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8435         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8436         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8439         tmp &= ~(7 << 13);
8440         tmp |= (5 << 13);
8441         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8442
8443         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8444         tmp &= ~(7 << 13);
8445         tmp |= (5 << 13);
8446         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8447
8448         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8449         tmp &= ~0xFF;
8450         tmp |= 0x1C;
8451         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8452
8453         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8454         tmp &= ~0xFF;
8455         tmp |= 0x1C;
8456         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8457
8458         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8459         tmp &= ~(0xFF << 16);
8460         tmp |= (0x1C << 16);
8461         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8462
8463         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8464         tmp &= ~(0xFF << 16);
8465         tmp |= (0x1C << 16);
8466         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8467
8468         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8469         tmp |= (1 << 27);
8470         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8471
8472         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8473         tmp |= (1 << 27);
8474         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8475
8476         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8477         tmp &= ~(0xF << 28);
8478         tmp |= (4 << 28);
8479         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8480
8481         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8482         tmp &= ~(0xF << 28);
8483         tmp |= (4 << 28);
8484         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8485 }
8486
8487 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8488  * Programming" based on the parameters passed:
8489  * - Sequence to enable CLKOUT_DP
8490  * - Sequence to enable CLKOUT_DP without spread
8491  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8492  */
8493 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8494                                  bool with_fdi)
8495 {
8496         struct drm_i915_private *dev_priv = dev->dev_private;
8497         uint32_t reg, tmp;
8498
8499         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8500                 with_spread = true;
8501         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8502                 with_fdi = false;
8503
8504         mutex_lock(&dev_priv->sb_lock);
8505
8506         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8507         tmp &= ~SBI_SSCCTL_DISABLE;
8508         tmp |= SBI_SSCCTL_PATHALT;
8509         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8510
8511         udelay(24);
8512
8513         if (with_spread) {
8514                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515                 tmp &= ~SBI_SSCCTL_PATHALT;
8516                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8517
8518                 if (with_fdi) {
8519                         lpt_reset_fdi_mphy(dev_priv);
8520                         lpt_program_fdi_mphy(dev_priv);
8521                 }
8522         }
8523
8524         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8525         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8526         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8527         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8528
8529         mutex_unlock(&dev_priv->sb_lock);
8530 }
8531
8532 /* Sequence to disable CLKOUT_DP */
8533 static void lpt_disable_clkout_dp(struct drm_device *dev)
8534 {
8535         struct drm_i915_private *dev_priv = dev->dev_private;
8536         uint32_t reg, tmp;
8537
8538         mutex_lock(&dev_priv->sb_lock);
8539
8540         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8541         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8542         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8543         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8544
8545         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8546         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8547                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8548                         tmp |= SBI_SSCCTL_PATHALT;
8549                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8550                         udelay(32);
8551                 }
8552                 tmp |= SBI_SSCCTL_DISABLE;
8553                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8554         }
8555
8556         mutex_unlock(&dev_priv->sb_lock);
8557 }
8558
8559 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8560
8561 static const uint16_t sscdivintphase[] = {
8562         [BEND_IDX( 50)] = 0x3B23,
8563         [BEND_IDX( 45)] = 0x3B23,
8564         [BEND_IDX( 40)] = 0x3C23,
8565         [BEND_IDX( 35)] = 0x3C23,
8566         [BEND_IDX( 30)] = 0x3D23,
8567         [BEND_IDX( 25)] = 0x3D23,
8568         [BEND_IDX( 20)] = 0x3E23,
8569         [BEND_IDX( 15)] = 0x3E23,
8570         [BEND_IDX( 10)] = 0x3F23,
8571         [BEND_IDX(  5)] = 0x3F23,
8572         [BEND_IDX(  0)] = 0x0025,
8573         [BEND_IDX( -5)] = 0x0025,
8574         [BEND_IDX(-10)] = 0x0125,
8575         [BEND_IDX(-15)] = 0x0125,
8576         [BEND_IDX(-20)] = 0x0225,
8577         [BEND_IDX(-25)] = 0x0225,
8578         [BEND_IDX(-30)] = 0x0325,
8579         [BEND_IDX(-35)] = 0x0325,
8580         [BEND_IDX(-40)] = 0x0425,
8581         [BEND_IDX(-45)] = 0x0425,
8582         [BEND_IDX(-50)] = 0x0525,
8583 };
8584
8585 /*
8586  * Bend CLKOUT_DP
8587  * steps -50 to 50 inclusive, in steps of 5
8588  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8589  * change in clock period = -(steps / 10) * 5.787 ps
8590  */
8591 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8592 {
8593         uint32_t tmp;
8594         int idx = BEND_IDX(steps);
8595
8596         if (WARN_ON(steps % 5 != 0))
8597                 return;
8598
8599         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8600                 return;
8601
8602         mutex_lock(&dev_priv->sb_lock);
8603
8604         if (steps % 10 != 0)
8605                 tmp = 0xAAAAAAAB;
8606         else
8607                 tmp = 0x00000000;
8608         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8609
8610         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8611         tmp &= 0xffff0000;
8612         tmp |= sscdivintphase[idx];
8613         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8614
8615         mutex_unlock(&dev_priv->sb_lock);
8616 }
8617
8618 #undef BEND_IDX
8619
8620 static void lpt_init_pch_refclk(struct drm_device *dev)
8621 {
8622         struct intel_encoder *encoder;
8623         bool has_vga = false;
8624
8625         for_each_intel_encoder(dev, encoder) {
8626                 switch (encoder->type) {
8627                 case INTEL_OUTPUT_ANALOG:
8628                         has_vga = true;
8629                         break;
8630                 default:
8631                         break;
8632                 }
8633         }
8634
8635         if (has_vga) {
8636                 lpt_bend_clkout_dp(to_i915(dev), 0);
8637                 lpt_enable_clkout_dp(dev, true, true);
8638         } else {
8639                 lpt_disable_clkout_dp(dev);
8640         }
8641 }
8642
8643 /*
8644  * Initialize reference clocks when the driver loads
8645  */
8646 void intel_init_pch_refclk(struct drm_device *dev)
8647 {
8648         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8649                 ironlake_init_pch_refclk(dev);
8650         else if (HAS_PCH_LPT(dev))
8651                 lpt_init_pch_refclk(dev);
8652 }
8653
8654 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8655 {
8656         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8658         int pipe = intel_crtc->pipe;
8659         uint32_t val;
8660
8661         val = 0;
8662
8663         switch (intel_crtc->config->pipe_bpp) {
8664         case 18:
8665                 val |= PIPECONF_6BPC;
8666                 break;
8667         case 24:
8668                 val |= PIPECONF_8BPC;
8669                 break;
8670         case 30:
8671                 val |= PIPECONF_10BPC;
8672                 break;
8673         case 36:
8674                 val |= PIPECONF_12BPC;
8675                 break;
8676         default:
8677                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8678                 BUG();
8679         }
8680
8681         if (intel_crtc->config->dither)
8682                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8683
8684         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8685                 val |= PIPECONF_INTERLACED_ILK;
8686         else
8687                 val |= PIPECONF_PROGRESSIVE;
8688
8689         if (intel_crtc->config->limited_color_range)
8690                 val |= PIPECONF_COLOR_RANGE_SELECT;
8691
8692         I915_WRITE(PIPECONF(pipe), val);
8693         POSTING_READ(PIPECONF(pipe));
8694 }
8695
8696 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8697 {
8698         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8700         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8701         u32 val = 0;
8702
8703         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8704                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8705
8706         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8707                 val |= PIPECONF_INTERLACED_ILK;
8708         else
8709                 val |= PIPECONF_PROGRESSIVE;
8710
8711         I915_WRITE(PIPECONF(cpu_transcoder), val);
8712         POSTING_READ(PIPECONF(cpu_transcoder));
8713 }
8714
8715 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8716 {
8717         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8719
8720         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8721                 u32 val = 0;
8722
8723                 switch (intel_crtc->config->pipe_bpp) {
8724                 case 18:
8725                         val |= PIPEMISC_DITHER_6_BPC;
8726                         break;
8727                 case 24:
8728                         val |= PIPEMISC_DITHER_8_BPC;
8729                         break;
8730                 case 30:
8731                         val |= PIPEMISC_DITHER_10_BPC;
8732                         break;
8733                 case 36:
8734                         val |= PIPEMISC_DITHER_12_BPC;
8735                         break;
8736                 default:
8737                         /* Case prevented by pipe_config_set_bpp. */
8738                         BUG();
8739                 }
8740
8741                 if (intel_crtc->config->dither)
8742                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8743
8744                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8745         }
8746 }
8747
8748 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8749 {
8750         /*
8751          * Account for spread spectrum to avoid
8752          * oversubscribing the link. Max center spread
8753          * is 2.5%; use 5% for safety's sake.
8754          */
8755         u32 bps = target_clock * bpp * 21 / 20;
8756         return DIV_ROUND_UP(bps, link_bw * 8);
8757 }
8758
8759 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8760 {
8761         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8762 }
8763
8764 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8765                                   struct intel_crtc_state *crtc_state,
8766                                   intel_clock_t *reduced_clock)
8767 {
8768         struct drm_crtc *crtc = &intel_crtc->base;
8769         struct drm_device *dev = crtc->dev;
8770         struct drm_i915_private *dev_priv = dev->dev_private;
8771         struct drm_atomic_state *state = crtc_state->base.state;
8772         struct drm_connector *connector;
8773         struct drm_connector_state *connector_state;
8774         struct intel_encoder *encoder;
8775         u32 dpll, fp, fp2;
8776         int factor, i;
8777         bool is_lvds = false, is_sdvo = false;
8778
8779         for_each_connector_in_state(state, connector, connector_state, i) {
8780                 if (connector_state->crtc != crtc_state->base.crtc)
8781                         continue;
8782
8783                 encoder = to_intel_encoder(connector_state->best_encoder);
8784
8785                 switch (encoder->type) {
8786                 case INTEL_OUTPUT_LVDS:
8787                         is_lvds = true;
8788                         break;
8789                 case INTEL_OUTPUT_SDVO:
8790                 case INTEL_OUTPUT_HDMI:
8791                         is_sdvo = true;
8792                         break;
8793                 default:
8794                         break;
8795                 }
8796         }
8797
8798         /* Enable autotuning of the PLL clock (if permissible) */
8799         factor = 21;
8800         if (is_lvds) {
8801                 if ((intel_panel_use_ssc(dev_priv) &&
8802                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8803                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8804                         factor = 25;
8805         } else if (crtc_state->sdvo_tv_clock)
8806                 factor = 20;
8807
8808         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8809
8810         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8811                 fp |= FP_CB_TUNE;
8812
8813         if (reduced_clock) {
8814                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8815
8816                 if (reduced_clock->m < factor * reduced_clock->n)
8817                         fp2 |= FP_CB_TUNE;
8818         } else {
8819                 fp2 = fp;
8820         }
8821
8822         dpll = 0;
8823
8824         if (is_lvds)
8825                 dpll |= DPLLB_MODE_LVDS;
8826         else
8827                 dpll |= DPLLB_MODE_DAC_SERIAL;
8828
8829         dpll |= (crtc_state->pixel_multiplier - 1)
8830                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8831
8832         if (is_sdvo)
8833                 dpll |= DPLL_SDVO_HIGH_SPEED;
8834         if (crtc_state->has_dp_encoder)
8835                 dpll |= DPLL_SDVO_HIGH_SPEED;
8836
8837         /* compute bitmask from p1 value */
8838         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8839         /* also FPA1 */
8840         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8841
8842         switch (crtc_state->dpll.p2) {
8843         case 5:
8844                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8845                 break;
8846         case 7:
8847                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8848                 break;
8849         case 10:
8850                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8851                 break;
8852         case 14:
8853                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8854                 break;
8855         }
8856
8857         if (is_lvds && intel_panel_use_ssc(dev_priv))
8858                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8859         else
8860                 dpll |= PLL_REF_INPUT_DREFCLK;
8861
8862         dpll |= DPLL_VCO_ENABLE;
8863
8864         crtc_state->dpll_hw_state.dpll = dpll;
8865         crtc_state->dpll_hw_state.fp0 = fp;
8866         crtc_state->dpll_hw_state.fp1 = fp2;
8867 }
8868
8869 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8870                                        struct intel_crtc_state *crtc_state)
8871 {
8872         struct drm_device *dev = crtc->base.dev;
8873         struct drm_i915_private *dev_priv = dev->dev_private;
8874         intel_clock_t reduced_clock;
8875         bool has_reduced_clock = false;
8876         struct intel_shared_dpll *pll;
8877         const intel_limit_t *limit;
8878         int refclk = 120000;
8879
8880         memset(&crtc_state->dpll_hw_state, 0,
8881                sizeof(crtc_state->dpll_hw_state));
8882
8883         crtc->lowfreq_avail = false;
8884
8885         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8886         if (!crtc_state->has_pch_encoder)
8887                 return 0;
8888
8889         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8890                 if (intel_panel_use_ssc(dev_priv)) {
8891                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8892                                       dev_priv->vbt.lvds_ssc_freq);
8893                         refclk = dev_priv->vbt.lvds_ssc_freq;
8894                 }
8895
8896                 if (intel_is_dual_link_lvds(dev)) {
8897                         if (refclk == 100000)
8898                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8899                         else
8900                                 limit = &intel_limits_ironlake_dual_lvds;
8901                 } else {
8902                         if (refclk == 100000)
8903                                 limit = &intel_limits_ironlake_single_lvds_100m;
8904                         else
8905                                 limit = &intel_limits_ironlake_single_lvds;
8906                 }
8907         } else {
8908                 limit = &intel_limits_ironlake_dac;
8909         }
8910
8911         if (!crtc_state->clock_set &&
8912             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8913                                 refclk, NULL, &crtc_state->dpll)) {
8914                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8915                 return -EINVAL;
8916         }
8917
8918         ironlake_compute_dpll(crtc, crtc_state,
8919                               has_reduced_clock ? &reduced_clock : NULL);
8920
8921         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8922         if (pll == NULL) {
8923                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8924                                  pipe_name(crtc->pipe));
8925                 return -EINVAL;
8926         }
8927
8928         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8929             has_reduced_clock)
8930                 crtc->lowfreq_avail = true;
8931
8932         return 0;
8933 }
8934
8935 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8936                                          struct intel_link_m_n *m_n)
8937 {
8938         struct drm_device *dev = crtc->base.dev;
8939         struct drm_i915_private *dev_priv = dev->dev_private;
8940         enum pipe pipe = crtc->pipe;
8941
8942         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8943         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8944         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8945                 & ~TU_SIZE_MASK;
8946         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8947         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8948                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8949 }
8950
8951 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8952                                          enum transcoder transcoder,
8953                                          struct intel_link_m_n *m_n,
8954                                          struct intel_link_m_n *m2_n2)
8955 {
8956         struct drm_device *dev = crtc->base.dev;
8957         struct drm_i915_private *dev_priv = dev->dev_private;
8958         enum pipe pipe = crtc->pipe;
8959
8960         if (INTEL_INFO(dev)->gen >= 5) {
8961                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8962                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8963                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8964                         & ~TU_SIZE_MASK;
8965                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8966                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8967                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8968                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8969                  * gen < 8) and if DRRS is supported (to make sure the
8970                  * registers are not unnecessarily read).
8971                  */
8972                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8973                         crtc->config->has_drrs) {
8974                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8975                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8976                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8977                                         & ~TU_SIZE_MASK;
8978                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8979                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8980                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8981                 }
8982         } else {
8983                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8984                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8985                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8986                         & ~TU_SIZE_MASK;
8987                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8988                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8989                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8990         }
8991 }
8992
8993 void intel_dp_get_m_n(struct intel_crtc *crtc,
8994                       struct intel_crtc_state *pipe_config)
8995 {
8996         if (pipe_config->has_pch_encoder)
8997                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8998         else
8999                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9000                                              &pipe_config->dp_m_n,
9001                                              &pipe_config->dp_m2_n2);
9002 }
9003
9004 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9005                                         struct intel_crtc_state *pipe_config)
9006 {
9007         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9008                                      &pipe_config->fdi_m_n, NULL);
9009 }
9010
9011 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9012                                     struct intel_crtc_state *pipe_config)
9013 {
9014         struct drm_device *dev = crtc->base.dev;
9015         struct drm_i915_private *dev_priv = dev->dev_private;
9016         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9017         uint32_t ps_ctrl = 0;
9018         int id = -1;
9019         int i;
9020
9021         /* find scaler attached to this pipe */
9022         for (i = 0; i < crtc->num_scalers; i++) {
9023                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9024                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9025                         id = i;
9026                         pipe_config->pch_pfit.enabled = true;
9027                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9028                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9029                         break;
9030                 }
9031         }
9032
9033         scaler_state->scaler_id = id;
9034         if (id >= 0) {
9035                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9036         } else {
9037                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9038         }
9039 }
9040
9041 static void
9042 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9043                                  struct intel_initial_plane_config *plane_config)
9044 {
9045         struct drm_device *dev = crtc->base.dev;
9046         struct drm_i915_private *dev_priv = dev->dev_private;
9047         u32 val, base, offset, stride_mult, tiling;
9048         int pipe = crtc->pipe;
9049         int fourcc, pixel_format;
9050         unsigned int aligned_height;
9051         struct drm_framebuffer *fb;
9052         struct intel_framebuffer *intel_fb;
9053
9054         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9055         if (!intel_fb) {
9056                 DRM_DEBUG_KMS("failed to alloc fb\n");
9057                 return;
9058         }
9059
9060         fb = &intel_fb->base;
9061
9062         val = I915_READ(PLANE_CTL(pipe, 0));
9063         if (!(val & PLANE_CTL_ENABLE))
9064                 goto error;
9065
9066         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9067         fourcc = skl_format_to_fourcc(pixel_format,
9068                                       val & PLANE_CTL_ORDER_RGBX,
9069                                       val & PLANE_CTL_ALPHA_MASK);
9070         fb->pixel_format = fourcc;
9071         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9072
9073         tiling = val & PLANE_CTL_TILED_MASK;
9074         switch (tiling) {
9075         case PLANE_CTL_TILED_LINEAR:
9076                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9077                 break;
9078         case PLANE_CTL_TILED_X:
9079                 plane_config->tiling = I915_TILING_X;
9080                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9081                 break;
9082         case PLANE_CTL_TILED_Y:
9083                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9084                 break;
9085         case PLANE_CTL_TILED_YF:
9086                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9087                 break;
9088         default:
9089                 MISSING_CASE(tiling);
9090                 goto error;
9091         }
9092
9093         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9094         plane_config->base = base;
9095
9096         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9097
9098         val = I915_READ(PLANE_SIZE(pipe, 0));
9099         fb->height = ((val >> 16) & 0xfff) + 1;
9100         fb->width = ((val >> 0) & 0x1fff) + 1;
9101
9102         val = I915_READ(PLANE_STRIDE(pipe, 0));
9103         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9104                                                 fb->pixel_format);
9105         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9106
9107         aligned_height = intel_fb_align_height(dev, fb->height,
9108                                                fb->pixel_format,
9109                                                fb->modifier[0]);
9110
9111         plane_config->size = fb->pitches[0] * aligned_height;
9112
9113         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9114                       pipe_name(pipe), fb->width, fb->height,
9115                       fb->bits_per_pixel, base, fb->pitches[0],
9116                       plane_config->size);
9117
9118         plane_config->fb = intel_fb;
9119         return;
9120
9121 error:
9122         kfree(fb);
9123 }
9124
9125 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9126                                      struct intel_crtc_state *pipe_config)
9127 {
9128         struct drm_device *dev = crtc->base.dev;
9129         struct drm_i915_private *dev_priv = dev->dev_private;
9130         uint32_t tmp;
9131
9132         tmp = I915_READ(PF_CTL(crtc->pipe));
9133
9134         if (tmp & PF_ENABLE) {
9135                 pipe_config->pch_pfit.enabled = true;
9136                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9137                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9138
9139                 /* We currently do not free assignements of panel fitters on
9140                  * ivb/hsw (since we don't use the higher upscaling modes which
9141                  * differentiates them) so just WARN about this case for now. */
9142                 if (IS_GEN7(dev)) {
9143                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9144                                 PF_PIPE_SEL_IVB(crtc->pipe));
9145                 }
9146         }
9147 }
9148
9149 static void
9150 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9151                                   struct intel_initial_plane_config *plane_config)
9152 {
9153         struct drm_device *dev = crtc->base.dev;
9154         struct drm_i915_private *dev_priv = dev->dev_private;
9155         u32 val, base, offset;
9156         int pipe = crtc->pipe;
9157         int fourcc, pixel_format;
9158         unsigned int aligned_height;
9159         struct drm_framebuffer *fb;
9160         struct intel_framebuffer *intel_fb;
9161
9162         val = I915_READ(DSPCNTR(pipe));
9163         if (!(val & DISPLAY_PLANE_ENABLE))
9164                 return;
9165
9166         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9167         if (!intel_fb) {
9168                 DRM_DEBUG_KMS("failed to alloc fb\n");
9169                 return;
9170         }
9171
9172         fb = &intel_fb->base;
9173
9174         if (INTEL_INFO(dev)->gen >= 4) {
9175                 if (val & DISPPLANE_TILED) {
9176                         plane_config->tiling = I915_TILING_X;
9177                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9178                 }
9179         }
9180
9181         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9182         fourcc = i9xx_format_to_fourcc(pixel_format);
9183         fb->pixel_format = fourcc;
9184         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9185
9186         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9187         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9188                 offset = I915_READ(DSPOFFSET(pipe));
9189         } else {
9190                 if (plane_config->tiling)
9191                         offset = I915_READ(DSPTILEOFF(pipe));
9192                 else
9193                         offset = I915_READ(DSPLINOFF(pipe));
9194         }
9195         plane_config->base = base;
9196
9197         val = I915_READ(PIPESRC(pipe));
9198         fb->width = ((val >> 16) & 0xfff) + 1;
9199         fb->height = ((val >> 0) & 0xfff) + 1;
9200
9201         val = I915_READ(DSPSTRIDE(pipe));
9202         fb->pitches[0] = val & 0xffffffc0;
9203
9204         aligned_height = intel_fb_align_height(dev, fb->height,
9205                                                fb->pixel_format,
9206                                                fb->modifier[0]);
9207
9208         plane_config->size = fb->pitches[0] * aligned_height;
9209
9210         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9211                       pipe_name(pipe), fb->width, fb->height,
9212                       fb->bits_per_pixel, base, fb->pitches[0],
9213                       plane_config->size);
9214
9215         plane_config->fb = intel_fb;
9216 }
9217
9218 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9219                                      struct intel_crtc_state *pipe_config)
9220 {
9221         struct drm_device *dev = crtc->base.dev;
9222         struct drm_i915_private *dev_priv = dev->dev_private;
9223         enum intel_display_power_domain power_domain;
9224         uint32_t tmp;
9225         bool ret;
9226
9227         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9228         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9229                 return false;
9230
9231         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9232         pipe_config->shared_dpll = NULL;
9233
9234         ret = false;
9235         tmp = I915_READ(PIPECONF(crtc->pipe));
9236         if (!(tmp & PIPECONF_ENABLE))
9237                 goto out;
9238
9239         switch (tmp & PIPECONF_BPC_MASK) {
9240         case PIPECONF_6BPC:
9241                 pipe_config->pipe_bpp = 18;
9242                 break;
9243         case PIPECONF_8BPC:
9244                 pipe_config->pipe_bpp = 24;
9245                 break;
9246         case PIPECONF_10BPC:
9247                 pipe_config->pipe_bpp = 30;
9248                 break;
9249         case PIPECONF_12BPC:
9250                 pipe_config->pipe_bpp = 36;
9251                 break;
9252         default:
9253                 break;
9254         }
9255
9256         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9257                 pipe_config->limited_color_range = true;
9258
9259         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9260                 struct intel_shared_dpll *pll;
9261                 enum intel_dpll_id pll_id;
9262
9263                 pipe_config->has_pch_encoder = true;
9264
9265                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9266                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9267                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9268
9269                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9270
9271                 if (HAS_PCH_IBX(dev_priv)) {
9272                         pll_id = (enum intel_dpll_id) crtc->pipe;
9273                 } else {
9274                         tmp = I915_READ(PCH_DPLL_SEL);
9275                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9276                                 pll_id = DPLL_ID_PCH_PLL_B;
9277                         else
9278                                 pll_id= DPLL_ID_PCH_PLL_A;
9279                 }
9280
9281                 pipe_config->shared_dpll =
9282                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9283                 pll = pipe_config->shared_dpll;
9284
9285                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9286                                                  &pipe_config->dpll_hw_state));
9287
9288                 tmp = pipe_config->dpll_hw_state.dpll;
9289                 pipe_config->pixel_multiplier =
9290                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9291                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9292
9293                 ironlake_pch_clock_get(crtc, pipe_config);
9294         } else {
9295                 pipe_config->pixel_multiplier = 1;
9296         }
9297
9298         intel_get_pipe_timings(crtc, pipe_config);
9299         intel_get_pipe_src_size(crtc, pipe_config);
9300
9301         ironlake_get_pfit_config(crtc, pipe_config);
9302
9303         ret = true;
9304
9305 out:
9306         intel_display_power_put(dev_priv, power_domain);
9307
9308         return ret;
9309 }
9310
9311 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9312 {
9313         struct drm_device *dev = dev_priv->dev;
9314         struct intel_crtc *crtc;
9315
9316         for_each_intel_crtc(dev, crtc)
9317                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9318                      pipe_name(crtc->pipe));
9319
9320         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9321         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9322         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9323         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9324         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9325         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9326              "CPU PWM1 enabled\n");
9327         if (IS_HASWELL(dev))
9328                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9329                      "CPU PWM2 enabled\n");
9330         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9331              "PCH PWM1 enabled\n");
9332         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9333              "Utility pin enabled\n");
9334         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9335
9336         /*
9337          * In theory we can still leave IRQs enabled, as long as only the HPD
9338          * interrupts remain enabled. We used to check for that, but since it's
9339          * gen-specific and since we only disable LCPLL after we fully disable
9340          * the interrupts, the check below should be enough.
9341          */
9342         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9343 }
9344
9345 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9346 {
9347         struct drm_device *dev = dev_priv->dev;
9348
9349         if (IS_HASWELL(dev))
9350                 return I915_READ(D_COMP_HSW);
9351         else
9352                 return I915_READ(D_COMP_BDW);
9353 }
9354
9355 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9356 {
9357         struct drm_device *dev = dev_priv->dev;
9358
9359         if (IS_HASWELL(dev)) {
9360                 mutex_lock(&dev_priv->rps.hw_lock);
9361                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9362                                             val))
9363                         DRM_ERROR("Failed to write to D_COMP\n");
9364                 mutex_unlock(&dev_priv->rps.hw_lock);
9365         } else {
9366                 I915_WRITE(D_COMP_BDW, val);
9367                 POSTING_READ(D_COMP_BDW);
9368         }
9369 }
9370
9371 /*
9372  * This function implements pieces of two sequences from BSpec:
9373  * - Sequence for display software to disable LCPLL
9374  * - Sequence for display software to allow package C8+
9375  * The steps implemented here are just the steps that actually touch the LCPLL
9376  * register. Callers should take care of disabling all the display engine
9377  * functions, doing the mode unset, fixing interrupts, etc.
9378  */
9379 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9380                               bool switch_to_fclk, bool allow_power_down)
9381 {
9382         uint32_t val;
9383
9384         assert_can_disable_lcpll(dev_priv);
9385
9386         val = I915_READ(LCPLL_CTL);
9387
9388         if (switch_to_fclk) {
9389                 val |= LCPLL_CD_SOURCE_FCLK;
9390                 I915_WRITE(LCPLL_CTL, val);
9391
9392                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9393                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9394                         DRM_ERROR("Switching to FCLK failed\n");
9395
9396                 val = I915_READ(LCPLL_CTL);
9397         }
9398
9399         val |= LCPLL_PLL_DISABLE;
9400         I915_WRITE(LCPLL_CTL, val);
9401         POSTING_READ(LCPLL_CTL);
9402
9403         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9404                 DRM_ERROR("LCPLL still locked\n");
9405
9406         val = hsw_read_dcomp(dev_priv);
9407         val |= D_COMP_COMP_DISABLE;
9408         hsw_write_dcomp(dev_priv, val);
9409         ndelay(100);
9410
9411         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9412                      1))
9413                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9414
9415         if (allow_power_down) {
9416                 val = I915_READ(LCPLL_CTL);
9417                 val |= LCPLL_POWER_DOWN_ALLOW;
9418                 I915_WRITE(LCPLL_CTL, val);
9419                 POSTING_READ(LCPLL_CTL);
9420         }
9421 }
9422
9423 /*
9424  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9425  * source.
9426  */
9427 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9428 {
9429         uint32_t val;
9430
9431         val = I915_READ(LCPLL_CTL);
9432
9433         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9434                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9435                 return;
9436
9437         /*
9438          * Make sure we're not on PC8 state before disabling PC8, otherwise
9439          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9440          */
9441         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9442
9443         if (val & LCPLL_POWER_DOWN_ALLOW) {
9444                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9445                 I915_WRITE(LCPLL_CTL, val);
9446                 POSTING_READ(LCPLL_CTL);
9447         }
9448
9449         val = hsw_read_dcomp(dev_priv);
9450         val |= D_COMP_COMP_FORCE;
9451         val &= ~D_COMP_COMP_DISABLE;
9452         hsw_write_dcomp(dev_priv, val);
9453
9454         val = I915_READ(LCPLL_CTL);
9455         val &= ~LCPLL_PLL_DISABLE;
9456         I915_WRITE(LCPLL_CTL, val);
9457
9458         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9459                 DRM_ERROR("LCPLL not locked yet\n");
9460
9461         if (val & LCPLL_CD_SOURCE_FCLK) {
9462                 val = I915_READ(LCPLL_CTL);
9463                 val &= ~LCPLL_CD_SOURCE_FCLK;
9464                 I915_WRITE(LCPLL_CTL, val);
9465
9466                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9467                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9468                         DRM_ERROR("Switching back to LCPLL failed\n");
9469         }
9470
9471         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9472         intel_update_cdclk(dev_priv->dev);
9473 }
9474
9475 /*
9476  * Package states C8 and deeper are really deep PC states that can only be
9477  * reached when all the devices on the system allow it, so even if the graphics
9478  * device allows PC8+, it doesn't mean the system will actually get to these
9479  * states. Our driver only allows PC8+ when going into runtime PM.
9480  *
9481  * The requirements for PC8+ are that all the outputs are disabled, the power
9482  * well is disabled and most interrupts are disabled, and these are also
9483  * requirements for runtime PM. When these conditions are met, we manually do
9484  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9485  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9486  * hang the machine.
9487  *
9488  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9489  * the state of some registers, so when we come back from PC8+ we need to
9490  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9491  * need to take care of the registers kept by RC6. Notice that this happens even
9492  * if we don't put the device in PCI D3 state (which is what currently happens
9493  * because of the runtime PM support).
9494  *
9495  * For more, read "Display Sequences for Package C8" on the hardware
9496  * documentation.
9497  */
9498 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9499 {
9500         struct drm_device *dev = dev_priv->dev;
9501         uint32_t val;
9502
9503         DRM_DEBUG_KMS("Enabling package C8+\n");
9504
9505         if (HAS_PCH_LPT_LP(dev)) {
9506                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9507                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9508                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9509         }
9510
9511         lpt_disable_clkout_dp(dev);
9512         hsw_disable_lcpll(dev_priv, true, true);
9513 }
9514
9515 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9516 {
9517         struct drm_device *dev = dev_priv->dev;
9518         uint32_t val;
9519
9520         DRM_DEBUG_KMS("Disabling package C8+\n");
9521
9522         hsw_restore_lcpll(dev_priv);
9523         lpt_init_pch_refclk(dev);
9524
9525         if (HAS_PCH_LPT_LP(dev)) {
9526                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9527                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9528                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9529         }
9530 }
9531
9532 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9533 {
9534         struct drm_device *dev = old_state->dev;
9535         struct intel_atomic_state *old_intel_state =
9536                 to_intel_atomic_state(old_state);
9537         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9538
9539         broxton_set_cdclk(dev, req_cdclk);
9540 }
9541
9542 /* compute the max rate for new configuration */
9543 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9544 {
9545         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9546         struct drm_i915_private *dev_priv = state->dev->dev_private;
9547         struct drm_crtc *crtc;
9548         struct drm_crtc_state *cstate;
9549         struct intel_crtc_state *crtc_state;
9550         unsigned max_pixel_rate = 0, i;
9551         enum pipe pipe;
9552
9553         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9554                sizeof(intel_state->min_pixclk));
9555
9556         for_each_crtc_in_state(state, crtc, cstate, i) {
9557                 int pixel_rate;
9558
9559                 crtc_state = to_intel_crtc_state(cstate);
9560                 if (!crtc_state->base.enable) {
9561                         intel_state->min_pixclk[i] = 0;
9562                         continue;
9563                 }
9564
9565                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9566
9567                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9568                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9569                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9570
9571                 intel_state->min_pixclk[i] = pixel_rate;
9572         }
9573
9574         for_each_pipe(dev_priv, pipe)
9575                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9576
9577         return max_pixel_rate;
9578 }
9579
9580 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9581 {
9582         struct drm_i915_private *dev_priv = dev->dev_private;
9583         uint32_t val, data;
9584         int ret;
9585
9586         if (WARN((I915_READ(LCPLL_CTL) &
9587                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9588                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9589                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9590                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9591                  "trying to change cdclk frequency with cdclk not enabled\n"))
9592                 return;
9593
9594         mutex_lock(&dev_priv->rps.hw_lock);
9595         ret = sandybridge_pcode_write(dev_priv,
9596                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9597         mutex_unlock(&dev_priv->rps.hw_lock);
9598         if (ret) {
9599                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9600                 return;
9601         }
9602
9603         val = I915_READ(LCPLL_CTL);
9604         val |= LCPLL_CD_SOURCE_FCLK;
9605         I915_WRITE(LCPLL_CTL, val);
9606
9607         if (wait_for_us(I915_READ(LCPLL_CTL) &
9608                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9609                 DRM_ERROR("Switching to FCLK failed\n");
9610
9611         val = I915_READ(LCPLL_CTL);
9612         val &= ~LCPLL_CLK_FREQ_MASK;
9613
9614         switch (cdclk) {
9615         case 450000:
9616                 val |= LCPLL_CLK_FREQ_450;
9617                 data = 0;
9618                 break;
9619         case 540000:
9620                 val |= LCPLL_CLK_FREQ_54O_BDW;
9621                 data = 1;
9622                 break;
9623         case 337500:
9624                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9625                 data = 2;
9626                 break;
9627         case 675000:
9628                 val |= LCPLL_CLK_FREQ_675_BDW;
9629                 data = 3;
9630                 break;
9631         default:
9632                 WARN(1, "invalid cdclk frequency\n");
9633                 return;
9634         }
9635
9636         I915_WRITE(LCPLL_CTL, val);
9637
9638         val = I915_READ(LCPLL_CTL);
9639         val &= ~LCPLL_CD_SOURCE_FCLK;
9640         I915_WRITE(LCPLL_CTL, val);
9641
9642         if (wait_for_us((I915_READ(LCPLL_CTL) &
9643                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9644                 DRM_ERROR("Switching back to LCPLL failed\n");
9645
9646         mutex_lock(&dev_priv->rps.hw_lock);
9647         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9648         mutex_unlock(&dev_priv->rps.hw_lock);
9649
9650         intel_update_cdclk(dev);
9651
9652         WARN(cdclk != dev_priv->cdclk_freq,
9653              "cdclk requested %d kHz but got %d kHz\n",
9654              cdclk, dev_priv->cdclk_freq);
9655 }
9656
9657 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9658 {
9659         struct drm_i915_private *dev_priv = to_i915(state->dev);
9660         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9661         int max_pixclk = ilk_max_pixel_rate(state);
9662         int cdclk;
9663
9664         /*
9665          * FIXME should also account for plane ratio
9666          * once 64bpp pixel formats are supported.
9667          */
9668         if (max_pixclk > 540000)
9669                 cdclk = 675000;
9670         else if (max_pixclk > 450000)
9671                 cdclk = 540000;
9672         else if (max_pixclk > 337500)
9673                 cdclk = 450000;
9674         else
9675                 cdclk = 337500;
9676
9677         if (cdclk > dev_priv->max_cdclk_freq) {
9678                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9679                               cdclk, dev_priv->max_cdclk_freq);
9680                 return -EINVAL;
9681         }
9682
9683         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9684         if (!intel_state->active_crtcs)
9685                 intel_state->dev_cdclk = 337500;
9686
9687         return 0;
9688 }
9689
9690 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9691 {
9692         struct drm_device *dev = old_state->dev;
9693         struct intel_atomic_state *old_intel_state =
9694                 to_intel_atomic_state(old_state);
9695         unsigned req_cdclk = old_intel_state->dev_cdclk;
9696
9697         broadwell_set_cdclk(dev, req_cdclk);
9698 }
9699
9700 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9701                                       struct intel_crtc_state *crtc_state)
9702 {
9703         struct intel_encoder *intel_encoder =
9704                 intel_ddi_get_crtc_new_encoder(crtc_state);
9705
9706         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9707                 if (!intel_ddi_pll_select(crtc, crtc_state))
9708                         return -EINVAL;
9709         }
9710
9711         crtc->lowfreq_avail = false;
9712
9713         return 0;
9714 }
9715
9716 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9717                                 enum port port,
9718                                 struct intel_crtc_state *pipe_config)
9719 {
9720         enum intel_dpll_id id;
9721
9722         switch (port) {
9723         case PORT_A:
9724                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9725                 id = DPLL_ID_SKL_DPLL0;
9726                 break;
9727         case PORT_B:
9728                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9729                 id = DPLL_ID_SKL_DPLL1;
9730                 break;
9731         case PORT_C:
9732                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9733                 id = DPLL_ID_SKL_DPLL2;
9734                 break;
9735         default:
9736                 DRM_ERROR("Incorrect port type\n");
9737                 return;
9738         }
9739
9740         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9741 }
9742
9743 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9744                                 enum port port,
9745                                 struct intel_crtc_state *pipe_config)
9746 {
9747         enum intel_dpll_id id;
9748         u32 temp;
9749
9750         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9751         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9752
9753         switch (pipe_config->ddi_pll_sel) {
9754         case SKL_DPLL0:
9755                 id = DPLL_ID_SKL_DPLL0;
9756                 break;
9757         case SKL_DPLL1:
9758                 id = DPLL_ID_SKL_DPLL1;
9759                 break;
9760         case SKL_DPLL2:
9761                 id = DPLL_ID_SKL_DPLL2;
9762                 break;
9763         case SKL_DPLL3:
9764                 id = DPLL_ID_SKL_DPLL3;
9765                 break;
9766         default:
9767                 MISSING_CASE(pipe_config->ddi_pll_sel);
9768                 return;
9769         }
9770
9771         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9772 }
9773
9774 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9775                                 enum port port,
9776                                 struct intel_crtc_state *pipe_config)
9777 {
9778         enum intel_dpll_id id;
9779
9780         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9781
9782         switch (pipe_config->ddi_pll_sel) {
9783         case PORT_CLK_SEL_WRPLL1:
9784                 id = DPLL_ID_WRPLL1;
9785                 break;
9786         case PORT_CLK_SEL_WRPLL2:
9787                 id = DPLL_ID_WRPLL2;
9788                 break;
9789         case PORT_CLK_SEL_SPLL:
9790                 id = DPLL_ID_SPLL;
9791                 break;
9792         case PORT_CLK_SEL_LCPLL_810:
9793                 id = DPLL_ID_LCPLL_810;
9794                 break;
9795         case PORT_CLK_SEL_LCPLL_1350:
9796                 id = DPLL_ID_LCPLL_1350;
9797                 break;
9798         case PORT_CLK_SEL_LCPLL_2700:
9799                 id = DPLL_ID_LCPLL_2700;
9800                 break;
9801         default:
9802                 MISSING_CASE(pipe_config->ddi_pll_sel);
9803                 /* fall through */
9804         case PORT_CLK_SEL_NONE:
9805                 return;
9806         }
9807
9808         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9809 }
9810
9811 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9812                                      struct intel_crtc_state *pipe_config,
9813                                      unsigned long *power_domain_mask)
9814 {
9815         struct drm_device *dev = crtc->base.dev;
9816         struct drm_i915_private *dev_priv = dev->dev_private;
9817         enum intel_display_power_domain power_domain;
9818         u32 tmp;
9819
9820         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9821
9822         /*
9823          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9824          * consistency and less surprising code; it's in always on power).
9825          */
9826         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9827         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9828                 enum pipe trans_edp_pipe;
9829                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9830                 default:
9831                         WARN(1, "unknown pipe linked to edp transcoder\n");
9832                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9833                 case TRANS_DDI_EDP_INPUT_A_ON:
9834                         trans_edp_pipe = PIPE_A;
9835                         break;
9836                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9837                         trans_edp_pipe = PIPE_B;
9838                         break;
9839                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9840                         trans_edp_pipe = PIPE_C;
9841                         break;
9842                 }
9843
9844                 if (trans_edp_pipe == crtc->pipe)
9845                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9846         }
9847
9848         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9849         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9850                 return false;
9851         *power_domain_mask |= BIT(power_domain);
9852
9853         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9854
9855         return tmp & PIPECONF_ENABLE;
9856 }
9857
9858 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9859                                          struct intel_crtc_state *pipe_config,
9860                                          unsigned long *power_domain_mask)
9861 {
9862         struct drm_device *dev = crtc->base.dev;
9863         struct drm_i915_private *dev_priv = dev->dev_private;
9864         enum intel_display_power_domain power_domain;
9865         enum port port;
9866         enum transcoder cpu_transcoder;
9867         u32 tmp;
9868
9869         pipe_config->has_dsi_encoder = false;
9870
9871         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9872                 if (port == PORT_A)
9873                         cpu_transcoder = TRANSCODER_DSI_A;
9874                 else
9875                         cpu_transcoder = TRANSCODER_DSI_C;
9876
9877                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9878                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9879                         continue;
9880                 *power_domain_mask |= BIT(power_domain);
9881
9882                 /*
9883                  * The PLL needs to be enabled with a valid divider
9884                  * configuration, otherwise accessing DSI registers will hang
9885                  * the machine. See BSpec North Display Engine
9886                  * registers/MIPI[BXT]. We can break out here early, since we
9887                  * need the same DSI PLL to be enabled for both DSI ports.
9888                  */
9889                 if (!intel_dsi_pll_is_enabled(dev_priv))
9890                         break;
9891
9892                 /* XXX: this works for video mode only */
9893                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9894                 if (!(tmp & DPI_ENABLE))
9895                         continue;
9896
9897                 tmp = I915_READ(MIPI_CTRL(port));
9898                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9899                         continue;
9900
9901                 pipe_config->cpu_transcoder = cpu_transcoder;
9902                 pipe_config->has_dsi_encoder = true;
9903                 break;
9904         }
9905
9906         return pipe_config->has_dsi_encoder;
9907 }
9908
9909 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9910                                        struct intel_crtc_state *pipe_config)
9911 {
9912         struct drm_device *dev = crtc->base.dev;
9913         struct drm_i915_private *dev_priv = dev->dev_private;
9914         struct intel_shared_dpll *pll;
9915         enum port port;
9916         uint32_t tmp;
9917
9918         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9919
9920         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9921
9922         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9923                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9924         else if (IS_BROXTON(dev))
9925                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9926         else
9927                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9928
9929         pll = pipe_config->shared_dpll;
9930         if (pll) {
9931                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9932                                                  &pipe_config->dpll_hw_state));
9933         }
9934
9935         /*
9936          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9937          * DDI E. So just check whether this pipe is wired to DDI E and whether
9938          * the PCH transcoder is on.
9939          */
9940         if (INTEL_INFO(dev)->gen < 9 &&
9941             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9942                 pipe_config->has_pch_encoder = true;
9943
9944                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9945                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9946                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9947
9948                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9949         }
9950 }
9951
9952 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9953                                     struct intel_crtc_state *pipe_config)
9954 {
9955         struct drm_device *dev = crtc->base.dev;
9956         struct drm_i915_private *dev_priv = dev->dev_private;
9957         enum intel_display_power_domain power_domain;
9958         unsigned long power_domain_mask;
9959         bool active;
9960
9961         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9962         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9963                 return false;
9964         power_domain_mask = BIT(power_domain);
9965
9966         pipe_config->shared_dpll = NULL;
9967
9968         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9969
9970         if (IS_BROXTON(dev_priv)) {
9971                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9972                                              &power_domain_mask);
9973                 WARN_ON(active && pipe_config->has_dsi_encoder);
9974                 if (pipe_config->has_dsi_encoder)
9975                         active = true;
9976         }
9977
9978         if (!active)
9979                 goto out;
9980
9981         if (!pipe_config->has_dsi_encoder) {
9982                 haswell_get_ddi_port_state(crtc, pipe_config);
9983                 intel_get_pipe_timings(crtc, pipe_config);
9984         }
9985
9986         intel_get_pipe_src_size(crtc, pipe_config);
9987
9988         pipe_config->gamma_mode =
9989                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9990
9991         if (INTEL_INFO(dev)->gen >= 9) {
9992                 skl_init_scalers(dev, crtc, pipe_config);
9993         }
9994
9995         if (INTEL_INFO(dev)->gen >= 9) {
9996                 pipe_config->scaler_state.scaler_id = -1;
9997                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9998         }
9999
10000         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10001         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10002                 power_domain_mask |= BIT(power_domain);
10003                 if (INTEL_INFO(dev)->gen >= 9)
10004                         skylake_get_pfit_config(crtc, pipe_config);
10005                 else
10006                         ironlake_get_pfit_config(crtc, pipe_config);
10007         }
10008
10009         if (IS_HASWELL(dev))
10010                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10011                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10012
10013         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10014             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10015                 pipe_config->pixel_multiplier =
10016                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10017         } else {
10018                 pipe_config->pixel_multiplier = 1;
10019         }
10020
10021 out:
10022         for_each_power_domain(power_domain, power_domain_mask)
10023                 intel_display_power_put(dev_priv, power_domain);
10024
10025         return active;
10026 }
10027
10028 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10029                                const struct intel_plane_state *plane_state)
10030 {
10031         struct drm_device *dev = crtc->dev;
10032         struct drm_i915_private *dev_priv = dev->dev_private;
10033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10034         uint32_t cntl = 0, size = 0;
10035
10036         if (plane_state && plane_state->visible) {
10037                 unsigned int width = plane_state->base.crtc_w;
10038                 unsigned int height = plane_state->base.crtc_h;
10039                 unsigned int stride = roundup_pow_of_two(width) * 4;
10040
10041                 switch (stride) {
10042                 default:
10043                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10044                                   width, stride);
10045                         stride = 256;
10046                         /* fallthrough */
10047                 case 256:
10048                 case 512:
10049                 case 1024:
10050                 case 2048:
10051                         break;
10052                 }
10053
10054                 cntl |= CURSOR_ENABLE |
10055                         CURSOR_GAMMA_ENABLE |
10056                         CURSOR_FORMAT_ARGB |
10057                         CURSOR_STRIDE(stride);
10058
10059                 size = (height << 12) | width;
10060         }
10061
10062         if (intel_crtc->cursor_cntl != 0 &&
10063             (intel_crtc->cursor_base != base ||
10064              intel_crtc->cursor_size != size ||
10065              intel_crtc->cursor_cntl != cntl)) {
10066                 /* On these chipsets we can only modify the base/size/stride
10067                  * whilst the cursor is disabled.
10068                  */
10069                 I915_WRITE(CURCNTR(PIPE_A), 0);
10070                 POSTING_READ(CURCNTR(PIPE_A));
10071                 intel_crtc->cursor_cntl = 0;
10072         }
10073
10074         if (intel_crtc->cursor_base != base) {
10075                 I915_WRITE(CURBASE(PIPE_A), base);
10076                 intel_crtc->cursor_base = base;
10077         }
10078
10079         if (intel_crtc->cursor_size != size) {
10080                 I915_WRITE(CURSIZE, size);
10081                 intel_crtc->cursor_size = size;
10082         }
10083
10084         if (intel_crtc->cursor_cntl != cntl) {
10085                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10086                 POSTING_READ(CURCNTR(PIPE_A));
10087                 intel_crtc->cursor_cntl = cntl;
10088         }
10089 }
10090
10091 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10092                                const struct intel_plane_state *plane_state)
10093 {
10094         struct drm_device *dev = crtc->dev;
10095         struct drm_i915_private *dev_priv = dev->dev_private;
10096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10097         int pipe = intel_crtc->pipe;
10098         uint32_t cntl = 0;
10099
10100         if (plane_state && plane_state->visible) {
10101                 cntl = MCURSOR_GAMMA_ENABLE;
10102                 switch (plane_state->base.crtc_w) {
10103                         case 64:
10104                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10105                                 break;
10106                         case 128:
10107                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10108                                 break;
10109                         case 256:
10110                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10111                                 break;
10112                         default:
10113                                 MISSING_CASE(plane_state->base.crtc_w);
10114                                 return;
10115                 }
10116                 cntl |= pipe << 28; /* Connect to correct pipe */
10117
10118                 if (HAS_DDI(dev))
10119                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10120
10121                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10122                         cntl |= CURSOR_ROTATE_180;
10123         }
10124
10125         if (intel_crtc->cursor_cntl != cntl) {
10126                 I915_WRITE(CURCNTR(pipe), cntl);
10127                 POSTING_READ(CURCNTR(pipe));
10128                 intel_crtc->cursor_cntl = cntl;
10129         }
10130
10131         /* and commit changes on next vblank */
10132         I915_WRITE(CURBASE(pipe), base);
10133         POSTING_READ(CURBASE(pipe));
10134
10135         intel_crtc->cursor_base = base;
10136 }
10137
10138 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10139 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10140                                      const struct intel_plane_state *plane_state)
10141 {
10142         struct drm_device *dev = crtc->dev;
10143         struct drm_i915_private *dev_priv = dev->dev_private;
10144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10145         int pipe = intel_crtc->pipe;
10146         u32 base = intel_crtc->cursor_addr;
10147         u32 pos = 0;
10148
10149         if (plane_state) {
10150                 int x = plane_state->base.crtc_x;
10151                 int y = plane_state->base.crtc_y;
10152
10153                 if (x < 0) {
10154                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10155                         x = -x;
10156                 }
10157                 pos |= x << CURSOR_X_SHIFT;
10158
10159                 if (y < 0) {
10160                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10161                         y = -y;
10162                 }
10163                 pos |= y << CURSOR_Y_SHIFT;
10164
10165                 /* ILK+ do this automagically */
10166                 if (HAS_GMCH_DISPLAY(dev) &&
10167                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10168                         base += (plane_state->base.crtc_h *
10169                                  plane_state->base.crtc_w - 1) * 4;
10170                 }
10171         }
10172
10173         I915_WRITE(CURPOS(pipe), pos);
10174
10175         if (IS_845G(dev) || IS_I865G(dev))
10176                 i845_update_cursor(crtc, base, plane_state);
10177         else
10178                 i9xx_update_cursor(crtc, base, plane_state);
10179 }
10180
10181 static bool cursor_size_ok(struct drm_device *dev,
10182                            uint32_t width, uint32_t height)
10183 {
10184         if (width == 0 || height == 0)
10185                 return false;
10186
10187         /*
10188          * 845g/865g are special in that they are only limited by
10189          * the width of their cursors, the height is arbitrary up to
10190          * the precision of the register. Everything else requires
10191          * square cursors, limited to a few power-of-two sizes.
10192          */
10193         if (IS_845G(dev) || IS_I865G(dev)) {
10194                 if ((width & 63) != 0)
10195                         return false;
10196
10197                 if (width > (IS_845G(dev) ? 64 : 512))
10198                         return false;
10199
10200                 if (height > 1023)
10201                         return false;
10202         } else {
10203                 switch (width | height) {
10204                 case 256:
10205                 case 128:
10206                         if (IS_GEN2(dev))
10207                                 return false;
10208                 case 64:
10209                         break;
10210                 default:
10211                         return false;
10212                 }
10213         }
10214
10215         return true;
10216 }
10217
10218 /* VESA 640x480x72Hz mode to set on the pipe */
10219 static struct drm_display_mode load_detect_mode = {
10220         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10221                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10222 };
10223
10224 struct drm_framebuffer *
10225 __intel_framebuffer_create(struct drm_device *dev,
10226                            struct drm_mode_fb_cmd2 *mode_cmd,
10227                            struct drm_i915_gem_object *obj)
10228 {
10229         struct intel_framebuffer *intel_fb;
10230         int ret;
10231
10232         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10233         if (!intel_fb)
10234                 return ERR_PTR(-ENOMEM);
10235
10236         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10237         if (ret)
10238                 goto err;
10239
10240         return &intel_fb->base;
10241
10242 err:
10243         kfree(intel_fb);
10244         return ERR_PTR(ret);
10245 }
10246
10247 static struct drm_framebuffer *
10248 intel_framebuffer_create(struct drm_device *dev,
10249                          struct drm_mode_fb_cmd2 *mode_cmd,
10250                          struct drm_i915_gem_object *obj)
10251 {
10252         struct drm_framebuffer *fb;
10253         int ret;
10254
10255         ret = i915_mutex_lock_interruptible(dev);
10256         if (ret)
10257                 return ERR_PTR(ret);
10258         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10259         mutex_unlock(&dev->struct_mutex);
10260
10261         return fb;
10262 }
10263
10264 static u32
10265 intel_framebuffer_pitch_for_width(int width, int bpp)
10266 {
10267         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10268         return ALIGN(pitch, 64);
10269 }
10270
10271 static u32
10272 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10273 {
10274         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10275         return PAGE_ALIGN(pitch * mode->vdisplay);
10276 }
10277
10278 static struct drm_framebuffer *
10279 intel_framebuffer_create_for_mode(struct drm_device *dev,
10280                                   struct drm_display_mode *mode,
10281                                   int depth, int bpp)
10282 {
10283         struct drm_framebuffer *fb;
10284         struct drm_i915_gem_object *obj;
10285         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10286
10287         obj = i915_gem_alloc_object(dev,
10288                                     intel_framebuffer_size_for_mode(mode, bpp));
10289         if (obj == NULL)
10290                 return ERR_PTR(-ENOMEM);
10291
10292         mode_cmd.width = mode->hdisplay;
10293         mode_cmd.height = mode->vdisplay;
10294         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10295                                                                 bpp);
10296         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10297
10298         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10299         if (IS_ERR(fb))
10300                 drm_gem_object_unreference_unlocked(&obj->base);
10301
10302         return fb;
10303 }
10304
10305 static struct drm_framebuffer *
10306 mode_fits_in_fbdev(struct drm_device *dev,
10307                    struct drm_display_mode *mode)
10308 {
10309 #ifdef CONFIG_DRM_FBDEV_EMULATION
10310         struct drm_i915_private *dev_priv = dev->dev_private;
10311         struct drm_i915_gem_object *obj;
10312         struct drm_framebuffer *fb;
10313
10314         if (!dev_priv->fbdev)
10315                 return NULL;
10316
10317         if (!dev_priv->fbdev->fb)
10318                 return NULL;
10319
10320         obj = dev_priv->fbdev->fb->obj;
10321         BUG_ON(!obj);
10322
10323         fb = &dev_priv->fbdev->fb->base;
10324         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10325                                                                fb->bits_per_pixel))
10326                 return NULL;
10327
10328         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10329                 return NULL;
10330
10331         drm_framebuffer_reference(fb);
10332         return fb;
10333 #else
10334         return NULL;
10335 #endif
10336 }
10337
10338 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10339                                            struct drm_crtc *crtc,
10340                                            struct drm_display_mode *mode,
10341                                            struct drm_framebuffer *fb,
10342                                            int x, int y)
10343 {
10344         struct drm_plane_state *plane_state;
10345         int hdisplay, vdisplay;
10346         int ret;
10347
10348         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10349         if (IS_ERR(plane_state))
10350                 return PTR_ERR(plane_state);
10351
10352         if (mode)
10353                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10354         else
10355                 hdisplay = vdisplay = 0;
10356
10357         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10358         if (ret)
10359                 return ret;
10360         drm_atomic_set_fb_for_plane(plane_state, fb);
10361         plane_state->crtc_x = 0;
10362         plane_state->crtc_y = 0;
10363         plane_state->crtc_w = hdisplay;
10364         plane_state->crtc_h = vdisplay;
10365         plane_state->src_x = x << 16;
10366         plane_state->src_y = y << 16;
10367         plane_state->src_w = hdisplay << 16;
10368         plane_state->src_h = vdisplay << 16;
10369
10370         return 0;
10371 }
10372
10373 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10374                                 struct drm_display_mode *mode,
10375                                 struct intel_load_detect_pipe *old,
10376                                 struct drm_modeset_acquire_ctx *ctx)
10377 {
10378         struct intel_crtc *intel_crtc;
10379         struct intel_encoder *intel_encoder =
10380                 intel_attached_encoder(connector);
10381         struct drm_crtc *possible_crtc;
10382         struct drm_encoder *encoder = &intel_encoder->base;
10383         struct drm_crtc *crtc = NULL;
10384         struct drm_device *dev = encoder->dev;
10385         struct drm_framebuffer *fb;
10386         struct drm_mode_config *config = &dev->mode_config;
10387         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10388         struct drm_connector_state *connector_state;
10389         struct intel_crtc_state *crtc_state;
10390         int ret, i = -1;
10391
10392         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10393                       connector->base.id, connector->name,
10394                       encoder->base.id, encoder->name);
10395
10396         old->restore_state = NULL;
10397
10398 retry:
10399         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10400         if (ret)
10401                 goto fail;
10402
10403         /*
10404          * Algorithm gets a little messy:
10405          *
10406          *   - if the connector already has an assigned crtc, use it (but make
10407          *     sure it's on first)
10408          *
10409          *   - try to find the first unused crtc that can drive this connector,
10410          *     and use that if we find one
10411          */
10412
10413         /* See if we already have a CRTC for this connector */
10414         if (connector->state->crtc) {
10415                 crtc = connector->state->crtc;
10416
10417                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10418                 if (ret)
10419                         goto fail;
10420
10421                 /* Make sure the crtc and connector are running */
10422                 goto found;
10423         }
10424
10425         /* Find an unused one (if possible) */
10426         for_each_crtc(dev, possible_crtc) {
10427                 i++;
10428                 if (!(encoder->possible_crtcs & (1 << i)))
10429                         continue;
10430
10431                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10432                 if (ret)
10433                         goto fail;
10434
10435                 if (possible_crtc->state->enable) {
10436                         drm_modeset_unlock(&possible_crtc->mutex);
10437                         continue;
10438                 }
10439
10440                 crtc = possible_crtc;
10441                 break;
10442         }
10443
10444         /*
10445          * If we didn't find an unused CRTC, don't use any.
10446          */
10447         if (!crtc) {
10448                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10449                 goto fail;
10450         }
10451
10452 found:
10453         intel_crtc = to_intel_crtc(crtc);
10454
10455         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10456         if (ret)
10457                 goto fail;
10458
10459         state = drm_atomic_state_alloc(dev);
10460         restore_state = drm_atomic_state_alloc(dev);
10461         if (!state || !restore_state) {
10462                 ret = -ENOMEM;
10463                 goto fail;
10464         }
10465
10466         state->acquire_ctx = ctx;
10467         restore_state->acquire_ctx = ctx;
10468
10469         connector_state = drm_atomic_get_connector_state(state, connector);
10470         if (IS_ERR(connector_state)) {
10471                 ret = PTR_ERR(connector_state);
10472                 goto fail;
10473         }
10474
10475         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10476         if (ret)
10477                 goto fail;
10478
10479         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10480         if (IS_ERR(crtc_state)) {
10481                 ret = PTR_ERR(crtc_state);
10482                 goto fail;
10483         }
10484
10485         crtc_state->base.active = crtc_state->base.enable = true;
10486
10487         if (!mode)
10488                 mode = &load_detect_mode;
10489
10490         /* We need a framebuffer large enough to accommodate all accesses
10491          * that the plane may generate whilst we perform load detection.
10492          * We can not rely on the fbcon either being present (we get called
10493          * during its initialisation to detect all boot displays, or it may
10494          * not even exist) or that it is large enough to satisfy the
10495          * requested mode.
10496          */
10497         fb = mode_fits_in_fbdev(dev, mode);
10498         if (fb == NULL) {
10499                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10500                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10501         } else
10502                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10503         if (IS_ERR(fb)) {
10504                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10505                 goto fail;
10506         }
10507
10508         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10509         if (ret)
10510                 goto fail;
10511
10512         drm_framebuffer_unreference(fb);
10513
10514         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10515         if (ret)
10516                 goto fail;
10517
10518         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10519         if (!ret)
10520                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10521         if (!ret)
10522                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10523         if (ret) {
10524                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10525                 goto fail;
10526         }
10527
10528         ret = drm_atomic_commit(state);
10529         if (ret) {
10530                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10531                 goto fail;
10532         }
10533
10534         old->restore_state = restore_state;
10535
10536         /* let the connector get through one full cycle before testing */
10537         intel_wait_for_vblank(dev, intel_crtc->pipe);
10538         return true;
10539
10540 fail:
10541         drm_atomic_state_free(state);
10542         drm_atomic_state_free(restore_state);
10543         restore_state = state = NULL;
10544
10545         if (ret == -EDEADLK) {
10546                 drm_modeset_backoff(ctx);
10547                 goto retry;
10548         }
10549
10550         return false;
10551 }
10552
10553 void intel_release_load_detect_pipe(struct drm_connector *connector,
10554                                     struct intel_load_detect_pipe *old,
10555                                     struct drm_modeset_acquire_ctx *ctx)
10556 {
10557         struct intel_encoder *intel_encoder =
10558                 intel_attached_encoder(connector);
10559         struct drm_encoder *encoder = &intel_encoder->base;
10560         struct drm_atomic_state *state = old->restore_state;
10561         int ret;
10562
10563         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10564                       connector->base.id, connector->name,
10565                       encoder->base.id, encoder->name);
10566
10567         if (!state)
10568                 return;
10569
10570         ret = drm_atomic_commit(state);
10571         if (ret) {
10572                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10573                 drm_atomic_state_free(state);
10574         }
10575 }
10576
10577 static int i9xx_pll_refclk(struct drm_device *dev,
10578                            const struct intel_crtc_state *pipe_config)
10579 {
10580         struct drm_i915_private *dev_priv = dev->dev_private;
10581         u32 dpll = pipe_config->dpll_hw_state.dpll;
10582
10583         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10584                 return dev_priv->vbt.lvds_ssc_freq;
10585         else if (HAS_PCH_SPLIT(dev))
10586                 return 120000;
10587         else if (!IS_GEN2(dev))
10588                 return 96000;
10589         else
10590                 return 48000;
10591 }
10592
10593 /* Returns the clock of the currently programmed mode of the given pipe. */
10594 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10595                                 struct intel_crtc_state *pipe_config)
10596 {
10597         struct drm_device *dev = crtc->base.dev;
10598         struct drm_i915_private *dev_priv = dev->dev_private;
10599         int pipe = pipe_config->cpu_transcoder;
10600         u32 dpll = pipe_config->dpll_hw_state.dpll;
10601         u32 fp;
10602         intel_clock_t clock;
10603         int port_clock;
10604         int refclk = i9xx_pll_refclk(dev, pipe_config);
10605
10606         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10607                 fp = pipe_config->dpll_hw_state.fp0;
10608         else
10609                 fp = pipe_config->dpll_hw_state.fp1;
10610
10611         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10612         if (IS_PINEVIEW(dev)) {
10613                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10614                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10615         } else {
10616                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10617                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10618         }
10619
10620         if (!IS_GEN2(dev)) {
10621                 if (IS_PINEVIEW(dev))
10622                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10623                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10624                 else
10625                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10626                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10627
10628                 switch (dpll & DPLL_MODE_MASK) {
10629                 case DPLLB_MODE_DAC_SERIAL:
10630                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10631                                 5 : 10;
10632                         break;
10633                 case DPLLB_MODE_LVDS:
10634                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10635                                 7 : 14;
10636                         break;
10637                 default:
10638                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10639                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10640                         return;
10641                 }
10642
10643                 if (IS_PINEVIEW(dev))
10644                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10645                 else
10646                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10647         } else {
10648                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10649                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10650
10651                 if (is_lvds) {
10652                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10653                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10654
10655                         if (lvds & LVDS_CLKB_POWER_UP)
10656                                 clock.p2 = 7;
10657                         else
10658                                 clock.p2 = 14;
10659                 } else {
10660                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10661                                 clock.p1 = 2;
10662                         else {
10663                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10664                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10665                         }
10666                         if (dpll & PLL_P2_DIVIDE_BY_4)
10667                                 clock.p2 = 4;
10668                         else
10669                                 clock.p2 = 2;
10670                 }
10671
10672                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10673         }
10674
10675         /*
10676          * This value includes pixel_multiplier. We will use
10677          * port_clock to compute adjusted_mode.crtc_clock in the
10678          * encoder's get_config() function.
10679          */
10680         pipe_config->port_clock = port_clock;
10681 }
10682
10683 int intel_dotclock_calculate(int link_freq,
10684                              const struct intel_link_m_n *m_n)
10685 {
10686         /*
10687          * The calculation for the data clock is:
10688          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10689          * But we want to avoid losing precison if possible, so:
10690          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10691          *
10692          * and the link clock is simpler:
10693          * link_clock = (m * link_clock) / n
10694          */
10695
10696         if (!m_n->link_n)
10697                 return 0;
10698
10699         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10700 }
10701
10702 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10703                                    struct intel_crtc_state *pipe_config)
10704 {
10705         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10706
10707         /* read out port_clock from the DPLL */
10708         i9xx_crtc_clock_get(crtc, pipe_config);
10709
10710         /*
10711          * In case there is an active pipe without active ports,
10712          * we may need some idea for the dotclock anyway.
10713          * Calculate one based on the FDI configuration.
10714          */
10715         pipe_config->base.adjusted_mode.crtc_clock =
10716                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10717                                          &pipe_config->fdi_m_n);
10718 }
10719
10720 /** Returns the currently programmed mode of the given pipe. */
10721 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10722                                              struct drm_crtc *crtc)
10723 {
10724         struct drm_i915_private *dev_priv = dev->dev_private;
10725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10726         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10727         struct drm_display_mode *mode;
10728         struct intel_crtc_state *pipe_config;
10729         int htot = I915_READ(HTOTAL(cpu_transcoder));
10730         int hsync = I915_READ(HSYNC(cpu_transcoder));
10731         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10732         int vsync = I915_READ(VSYNC(cpu_transcoder));
10733         enum pipe pipe = intel_crtc->pipe;
10734
10735         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10736         if (!mode)
10737                 return NULL;
10738
10739         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10740         if (!pipe_config) {
10741                 kfree(mode);
10742                 return NULL;
10743         }
10744
10745         /*
10746          * Construct a pipe_config sufficient for getting the clock info
10747          * back out of crtc_clock_get.
10748          *
10749          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10750          * to use a real value here instead.
10751          */
10752         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10753         pipe_config->pixel_multiplier = 1;
10754         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10755         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10756         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10757         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10758
10759         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10760         mode->hdisplay = (htot & 0xffff) + 1;
10761         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10762         mode->hsync_start = (hsync & 0xffff) + 1;
10763         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10764         mode->vdisplay = (vtot & 0xffff) + 1;
10765         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10766         mode->vsync_start = (vsync & 0xffff) + 1;
10767         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10768
10769         drm_mode_set_name(mode);
10770
10771         kfree(pipe_config);
10772
10773         return mode;
10774 }
10775
10776 void intel_mark_busy(struct drm_device *dev)
10777 {
10778         struct drm_i915_private *dev_priv = dev->dev_private;
10779
10780         if (dev_priv->mm.busy)
10781                 return;
10782
10783         intel_runtime_pm_get(dev_priv);
10784         i915_update_gfx_val(dev_priv);
10785         if (INTEL_INFO(dev)->gen >= 6)
10786                 gen6_rps_busy(dev_priv);
10787         dev_priv->mm.busy = true;
10788 }
10789
10790 void intel_mark_idle(struct drm_device *dev)
10791 {
10792         struct drm_i915_private *dev_priv = dev->dev_private;
10793
10794         if (!dev_priv->mm.busy)
10795                 return;
10796
10797         dev_priv->mm.busy = false;
10798
10799         if (INTEL_INFO(dev)->gen >= 6)
10800                 gen6_rps_idle(dev->dev_private);
10801
10802         intel_runtime_pm_put(dev_priv);
10803 }
10804
10805 static void intel_crtc_destroy(struct drm_crtc *crtc)
10806 {
10807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10808         struct drm_device *dev = crtc->dev;
10809         struct intel_unpin_work *work;
10810
10811         spin_lock_irq(&dev->event_lock);
10812         work = intel_crtc->unpin_work;
10813         intel_crtc->unpin_work = NULL;
10814         spin_unlock_irq(&dev->event_lock);
10815
10816         if (work) {
10817                 cancel_work_sync(&work->work);
10818                 kfree(work);
10819         }
10820
10821         drm_crtc_cleanup(crtc);
10822
10823         kfree(intel_crtc);
10824 }
10825
10826 static void intel_unpin_work_fn(struct work_struct *__work)
10827 {
10828         struct intel_unpin_work *work =
10829                 container_of(__work, struct intel_unpin_work, work);
10830         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10831         struct drm_device *dev = crtc->base.dev;
10832         struct drm_plane *primary = crtc->base.primary;
10833
10834         mutex_lock(&dev->struct_mutex);
10835         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10836         drm_gem_object_unreference(&work->pending_flip_obj->base);
10837
10838         if (work->flip_queued_req)
10839                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10840         mutex_unlock(&dev->struct_mutex);
10841
10842         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10843         intel_fbc_post_update(crtc);
10844         drm_framebuffer_unreference(work->old_fb);
10845
10846         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10847         atomic_dec(&crtc->unpin_work_count);
10848
10849         kfree(work);
10850 }
10851
10852 static void do_intel_finish_page_flip(struct drm_device *dev,
10853                                       struct drm_crtc *crtc)
10854 {
10855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10856         struct intel_unpin_work *work;
10857         unsigned long flags;
10858
10859         /* Ignore early vblank irqs */
10860         if (intel_crtc == NULL)
10861                 return;
10862
10863         /*
10864          * This is called both by irq handlers and the reset code (to complete
10865          * lost pageflips) so needs the full irqsave spinlocks.
10866          */
10867         spin_lock_irqsave(&dev->event_lock, flags);
10868         work = intel_crtc->unpin_work;
10869
10870         /* Ensure we don't miss a work->pending update ... */
10871         smp_rmb();
10872
10873         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10874                 spin_unlock_irqrestore(&dev->event_lock, flags);
10875                 return;
10876         }
10877
10878         page_flip_completed(intel_crtc);
10879
10880         spin_unlock_irqrestore(&dev->event_lock, flags);
10881 }
10882
10883 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10884 {
10885         struct drm_i915_private *dev_priv = dev->dev_private;
10886         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10887
10888         do_intel_finish_page_flip(dev, crtc);
10889 }
10890
10891 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10892 {
10893         struct drm_i915_private *dev_priv = dev->dev_private;
10894         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10895
10896         do_intel_finish_page_flip(dev, crtc);
10897 }
10898
10899 /* Is 'a' after or equal to 'b'? */
10900 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10901 {
10902         return !((a - b) & 0x80000000);
10903 }
10904
10905 static bool page_flip_finished(struct intel_crtc *crtc)
10906 {
10907         struct drm_device *dev = crtc->base.dev;
10908         struct drm_i915_private *dev_priv = dev->dev_private;
10909         unsigned reset_counter;
10910
10911         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10912         if (crtc->reset_counter != reset_counter)
10913                 return true;
10914
10915         /*
10916          * The relevant registers doen't exist on pre-ctg.
10917          * As the flip done interrupt doesn't trigger for mmio
10918          * flips on gmch platforms, a flip count check isn't
10919          * really needed there. But since ctg has the registers,
10920          * include it in the check anyway.
10921          */
10922         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10923                 return true;
10924
10925         /*
10926          * BDW signals flip done immediately if the plane
10927          * is disabled, even if the plane enable is already
10928          * armed to occur at the next vblank :(
10929          */
10930
10931         /*
10932          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10933          * used the same base address. In that case the mmio flip might
10934          * have completed, but the CS hasn't even executed the flip yet.
10935          *
10936          * A flip count check isn't enough as the CS might have updated
10937          * the base address just after start of vblank, but before we
10938          * managed to process the interrupt. This means we'd complete the
10939          * CS flip too soon.
10940          *
10941          * Combining both checks should get us a good enough result. It may
10942          * still happen that the CS flip has been executed, but has not
10943          * yet actually completed. But in case the base address is the same
10944          * anyway, we don't really care.
10945          */
10946         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10947                 crtc->unpin_work->gtt_offset &&
10948                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10949                                     crtc->unpin_work->flip_count);
10950 }
10951
10952 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10953 {
10954         struct drm_i915_private *dev_priv = dev->dev_private;
10955         struct intel_crtc *intel_crtc =
10956                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10957         unsigned long flags;
10958
10959
10960         /*
10961          * This is called both by irq handlers and the reset code (to complete
10962          * lost pageflips) so needs the full irqsave spinlocks.
10963          *
10964          * NB: An MMIO update of the plane base pointer will also
10965          * generate a page-flip completion irq, i.e. every modeset
10966          * is also accompanied by a spurious intel_prepare_page_flip().
10967          */
10968         spin_lock_irqsave(&dev->event_lock, flags);
10969         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10970                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10971         spin_unlock_irqrestore(&dev->event_lock, flags);
10972 }
10973
10974 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10975 {
10976         /* Ensure that the work item is consistent when activating it ... */
10977         smp_wmb();
10978         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10979         /* and that it is marked active as soon as the irq could fire. */
10980         smp_wmb();
10981 }
10982
10983 static int intel_gen2_queue_flip(struct drm_device *dev,
10984                                  struct drm_crtc *crtc,
10985                                  struct drm_framebuffer *fb,
10986                                  struct drm_i915_gem_object *obj,
10987                                  struct drm_i915_gem_request *req,
10988                                  uint32_t flags)
10989 {
10990         struct intel_engine_cs *engine = req->engine;
10991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10992         u32 flip_mask;
10993         int ret;
10994
10995         ret = intel_ring_begin(req, 6);
10996         if (ret)
10997                 return ret;
10998
10999         /* Can't queue multiple flips, so wait for the previous
11000          * one to finish before executing the next.
11001          */
11002         if (intel_crtc->plane)
11003                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11004         else
11005                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11006         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11007         intel_ring_emit(engine, MI_NOOP);
11008         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11009                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11010         intel_ring_emit(engine, fb->pitches[0]);
11011         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11012         intel_ring_emit(engine, 0); /* aux display base address, unused */
11013
11014         intel_mark_page_flip_active(intel_crtc->unpin_work);
11015         return 0;
11016 }
11017
11018 static int intel_gen3_queue_flip(struct drm_device *dev,
11019                                  struct drm_crtc *crtc,
11020                                  struct drm_framebuffer *fb,
11021                                  struct drm_i915_gem_object *obj,
11022                                  struct drm_i915_gem_request *req,
11023                                  uint32_t flags)
11024 {
11025         struct intel_engine_cs *engine = req->engine;
11026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11027         u32 flip_mask;
11028         int ret;
11029
11030         ret = intel_ring_begin(req, 6);
11031         if (ret)
11032                 return ret;
11033
11034         if (intel_crtc->plane)
11035                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11036         else
11037                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11038         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11039         intel_ring_emit(engine, MI_NOOP);
11040         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11041                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11042         intel_ring_emit(engine, fb->pitches[0]);
11043         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11044         intel_ring_emit(engine, MI_NOOP);
11045
11046         intel_mark_page_flip_active(intel_crtc->unpin_work);
11047         return 0;
11048 }
11049
11050 static int intel_gen4_queue_flip(struct drm_device *dev,
11051                                  struct drm_crtc *crtc,
11052                                  struct drm_framebuffer *fb,
11053                                  struct drm_i915_gem_object *obj,
11054                                  struct drm_i915_gem_request *req,
11055                                  uint32_t flags)
11056 {
11057         struct intel_engine_cs *engine = req->engine;
11058         struct drm_i915_private *dev_priv = dev->dev_private;
11059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11060         uint32_t pf, pipesrc;
11061         int ret;
11062
11063         ret = intel_ring_begin(req, 4);
11064         if (ret)
11065                 return ret;
11066
11067         /* i965+ uses the linear or tiled offsets from the
11068          * Display Registers (which do not change across a page-flip)
11069          * so we need only reprogram the base address.
11070          */
11071         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11072                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11073         intel_ring_emit(engine, fb->pitches[0]);
11074         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11075                         obj->tiling_mode);
11076
11077         /* XXX Enabling the panel-fitter across page-flip is so far
11078          * untested on non-native modes, so ignore it for now.
11079          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11080          */
11081         pf = 0;
11082         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11083         intel_ring_emit(engine, pf | pipesrc);
11084
11085         intel_mark_page_flip_active(intel_crtc->unpin_work);
11086         return 0;
11087 }
11088
11089 static int intel_gen6_queue_flip(struct drm_device *dev,
11090                                  struct drm_crtc *crtc,
11091                                  struct drm_framebuffer *fb,
11092                                  struct drm_i915_gem_object *obj,
11093                                  struct drm_i915_gem_request *req,
11094                                  uint32_t flags)
11095 {
11096         struct intel_engine_cs *engine = req->engine;
11097         struct drm_i915_private *dev_priv = dev->dev_private;
11098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11099         uint32_t pf, pipesrc;
11100         int ret;
11101
11102         ret = intel_ring_begin(req, 4);
11103         if (ret)
11104                 return ret;
11105
11106         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11107                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11108         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11109         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11110
11111         /* Contrary to the suggestions in the documentation,
11112          * "Enable Panel Fitter" does not seem to be required when page
11113          * flipping with a non-native mode, and worse causes a normal
11114          * modeset to fail.
11115          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11116          */
11117         pf = 0;
11118         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11119         intel_ring_emit(engine, pf | pipesrc);
11120
11121         intel_mark_page_flip_active(intel_crtc->unpin_work);
11122         return 0;
11123 }
11124
11125 static int intel_gen7_queue_flip(struct drm_device *dev,
11126                                  struct drm_crtc *crtc,
11127                                  struct drm_framebuffer *fb,
11128                                  struct drm_i915_gem_object *obj,
11129                                  struct drm_i915_gem_request *req,
11130                                  uint32_t flags)
11131 {
11132         struct intel_engine_cs *engine = req->engine;
11133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11134         uint32_t plane_bit = 0;
11135         int len, ret;
11136
11137         switch (intel_crtc->plane) {
11138         case PLANE_A:
11139                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11140                 break;
11141         case PLANE_B:
11142                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11143                 break;
11144         case PLANE_C:
11145                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11146                 break;
11147         default:
11148                 WARN_ONCE(1, "unknown plane in flip command\n");
11149                 return -ENODEV;
11150         }
11151
11152         len = 4;
11153         if (engine->id == RCS) {
11154                 len += 6;
11155                 /*
11156                  * On Gen 8, SRM is now taking an extra dword to accommodate
11157                  * 48bits addresses, and we need a NOOP for the batch size to
11158                  * stay even.
11159                  */
11160                 if (IS_GEN8(dev))
11161                         len += 2;
11162         }
11163
11164         /*
11165          * BSpec MI_DISPLAY_FLIP for IVB:
11166          * "The full packet must be contained within the same cache line."
11167          *
11168          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11169          * cacheline, if we ever start emitting more commands before
11170          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11171          * then do the cacheline alignment, and finally emit the
11172          * MI_DISPLAY_FLIP.
11173          */
11174         ret = intel_ring_cacheline_align(req);
11175         if (ret)
11176                 return ret;
11177
11178         ret = intel_ring_begin(req, len);
11179         if (ret)
11180                 return ret;
11181
11182         /* Unmask the flip-done completion message. Note that the bspec says that
11183          * we should do this for both the BCS and RCS, and that we must not unmask
11184          * more than one flip event at any time (or ensure that one flip message
11185          * can be sent by waiting for flip-done prior to queueing new flips).
11186          * Experimentation says that BCS works despite DERRMR masking all
11187          * flip-done completion events and that unmasking all planes at once
11188          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11189          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11190          */
11191         if (engine->id == RCS) {
11192                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11193                 intel_ring_emit_reg(engine, DERRMR);
11194                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11195                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11196                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11197                 if (IS_GEN8(dev))
11198                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11199                                               MI_SRM_LRM_GLOBAL_GTT);
11200                 else
11201                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11202                                               MI_SRM_LRM_GLOBAL_GTT);
11203                 intel_ring_emit_reg(engine, DERRMR);
11204                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11205                 if (IS_GEN8(dev)) {
11206                         intel_ring_emit(engine, 0);
11207                         intel_ring_emit(engine, MI_NOOP);
11208                 }
11209         }
11210
11211         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11212         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11213         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11214         intel_ring_emit(engine, (MI_NOOP));
11215
11216         intel_mark_page_flip_active(intel_crtc->unpin_work);
11217         return 0;
11218 }
11219
11220 static bool use_mmio_flip(struct intel_engine_cs *engine,
11221                           struct drm_i915_gem_object *obj)
11222 {
11223         /*
11224          * This is not being used for older platforms, because
11225          * non-availability of flip done interrupt forces us to use
11226          * CS flips. Older platforms derive flip done using some clever
11227          * tricks involving the flip_pending status bits and vblank irqs.
11228          * So using MMIO flips there would disrupt this mechanism.
11229          */
11230
11231         if (engine == NULL)
11232                 return true;
11233
11234         if (INTEL_INFO(engine->dev)->gen < 5)
11235                 return false;
11236
11237         if (i915.use_mmio_flip < 0)
11238                 return false;
11239         else if (i915.use_mmio_flip > 0)
11240                 return true;
11241         else if (i915.enable_execlists)
11242                 return true;
11243         else if (obj->base.dma_buf &&
11244                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11245                                                        false))
11246                 return true;
11247         else
11248                 return engine != i915_gem_request_get_engine(obj->last_write_req);
11249 }
11250
11251 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11252                              unsigned int rotation,
11253                              struct intel_unpin_work *work)
11254 {
11255         struct drm_device *dev = intel_crtc->base.dev;
11256         struct drm_i915_private *dev_priv = dev->dev_private;
11257         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11258         const enum pipe pipe = intel_crtc->pipe;
11259         u32 ctl, stride, tile_height;
11260
11261         ctl = I915_READ(PLANE_CTL(pipe, 0));
11262         ctl &= ~PLANE_CTL_TILED_MASK;
11263         switch (fb->modifier[0]) {
11264         case DRM_FORMAT_MOD_NONE:
11265                 break;
11266         case I915_FORMAT_MOD_X_TILED:
11267                 ctl |= PLANE_CTL_TILED_X;
11268                 break;
11269         case I915_FORMAT_MOD_Y_TILED:
11270                 ctl |= PLANE_CTL_TILED_Y;
11271                 break;
11272         case I915_FORMAT_MOD_Yf_TILED:
11273                 ctl |= PLANE_CTL_TILED_YF;
11274                 break;
11275         default:
11276                 MISSING_CASE(fb->modifier[0]);
11277         }
11278
11279         /*
11280          * The stride is either expressed as a multiple of 64 bytes chunks for
11281          * linear buffers or in number of tiles for tiled buffers.
11282          */
11283         if (intel_rotation_90_or_270(rotation)) {
11284                 /* stride = Surface height in tiles */
11285                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11286                 stride = DIV_ROUND_UP(fb->height, tile_height);
11287         } else {
11288                 stride = fb->pitches[0] /
11289                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11290                                                   fb->pixel_format);
11291         }
11292
11293         /*
11294          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11295          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11296          */
11297         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11298         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11299
11300         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11301         POSTING_READ(PLANE_SURF(pipe, 0));
11302 }
11303
11304 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11305                              struct intel_unpin_work *work)
11306 {
11307         struct drm_device *dev = intel_crtc->base.dev;
11308         struct drm_i915_private *dev_priv = dev->dev_private;
11309         struct intel_framebuffer *intel_fb =
11310                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11311         struct drm_i915_gem_object *obj = intel_fb->obj;
11312         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11313         u32 dspcntr;
11314
11315         dspcntr = I915_READ(reg);
11316
11317         if (obj->tiling_mode != I915_TILING_NONE)
11318                 dspcntr |= DISPPLANE_TILED;
11319         else
11320                 dspcntr &= ~DISPPLANE_TILED;
11321
11322         I915_WRITE(reg, dspcntr);
11323
11324         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11325         POSTING_READ(DSPSURF(intel_crtc->plane));
11326 }
11327
11328 /*
11329  * XXX: This is the temporary way to update the plane registers until we get
11330  * around to using the usual plane update functions for MMIO flips
11331  */
11332 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11333 {
11334         struct intel_crtc *crtc = mmio_flip->crtc;
11335         struct intel_unpin_work *work;
11336
11337         spin_lock_irq(&crtc->base.dev->event_lock);
11338         work = crtc->unpin_work;
11339         spin_unlock_irq(&crtc->base.dev->event_lock);
11340         if (work == NULL)
11341                 return;
11342
11343         intel_mark_page_flip_active(work);
11344
11345         intel_pipe_update_start(crtc);
11346
11347         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11348                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11349         else
11350                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11351                 ilk_do_mmio_flip(crtc, work);
11352
11353         intel_pipe_update_end(crtc);
11354 }
11355
11356 static void intel_mmio_flip_work_func(struct work_struct *work)
11357 {
11358         struct intel_mmio_flip *mmio_flip =
11359                 container_of(work, struct intel_mmio_flip, work);
11360         struct intel_framebuffer *intel_fb =
11361                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11362         struct drm_i915_gem_object *obj = intel_fb->obj;
11363
11364         if (mmio_flip->req) {
11365                 WARN_ON(__i915_wait_request(mmio_flip->req,
11366                                             false, NULL,
11367                                             &mmio_flip->i915->rps.mmioflips));
11368                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11369         }
11370
11371         /* For framebuffer backed by dmabuf, wait for fence */
11372         if (obj->base.dma_buf)
11373                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11374                                                             false, false,
11375                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11376
11377         intel_do_mmio_flip(mmio_flip);
11378         kfree(mmio_flip);
11379 }
11380
11381 static int intel_queue_mmio_flip(struct drm_device *dev,
11382                                  struct drm_crtc *crtc,
11383                                  struct drm_i915_gem_object *obj)
11384 {
11385         struct intel_mmio_flip *mmio_flip;
11386
11387         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11388         if (mmio_flip == NULL)
11389                 return -ENOMEM;
11390
11391         mmio_flip->i915 = to_i915(dev);
11392         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11393         mmio_flip->crtc = to_intel_crtc(crtc);
11394         mmio_flip->rotation = crtc->primary->state->rotation;
11395
11396         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11397         schedule_work(&mmio_flip->work);
11398
11399         return 0;
11400 }
11401
11402 static int intel_default_queue_flip(struct drm_device *dev,
11403                                     struct drm_crtc *crtc,
11404                                     struct drm_framebuffer *fb,
11405                                     struct drm_i915_gem_object *obj,
11406                                     struct drm_i915_gem_request *req,
11407                                     uint32_t flags)
11408 {
11409         return -ENODEV;
11410 }
11411
11412 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11413                                          struct drm_crtc *crtc)
11414 {
11415         struct drm_i915_private *dev_priv = dev->dev_private;
11416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11417         struct intel_unpin_work *work = intel_crtc->unpin_work;
11418         u32 addr;
11419
11420         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11421                 return true;
11422
11423         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11424                 return false;
11425
11426         if (!work->enable_stall_check)
11427                 return false;
11428
11429         if (work->flip_ready_vblank == 0) {
11430                 if (work->flip_queued_req &&
11431                     !i915_gem_request_completed(work->flip_queued_req, true))
11432                         return false;
11433
11434                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11435         }
11436
11437         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11438                 return false;
11439
11440         /* Potential stall - if we see that the flip has happened,
11441          * assume a missed interrupt. */
11442         if (INTEL_INFO(dev)->gen >= 4)
11443                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11444         else
11445                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11446
11447         /* There is a potential issue here with a false positive after a flip
11448          * to the same address. We could address this by checking for a
11449          * non-incrementing frame counter.
11450          */
11451         return addr == work->gtt_offset;
11452 }
11453
11454 void intel_check_page_flip(struct drm_device *dev, int pipe)
11455 {
11456         struct drm_i915_private *dev_priv = dev->dev_private;
11457         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11459         struct intel_unpin_work *work;
11460
11461         WARN_ON(!in_interrupt());
11462
11463         if (crtc == NULL)
11464                 return;
11465
11466         spin_lock(&dev->event_lock);
11467         work = intel_crtc->unpin_work;
11468         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11469                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11470                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11471                 page_flip_completed(intel_crtc);
11472                 work = NULL;
11473         }
11474         if (work != NULL &&
11475             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11476                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11477         spin_unlock(&dev->event_lock);
11478 }
11479
11480 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11481                                 struct drm_framebuffer *fb,
11482                                 struct drm_pending_vblank_event *event,
11483                                 uint32_t page_flip_flags)
11484 {
11485         struct drm_device *dev = crtc->dev;
11486         struct drm_i915_private *dev_priv = dev->dev_private;
11487         struct drm_framebuffer *old_fb = crtc->primary->fb;
11488         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11490         struct drm_plane *primary = crtc->primary;
11491         enum pipe pipe = intel_crtc->pipe;
11492         struct intel_unpin_work *work;
11493         struct intel_engine_cs *engine;
11494         bool mmio_flip;
11495         struct drm_i915_gem_request *request = NULL;
11496         int ret;
11497
11498         /*
11499          * drm_mode_page_flip_ioctl() should already catch this, but double
11500          * check to be safe.  In the future we may enable pageflipping from
11501          * a disabled primary plane.
11502          */
11503         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11504                 return -EBUSY;
11505
11506         /* Can't change pixel format via MI display flips. */
11507         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11508                 return -EINVAL;
11509
11510         /*
11511          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11512          * Note that pitch changes could also affect these register.
11513          */
11514         if (INTEL_INFO(dev)->gen > 3 &&
11515             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11516              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11517                 return -EINVAL;
11518
11519         if (i915_terminally_wedged(&dev_priv->gpu_error))
11520                 goto out_hang;
11521
11522         work = kzalloc(sizeof(*work), GFP_KERNEL);
11523         if (work == NULL)
11524                 return -ENOMEM;
11525
11526         work->event = event;
11527         work->crtc = crtc;
11528         work->old_fb = old_fb;
11529         INIT_WORK(&work->work, intel_unpin_work_fn);
11530
11531         ret = drm_crtc_vblank_get(crtc);
11532         if (ret)
11533                 goto free_work;
11534
11535         /* We borrow the event spin lock for protecting unpin_work */
11536         spin_lock_irq(&dev->event_lock);
11537         if (intel_crtc->unpin_work) {
11538                 /* Before declaring the flip queue wedged, check if
11539                  * the hardware completed the operation behind our backs.
11540                  */
11541                 if (__intel_pageflip_stall_check(dev, crtc)) {
11542                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11543                         page_flip_completed(intel_crtc);
11544                 } else {
11545                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11546                         spin_unlock_irq(&dev->event_lock);
11547
11548                         drm_crtc_vblank_put(crtc);
11549                         kfree(work);
11550                         return -EBUSY;
11551                 }
11552         }
11553         intel_crtc->unpin_work = work;
11554         spin_unlock_irq(&dev->event_lock);
11555
11556         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11557                 flush_workqueue(dev_priv->wq);
11558
11559         /* Reference the objects for the scheduled work. */
11560         drm_framebuffer_reference(work->old_fb);
11561         drm_gem_object_reference(&obj->base);
11562
11563         crtc->primary->fb = fb;
11564         update_state_fb(crtc->primary);
11565         intel_fbc_pre_update(intel_crtc);
11566
11567         work->pending_flip_obj = obj;
11568
11569         ret = i915_mutex_lock_interruptible(dev);
11570         if (ret)
11571                 goto cleanup;
11572
11573         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11574         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11575                 ret = -EIO;
11576                 goto cleanup;
11577         }
11578
11579         atomic_inc(&intel_crtc->unpin_work_count);
11580
11581         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11582                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11583
11584         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11585                 engine = &dev_priv->engine[BCS];
11586                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11587                         /* vlv: DISPLAY_FLIP fails to change tiling */
11588                         engine = NULL;
11589         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11590                 engine = &dev_priv->engine[BCS];
11591         } else if (INTEL_INFO(dev)->gen >= 7) {
11592                 engine = i915_gem_request_get_engine(obj->last_write_req);
11593                 if (engine == NULL || engine->id != RCS)
11594                         engine = &dev_priv->engine[BCS];
11595         } else {
11596                 engine = &dev_priv->engine[RCS];
11597         }
11598
11599         mmio_flip = use_mmio_flip(engine, obj);
11600
11601         /* When using CS flips, we want to emit semaphores between rings.
11602          * However, when using mmio flips we will create a task to do the
11603          * synchronisation, so all we want here is to pin the framebuffer
11604          * into the display plane and skip any waits.
11605          */
11606         if (!mmio_flip) {
11607                 ret = i915_gem_object_sync(obj, engine, &request);
11608                 if (ret)
11609                         goto cleanup_pending;
11610         }
11611
11612         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11613         if (ret)
11614                 goto cleanup_pending;
11615
11616         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11617                                                   obj, 0);
11618         work->gtt_offset += intel_crtc->dspaddr_offset;
11619
11620         if (mmio_flip) {
11621                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11622                 if (ret)
11623                         goto cleanup_unpin;
11624
11625                 i915_gem_request_assign(&work->flip_queued_req,
11626                                         obj->last_write_req);
11627         } else {
11628                 if (!request) {
11629                         request = i915_gem_request_alloc(engine, NULL);
11630                         if (IS_ERR(request)) {
11631                                 ret = PTR_ERR(request);
11632                                 goto cleanup_unpin;
11633                         }
11634                 }
11635
11636                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11637                                                    page_flip_flags);
11638                 if (ret)
11639                         goto cleanup_unpin;
11640
11641                 i915_gem_request_assign(&work->flip_queued_req, request);
11642         }
11643
11644         if (request)
11645                 i915_add_request_no_flush(request);
11646
11647         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11648         work->enable_stall_check = true;
11649
11650         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11651                           to_intel_plane(primary)->frontbuffer_bit);
11652         mutex_unlock(&dev->struct_mutex);
11653
11654         intel_frontbuffer_flip_prepare(dev,
11655                                        to_intel_plane(primary)->frontbuffer_bit);
11656
11657         trace_i915_flip_request(intel_crtc->plane, obj);
11658
11659         return 0;
11660
11661 cleanup_unpin:
11662         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11663 cleanup_pending:
11664         if (!IS_ERR_OR_NULL(request))
11665                 i915_add_request_no_flush(request);
11666         atomic_dec(&intel_crtc->unpin_work_count);
11667         mutex_unlock(&dev->struct_mutex);
11668 cleanup:
11669         crtc->primary->fb = old_fb;
11670         update_state_fb(crtc->primary);
11671
11672         drm_gem_object_unreference_unlocked(&obj->base);
11673         drm_framebuffer_unreference(work->old_fb);
11674
11675         spin_lock_irq(&dev->event_lock);
11676         intel_crtc->unpin_work = NULL;
11677         spin_unlock_irq(&dev->event_lock);
11678
11679         drm_crtc_vblank_put(crtc);
11680 free_work:
11681         kfree(work);
11682
11683         if (ret == -EIO) {
11684                 struct drm_atomic_state *state;
11685                 struct drm_plane_state *plane_state;
11686
11687 out_hang:
11688                 state = drm_atomic_state_alloc(dev);
11689                 if (!state)
11690                         return -ENOMEM;
11691                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11692
11693 retry:
11694                 plane_state = drm_atomic_get_plane_state(state, primary);
11695                 ret = PTR_ERR_OR_ZERO(plane_state);
11696                 if (!ret) {
11697                         drm_atomic_set_fb_for_plane(plane_state, fb);
11698
11699                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11700                         if (!ret)
11701                                 ret = drm_atomic_commit(state);
11702                 }
11703
11704                 if (ret == -EDEADLK) {
11705                         drm_modeset_backoff(state->acquire_ctx);
11706                         drm_atomic_state_clear(state);
11707                         goto retry;
11708                 }
11709
11710                 if (ret)
11711                         drm_atomic_state_free(state);
11712
11713                 if (ret == 0 && event) {
11714                         spin_lock_irq(&dev->event_lock);
11715                         drm_crtc_send_vblank_event(crtc, event);
11716                         spin_unlock_irq(&dev->event_lock);
11717                 }
11718         }
11719         return ret;
11720 }
11721
11722
11723 /**
11724  * intel_wm_need_update - Check whether watermarks need updating
11725  * @plane: drm plane
11726  * @state: new plane state
11727  *
11728  * Check current plane state versus the new one to determine whether
11729  * watermarks need to be recalculated.
11730  *
11731  * Returns true or false.
11732  */
11733 static bool intel_wm_need_update(struct drm_plane *plane,
11734                                  struct drm_plane_state *state)
11735 {
11736         struct intel_plane_state *new = to_intel_plane_state(state);
11737         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11738
11739         /* Update watermarks on tiling or size changes. */
11740         if (new->visible != cur->visible)
11741                 return true;
11742
11743         if (!cur->base.fb || !new->base.fb)
11744                 return false;
11745
11746         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11747             cur->base.rotation != new->base.rotation ||
11748             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11749             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11750             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11751             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11752                 return true;
11753
11754         return false;
11755 }
11756
11757 static bool needs_scaling(struct intel_plane_state *state)
11758 {
11759         int src_w = drm_rect_width(&state->src) >> 16;
11760         int src_h = drm_rect_height(&state->src) >> 16;
11761         int dst_w = drm_rect_width(&state->dst);
11762         int dst_h = drm_rect_height(&state->dst);
11763
11764         return (src_w != dst_w || src_h != dst_h);
11765 }
11766
11767 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11768                                     struct drm_plane_state *plane_state)
11769 {
11770         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11771         struct drm_crtc *crtc = crtc_state->crtc;
11772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11773         struct drm_plane *plane = plane_state->plane;
11774         struct drm_device *dev = crtc->dev;
11775         struct drm_i915_private *dev_priv = to_i915(dev);
11776         struct intel_plane_state *old_plane_state =
11777                 to_intel_plane_state(plane->state);
11778         int idx = intel_crtc->base.base.id, ret;
11779         bool mode_changed = needs_modeset(crtc_state);
11780         bool was_crtc_enabled = crtc->state->active;
11781         bool is_crtc_enabled = crtc_state->active;
11782         bool turn_off, turn_on, visible, was_visible;
11783         struct drm_framebuffer *fb = plane_state->fb;
11784
11785         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11786             plane->type != DRM_PLANE_TYPE_CURSOR) {
11787                 ret = skl_update_scaler_plane(
11788                         to_intel_crtc_state(crtc_state),
11789                         to_intel_plane_state(plane_state));
11790                 if (ret)
11791                         return ret;
11792         }
11793
11794         was_visible = old_plane_state->visible;
11795         visible = to_intel_plane_state(plane_state)->visible;
11796
11797         if (!was_crtc_enabled && WARN_ON(was_visible))
11798                 was_visible = false;
11799
11800         /*
11801          * Visibility is calculated as if the crtc was on, but
11802          * after scaler setup everything depends on it being off
11803          * when the crtc isn't active.
11804          */
11805         if (!is_crtc_enabled)
11806                 to_intel_plane_state(plane_state)->visible = visible = false;
11807
11808         if (!was_visible && !visible)
11809                 return 0;
11810
11811         if (fb != old_plane_state->base.fb)
11812                 pipe_config->fb_changed = true;
11813
11814         turn_off = was_visible && (!visible || mode_changed);
11815         turn_on = visible && (!was_visible || mode_changed);
11816
11817         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11818                          plane->base.id, fb ? fb->base.id : -1);
11819
11820         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11821                          plane->base.id, was_visible, visible,
11822                          turn_off, turn_on, mode_changed);
11823
11824         if (turn_on) {
11825                 pipe_config->update_wm_pre = true;
11826
11827                 /* must disable cxsr around plane enable/disable */
11828                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11829                         pipe_config->disable_cxsr = true;
11830         } else if (turn_off) {
11831                 pipe_config->update_wm_post = true;
11832
11833                 /* must disable cxsr around plane enable/disable */
11834                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11835                         pipe_config->disable_cxsr = true;
11836         } else if (intel_wm_need_update(plane, plane_state)) {
11837                 /* FIXME bollocks */
11838                 pipe_config->update_wm_pre = true;
11839                 pipe_config->update_wm_post = true;
11840         }
11841
11842         /* Pre-gen9 platforms need two-step watermark updates */
11843         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11844             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11845                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11846
11847         if (visible || was_visible)
11848                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11849
11850         /*
11851          * WaCxSRDisabledForSpriteScaling:ivb
11852          *
11853          * cstate->update_wm was already set above, so this flag will
11854          * take effect when we commit and program watermarks.
11855          */
11856         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11857             needs_scaling(to_intel_plane_state(plane_state)) &&
11858             !needs_scaling(old_plane_state))
11859                 pipe_config->disable_lp_wm = true;
11860
11861         return 0;
11862 }
11863
11864 static bool encoders_cloneable(const struct intel_encoder *a,
11865                                const struct intel_encoder *b)
11866 {
11867         /* masks could be asymmetric, so check both ways */
11868         return a == b || (a->cloneable & (1 << b->type) &&
11869                           b->cloneable & (1 << a->type));
11870 }
11871
11872 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11873                                          struct intel_crtc *crtc,
11874                                          struct intel_encoder *encoder)
11875 {
11876         struct intel_encoder *source_encoder;
11877         struct drm_connector *connector;
11878         struct drm_connector_state *connector_state;
11879         int i;
11880
11881         for_each_connector_in_state(state, connector, connector_state, i) {
11882                 if (connector_state->crtc != &crtc->base)
11883                         continue;
11884
11885                 source_encoder =
11886                         to_intel_encoder(connector_state->best_encoder);
11887                 if (!encoders_cloneable(encoder, source_encoder))
11888                         return false;
11889         }
11890
11891         return true;
11892 }
11893
11894 static bool check_encoder_cloning(struct drm_atomic_state *state,
11895                                   struct intel_crtc *crtc)
11896 {
11897         struct intel_encoder *encoder;
11898         struct drm_connector *connector;
11899         struct drm_connector_state *connector_state;
11900         int i;
11901
11902         for_each_connector_in_state(state, connector, connector_state, i) {
11903                 if (connector_state->crtc != &crtc->base)
11904                         continue;
11905
11906                 encoder = to_intel_encoder(connector_state->best_encoder);
11907                 if (!check_single_encoder_cloning(state, crtc, encoder))
11908                         return false;
11909         }
11910
11911         return true;
11912 }
11913
11914 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11915                                    struct drm_crtc_state *crtc_state)
11916 {
11917         struct drm_device *dev = crtc->dev;
11918         struct drm_i915_private *dev_priv = dev->dev_private;
11919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11920         struct intel_crtc_state *pipe_config =
11921                 to_intel_crtc_state(crtc_state);
11922         struct drm_atomic_state *state = crtc_state->state;
11923         int ret;
11924         bool mode_changed = needs_modeset(crtc_state);
11925
11926         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11927                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11928                 return -EINVAL;
11929         }
11930
11931         if (mode_changed && !crtc_state->active)
11932                 pipe_config->update_wm_post = true;
11933
11934         if (mode_changed && crtc_state->enable &&
11935             dev_priv->display.crtc_compute_clock &&
11936             !WARN_ON(pipe_config->shared_dpll)) {
11937                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11938                                                            pipe_config);
11939                 if (ret)
11940                         return ret;
11941         }
11942
11943         if (crtc_state->color_mgmt_changed) {
11944                 ret = intel_color_check(crtc, crtc_state);
11945                 if (ret)
11946                         return ret;
11947         }
11948
11949         ret = 0;
11950         if (dev_priv->display.compute_pipe_wm) {
11951                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11952                 if (ret) {
11953                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11954                         return ret;
11955                 }
11956         }
11957
11958         if (dev_priv->display.compute_intermediate_wm &&
11959             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11960                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11961                         return 0;
11962
11963                 /*
11964                  * Calculate 'intermediate' watermarks that satisfy both the
11965                  * old state and the new state.  We can program these
11966                  * immediately.
11967                  */
11968                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11969                                                                 intel_crtc,
11970                                                                 pipe_config);
11971                 if (ret) {
11972                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11973                         return ret;
11974                 }
11975         }
11976
11977         if (INTEL_INFO(dev)->gen >= 9) {
11978                 if (mode_changed)
11979                         ret = skl_update_scaler_crtc(pipe_config);
11980
11981                 if (!ret)
11982                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11983                                                          pipe_config);
11984         }
11985
11986         return ret;
11987 }
11988
11989 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11990         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11991         .atomic_begin = intel_begin_crtc_commit,
11992         .atomic_flush = intel_finish_crtc_commit,
11993         .atomic_check = intel_crtc_atomic_check,
11994 };
11995
11996 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11997 {
11998         struct intel_connector *connector;
11999
12000         for_each_intel_connector(dev, connector) {
12001                 if (connector->base.encoder) {
12002                         connector->base.state->best_encoder =
12003                                 connector->base.encoder;
12004                         connector->base.state->crtc =
12005                                 connector->base.encoder->crtc;
12006                 } else {
12007                         connector->base.state->best_encoder = NULL;
12008                         connector->base.state->crtc = NULL;
12009                 }
12010         }
12011 }
12012
12013 static void
12014 connected_sink_compute_bpp(struct intel_connector *connector,
12015                            struct intel_crtc_state *pipe_config)
12016 {
12017         int bpp = pipe_config->pipe_bpp;
12018
12019         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12020                 connector->base.base.id,
12021                 connector->base.name);
12022
12023         /* Don't use an invalid EDID bpc value */
12024         if (connector->base.display_info.bpc &&
12025             connector->base.display_info.bpc * 3 < bpp) {
12026                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12027                               bpp, connector->base.display_info.bpc*3);
12028                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12029         }
12030
12031         /* Clamp bpp to default limit on screens without EDID 1.4 */
12032         if (connector->base.display_info.bpc == 0) {
12033                 int type = connector->base.connector_type;
12034                 int clamp_bpp = 24;
12035
12036                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12037                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12038                     type == DRM_MODE_CONNECTOR_eDP)
12039                         clamp_bpp = 18;
12040
12041                 if (bpp > clamp_bpp) {
12042                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12043                                       bpp, clamp_bpp);
12044                         pipe_config->pipe_bpp = clamp_bpp;
12045                 }
12046         }
12047 }
12048
12049 static int
12050 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12051                           struct intel_crtc_state *pipe_config)
12052 {
12053         struct drm_device *dev = crtc->base.dev;
12054         struct drm_atomic_state *state;
12055         struct drm_connector *connector;
12056         struct drm_connector_state *connector_state;
12057         int bpp, i;
12058
12059         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12060                 bpp = 10*3;
12061         else if (INTEL_INFO(dev)->gen >= 5)
12062                 bpp = 12*3;
12063         else
12064                 bpp = 8*3;
12065
12066
12067         pipe_config->pipe_bpp = bpp;
12068
12069         state = pipe_config->base.state;
12070
12071         /* Clamp display bpp to EDID value */
12072         for_each_connector_in_state(state, connector, connector_state, i) {
12073                 if (connector_state->crtc != &crtc->base)
12074                         continue;
12075
12076                 connected_sink_compute_bpp(to_intel_connector(connector),
12077                                            pipe_config);
12078         }
12079
12080         return bpp;
12081 }
12082
12083 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12084 {
12085         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12086                         "type: 0x%x flags: 0x%x\n",
12087                 mode->crtc_clock,
12088                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12089                 mode->crtc_hsync_end, mode->crtc_htotal,
12090                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12091                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12092 }
12093
12094 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12095                                    struct intel_crtc_state *pipe_config,
12096                                    const char *context)
12097 {
12098         struct drm_device *dev = crtc->base.dev;
12099         struct drm_plane *plane;
12100         struct intel_plane *intel_plane;
12101         struct intel_plane_state *state;
12102         struct drm_framebuffer *fb;
12103
12104         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12105                       context, pipe_config, pipe_name(crtc->pipe));
12106
12107         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12108         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12109                       pipe_config->pipe_bpp, pipe_config->dither);
12110         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12111                       pipe_config->has_pch_encoder,
12112                       pipe_config->fdi_lanes,
12113                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12114                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12115                       pipe_config->fdi_m_n.tu);
12116         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12117                       pipe_config->has_dp_encoder,
12118                       pipe_config->lane_count,
12119                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12120                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12121                       pipe_config->dp_m_n.tu);
12122
12123         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12124                       pipe_config->has_dp_encoder,
12125                       pipe_config->lane_count,
12126                       pipe_config->dp_m2_n2.gmch_m,
12127                       pipe_config->dp_m2_n2.gmch_n,
12128                       pipe_config->dp_m2_n2.link_m,
12129                       pipe_config->dp_m2_n2.link_n,
12130                       pipe_config->dp_m2_n2.tu);
12131
12132         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12133                       pipe_config->has_audio,
12134                       pipe_config->has_infoframe);
12135
12136         DRM_DEBUG_KMS("requested mode:\n");
12137         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12138         DRM_DEBUG_KMS("adjusted mode:\n");
12139         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12140         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12141         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12142         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12143                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12144         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12145                       crtc->num_scalers,
12146                       pipe_config->scaler_state.scaler_users,
12147                       pipe_config->scaler_state.scaler_id);
12148         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12149                       pipe_config->gmch_pfit.control,
12150                       pipe_config->gmch_pfit.pgm_ratios,
12151                       pipe_config->gmch_pfit.lvds_border_bits);
12152         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12153                       pipe_config->pch_pfit.pos,
12154                       pipe_config->pch_pfit.size,
12155                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12156         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12157         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12158
12159         if (IS_BROXTON(dev)) {
12160                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12161                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12162                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12163                               pipe_config->ddi_pll_sel,
12164                               pipe_config->dpll_hw_state.ebb0,
12165                               pipe_config->dpll_hw_state.ebb4,
12166                               pipe_config->dpll_hw_state.pll0,
12167                               pipe_config->dpll_hw_state.pll1,
12168                               pipe_config->dpll_hw_state.pll2,
12169                               pipe_config->dpll_hw_state.pll3,
12170                               pipe_config->dpll_hw_state.pll6,
12171                               pipe_config->dpll_hw_state.pll8,
12172                               pipe_config->dpll_hw_state.pll9,
12173                               pipe_config->dpll_hw_state.pll10,
12174                               pipe_config->dpll_hw_state.pcsdw12);
12175         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12176                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12177                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12178                               pipe_config->ddi_pll_sel,
12179                               pipe_config->dpll_hw_state.ctrl1,
12180                               pipe_config->dpll_hw_state.cfgcr1,
12181                               pipe_config->dpll_hw_state.cfgcr2);
12182         } else if (HAS_DDI(dev)) {
12183                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12184                               pipe_config->ddi_pll_sel,
12185                               pipe_config->dpll_hw_state.wrpll,
12186                               pipe_config->dpll_hw_state.spll);
12187         } else {
12188                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12189                               "fp0: 0x%x, fp1: 0x%x\n",
12190                               pipe_config->dpll_hw_state.dpll,
12191                               pipe_config->dpll_hw_state.dpll_md,
12192                               pipe_config->dpll_hw_state.fp0,
12193                               pipe_config->dpll_hw_state.fp1);
12194         }
12195
12196         DRM_DEBUG_KMS("planes on this crtc\n");
12197         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12198                 intel_plane = to_intel_plane(plane);
12199                 if (intel_plane->pipe != crtc->pipe)
12200                         continue;
12201
12202                 state = to_intel_plane_state(plane->state);
12203                 fb = state->base.fb;
12204                 if (!fb) {
12205                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12206                                 "disabled, scaler_id = %d\n",
12207                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12208                                 plane->base.id, intel_plane->pipe,
12209                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12210                                 drm_plane_index(plane), state->scaler_id);
12211                         continue;
12212                 }
12213
12214                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12215                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12216                         plane->base.id, intel_plane->pipe,
12217                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12218                         drm_plane_index(plane));
12219                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12220                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12221                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12222                         state->scaler_id,
12223                         state->src.x1 >> 16, state->src.y1 >> 16,
12224                         drm_rect_width(&state->src) >> 16,
12225                         drm_rect_height(&state->src) >> 16,
12226                         state->dst.x1, state->dst.y1,
12227                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12228         }
12229 }
12230
12231 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12232 {
12233         struct drm_device *dev = state->dev;
12234         struct drm_connector *connector;
12235         unsigned int used_ports = 0;
12236
12237         /*
12238          * Walk the connector list instead of the encoder
12239          * list to detect the problem on ddi platforms
12240          * where there's just one encoder per digital port.
12241          */
12242         drm_for_each_connector(connector, dev) {
12243                 struct drm_connector_state *connector_state;
12244                 struct intel_encoder *encoder;
12245
12246                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12247                 if (!connector_state)
12248                         connector_state = connector->state;
12249
12250                 if (!connector_state->best_encoder)
12251                         continue;
12252
12253                 encoder = to_intel_encoder(connector_state->best_encoder);
12254
12255                 WARN_ON(!connector_state->crtc);
12256
12257                 switch (encoder->type) {
12258                         unsigned int port_mask;
12259                 case INTEL_OUTPUT_UNKNOWN:
12260                         if (WARN_ON(!HAS_DDI(dev)))
12261                                 break;
12262                 case INTEL_OUTPUT_DISPLAYPORT:
12263                 case INTEL_OUTPUT_HDMI:
12264                 case INTEL_OUTPUT_EDP:
12265                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12266
12267                         /* the same port mustn't appear more than once */
12268                         if (used_ports & port_mask)
12269                                 return false;
12270
12271                         used_ports |= port_mask;
12272                 default:
12273                         break;
12274                 }
12275         }
12276
12277         return true;
12278 }
12279
12280 static void
12281 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12282 {
12283         struct drm_crtc_state tmp_state;
12284         struct intel_crtc_scaler_state scaler_state;
12285         struct intel_dpll_hw_state dpll_hw_state;
12286         struct intel_shared_dpll *shared_dpll;
12287         uint32_t ddi_pll_sel;
12288         bool force_thru;
12289
12290         /* FIXME: before the switch to atomic started, a new pipe_config was
12291          * kzalloc'd. Code that depends on any field being zero should be
12292          * fixed, so that the crtc_state can be safely duplicated. For now,
12293          * only fields that are know to not cause problems are preserved. */
12294
12295         tmp_state = crtc_state->base;
12296         scaler_state = crtc_state->scaler_state;
12297         shared_dpll = crtc_state->shared_dpll;
12298         dpll_hw_state = crtc_state->dpll_hw_state;
12299         ddi_pll_sel = crtc_state->ddi_pll_sel;
12300         force_thru = crtc_state->pch_pfit.force_thru;
12301
12302         memset(crtc_state, 0, sizeof *crtc_state);
12303
12304         crtc_state->base = tmp_state;
12305         crtc_state->scaler_state = scaler_state;
12306         crtc_state->shared_dpll = shared_dpll;
12307         crtc_state->dpll_hw_state = dpll_hw_state;
12308         crtc_state->ddi_pll_sel = ddi_pll_sel;
12309         crtc_state->pch_pfit.force_thru = force_thru;
12310 }
12311
12312 static int
12313 intel_modeset_pipe_config(struct drm_crtc *crtc,
12314                           struct intel_crtc_state *pipe_config)
12315 {
12316         struct drm_atomic_state *state = pipe_config->base.state;
12317         struct intel_encoder *encoder;
12318         struct drm_connector *connector;
12319         struct drm_connector_state *connector_state;
12320         int base_bpp, ret = -EINVAL;
12321         int i;
12322         bool retry = true;
12323
12324         clear_intel_crtc_state(pipe_config);
12325
12326         pipe_config->cpu_transcoder =
12327                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12328
12329         /*
12330          * Sanitize sync polarity flags based on requested ones. If neither
12331          * positive or negative polarity is requested, treat this as meaning
12332          * negative polarity.
12333          */
12334         if (!(pipe_config->base.adjusted_mode.flags &
12335               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12336                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12337
12338         if (!(pipe_config->base.adjusted_mode.flags &
12339               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12340                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12341
12342         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12343                                              pipe_config);
12344         if (base_bpp < 0)
12345                 goto fail;
12346
12347         /*
12348          * Determine the real pipe dimensions. Note that stereo modes can
12349          * increase the actual pipe size due to the frame doubling and
12350          * insertion of additional space for blanks between the frame. This
12351          * is stored in the crtc timings. We use the requested mode to do this
12352          * computation to clearly distinguish it from the adjusted mode, which
12353          * can be changed by the connectors in the below retry loop.
12354          */
12355         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12356                                &pipe_config->pipe_src_w,
12357                                &pipe_config->pipe_src_h);
12358
12359 encoder_retry:
12360         /* Ensure the port clock defaults are reset when retrying. */
12361         pipe_config->port_clock = 0;
12362         pipe_config->pixel_multiplier = 1;
12363
12364         /* Fill in default crtc timings, allow encoders to overwrite them. */
12365         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12366                               CRTC_STEREO_DOUBLE);
12367
12368         /* Pass our mode to the connectors and the CRTC to give them a chance to
12369          * adjust it according to limitations or connector properties, and also
12370          * a chance to reject the mode entirely.
12371          */
12372         for_each_connector_in_state(state, connector, connector_state, i) {
12373                 if (connector_state->crtc != crtc)
12374                         continue;
12375
12376                 encoder = to_intel_encoder(connector_state->best_encoder);
12377
12378                 if (!(encoder->compute_config(encoder, pipe_config))) {
12379                         DRM_DEBUG_KMS("Encoder config failure\n");
12380                         goto fail;
12381                 }
12382         }
12383
12384         /* Set default port clock if not overwritten by the encoder. Needs to be
12385          * done afterwards in case the encoder adjusts the mode. */
12386         if (!pipe_config->port_clock)
12387                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12388                         * pipe_config->pixel_multiplier;
12389
12390         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12391         if (ret < 0) {
12392                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12393                 goto fail;
12394         }
12395
12396         if (ret == RETRY) {
12397                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12398                         ret = -EINVAL;
12399                         goto fail;
12400                 }
12401
12402                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12403                 retry = false;
12404                 goto encoder_retry;
12405         }
12406
12407         /* Dithering seems to not pass-through bits correctly when it should, so
12408          * only enable it on 6bpc panels. */
12409         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12410         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12411                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12412
12413 fail:
12414         return ret;
12415 }
12416
12417 static void
12418 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12419 {
12420         struct drm_crtc *crtc;
12421         struct drm_crtc_state *crtc_state;
12422         int i;
12423
12424         /* Double check state. */
12425         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12426                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12427
12428                 /* Update hwmode for vblank functions */
12429                 if (crtc->state->active)
12430                         crtc->hwmode = crtc->state->adjusted_mode;
12431                 else
12432                         crtc->hwmode.crtc_clock = 0;
12433
12434                 /*
12435                  * Update legacy state to satisfy fbc code. This can
12436                  * be removed when fbc uses the atomic state.
12437                  */
12438                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12439                         struct drm_plane_state *plane_state = crtc->primary->state;
12440
12441                         crtc->primary->fb = plane_state->fb;
12442                         crtc->x = plane_state->src_x >> 16;
12443                         crtc->y = plane_state->src_y >> 16;
12444                 }
12445         }
12446 }
12447
12448 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12449 {
12450         int diff;
12451
12452         if (clock1 == clock2)
12453                 return true;
12454
12455         if (!clock1 || !clock2)
12456                 return false;
12457
12458         diff = abs(clock1 - clock2);
12459
12460         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12461                 return true;
12462
12463         return false;
12464 }
12465
12466 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12467         list_for_each_entry((intel_crtc), \
12468                             &(dev)->mode_config.crtc_list, \
12469                             base.head) \
12470                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12471
12472 static bool
12473 intel_compare_m_n(unsigned int m, unsigned int n,
12474                   unsigned int m2, unsigned int n2,
12475                   bool exact)
12476 {
12477         if (m == m2 && n == n2)
12478                 return true;
12479
12480         if (exact || !m || !n || !m2 || !n2)
12481                 return false;
12482
12483         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12484
12485         if (n > n2) {
12486                 while (n > n2) {
12487                         m2 <<= 1;
12488                         n2 <<= 1;
12489                 }
12490         } else if (n < n2) {
12491                 while (n < n2) {
12492                         m <<= 1;
12493                         n <<= 1;
12494                 }
12495         }
12496
12497         if (n != n2)
12498                 return false;
12499
12500         return intel_fuzzy_clock_check(m, m2);
12501 }
12502
12503 static bool
12504 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12505                        struct intel_link_m_n *m2_n2,
12506                        bool adjust)
12507 {
12508         if (m_n->tu == m2_n2->tu &&
12509             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12510                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12511             intel_compare_m_n(m_n->link_m, m_n->link_n,
12512                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12513                 if (adjust)
12514                         *m2_n2 = *m_n;
12515
12516                 return true;
12517         }
12518
12519         return false;
12520 }
12521
12522 static bool
12523 intel_pipe_config_compare(struct drm_device *dev,
12524                           struct intel_crtc_state *current_config,
12525                           struct intel_crtc_state *pipe_config,
12526                           bool adjust)
12527 {
12528         bool ret = true;
12529
12530 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12531         do { \
12532                 if (!adjust) \
12533                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12534                 else \
12535                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12536         } while (0)
12537
12538 #define PIPE_CONF_CHECK_X(name) \
12539         if (current_config->name != pipe_config->name) { \
12540                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12541                           "(expected 0x%08x, found 0x%08x)\n", \
12542                           current_config->name, \
12543                           pipe_config->name); \
12544                 ret = false; \
12545         }
12546
12547 #define PIPE_CONF_CHECK_I(name) \
12548         if (current_config->name != pipe_config->name) { \
12549                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12550                           "(expected %i, found %i)\n", \
12551                           current_config->name, \
12552                           pipe_config->name); \
12553                 ret = false; \
12554         }
12555
12556 #define PIPE_CONF_CHECK_P(name) \
12557         if (current_config->name != pipe_config->name) { \
12558                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12559                           "(expected %p, found %p)\n", \
12560                           current_config->name, \
12561                           pipe_config->name); \
12562                 ret = false; \
12563         }
12564
12565 #define PIPE_CONF_CHECK_M_N(name) \
12566         if (!intel_compare_link_m_n(&current_config->name, \
12567                                     &pipe_config->name,\
12568                                     adjust)) { \
12569                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12570                           "(expected tu %i gmch %i/%i link %i/%i, " \
12571                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12572                           current_config->name.tu, \
12573                           current_config->name.gmch_m, \
12574                           current_config->name.gmch_n, \
12575                           current_config->name.link_m, \
12576                           current_config->name.link_n, \
12577                           pipe_config->name.tu, \
12578                           pipe_config->name.gmch_m, \
12579                           pipe_config->name.gmch_n, \
12580                           pipe_config->name.link_m, \
12581                           pipe_config->name.link_n); \
12582                 ret = false; \
12583         }
12584
12585 /* This is required for BDW+ where there is only one set of registers for
12586  * switching between high and low RR.
12587  * This macro can be used whenever a comparison has to be made between one
12588  * hw state and multiple sw state variables.
12589  */
12590 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12591         if (!intel_compare_link_m_n(&current_config->name, \
12592                                     &pipe_config->name, adjust) && \
12593             !intel_compare_link_m_n(&current_config->alt_name, \
12594                                     &pipe_config->name, adjust)) { \
12595                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12596                           "(expected tu %i gmch %i/%i link %i/%i, " \
12597                           "or tu %i gmch %i/%i link %i/%i, " \
12598                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12599                           current_config->name.tu, \
12600                           current_config->name.gmch_m, \
12601                           current_config->name.gmch_n, \
12602                           current_config->name.link_m, \
12603                           current_config->name.link_n, \
12604                           current_config->alt_name.tu, \
12605                           current_config->alt_name.gmch_m, \
12606                           current_config->alt_name.gmch_n, \
12607                           current_config->alt_name.link_m, \
12608                           current_config->alt_name.link_n, \
12609                           pipe_config->name.tu, \
12610                           pipe_config->name.gmch_m, \
12611                           pipe_config->name.gmch_n, \
12612                           pipe_config->name.link_m, \
12613                           pipe_config->name.link_n); \
12614                 ret = false; \
12615         }
12616
12617 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12618         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12619                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12620                           "(expected %i, found %i)\n", \
12621                           current_config->name & (mask), \
12622                           pipe_config->name & (mask)); \
12623                 ret = false; \
12624         }
12625
12626 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12627         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12628                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12629                           "(expected %i, found %i)\n", \
12630                           current_config->name, \
12631                           pipe_config->name); \
12632                 ret = false; \
12633         }
12634
12635 #define PIPE_CONF_QUIRK(quirk)  \
12636         ((current_config->quirks | pipe_config->quirks) & (quirk))
12637
12638         PIPE_CONF_CHECK_I(cpu_transcoder);
12639
12640         PIPE_CONF_CHECK_I(has_pch_encoder);
12641         PIPE_CONF_CHECK_I(fdi_lanes);
12642         PIPE_CONF_CHECK_M_N(fdi_m_n);
12643
12644         PIPE_CONF_CHECK_I(has_dp_encoder);
12645         PIPE_CONF_CHECK_I(lane_count);
12646
12647         if (INTEL_INFO(dev)->gen < 8) {
12648                 PIPE_CONF_CHECK_M_N(dp_m_n);
12649
12650                 if (current_config->has_drrs)
12651                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12652         } else
12653                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12654
12655         PIPE_CONF_CHECK_I(has_dsi_encoder);
12656
12657         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12658         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12659         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12660         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12661         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12662         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12663
12664         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12665         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12666         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12667         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12668         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12669         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12670
12671         PIPE_CONF_CHECK_I(pixel_multiplier);
12672         PIPE_CONF_CHECK_I(has_hdmi_sink);
12673         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12674             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12675                 PIPE_CONF_CHECK_I(limited_color_range);
12676         PIPE_CONF_CHECK_I(has_infoframe);
12677
12678         PIPE_CONF_CHECK_I(has_audio);
12679
12680         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12681                               DRM_MODE_FLAG_INTERLACE);
12682
12683         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12684                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12685                                       DRM_MODE_FLAG_PHSYNC);
12686                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12687                                       DRM_MODE_FLAG_NHSYNC);
12688                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12689                                       DRM_MODE_FLAG_PVSYNC);
12690                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12691                                       DRM_MODE_FLAG_NVSYNC);
12692         }
12693
12694         PIPE_CONF_CHECK_X(gmch_pfit.control);
12695         /* pfit ratios are autocomputed by the hw on gen4+ */
12696         if (INTEL_INFO(dev)->gen < 4)
12697                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12698         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12699
12700         if (!adjust) {
12701                 PIPE_CONF_CHECK_I(pipe_src_w);
12702                 PIPE_CONF_CHECK_I(pipe_src_h);
12703
12704                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12705                 if (current_config->pch_pfit.enabled) {
12706                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12707                         PIPE_CONF_CHECK_X(pch_pfit.size);
12708                 }
12709
12710                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12711         }
12712
12713         /* BDW+ don't expose a synchronous way to read the state */
12714         if (IS_HASWELL(dev))
12715                 PIPE_CONF_CHECK_I(ips_enabled);
12716
12717         PIPE_CONF_CHECK_I(double_wide);
12718
12719         PIPE_CONF_CHECK_X(ddi_pll_sel);
12720
12721         PIPE_CONF_CHECK_P(shared_dpll);
12722         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12723         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12724         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12725         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12726         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12727         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12728         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12729         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12730         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12731
12732         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12733                 PIPE_CONF_CHECK_I(pipe_bpp);
12734
12735         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12736         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12737
12738 #undef PIPE_CONF_CHECK_X
12739 #undef PIPE_CONF_CHECK_I
12740 #undef PIPE_CONF_CHECK_P
12741 #undef PIPE_CONF_CHECK_FLAGS
12742 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12743 #undef PIPE_CONF_QUIRK
12744 #undef INTEL_ERR_OR_DBG_KMS
12745
12746         return ret;
12747 }
12748
12749 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12750                                            const struct intel_crtc_state *pipe_config)
12751 {
12752         if (pipe_config->has_pch_encoder) {
12753                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12754                                                             &pipe_config->fdi_m_n);
12755                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12756
12757                 /*
12758                  * FDI already provided one idea for the dotclock.
12759                  * Yell if the encoder disagrees.
12760                  */
12761                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12762                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12763                      fdi_dotclock, dotclock);
12764         }
12765 }
12766
12767 static void verify_wm_state(struct drm_crtc *crtc,
12768                             struct drm_crtc_state *new_state)
12769 {
12770         struct drm_device *dev = crtc->dev;
12771         struct drm_i915_private *dev_priv = dev->dev_private;
12772         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12773         struct skl_ddb_entry *hw_entry, *sw_entry;
12774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12775         const enum pipe pipe = intel_crtc->pipe;
12776         int plane;
12777
12778         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12779                 return;
12780
12781         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12782         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12783
12784         /* planes */
12785         for_each_plane(dev_priv, pipe, plane) {
12786                 hw_entry = &hw_ddb.plane[pipe][plane];
12787                 sw_entry = &sw_ddb->plane[pipe][plane];
12788
12789                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12790                         continue;
12791
12792                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12793                           "(expected (%u,%u), found (%u,%u))\n",
12794                           pipe_name(pipe), plane + 1,
12795                           sw_entry->start, sw_entry->end,
12796                           hw_entry->start, hw_entry->end);
12797         }
12798
12799         /* cursor */
12800         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12801         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12802
12803         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12804                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12805                           "(expected (%u,%u), found (%u,%u))\n",
12806                           pipe_name(pipe),
12807                           sw_entry->start, sw_entry->end,
12808                           hw_entry->start, hw_entry->end);
12809         }
12810 }
12811
12812 static void
12813 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12814 {
12815         struct drm_connector *connector;
12816
12817         drm_for_each_connector(connector, dev) {
12818                 struct drm_encoder *encoder = connector->encoder;
12819                 struct drm_connector_state *state = connector->state;
12820
12821                 if (state->crtc != crtc)
12822                         continue;
12823
12824                 intel_connector_verify_state(to_intel_connector(connector));
12825
12826                 I915_STATE_WARN(state->best_encoder != encoder,
12827                      "connector's atomic encoder doesn't match legacy encoder\n");
12828         }
12829 }
12830
12831 static void
12832 verify_encoder_state(struct drm_device *dev)
12833 {
12834         struct intel_encoder *encoder;
12835         struct intel_connector *connector;
12836
12837         for_each_intel_encoder(dev, encoder) {
12838                 bool enabled = false;
12839                 enum pipe pipe;
12840
12841                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12842                               encoder->base.base.id,
12843                               encoder->base.name);
12844
12845                 for_each_intel_connector(dev, connector) {
12846                         if (connector->base.state->best_encoder != &encoder->base)
12847                                 continue;
12848                         enabled = true;
12849
12850                         I915_STATE_WARN(connector->base.state->crtc !=
12851                                         encoder->base.crtc,
12852                              "connector's crtc doesn't match encoder crtc\n");
12853                 }
12854
12855                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12856                      "encoder's enabled state mismatch "
12857                      "(expected %i, found %i)\n",
12858                      !!encoder->base.crtc, enabled);
12859
12860                 if (!encoder->base.crtc) {
12861                         bool active;
12862
12863                         active = encoder->get_hw_state(encoder, &pipe);
12864                         I915_STATE_WARN(active,
12865                              "encoder detached but still enabled on pipe %c.\n",
12866                              pipe_name(pipe));
12867                 }
12868         }
12869 }
12870
12871 static void
12872 verify_crtc_state(struct drm_crtc *crtc,
12873                   struct drm_crtc_state *old_crtc_state,
12874                   struct drm_crtc_state *new_crtc_state)
12875 {
12876         struct drm_device *dev = crtc->dev;
12877         struct drm_i915_private *dev_priv = dev->dev_private;
12878         struct intel_encoder *encoder;
12879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12880         struct intel_crtc_state *pipe_config, *sw_config;
12881         struct drm_atomic_state *old_state;
12882         bool active;
12883
12884         old_state = old_crtc_state->state;
12885         __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12886         pipe_config = to_intel_crtc_state(old_crtc_state);
12887         memset(pipe_config, 0, sizeof(*pipe_config));
12888         pipe_config->base.crtc = crtc;
12889         pipe_config->base.state = old_state;
12890
12891         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12892
12893         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12894
12895         /* hw state is inconsistent with the pipe quirk */
12896         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12897             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12898                 active = new_crtc_state->active;
12899
12900         I915_STATE_WARN(new_crtc_state->active != active,
12901              "crtc active state doesn't match with hw state "
12902              "(expected %i, found %i)\n", new_crtc_state->active, active);
12903
12904         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12905              "transitional active state does not match atomic hw state "
12906              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12907
12908         for_each_encoder_on_crtc(dev, crtc, encoder) {
12909                 enum pipe pipe;
12910
12911                 active = encoder->get_hw_state(encoder, &pipe);
12912                 I915_STATE_WARN(active != new_crtc_state->active,
12913                         "[ENCODER:%i] active %i with crtc active %i\n",
12914                         encoder->base.base.id, active, new_crtc_state->active);
12915
12916                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12917                                 "Encoder connected to wrong pipe %c\n",
12918                                 pipe_name(pipe));
12919
12920                 if (active)
12921                         encoder->get_config(encoder, pipe_config);
12922         }
12923
12924         if (!new_crtc_state->active)
12925                 return;
12926
12927         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12928
12929         sw_config = to_intel_crtc_state(crtc->state);
12930         if (!intel_pipe_config_compare(dev, sw_config,
12931                                        pipe_config, false)) {
12932                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12933                 intel_dump_pipe_config(intel_crtc, pipe_config,
12934                                        "[hw state]");
12935                 intel_dump_pipe_config(intel_crtc, sw_config,
12936                                        "[sw state]");
12937         }
12938 }
12939
12940 static void
12941 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12942                          struct intel_shared_dpll *pll,
12943                          struct drm_crtc *crtc,
12944                          struct drm_crtc_state *new_state)
12945 {
12946         struct intel_dpll_hw_state dpll_hw_state;
12947         unsigned crtc_mask;
12948         bool active;
12949
12950         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12951
12952         DRM_DEBUG_KMS("%s\n", pll->name);
12953
12954         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12955
12956         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12957                 I915_STATE_WARN(!pll->on && pll->active_mask,
12958                      "pll in active use but not on in sw tracking\n");
12959                 I915_STATE_WARN(pll->on && !pll->active_mask,
12960                      "pll is on but not used by any active crtc\n");
12961                 I915_STATE_WARN(pll->on != active,
12962                      "pll on state mismatch (expected %i, found %i)\n",
12963                      pll->on, active);
12964         }
12965
12966         if (!crtc) {
12967                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12968                                 "more active pll users than references: %x vs %x\n",
12969                                 pll->active_mask, pll->config.crtc_mask);
12970
12971                 return;
12972         }
12973
12974         crtc_mask = 1 << drm_crtc_index(crtc);
12975
12976         if (new_state->active)
12977                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12978                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12979                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12980         else
12981                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12982                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12983                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12984
12985         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12986                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12987                         crtc_mask, pll->config.crtc_mask);
12988
12989         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12990                                           &dpll_hw_state,
12991                                           sizeof(dpll_hw_state)),
12992                         "pll hw state mismatch\n");
12993 }
12994
12995 static void
12996 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12997                          struct drm_crtc_state *old_crtc_state,
12998                          struct drm_crtc_state *new_crtc_state)
12999 {
13000         struct drm_i915_private *dev_priv = dev->dev_private;
13001         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13002         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13003
13004         if (new_state->shared_dpll)
13005                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13006
13007         if (old_state->shared_dpll &&
13008             old_state->shared_dpll != new_state->shared_dpll) {
13009                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13010                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13011
13012                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13013                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13014                                 pipe_name(drm_crtc_index(crtc)));
13015                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13016                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13017                                 pipe_name(drm_crtc_index(crtc)));
13018         }
13019 }
13020
13021 static void
13022 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13023                          struct drm_crtc_state *old_state,
13024                          struct drm_crtc_state *new_state)
13025 {
13026         if (!needs_modeset(new_state) &&
13027             !to_intel_crtc_state(new_state)->update_pipe)
13028                 return;
13029
13030         verify_wm_state(crtc, new_state);
13031         verify_connector_state(crtc->dev, crtc);
13032         verify_crtc_state(crtc, old_state, new_state);
13033         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13034 }
13035
13036 static void
13037 verify_disabled_dpll_state(struct drm_device *dev)
13038 {
13039         struct drm_i915_private *dev_priv = dev->dev_private;
13040         int i;
13041
13042         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13043                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13044 }
13045
13046 static void
13047 intel_modeset_verify_disabled(struct drm_device *dev)
13048 {
13049         verify_encoder_state(dev);
13050         verify_connector_state(dev, NULL);
13051         verify_disabled_dpll_state(dev);
13052 }
13053
13054 static void update_scanline_offset(struct intel_crtc *crtc)
13055 {
13056         struct drm_device *dev = crtc->base.dev;
13057
13058         /*
13059          * The scanline counter increments at the leading edge of hsync.
13060          *
13061          * On most platforms it starts counting from vtotal-1 on the
13062          * first active line. That means the scanline counter value is
13063          * always one less than what we would expect. Ie. just after
13064          * start of vblank, which also occurs at start of hsync (on the
13065          * last active line), the scanline counter will read vblank_start-1.
13066          *
13067          * On gen2 the scanline counter starts counting from 1 instead
13068          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13069          * to keep the value positive), instead of adding one.
13070          *
13071          * On HSW+ the behaviour of the scanline counter depends on the output
13072          * type. For DP ports it behaves like most other platforms, but on HDMI
13073          * there's an extra 1 line difference. So we need to add two instead of
13074          * one to the value.
13075          */
13076         if (IS_GEN2(dev)) {
13077                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13078                 int vtotal;
13079
13080                 vtotal = adjusted_mode->crtc_vtotal;
13081                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13082                         vtotal /= 2;
13083
13084                 crtc->scanline_offset = vtotal - 1;
13085         } else if (HAS_DDI(dev) &&
13086                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13087                 crtc->scanline_offset = 2;
13088         } else
13089                 crtc->scanline_offset = 1;
13090 }
13091
13092 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13093 {
13094         struct drm_device *dev = state->dev;
13095         struct drm_i915_private *dev_priv = to_i915(dev);
13096         struct intel_shared_dpll_config *shared_dpll = NULL;
13097         struct drm_crtc *crtc;
13098         struct drm_crtc_state *crtc_state;
13099         int i;
13100
13101         if (!dev_priv->display.crtc_compute_clock)
13102                 return;
13103
13104         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13105                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13106                 struct intel_shared_dpll *old_dpll =
13107                         to_intel_crtc_state(crtc->state)->shared_dpll;
13108
13109                 if (!needs_modeset(crtc_state))
13110                         continue;
13111
13112                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13113
13114                 if (!old_dpll)
13115                         continue;
13116
13117                 if (!shared_dpll)
13118                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13119
13120                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13121         }
13122 }
13123
13124 /*
13125  * This implements the workaround described in the "notes" section of the mode
13126  * set sequence documentation. When going from no pipes or single pipe to
13127  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13128  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13129  */
13130 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13131 {
13132         struct drm_crtc_state *crtc_state;
13133         struct intel_crtc *intel_crtc;
13134         struct drm_crtc *crtc;
13135         struct intel_crtc_state *first_crtc_state = NULL;
13136         struct intel_crtc_state *other_crtc_state = NULL;
13137         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13138         int i;
13139
13140         /* look at all crtc's that are going to be enabled in during modeset */
13141         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13142                 intel_crtc = to_intel_crtc(crtc);
13143
13144                 if (!crtc_state->active || !needs_modeset(crtc_state))
13145                         continue;
13146
13147                 if (first_crtc_state) {
13148                         other_crtc_state = to_intel_crtc_state(crtc_state);
13149                         break;
13150                 } else {
13151                         first_crtc_state = to_intel_crtc_state(crtc_state);
13152                         first_pipe = intel_crtc->pipe;
13153                 }
13154         }
13155
13156         /* No workaround needed? */
13157         if (!first_crtc_state)
13158                 return 0;
13159
13160         /* w/a possibly needed, check how many crtc's are already enabled. */
13161         for_each_intel_crtc(state->dev, intel_crtc) {
13162                 struct intel_crtc_state *pipe_config;
13163
13164                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13165                 if (IS_ERR(pipe_config))
13166                         return PTR_ERR(pipe_config);
13167
13168                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13169
13170                 if (!pipe_config->base.active ||
13171                     needs_modeset(&pipe_config->base))
13172                         continue;
13173
13174                 /* 2 or more enabled crtcs means no need for w/a */
13175                 if (enabled_pipe != INVALID_PIPE)
13176                         return 0;
13177
13178                 enabled_pipe = intel_crtc->pipe;
13179         }
13180
13181         if (enabled_pipe != INVALID_PIPE)
13182                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13183         else if (other_crtc_state)
13184                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13185
13186         return 0;
13187 }
13188
13189 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13190 {
13191         struct drm_crtc *crtc;
13192         struct drm_crtc_state *crtc_state;
13193         int ret = 0;
13194
13195         /* add all active pipes to the state */
13196         for_each_crtc(state->dev, crtc) {
13197                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13198                 if (IS_ERR(crtc_state))
13199                         return PTR_ERR(crtc_state);
13200
13201                 if (!crtc_state->active || needs_modeset(crtc_state))
13202                         continue;
13203
13204                 crtc_state->mode_changed = true;
13205
13206                 ret = drm_atomic_add_affected_connectors(state, crtc);
13207                 if (ret)
13208                         break;
13209
13210                 ret = drm_atomic_add_affected_planes(state, crtc);
13211                 if (ret)
13212                         break;
13213         }
13214
13215         return ret;
13216 }
13217
13218 static int intel_modeset_checks(struct drm_atomic_state *state)
13219 {
13220         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13221         struct drm_i915_private *dev_priv = state->dev->dev_private;
13222         struct drm_crtc *crtc;
13223         struct drm_crtc_state *crtc_state;
13224         int ret = 0, i;
13225
13226         if (!check_digital_port_conflicts(state)) {
13227                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13228                 return -EINVAL;
13229         }
13230
13231         intel_state->modeset = true;
13232         intel_state->active_crtcs = dev_priv->active_crtcs;
13233
13234         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13235                 if (crtc_state->active)
13236                         intel_state->active_crtcs |= 1 << i;
13237                 else
13238                         intel_state->active_crtcs &= ~(1 << i);
13239         }
13240
13241         /*
13242          * See if the config requires any additional preparation, e.g.
13243          * to adjust global state with pipes off.  We need to do this
13244          * here so we can get the modeset_pipe updated config for the new
13245          * mode set on this crtc.  For other crtcs we need to use the
13246          * adjusted_mode bits in the crtc directly.
13247          */
13248         if (dev_priv->display.modeset_calc_cdclk) {
13249                 ret = dev_priv->display.modeset_calc_cdclk(state);
13250
13251                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13252                         ret = intel_modeset_all_pipes(state);
13253
13254                 if (ret < 0)
13255                         return ret;
13256
13257                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13258                               intel_state->cdclk, intel_state->dev_cdclk);
13259         } else
13260                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13261
13262         intel_modeset_clear_plls(state);
13263
13264         if (IS_HASWELL(dev_priv))
13265                 return haswell_mode_set_planes_workaround(state);
13266
13267         return 0;
13268 }
13269
13270 /*
13271  * Handle calculation of various watermark data at the end of the atomic check
13272  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13273  * handlers to ensure that all derived state has been updated.
13274  */
13275 static void calc_watermark_data(struct drm_atomic_state *state)
13276 {
13277         struct drm_device *dev = state->dev;
13278         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13279         struct drm_crtc *crtc;
13280         struct drm_crtc_state *cstate;
13281         struct drm_plane *plane;
13282         struct drm_plane_state *pstate;
13283
13284         /*
13285          * Calculate watermark configuration details now that derived
13286          * plane/crtc state is all properly updated.
13287          */
13288         drm_for_each_crtc(crtc, dev) {
13289                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13290                         crtc->state;
13291
13292                 if (cstate->active)
13293                         intel_state->wm_config.num_pipes_active++;
13294         }
13295         drm_for_each_legacy_plane(plane, dev) {
13296                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13297                         plane->state;
13298
13299                 if (!to_intel_plane_state(pstate)->visible)
13300                         continue;
13301
13302                 intel_state->wm_config.sprites_enabled = true;
13303                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13304                     pstate->crtc_h != pstate->src_h >> 16)
13305                         intel_state->wm_config.sprites_scaled = true;
13306         }
13307 }
13308
13309 /**
13310  * intel_atomic_check - validate state object
13311  * @dev: drm device
13312  * @state: state to validate
13313  */
13314 static int intel_atomic_check(struct drm_device *dev,
13315                               struct drm_atomic_state *state)
13316 {
13317         struct drm_i915_private *dev_priv = to_i915(dev);
13318         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13319         struct drm_crtc *crtc;
13320         struct drm_crtc_state *crtc_state;
13321         int ret, i;
13322         bool any_ms = false;
13323
13324         ret = drm_atomic_helper_check_modeset(dev, state);
13325         if (ret)
13326                 return ret;
13327
13328         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13329                 struct intel_crtc_state *pipe_config =
13330                         to_intel_crtc_state(crtc_state);
13331
13332                 /* Catch I915_MODE_FLAG_INHERITED */
13333                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13334                         crtc_state->mode_changed = true;
13335
13336                 if (!crtc_state->enable) {
13337                         if (needs_modeset(crtc_state))
13338                                 any_ms = true;
13339                         continue;
13340                 }
13341
13342                 if (!needs_modeset(crtc_state))
13343                         continue;
13344
13345                 /* FIXME: For only active_changed we shouldn't need to do any
13346                  * state recomputation at all. */
13347
13348                 ret = drm_atomic_add_affected_connectors(state, crtc);
13349                 if (ret)
13350                         return ret;
13351
13352                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13353                 if (ret)
13354                         return ret;
13355
13356                 if (i915.fastboot &&
13357                     intel_pipe_config_compare(dev,
13358                                         to_intel_crtc_state(crtc->state),
13359                                         pipe_config, true)) {
13360                         crtc_state->mode_changed = false;
13361                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13362                 }
13363
13364                 if (needs_modeset(crtc_state)) {
13365                         any_ms = true;
13366
13367                         ret = drm_atomic_add_affected_planes(state, crtc);
13368                         if (ret)
13369                                 return ret;
13370                 }
13371
13372                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13373                                        needs_modeset(crtc_state) ?
13374                                        "[modeset]" : "[fastset]");
13375         }
13376
13377         if (any_ms) {
13378                 ret = intel_modeset_checks(state);
13379
13380                 if (ret)
13381                         return ret;
13382         } else
13383                 intel_state->cdclk = dev_priv->cdclk_freq;
13384
13385         ret = drm_atomic_helper_check_planes(dev, state);
13386         if (ret)
13387                 return ret;
13388
13389         intel_fbc_choose_crtc(dev_priv, state);
13390         calc_watermark_data(state);
13391
13392         return 0;
13393 }
13394
13395 static int intel_atomic_prepare_commit(struct drm_device *dev,
13396                                        struct drm_atomic_state *state,
13397                                        bool async)
13398 {
13399         struct drm_i915_private *dev_priv = dev->dev_private;
13400         struct drm_plane_state *plane_state;
13401         struct drm_crtc_state *crtc_state;
13402         struct drm_plane *plane;
13403         struct drm_crtc *crtc;
13404         int i, ret;
13405
13406         if (async) {
13407                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13408                 return -EINVAL;
13409         }
13410
13411         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13412                 ret = intel_crtc_wait_for_pending_flips(crtc);
13413                 if (ret)
13414                         return ret;
13415
13416                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13417                         flush_workqueue(dev_priv->wq);
13418         }
13419
13420         ret = mutex_lock_interruptible(&dev->struct_mutex);
13421         if (ret)
13422                 return ret;
13423
13424         ret = drm_atomic_helper_prepare_planes(dev, state);
13425         mutex_unlock(&dev->struct_mutex);
13426
13427         if (!ret && !async) {
13428                 for_each_plane_in_state(state, plane, plane_state, i) {
13429                         struct intel_plane_state *intel_plane_state =
13430                                 to_intel_plane_state(plane_state);
13431
13432                         if (!intel_plane_state->wait_req)
13433                                 continue;
13434
13435                         ret = __i915_wait_request(intel_plane_state->wait_req,
13436                                                   true, NULL, NULL);
13437                         if (ret) {
13438                                 /* Any hang should be swallowed by the wait */
13439                                 WARN_ON(ret == -EIO);
13440                                 mutex_lock(&dev->struct_mutex);
13441                                 drm_atomic_helper_cleanup_planes(dev, state);
13442                                 mutex_unlock(&dev->struct_mutex);
13443                                 break;
13444                         }
13445                 }
13446         }
13447
13448         return ret;
13449 }
13450
13451 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13452                                           struct drm_i915_private *dev_priv,
13453                                           unsigned crtc_mask)
13454 {
13455         unsigned last_vblank_count[I915_MAX_PIPES];
13456         enum pipe pipe;
13457         int ret;
13458
13459         if (!crtc_mask)
13460                 return;
13461
13462         for_each_pipe(dev_priv, pipe) {
13463                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13464
13465                 if (!((1 << pipe) & crtc_mask))
13466                         continue;
13467
13468                 ret = drm_crtc_vblank_get(crtc);
13469                 if (WARN_ON(ret != 0)) {
13470                         crtc_mask &= ~(1 << pipe);
13471                         continue;
13472                 }
13473
13474                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13475         }
13476
13477         for_each_pipe(dev_priv, pipe) {
13478                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13479                 long lret;
13480
13481                 if (!((1 << pipe) & crtc_mask))
13482                         continue;
13483
13484                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13485                                 last_vblank_count[pipe] !=
13486                                         drm_crtc_vblank_count(crtc),
13487                                 msecs_to_jiffies(50));
13488
13489                 WARN_ON(!lret);
13490
13491                 drm_crtc_vblank_put(crtc);
13492         }
13493 }
13494
13495 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13496 {
13497         /* fb updated, need to unpin old fb */
13498         if (crtc_state->fb_changed)
13499                 return true;
13500
13501         /* wm changes, need vblank before final wm's */
13502         if (crtc_state->update_wm_post)
13503                 return true;
13504
13505         /*
13506          * cxsr is re-enabled after vblank.
13507          * This is already handled by crtc_state->update_wm_post,
13508          * but added for clarity.
13509          */
13510         if (crtc_state->disable_cxsr)
13511                 return true;
13512
13513         return false;
13514 }
13515
13516 /**
13517  * intel_atomic_commit - commit validated state object
13518  * @dev: DRM device
13519  * @state: the top-level driver state object
13520  * @async: asynchronous commit
13521  *
13522  * This function commits a top-level state object that has been validated
13523  * with drm_atomic_helper_check().
13524  *
13525  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13526  * we can only handle plane-related operations and do not yet support
13527  * asynchronous commit.
13528  *
13529  * RETURNS
13530  * Zero for success or -errno.
13531  */
13532 static int intel_atomic_commit(struct drm_device *dev,
13533                                struct drm_atomic_state *state,
13534                                bool async)
13535 {
13536         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13537         struct drm_i915_private *dev_priv = dev->dev_private;
13538         struct drm_crtc_state *old_crtc_state;
13539         struct drm_crtc *crtc;
13540         struct intel_crtc_state *intel_cstate;
13541         int ret = 0, i;
13542         bool hw_check = intel_state->modeset;
13543         unsigned long put_domains[I915_MAX_PIPES] = {};
13544         unsigned crtc_vblank_mask = 0;
13545
13546         ret = intel_atomic_prepare_commit(dev, state, async);
13547         if (ret) {
13548                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13549                 return ret;
13550         }
13551
13552         drm_atomic_helper_swap_state(dev, state);
13553         dev_priv->wm.config = intel_state->wm_config;
13554         intel_shared_dpll_commit(state);
13555
13556         if (intel_state->modeset) {
13557                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13558                        sizeof(intel_state->min_pixclk));
13559                 dev_priv->active_crtcs = intel_state->active_crtcs;
13560                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13561
13562                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13563         }
13564
13565         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13566                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13567
13568                 if (needs_modeset(crtc->state) ||
13569                     to_intel_crtc_state(crtc->state)->update_pipe) {
13570                         hw_check = true;
13571
13572                         put_domains[to_intel_crtc(crtc)->pipe] =
13573                                 modeset_get_crtc_power_domains(crtc,
13574                                         to_intel_crtc_state(crtc->state));
13575                 }
13576
13577                 if (!needs_modeset(crtc->state))
13578                         continue;
13579
13580                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13581
13582                 if (old_crtc_state->active) {
13583                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13584                         dev_priv->display.crtc_disable(crtc);
13585                         intel_crtc->active = false;
13586                         intel_fbc_disable(intel_crtc);
13587                         intel_disable_shared_dpll(intel_crtc);
13588
13589                         /*
13590                          * Underruns don't always raise
13591                          * interrupts, so check manually.
13592                          */
13593                         intel_check_cpu_fifo_underruns(dev_priv);
13594                         intel_check_pch_fifo_underruns(dev_priv);
13595
13596                         if (!crtc->state->active)
13597                                 intel_update_watermarks(crtc);
13598                 }
13599         }
13600
13601         /* Only after disabling all output pipelines that will be changed can we
13602          * update the the output configuration. */
13603         intel_modeset_update_crtc_state(state);
13604
13605         if (intel_state->modeset) {
13606                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13607
13608                 if (dev_priv->display.modeset_commit_cdclk &&
13609                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13610                         dev_priv->display.modeset_commit_cdclk(state);
13611
13612                 intel_modeset_verify_disabled(dev);
13613         }
13614
13615         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13616         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13617                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13618                 bool modeset = needs_modeset(crtc->state);
13619                 struct intel_crtc_state *pipe_config =
13620                         to_intel_crtc_state(crtc->state);
13621                 bool update_pipe = !modeset && pipe_config->update_pipe;
13622
13623                 if (modeset && crtc->state->active) {
13624                         update_scanline_offset(to_intel_crtc(crtc));
13625                         dev_priv->display.crtc_enable(crtc);
13626                 }
13627
13628                 if (!modeset)
13629                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13630
13631                 if (crtc->state->active &&
13632                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13633                         intel_fbc_enable(intel_crtc);
13634
13635                 if (crtc->state->active &&
13636                     (crtc->state->planes_changed || update_pipe))
13637                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13638
13639                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13640                         crtc_vblank_mask |= 1 << i;
13641         }
13642
13643         /* FIXME: add subpixel order */
13644
13645         if (!state->legacy_cursor_update)
13646                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13647
13648         /*
13649          * Now that the vblank has passed, we can go ahead and program the
13650          * optimal watermarks on platforms that need two-step watermark
13651          * programming.
13652          *
13653          * TODO: Move this (and other cleanup) to an async worker eventually.
13654          */
13655         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13656                 intel_cstate = to_intel_crtc_state(crtc->state);
13657
13658                 if (dev_priv->display.optimize_watermarks)
13659                         dev_priv->display.optimize_watermarks(intel_cstate);
13660         }
13661
13662         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13663                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13664
13665                 if (put_domains[i])
13666                         modeset_put_power_domains(dev_priv, put_domains[i]);
13667
13668                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13669         }
13670
13671         if (intel_state->modeset)
13672                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13673
13674         mutex_lock(&dev->struct_mutex);
13675         drm_atomic_helper_cleanup_planes(dev, state);
13676         mutex_unlock(&dev->struct_mutex);
13677
13678         drm_atomic_state_free(state);
13679
13680         /* As one of the primary mmio accessors, KMS has a high likelihood
13681          * of triggering bugs in unclaimed access. After we finish
13682          * modesetting, see if an error has been flagged, and if so
13683          * enable debugging for the next modeset - and hope we catch
13684          * the culprit.
13685          *
13686          * XXX note that we assume display power is on at this point.
13687          * This might hold true now but we need to add pm helper to check
13688          * unclaimed only when the hardware is on, as atomic commits
13689          * can happen also when the device is completely off.
13690          */
13691         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13692
13693         return 0;
13694 }
13695
13696 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13697 {
13698         struct drm_device *dev = crtc->dev;
13699         struct drm_atomic_state *state;
13700         struct drm_crtc_state *crtc_state;
13701         int ret;
13702
13703         state = drm_atomic_state_alloc(dev);
13704         if (!state) {
13705                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13706                               crtc->base.id);
13707                 return;
13708         }
13709
13710         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13711
13712 retry:
13713         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13714         ret = PTR_ERR_OR_ZERO(crtc_state);
13715         if (!ret) {
13716                 if (!crtc_state->active)
13717                         goto out;
13718
13719                 crtc_state->mode_changed = true;
13720                 ret = drm_atomic_commit(state);
13721         }
13722
13723         if (ret == -EDEADLK) {
13724                 drm_atomic_state_clear(state);
13725                 drm_modeset_backoff(state->acquire_ctx);
13726                 goto retry;
13727         }
13728
13729         if (ret)
13730 out:
13731                 drm_atomic_state_free(state);
13732 }
13733
13734 #undef for_each_intel_crtc_masked
13735
13736 static const struct drm_crtc_funcs intel_crtc_funcs = {
13737         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13738         .set_config = drm_atomic_helper_set_config,
13739         .set_property = drm_atomic_helper_crtc_set_property,
13740         .destroy = intel_crtc_destroy,
13741         .page_flip = intel_crtc_page_flip,
13742         .atomic_duplicate_state = intel_crtc_duplicate_state,
13743         .atomic_destroy_state = intel_crtc_destroy_state,
13744 };
13745
13746 /**
13747  * intel_prepare_plane_fb - Prepare fb for usage on plane
13748  * @plane: drm plane to prepare for
13749  * @fb: framebuffer to prepare for presentation
13750  *
13751  * Prepares a framebuffer for usage on a display plane.  Generally this
13752  * involves pinning the underlying object and updating the frontbuffer tracking
13753  * bits.  Some older platforms need special physical address handling for
13754  * cursor planes.
13755  *
13756  * Must be called with struct_mutex held.
13757  *
13758  * Returns 0 on success, negative error code on failure.
13759  */
13760 int
13761 intel_prepare_plane_fb(struct drm_plane *plane,
13762                        const struct drm_plane_state *new_state)
13763 {
13764         struct drm_device *dev = plane->dev;
13765         struct drm_framebuffer *fb = new_state->fb;
13766         struct intel_plane *intel_plane = to_intel_plane(plane);
13767         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13768         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13769         int ret = 0;
13770
13771         if (!obj && !old_obj)
13772                 return 0;
13773
13774         if (old_obj) {
13775                 struct drm_crtc_state *crtc_state =
13776                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13777
13778                 /* Big Hammer, we also need to ensure that any pending
13779                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13780                  * current scanout is retired before unpinning the old
13781                  * framebuffer. Note that we rely on userspace rendering
13782                  * into the buffer attached to the pipe they are waiting
13783                  * on. If not, userspace generates a GPU hang with IPEHR
13784                  * point to the MI_WAIT_FOR_EVENT.
13785                  *
13786                  * This should only fail upon a hung GPU, in which case we
13787                  * can safely continue.
13788                  */
13789                 if (needs_modeset(crtc_state))
13790                         ret = i915_gem_object_wait_rendering(old_obj, true);
13791                 if (ret) {
13792                         /* GPU hangs should have been swallowed by the wait */
13793                         WARN_ON(ret == -EIO);
13794                         return ret;
13795                 }
13796         }
13797
13798         /* For framebuffer backed by dmabuf, wait for fence */
13799         if (obj && obj->base.dma_buf) {
13800                 long lret;
13801
13802                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13803                                                            false, true,
13804                                                            MAX_SCHEDULE_TIMEOUT);
13805                 if (lret == -ERESTARTSYS)
13806                         return lret;
13807
13808                 WARN(lret < 0, "waiting returns %li\n", lret);
13809         }
13810
13811         if (!obj) {
13812                 ret = 0;
13813         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13814             INTEL_INFO(dev)->cursor_needs_physical) {
13815                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13816                 ret = i915_gem_object_attach_phys(obj, align);
13817                 if (ret)
13818                         DRM_DEBUG_KMS("failed to attach phys object\n");
13819         } else {
13820                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13821         }
13822
13823         if (ret == 0) {
13824                 if (obj) {
13825                         struct intel_plane_state *plane_state =
13826                                 to_intel_plane_state(new_state);
13827
13828                         i915_gem_request_assign(&plane_state->wait_req,
13829                                                 obj->last_write_req);
13830                 }
13831
13832                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13833         }
13834
13835         return ret;
13836 }
13837
13838 /**
13839  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13840  * @plane: drm plane to clean up for
13841  * @fb: old framebuffer that was on plane
13842  *
13843  * Cleans up a framebuffer that has just been removed from a plane.
13844  *
13845  * Must be called with struct_mutex held.
13846  */
13847 void
13848 intel_cleanup_plane_fb(struct drm_plane *plane,
13849                        const struct drm_plane_state *old_state)
13850 {
13851         struct drm_device *dev = plane->dev;
13852         struct intel_plane *intel_plane = to_intel_plane(plane);
13853         struct intel_plane_state *old_intel_state;
13854         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13855         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13856
13857         old_intel_state = to_intel_plane_state(old_state);
13858
13859         if (!obj && !old_obj)
13860                 return;
13861
13862         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13863             !INTEL_INFO(dev)->cursor_needs_physical))
13864                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13865
13866         /* prepare_fb aborted? */
13867         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13868             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13869                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13870
13871         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13872 }
13873
13874 int
13875 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13876 {
13877         int max_scale;
13878         struct drm_device *dev;
13879         struct drm_i915_private *dev_priv;
13880         int crtc_clock, cdclk;
13881
13882         if (!intel_crtc || !crtc_state->base.enable)
13883                 return DRM_PLANE_HELPER_NO_SCALING;
13884
13885         dev = intel_crtc->base.dev;
13886         dev_priv = dev->dev_private;
13887         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13888         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13889
13890         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13891                 return DRM_PLANE_HELPER_NO_SCALING;
13892
13893         /*
13894          * skl max scale is lower of:
13895          *    close to 3 but not 3, -1 is for that purpose
13896          *            or
13897          *    cdclk/crtc_clock
13898          */
13899         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13900
13901         return max_scale;
13902 }
13903
13904 static int
13905 intel_check_primary_plane(struct drm_plane *plane,
13906                           struct intel_crtc_state *crtc_state,
13907                           struct intel_plane_state *state)
13908 {
13909         struct drm_crtc *crtc = state->base.crtc;
13910         struct drm_framebuffer *fb = state->base.fb;
13911         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13912         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13913         bool can_position = false;
13914
13915         if (INTEL_INFO(plane->dev)->gen >= 9) {
13916                 /* use scaler when colorkey is not required */
13917                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13918                         min_scale = 1;
13919                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13920                 }
13921                 can_position = true;
13922         }
13923
13924         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13925                                              &state->dst, &state->clip,
13926                                              min_scale, max_scale,
13927                                              can_position, true,
13928                                              &state->visible);
13929 }
13930
13931 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13932                                     struct drm_crtc_state *old_crtc_state)
13933 {
13934         struct drm_device *dev = crtc->dev;
13935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13936         struct intel_crtc_state *old_intel_state =
13937                 to_intel_crtc_state(old_crtc_state);
13938         bool modeset = needs_modeset(crtc->state);
13939
13940         /* Perform vblank evasion around commit operation */
13941         intel_pipe_update_start(intel_crtc);
13942
13943         if (modeset)
13944                 return;
13945
13946         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13947                 intel_color_set_csc(crtc->state);
13948                 intel_color_load_luts(crtc->state);
13949         }
13950
13951         if (to_intel_crtc_state(crtc->state)->update_pipe)
13952                 intel_update_pipe_config(intel_crtc, old_intel_state);
13953         else if (INTEL_INFO(dev)->gen >= 9)
13954                 skl_detach_scalers(intel_crtc);
13955 }
13956
13957 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13958                                      struct drm_crtc_state *old_crtc_state)
13959 {
13960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13961
13962         intel_pipe_update_end(intel_crtc);
13963 }
13964
13965 /**
13966  * intel_plane_destroy - destroy a plane
13967  * @plane: plane to destroy
13968  *
13969  * Common destruction function for all types of planes (primary, cursor,
13970  * sprite).
13971  */
13972 void intel_plane_destroy(struct drm_plane *plane)
13973 {
13974         struct intel_plane *intel_plane = to_intel_plane(plane);
13975         drm_plane_cleanup(plane);
13976         kfree(intel_plane);
13977 }
13978
13979 const struct drm_plane_funcs intel_plane_funcs = {
13980         .update_plane = drm_atomic_helper_update_plane,
13981         .disable_plane = drm_atomic_helper_disable_plane,
13982         .destroy = intel_plane_destroy,
13983         .set_property = drm_atomic_helper_plane_set_property,
13984         .atomic_get_property = intel_plane_atomic_get_property,
13985         .atomic_set_property = intel_plane_atomic_set_property,
13986         .atomic_duplicate_state = intel_plane_duplicate_state,
13987         .atomic_destroy_state = intel_plane_destroy_state,
13988
13989 };
13990
13991 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13992                                                     int pipe)
13993 {
13994         struct intel_plane *primary = NULL;
13995         struct intel_plane_state *state = NULL;
13996         const uint32_t *intel_primary_formats;
13997         unsigned int num_formats;
13998         int ret;
13999
14000         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14001         if (!primary)
14002                 goto fail;
14003
14004         state = intel_create_plane_state(&primary->base);
14005         if (!state)
14006                 goto fail;
14007         primary->base.state = &state->base;
14008
14009         primary->can_scale = false;
14010         primary->max_downscale = 1;
14011         if (INTEL_INFO(dev)->gen >= 9) {
14012                 primary->can_scale = true;
14013                 state->scaler_id = -1;
14014         }
14015         primary->pipe = pipe;
14016         primary->plane = pipe;
14017         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14018         primary->check_plane = intel_check_primary_plane;
14019         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14020                 primary->plane = !pipe;
14021
14022         if (INTEL_INFO(dev)->gen >= 9) {
14023                 intel_primary_formats = skl_primary_formats;
14024                 num_formats = ARRAY_SIZE(skl_primary_formats);
14025
14026                 primary->update_plane = skylake_update_primary_plane;
14027                 primary->disable_plane = skylake_disable_primary_plane;
14028         } else if (HAS_PCH_SPLIT(dev)) {
14029                 intel_primary_formats = i965_primary_formats;
14030                 num_formats = ARRAY_SIZE(i965_primary_formats);
14031
14032                 primary->update_plane = ironlake_update_primary_plane;
14033                 primary->disable_plane = i9xx_disable_primary_plane;
14034         } else if (INTEL_INFO(dev)->gen >= 4) {
14035                 intel_primary_formats = i965_primary_formats;
14036                 num_formats = ARRAY_SIZE(i965_primary_formats);
14037
14038                 primary->update_plane = i9xx_update_primary_plane;
14039                 primary->disable_plane = i9xx_disable_primary_plane;
14040         } else {
14041                 intel_primary_formats = i8xx_primary_formats;
14042                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14043
14044                 primary->update_plane = i9xx_update_primary_plane;
14045                 primary->disable_plane = i9xx_disable_primary_plane;
14046         }
14047
14048         ret = drm_universal_plane_init(dev, &primary->base, 0,
14049                                        &intel_plane_funcs,
14050                                        intel_primary_formats, num_formats,
14051                                        DRM_PLANE_TYPE_PRIMARY, NULL);
14052         if (ret)
14053                 goto fail;
14054
14055         if (INTEL_INFO(dev)->gen >= 4)
14056                 intel_create_rotation_property(dev, primary);
14057
14058         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14059
14060         return &primary->base;
14061
14062 fail:
14063         kfree(state);
14064         kfree(primary);
14065
14066         return NULL;
14067 }
14068
14069 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14070 {
14071         if (!dev->mode_config.rotation_property) {
14072                 unsigned long flags = BIT(DRM_ROTATE_0) |
14073                         BIT(DRM_ROTATE_180);
14074
14075                 if (INTEL_INFO(dev)->gen >= 9)
14076                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14077
14078                 dev->mode_config.rotation_property =
14079                         drm_mode_create_rotation_property(dev, flags);
14080         }
14081         if (dev->mode_config.rotation_property)
14082                 drm_object_attach_property(&plane->base.base,
14083                                 dev->mode_config.rotation_property,
14084                                 plane->base.state->rotation);
14085 }
14086
14087 static int
14088 intel_check_cursor_plane(struct drm_plane *plane,
14089                          struct intel_crtc_state *crtc_state,
14090                          struct intel_plane_state *state)
14091 {
14092         struct drm_crtc *crtc = crtc_state->base.crtc;
14093         struct drm_framebuffer *fb = state->base.fb;
14094         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14095         enum pipe pipe = to_intel_plane(plane)->pipe;
14096         unsigned stride;
14097         int ret;
14098
14099         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14100                                             &state->dst, &state->clip,
14101                                             DRM_PLANE_HELPER_NO_SCALING,
14102                                             DRM_PLANE_HELPER_NO_SCALING,
14103                                             true, true, &state->visible);
14104         if (ret)
14105                 return ret;
14106
14107         /* if we want to turn off the cursor ignore width and height */
14108         if (!obj)
14109                 return 0;
14110
14111         /* Check for which cursor types we support */
14112         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14113                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14114                           state->base.crtc_w, state->base.crtc_h);
14115                 return -EINVAL;
14116         }
14117
14118         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14119         if (obj->base.size < stride * state->base.crtc_h) {
14120                 DRM_DEBUG_KMS("buffer is too small\n");
14121                 return -ENOMEM;
14122         }
14123
14124         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14125                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14126                 return -EINVAL;
14127         }
14128
14129         /*
14130          * There's something wrong with the cursor on CHV pipe C.
14131          * If it straddles the left edge of the screen then
14132          * moving it away from the edge or disabling it often
14133          * results in a pipe underrun, and often that can lead to
14134          * dead pipe (constant underrun reported, and it scans
14135          * out just a solid color). To recover from that, the
14136          * display power well must be turned off and on again.
14137          * Refuse the put the cursor into that compromised position.
14138          */
14139         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14140             state->visible && state->base.crtc_x < 0) {
14141                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14142                 return -EINVAL;
14143         }
14144
14145         return 0;
14146 }
14147
14148 static void
14149 intel_disable_cursor_plane(struct drm_plane *plane,
14150                            struct drm_crtc *crtc)
14151 {
14152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14153
14154         intel_crtc->cursor_addr = 0;
14155         intel_crtc_update_cursor(crtc, NULL);
14156 }
14157
14158 static void
14159 intel_update_cursor_plane(struct drm_plane *plane,
14160                           const struct intel_crtc_state *crtc_state,
14161                           const struct intel_plane_state *state)
14162 {
14163         struct drm_crtc *crtc = crtc_state->base.crtc;
14164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14165         struct drm_device *dev = plane->dev;
14166         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14167         uint32_t addr;
14168
14169         if (!obj)
14170                 addr = 0;
14171         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14172                 addr = i915_gem_obj_ggtt_offset(obj);
14173         else
14174                 addr = obj->phys_handle->busaddr;
14175
14176         intel_crtc->cursor_addr = addr;
14177         intel_crtc_update_cursor(crtc, state);
14178 }
14179
14180 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14181                                                    int pipe)
14182 {
14183         struct intel_plane *cursor = NULL;
14184         struct intel_plane_state *state = NULL;
14185         int ret;
14186
14187         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14188         if (!cursor)
14189                 goto fail;
14190
14191         state = intel_create_plane_state(&cursor->base);
14192         if (!state)
14193                 goto fail;
14194         cursor->base.state = &state->base;
14195
14196         cursor->can_scale = false;
14197         cursor->max_downscale = 1;
14198         cursor->pipe = pipe;
14199         cursor->plane = pipe;
14200         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14201         cursor->check_plane = intel_check_cursor_plane;
14202         cursor->update_plane = intel_update_cursor_plane;
14203         cursor->disable_plane = intel_disable_cursor_plane;
14204
14205         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14206                                        &intel_plane_funcs,
14207                                        intel_cursor_formats,
14208                                        ARRAY_SIZE(intel_cursor_formats),
14209                                        DRM_PLANE_TYPE_CURSOR, NULL);
14210         if (ret)
14211                 goto fail;
14212
14213         if (INTEL_INFO(dev)->gen >= 4) {
14214                 if (!dev->mode_config.rotation_property)
14215                         dev->mode_config.rotation_property =
14216                                 drm_mode_create_rotation_property(dev,
14217                                                         BIT(DRM_ROTATE_0) |
14218                                                         BIT(DRM_ROTATE_180));
14219                 if (dev->mode_config.rotation_property)
14220                         drm_object_attach_property(&cursor->base.base,
14221                                 dev->mode_config.rotation_property,
14222                                 state->base.rotation);
14223         }
14224
14225         if (INTEL_INFO(dev)->gen >=9)
14226                 state->scaler_id = -1;
14227
14228         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14229
14230         return &cursor->base;
14231
14232 fail:
14233         kfree(state);
14234         kfree(cursor);
14235
14236         return NULL;
14237 }
14238
14239 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14240         struct intel_crtc_state *crtc_state)
14241 {
14242         int i;
14243         struct intel_scaler *intel_scaler;
14244         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14245
14246         for (i = 0; i < intel_crtc->num_scalers; i++) {
14247                 intel_scaler = &scaler_state->scalers[i];
14248                 intel_scaler->in_use = 0;
14249                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14250         }
14251
14252         scaler_state->scaler_id = -1;
14253 }
14254
14255 static void intel_crtc_init(struct drm_device *dev, int pipe)
14256 {
14257         struct drm_i915_private *dev_priv = dev->dev_private;
14258         struct intel_crtc *intel_crtc;
14259         struct intel_crtc_state *crtc_state = NULL;
14260         struct drm_plane *primary = NULL;
14261         struct drm_plane *cursor = NULL;
14262         int ret;
14263
14264         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14265         if (intel_crtc == NULL)
14266                 return;
14267
14268         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14269         if (!crtc_state)
14270                 goto fail;
14271         intel_crtc->config = crtc_state;
14272         intel_crtc->base.state = &crtc_state->base;
14273         crtc_state->base.crtc = &intel_crtc->base;
14274
14275         /* initialize shared scalers */
14276         if (INTEL_INFO(dev)->gen >= 9) {
14277                 if (pipe == PIPE_C)
14278                         intel_crtc->num_scalers = 1;
14279                 else
14280                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14281
14282                 skl_init_scalers(dev, intel_crtc, crtc_state);
14283         }
14284
14285         primary = intel_primary_plane_create(dev, pipe);
14286         if (!primary)
14287                 goto fail;
14288
14289         cursor = intel_cursor_plane_create(dev, pipe);
14290         if (!cursor)
14291                 goto fail;
14292
14293         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14294                                         cursor, &intel_crtc_funcs, NULL);
14295         if (ret)
14296                 goto fail;
14297
14298         /*
14299          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14300          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14301          */
14302         intel_crtc->pipe = pipe;
14303         intel_crtc->plane = pipe;
14304         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14305                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14306                 intel_crtc->plane = !pipe;
14307         }
14308
14309         intel_crtc->cursor_base = ~0;
14310         intel_crtc->cursor_cntl = ~0;
14311         intel_crtc->cursor_size = ~0;
14312
14313         intel_crtc->wm.cxsr_allowed = true;
14314
14315         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14316                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14317         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14318         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14319
14320         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14321
14322         intel_color_init(&intel_crtc->base);
14323
14324         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14325         return;
14326
14327 fail:
14328         if (primary)
14329                 drm_plane_cleanup(primary);
14330         if (cursor)
14331                 drm_plane_cleanup(cursor);
14332         kfree(crtc_state);
14333         kfree(intel_crtc);
14334 }
14335
14336 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14337 {
14338         struct drm_encoder *encoder = connector->base.encoder;
14339         struct drm_device *dev = connector->base.dev;
14340
14341         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14342
14343         if (!encoder || WARN_ON(!encoder->crtc))
14344                 return INVALID_PIPE;
14345
14346         return to_intel_crtc(encoder->crtc)->pipe;
14347 }
14348
14349 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14350                                 struct drm_file *file)
14351 {
14352         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14353         struct drm_crtc *drmmode_crtc;
14354         struct intel_crtc *crtc;
14355
14356         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14357
14358         if (!drmmode_crtc) {
14359                 DRM_ERROR("no such CRTC id\n");
14360                 return -ENOENT;
14361         }
14362
14363         crtc = to_intel_crtc(drmmode_crtc);
14364         pipe_from_crtc_id->pipe = crtc->pipe;
14365
14366         return 0;
14367 }
14368
14369 static int intel_encoder_clones(struct intel_encoder *encoder)
14370 {
14371         struct drm_device *dev = encoder->base.dev;
14372         struct intel_encoder *source_encoder;
14373         int index_mask = 0;
14374         int entry = 0;
14375
14376         for_each_intel_encoder(dev, source_encoder) {
14377                 if (encoders_cloneable(encoder, source_encoder))
14378                         index_mask |= (1 << entry);
14379
14380                 entry++;
14381         }
14382
14383         return index_mask;
14384 }
14385
14386 static bool has_edp_a(struct drm_device *dev)
14387 {
14388         struct drm_i915_private *dev_priv = dev->dev_private;
14389
14390         if (!IS_MOBILE(dev))
14391                 return false;
14392
14393         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14394                 return false;
14395
14396         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14397                 return false;
14398
14399         return true;
14400 }
14401
14402 static bool intel_crt_present(struct drm_device *dev)
14403 {
14404         struct drm_i915_private *dev_priv = dev->dev_private;
14405
14406         if (INTEL_INFO(dev)->gen >= 9)
14407                 return false;
14408
14409         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14410                 return false;
14411
14412         if (IS_CHERRYVIEW(dev))
14413                 return false;
14414
14415         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14416                 return false;
14417
14418         /* DDI E can't be used if DDI A requires 4 lanes */
14419         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14420                 return false;
14421
14422         if (!dev_priv->vbt.int_crt_support)
14423                 return false;
14424
14425         return true;
14426 }
14427
14428 static void intel_setup_outputs(struct drm_device *dev)
14429 {
14430         struct drm_i915_private *dev_priv = dev->dev_private;
14431         struct intel_encoder *encoder;
14432         bool dpd_is_edp = false;
14433
14434         intel_lvds_init(dev);
14435
14436         if (intel_crt_present(dev))
14437                 intel_crt_init(dev);
14438
14439         if (IS_BROXTON(dev)) {
14440                 /*
14441                  * FIXME: Broxton doesn't support port detection via the
14442                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14443                  * detect the ports.
14444                  */
14445                 intel_ddi_init(dev, PORT_A);
14446                 intel_ddi_init(dev, PORT_B);
14447                 intel_ddi_init(dev, PORT_C);
14448
14449                 intel_dsi_init(dev);
14450         } else if (HAS_DDI(dev)) {
14451                 int found;
14452
14453                 /*
14454                  * Haswell uses DDI functions to detect digital outputs.
14455                  * On SKL pre-D0 the strap isn't connected, so we assume
14456                  * it's there.
14457                  */
14458                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14459                 /* WaIgnoreDDIAStrap: skl */
14460                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14461                         intel_ddi_init(dev, PORT_A);
14462
14463                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14464                  * register */
14465                 found = I915_READ(SFUSE_STRAP);
14466
14467                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14468                         intel_ddi_init(dev, PORT_B);
14469                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14470                         intel_ddi_init(dev, PORT_C);
14471                 if (found & SFUSE_STRAP_DDID_DETECTED)
14472                         intel_ddi_init(dev, PORT_D);
14473                 /*
14474                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14475                  */
14476                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14477                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14478                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14479                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14480                         intel_ddi_init(dev, PORT_E);
14481
14482         } else if (HAS_PCH_SPLIT(dev)) {
14483                 int found;
14484                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14485
14486                 if (has_edp_a(dev))
14487                         intel_dp_init(dev, DP_A, PORT_A);
14488
14489                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14490                         /* PCH SDVOB multiplex with HDMIB */
14491                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14492                         if (!found)
14493                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14494                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14495                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14496                 }
14497
14498                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14499                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14500
14501                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14502                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14503
14504                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14505                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14506
14507                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14508                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14509         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14510                 /*
14511                  * The DP_DETECTED bit is the latched state of the DDC
14512                  * SDA pin at boot. However since eDP doesn't require DDC
14513                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14514                  * eDP ports may have been muxed to an alternate function.
14515                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14516                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14517                  * detect eDP ports.
14518                  */
14519                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14520                     !intel_dp_is_edp(dev, PORT_B))
14521                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14522                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14523                     intel_dp_is_edp(dev, PORT_B))
14524                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14525
14526                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14527                     !intel_dp_is_edp(dev, PORT_C))
14528                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14529                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14530                     intel_dp_is_edp(dev, PORT_C))
14531                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14532
14533                 if (IS_CHERRYVIEW(dev)) {
14534                         /* eDP not supported on port D, so don't check VBT */
14535                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14536                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14537                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14538                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14539                 }
14540
14541                 intel_dsi_init(dev);
14542         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14543                 bool found = false;
14544
14545                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14546                         DRM_DEBUG_KMS("probing SDVOB\n");
14547                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14548                         if (!found && IS_G4X(dev)) {
14549                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14550                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14551                         }
14552
14553                         if (!found && IS_G4X(dev))
14554                                 intel_dp_init(dev, DP_B, PORT_B);
14555                 }
14556
14557                 /* Before G4X SDVOC doesn't have its own detect register */
14558
14559                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14560                         DRM_DEBUG_KMS("probing SDVOC\n");
14561                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14562                 }
14563
14564                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14565
14566                         if (IS_G4X(dev)) {
14567                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14568                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14569                         }
14570                         if (IS_G4X(dev))
14571                                 intel_dp_init(dev, DP_C, PORT_C);
14572                 }
14573
14574                 if (IS_G4X(dev) &&
14575                     (I915_READ(DP_D) & DP_DETECTED))
14576                         intel_dp_init(dev, DP_D, PORT_D);
14577         } else if (IS_GEN2(dev))
14578                 intel_dvo_init(dev);
14579
14580         if (SUPPORTS_TV(dev))
14581                 intel_tv_init(dev);
14582
14583         intel_psr_init(dev);
14584
14585         for_each_intel_encoder(dev, encoder) {
14586                 encoder->base.possible_crtcs = encoder->crtc_mask;
14587                 encoder->base.possible_clones =
14588                         intel_encoder_clones(encoder);
14589         }
14590
14591         intel_init_pch_refclk(dev);
14592
14593         drm_helper_move_panel_connectors_to_head(dev);
14594 }
14595
14596 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14597 {
14598         struct drm_device *dev = fb->dev;
14599         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14600
14601         drm_framebuffer_cleanup(fb);
14602         mutex_lock(&dev->struct_mutex);
14603         WARN_ON(!intel_fb->obj->framebuffer_references--);
14604         drm_gem_object_unreference(&intel_fb->obj->base);
14605         mutex_unlock(&dev->struct_mutex);
14606         kfree(intel_fb);
14607 }
14608
14609 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14610                                                 struct drm_file *file,
14611                                                 unsigned int *handle)
14612 {
14613         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14614         struct drm_i915_gem_object *obj = intel_fb->obj;
14615
14616         if (obj->userptr.mm) {
14617                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14618                 return -EINVAL;
14619         }
14620
14621         return drm_gem_handle_create(file, &obj->base, handle);
14622 }
14623
14624 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14625                                         struct drm_file *file,
14626                                         unsigned flags, unsigned color,
14627                                         struct drm_clip_rect *clips,
14628                                         unsigned num_clips)
14629 {
14630         struct drm_device *dev = fb->dev;
14631         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14632         struct drm_i915_gem_object *obj = intel_fb->obj;
14633
14634         mutex_lock(&dev->struct_mutex);
14635         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14636         mutex_unlock(&dev->struct_mutex);
14637
14638         return 0;
14639 }
14640
14641 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14642         .destroy = intel_user_framebuffer_destroy,
14643         .create_handle = intel_user_framebuffer_create_handle,
14644         .dirty = intel_user_framebuffer_dirty,
14645 };
14646
14647 static
14648 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14649                          uint32_t pixel_format)
14650 {
14651         u32 gen = INTEL_INFO(dev)->gen;
14652
14653         if (gen >= 9) {
14654                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14655
14656                 /* "The stride in bytes must not exceed the of the size of 8K
14657                  *  pixels and 32K bytes."
14658                  */
14659                 return min(8192 * cpp, 32768);
14660         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14661                 return 32*1024;
14662         } else if (gen >= 4) {
14663                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14664                         return 16*1024;
14665                 else
14666                         return 32*1024;
14667         } else if (gen >= 3) {
14668                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14669                         return 8*1024;
14670                 else
14671                         return 16*1024;
14672         } else {
14673                 /* XXX DSPC is limited to 4k tiled */
14674                 return 8*1024;
14675         }
14676 }
14677
14678 static int intel_framebuffer_init(struct drm_device *dev,
14679                                   struct intel_framebuffer *intel_fb,
14680                                   struct drm_mode_fb_cmd2 *mode_cmd,
14681                                   struct drm_i915_gem_object *obj)
14682 {
14683         struct drm_i915_private *dev_priv = to_i915(dev);
14684         unsigned int aligned_height;
14685         int ret;
14686         u32 pitch_limit, stride_alignment;
14687
14688         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14689
14690         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14691                 /* Enforce that fb modifier and tiling mode match, but only for
14692                  * X-tiled. This is needed for FBC. */
14693                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14694                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14695                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14696                         return -EINVAL;
14697                 }
14698         } else {
14699                 if (obj->tiling_mode == I915_TILING_X)
14700                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14701                 else if (obj->tiling_mode == I915_TILING_Y) {
14702                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14703                         return -EINVAL;
14704                 }
14705         }
14706
14707         /* Passed in modifier sanity checking. */
14708         switch (mode_cmd->modifier[0]) {
14709         case I915_FORMAT_MOD_Y_TILED:
14710         case I915_FORMAT_MOD_Yf_TILED:
14711                 if (INTEL_INFO(dev)->gen < 9) {
14712                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14713                                   mode_cmd->modifier[0]);
14714                         return -EINVAL;
14715                 }
14716         case DRM_FORMAT_MOD_NONE:
14717         case I915_FORMAT_MOD_X_TILED:
14718                 break;
14719         default:
14720                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14721                           mode_cmd->modifier[0]);
14722                 return -EINVAL;
14723         }
14724
14725         stride_alignment = intel_fb_stride_alignment(dev_priv,
14726                                                      mode_cmd->modifier[0],
14727                                                      mode_cmd->pixel_format);
14728         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14729                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14730                           mode_cmd->pitches[0], stride_alignment);
14731                 return -EINVAL;
14732         }
14733
14734         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14735                                            mode_cmd->pixel_format);
14736         if (mode_cmd->pitches[0] > pitch_limit) {
14737                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14738                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14739                           "tiled" : "linear",
14740                           mode_cmd->pitches[0], pitch_limit);
14741                 return -EINVAL;
14742         }
14743
14744         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14745             mode_cmd->pitches[0] != obj->stride) {
14746                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14747                           mode_cmd->pitches[0], obj->stride);
14748                 return -EINVAL;
14749         }
14750
14751         /* Reject formats not supported by any plane early. */
14752         switch (mode_cmd->pixel_format) {
14753         case DRM_FORMAT_C8:
14754         case DRM_FORMAT_RGB565:
14755         case DRM_FORMAT_XRGB8888:
14756         case DRM_FORMAT_ARGB8888:
14757                 break;
14758         case DRM_FORMAT_XRGB1555:
14759                 if (INTEL_INFO(dev)->gen > 3) {
14760                         DRM_DEBUG("unsupported pixel format: %s\n",
14761                                   drm_get_format_name(mode_cmd->pixel_format));
14762                         return -EINVAL;
14763                 }
14764                 break;
14765         case DRM_FORMAT_ABGR8888:
14766                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14767                     INTEL_INFO(dev)->gen < 9) {
14768                         DRM_DEBUG("unsupported pixel format: %s\n",
14769                                   drm_get_format_name(mode_cmd->pixel_format));
14770                         return -EINVAL;
14771                 }
14772                 break;
14773         case DRM_FORMAT_XBGR8888:
14774         case DRM_FORMAT_XRGB2101010:
14775         case DRM_FORMAT_XBGR2101010:
14776                 if (INTEL_INFO(dev)->gen < 4) {
14777                         DRM_DEBUG("unsupported pixel format: %s\n",
14778                                   drm_get_format_name(mode_cmd->pixel_format));
14779                         return -EINVAL;
14780                 }
14781                 break;
14782         case DRM_FORMAT_ABGR2101010:
14783                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14784                         DRM_DEBUG("unsupported pixel format: %s\n",
14785                                   drm_get_format_name(mode_cmd->pixel_format));
14786                         return -EINVAL;
14787                 }
14788                 break;
14789         case DRM_FORMAT_YUYV:
14790         case DRM_FORMAT_UYVY:
14791         case DRM_FORMAT_YVYU:
14792         case DRM_FORMAT_VYUY:
14793                 if (INTEL_INFO(dev)->gen < 5) {
14794                         DRM_DEBUG("unsupported pixel format: %s\n",
14795                                   drm_get_format_name(mode_cmd->pixel_format));
14796                         return -EINVAL;
14797                 }
14798                 break;
14799         default:
14800                 DRM_DEBUG("unsupported pixel format: %s\n",
14801                           drm_get_format_name(mode_cmd->pixel_format));
14802                 return -EINVAL;
14803         }
14804
14805         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14806         if (mode_cmd->offsets[0] != 0)
14807                 return -EINVAL;
14808
14809         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14810                                                mode_cmd->pixel_format,
14811                                                mode_cmd->modifier[0]);
14812         /* FIXME drm helper for size checks (especially planar formats)? */
14813         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14814                 return -EINVAL;
14815
14816         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14817         intel_fb->obj = obj;
14818
14819         intel_fill_fb_info(dev_priv, &intel_fb->base);
14820
14821         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14822         if (ret) {
14823                 DRM_ERROR("framebuffer init failed %d\n", ret);
14824                 return ret;
14825         }
14826
14827         intel_fb->obj->framebuffer_references++;
14828
14829         return 0;
14830 }
14831
14832 static struct drm_framebuffer *
14833 intel_user_framebuffer_create(struct drm_device *dev,
14834                               struct drm_file *filp,
14835                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14836 {
14837         struct drm_framebuffer *fb;
14838         struct drm_i915_gem_object *obj;
14839         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14840
14841         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14842                                                 mode_cmd.handles[0]));
14843         if (&obj->base == NULL)
14844                 return ERR_PTR(-ENOENT);
14845
14846         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14847         if (IS_ERR(fb))
14848                 drm_gem_object_unreference_unlocked(&obj->base);
14849
14850         return fb;
14851 }
14852
14853 #ifndef CONFIG_DRM_FBDEV_EMULATION
14854 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14855 {
14856 }
14857 #endif
14858
14859 static const struct drm_mode_config_funcs intel_mode_funcs = {
14860         .fb_create = intel_user_framebuffer_create,
14861         .output_poll_changed = intel_fbdev_output_poll_changed,
14862         .atomic_check = intel_atomic_check,
14863         .atomic_commit = intel_atomic_commit,
14864         .atomic_state_alloc = intel_atomic_state_alloc,
14865         .atomic_state_clear = intel_atomic_state_clear,
14866 };
14867
14868 /**
14869  * intel_init_display_hooks - initialize the display modesetting hooks
14870  * @dev_priv: device private
14871  */
14872 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14873 {
14874         if (INTEL_INFO(dev_priv)->gen >= 9) {
14875                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14876                 dev_priv->display.get_initial_plane_config =
14877                         skylake_get_initial_plane_config;
14878                 dev_priv->display.crtc_compute_clock =
14879                         haswell_crtc_compute_clock;
14880                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14881                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14882         } else if (HAS_DDI(dev_priv)) {
14883                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14884                 dev_priv->display.get_initial_plane_config =
14885                         ironlake_get_initial_plane_config;
14886                 dev_priv->display.crtc_compute_clock =
14887                         haswell_crtc_compute_clock;
14888                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14889                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14890         } else if (HAS_PCH_SPLIT(dev_priv)) {
14891                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14892                 dev_priv->display.get_initial_plane_config =
14893                         ironlake_get_initial_plane_config;
14894                 dev_priv->display.crtc_compute_clock =
14895                         ironlake_crtc_compute_clock;
14896                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14897                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14898         } else if (IS_CHERRYVIEW(dev_priv)) {
14899                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14900                 dev_priv->display.get_initial_plane_config =
14901                         i9xx_get_initial_plane_config;
14902                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14903                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14904                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14905         } else if (IS_VALLEYVIEW(dev_priv)) {
14906                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14907                 dev_priv->display.get_initial_plane_config =
14908                         i9xx_get_initial_plane_config;
14909                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14910                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14911                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14912         } else if (IS_G4X(dev_priv)) {
14913                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14914                 dev_priv->display.get_initial_plane_config =
14915                         i9xx_get_initial_plane_config;
14916                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14917                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14918                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14919         } else if (IS_PINEVIEW(dev_priv)) {
14920                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14921                 dev_priv->display.get_initial_plane_config =
14922                         i9xx_get_initial_plane_config;
14923                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14924                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14925                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14926         } else if (!IS_GEN2(dev_priv)) {
14927                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14928                 dev_priv->display.get_initial_plane_config =
14929                         i9xx_get_initial_plane_config;
14930                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14931                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14932                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14933         } else {
14934                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14935                 dev_priv->display.get_initial_plane_config =
14936                         i9xx_get_initial_plane_config;
14937                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14938                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14939                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14940         }
14941
14942         /* Returns the core display clock speed */
14943         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14944                 dev_priv->display.get_display_clock_speed =
14945                         skylake_get_display_clock_speed;
14946         else if (IS_BROXTON(dev_priv))
14947                 dev_priv->display.get_display_clock_speed =
14948                         broxton_get_display_clock_speed;
14949         else if (IS_BROADWELL(dev_priv))
14950                 dev_priv->display.get_display_clock_speed =
14951                         broadwell_get_display_clock_speed;
14952         else if (IS_HASWELL(dev_priv))
14953                 dev_priv->display.get_display_clock_speed =
14954                         haswell_get_display_clock_speed;
14955         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14956                 dev_priv->display.get_display_clock_speed =
14957                         valleyview_get_display_clock_speed;
14958         else if (IS_GEN5(dev_priv))
14959                 dev_priv->display.get_display_clock_speed =
14960                         ilk_get_display_clock_speed;
14961         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14962                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14963                 dev_priv->display.get_display_clock_speed =
14964                         i945_get_display_clock_speed;
14965         else if (IS_GM45(dev_priv))
14966                 dev_priv->display.get_display_clock_speed =
14967                         gm45_get_display_clock_speed;
14968         else if (IS_CRESTLINE(dev_priv))
14969                 dev_priv->display.get_display_clock_speed =
14970                         i965gm_get_display_clock_speed;
14971         else if (IS_PINEVIEW(dev_priv))
14972                 dev_priv->display.get_display_clock_speed =
14973                         pnv_get_display_clock_speed;
14974         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14975                 dev_priv->display.get_display_clock_speed =
14976                         g33_get_display_clock_speed;
14977         else if (IS_I915G(dev_priv))
14978                 dev_priv->display.get_display_clock_speed =
14979                         i915_get_display_clock_speed;
14980         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14981                 dev_priv->display.get_display_clock_speed =
14982                         i9xx_misc_get_display_clock_speed;
14983         else if (IS_I915GM(dev_priv))
14984                 dev_priv->display.get_display_clock_speed =
14985                         i915gm_get_display_clock_speed;
14986         else if (IS_I865G(dev_priv))
14987                 dev_priv->display.get_display_clock_speed =
14988                         i865_get_display_clock_speed;
14989         else if (IS_I85X(dev_priv))
14990                 dev_priv->display.get_display_clock_speed =
14991                         i85x_get_display_clock_speed;
14992         else { /* 830 */
14993                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14994                 dev_priv->display.get_display_clock_speed =
14995                         i830_get_display_clock_speed;
14996         }
14997
14998         if (IS_GEN5(dev_priv)) {
14999                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15000         } else if (IS_GEN6(dev_priv)) {
15001                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15002         } else if (IS_IVYBRIDGE(dev_priv)) {
15003                 /* FIXME: detect B0+ stepping and use auto training */
15004                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15005         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15006                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15007                 if (IS_BROADWELL(dev_priv)) {
15008                         dev_priv->display.modeset_commit_cdclk =
15009                                 broadwell_modeset_commit_cdclk;
15010                         dev_priv->display.modeset_calc_cdclk =
15011                                 broadwell_modeset_calc_cdclk;
15012                 }
15013         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15014                 dev_priv->display.modeset_commit_cdclk =
15015                         valleyview_modeset_commit_cdclk;
15016                 dev_priv->display.modeset_calc_cdclk =
15017                         valleyview_modeset_calc_cdclk;
15018         } else if (IS_BROXTON(dev_priv)) {
15019                 dev_priv->display.modeset_commit_cdclk =
15020                         broxton_modeset_commit_cdclk;
15021                 dev_priv->display.modeset_calc_cdclk =
15022                         broxton_modeset_calc_cdclk;
15023         }
15024
15025         switch (INTEL_INFO(dev_priv)->gen) {
15026         case 2:
15027                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15028                 break;
15029
15030         case 3:
15031                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15032                 break;
15033
15034         case 4:
15035         case 5:
15036                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15037                 break;
15038
15039         case 6:
15040                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15041                 break;
15042         case 7:
15043         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15044                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15045                 break;
15046         case 9:
15047                 /* Drop through - unsupported since execlist only. */
15048         default:
15049                 /* Default just returns -ENODEV to indicate unsupported */
15050                 dev_priv->display.queue_flip = intel_default_queue_flip;
15051         }
15052 }
15053
15054 /*
15055  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15056  * resume, or other times.  This quirk makes sure that's the case for
15057  * affected systems.
15058  */
15059 static void quirk_pipea_force(struct drm_device *dev)
15060 {
15061         struct drm_i915_private *dev_priv = dev->dev_private;
15062
15063         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15064         DRM_INFO("applying pipe a force quirk\n");
15065 }
15066
15067 static void quirk_pipeb_force(struct drm_device *dev)
15068 {
15069         struct drm_i915_private *dev_priv = dev->dev_private;
15070
15071         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15072         DRM_INFO("applying pipe b force quirk\n");
15073 }
15074
15075 /*
15076  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15077  */
15078 static void quirk_ssc_force_disable(struct drm_device *dev)
15079 {
15080         struct drm_i915_private *dev_priv = dev->dev_private;
15081         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15082         DRM_INFO("applying lvds SSC disable quirk\n");
15083 }
15084
15085 /*
15086  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15087  * brightness value
15088  */
15089 static void quirk_invert_brightness(struct drm_device *dev)
15090 {
15091         struct drm_i915_private *dev_priv = dev->dev_private;
15092         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15093         DRM_INFO("applying inverted panel brightness quirk\n");
15094 }
15095
15096 /* Some VBT's incorrectly indicate no backlight is present */
15097 static void quirk_backlight_present(struct drm_device *dev)
15098 {
15099         struct drm_i915_private *dev_priv = dev->dev_private;
15100         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15101         DRM_INFO("applying backlight present quirk\n");
15102 }
15103
15104 struct intel_quirk {
15105         int device;
15106         int subsystem_vendor;
15107         int subsystem_device;
15108         void (*hook)(struct drm_device *dev);
15109 };
15110
15111 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15112 struct intel_dmi_quirk {
15113         void (*hook)(struct drm_device *dev);
15114         const struct dmi_system_id (*dmi_id_list)[];
15115 };
15116
15117 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15118 {
15119         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15120         return 1;
15121 }
15122
15123 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15124         {
15125                 .dmi_id_list = &(const struct dmi_system_id[]) {
15126                         {
15127                                 .callback = intel_dmi_reverse_brightness,
15128                                 .ident = "NCR Corporation",
15129                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15130                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15131                                 },
15132                         },
15133                         { }  /* terminating entry */
15134                 },
15135                 .hook = quirk_invert_brightness,
15136         },
15137 };
15138
15139 static struct intel_quirk intel_quirks[] = {
15140         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15141         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15142
15143         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15144         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15145
15146         /* 830 needs to leave pipe A & dpll A up */
15147         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15148
15149         /* 830 needs to leave pipe B & dpll B up */
15150         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15151
15152         /* Lenovo U160 cannot use SSC on LVDS */
15153         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15154
15155         /* Sony Vaio Y cannot use SSC on LVDS */
15156         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15157
15158         /* Acer Aspire 5734Z must invert backlight brightness */
15159         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15160
15161         /* Acer/eMachines G725 */
15162         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15163
15164         /* Acer/eMachines e725 */
15165         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15166
15167         /* Acer/Packard Bell NCL20 */
15168         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15169
15170         /* Acer Aspire 4736Z */
15171         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15172
15173         /* Acer Aspire 5336 */
15174         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15175
15176         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15177         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15178
15179         /* Acer C720 Chromebook (Core i3 4005U) */
15180         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15181
15182         /* Apple Macbook 2,1 (Core 2 T7400) */
15183         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15184
15185         /* Apple Macbook 4,1 */
15186         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15187
15188         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15189         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15190
15191         /* HP Chromebook 14 (Celeron 2955U) */
15192         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15193
15194         /* Dell Chromebook 11 */
15195         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15196
15197         /* Dell Chromebook 11 (2015 version) */
15198         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15199 };
15200
15201 static void intel_init_quirks(struct drm_device *dev)
15202 {
15203         struct pci_dev *d = dev->pdev;
15204         int i;
15205
15206         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15207                 struct intel_quirk *q = &intel_quirks[i];
15208
15209                 if (d->device == q->device &&
15210                     (d->subsystem_vendor == q->subsystem_vendor ||
15211                      q->subsystem_vendor == PCI_ANY_ID) &&
15212                     (d->subsystem_device == q->subsystem_device ||
15213                      q->subsystem_device == PCI_ANY_ID))
15214                         q->hook(dev);
15215         }
15216         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15217                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15218                         intel_dmi_quirks[i].hook(dev);
15219         }
15220 }
15221
15222 /* Disable the VGA plane that we never use */
15223 static void i915_disable_vga(struct drm_device *dev)
15224 {
15225         struct drm_i915_private *dev_priv = dev->dev_private;
15226         u8 sr1;
15227         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15228
15229         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15230         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15231         outb(SR01, VGA_SR_INDEX);
15232         sr1 = inb(VGA_SR_DATA);
15233         outb(sr1 | 1<<5, VGA_SR_DATA);
15234         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15235         udelay(300);
15236
15237         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15238         POSTING_READ(vga_reg);
15239 }
15240
15241 void intel_modeset_init_hw(struct drm_device *dev)
15242 {
15243         struct drm_i915_private *dev_priv = dev->dev_private;
15244
15245         intel_update_cdclk(dev);
15246
15247         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15248
15249         intel_init_clock_gating(dev);
15250         intel_enable_gt_powersave(dev);
15251 }
15252
15253 /*
15254  * Calculate what we think the watermarks should be for the state we've read
15255  * out of the hardware and then immediately program those watermarks so that
15256  * we ensure the hardware settings match our internal state.
15257  *
15258  * We can calculate what we think WM's should be by creating a duplicate of the
15259  * current state (which was constructed during hardware readout) and running it
15260  * through the atomic check code to calculate new watermark values in the
15261  * state object.
15262  */
15263 static void sanitize_watermarks(struct drm_device *dev)
15264 {
15265         struct drm_i915_private *dev_priv = to_i915(dev);
15266         struct drm_atomic_state *state;
15267         struct drm_crtc *crtc;
15268         struct drm_crtc_state *cstate;
15269         struct drm_modeset_acquire_ctx ctx;
15270         int ret;
15271         int i;
15272
15273         /* Only supported on platforms that use atomic watermark design */
15274         if (!dev_priv->display.optimize_watermarks)
15275                 return;
15276
15277         /*
15278          * We need to hold connection_mutex before calling duplicate_state so
15279          * that the connector loop is protected.
15280          */
15281         drm_modeset_acquire_init(&ctx, 0);
15282 retry:
15283         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15284         if (ret == -EDEADLK) {
15285                 drm_modeset_backoff(&ctx);
15286                 goto retry;
15287         } else if (WARN_ON(ret)) {
15288                 goto fail;
15289         }
15290
15291         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15292         if (WARN_ON(IS_ERR(state)))
15293                 goto fail;
15294
15295         /*
15296          * Hardware readout is the only time we don't want to calculate
15297          * intermediate watermarks (since we don't trust the current
15298          * watermarks).
15299          */
15300         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15301
15302         ret = intel_atomic_check(dev, state);
15303         if (ret) {
15304                 /*
15305                  * If we fail here, it means that the hardware appears to be
15306                  * programmed in a way that shouldn't be possible, given our
15307                  * understanding of watermark requirements.  This might mean a
15308                  * mistake in the hardware readout code or a mistake in the
15309                  * watermark calculations for a given platform.  Raise a WARN
15310                  * so that this is noticeable.
15311                  *
15312                  * If this actually happens, we'll have to just leave the
15313                  * BIOS-programmed watermarks untouched and hope for the best.
15314                  */
15315                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15316                 goto fail;
15317         }
15318
15319         /* Write calculated watermark values back */
15320         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15321         for_each_crtc_in_state(state, crtc, cstate, i) {
15322                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15323
15324                 cs->wm.need_postvbl_update = true;
15325                 dev_priv->display.optimize_watermarks(cs);
15326         }
15327
15328         drm_atomic_state_free(state);
15329 fail:
15330         drm_modeset_drop_locks(&ctx);
15331         drm_modeset_acquire_fini(&ctx);
15332 }
15333
15334 void intel_modeset_init(struct drm_device *dev)
15335 {
15336         struct drm_i915_private *dev_priv = to_i915(dev);
15337         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15338         int sprite, ret;
15339         enum pipe pipe;
15340         struct intel_crtc *crtc;
15341
15342         drm_mode_config_init(dev);
15343
15344         dev->mode_config.min_width = 0;
15345         dev->mode_config.min_height = 0;
15346
15347         dev->mode_config.preferred_depth = 24;
15348         dev->mode_config.prefer_shadow = 1;
15349
15350         dev->mode_config.allow_fb_modifiers = true;
15351
15352         dev->mode_config.funcs = &intel_mode_funcs;
15353
15354         intel_init_quirks(dev);
15355
15356         intel_init_pm(dev);
15357
15358         if (INTEL_INFO(dev)->num_pipes == 0)
15359                 return;
15360
15361         /*
15362          * There may be no VBT; and if the BIOS enabled SSC we can
15363          * just keep using it to avoid unnecessary flicker.  Whereas if the
15364          * BIOS isn't using it, don't assume it will work even if the VBT
15365          * indicates as much.
15366          */
15367         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15368                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15369                                             DREF_SSC1_ENABLE);
15370
15371                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15372                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15373                                      bios_lvds_use_ssc ? "en" : "dis",
15374                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15375                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15376                 }
15377         }
15378
15379         if (IS_GEN2(dev)) {
15380                 dev->mode_config.max_width = 2048;
15381                 dev->mode_config.max_height = 2048;
15382         } else if (IS_GEN3(dev)) {
15383                 dev->mode_config.max_width = 4096;
15384                 dev->mode_config.max_height = 4096;
15385         } else {
15386                 dev->mode_config.max_width = 8192;
15387                 dev->mode_config.max_height = 8192;
15388         }
15389
15390         if (IS_845G(dev) || IS_I865G(dev)) {
15391                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15392                 dev->mode_config.cursor_height = 1023;
15393         } else if (IS_GEN2(dev)) {
15394                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15395                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15396         } else {
15397                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15398                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15399         }
15400
15401         dev->mode_config.fb_base = ggtt->mappable_base;
15402
15403         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15404                       INTEL_INFO(dev)->num_pipes,
15405                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15406
15407         for_each_pipe(dev_priv, pipe) {
15408                 intel_crtc_init(dev, pipe);
15409                 for_each_sprite(dev_priv, pipe, sprite) {
15410                         ret = intel_plane_init(dev, pipe, sprite);
15411                         if (ret)
15412                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15413                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15414                 }
15415         }
15416
15417         intel_update_czclk(dev_priv);
15418         intel_update_rawclk(dev_priv);
15419         intel_update_cdclk(dev);
15420
15421         intel_shared_dpll_init(dev);
15422
15423         /* Just disable it once at startup */
15424         i915_disable_vga(dev);
15425         intel_setup_outputs(dev);
15426
15427         drm_modeset_lock_all(dev);
15428         intel_modeset_setup_hw_state(dev);
15429         drm_modeset_unlock_all(dev);
15430
15431         for_each_intel_crtc(dev, crtc) {
15432                 struct intel_initial_plane_config plane_config = {};
15433
15434                 if (!crtc->active)
15435                         continue;
15436
15437                 /*
15438                  * Note that reserving the BIOS fb up front prevents us
15439                  * from stuffing other stolen allocations like the ring
15440                  * on top.  This prevents some ugliness at boot time, and
15441                  * can even allow for smooth boot transitions if the BIOS
15442                  * fb is large enough for the active pipe configuration.
15443                  */
15444                 dev_priv->display.get_initial_plane_config(crtc,
15445                                                            &plane_config);
15446
15447                 /*
15448                  * If the fb is shared between multiple heads, we'll
15449                  * just get the first one.
15450                  */
15451                 intel_find_initial_plane_obj(crtc, &plane_config);
15452         }
15453
15454         /*
15455          * Make sure hardware watermarks really match the state we read out.
15456          * Note that we need to do this after reconstructing the BIOS fb's
15457          * since the watermark calculation done here will use pstate->fb.
15458          */
15459         sanitize_watermarks(dev);
15460 }
15461
15462 static void intel_enable_pipe_a(struct drm_device *dev)
15463 {
15464         struct intel_connector *connector;
15465         struct drm_connector *crt = NULL;
15466         struct intel_load_detect_pipe load_detect_temp;
15467         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15468
15469         /* We can't just switch on the pipe A, we need to set things up with a
15470          * proper mode and output configuration. As a gross hack, enable pipe A
15471          * by enabling the load detect pipe once. */
15472         for_each_intel_connector(dev, connector) {
15473                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15474                         crt = &connector->base;
15475                         break;
15476                 }
15477         }
15478
15479         if (!crt)
15480                 return;
15481
15482         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15483                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15484 }
15485
15486 static bool
15487 intel_check_plane_mapping(struct intel_crtc *crtc)
15488 {
15489         struct drm_device *dev = crtc->base.dev;
15490         struct drm_i915_private *dev_priv = dev->dev_private;
15491         u32 val;
15492
15493         if (INTEL_INFO(dev)->num_pipes == 1)
15494                 return true;
15495
15496         val = I915_READ(DSPCNTR(!crtc->plane));
15497
15498         if ((val & DISPLAY_PLANE_ENABLE) &&
15499             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15500                 return false;
15501
15502         return true;
15503 }
15504
15505 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15506 {
15507         struct drm_device *dev = crtc->base.dev;
15508         struct intel_encoder *encoder;
15509
15510         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15511                 return true;
15512
15513         return false;
15514 }
15515
15516 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15517 {
15518         struct drm_device *dev = encoder->base.dev;
15519         struct intel_connector *connector;
15520
15521         for_each_connector_on_encoder(dev, &encoder->base, connector)
15522                 return true;
15523
15524         return false;
15525 }
15526
15527 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15528 {
15529         struct drm_device *dev = crtc->base.dev;
15530         struct drm_i915_private *dev_priv = dev->dev_private;
15531         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15532
15533         /* Clear any frame start delays used for debugging left by the BIOS */
15534         if (!transcoder_is_dsi(cpu_transcoder)) {
15535                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15536
15537                 I915_WRITE(reg,
15538                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15539         }
15540
15541         /* restore vblank interrupts to correct state */
15542         drm_crtc_vblank_reset(&crtc->base);
15543         if (crtc->active) {
15544                 struct intel_plane *plane;
15545
15546                 drm_crtc_vblank_on(&crtc->base);
15547
15548                 /* Disable everything but the primary plane */
15549                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15550                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15551                                 continue;
15552
15553                         plane->disable_plane(&plane->base, &crtc->base);
15554                 }
15555         }
15556
15557         /* We need to sanitize the plane -> pipe mapping first because this will
15558          * disable the crtc (and hence change the state) if it is wrong. Note
15559          * that gen4+ has a fixed plane -> pipe mapping.  */
15560         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15561                 bool plane;
15562
15563                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15564                               crtc->base.base.id);
15565
15566                 /* Pipe has the wrong plane attached and the plane is active.
15567                  * Temporarily change the plane mapping and disable everything
15568                  * ...  */
15569                 plane = crtc->plane;
15570                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15571                 crtc->plane = !plane;
15572                 intel_crtc_disable_noatomic(&crtc->base);
15573                 crtc->plane = plane;
15574         }
15575
15576         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15577             crtc->pipe == PIPE_A && !crtc->active) {
15578                 /* BIOS forgot to enable pipe A, this mostly happens after
15579                  * resume. Force-enable the pipe to fix this, the update_dpms
15580                  * call below we restore the pipe to the right state, but leave
15581                  * the required bits on. */
15582                 intel_enable_pipe_a(dev);
15583         }
15584
15585         /* Adjust the state of the output pipe according to whether we
15586          * have active connectors/encoders. */
15587         if (crtc->active && !intel_crtc_has_encoders(crtc))
15588                 intel_crtc_disable_noatomic(&crtc->base);
15589
15590         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15591                 /*
15592                  * We start out with underrun reporting disabled to avoid races.
15593                  * For correct bookkeeping mark this on active crtcs.
15594                  *
15595                  * Also on gmch platforms we dont have any hardware bits to
15596                  * disable the underrun reporting. Which means we need to start
15597                  * out with underrun reporting disabled also on inactive pipes,
15598                  * since otherwise we'll complain about the garbage we read when
15599                  * e.g. coming up after runtime pm.
15600                  *
15601                  * No protection against concurrent access is required - at
15602                  * worst a fifo underrun happens which also sets this to false.
15603                  */
15604                 crtc->cpu_fifo_underrun_disabled = true;
15605                 crtc->pch_fifo_underrun_disabled = true;
15606         }
15607 }
15608
15609 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15610 {
15611         struct intel_connector *connector;
15612         struct drm_device *dev = encoder->base.dev;
15613
15614         /* We need to check both for a crtc link (meaning that the
15615          * encoder is active and trying to read from a pipe) and the
15616          * pipe itself being active. */
15617         bool has_active_crtc = encoder->base.crtc &&
15618                 to_intel_crtc(encoder->base.crtc)->active;
15619
15620         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15621                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15622                               encoder->base.base.id,
15623                               encoder->base.name);
15624
15625                 /* Connector is active, but has no active pipe. This is
15626                  * fallout from our resume register restoring. Disable
15627                  * the encoder manually again. */
15628                 if (encoder->base.crtc) {
15629                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15630                                       encoder->base.base.id,
15631                                       encoder->base.name);
15632                         encoder->disable(encoder);
15633                         if (encoder->post_disable)
15634                                 encoder->post_disable(encoder);
15635                 }
15636                 encoder->base.crtc = NULL;
15637
15638                 /* Inconsistent output/port/pipe state happens presumably due to
15639                  * a bug in one of the get_hw_state functions. Or someplace else
15640                  * in our code, like the register restore mess on resume. Clamp
15641                  * things to off as a safer default. */
15642                 for_each_intel_connector(dev, connector) {
15643                         if (connector->encoder != encoder)
15644                                 continue;
15645                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15646                         connector->base.encoder = NULL;
15647                 }
15648         }
15649         /* Enabled encoders without active connectors will be fixed in
15650          * the crtc fixup. */
15651 }
15652
15653 void i915_redisable_vga_power_on(struct drm_device *dev)
15654 {
15655         struct drm_i915_private *dev_priv = dev->dev_private;
15656         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15657
15658         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15659                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15660                 i915_disable_vga(dev);
15661         }
15662 }
15663
15664 void i915_redisable_vga(struct drm_device *dev)
15665 {
15666         struct drm_i915_private *dev_priv = dev->dev_private;
15667
15668         /* This function can be called both from intel_modeset_setup_hw_state or
15669          * at a very early point in our resume sequence, where the power well
15670          * structures are not yet restored. Since this function is at a very
15671          * paranoid "someone might have enabled VGA while we were not looking"
15672          * level, just check if the power well is enabled instead of trying to
15673          * follow the "don't touch the power well if we don't need it" policy
15674          * the rest of the driver uses. */
15675         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15676                 return;
15677
15678         i915_redisable_vga_power_on(dev);
15679
15680         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15681 }
15682
15683 static bool primary_get_hw_state(struct intel_plane *plane)
15684 {
15685         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15686
15687         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15688 }
15689
15690 /* FIXME read out full plane state for all planes */
15691 static void readout_plane_state(struct intel_crtc *crtc)
15692 {
15693         struct drm_plane *primary = crtc->base.primary;
15694         struct intel_plane_state *plane_state =
15695                 to_intel_plane_state(primary->state);
15696
15697         plane_state->visible = crtc->active &&
15698                 primary_get_hw_state(to_intel_plane(primary));
15699
15700         if (plane_state->visible)
15701                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15702 }
15703
15704 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15705 {
15706         struct drm_i915_private *dev_priv = dev->dev_private;
15707         enum pipe pipe;
15708         struct intel_crtc *crtc;
15709         struct intel_encoder *encoder;
15710         struct intel_connector *connector;
15711         int i;
15712
15713         dev_priv->active_crtcs = 0;
15714
15715         for_each_intel_crtc(dev, crtc) {
15716                 struct intel_crtc_state *crtc_state = crtc->config;
15717                 int pixclk = 0;
15718
15719                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15720                 memset(crtc_state, 0, sizeof(*crtc_state));
15721                 crtc_state->base.crtc = &crtc->base;
15722
15723                 crtc_state->base.active = crtc_state->base.enable =
15724                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15725
15726                 crtc->base.enabled = crtc_state->base.enable;
15727                 crtc->active = crtc_state->base.active;
15728
15729                 if (crtc_state->base.active) {
15730                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15731
15732                         if (IS_BROADWELL(dev_priv)) {
15733                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15734
15735                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15736                                 if (crtc_state->ips_enabled)
15737                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15738                         } else if (IS_VALLEYVIEW(dev_priv) ||
15739                                    IS_CHERRYVIEW(dev_priv) ||
15740                                    IS_BROXTON(dev_priv))
15741                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15742                         else
15743                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15744                 }
15745
15746                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15747
15748                 readout_plane_state(crtc);
15749
15750                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15751                               crtc->base.base.id,
15752                               crtc->active ? "enabled" : "disabled");
15753         }
15754
15755         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15756                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15757
15758                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15759                                                   &pll->config.hw_state);
15760                 pll->config.crtc_mask = 0;
15761                 for_each_intel_crtc(dev, crtc) {
15762                         if (crtc->active && crtc->config->shared_dpll == pll)
15763                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15764                 }
15765                 pll->active_mask = pll->config.crtc_mask;
15766
15767                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15768                               pll->name, pll->config.crtc_mask, pll->on);
15769         }
15770
15771         for_each_intel_encoder(dev, encoder) {
15772                 pipe = 0;
15773
15774                 if (encoder->get_hw_state(encoder, &pipe)) {
15775                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15776                         encoder->base.crtc = &crtc->base;
15777                         encoder->get_config(encoder, crtc->config);
15778                 } else {
15779                         encoder->base.crtc = NULL;
15780                 }
15781
15782                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15783                               encoder->base.base.id,
15784                               encoder->base.name,
15785                               encoder->base.crtc ? "enabled" : "disabled",
15786                               pipe_name(pipe));
15787         }
15788
15789         for_each_intel_connector(dev, connector) {
15790                 if (connector->get_hw_state(connector)) {
15791                         connector->base.dpms = DRM_MODE_DPMS_ON;
15792
15793                         encoder = connector->encoder;
15794                         connector->base.encoder = &encoder->base;
15795
15796                         if (encoder->base.crtc &&
15797                             encoder->base.crtc->state->active) {
15798                                 /*
15799                                  * This has to be done during hardware readout
15800                                  * because anything calling .crtc_disable may
15801                                  * rely on the connector_mask being accurate.
15802                                  */
15803                                 encoder->base.crtc->state->connector_mask |=
15804                                         1 << drm_connector_index(&connector->base);
15805                                 encoder->base.crtc->state->encoder_mask |=
15806                                         1 << drm_encoder_index(&encoder->base);
15807                         }
15808
15809                 } else {
15810                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15811                         connector->base.encoder = NULL;
15812                 }
15813                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15814                               connector->base.base.id,
15815                               connector->base.name,
15816                               connector->base.encoder ? "enabled" : "disabled");
15817         }
15818
15819         for_each_intel_crtc(dev, crtc) {
15820                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15821
15822                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15823                 if (crtc->base.state->active) {
15824                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15825                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15826                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15827
15828                         /*
15829                          * The initial mode needs to be set in order to keep
15830                          * the atomic core happy. It wants a valid mode if the
15831                          * crtc's enabled, so we do the above call.
15832                          *
15833                          * At this point some state updated by the connectors
15834                          * in their ->detect() callback has not run yet, so
15835                          * no recalculation can be done yet.
15836                          *
15837                          * Even if we could do a recalculation and modeset
15838                          * right now it would cause a double modeset if
15839                          * fbdev or userspace chooses a different initial mode.
15840                          *
15841                          * If that happens, someone indicated they wanted a
15842                          * mode change, which means it's safe to do a full
15843                          * recalculation.
15844                          */
15845                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15846
15847                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15848                         update_scanline_offset(crtc);
15849                 }
15850
15851                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15852         }
15853 }
15854
15855 /* Scan out the current hw modeset state,
15856  * and sanitizes it to the current state
15857  */
15858 static void
15859 intel_modeset_setup_hw_state(struct drm_device *dev)
15860 {
15861         struct drm_i915_private *dev_priv = dev->dev_private;
15862         enum pipe pipe;
15863         struct intel_crtc *crtc;
15864         struct intel_encoder *encoder;
15865         int i;
15866
15867         intel_modeset_readout_hw_state(dev);
15868
15869         /* HW state is read out, now we need to sanitize this mess. */
15870         for_each_intel_encoder(dev, encoder) {
15871                 intel_sanitize_encoder(encoder);
15872         }
15873
15874         for_each_pipe(dev_priv, pipe) {
15875                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15876                 intel_sanitize_crtc(crtc);
15877                 intel_dump_pipe_config(crtc, crtc->config,
15878                                        "[setup_hw_state]");
15879         }
15880
15881         intel_modeset_update_connector_atomic_state(dev);
15882
15883         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15884                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15885
15886                 if (!pll->on || pll->active_mask)
15887                         continue;
15888
15889                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15890
15891                 pll->funcs.disable(dev_priv, pll);
15892                 pll->on = false;
15893         }
15894
15895         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15896                 vlv_wm_get_hw_state(dev);
15897         else if (IS_GEN9(dev))
15898                 skl_wm_get_hw_state(dev);
15899         else if (HAS_PCH_SPLIT(dev))
15900                 ilk_wm_get_hw_state(dev);
15901
15902         for_each_intel_crtc(dev, crtc) {
15903                 unsigned long put_domains;
15904
15905                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15906                 if (WARN_ON(put_domains))
15907                         modeset_put_power_domains(dev_priv, put_domains);
15908         }
15909         intel_display_set_init_power(dev_priv, false);
15910
15911         intel_fbc_init_pipe_state(dev_priv);
15912 }
15913
15914 void intel_display_resume(struct drm_device *dev)
15915 {
15916         struct drm_i915_private *dev_priv = to_i915(dev);
15917         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15918         struct drm_modeset_acquire_ctx ctx;
15919         int ret;
15920         bool setup = false;
15921
15922         dev_priv->modeset_restore_state = NULL;
15923
15924         /*
15925          * This is a cludge because with real atomic modeset mode_config.mutex
15926          * won't be taken. Unfortunately some probed state like
15927          * audio_codec_enable is still protected by mode_config.mutex, so lock
15928          * it here for now.
15929          */
15930         mutex_lock(&dev->mode_config.mutex);
15931         drm_modeset_acquire_init(&ctx, 0);
15932
15933 retry:
15934         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15935
15936         if (ret == 0 && !setup) {
15937                 setup = true;
15938
15939                 intel_modeset_setup_hw_state(dev);
15940                 i915_redisable_vga(dev);
15941         }
15942
15943         if (ret == 0 && state) {
15944                 struct drm_crtc_state *crtc_state;
15945                 struct drm_crtc *crtc;
15946                 int i;
15947
15948                 state->acquire_ctx = &ctx;
15949
15950                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15951                         /*
15952                          * Force recalculation even if we restore
15953                          * current state. With fast modeset this may not result
15954                          * in a modeset when the state is compatible.
15955                          */
15956                         crtc_state->mode_changed = true;
15957                 }
15958
15959                 ret = drm_atomic_commit(state);
15960         }
15961
15962         if (ret == -EDEADLK) {
15963                 drm_modeset_backoff(&ctx);
15964                 goto retry;
15965         }
15966
15967         drm_modeset_drop_locks(&ctx);
15968         drm_modeset_acquire_fini(&ctx);
15969         mutex_unlock(&dev->mode_config.mutex);
15970
15971         if (ret) {
15972                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15973                 drm_atomic_state_free(state);
15974         }
15975 }
15976
15977 void intel_modeset_gem_init(struct drm_device *dev)
15978 {
15979         struct drm_crtc *c;
15980         struct drm_i915_gem_object *obj;
15981         int ret;
15982
15983         intel_init_gt_powersave(dev);
15984
15985         intel_modeset_init_hw(dev);
15986
15987         intel_setup_overlay(dev);
15988
15989         /*
15990          * Make sure any fbs we allocated at startup are properly
15991          * pinned & fenced.  When we do the allocation it's too early
15992          * for this.
15993          */
15994         for_each_crtc(dev, c) {
15995                 obj = intel_fb_obj(c->primary->fb);
15996                 if (obj == NULL)
15997                         continue;
15998
15999                 mutex_lock(&dev->struct_mutex);
16000                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16001                                                  c->primary->state->rotation);
16002                 mutex_unlock(&dev->struct_mutex);
16003                 if (ret) {
16004                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16005                                   to_intel_crtc(c)->pipe);
16006                         drm_framebuffer_unreference(c->primary->fb);
16007                         c->primary->fb = NULL;
16008                         c->primary->crtc = c->primary->state->crtc = NULL;
16009                         update_state_fb(c->primary);
16010                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16011                 }
16012         }
16013
16014         intel_backlight_register(dev);
16015 }
16016
16017 void intel_connector_unregister(struct intel_connector *intel_connector)
16018 {
16019         struct drm_connector *connector = &intel_connector->base;
16020
16021         intel_panel_destroy_backlight(connector);
16022         drm_connector_unregister(connector);
16023 }
16024
16025 void intel_modeset_cleanup(struct drm_device *dev)
16026 {
16027         struct drm_i915_private *dev_priv = dev->dev_private;
16028         struct intel_connector *connector;
16029
16030         intel_disable_gt_powersave(dev);
16031
16032         intel_backlight_unregister(dev);
16033
16034         /*
16035          * Interrupts and polling as the first thing to avoid creating havoc.
16036          * Too much stuff here (turning of connectors, ...) would
16037          * experience fancy races otherwise.
16038          */
16039         intel_irq_uninstall(dev_priv);
16040
16041         /*
16042          * Due to the hpd irq storm handling the hotplug work can re-arm the
16043          * poll handlers. Hence disable polling after hpd handling is shut down.
16044          */
16045         drm_kms_helper_poll_fini(dev);
16046
16047         intel_unregister_dsm_handler();
16048
16049         intel_fbc_global_disable(dev_priv);
16050
16051         /* flush any delayed tasks or pending work */
16052         flush_scheduled_work();
16053
16054         /* destroy the backlight and sysfs files before encoders/connectors */
16055         for_each_intel_connector(dev, connector)
16056                 connector->unregister(connector);
16057
16058         drm_mode_config_cleanup(dev);
16059
16060         intel_cleanup_overlay(dev);
16061
16062         intel_cleanup_gt_powersave(dev);
16063
16064         intel_teardown_gmbus(dev);
16065 }
16066
16067 /*
16068  * Return which encoder is currently attached for connector.
16069  */
16070 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16071 {
16072         return &intel_attached_encoder(connector)->base;
16073 }
16074
16075 void intel_connector_attach_encoder(struct intel_connector *connector,
16076                                     struct intel_encoder *encoder)
16077 {
16078         connector->encoder = encoder;
16079         drm_mode_connector_attach_encoder(&connector->base,
16080                                           &encoder->base);
16081 }
16082
16083 /*
16084  * set vga decode state - true == enable VGA decode
16085  */
16086 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16087 {
16088         struct drm_i915_private *dev_priv = dev->dev_private;
16089         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16090         u16 gmch_ctrl;
16091
16092         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16093                 DRM_ERROR("failed to read control word\n");
16094                 return -EIO;
16095         }
16096
16097         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16098                 return 0;
16099
16100         if (state)
16101                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16102         else
16103                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16104
16105         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16106                 DRM_ERROR("failed to write control word\n");
16107                 return -EIO;
16108         }
16109
16110         return 0;
16111 }
16112
16113 struct intel_display_error_state {
16114
16115         u32 power_well_driver;
16116
16117         int num_transcoders;
16118
16119         struct intel_cursor_error_state {
16120                 u32 control;
16121                 u32 position;
16122                 u32 base;
16123                 u32 size;
16124         } cursor[I915_MAX_PIPES];
16125
16126         struct intel_pipe_error_state {
16127                 bool power_domain_on;
16128                 u32 source;
16129                 u32 stat;
16130         } pipe[I915_MAX_PIPES];
16131
16132         struct intel_plane_error_state {
16133                 u32 control;
16134                 u32 stride;
16135                 u32 size;
16136                 u32 pos;
16137                 u32 addr;
16138                 u32 surface;
16139                 u32 tile_offset;
16140         } plane[I915_MAX_PIPES];
16141
16142         struct intel_transcoder_error_state {
16143                 bool power_domain_on;
16144                 enum transcoder cpu_transcoder;
16145
16146                 u32 conf;
16147
16148                 u32 htotal;
16149                 u32 hblank;
16150                 u32 hsync;
16151                 u32 vtotal;
16152                 u32 vblank;
16153                 u32 vsync;
16154         } transcoder[4];
16155 };
16156
16157 struct intel_display_error_state *
16158 intel_display_capture_error_state(struct drm_device *dev)
16159 {
16160         struct drm_i915_private *dev_priv = dev->dev_private;
16161         struct intel_display_error_state *error;
16162         int transcoders[] = {
16163                 TRANSCODER_A,
16164                 TRANSCODER_B,
16165                 TRANSCODER_C,
16166                 TRANSCODER_EDP,
16167         };
16168         int i;
16169
16170         if (INTEL_INFO(dev)->num_pipes == 0)
16171                 return NULL;
16172
16173         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16174         if (error == NULL)
16175                 return NULL;
16176
16177         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16178                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16179
16180         for_each_pipe(dev_priv, i) {
16181                 error->pipe[i].power_domain_on =
16182                         __intel_display_power_is_enabled(dev_priv,
16183                                                          POWER_DOMAIN_PIPE(i));
16184                 if (!error->pipe[i].power_domain_on)
16185                         continue;
16186
16187                 error->cursor[i].control = I915_READ(CURCNTR(i));
16188                 error->cursor[i].position = I915_READ(CURPOS(i));
16189                 error->cursor[i].base = I915_READ(CURBASE(i));
16190
16191                 error->plane[i].control = I915_READ(DSPCNTR(i));
16192                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16193                 if (INTEL_INFO(dev)->gen <= 3) {
16194                         error->plane[i].size = I915_READ(DSPSIZE(i));
16195                         error->plane[i].pos = I915_READ(DSPPOS(i));
16196                 }
16197                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16198                         error->plane[i].addr = I915_READ(DSPADDR(i));
16199                 if (INTEL_INFO(dev)->gen >= 4) {
16200                         error->plane[i].surface = I915_READ(DSPSURF(i));
16201                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16202                 }
16203
16204                 error->pipe[i].source = I915_READ(PIPESRC(i));
16205
16206                 if (HAS_GMCH_DISPLAY(dev))
16207                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16208         }
16209
16210         /* Note: this does not include DSI transcoders. */
16211         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16212         if (HAS_DDI(dev_priv))
16213                 error->num_transcoders++; /* Account for eDP. */
16214
16215         for (i = 0; i < error->num_transcoders; i++) {
16216                 enum transcoder cpu_transcoder = transcoders[i];
16217
16218                 error->transcoder[i].power_domain_on =
16219                         __intel_display_power_is_enabled(dev_priv,
16220                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16221                 if (!error->transcoder[i].power_domain_on)
16222                         continue;
16223
16224                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16225
16226                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16227                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16228                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16229                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16230                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16231                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16232                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16233         }
16234
16235         return error;
16236 }
16237
16238 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16239
16240 void
16241 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16242                                 struct drm_device *dev,
16243                                 struct intel_display_error_state *error)
16244 {
16245         struct drm_i915_private *dev_priv = dev->dev_private;
16246         int i;
16247
16248         if (!error)
16249                 return;
16250
16251         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16252         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16253                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16254                            error->power_well_driver);
16255         for_each_pipe(dev_priv, i) {
16256                 err_printf(m, "Pipe [%d]:\n", i);
16257                 err_printf(m, "  Power: %s\n",
16258                            onoff(error->pipe[i].power_domain_on));
16259                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16260                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16261
16262                 err_printf(m, "Plane [%d]:\n", i);
16263                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16264                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16265                 if (INTEL_INFO(dev)->gen <= 3) {
16266                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16267                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16268                 }
16269                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16270                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16271                 if (INTEL_INFO(dev)->gen >= 4) {
16272                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16273                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16274                 }
16275
16276                 err_printf(m, "Cursor [%d]:\n", i);
16277                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16278                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16279                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16280         }
16281
16282         for (i = 0; i < error->num_transcoders; i++) {
16283                 err_printf(m, "CPU transcoder: %s\n",
16284                            transcoder_name(error->transcoder[i].cpu_transcoder));
16285                 err_printf(m, "  Power: %s\n",
16286                            onoff(error->transcoder[i].power_domain_on));
16287                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16288                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16289                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16290                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16291                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16292                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16293                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16294         }
16295 }