drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 int
 173 intel_pch_rawclk(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176
 177         WARN_ON(!HAS_PCH_SPLIT(dev));
 178
 179         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 180 }
 181
 182 /* hrawclock is 1/4 the FSB frequency */
 183 int intel_hrawclk(struct drm_device *dev)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         uint32_t clkcfg;
 187
 188         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 189         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 190                 return 200;
 191
 192         clkcfg = I915_READ(CLKCFG);
 193         switch (clkcfg & CLKCFG_FSB_MASK) {
 194         case CLKCFG_FSB_400:
 195                 return 100;
 196         case CLKCFG_FSB_533:
 197                 return 133;
 198         case CLKCFG_FSB_667:
 199                 return 166;
 200         case CLKCFG_FSB_800:
 201                 return 200;
 202         case CLKCFG_FSB_1067:
 203                 return 266;
 204         case CLKCFG_FSB_1333:
 205                 return 333;
 206         /* these two are just a guess; one of them might be right */
 207         case CLKCFG_FSB_1600:
 208         case CLKCFG_FSB_1600_ALT:
 209                 return 400;
 210         default:
 211                 return 133;
 212         }
 213 }
 214
 215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 216 {
 217         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 218                 return;
 219
 220         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 221                                                       CCK_CZ_CLOCK_CONTROL);
 222
 223         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 224 }
 225
 226 static inline u32 /* units of 100MHz */
 227 intel_fdi_link_freq(struct drm_device *dev)
 228 {
 229         if (IS_GEN5(dev)) {
 230                 struct drm_i915_private *dev_priv = dev->dev_private;
 231                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 232         } else
 233                 return 27;
 234 }
 235
 236 static const intel_limit_t intel_limits_i8xx_dac = {
 237         .dot = { .min = 25000, .max = 350000 },
 238         .vco = { .min = 908000, .max = 1512000 },
 239         .n = { .min = 2, .max = 16 },
 240         .m = { .min = 96, .max = 140 },
 241         .m1 = { .min = 18, .max = 26 },
 242         .m2 = { .min = 6, .max = 16 },
 243         .p = { .min = 4, .max = 128 },
 244         .p1 = { .min = 2, .max = 33 },
 245         .p2 = { .dot_limit = 165000,
 246                 .p2_slow = 4, .p2_fast = 2 },
 247 };
 248
 249 static const intel_limit_t intel_limits_i8xx_dvo = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 908000, .max = 1512000 },
 252         .n = { .min = 2, .max = 16 },
 253         .m = { .min = 96, .max = 140 },
 254         .m1 = { .min = 18, .max = 26 },
 255         .m2 = { .min = 6, .max = 16 },
 256         .p = { .min = 4, .max = 128 },
 257         .p1 = { .min = 2, .max = 33 },
 258         .p2 = { .dot_limit = 165000,
 259                 .p2_slow = 4, .p2_fast = 4 },
 260 };
 261
 262 static const intel_limit_t intel_limits_i8xx_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 1, .max = 6 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 14, .p2_fast = 7 },
 273 };
 274
 275 static const intel_limit_t intel_limits_i9xx_sdvo = {
 276         .dot = { .min = 20000, .max = 400000 },
 277         .vco = { .min = 1400000, .max = 2800000 },
 278         .n = { .min = 1, .max = 6 },
 279         .m = { .min = 70, .max = 120 },
 280         .m1 = { .min = 8, .max = 18 },
 281         .m2 = { .min = 3, .max = 7 },
 282         .p = { .min = 5, .max = 80 },
 283         .p1 = { .min = 1, .max = 8 },
 284         .p2 = { .dot_limit = 200000,
 285                 .p2_slow = 10, .p2_fast = 5 },
 286 };
 287
 288 static const intel_limit_t intel_limits_i9xx_lvds = {
 289         .dot = { .min = 20000, .max = 400000 },
 290         .vco = { .min = 1400000, .max = 2800000 },
 291         .n = { .min = 1, .max = 6 },
 292         .m = { .min = 70, .max = 120 },
 293         .m1 = { .min = 8, .max = 18 },
 294         .m2 = { .min = 3, .max = 7 },
 295         .p = { .min = 7, .max = 98 },
 296         .p1 = { .min = 1, .max = 8 },
 297         .p2 = { .dot_limit = 112000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301
 302 static const intel_limit_t intel_limits_g4x_sdvo = {
 303         .dot = { .min = 25000, .max = 270000 },
 304         .vco = { .min = 1750000, .max = 3500000},
 305         .n = { .min = 1, .max = 4 },
 306         .m = { .min = 104, .max = 138 },
 307         .m1 = { .min = 17, .max = 23 },
 308         .m2 = { .min = 5, .max = 11 },
 309         .p = { .min = 10, .max = 30 },
 310         .p1 = { .min = 1, .max = 3},
 311         .p2 = { .dot_limit = 270000,
 312                 .p2_slow = 10,
 313                 .p2_fast = 10
 314         },
 315 };
 316
 317 static const intel_limit_t intel_limits_g4x_hdmi = {
 318         .dot = { .min = 22000, .max = 400000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 16, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 5, .max = 80 },
 325         .p1 = { .min = 1, .max = 8},
 326         .p2 = { .dot_limit = 165000,
 327                 .p2_slow = 10, .p2_fast = 5 },
 328 };
 329
 330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 331         .dot = { .min = 20000, .max = 115000 },
 332         .vco = { .min = 1750000, .max = 3500000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 104, .max = 138 },
 335         .m1 = { .min = 17, .max = 23 },
 336         .m2 = { .min = 5, .max = 11 },
 337         .p = { .min = 28, .max = 112 },
 338         .p1 = { .min = 2, .max = 8 },
 339         .p2 = { .dot_limit = 0,
 340                 .p2_slow = 14, .p2_fast = 14
 341         },
 342 };
 343
 344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 345         .dot = { .min = 80000, .max = 224000 },
 346         .vco = { .min = 1750000, .max = 3500000 },
 347         .n = { .min = 1, .max = 3 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 17, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 14, .max = 42 },
 352         .p1 = { .min = 2, .max = 6 },
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 7, .p2_fast = 7
 355         },
 356 };
 357
 358 static const intel_limit_t intel_limits_pineview_sdvo = {
 359         .dot = { .min = 20000, .max = 400000},
 360         .vco = { .min = 1700000, .max = 3500000 },
 361         /* Pineview's Ncounter is a ring counter */
 362         .n = { .min = 3, .max = 6 },
 363         .m = { .min = 2, .max = 256 },
 364         /* Pineview only has one combined m divider, which we treat as m2. */
 365         .m1 = { .min = 0, .max = 0 },
 366         .m2 = { .min = 0, .max = 254 },
 367         .p = { .min = 5, .max = 80 },
 368         .p1 = { .min = 1, .max = 8 },
 369         .p2 = { .dot_limit = 200000,
 370                 .p2_slow = 10, .p2_fast = 5 },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_lvds = {
 374         .dot = { .min = 20000, .max = 400000 },
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         .n = { .min = 3, .max = 6 },
 377         .m = { .min = 2, .max = 256 },
 378         .m1 = { .min = 0, .max = 0 },
 379         .m2 = { .min = 0, .max = 254 },
 380         .p = { .min = 7, .max = 112 },
 381         .p1 = { .min = 1, .max = 8 },
 382         .p2 = { .dot_limit = 112000,
 383                 .p2_slow = 14, .p2_fast = 14 },
 384 };
 385
 386 /* Ironlake / Sandybridge
 387  *
 388  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 389  * the range value for them is (actual_value - 2).
 390  */
 391 static const intel_limit_t intel_limits_ironlake_dac = {
 392         .dot = { .min = 25000, .max = 350000 },
 393         .vco = { .min = 1760000, .max = 3510000 },
 394         .n = { .min = 1, .max = 5 },
 395         .m = { .min = 79, .max = 127 },
 396         .m1 = { .min = 12, .max = 22 },
 397         .m2 = { .min = 5, .max = 9 },
 398         .p = { .min = 5, .max = 80 },
 399         .p1 = { .min = 1, .max = 8 },
 400         .p2 = { .dot_limit = 225000,
 401                 .p2_slow = 10, .p2_fast = 5 },
 402 };
 403
 404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 405         .dot = { .min = 25000, .max = 350000 },
 406         .vco = { .min = 1760000, .max = 3510000 },
 407         .n = { .min = 1, .max = 3 },
 408         .m = { .min = 79, .max = 118 },
 409         .m1 = { .min = 12, .max = 22 },
 410         .m2 = { .min = 5, .max = 9 },
 411         .p = { .min = 28, .max = 112 },
 412         .p1 = { .min = 2, .max = 8 },
 413         .p2 = { .dot_limit = 225000,
 414                 .p2_slow = 14, .p2_fast = 14 },
 415 };
 416
 417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 3 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 14, .max = 56 },
 425         .p1 = { .min = 2, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 7, .p2_fast = 7 },
 428 };
 429
 430 /* LVDS 100mhz refclk limits. */
 431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 2 },
 435         .m = { .min = 79, .max = 126 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 126 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 42 },
 452         .p1 = { .min = 2, .max = 6 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 static const intel_limit_t intel_limits_vlv = {
 458          /*
 459           * These are the data rate limits (measured in fast clocks)
 460           * since those are the strictest limits we have. The fast
 461           * clock and actual rate limits are more relaxed, so checking
 462           * them would make no difference.
 463           */
 464         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 465         .vco = { .min = 4000000, .max = 6000000 },
 466         .n = { .min = 1, .max = 7 },
 467         .m1 = { .min = 2, .max = 3 },
 468         .m2 = { .min = 11, .max = 156 },
 469         .p1 = { .min = 2, .max = 3 },
 470         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 471 };
 472
 473 static const intel_limit_t intel_limits_chv = {
 474         /*
 475          * These are the data rate limits (measured in fast clocks)
 476          * since those are the strictest limits we have.  The fast
 477          * clock and actual rate limits are more relaxed, so checking
 478          * them would make no difference.
 479          */
 480         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 481         .vco = { .min = 4800000, .max = 6480000 },
 482         .n = { .min = 1, .max = 1 },
 483         .m1 = { .min = 2, .max = 2 },
 484         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 485         .p1 = { .min = 2, .max = 4 },
 486         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 487 };
 488
 489 static const intel_limit_t intel_limits_bxt = {
 490         /* FIXME: find real dot limits */
 491         .dot = { .min = 0, .max = INT_MAX },
 492         .vco = { .min = 4800000, .max = 6700000 },
 493         .n = { .min = 1, .max = 1 },
 494         .m1 = { .min = 2, .max = 2 },
 495         /* FIXME: find real m2 limits */
 496         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 497         .p1 = { .min = 2, .max = 4 },
 498         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 499 };
 500
 501 static bool
 502 needs_modeset(struct drm_crtc_state *state)
 503 {
 504         return drm_atomic_crtc_needs_modeset(state);
 505 }
 506
 507 /**
 508  * Returns whether any output on the specified pipe is of the specified type
 509  */
 510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 511 {
 512         struct drm_device *dev = crtc->base.dev;
 513         struct intel_encoder *encoder;
 514
 515         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 516                 if (encoder->type == type)
 517                         return true;
 518
 519         return false;
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe will have the specified
 524  * type after a staged modeset is complete, i.e., the same as
 525  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 526  * encoder->crtc.
 527  */
 528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 529                                       int type)
 530 {
 531         struct drm_atomic_state *state = crtc_state->base.state;
 532         struct drm_connector *connector;
 533         struct drm_connector_state *connector_state;
 534         struct intel_encoder *encoder;
 535         int i, num_connectors = 0;
 536
 537         for_each_connector_in_state(state, connector, connector_state, i) {
 538                 if (connector_state->crtc != crtc_state->base.crtc)
 539                         continue;
 540
 541                 num_connectors++;
 542
 543                 encoder = to_intel_encoder(connector_state->best_encoder);
 544                 if (encoder->type == type)
 545                         return true;
 546         }
 547
 548         WARN_ON(num_connectors == 0);
 549
 550         return false;
 551 }
 552
 553 static const intel_limit_t *
 554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 555 {
 556         struct drm_device *dev = crtc_state->base.crtc->dev;
 557         const intel_limit_t *limit;
 558
 559         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 560                 if (intel_is_dual_link_lvds(dev)) {
 561                         if (refclk == 100000)
 562                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 563                         else
 564                                 limit = &intel_limits_ironlake_dual_lvds;
 565                 } else {
 566                         if (refclk == 100000)
 567                                 limit = &intel_limits_ironlake_single_lvds_100m;
 568                         else
 569                                 limit = &intel_limits_ironlake_single_lvds;
 570                 }
 571         } else
 572                 limit = &intel_limits_ironlake_dac;
 573
 574         return limit;
 575 }
 576
 577 static const intel_limit_t *
 578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 579 {
 580         struct drm_device *dev = crtc_state->base.crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 584                 if (intel_is_dual_link_lvds(dev))
 585                         limit = &intel_limits_g4x_dual_channel_lvds;
 586                 else
 587                         limit = &intel_limits_g4x_single_channel_lvds;
 588         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 589                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 590                 limit = &intel_limits_g4x_hdmi;
 591         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 592                 limit = &intel_limits_g4x_sdvo;
 593         } else /* The option is for other outputs */
 594                 limit = &intel_limits_i9xx_sdvo;
 595
 596         return limit;
 597 }
 598
 599 static const intel_limit_t *
 600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 601 {
 602         struct drm_device *dev = crtc_state->base.crtc->dev;
 603         const intel_limit_t *limit;
 604
 605         if (IS_BROXTON(dev))
 606                 limit = &intel_limits_bxt;
 607         else if (HAS_PCH_SPLIT(dev))
 608                 limit = intel_ironlake_limit(crtc_state, refclk);
 609         else if (IS_G4X(dev)) {
 610                 limit = intel_g4x_limit(crtc_state);
 611         } else if (IS_PINEVIEW(dev)) {
 612                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 613                         limit = &intel_limits_pineview_lvds;
 614                 else
 615                         limit = &intel_limits_pineview_sdvo;
 616         } else if (IS_CHERRYVIEW(dev)) {
 617                 limit = &intel_limits_chv;
 618         } else if (IS_VALLEYVIEW(dev)) {
 619                 limit = &intel_limits_vlv;
 620         } else if (!IS_GEN2(dev)) {
 621                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 622                         limit = &intel_limits_i9xx_lvds;
 623                 else
 624                         limit = &intel_limits_i9xx_sdvo;
 625         } else {
 626                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 627                         limit = &intel_limits_i8xx_lvds;
 628                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 629                         limit = &intel_limits_i8xx_dvo;
 630                 else
 631                         limit = &intel_limits_i8xx_dac;
 632         }
 633         return limit;
 634 }
 635
 636 /*
 637  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 638  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 639  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 640  * The helpers' return value is the rate of the clock that is fed to the
 641  * display engine's pipe which can be the above fast dot clock rate or a
 642  * divided-down version of it.
 643  */
 644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 646 {
 647         clock->m = clock->m2 + 2;
 648         clock->p = clock->p1 * clock->p2;
 649         if (WARN_ON(clock->n == 0 || clock->p == 0))
 650                 return 0;
 651         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 652         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 653
 654         return clock->dot;
 655 }
 656
 657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 658 {
 659         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 660 }
 661
 662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 663 {
 664         clock->m = i9xx_dpll_compute_m(clock);
 665         clock->p = clock->p1 * clock->p2;
 666         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 667                 return 0;
 668         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 669         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 670
 671         return clock->dot;
 672 }
 673
 674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 675 {
 676         clock->m = clock->m1 * clock->m2;
 677         clock->p = clock->p1 * clock->p2;
 678         if (WARN_ON(clock->n == 0 || clock->p == 0))
 679                 return 0;
 680         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 681         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 682
 683         return clock->dot / 5;
 684 }
 685
 686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 687 {
 688         clock->m = clock->m1 * clock->m2;
 689         clock->p = clock->p1 * clock->p2;
 690         if (WARN_ON(clock->n == 0 || clock->p == 0))
 691                 return 0;
 692         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 693                         clock->n << 22);
 694         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 695
 696         return clock->dot / 5;
 697 }
 698
 699 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 700 /**
 701  * Returns whether the given set of divisors are valid for a given refclk with
 702  * the given connectors.
 703  */
 704
 705 static bool intel_PLL_is_valid(struct drm_device *dev,
 706                                const intel_limit_t *limit,
 707                                const intel_clock_t *clock)
 708 {
 709         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 710                 INTELPllInvalid("n out of range\n");
 711         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 712                 INTELPllInvalid("p1 out of range\n");
 713         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 714                 INTELPllInvalid("m2 out of range\n");
 715         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 716                 INTELPllInvalid("m1 out of range\n");
 717
 718         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 719             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 /* Only for pre-ILK configs */
1154 void assert_pll(struct drm_i915_private *dev_priv,
1155                 enum pipe pipe, bool state)
1156 {
1157         u32 val;
1158         bool cur_state;
1159
1160         val = I915_READ(DPLL(pipe));
1161         cur_state = !!(val & DPLL_VCO_ENABLE);
1162         I915_STATE_WARN(cur_state != state,
1163              "PLL state assertion failure (expected %s, current %s)\n",
1164                         onoff(state), onoff(cur_state));
1165 }
1166
1167 /* XXX: the dsi pll is shared between MIPI DSI ports */
1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1169 {
1170         u32 val;
1171         bool cur_state;
1172
1173         mutex_lock(&dev_priv->sb_lock);
1174         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1175         mutex_unlock(&dev_priv->sb_lock);
1176
1177         cur_state = val & DSI_PLL_VCO_EN;
1178         I915_STATE_WARN(cur_state != state,
1179              "DSI PLL state assertion failure (expected %s, current %s)\n",
1180                         onoff(state), onoff(cur_state));
1181 }
1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1184
1185 struct intel_shared_dpll *
1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1187 {
1188         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1189
1190         if (crtc->config->shared_dpll < 0)
1191                 return NULL;
1192
1193         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1194 }
1195
1196 /* For ILK+ */
1197 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1198                         struct intel_shared_dpll *pll,
1199                         bool state)
1200 {
1201         bool cur_state;
1202         struct intel_dpll_hw_state hw_state;
1203
1204         if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
1205                 return;
1206
1207         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1208         I915_STATE_WARN(cur_state != state,
1209              "%s assertion failure (expected %s, current %s)\n",
1210                         pll->name, onoff(state), onoff(cur_state));
1211 }
1212
1213 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1214                           enum pipe pipe, bool state)
1215 {
1216         bool cur_state;
1217         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218                                                                       pipe);
1219
1220         if (HAS_DDI(dev_priv->dev)) {
1221                 /* DDI does not have a specific FDI_TX register */
1222                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1224         } else {
1225                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1226                 cur_state = !!(val & FDI_TX_ENABLE);
1227         }
1228         I915_STATE_WARN(cur_state != state,
1229              "FDI TX state assertion failure (expected %s, current %s)\n",
1230                         onoff(state), onoff(cur_state));
1231 }
1232 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1233 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1234
1235 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1236                           enum pipe pipe, bool state)
1237 {
1238         u32 val;
1239         bool cur_state;
1240
1241         val = I915_READ(FDI_RX_CTL(pipe));
1242         cur_state = !!(val & FDI_RX_ENABLE);
1243         I915_STATE_WARN(cur_state != state,
1244              "FDI RX state assertion failure (expected %s, current %s)\n",
1245                         onoff(state), onoff(cur_state));
1246 }
1247 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1248 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1249
1250 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1251                                       enum pipe pipe)
1252 {
1253         u32 val;
1254
1255         /* ILK FDI PLL is always enabled */
1256         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1257                 return;
1258
1259         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1260         if (HAS_DDI(dev_priv->dev))
1261                 return;
1262
1263         val = I915_READ(FDI_TX_CTL(pipe));
1264         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1265 }
1266
1267 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1268                        enum pipe pipe, bool state)
1269 {
1270         u32 val;
1271         bool cur_state;
1272
1273         val = I915_READ(FDI_RX_CTL(pipe));
1274         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1275         I915_STATE_WARN(cur_state != state,
1276              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1277                         onoff(state), onoff(cur_state));
1278 }
1279
1280 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1281                            enum pipe pipe)
1282 {
1283         struct drm_device *dev = dev_priv->dev;
1284         i915_reg_t pp_reg;
1285         u32 val;
1286         enum pipe panel_pipe = PIPE_A;
1287         bool locked = true;
1288
1289         if (WARN_ON(HAS_DDI(dev)))
1290                 return;
1291
1292         if (HAS_PCH_SPLIT(dev)) {
1293                 u32 port_sel;
1294
1295                 pp_reg = PCH_PP_CONTROL;
1296                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1297
1298                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1299                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1300                         panel_pipe = PIPE_B;
1301                 /* XXX: else fix for eDP */
1302         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1303                 /* presumably write lock depends on pipe, not port select */
1304                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1305                 panel_pipe = pipe;
1306         } else {
1307                 pp_reg = PP_CONTROL;
1308                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1309                         panel_pipe = PIPE_B;
1310         }
1311
1312         val = I915_READ(pp_reg);
1313         if (!(val & PANEL_POWER_ON) ||
1314             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1315                 locked = false;
1316
1317         I915_STATE_WARN(panel_pipe == pipe && locked,
1318              "panel assertion failure, pipe %c regs locked\n",
1319              pipe_name(pipe));
1320 }
1321
1322 static void assert_cursor(struct drm_i915_private *dev_priv,
1323                           enum pipe pipe, bool state)
1324 {
1325         struct drm_device *dev = dev_priv->dev;
1326         bool cur_state;
1327
1328         if (IS_845G(dev) || IS_I865G(dev))
1329                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1330         else
1331                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1332
1333         I915_STATE_WARN(cur_state != state,
1334              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1335                         pipe_name(pipe), onoff(state), onoff(cur_state));
1336 }
1337 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1338 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1339
1340 void assert_pipe(struct drm_i915_private *dev_priv,
1341                  enum pipe pipe, bool state)
1342 {
1343         bool cur_state;
1344         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1345                                                                       pipe);
1346         enum intel_display_power_domain power_domain;
1347
1348         /* if we need the pipe quirk it must be always on */
1349         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1350             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1351                 state = true;
1352
1353         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1354         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1355                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1356                 cur_state = !!(val & PIPECONF_ENABLE);
1357
1358                 intel_display_power_put(dev_priv, power_domain);
1359         } else {
1360                 cur_state = false;
1361         }
1362
1363         I915_STATE_WARN(cur_state != state,
1364              "pipe %c assertion failure (expected %s, current %s)\n",
1365                         pipe_name(pipe), onoff(state), onoff(cur_state));
1366 }
1367
1368 static void assert_plane(struct drm_i915_private *dev_priv,
1369                          enum plane plane, bool state)
1370 {
1371         u32 val;
1372         bool cur_state;
1373
1374         val = I915_READ(DSPCNTR(plane));
1375         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1376         I915_STATE_WARN(cur_state != state,
1377              "plane %c assertion failure (expected %s, current %s)\n",
1378                         plane_name(plane), onoff(state), onoff(cur_state));
1379 }
1380
1381 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1382 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1383
1384 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1385                                    enum pipe pipe)
1386 {
1387         struct drm_device *dev = dev_priv->dev;
1388         int i;
1389
1390         /* Primary planes are fixed to pipes on gen4+ */
1391         if (INTEL_INFO(dev)->gen >= 4) {
1392                 u32 val = I915_READ(DSPCNTR(pipe));
1393                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1394                      "plane %c assertion failure, should be disabled but not\n",
1395                      plane_name(pipe));
1396                 return;
1397         }
1398
1399         /* Need to check both planes against the pipe */
1400         for_each_pipe(dev_priv, i) {
1401                 u32 val = I915_READ(DSPCNTR(i));
1402                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1403                         DISPPLANE_SEL_PIPE_SHIFT;
1404                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1405                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1406                      plane_name(i), pipe_name(pipe));
1407         }
1408 }
1409
1410 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1411                                     enum pipe pipe)
1412 {
1413         struct drm_device *dev = dev_priv->dev;
1414         int sprite;
1415
1416         if (INTEL_INFO(dev)->gen >= 9) {
1417                 for_each_sprite(dev_priv, pipe, sprite) {
1418                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1419                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1420                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1421                              sprite, pipe_name(pipe));
1422                 }
1423         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1424                 for_each_sprite(dev_priv, pipe, sprite) {
1425                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1426                         I915_STATE_WARN(val & SP_ENABLE,
1427                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1428                              sprite_name(pipe, sprite), pipe_name(pipe));
1429                 }
1430         } else if (INTEL_INFO(dev)->gen >= 7) {
1431                 u32 val = I915_READ(SPRCTL(pipe));
1432                 I915_STATE_WARN(val & SPRITE_ENABLE,
1433                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1434                      plane_name(pipe), pipe_name(pipe));
1435         } else if (INTEL_INFO(dev)->gen >= 5) {
1436                 u32 val = I915_READ(DVSCNTR(pipe));
1437                 I915_STATE_WARN(val & DVS_ENABLE,
1438                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1439                      plane_name(pipe), pipe_name(pipe));
1440         }
1441 }
1442
1443 static void assert_vblank_disabled(struct drm_crtc *crtc)
1444 {
1445         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1446                 drm_crtc_vblank_put(crtc);
1447 }
1448
1449 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1450 {
1451         u32 val;
1452         bool enabled;
1453
1454         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1455
1456         val = I915_READ(PCH_DREF_CONTROL);
1457         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1458                             DREF_SUPERSPREAD_SOURCE_MASK));
1459         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1460 }
1461
1462 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1463                                            enum pipe pipe)
1464 {
1465         u32 val;
1466         bool enabled;
1467
1468         val = I915_READ(PCH_TRANSCONF(pipe));
1469         enabled = !!(val & TRANS_ENABLE);
1470         I915_STATE_WARN(enabled,
1471              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1472              pipe_name(pipe));
1473 }
1474
1475 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1476                             enum pipe pipe, u32 port_sel, u32 val)
1477 {
1478         if ((val & DP_PORT_EN) == 0)
1479                 return false;
1480
1481         if (HAS_PCH_CPT(dev_priv->dev)) {
1482                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1483                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1484                         return false;
1485         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1486                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1487                         return false;
1488         } else {
1489                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1490                         return false;
1491         }
1492         return true;
1493 }
1494
1495 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1496                               enum pipe pipe, u32 val)
1497 {
1498         if ((val & SDVO_ENABLE) == 0)
1499                 return false;
1500
1501         if (HAS_PCH_CPT(dev_priv->dev)) {
1502                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1503                         return false;
1504         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1505                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1506                         return false;
1507         } else {
1508                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1509                         return false;
1510         }
1511         return true;
1512 }
1513
1514 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1515                               enum pipe pipe, u32 val)
1516 {
1517         if ((val & LVDS_PORT_EN) == 0)
1518                 return false;
1519
1520         if (HAS_PCH_CPT(dev_priv->dev)) {
1521                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1522                         return false;
1523         } else {
1524                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1525                         return false;
1526         }
1527         return true;
1528 }
1529
1530 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1531                               enum pipe pipe, u32 val)
1532 {
1533         if ((val & ADPA_DAC_ENABLE) == 0)
1534                 return false;
1535         if (HAS_PCH_CPT(dev_priv->dev)) {
1536                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1537                         return false;
1538         } else {
1539                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1540                         return false;
1541         }
1542         return true;
1543 }
1544
1545 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1546                                    enum pipe pipe, i915_reg_t reg,
1547                                    u32 port_sel)
1548 {
1549         u32 val = I915_READ(reg);
1550         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1551              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1552              i915_mmio_reg_offset(reg), pipe_name(pipe));
1553
1554         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1555              && (val & DP_PIPEB_SELECT),
1556              "IBX PCH dp port still using transcoder B\n");
1557 }
1558
1559 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1560                                      enum pipe pipe, i915_reg_t reg)
1561 {
1562         u32 val = I915_READ(reg);
1563         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1564              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1565              i915_mmio_reg_offset(reg), pipe_name(pipe));
1566
1567         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1568              && (val & SDVO_PIPE_B_SELECT),
1569              "IBX PCH hdmi port still using transcoder B\n");
1570 }
1571
1572 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1573                                       enum pipe pipe)
1574 {
1575         u32 val;
1576
1577         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1580
1581         val = I915_READ(PCH_ADPA);
1582         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583              "PCH VGA enabled on transcoder %c, should be disabled\n",
1584              pipe_name(pipe));
1585
1586         val = I915_READ(PCH_LVDS);
1587         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1588              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1589              pipe_name(pipe));
1590
1591         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1594 }
1595
1596 static void vlv_enable_pll(struct intel_crtc *crtc,
1597                            const struct intel_crtc_state *pipe_config)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         i915_reg_t reg = DPLL(crtc->pipe);
1602         u32 dpll = pipe_config->dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* PLL is protected by panel, make sure we can write it */
1607         if (IS_MOBILE(dev_priv->dev))
1608                 assert_panel_unlocked(dev_priv, crtc->pipe);
1609
1610         I915_WRITE(reg, dpll);
1611         POSTING_READ(reg);
1612         udelay(150);
1613
1614         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1615                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1616
1617         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1618         POSTING_READ(DPLL_MD(crtc->pipe));
1619
1620         /* We do this three times for luck */
1621         I915_WRITE(reg, dpll);
1622         POSTING_READ(reg);
1623         udelay(150); /* wait for warmup */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630 }
1631
1632 static void chv_enable_pll(struct intel_crtc *crtc,
1633                            const struct intel_crtc_state *pipe_config)
1634 {
1635         struct drm_device *dev = crtc->base.dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         int pipe = crtc->pipe;
1638         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1639         u32 tmp;
1640
1641         assert_pipe_disabled(dev_priv, crtc->pipe);
1642
1643         mutex_lock(&dev_priv->sb_lock);
1644
1645         /* Enable back the 10bit clock to display controller */
1646         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1647         tmp |= DPIO_DCLKP_EN;
1648         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1649
1650         mutex_unlock(&dev_priv->sb_lock);
1651
1652         /*
1653          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1654          */
1655         udelay(1);
1656
1657         /* Enable PLL */
1658         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1659
1660         /* Check PLL is locked */
1661         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1662                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1663
1664         /* not sure when this should be written */
1665         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1666         POSTING_READ(DPLL_MD(pipe));
1667 }
1668
1669 static int intel_num_dvo_pipes(struct drm_device *dev)
1670 {
1671         struct intel_crtc *crtc;
1672         int count = 0;
1673
1674         for_each_intel_crtc(dev, crtc)
1675                 count += crtc->base.state->active &&
1676                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1677
1678         return count;
1679 }
1680
1681 static void i9xx_enable_pll(struct intel_crtc *crtc)
1682 {
1683         struct drm_device *dev = crtc->base.dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         i915_reg_t reg = DPLL(crtc->pipe);
1686         u32 dpll = crtc->config->dpll_hw_state.dpll;
1687
1688         assert_pipe_disabled(dev_priv, crtc->pipe);
1689
1690         /* No really, not for ILK+ */
1691         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1692
1693         /* PLL is protected by panel, make sure we can write it */
1694         if (IS_MOBILE(dev) && !IS_I830(dev))
1695                 assert_panel_unlocked(dev_priv, crtc->pipe);
1696
1697         /* Enable DVO 2x clock on both PLLs if necessary */
1698         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1699                 /*
1700                  * It appears to be important that we don't enable this
1701                  * for the current pipe before otherwise configuring the
1702                  * PLL. No idea how this should be handled if multiple
1703                  * DVO outputs are enabled simultaneosly.
1704                  */
1705                 dpll |= DPLL_DVO_2X_MODE;
1706                 I915_WRITE(DPLL(!crtc->pipe),
1707                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1708         }
1709
1710         /*
1711          * Apparently we need to have VGA mode enabled prior to changing
1712          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1713          * dividers, even though the register value does change.
1714          */
1715         I915_WRITE(reg, 0);
1716
1717         I915_WRITE(reg, dpll);
1718
1719         /* Wait for the clocks to stabilize. */
1720         POSTING_READ(reg);
1721         udelay(150);
1722
1723         if (INTEL_INFO(dev)->gen >= 4) {
1724                 I915_WRITE(DPLL_MD(crtc->pipe),
1725                            crtc->config->dpll_hw_state.dpll_md);
1726         } else {
1727                 /* The pixel multiplier can only be updated once the
1728                  * DPLL is enabled and the clocks are stable.
1729                  *
1730                  * So write it again.
1731                  */
1732                 I915_WRITE(reg, dpll);
1733         }
1734
1735         /* We do this three times for luck */
1736         I915_WRITE(reg, dpll);
1737         POSTING_READ(reg);
1738         udelay(150); /* wait for warmup */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745 }
1746
1747 /**
1748  * i9xx_disable_pll - disable a PLL
1749  * @dev_priv: i915 private structure
1750  * @pipe: pipe PLL to disable
1751  *
1752  * Disable the PLL for @pipe, making sure the pipe is off first.
1753  *
1754  * Note!  This is for pre-ILK only.
1755  */
1756 static void i9xx_disable_pll(struct intel_crtc *crtc)
1757 {
1758         struct drm_device *dev = crtc->base.dev;
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         enum pipe pipe = crtc->pipe;
1761
1762         /* Disable DVO 2x clock on both PLLs if necessary */
1763         if (IS_I830(dev) &&
1764             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1765             !intel_num_dvo_pipes(dev)) {
1766                 I915_WRITE(DPLL(PIPE_B),
1767                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1768                 I915_WRITE(DPLL(PIPE_A),
1769                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1770         }
1771
1772         /* Don't disable pipe or pipe PLLs if needed */
1773         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1774             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1775                 return;
1776
1777         /* Make sure the pipe isn't still relying on us */
1778         assert_pipe_disabled(dev_priv, pipe);
1779
1780         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1781         POSTING_READ(DPLL(pipe));
1782 }
1783
1784 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1785 {
1786         u32 val;
1787
1788         /* Make sure the pipe isn't still relying on us */
1789         assert_pipe_disabled(dev_priv, pipe);
1790
1791         /*
1792          * Leave integrated clock source and reference clock enabled for pipe B.
1793          * The latter is needed for VGA hotplug / manual detection.
1794          */
1795         val = DPLL_VGA_MODE_DIS;
1796         if (pipe == PIPE_B)
1797                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1798         I915_WRITE(DPLL(pipe), val);
1799         POSTING_READ(DPLL(pipe));
1800
1801 }
1802
1803 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1804 {
1805         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1806         u32 val;
1807
1808         /* Make sure the pipe isn't still relying on us */
1809         assert_pipe_disabled(dev_priv, pipe);
1810
1811         /* Set PLL en = 0 */
1812         val = DPLL_SSC_REF_CLK_CHV |
1813                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1814         if (pipe != PIPE_A)
1815                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1816         I915_WRITE(DPLL(pipe), val);
1817         POSTING_READ(DPLL(pipe));
1818
1819         mutex_lock(&dev_priv->sb_lock);
1820
1821         /* Disable 10bit clock to display controller */
1822         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1823         val &= ~DPIO_DCLKP_EN;
1824         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1825
1826         mutex_unlock(&dev_priv->sb_lock);
1827 }
1828
1829 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1830                          struct intel_digital_port *dport,
1831                          unsigned int expected_mask)
1832 {
1833         u32 port_mask;
1834         i915_reg_t dpll_reg;
1835
1836         switch (dport->port) {
1837         case PORT_B:
1838                 port_mask = DPLL_PORTB_READY_MASK;
1839                 dpll_reg = DPLL(0);
1840                 break;
1841         case PORT_C:
1842                 port_mask = DPLL_PORTC_READY_MASK;
1843                 dpll_reg = DPLL(0);
1844                 expected_mask <<= 4;
1845                 break;
1846         case PORT_D:
1847                 port_mask = DPLL_PORTD_READY_MASK;
1848                 dpll_reg = DPIO_PHY_STATUS;
1849                 break;
1850         default:
1851                 BUG();
1852         }
1853
1854         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1855                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1856                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1857 }
1858
1859 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1860 {
1861         struct drm_device *dev = crtc->base.dev;
1862         struct drm_i915_private *dev_priv = dev->dev_private;
1863         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1864
1865         if (WARN_ON(pll == NULL))
1866                 return;
1867
1868         WARN_ON(!pll->config.crtc_mask);
1869         if (pll->active == 0) {
1870                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1871                 WARN_ON(pll->on);
1872                 assert_shared_dpll_disabled(dev_priv, pll);
1873
1874                 pll->mode_set(dev_priv, pll);
1875         }
1876 }
1877
1878 /**
1879  * intel_enable_shared_dpll - enable PCH PLL
1880  * @dev_priv: i915 private structure
1881  * @pipe: pipe PLL to enable
1882  *
1883  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1884  * drives the transcoder clock.
1885  */
1886 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1887 {
1888         struct drm_device *dev = crtc->base.dev;
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
1892         if (WARN_ON(pll == NULL))
1893                 return;
1894
1895         if (WARN_ON(pll->config.crtc_mask == 0))
1896                 return;
1897
1898         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1899                       pll->name, pll->active, pll->on,
1900                       crtc->base.base.id);
1901
1902         if (pll->active++) {
1903                 WARN_ON(!pll->on);
1904                 assert_shared_dpll_enabled(dev_priv, pll);
1905                 return;
1906         }
1907         WARN_ON(pll->on);
1908
1909         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1910
1911         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1912         pll->enable(dev_priv, pll);
1913         pll->on = true;
1914 }
1915
1916 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1917 {
1918         struct drm_device *dev = crtc->base.dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1921
1922         /* PCH only available on ILK+ */
1923         if (INTEL_INFO(dev)->gen < 5)
1924                 return;
1925
1926         if (pll == NULL)
1927                 return;
1928
1929         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1930                 return;
1931
1932         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1933                       pll->name, pll->active, pll->on,
1934                       crtc->base.base.id);
1935
1936         if (WARN_ON(pll->active == 0)) {
1937                 assert_shared_dpll_disabled(dev_priv, pll);
1938                 return;
1939         }
1940
1941         assert_shared_dpll_enabled(dev_priv, pll);
1942         WARN_ON(!pll->on);
1943         if (--pll->active)
1944                 return;
1945
1946         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1947         pll->disable(dev_priv, pll);
1948         pll->on = false;
1949
1950         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1951 }
1952
1953 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1954                                            enum pipe pipe)
1955 {
1956         struct drm_device *dev = dev_priv->dev;
1957         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1959         i915_reg_t reg;
1960         uint32_t val, pipeconf_val;
1961
1962         /* PCH only available on ILK+ */
1963         BUG_ON(!HAS_PCH_SPLIT(dev));
1964
1965         /* Make sure PCH DPLL is enabled */
1966         assert_shared_dpll_enabled(dev_priv,
1967                                    intel_crtc_to_shared_dpll(intel_crtc));
1968
1969         /* FDI must be feeding us bits for PCH ports */
1970         assert_fdi_tx_enabled(dev_priv, pipe);
1971         assert_fdi_rx_enabled(dev_priv, pipe);
1972
1973         if (HAS_PCH_CPT(dev)) {
1974                 /* Workaround: Set the timing override bit before enabling the
1975                  * pch transcoder. */
1976                 reg = TRANS_CHICKEN2(pipe);
1977                 val = I915_READ(reg);
1978                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1979                 I915_WRITE(reg, val);
1980         }
1981
1982         reg = PCH_TRANSCONF(pipe);
1983         val = I915_READ(reg);
1984         pipeconf_val = I915_READ(PIPECONF(pipe));
1985
1986         if (HAS_PCH_IBX(dev_priv->dev)) {
1987                 /*
1988                  * Make the BPC in transcoder be consistent with
1989                  * that in pipeconf reg. For HDMI we must use 8bpc
1990                  * here for both 8bpc and 12bpc.
1991                  */
1992                 val &= ~PIPECONF_BPC_MASK;
1993                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1994                         val |= PIPECONF_8BPC;
1995                 else
1996                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1997         }
1998
1999         val &= ~TRANS_INTERLACE_MASK;
2000         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2001                 if (HAS_PCH_IBX(dev_priv->dev) &&
2002                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2003                         val |= TRANS_LEGACY_INTERLACED_ILK;
2004                 else
2005                         val |= TRANS_INTERLACED;
2006         else
2007                 val |= TRANS_PROGRESSIVE;
2008
2009         I915_WRITE(reg, val | TRANS_ENABLE);
2010         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2011                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2012 }
2013
2014 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2015                                       enum transcoder cpu_transcoder)
2016 {
2017         u32 val, pipeconf_val;
2018
2019         /* PCH only available on ILK+ */
2020         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2021
2022         /* FDI must be feeding us bits for PCH ports */
2023         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2024         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2025
2026         /* Workaround: set timing override bit. */
2027         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2028         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2029         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2030
2031         val = TRANS_ENABLE;
2032         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2033
2034         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2035             PIPECONF_INTERLACED_ILK)
2036                 val |= TRANS_INTERLACED;
2037         else
2038                 val |= TRANS_PROGRESSIVE;
2039
2040         I915_WRITE(LPT_TRANSCONF, val);
2041         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2042                 DRM_ERROR("Failed to enable PCH transcoder\n");
2043 }
2044
2045 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2046                                             enum pipe pipe)
2047 {
2048         struct drm_device *dev = dev_priv->dev;
2049         i915_reg_t reg;
2050         uint32_t val;
2051
2052         /* FDI relies on the transcoder */
2053         assert_fdi_tx_disabled(dev_priv, pipe);
2054         assert_fdi_rx_disabled(dev_priv, pipe);
2055
2056         /* Ports must be off as well */
2057         assert_pch_ports_disabled(dev_priv, pipe);
2058
2059         reg = PCH_TRANSCONF(pipe);
2060         val = I915_READ(reg);
2061         val &= ~TRANS_ENABLE;
2062         I915_WRITE(reg, val);
2063         /* wait for PCH transcoder off, transcoder state */
2064         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2065                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2066
2067         if (HAS_PCH_CPT(dev)) {
2068                 /* Workaround: Clear the timing override chicken bit again. */
2069                 reg = TRANS_CHICKEN2(pipe);
2070                 val = I915_READ(reg);
2071                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2072                 I915_WRITE(reg, val);
2073         }
2074 }
2075
2076 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2077 {
2078         u32 val;
2079
2080         val = I915_READ(LPT_TRANSCONF);
2081         val &= ~TRANS_ENABLE;
2082         I915_WRITE(LPT_TRANSCONF, val);
2083         /* wait for PCH transcoder off, transcoder state */
2084         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2085                 DRM_ERROR("Failed to disable PCH transcoder\n");
2086
2087         /* Workaround: clear timing override bit. */
2088         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2089         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2091 }
2092
2093 /**
2094  * intel_enable_pipe - enable a pipe, asserting requirements
2095  * @crtc: crtc responsible for the pipe
2096  *
2097  * Enable @crtc's pipe, making sure that various hardware specific requirements
2098  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2099  */
2100 static void intel_enable_pipe(struct intel_crtc *crtc)
2101 {
2102         struct drm_device *dev = crtc->base.dev;
2103         struct drm_i915_private *dev_priv = dev->dev_private;
2104         enum pipe pipe = crtc->pipe;
2105         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2106         enum pipe pch_transcoder;
2107         i915_reg_t reg;
2108         u32 val;
2109
2110         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2111
2112         assert_planes_disabled(dev_priv, pipe);
2113         assert_cursor_disabled(dev_priv, pipe);
2114         assert_sprites_disabled(dev_priv, pipe);
2115
2116         if (HAS_PCH_LPT(dev_priv->dev))
2117                 pch_transcoder = TRANSCODER_A;
2118         else
2119                 pch_transcoder = pipe;
2120
2121         /*
2122          * A pipe without a PLL won't actually be able to drive bits from
2123          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2124          * need the check.
2125          */
2126         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2127                 if (crtc->config->has_dsi_encoder)
2128                         assert_dsi_pll_enabled(dev_priv);
2129                 else
2130                         assert_pll_enabled(dev_priv, pipe);
2131         else {
2132                 if (crtc->config->has_pch_encoder) {
2133                         /* if driving the PCH, we need FDI enabled */
2134                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2135                         assert_fdi_tx_pll_enabled(dev_priv,
2136                                                   (enum pipe) cpu_transcoder);
2137                 }
2138                 /* FIXME: assert CPU port conditions for SNB+ */
2139         }
2140
2141         reg = PIPECONF(cpu_transcoder);
2142         val = I915_READ(reg);
2143         if (val & PIPECONF_ENABLE) {
2144                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2145                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2146                 return;
2147         }
2148
2149         I915_WRITE(reg, val | PIPECONF_ENABLE);
2150         POSTING_READ(reg);
2151
2152         /*
2153          * Until the pipe starts DSL will read as 0, which would cause
2154          * an apparent vblank timestamp jump, which messes up also the
2155          * frame count when it's derived from the timestamps. So let's
2156          * wait for the pipe to start properly before we call
2157          * drm_crtc_vblank_on()
2158          */
2159         if (dev->max_vblank_count == 0 &&
2160             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2161                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2162 }
2163
2164 /**
2165  * intel_disable_pipe - disable a pipe, asserting requirements
2166  * @crtc: crtc whose pipes is to be disabled
2167  *
2168  * Disable the pipe of @crtc, making sure that various hardware
2169  * specific requirements are met, if applicable, e.g. plane
2170  * disabled, panel fitter off, etc.
2171  *
2172  * Will wait until the pipe has shut down before returning.
2173  */
2174 static void intel_disable_pipe(struct intel_crtc *crtc)
2175 {
2176         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2177         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2178         enum pipe pipe = crtc->pipe;
2179         i915_reg_t reg;
2180         u32 val;
2181
2182         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2183
2184         /*
2185          * Make sure planes won't keep trying to pump pixels to us,
2186          * or we might hang the display.
2187          */
2188         assert_planes_disabled(dev_priv, pipe);
2189         assert_cursor_disabled(dev_priv, pipe);
2190         assert_sprites_disabled(dev_priv, pipe);
2191
2192         reg = PIPECONF(cpu_transcoder);
2193         val = I915_READ(reg);
2194         if ((val & PIPECONF_ENABLE) == 0)
2195                 return;
2196
2197         /*
2198          * Double wide has implications for planes
2199          * so best keep it disabled when not needed.
2200          */
2201         if (crtc->config->double_wide)
2202                 val &= ~PIPECONF_DOUBLE_WIDE;
2203
2204         /* Don't disable pipe or pipe PLLs if needed */
2205         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2206             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2207                 val &= ~PIPECONF_ENABLE;
2208
2209         I915_WRITE(reg, val);
2210         if ((val & PIPECONF_ENABLE) == 0)
2211                 intel_wait_for_pipe_off(crtc);
2212 }
2213
2214 static bool need_vtd_wa(struct drm_device *dev)
2215 {
2216 #ifdef CONFIG_INTEL_IOMMU
2217         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2218                 return true;
2219 #endif
2220         return false;
2221 }
2222
2223 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2224 {
2225         return IS_GEN2(dev_priv) ? 2048 : 4096;
2226 }
2227
2228 static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
2229                                      uint64_t fb_modifier, unsigned int cpp)
2230 {
2231         switch (fb_modifier) {
2232         case DRM_FORMAT_MOD_NONE:
2233                 return cpp;
2234         case I915_FORMAT_MOD_X_TILED:
2235                 if (IS_GEN2(dev_priv))
2236                         return 128;
2237                 else
2238                         return 512;
2239         case I915_FORMAT_MOD_Y_TILED:
2240                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2241                         return 128;
2242                 else
2243                         return 512;
2244         case I915_FORMAT_MOD_Yf_TILED:
2245                 switch (cpp) {
2246                 case 1:
2247                         return 64;
2248                 case 2:
2249                 case 4:
2250                         return 128;
2251                 case 8:
2252                 case 16:
2253                         return 256;
2254                 default:
2255                         MISSING_CASE(cpp);
2256                         return cpp;
2257                 }
2258                 break;
2259         default:
2260                 MISSING_CASE(fb_modifier);
2261                 return cpp;
2262         }
2263 }
2264
2265 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2266                                uint64_t fb_modifier, unsigned int cpp)
2267 {
2268         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2269                 return 1;
2270         else
2271                 return intel_tile_size(dev_priv) /
2272                         intel_tile_width(dev_priv, fb_modifier, cpp);
2273 }
2274
2275 unsigned int
2276 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2277                       uint32_t pixel_format, uint64_t fb_modifier)
2278 {
2279         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2280         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2281
2282         return ALIGN(height, tile_height);
2283 }
2284
2285 static void
2286 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2287                         const struct drm_plane_state *plane_state)
2288 {
2289         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2290         struct intel_rotation_info *info = &view->params.rotated;
2291         unsigned int tile_size, tile_width, tile_height, cpp;
2292
2293         *view = i915_ggtt_view_normal;
2294
2295         if (!plane_state)
2296                 return;
2297
2298         if (!intel_rotation_90_or_270(plane_state->rotation))
2299                 return;
2300
2301         *view = i915_ggtt_view_rotated;
2302
2303         info->height = fb->height;
2304         info->pixel_format = fb->pixel_format;
2305         info->pitch = fb->pitches[0];
2306         info->uv_offset = fb->offsets[1];
2307         info->fb_modifier = fb->modifier[0];
2308
2309         tile_size = intel_tile_size(dev_priv);
2310
2311         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2312         tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
2313         tile_height = tile_size / tile_width;
2314
2315         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
2316         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2317         info->size = info->width_pages * info->height_pages * tile_size;
2318
2319         if (info->pixel_format == DRM_FORMAT_NV12) {
2320                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2321                 tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
2322                 tile_height = tile_size / tile_width;
2323
2324                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
2325                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
2326                 info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
2327         }
2328 }
2329
2330 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2331 {
2332         if (INTEL_INFO(dev_priv)->gen >= 9)
2333                 return 256 * 1024;
2334         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2335                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2336                 return 128 * 1024;
2337         else if (INTEL_INFO(dev_priv)->gen >= 4)
2338                 return 4 * 1024;
2339         else
2340                 return 0;
2341 }
2342
2343 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2344                                          uint64_t fb_modifier)
2345 {
2346         switch (fb_modifier) {
2347         case DRM_FORMAT_MOD_NONE:
2348                 return intel_linear_alignment(dev_priv);
2349         case I915_FORMAT_MOD_X_TILED:
2350                 if (INTEL_INFO(dev_priv)->gen >= 9)
2351                         return 256 * 1024;
2352                 return 0;
2353         case I915_FORMAT_MOD_Y_TILED:
2354         case I915_FORMAT_MOD_Yf_TILED:
2355                 return 1 * 1024 * 1024;
2356         default:
2357                 MISSING_CASE(fb_modifier);
2358                 return 0;
2359         }
2360 }
2361
2362 int
2363 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2364                            struct drm_framebuffer *fb,
2365                            const struct drm_plane_state *plane_state)
2366 {
2367         struct drm_device *dev = fb->dev;
2368         struct drm_i915_private *dev_priv = dev->dev_private;
2369         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2370         struct i915_ggtt_view view;
2371         u32 alignment;
2372         int ret;
2373
2374         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2375
2376         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2377
2378         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2379
2380         /* Note that the w/a also requires 64 PTE of padding following the
2381          * bo. We currently fill all unused PTE with the shadow page and so
2382          * we should always have valid PTE following the scanout preventing
2383          * the VT-d warning.
2384          */
2385         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2386                 alignment = 256 * 1024;
2387
2388         /*
2389          * Global gtt pte registers are special registers which actually forward
2390          * writes to a chunk of system memory. Which means that there is no risk
2391          * that the register values disappear as soon as we call
2392          * intel_runtime_pm_put(), so it is correct to wrap only the
2393          * pin/unpin/fence and not more.
2394          */
2395         intel_runtime_pm_get(dev_priv);
2396
2397         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2398                                                    &view);
2399         if (ret)
2400                 goto err_pm;
2401
2402         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2403          * fence, whereas 965+ only requires a fence if using
2404          * framebuffer compression.  For simplicity, we always install
2405          * a fence as the cost is not that onerous.
2406          */
2407         if (view.type == I915_GGTT_VIEW_NORMAL) {
2408                 ret = i915_gem_object_get_fence(obj);
2409                 if (ret == -EDEADLK) {
2410                         /*
2411                          * -EDEADLK means there are no free fences
2412                          * no pending flips.
2413                          *
2414                          * This is propagated to atomic, but it uses
2415                          * -EDEADLK to force a locking recovery, so
2416                          * change the returned error to -EBUSY.
2417                          */
2418                         ret = -EBUSY;
2419                         goto err_unpin;
2420                 } else if (ret)
2421                         goto err_unpin;
2422
2423                 i915_gem_object_pin_fence(obj);
2424         }
2425
2426         intel_runtime_pm_put(dev_priv);
2427         return 0;
2428
2429 err_unpin:
2430         i915_gem_object_unpin_from_display_plane(obj, &view);
2431 err_pm:
2432         intel_runtime_pm_put(dev_priv);
2433         return ret;
2434 }
2435
2436 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2437                                const struct drm_plane_state *plane_state)
2438 {
2439         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2440         struct i915_ggtt_view view;
2441
2442         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2443
2444         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2445
2446         if (view.type == I915_GGTT_VIEW_NORMAL)
2447                 i915_gem_object_unpin_fence(obj);
2448
2449         i915_gem_object_unpin_from_display_plane(obj, &view);
2450 }
2451
2452 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2453  * is assumed to be a power-of-two. */
2454 u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
2455                               int *x, int *y,
2456                               uint64_t fb_modifier,
2457                               unsigned int cpp,
2458                               unsigned int pitch)
2459 {
2460         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2461                 unsigned int tile_size, tile_width, tile_height;
2462                 unsigned int tile_rows, tiles;
2463
2464                 tile_size = intel_tile_size(dev_priv);
2465                 tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
2466                 tile_height = tile_size / tile_width;
2467
2468                 tile_rows = *y / tile_height;
2469                 *y %= tile_height;
2470
2471                 tiles = *x / (tile_width/cpp);
2472                 *x %= tile_width/cpp;
2473
2474                 return tile_rows * pitch * tile_height + tiles * tile_size;
2475         } else {
2476                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2477                 unsigned int offset;
2478
2479                 offset = *y * pitch + *x * cpp;
2480                 *y = (offset & alignment) / pitch;
2481                 *x = ((offset & alignment) - *y * pitch) / cpp;
2482                 return offset & ~alignment;
2483         }
2484 }
2485
2486 static int i9xx_format_to_fourcc(int format)
2487 {
2488         switch (format) {
2489         case DISPPLANE_8BPP:
2490                 return DRM_FORMAT_C8;
2491         case DISPPLANE_BGRX555:
2492                 return DRM_FORMAT_XRGB1555;
2493         case DISPPLANE_BGRX565:
2494                 return DRM_FORMAT_RGB565;
2495         default:
2496         case DISPPLANE_BGRX888:
2497                 return DRM_FORMAT_XRGB8888;
2498         case DISPPLANE_RGBX888:
2499                 return DRM_FORMAT_XBGR8888;
2500         case DISPPLANE_BGRX101010:
2501                 return DRM_FORMAT_XRGB2101010;
2502         case DISPPLANE_RGBX101010:
2503                 return DRM_FORMAT_XBGR2101010;
2504         }
2505 }
2506
2507 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2508 {
2509         switch (format) {
2510         case PLANE_CTL_FORMAT_RGB_565:
2511                 return DRM_FORMAT_RGB565;
2512         default:
2513         case PLANE_CTL_FORMAT_XRGB_8888:
2514                 if (rgb_order) {
2515                         if (alpha)
2516                                 return DRM_FORMAT_ABGR8888;
2517                         else
2518                                 return DRM_FORMAT_XBGR8888;
2519                 } else {
2520                         if (alpha)
2521                                 return DRM_FORMAT_ARGB8888;
2522                         else
2523                                 return DRM_FORMAT_XRGB8888;
2524                 }
2525         case PLANE_CTL_FORMAT_XRGB_2101010:
2526                 if (rgb_order)
2527                         return DRM_FORMAT_XBGR2101010;
2528                 else
2529                         return DRM_FORMAT_XRGB2101010;
2530         }
2531 }
2532
2533 static bool
2534 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2535                               struct intel_initial_plane_config *plane_config)
2536 {
2537         struct drm_device *dev = crtc->base.dev;
2538         struct drm_i915_private *dev_priv = to_i915(dev);
2539         struct drm_i915_gem_object *obj = NULL;
2540         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2541         struct drm_framebuffer *fb = &plane_config->fb->base;
2542         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2543         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2544                                     PAGE_SIZE);
2545
2546         size_aligned -= base_aligned;
2547
2548         if (plane_config->size == 0)
2549                 return false;
2550
2551         /* If the FB is too big, just don't use it since fbdev is not very
2552          * important and we should probably use that space with FBC or other
2553          * features. */
2554         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2555                 return false;
2556
2557         mutex_lock(&dev->struct_mutex);
2558
2559         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2560                                                              base_aligned,
2561                                                              base_aligned,
2562                                                              size_aligned);
2563         if (!obj) {
2564                 mutex_unlock(&dev->struct_mutex);
2565                 return false;
2566         }
2567
2568         obj->tiling_mode = plane_config->tiling;
2569         if (obj->tiling_mode == I915_TILING_X)
2570                 obj->stride = fb->pitches[0];
2571
2572         mode_cmd.pixel_format = fb->pixel_format;
2573         mode_cmd.width = fb->width;
2574         mode_cmd.height = fb->height;
2575         mode_cmd.pitches[0] = fb->pitches[0];
2576         mode_cmd.modifier[0] = fb->modifier[0];
2577         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2578
2579         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2580                                    &mode_cmd, obj)) {
2581                 DRM_DEBUG_KMS("intel fb init failed\n");
2582                 goto out_unref_obj;
2583         }
2584
2585         mutex_unlock(&dev->struct_mutex);
2586
2587         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2588         return true;
2589
2590 out_unref_obj:
2591         drm_gem_object_unreference(&obj->base);
2592         mutex_unlock(&dev->struct_mutex);
2593         return false;
2594 }
2595
2596 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2597 static void
2598 update_state_fb(struct drm_plane *plane)
2599 {
2600         if (plane->fb == plane->state->fb)
2601                 return;
2602
2603         if (plane->state->fb)
2604                 drm_framebuffer_unreference(plane->state->fb);
2605         plane->state->fb = plane->fb;
2606         if (plane->state->fb)
2607                 drm_framebuffer_reference(plane->state->fb);
2608 }
2609
2610 static void
2611 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2612                              struct intel_initial_plane_config *plane_config)
2613 {
2614         struct drm_device *dev = intel_crtc->base.dev;
2615         struct drm_i915_private *dev_priv = dev->dev_private;
2616         struct drm_crtc *c;
2617         struct intel_crtc *i;
2618         struct drm_i915_gem_object *obj;
2619         struct drm_plane *primary = intel_crtc->base.primary;
2620         struct drm_plane_state *plane_state = primary->state;
2621         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2622         struct intel_plane *intel_plane = to_intel_plane(primary);
2623         struct intel_plane_state *intel_state =
2624                 to_intel_plane_state(plane_state);
2625         struct drm_framebuffer *fb;
2626
2627         if (!plane_config->fb)
2628                 return;
2629
2630         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2631                 fb = &plane_config->fb->base;
2632                 goto valid_fb;
2633         }
2634
2635         kfree(plane_config->fb);
2636
2637         /*
2638          * Failed to alloc the obj, check to see if we should share
2639          * an fb with another CRTC instead
2640          */
2641         for_each_crtc(dev, c) {
2642                 i = to_intel_crtc(c);
2643
2644                 if (c == &intel_crtc->base)
2645                         continue;
2646
2647                 if (!i->active)
2648                         continue;
2649
2650                 fb = c->primary->fb;
2651                 if (!fb)
2652                         continue;
2653
2654                 obj = intel_fb_obj(fb);
2655                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2656                         drm_framebuffer_reference(fb);
2657                         goto valid_fb;
2658                 }
2659         }
2660
2661         /*
2662          * We've failed to reconstruct the BIOS FB.  Current display state
2663          * indicates that the primary plane is visible, but has a NULL FB,
2664          * which will lead to problems later if we don't fix it up.  The
2665          * simplest solution is to just disable the primary plane now and
2666          * pretend the BIOS never had it enabled.
2667          */
2668         to_intel_plane_state(plane_state)->visible = false;
2669         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2670         intel_pre_disable_primary(&intel_crtc->base);
2671         intel_plane->disable_plane(primary, &intel_crtc->base);
2672
2673         return;
2674
2675 valid_fb:
2676         plane_state->src_x = 0;
2677         plane_state->src_y = 0;
2678         plane_state->src_w = fb->width << 16;
2679         plane_state->src_h = fb->height << 16;
2680
2681         plane_state->crtc_x = 0;
2682         plane_state->crtc_y = 0;
2683         plane_state->crtc_w = fb->width;
2684         plane_state->crtc_h = fb->height;
2685
2686         intel_state->src.x1 = plane_state->src_x;
2687         intel_state->src.y1 = plane_state->src_y;
2688         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2689         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2690         intel_state->dst.x1 = plane_state->crtc_x;
2691         intel_state->dst.y1 = plane_state->crtc_y;
2692         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2693         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2694
2695         obj = intel_fb_obj(fb);
2696         if (obj->tiling_mode != I915_TILING_NONE)
2697                 dev_priv->preserve_bios_swizzle = true;
2698
2699         drm_framebuffer_reference(fb);
2700         primary->fb = primary->state->fb = fb;
2701         primary->crtc = primary->state->crtc = &intel_crtc->base;
2702         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2703         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2704 }
2705
2706 static void i9xx_update_primary_plane(struct drm_plane *primary,
2707                                       const struct intel_crtc_state *crtc_state,
2708                                       const struct intel_plane_state *plane_state)
2709 {
2710         struct drm_device *dev = primary->dev;
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2713         struct drm_framebuffer *fb = plane_state->base.fb;
2714         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2715         int plane = intel_crtc->plane;
2716         u32 linear_offset;
2717         u32 dspcntr;
2718         i915_reg_t reg = DSPCNTR(plane);
2719         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2720         int x = plane_state->src.x1 >> 16;
2721         int y = plane_state->src.y1 >> 16;
2722
2723         dspcntr = DISPPLANE_GAMMA_ENABLE;
2724
2725         dspcntr |= DISPLAY_PLANE_ENABLE;
2726
2727         if (INTEL_INFO(dev)->gen < 4) {
2728                 if (intel_crtc->pipe == PIPE_B)
2729                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2730
2731                 /* pipesrc and dspsize control the size that is scaled from,
2732                  * which should always be the user's requested size.
2733                  */
2734                 I915_WRITE(DSPSIZE(plane),
2735                            ((crtc_state->pipe_src_h - 1) << 16) |
2736                            (crtc_state->pipe_src_w - 1));
2737                 I915_WRITE(DSPPOS(plane), 0);
2738         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2739                 I915_WRITE(PRIMSIZE(plane),
2740                            ((crtc_state->pipe_src_h - 1) << 16) |
2741                            (crtc_state->pipe_src_w - 1));
2742                 I915_WRITE(PRIMPOS(plane), 0);
2743                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2744         }
2745
2746         switch (fb->pixel_format) {
2747         case DRM_FORMAT_C8:
2748                 dspcntr |= DISPPLANE_8BPP;
2749                 break;
2750         case DRM_FORMAT_XRGB1555:
2751                 dspcntr |= DISPPLANE_BGRX555;
2752                 break;
2753         case DRM_FORMAT_RGB565:
2754                 dspcntr |= DISPPLANE_BGRX565;
2755                 break;
2756         case DRM_FORMAT_XRGB8888:
2757                 dspcntr |= DISPPLANE_BGRX888;
2758                 break;
2759         case DRM_FORMAT_XBGR8888:
2760                 dspcntr |= DISPPLANE_RGBX888;
2761                 break;
2762         case DRM_FORMAT_XRGB2101010:
2763                 dspcntr |= DISPPLANE_BGRX101010;
2764                 break;
2765         case DRM_FORMAT_XBGR2101010:
2766                 dspcntr |= DISPPLANE_RGBX101010;
2767                 break;
2768         default:
2769                 BUG();
2770         }
2771
2772         if (INTEL_INFO(dev)->gen >= 4 &&
2773             obj->tiling_mode != I915_TILING_NONE)
2774                 dspcntr |= DISPPLANE_TILED;
2775
2776         if (IS_G4X(dev))
2777                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2778
2779         linear_offset = y * fb->pitches[0] + x * cpp;
2780
2781         if (INTEL_INFO(dev)->gen >= 4) {
2782                 intel_crtc->dspaddr_offset =
2783                         intel_compute_tile_offset(dev_priv, &x, &y,
2784                                                   fb->modifier[0], cpp,
2785                                                   fb->pitches[0]);
2786                 linear_offset -= intel_crtc->dspaddr_offset;
2787         } else {
2788                 intel_crtc->dspaddr_offset = linear_offset;
2789         }
2790
2791         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2792                 dspcntr |= DISPPLANE_ROTATE_180;
2793
2794                 x += (crtc_state->pipe_src_w - 1);
2795                 y += (crtc_state->pipe_src_h - 1);
2796
2797                 /* Finding the last pixel of the last line of the display
2798                 data and adding to linear_offset*/
2799                 linear_offset +=
2800                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2801                         (crtc_state->pipe_src_w - 1) * cpp;
2802         }
2803
2804         intel_crtc->adjusted_x = x;
2805         intel_crtc->adjusted_y = y;
2806
2807         I915_WRITE(reg, dspcntr);
2808
2809         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2810         if (INTEL_INFO(dev)->gen >= 4) {
2811                 I915_WRITE(DSPSURF(plane),
2812                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2813                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2814                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2815         } else
2816                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2817         POSTING_READ(reg);
2818 }
2819
2820 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2821                                        struct drm_crtc *crtc)
2822 {
2823         struct drm_device *dev = crtc->dev;
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2826         int plane = intel_crtc->plane;
2827
2828         I915_WRITE(DSPCNTR(plane), 0);
2829         if (INTEL_INFO(dev_priv)->gen >= 4)
2830                 I915_WRITE(DSPSURF(plane), 0);
2831         else
2832                 I915_WRITE(DSPADDR(plane), 0);
2833         POSTING_READ(DSPCNTR(plane));
2834 }
2835
2836 static void ironlake_update_primary_plane(struct drm_plane *primary,
2837                                           const struct intel_crtc_state *crtc_state,
2838                                           const struct intel_plane_state *plane_state)
2839 {
2840         struct drm_device *dev = primary->dev;
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2843         struct drm_framebuffer *fb = plane_state->base.fb;
2844         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2845         int plane = intel_crtc->plane;
2846         u32 linear_offset;
2847         u32 dspcntr;
2848         i915_reg_t reg = DSPCNTR(plane);
2849         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2850         int x = plane_state->src.x1 >> 16;
2851         int y = plane_state->src.y1 >> 16;
2852
2853         dspcntr = DISPPLANE_GAMMA_ENABLE;
2854         dspcntr |= DISPLAY_PLANE_ENABLE;
2855
2856         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2857                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2858
2859         switch (fb->pixel_format) {
2860         case DRM_FORMAT_C8:
2861                 dspcntr |= DISPPLANE_8BPP;
2862                 break;
2863         case DRM_FORMAT_RGB565:
2864                 dspcntr |= DISPPLANE_BGRX565;
2865                 break;
2866         case DRM_FORMAT_XRGB8888:
2867                 dspcntr |= DISPPLANE_BGRX888;
2868                 break;
2869         case DRM_FORMAT_XBGR8888:
2870                 dspcntr |= DISPPLANE_RGBX888;
2871                 break;
2872         case DRM_FORMAT_XRGB2101010:
2873                 dspcntr |= DISPPLANE_BGRX101010;
2874                 break;
2875         case DRM_FORMAT_XBGR2101010:
2876                 dspcntr |= DISPPLANE_RGBX101010;
2877                 break;
2878         default:
2879                 BUG();
2880         }
2881
2882         if (obj->tiling_mode != I915_TILING_NONE)
2883                 dspcntr |= DISPPLANE_TILED;
2884
2885         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2886                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2887
2888         linear_offset = y * fb->pitches[0] + x * cpp;
2889         intel_crtc->dspaddr_offset =
2890                 intel_compute_tile_offset(dev_priv, &x, &y,
2891                                           fb->modifier[0], cpp,
2892                                           fb->pitches[0]);
2893         linear_offset -= intel_crtc->dspaddr_offset;
2894         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2895                 dspcntr |= DISPPLANE_ROTATE_180;
2896
2897                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2898                         x += (crtc_state->pipe_src_w - 1);
2899                         y += (crtc_state->pipe_src_h - 1);
2900
2901                         /* Finding the last pixel of the last line of the display
2902                         data and adding to linear_offset*/
2903                         linear_offset +=
2904                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2905                                 (crtc_state->pipe_src_w - 1) * cpp;
2906                 }
2907         }
2908
2909         intel_crtc->adjusted_x = x;
2910         intel_crtc->adjusted_y = y;
2911
2912         I915_WRITE(reg, dspcntr);
2913
2914         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2915         I915_WRITE(DSPSURF(plane),
2916                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2917         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2918                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2919         } else {
2920                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2921                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2922         }
2923         POSTING_READ(reg);
2924 }
2925
2926 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2927                               uint64_t fb_modifier, uint32_t pixel_format)
2928 {
2929         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2930                 return 64;
2931         } else {
2932                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2933
2934                 return intel_tile_width(dev_priv, fb_modifier, cpp);
2935         }
2936 }
2937
2938 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2939                            struct drm_i915_gem_object *obj,
2940                            unsigned int plane)
2941 {
2942         struct i915_ggtt_view view;
2943         struct i915_vma *vma;
2944         u64 offset;
2945
2946         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2947                                 intel_plane->base.state);
2948
2949         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2950         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2951                 view.type))
2952                 return -1;
2953
2954         offset = vma->node.start;
2955
2956         if (plane == 1) {
2957                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2958                           PAGE_SIZE;
2959         }
2960
2961         WARN_ON(upper_32_bits(offset));
2962
2963         return lower_32_bits(offset);
2964 }
2965
2966 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2967 {
2968         struct drm_device *dev = intel_crtc->base.dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970
2971         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2972         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2973         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2974 }
2975
2976 /*
2977  * This function detaches (aka. unbinds) unused scalers in hardware
2978  */
2979 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2980 {
2981         struct intel_crtc_scaler_state *scaler_state;
2982         int i;
2983
2984         scaler_state = &intel_crtc->config->scaler_state;
2985
2986         /* loop through and disable scalers that aren't in use */
2987         for (i = 0; i < intel_crtc->num_scalers; i++) {
2988                 if (!scaler_state->scalers[i].in_use)
2989                         skl_detach_scaler(intel_crtc, i);
2990         }
2991 }
2992
2993 u32 skl_plane_ctl_format(uint32_t pixel_format)
2994 {
2995         switch (pixel_format) {
2996         case DRM_FORMAT_C8:
2997                 return PLANE_CTL_FORMAT_INDEXED;
2998         case DRM_FORMAT_RGB565:
2999                 return PLANE_CTL_FORMAT_RGB_565;
3000         case DRM_FORMAT_XBGR8888:
3001                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3002         case DRM_FORMAT_XRGB8888:
3003                 return PLANE_CTL_FORMAT_XRGB_8888;
3004         /*
3005          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3006          * to be already pre-multiplied. We need to add a knob (or a different
3007          * DRM_FORMAT) for user-space to configure that.
3008          */
3009         case DRM_FORMAT_ABGR8888:
3010                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3011                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3012         case DRM_FORMAT_ARGB8888:
3013                 return PLANE_CTL_FORMAT_XRGB_8888 |
3014                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3015         case DRM_FORMAT_XRGB2101010:
3016                 return PLANE_CTL_FORMAT_XRGB_2101010;
3017         case DRM_FORMAT_XBGR2101010:
3018                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3019         case DRM_FORMAT_YUYV:
3020                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3021         case DRM_FORMAT_YVYU:
3022                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3023         case DRM_FORMAT_UYVY:
3024                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3025         case DRM_FORMAT_VYUY:
3026                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3027         default:
3028                 MISSING_CASE(pixel_format);
3029         }
3030
3031         return 0;
3032 }
3033
3034 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3035 {
3036         switch (fb_modifier) {
3037         case DRM_FORMAT_MOD_NONE:
3038                 break;
3039         case I915_FORMAT_MOD_X_TILED:
3040                 return PLANE_CTL_TILED_X;
3041         case I915_FORMAT_MOD_Y_TILED:
3042                 return PLANE_CTL_TILED_Y;
3043         case I915_FORMAT_MOD_Yf_TILED:
3044                 return PLANE_CTL_TILED_YF;
3045         default:
3046                 MISSING_CASE(fb_modifier);
3047         }
3048
3049         return 0;
3050 }
3051
3052 u32 skl_plane_ctl_rotation(unsigned int rotation)
3053 {
3054         switch (rotation) {
3055         case BIT(DRM_ROTATE_0):
3056                 break;
3057         /*
3058          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3059          * while i915 HW rotation is clockwise, thats why this swapping.
3060          */
3061         case BIT(DRM_ROTATE_90):
3062                 return PLANE_CTL_ROTATE_270;
3063         case BIT(DRM_ROTATE_180):
3064                 return PLANE_CTL_ROTATE_180;
3065         case BIT(DRM_ROTATE_270):
3066                 return PLANE_CTL_ROTATE_90;
3067         default:
3068                 MISSING_CASE(rotation);
3069         }
3070
3071         return 0;
3072 }
3073
3074 static void skylake_update_primary_plane(struct drm_plane *plane,
3075                                          const struct intel_crtc_state *crtc_state,
3076                                          const struct intel_plane_state *plane_state)
3077 {
3078         struct drm_device *dev = plane->dev;
3079         struct drm_i915_private *dev_priv = dev->dev_private;
3080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3081         struct drm_framebuffer *fb = plane_state->base.fb;
3082         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3083         int pipe = intel_crtc->pipe;
3084         u32 plane_ctl, stride_div, stride;
3085         u32 tile_height, plane_offset, plane_size;
3086         unsigned int rotation = plane_state->base.rotation;
3087         int x_offset, y_offset;
3088         u32 surf_addr;
3089         int scaler_id = plane_state->scaler_id;
3090         int src_x = plane_state->src.x1 >> 16;
3091         int src_y = plane_state->src.y1 >> 16;
3092         int src_w = drm_rect_width(&plane_state->src) >> 16;
3093         int src_h = drm_rect_height(&plane_state->src) >> 16;
3094         int dst_x = plane_state->dst.x1;
3095         int dst_y = plane_state->dst.y1;
3096         int dst_w = drm_rect_width(&plane_state->dst);
3097         int dst_h = drm_rect_height(&plane_state->dst);
3098
3099         plane_ctl = PLANE_CTL_ENABLE |
3100                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3101                     PLANE_CTL_PIPE_CSC_ENABLE;
3102
3103         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3104         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3105         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3106         plane_ctl |= skl_plane_ctl_rotation(rotation);
3107
3108         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3109                                                fb->pixel_format);
3110         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3111
3112         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3113
3114         if (intel_rotation_90_or_270(rotation)) {
3115                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3116
3117                 /* stride = Surface height in tiles */
3118                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3119                 stride = DIV_ROUND_UP(fb->height, tile_height);
3120                 x_offset = stride * tile_height - src_y - src_h;
3121                 y_offset = src_x;
3122                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3123         } else {
3124                 stride = fb->pitches[0] / stride_div;
3125                 x_offset = src_x;
3126                 y_offset = src_y;
3127                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3128         }
3129         plane_offset = y_offset << 16 | x_offset;
3130
3131         intel_crtc->adjusted_x = x_offset;
3132         intel_crtc->adjusted_y = y_offset;
3133
3134         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3135         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3136         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3137         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3138
3139         if (scaler_id >= 0) {
3140                 uint32_t ps_ctrl = 0;
3141
3142                 WARN_ON(!dst_w || !dst_h);
3143                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3144                         crtc_state->scaler_state.scalers[scaler_id].mode;
3145                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3146                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3147                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3148                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3149                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3150         } else {
3151                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3152         }
3153
3154         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3155
3156         POSTING_READ(PLANE_SURF(pipe, 0));
3157 }
3158
3159 static void skylake_disable_primary_plane(struct drm_plane *primary,
3160                                           struct drm_crtc *crtc)
3161 {
3162         struct drm_device *dev = crtc->dev;
3163         struct drm_i915_private *dev_priv = dev->dev_private;
3164         int pipe = to_intel_crtc(crtc)->pipe;
3165
3166         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3167         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         /* Support for kgdboc is disabled, this needs a major rework. */
3177         DRM_ERROR("legacy panic handler not supported any more.\n");
3178
3179         return -ENODEV;
3180 }
3181
3182 static void intel_complete_page_flips(struct drm_device *dev)
3183 {
3184         struct drm_crtc *crtc;
3185
3186         for_each_crtc(dev, crtc) {
3187                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188                 enum plane plane = intel_crtc->plane;
3189
3190                 intel_prepare_page_flip(dev, plane);
3191                 intel_finish_page_flip_plane(dev, plane);
3192         }
3193 }
3194
3195 static void intel_update_primary_planes(struct drm_device *dev)
3196 {
3197         struct drm_crtc *crtc;
3198
3199         for_each_crtc(dev, crtc) {
3200                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3201                 struct intel_plane_state *plane_state;
3202
3203                 drm_modeset_lock_crtc(crtc, &plane->base);
3204                 plane_state = to_intel_plane_state(plane->base.state);
3205
3206                 if (plane_state->visible)
3207                         plane->update_plane(&plane->base,
3208                                             to_intel_crtc_state(crtc->state),
3209                                             plane_state);
3210
3211                 drm_modeset_unlock_crtc(crtc);
3212         }
3213 }
3214
3215 void intel_prepare_reset(struct drm_device *dev)
3216 {
3217         /* no reset support for gen2 */
3218         if (IS_GEN2(dev))
3219                 return;
3220
3221         /* reset doesn't touch the display */
3222         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3223                 return;
3224
3225         drm_modeset_lock_all(dev);
3226         /*
3227          * Disabling the crtcs gracefully seems nicer. Also the
3228          * g33 docs say we should at least disable all the planes.
3229          */
3230         intel_display_suspend(dev);
3231 }
3232
3233 void intel_finish_reset(struct drm_device *dev)
3234 {
3235         struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237         /*
3238          * Flips in the rings will be nuked by the reset,
3239          * so complete all pending flips so that user space
3240          * will get its events and not get stuck.
3241          */
3242         intel_complete_page_flips(dev);
3243
3244         /* no reset support for gen2 */
3245         if (IS_GEN2(dev))
3246                 return;
3247
3248         /* reset doesn't touch the display */
3249         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250                 /*
3251                  * Flips in the rings have been nuked by the reset,
3252                  * so update the base address of all primary
3253                  * planes to the the last fb to make sure we're
3254                  * showing the correct fb after a reset.
3255                  *
3256                  * FIXME: Atomic will make this obsolete since we won't schedule
3257                  * CS-based flips (which might get lost in gpu resets) any more.
3258                  */
3259                 intel_update_primary_planes(dev);
3260                 return;
3261         }
3262
3263         /*
3264          * The display has been reset as well,
3265          * so need a full re-initialization.
3266          */
3267         intel_runtime_pm_disable_interrupts(dev_priv);
3268         intel_runtime_pm_enable_interrupts(dev_priv);
3269
3270         intel_modeset_init_hw(dev);
3271
3272         spin_lock_irq(&dev_priv->irq_lock);
3273         if (dev_priv->display.hpd_irq_setup)
3274                 dev_priv->display.hpd_irq_setup(dev);
3275         spin_unlock_irq(&dev_priv->irq_lock);
3276
3277         intel_display_resume(dev);
3278
3279         intel_hpd_init(dev_priv);
3280
3281         drm_modeset_unlock_all(dev);
3282 }
3283
3284 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3285 {
3286         struct drm_device *dev = crtc->dev;
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289         bool pending;
3290
3291         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3292             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3293                 return false;
3294
3295         spin_lock_irq(&dev->event_lock);
3296         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3297         spin_unlock_irq(&dev->event_lock);
3298
3299         return pending;
3300 }
3301
3302 static void intel_update_pipe_config(struct intel_crtc *crtc,
3303                                      struct intel_crtc_state *old_crtc_state)
3304 {
3305         struct drm_device *dev = crtc->base.dev;
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         struct intel_crtc_state *pipe_config =
3308                 to_intel_crtc_state(crtc->base.state);
3309
3310         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3311         crtc->base.mode = crtc->base.state->mode;
3312
3313         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3314                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3315                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3316
3317         if (HAS_DDI(dev))
3318                 intel_set_pipe_csc(&crtc->base);
3319
3320         /*
3321          * Update pipe size and adjust fitter if needed: the reason for this is
3322          * that in compute_mode_changes we check the native mode (not the pfit
3323          * mode) to see if we can flip rather than do a full mode set. In the
3324          * fastboot case, we'll flip, but if we don't update the pipesrc and
3325          * pfit state, we'll end up with a big fb scanned out into the wrong
3326          * sized surface.
3327          */
3328
3329         I915_WRITE(PIPESRC(crtc->pipe),
3330                    ((pipe_config->pipe_src_w - 1) << 16) |
3331                    (pipe_config->pipe_src_h - 1));
3332
3333         /* on skylake this is done by detaching scalers */
3334         if (INTEL_INFO(dev)->gen >= 9) {
3335                 skl_detach_scalers(crtc);
3336
3337                 if (pipe_config->pch_pfit.enabled)
3338                         skylake_pfit_enable(crtc);
3339         } else if (HAS_PCH_SPLIT(dev)) {
3340                 if (pipe_config->pch_pfit.enabled)
3341                         ironlake_pfit_enable(crtc);
3342                 else if (old_crtc_state->pch_pfit.enabled)
3343                         ironlake_pfit_disable(crtc, true);
3344         }
3345 }
3346
3347 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3348 {
3349         struct drm_device *dev = crtc->dev;
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352         int pipe = intel_crtc->pipe;
3353         i915_reg_t reg;
3354         u32 temp;
3355
3356         /* enable normal train */
3357         reg = FDI_TX_CTL(pipe);
3358         temp = I915_READ(reg);
3359         if (IS_IVYBRIDGE(dev)) {
3360                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3361                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3362         } else {
3363                 temp &= ~FDI_LINK_TRAIN_NONE;
3364                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3365         }
3366         I915_WRITE(reg, temp);
3367
3368         reg = FDI_RX_CTL(pipe);
3369         temp = I915_READ(reg);
3370         if (HAS_PCH_CPT(dev)) {
3371                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3372                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3373         } else {
3374                 temp &= ~FDI_LINK_TRAIN_NONE;
3375                 temp |= FDI_LINK_TRAIN_NONE;
3376         }
3377         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3378
3379         /* wait one idle pattern time */
3380         POSTING_READ(reg);
3381         udelay(1000);
3382
3383         /* IVB wants error correction enabled */
3384         if (IS_IVYBRIDGE(dev))
3385                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3386                            FDI_FE_ERRC_ENABLE);
3387 }
3388
3389 /* The FDI link training functions for ILK/Ibexpeak. */
3390 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3391 {
3392         struct drm_device *dev = crtc->dev;
3393         struct drm_i915_private *dev_priv = dev->dev_private;
3394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395         int pipe = intel_crtc->pipe;
3396         i915_reg_t reg;
3397         u32 temp, tries;
3398
3399         /* FDI needs bits from pipe first */
3400         assert_pipe_enabled(dev_priv, pipe);
3401
3402         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3403            for train result */
3404         reg = FDI_RX_IMR(pipe);
3405         temp = I915_READ(reg);
3406         temp &= ~FDI_RX_SYMBOL_LOCK;
3407         temp &= ~FDI_RX_BIT_LOCK;
3408         I915_WRITE(reg, temp);
3409         I915_READ(reg);
3410         udelay(150);
3411
3412         /* enable CPU FDI TX and PCH FDI RX */
3413         reg = FDI_TX_CTL(pipe);
3414         temp = I915_READ(reg);
3415         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3416         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3417         temp &= ~FDI_LINK_TRAIN_NONE;
3418         temp |= FDI_LINK_TRAIN_PATTERN_1;
3419         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3420
3421         reg = FDI_RX_CTL(pipe);
3422         temp = I915_READ(reg);
3423         temp &= ~FDI_LINK_TRAIN_NONE;
3424         temp |= FDI_LINK_TRAIN_PATTERN_1;
3425         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427         POSTING_READ(reg);
3428         udelay(150);
3429
3430         /* Ironlake workaround, enable clock pointer after FDI enable*/
3431         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3432         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3433                    FDI_RX_PHASE_SYNC_POINTER_EN);
3434
3435         reg = FDI_RX_IIR(pipe);
3436         for (tries = 0; tries < 5; tries++) {
3437                 temp = I915_READ(reg);
3438                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440                 if ((temp & FDI_RX_BIT_LOCK)) {
3441                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3442                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443                         break;
3444                 }
3445         }
3446         if (tries == 5)
3447                 DRM_ERROR("FDI train 1 fail!\n");
3448
3449         /* Train 2 */
3450         reg = FDI_TX_CTL(pipe);
3451         temp = I915_READ(reg);
3452         temp &= ~FDI_LINK_TRAIN_NONE;
3453         temp |= FDI_LINK_TRAIN_PATTERN_2;
3454         I915_WRITE(reg, temp);
3455
3456         reg = FDI_RX_CTL(pipe);
3457         temp = I915_READ(reg);
3458         temp &= ~FDI_LINK_TRAIN_NONE;
3459         temp |= FDI_LINK_TRAIN_PATTERN_2;
3460         I915_WRITE(reg, temp);
3461
3462         POSTING_READ(reg);
3463         udelay(150);
3464
3465         reg = FDI_RX_IIR(pipe);
3466         for (tries = 0; tries < 5; tries++) {
3467                 temp = I915_READ(reg);
3468                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470                 if (temp & FDI_RX_SYMBOL_LOCK) {
3471                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3472                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3473                         break;
3474                 }
3475         }
3476         if (tries == 5)
3477                 DRM_ERROR("FDI train 2 fail!\n");
3478
3479         DRM_DEBUG_KMS("FDI train done\n");
3480
3481 }
3482
3483 static const int snb_b_fdi_train_param[] = {
3484         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3485         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3486         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3487         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3488 };
3489
3490 /* The FDI link training functions for SNB/Cougarpoint. */
3491 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3492 {
3493         struct drm_device *dev = crtc->dev;
3494         struct drm_i915_private *dev_priv = dev->dev_private;
3495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496         int pipe = intel_crtc->pipe;
3497         i915_reg_t reg;
3498         u32 temp, i, retry;
3499
3500         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501            for train result */
3502         reg = FDI_RX_IMR(pipe);
3503         temp = I915_READ(reg);
3504         temp &= ~FDI_RX_SYMBOL_LOCK;
3505         temp &= ~FDI_RX_BIT_LOCK;
3506         I915_WRITE(reg, temp);
3507
3508         POSTING_READ(reg);
3509         udelay(150);
3510
3511         /* enable CPU FDI TX and PCH FDI RX */
3512         reg = FDI_TX_CTL(pipe);
3513         temp = I915_READ(reg);
3514         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3515         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3516         temp &= ~FDI_LINK_TRAIN_NONE;
3517         temp |= FDI_LINK_TRAIN_PATTERN_1;
3518         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519         /* SNB-B */
3520         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3521         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3522
3523         I915_WRITE(FDI_RX_MISC(pipe),
3524                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
3526         reg = FDI_RX_CTL(pipe);
3527         temp = I915_READ(reg);
3528         if (HAS_PCH_CPT(dev)) {
3529                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531         } else {
3532                 temp &= ~FDI_LINK_TRAIN_NONE;
3533                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534         }
3535         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537         POSTING_READ(reg);
3538         udelay(150);
3539
3540         for (i = 0; i < 4; i++) {
3541                 reg = FDI_TX_CTL(pipe);
3542                 temp = I915_READ(reg);
3543                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544                 temp |= snb_b_fdi_train_param[i];
3545                 I915_WRITE(reg, temp);
3546
3547                 POSTING_READ(reg);
3548                 udelay(500);
3549
3550                 for (retry = 0; retry < 5; retry++) {
3551                         reg = FDI_RX_IIR(pipe);
3552                         temp = I915_READ(reg);
3553                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554                         if (temp & FDI_RX_BIT_LOCK) {
3555                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557                                 break;
3558                         }
3559                         udelay(50);
3560                 }
3561                 if (retry < 5)
3562                         break;
3563         }
3564         if (i == 4)
3565                 DRM_ERROR("FDI train 1 fail!\n");
3566
3567         /* Train 2 */
3568         reg = FDI_TX_CTL(pipe);
3569         temp = I915_READ(reg);
3570         temp &= ~FDI_LINK_TRAIN_NONE;
3571         temp |= FDI_LINK_TRAIN_PATTERN_2;
3572         if (IS_GEN6(dev)) {
3573                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574                 /* SNB-B */
3575                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576         }
3577         I915_WRITE(reg, temp);
3578
3579         reg = FDI_RX_CTL(pipe);
3580         temp = I915_READ(reg);
3581         if (HAS_PCH_CPT(dev)) {
3582                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584         } else {
3585                 temp &= ~FDI_LINK_TRAIN_NONE;
3586                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587         }
3588         I915_WRITE(reg, temp);
3589
3590         POSTING_READ(reg);
3591         udelay(150);
3592
3593         for (i = 0; i < 4; i++) {
3594                 reg = FDI_TX_CTL(pipe);
3595                 temp = I915_READ(reg);
3596                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597                 temp |= snb_b_fdi_train_param[i];
3598                 I915_WRITE(reg, temp);
3599
3600                 POSTING_READ(reg);
3601                 udelay(500);
3602
3603                 for (retry = 0; retry < 5; retry++) {
3604                         reg = FDI_RX_IIR(pipe);
3605                         temp = I915_READ(reg);
3606                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607                         if (temp & FDI_RX_SYMBOL_LOCK) {
3608                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610                                 break;
3611                         }
3612                         udelay(50);
3613                 }
3614                 if (retry < 5)
3615                         break;
3616         }
3617         if (i == 4)
3618                 DRM_ERROR("FDI train 2 fail!\n");
3619
3620         DRM_DEBUG_KMS("FDI train done.\n");
3621 }
3622
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629         int pipe = intel_crtc->pipe;
3630         i915_reg_t reg;
3631         u32 temp, i, j;
3632
3633         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634            for train result */
3635         reg = FDI_RX_IMR(pipe);
3636         temp = I915_READ(reg);
3637         temp &= ~FDI_RX_SYMBOL_LOCK;
3638         temp &= ~FDI_RX_BIT_LOCK;
3639         I915_WRITE(reg, temp);
3640
3641         POSTING_READ(reg);
3642         udelay(150);
3643
3644         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3645                       I915_READ(FDI_RX_IIR(pipe)));
3646
3647         /* Try each vswing and preemphasis setting twice before moving on */
3648         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3649                 /* disable first in case we need to retry */
3650                 reg = FDI_TX_CTL(pipe);
3651                 temp = I915_READ(reg);
3652                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3653                 temp &= ~FDI_TX_ENABLE;
3654                 I915_WRITE(reg, temp);
3655
3656                 reg = FDI_RX_CTL(pipe);
3657                 temp = I915_READ(reg);
3658                 temp &= ~FDI_LINK_TRAIN_AUTO;
3659                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3660                 temp &= ~FDI_RX_ENABLE;
3661                 I915_WRITE(reg, temp);
3662
3663                 /* enable CPU FDI TX and PCH FDI RX */
3664                 reg = FDI_TX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3667                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3668                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3669                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3670                 temp |= snb_b_fdi_train_param[j/2];
3671                 temp |= FDI_COMPOSITE_SYNC;
3672                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3673
3674                 I915_WRITE(FDI_RX_MISC(pipe),
3675                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3676
3677                 reg = FDI_RX_CTL(pipe);
3678                 temp = I915_READ(reg);
3679                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3680                 temp |= FDI_COMPOSITE_SYNC;
3681                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3682
3683                 POSTING_READ(reg);
3684                 udelay(1); /* should be 0.5us */
3685
3686                 for (i = 0; i < 4; i++) {
3687                         reg = FDI_RX_IIR(pipe);
3688                         temp = I915_READ(reg);
3689                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3690
3691                         if (temp & FDI_RX_BIT_LOCK ||
3692                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3693                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3694                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3695                                               i);
3696                                 break;
3697                         }
3698                         udelay(1); /* should be 0.5us */
3699                 }
3700                 if (i == 4) {
3701                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3702                         continue;
3703                 }
3704
3705                 /* Train 2 */
3706                 reg = FDI_TX_CTL(pipe);
3707                 temp = I915_READ(reg);
3708                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3709                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3710                 I915_WRITE(reg, temp);
3711
3712                 reg = FDI_RX_CTL(pipe);
3713                 temp = I915_READ(reg);
3714                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3716                 I915_WRITE(reg, temp);
3717
3718                 POSTING_READ(reg);
3719                 udelay(2); /* should be 1.5us */
3720
3721                 for (i = 0; i < 4; i++) {
3722                         reg = FDI_RX_IIR(pipe);
3723                         temp = I915_READ(reg);
3724                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3725
3726                         if (temp & FDI_RX_SYMBOL_LOCK ||
3727                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3728                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3729                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3730                                               i);
3731                                 goto train_done;
3732                         }
3733                         udelay(2); /* should be 1.5us */
3734                 }
3735                 if (i == 4)
3736                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3737         }
3738
3739 train_done:
3740         DRM_DEBUG_KMS("FDI train done.\n");
3741 }
3742
3743 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3744 {
3745         struct drm_device *dev = intel_crtc->base.dev;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         int pipe = intel_crtc->pipe;
3748         i915_reg_t reg;
3749         u32 temp;
3750
3751         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3752         reg = FDI_RX_CTL(pipe);
3753         temp = I915_READ(reg);
3754         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3755         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3756         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3758
3759         POSTING_READ(reg);
3760         udelay(200);
3761
3762         /* Switch from Rawclk to PCDclk */
3763         temp = I915_READ(reg);
3764         I915_WRITE(reg, temp | FDI_PCDCLK);
3765
3766         POSTING_READ(reg);
3767         udelay(200);
3768
3769         /* Enable CPU FDI TX PLL, always on for Ironlake */
3770         reg = FDI_TX_CTL(pipe);
3771         temp = I915_READ(reg);
3772         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3773                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3774
3775                 POSTING_READ(reg);
3776                 udelay(100);
3777         }
3778 }
3779
3780 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3781 {
3782         struct drm_device *dev = intel_crtc->base.dev;
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         int pipe = intel_crtc->pipe;
3785         i915_reg_t reg;
3786         u32 temp;
3787
3788         /* Switch from PCDclk to Rawclk */
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793         /* Disable CPU FDI TX PLL */
3794         reg = FDI_TX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798         POSTING_READ(reg);
3799         udelay(100);
3800
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805         /* Wait for the clocks to turn off. */
3806         POSTING_READ(reg);
3807         udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815         int pipe = intel_crtc->pipe;
3816         i915_reg_t reg;
3817         u32 temp;
3818
3819         /* disable CPU FDI tx and PCH FDI rx */
3820         reg = FDI_TX_CTL(pipe);
3821         temp = I915_READ(reg);
3822         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3823         POSTING_READ(reg);
3824
3825         reg = FDI_RX_CTL(pipe);
3826         temp = I915_READ(reg);
3827         temp &= ~(0x7 << 16);
3828         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3829         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3830
3831         POSTING_READ(reg);
3832         udelay(100);
3833
3834         /* Ironlake workaround, disable clock pointer after downing FDI */
3835         if (HAS_PCH_IBX(dev))
3836                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3837
3838         /* still set train pattern 1 */
3839         reg = FDI_TX_CTL(pipe);
3840         temp = I915_READ(reg);
3841         temp &= ~FDI_LINK_TRAIN_NONE;
3842         temp |= FDI_LINK_TRAIN_PATTERN_1;
3843         I915_WRITE(reg, temp);
3844
3845         reg = FDI_RX_CTL(pipe);
3846         temp = I915_READ(reg);
3847         if (HAS_PCH_CPT(dev)) {
3848                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3849                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3850         } else {
3851                 temp &= ~FDI_LINK_TRAIN_NONE;
3852                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3853         }
3854         /* BPC in FDI rx is consistent with that in PIPECONF */
3855         temp &= ~(0x07 << 16);
3856         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3857         I915_WRITE(reg, temp);
3858
3859         POSTING_READ(reg);
3860         udelay(100);
3861 }
3862
3863 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3864 {
3865         struct intel_crtc *crtc;
3866
3867         /* Note that we don't need to be called with mode_config.lock here
3868          * as our list of CRTC objects is static for the lifetime of the
3869          * device and so cannot disappear as we iterate. Similarly, we can
3870          * happily treat the predicates as racy, atomic checks as userspace
3871          * cannot claim and pin a new fb without at least acquring the
3872          * struct_mutex and so serialising with us.
3873          */
3874         for_each_intel_crtc(dev, crtc) {
3875                 if (atomic_read(&crtc->unpin_work_count) == 0)
3876                         continue;
3877
3878                 if (crtc->unpin_work)
3879                         intel_wait_for_vblank(dev, crtc->pipe);
3880
3881                 return true;
3882         }
3883
3884         return false;
3885 }
3886
3887 static void page_flip_completed(struct intel_crtc *intel_crtc)
3888 {
3889         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3890         struct intel_unpin_work *work = intel_crtc->unpin_work;
3891
3892         /* ensure that the unpin work is consistent wrt ->pending. */
3893         smp_rmb();
3894         intel_crtc->unpin_work = NULL;
3895
3896         if (work->event)
3897                 drm_send_vblank_event(intel_crtc->base.dev,
3898                                       intel_crtc->pipe,
3899                                       work->event);
3900
3901         drm_crtc_vblank_put(&intel_crtc->base);
3902
3903         wake_up_all(&dev_priv->pending_flip_queue);
3904         queue_work(dev_priv->wq, &work->work);
3905
3906         trace_i915_flip_complete(intel_crtc->plane,
3907                                  work->pending_flip_obj);
3908 }
3909
3910 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3911 {
3912         struct drm_device *dev = crtc->dev;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         long ret;
3915
3916         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3917
3918         ret = wait_event_interruptible_timeout(
3919                                         dev_priv->pending_flip_queue,
3920                                         !intel_crtc_has_pending_flip(crtc),
3921                                         60*HZ);
3922
3923         if (ret < 0)
3924                 return ret;
3925
3926         if (ret == 0) {
3927                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928
3929                 spin_lock_irq(&dev->event_lock);
3930                 if (intel_crtc->unpin_work) {
3931                         WARN_ONCE(1, "Removing stuck page flip\n");
3932                         page_flip_completed(intel_crtc);
3933                 }
3934                 spin_unlock_irq(&dev->event_lock);
3935         }
3936
3937         return 0;
3938 }
3939
3940 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3941 {
3942         u32 temp;
3943
3944         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3945
3946         mutex_lock(&dev_priv->sb_lock);
3947
3948         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3949         temp |= SBI_SSCCTL_DISABLE;
3950         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3951
3952         mutex_unlock(&dev_priv->sb_lock);
3953 }
3954
3955 /* Program iCLKIP clock to the desired frequency */
3956 static void lpt_program_iclkip(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3961         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3962         u32 temp;
3963
3964         lpt_disable_iclkip(dev_priv);
3965
3966         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3967         if (clock == 20000) {
3968                 auxdiv = 1;
3969                 divsel = 0x41;
3970                 phaseinc = 0x20;
3971         } else {
3972                 /* The iCLK virtual clock root frequency is in MHz,
3973                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3974                  * divisors, it is necessary to divide one by another, so we
3975                  * convert the virtual clock precision to KHz here for higher
3976                  * precision.
3977                  */
3978                 u32 iclk_virtual_root_freq = 172800 * 1000;
3979                 u32 iclk_pi_range = 64;
3980                 u32 desired_divisor, msb_divisor_value, pi_value;
3981
3982                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3983                 msb_divisor_value = desired_divisor / iclk_pi_range;
3984                 pi_value = desired_divisor % iclk_pi_range;
3985
3986                 auxdiv = 0;
3987                 divsel = msb_divisor_value - 2;
3988                 phaseinc = pi_value;
3989         }
3990
3991         /* This should not happen with any sane values */
3992         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3993                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3994         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3995                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3996
3997         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3998                         clock,
3999                         auxdiv,
4000                         divsel,
4001                         phasedir,
4002                         phaseinc);
4003
4004         mutex_lock(&dev_priv->sb_lock);
4005
4006         /* Program SSCDIVINTPHASE6 */
4007         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4008         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4009         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4010         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4011         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4012         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4013         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4014         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4015
4016         /* Program SSCAUXDIV */
4017         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4018         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4019         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4020         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4021
4022         /* Enable modulator and associated divider */
4023         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4024         temp &= ~SBI_SSCCTL_DISABLE;
4025         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4026
4027         mutex_unlock(&dev_priv->sb_lock);
4028
4029         /* Wait for initialization time */
4030         udelay(24);
4031
4032         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4033 }
4034
4035 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4036                                                 enum pipe pch_transcoder)
4037 {
4038         struct drm_device *dev = crtc->base.dev;
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4041
4042         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4043                    I915_READ(HTOTAL(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4045                    I915_READ(HBLANK(cpu_transcoder)));
4046         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4047                    I915_READ(HSYNC(cpu_transcoder)));
4048
4049         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4050                    I915_READ(VTOTAL(cpu_transcoder)));
4051         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4052                    I915_READ(VBLANK(cpu_transcoder)));
4053         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4054                    I915_READ(VSYNC(cpu_transcoder)));
4055         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4056                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4057 }
4058
4059 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4060 {
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         uint32_t temp;
4063
4064         temp = I915_READ(SOUTH_CHICKEN1);
4065         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4066                 return;
4067
4068         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4069         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4070
4071         temp &= ~FDI_BC_BIFURCATION_SELECT;
4072         if (enable)
4073                 temp |= FDI_BC_BIFURCATION_SELECT;
4074
4075         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4076         I915_WRITE(SOUTH_CHICKEN1, temp);
4077         POSTING_READ(SOUTH_CHICKEN1);
4078 }
4079
4080 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4081 {
4082         struct drm_device *dev = intel_crtc->base.dev;
4083
4084         switch (intel_crtc->pipe) {
4085         case PIPE_A:
4086                 break;
4087         case PIPE_B:
4088                 if (intel_crtc->config->fdi_lanes > 2)
4089                         cpt_set_fdi_bc_bifurcation(dev, false);
4090                 else
4091                         cpt_set_fdi_bc_bifurcation(dev, true);
4092
4093                 break;
4094         case PIPE_C:
4095                 cpt_set_fdi_bc_bifurcation(dev, true);
4096
4097                 break;
4098         default:
4099                 BUG();
4100         }
4101 }
4102
4103 /* Return which DP Port should be selected for Transcoder DP control */
4104 static enum port
4105 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         struct intel_encoder *encoder;
4109
4110         for_each_encoder_on_crtc(dev, crtc, encoder) {
4111                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4112                     encoder->type == INTEL_OUTPUT_EDP)
4113                         return enc_to_dig_port(&encoder->base)->port;
4114         }
4115
4116         return -1;
4117 }
4118
4119 /*
4120  * Enable PCH resources required for PCH ports:
4121  *   - PCH PLLs
4122  *   - FDI training & RX/TX
4123  *   - update transcoder timings
4124  *   - DP transcoding bits
4125  *   - transcoder
4126  */
4127 static void ironlake_pch_enable(struct drm_crtc *crtc)
4128 {
4129         struct drm_device *dev = crtc->dev;
4130         struct drm_i915_private *dev_priv = dev->dev_private;
4131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132         int pipe = intel_crtc->pipe;
4133         u32 temp;
4134
4135         assert_pch_transcoder_disabled(dev_priv, pipe);
4136
4137         if (IS_IVYBRIDGE(dev))
4138                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4139
4140         /* Write the TU size bits before fdi link training, so that error
4141          * detection works. */
4142         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4143                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4144
4145         /*
4146          * Sometimes spurious CPU pipe underruns happen during FDI
4147          * training, at least with VGA+HDMI cloning. Suppress them.
4148          */
4149         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4150
4151         /* For PCH output, training FDI link */
4152         dev_priv->display.fdi_link_train(crtc);
4153
4154         /* We need to program the right clock selection before writing the pixel
4155          * mutliplier into the DPLL. */
4156         if (HAS_PCH_CPT(dev)) {
4157                 u32 sel;
4158
4159                 temp = I915_READ(PCH_DPLL_SEL);
4160                 temp |= TRANS_DPLL_ENABLE(pipe);
4161                 sel = TRANS_DPLLB_SEL(pipe);
4162                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4163                         temp |= sel;
4164                 else
4165                         temp &= ~sel;
4166                 I915_WRITE(PCH_DPLL_SEL, temp);
4167         }
4168
4169         /* XXX: pch pll's can be enabled any time before we enable the PCH
4170          * transcoder, and we actually should do this to not upset any PCH
4171          * transcoder that already use the clock when we share it.
4172          *
4173          * Note that enable_shared_dpll tries to do the right thing, but
4174          * get_shared_dpll unconditionally resets the pll - we need that to have
4175          * the right LVDS enable sequence. */
4176         intel_enable_shared_dpll(intel_crtc);
4177
4178         /* set transcoder timing, panel must allow it */
4179         assert_panel_unlocked(dev_priv, pipe);
4180         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4181
4182         intel_fdi_normal_train(crtc);
4183
4184         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4185
4186         /* For PCH DP, enable TRANS_DP_CTL */
4187         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4188                 const struct drm_display_mode *adjusted_mode =
4189                         &intel_crtc->config->base.adjusted_mode;
4190                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4191                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4192                 temp = I915_READ(reg);
4193                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4194                           TRANS_DP_SYNC_MASK |
4195                           TRANS_DP_BPC_MASK);
4196                 temp |= TRANS_DP_OUTPUT_ENABLE;
4197                 temp |= bpc << 9; /* same format but at 11:9 */
4198
4199                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4200                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4201                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4202                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4203
4204                 switch (intel_trans_dp_port_sel(crtc)) {
4205                 case PORT_B:
4206                         temp |= TRANS_DP_PORT_SEL_B;
4207                         break;
4208                 case PORT_C:
4209                         temp |= TRANS_DP_PORT_SEL_C;
4210                         break;
4211                 case PORT_D:
4212                         temp |= TRANS_DP_PORT_SEL_D;
4213                         break;
4214                 default:
4215                         BUG();
4216                 }
4217
4218                 I915_WRITE(reg, temp);
4219         }
4220
4221         ironlake_enable_pch_transcoder(dev_priv, pipe);
4222 }
4223
4224 static void lpt_pch_enable(struct drm_crtc *crtc)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4230
4231         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4232
4233         lpt_program_iclkip(crtc);
4234
4235         /* Set transcoder timing. */
4236         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4237
4238         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4239 }
4240
4241 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4242                                                 struct intel_crtc_state *crtc_state)
4243 {
4244         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4245         struct intel_shared_dpll *pll;
4246         struct intel_shared_dpll_config *shared_dpll;
4247         enum intel_dpll_id i;
4248         int max = dev_priv->num_shared_dpll;
4249
4250         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4251
4252         if (HAS_PCH_IBX(dev_priv->dev)) {
4253                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4254                 i = (enum intel_dpll_id) crtc->pipe;
4255                 pll = &dev_priv->shared_dplls[i];
4256
4257                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4258                               crtc->base.base.id, pll->name);
4259
4260                 WARN_ON(shared_dpll[i].crtc_mask);
4261
4262                 goto found;
4263         }
4264
4265         if (IS_BROXTON(dev_priv->dev)) {
4266                 /* PLL is attached to port in bxt */
4267                 struct intel_encoder *encoder;
4268                 struct intel_digital_port *intel_dig_port;
4269
4270                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4271                 if (WARN_ON(!encoder))
4272                         return NULL;
4273
4274                 intel_dig_port = enc_to_dig_port(&encoder->base);
4275                 /* 1:1 mapping between ports and PLLs */
4276                 i = (enum intel_dpll_id)intel_dig_port->port;
4277                 pll = &dev_priv->shared_dplls[i];
4278                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4279                         crtc->base.base.id, pll->name);
4280                 WARN_ON(shared_dpll[i].crtc_mask);
4281
4282                 goto found;
4283         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4284                 /* Do not consider SPLL */
4285                 max = 2;
4286
4287         for (i = 0; i < max; i++) {
4288                 pll = &dev_priv->shared_dplls[i];
4289
4290                 /* Only want to check enabled timings first */
4291                 if (shared_dpll[i].crtc_mask == 0)
4292                         continue;
4293
4294                 if (memcmp(&crtc_state->dpll_hw_state,
4295                            &shared_dpll[i].hw_state,
4296                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4297                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4298                                       crtc->base.base.id, pll->name,
4299                                       shared_dpll[i].crtc_mask,
4300                                       pll->active);
4301                         goto found;
4302                 }
4303         }
4304
4305         /* Ok no matching timings, maybe there's a free one? */
4306         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4307                 pll = &dev_priv->shared_dplls[i];
4308                 if (shared_dpll[i].crtc_mask == 0) {
4309                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4310                                       crtc->base.base.id, pll->name);
4311                         goto found;
4312                 }
4313         }
4314
4315         return NULL;
4316
4317 found:
4318         if (shared_dpll[i].crtc_mask == 0)
4319                 shared_dpll[i].hw_state =
4320                         crtc_state->dpll_hw_state;
4321
4322         crtc_state->shared_dpll = i;
4323         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4324                          pipe_name(crtc->pipe));
4325
4326         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4327
4328         return pll;
4329 }
4330
4331 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4332 {
4333         struct drm_i915_private *dev_priv = to_i915(state->dev);
4334         struct intel_shared_dpll_config *shared_dpll;
4335         struct intel_shared_dpll *pll;
4336         enum intel_dpll_id i;
4337
4338         if (!to_intel_atomic_state(state)->dpll_set)
4339                 return;
4340
4341         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4342         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4343                 pll = &dev_priv->shared_dplls[i];
4344                 pll->config = shared_dpll[i];
4345         }
4346 }
4347
4348 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4349 {
4350         struct drm_i915_private *dev_priv = dev->dev_private;
4351         i915_reg_t dslreg = PIPEDSL(pipe);
4352         u32 temp;
4353
4354         temp = I915_READ(dslreg);
4355         udelay(500);
4356         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4357                 if (wait_for(I915_READ(dslreg) != temp, 5))
4358                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4359         }
4360 }
4361
4362 static int
4363 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4364                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4365                   int src_w, int src_h, int dst_w, int dst_h)
4366 {
4367         struct intel_crtc_scaler_state *scaler_state =
4368                 &crtc_state->scaler_state;
4369         struct intel_crtc *intel_crtc =
4370                 to_intel_crtc(crtc_state->base.crtc);
4371         int need_scaling;
4372
4373         need_scaling = intel_rotation_90_or_270(rotation) ?
4374                 (src_h != dst_w || src_w != dst_h):
4375                 (src_w != dst_w || src_h != dst_h);
4376
4377         /*
4378          * if plane is being disabled or scaler is no more required or force detach
4379          *  - free scaler binded to this plane/crtc
4380          *  - in order to do this, update crtc->scaler_usage
4381          *
4382          * Here scaler state in crtc_state is set free so that
4383          * scaler can be assigned to other user. Actual register
4384          * update to free the scaler is done in plane/panel-fit programming.
4385          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4386          */
4387         if (force_detach || !need_scaling) {
4388                 if (*scaler_id >= 0) {
4389                         scaler_state->scaler_users &= ~(1 << scaler_user);
4390                         scaler_state->scalers[*scaler_id].in_use = 0;
4391
4392                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4393                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4394                                 intel_crtc->pipe, scaler_user, *scaler_id,
4395                                 scaler_state->scaler_users);
4396                         *scaler_id = -1;
4397                 }
4398                 return 0;
4399         }
4400
4401         /* range checks */
4402         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4403                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4404
4405                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4406                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4407                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4408                         "size is out of scaler range\n",
4409                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4410                 return -EINVAL;
4411         }
4412
4413         /* mark this plane as a scaler user in crtc_state */
4414         scaler_state->scaler_users |= (1 << scaler_user);
4415         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4416                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4417                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4418                 scaler_state->scaler_users);
4419
4420         return 0;
4421 }
4422
4423 /**
4424  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4425  *
4426  * @state: crtc's scaler state
4427  *
4428  * Return
4429  *     0 - scaler_usage updated successfully
4430  *    error - requested scaling cannot be supported or other error condition
4431  */
4432 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4433 {
4434         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4435         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4436
4437         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4438                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4439
4440         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4441                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4442                 state->pipe_src_w, state->pipe_src_h,
4443                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4444 }
4445
4446 /**
4447  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4448  *
4449  * @state: crtc's scaler state
4450  * @plane_state: atomic plane state to update
4451  *
4452  * Return
4453  *     0 - scaler_usage updated successfully
4454  *    error - requested scaling cannot be supported or other error condition
4455  */
4456 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4457                                    struct intel_plane_state *plane_state)
4458 {
4459
4460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4461         struct intel_plane *intel_plane =
4462                 to_intel_plane(plane_state->base.plane);
4463         struct drm_framebuffer *fb = plane_state->base.fb;
4464         int ret;
4465
4466         bool force_detach = !fb || !plane_state->visible;
4467
4468         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4469                       intel_plane->base.base.id, intel_crtc->pipe,
4470                       drm_plane_index(&intel_plane->base));
4471
4472         ret = skl_update_scaler(crtc_state, force_detach,
4473                                 drm_plane_index(&intel_plane->base),
4474                                 &plane_state->scaler_id,
4475                                 plane_state->base.rotation,
4476                                 drm_rect_width(&plane_state->src) >> 16,
4477                                 drm_rect_height(&plane_state->src) >> 16,
4478                                 drm_rect_width(&plane_state->dst),
4479                                 drm_rect_height(&plane_state->dst));
4480
4481         if (ret || plane_state->scaler_id < 0)
4482                 return ret;
4483
4484         /* check colorkey */
4485         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4486                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4487                               intel_plane->base.base.id);
4488                 return -EINVAL;
4489         }
4490
4491         /* Check src format */
4492         switch (fb->pixel_format) {
4493         case DRM_FORMAT_RGB565:
4494         case DRM_FORMAT_XBGR8888:
4495         case DRM_FORMAT_XRGB8888:
4496         case DRM_FORMAT_ABGR8888:
4497         case DRM_FORMAT_ARGB8888:
4498         case DRM_FORMAT_XRGB2101010:
4499         case DRM_FORMAT_XBGR2101010:
4500         case DRM_FORMAT_YUYV:
4501         case DRM_FORMAT_YVYU:
4502         case DRM_FORMAT_UYVY:
4503         case DRM_FORMAT_VYUY:
4504                 break;
4505         default:
4506                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4507                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4508                 return -EINVAL;
4509         }
4510
4511         return 0;
4512 }
4513
4514 static void skylake_scaler_disable(struct intel_crtc *crtc)
4515 {
4516         int i;
4517
4518         for (i = 0; i < crtc->num_scalers; i++)
4519                 skl_detach_scaler(crtc, i);
4520 }
4521
4522 static void skylake_pfit_enable(struct intel_crtc *crtc)
4523 {
4524         struct drm_device *dev = crtc->base.dev;
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         int pipe = crtc->pipe;
4527         struct intel_crtc_scaler_state *scaler_state =
4528                 &crtc->config->scaler_state;
4529
4530         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4531
4532         if (crtc->config->pch_pfit.enabled) {
4533                 int id;
4534
4535                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4536                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4537                         return;
4538                 }
4539
4540                 id = scaler_state->scaler_id;
4541                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4542                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4543                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4544                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4545
4546                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4547         }
4548 }
4549
4550 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4551 {
4552         struct drm_device *dev = crtc->base.dev;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         int pipe = crtc->pipe;
4555
4556         if (crtc->config->pch_pfit.enabled) {
4557                 /* Force use of hard-coded filter coefficients
4558                  * as some pre-programmed values are broken,
4559                  * e.g. x201.
4560                  */
4561                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4562                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4563                                                  PF_PIPE_SEL_IVB(pipe));
4564                 else
4565                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4566                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4567                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4568         }
4569 }
4570
4571 void hsw_enable_ips(struct intel_crtc *crtc)
4572 {
4573         struct drm_device *dev = crtc->base.dev;
4574         struct drm_i915_private *dev_priv = dev->dev_private;
4575
4576         if (!crtc->config->ips_enabled)
4577                 return;
4578
4579         /* We can only enable IPS after we enable a plane and wait for a vblank */
4580         intel_wait_for_vblank(dev, crtc->pipe);
4581
4582         assert_plane_enabled(dev_priv, crtc->plane);
4583         if (IS_BROADWELL(dev)) {
4584                 mutex_lock(&dev_priv->rps.hw_lock);
4585                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4586                 mutex_unlock(&dev_priv->rps.hw_lock);
4587                 /* Quoting Art Runyan: "its not safe to expect any particular
4588                  * value in IPS_CTL bit 31 after enabling IPS through the
4589                  * mailbox." Moreover, the mailbox may return a bogus state,
4590                  * so we need to just enable it and continue on.
4591                  */
4592         } else {
4593                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4594                 /* The bit only becomes 1 in the next vblank, so this wait here
4595                  * is essentially intel_wait_for_vblank. If we don't have this
4596                  * and don't wait for vblanks until the end of crtc_enable, then
4597                  * the HW state readout code will complain that the expected
4598                  * IPS_CTL value is not the one we read. */
4599                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4600                         DRM_ERROR("Timed out waiting for IPS enable\n");
4601         }
4602 }
4603
4604 void hsw_disable_ips(struct intel_crtc *crtc)
4605 {
4606         struct drm_device *dev = crtc->base.dev;
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609         if (!crtc->config->ips_enabled)
4610                 return;
4611
4612         assert_plane_enabled(dev_priv, crtc->plane);
4613         if (IS_BROADWELL(dev)) {
4614                 mutex_lock(&dev_priv->rps.hw_lock);
4615                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4616                 mutex_unlock(&dev_priv->rps.hw_lock);
4617                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4618                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4619                         DRM_ERROR("Timed out waiting for IPS disable\n");
4620         } else {
4621                 I915_WRITE(IPS_CTL, 0);
4622                 POSTING_READ(IPS_CTL);
4623         }
4624
4625         /* We need to wait for a vblank before we can disable the plane. */
4626         intel_wait_for_vblank(dev, crtc->pipe);
4627 }
4628
4629 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4630 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4631 {
4632         struct drm_device *dev = crtc->dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4635         enum pipe pipe = intel_crtc->pipe;
4636         int i;
4637         bool reenable_ips = false;
4638
4639         /* The clocks have to be on to load the palette. */
4640         if (!crtc->state->active)
4641                 return;
4642
4643         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4644                 if (intel_crtc->config->has_dsi_encoder)
4645                         assert_dsi_pll_enabled(dev_priv);
4646                 else
4647                         assert_pll_enabled(dev_priv, pipe);
4648         }
4649
4650         /* Workaround : Do not read or write the pipe palette/gamma data while
4651          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4652          */
4653         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4654             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4655              GAMMA_MODE_MODE_SPLIT)) {
4656                 hsw_disable_ips(intel_crtc);
4657                 reenable_ips = true;
4658         }
4659
4660         for (i = 0; i < 256; i++) {
4661                 i915_reg_t palreg;
4662
4663                 if (HAS_GMCH_DISPLAY(dev))
4664                         palreg = PALETTE(pipe, i);
4665                 else
4666                         palreg = LGC_PALETTE(pipe, i);
4667
4668                 I915_WRITE(palreg,
4669                            (intel_crtc->lut_r[i] << 16) |
4670                            (intel_crtc->lut_g[i] << 8) |
4671                            intel_crtc->lut_b[i]);
4672         }
4673
4674         if (reenable_ips)
4675                 hsw_enable_ips(intel_crtc);
4676 }
4677
4678 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4679 {
4680         if (intel_crtc->overlay) {
4681                 struct drm_device *dev = intel_crtc->base.dev;
4682                 struct drm_i915_private *dev_priv = dev->dev_private;
4683
4684                 mutex_lock(&dev->struct_mutex);
4685                 dev_priv->mm.interruptible = false;
4686                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4687                 dev_priv->mm.interruptible = true;
4688                 mutex_unlock(&dev->struct_mutex);
4689         }
4690
4691         /* Let userspace switch the overlay on again. In most cases userspace
4692          * has to recompute where to put it anyway.
4693          */
4694 }
4695
4696 /**
4697  * intel_post_enable_primary - Perform operations after enabling primary plane
4698  * @crtc: the CRTC whose primary plane was just enabled
4699  *
4700  * Performs potentially sleeping operations that must be done after the primary
4701  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4702  * called due to an explicit primary plane update, or due to an implicit
4703  * re-enable that is caused when a sprite plane is updated to no longer
4704  * completely hide the primary plane.
4705  */
4706 static void
4707 intel_post_enable_primary(struct drm_crtc *crtc)
4708 {
4709         struct drm_device *dev = crtc->dev;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712         int pipe = intel_crtc->pipe;
4713
4714         /*
4715          * FIXME IPS should be fine as long as one plane is
4716          * enabled, but in practice it seems to have problems
4717          * when going from primary only to sprite only and vice
4718          * versa.
4719          */
4720         hsw_enable_ips(intel_crtc);
4721
4722         /*
4723          * Gen2 reports pipe underruns whenever all planes are disabled.
4724          * So don't enable underrun reporting before at least some planes
4725          * are enabled.
4726          * FIXME: Need to fix the logic to work when we turn off all planes
4727          * but leave the pipe running.
4728          */
4729         if (IS_GEN2(dev))
4730                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4731
4732         /* Underruns don't always raise interrupts, so check manually. */
4733         intel_check_cpu_fifo_underruns(dev_priv);
4734         intel_check_pch_fifo_underruns(dev_priv);
4735 }
4736
4737 /**
4738  * intel_pre_disable_primary - Perform operations before disabling primary plane
4739  * @crtc: the CRTC whose primary plane is to be disabled
4740  *
4741  * Performs potentially sleeping operations that must be done before the
4742  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4743  * be called due to an explicit primary plane update, or due to an implicit
4744  * disable that is caused when a sprite plane completely hides the primary
4745  * plane.
4746  */
4747 static void
4748 intel_pre_disable_primary(struct drm_crtc *crtc)
4749 {
4750         struct drm_device *dev = crtc->dev;
4751         struct drm_i915_private *dev_priv = dev->dev_private;
4752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753         int pipe = intel_crtc->pipe;
4754
4755         /*
4756          * Gen2 reports pipe underruns whenever all planes are disabled.
4757          * So diasble underrun reporting before all the planes get disabled.
4758          * FIXME: Need to fix the logic to work when we turn off all planes
4759          * but leave the pipe running.
4760          */
4761         if (IS_GEN2(dev))
4762                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4763
4764         /*
4765          * Vblank time updates from the shadow to live plane control register
4766          * are blocked if the memory self-refresh mode is active at that
4767          * moment. So to make sure the plane gets truly disabled, disable
4768          * first the self-refresh mode. The self-refresh enable bit in turn
4769          * will be checked/applied by the HW only at the next frame start
4770          * event which is after the vblank start event, so we need to have a
4771          * wait-for-vblank between disabling the plane and the pipe.
4772          */
4773         if (HAS_GMCH_DISPLAY(dev)) {
4774                 intel_set_memory_cxsr(dev_priv, false);
4775                 dev_priv->wm.vlv.cxsr = false;
4776                 intel_wait_for_vblank(dev, pipe);
4777         }
4778
4779         /*
4780          * FIXME IPS should be fine as long as one plane is
4781          * enabled, but in practice it seems to have problems
4782          * when going from primary only to sprite only and vice
4783          * versa.
4784          */
4785         hsw_disable_ips(intel_crtc);
4786 }
4787
4788 static void intel_post_plane_update(struct intel_crtc *crtc)
4789 {
4790         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791         struct intel_crtc_state *pipe_config =
4792                 to_intel_crtc_state(crtc->base.state);
4793         struct drm_device *dev = crtc->base.dev;
4794
4795         if (atomic->wait_vblank)
4796                 intel_wait_for_vblank(dev, crtc->pipe);
4797
4798         intel_frontbuffer_flip(dev, atomic->fb_bits);
4799
4800         crtc->wm.cxsr_allowed = true;
4801
4802         if (pipe_config->wm_changed && pipe_config->base.active)
4803                 intel_update_watermarks(&crtc->base);
4804
4805         if (atomic->update_fbc)
4806                 intel_fbc_post_update(crtc);
4807
4808         if (atomic->post_enable_primary)
4809                 intel_post_enable_primary(&crtc->base);
4810
4811         memset(atomic, 0, sizeof(*atomic));
4812 }
4813
4814 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4815 {
4816         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4817         struct drm_device *dev = crtc->base.dev;
4818         struct drm_i915_private *dev_priv = dev->dev_private;
4819         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4820         struct intel_crtc_state *pipe_config =
4821                 to_intel_crtc_state(crtc->base.state);
4822         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4823         struct drm_plane *primary = crtc->base.primary;
4824         struct drm_plane_state *old_pri_state =
4825                 drm_atomic_get_existing_plane_state(old_state, primary);
4826         bool modeset = needs_modeset(&pipe_config->base);
4827
4828         if (atomic->update_fbc)
4829                 intel_fbc_pre_update(crtc);
4830
4831         if (old_pri_state) {
4832                 struct intel_plane_state *primary_state =
4833                         to_intel_plane_state(primary->state);
4834                 struct intel_plane_state *old_primary_state =
4835                         to_intel_plane_state(old_pri_state);
4836
4837                 if (old_primary_state->visible &&
4838                     (modeset || !primary_state->visible))
4839                         intel_pre_disable_primary(&crtc->base);
4840         }
4841
4842         if (pipe_config->disable_cxsr) {
4843                 crtc->wm.cxsr_allowed = false;
4844
4845                 if (old_crtc_state->base.active)
4846                         intel_set_memory_cxsr(dev_priv, false);
4847         }
4848
4849         if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4850                 intel_update_watermarks(&crtc->base);
4851 }
4852
4853 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4854 {
4855         struct drm_device *dev = crtc->dev;
4856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857         struct drm_plane *p;
4858         int pipe = intel_crtc->pipe;
4859
4860         intel_crtc_dpms_overlay_disable(intel_crtc);
4861
4862         drm_for_each_plane_mask(p, dev, plane_mask)
4863                 to_intel_plane(p)->disable_plane(p, crtc);
4864
4865         /*
4866          * FIXME: Once we grow proper nuclear flip support out of this we need
4867          * to compute the mask of flip planes precisely. For the time being
4868          * consider this a flip to a NULL plane.
4869          */
4870         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4871 }
4872
4873 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4874 {
4875         struct drm_device *dev = crtc->dev;
4876         struct drm_i915_private *dev_priv = dev->dev_private;
4877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878         struct intel_encoder *encoder;
4879         int pipe = intel_crtc->pipe;
4880
4881         if (WARN_ON(intel_crtc->active))
4882                 return;
4883
4884         if (intel_crtc->config->has_pch_encoder)
4885                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4886
4887         if (intel_crtc->config->has_pch_encoder)
4888                 intel_prepare_shared_dpll(intel_crtc);
4889
4890         if (intel_crtc->config->has_dp_encoder)
4891                 intel_dp_set_m_n(intel_crtc, M1_N1);
4892
4893         intel_set_pipe_timings(intel_crtc);
4894
4895         if (intel_crtc->config->has_pch_encoder) {
4896                 intel_cpu_transcoder_set_m_n(intel_crtc,
4897                                      &intel_crtc->config->fdi_m_n, NULL);
4898         }
4899
4900         ironlake_set_pipeconf(crtc);
4901
4902         intel_crtc->active = true;
4903
4904         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4905
4906         for_each_encoder_on_crtc(dev, crtc, encoder)
4907                 if (encoder->pre_enable)
4908                         encoder->pre_enable(encoder);
4909
4910         if (intel_crtc->config->has_pch_encoder) {
4911                 /* Note: FDI PLL enabling _must_ be done before we enable the
4912                  * cpu pipes, hence this is separate from all the other fdi/pch
4913                  * enabling. */
4914                 ironlake_fdi_pll_enable(intel_crtc);
4915         } else {
4916                 assert_fdi_tx_disabled(dev_priv, pipe);
4917                 assert_fdi_rx_disabled(dev_priv, pipe);
4918         }
4919
4920         ironlake_pfit_enable(intel_crtc);
4921
4922         /*
4923          * On ILK+ LUT must be loaded before the pipe is running but with
4924          * clocks enabled
4925          */
4926         intel_crtc_load_lut(crtc);
4927
4928         intel_update_watermarks(crtc);
4929         intel_enable_pipe(intel_crtc);
4930
4931         if (intel_crtc->config->has_pch_encoder)
4932                 ironlake_pch_enable(crtc);
4933
4934         assert_vblank_disabled(crtc);
4935         drm_crtc_vblank_on(crtc);
4936
4937         for_each_encoder_on_crtc(dev, crtc, encoder)
4938                 encoder->enable(encoder);
4939
4940         if (HAS_PCH_CPT(dev))
4941                 cpt_verify_modeset(dev, intel_crtc->pipe);
4942
4943         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4944         if (intel_crtc->config->has_pch_encoder)
4945                 intel_wait_for_vblank(dev, pipe);
4946         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4947 }
4948
4949 /* IPS only exists on ULT machines and is tied to pipe A. */
4950 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4951 {
4952         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4953 }
4954
4955 static void haswell_crtc_enable(struct drm_crtc *crtc)
4956 {
4957         struct drm_device *dev = crtc->dev;
4958         struct drm_i915_private *dev_priv = dev->dev_private;
4959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4960         struct intel_encoder *encoder;
4961         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4962         struct intel_crtc_state *pipe_config =
4963                 to_intel_crtc_state(crtc->state);
4964
4965         if (WARN_ON(intel_crtc->active))
4966                 return;
4967
4968         if (intel_crtc->config->has_pch_encoder)
4969                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4970                                                       false);
4971
4972         if (intel_crtc_to_shared_dpll(intel_crtc))
4973                 intel_enable_shared_dpll(intel_crtc);
4974
4975         if (intel_crtc->config->has_dp_encoder)
4976                 intel_dp_set_m_n(intel_crtc, M1_N1);
4977
4978         intel_set_pipe_timings(intel_crtc);
4979
4980         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4981                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4982                            intel_crtc->config->pixel_multiplier - 1);
4983         }
4984
4985         if (intel_crtc->config->has_pch_encoder) {
4986                 intel_cpu_transcoder_set_m_n(intel_crtc,
4987                                      &intel_crtc->config->fdi_m_n, NULL);
4988         }
4989
4990         haswell_set_pipeconf(crtc);
4991
4992         intel_set_pipe_csc(crtc);
4993
4994         intel_crtc->active = true;
4995
4996         if (intel_crtc->config->has_pch_encoder)
4997                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4998         else
4999                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5000
5001         for_each_encoder_on_crtc(dev, crtc, encoder) {
5002                 if (encoder->pre_enable)
5003                         encoder->pre_enable(encoder);
5004         }
5005
5006         if (intel_crtc->config->has_pch_encoder)
5007                 dev_priv->display.fdi_link_train(crtc);
5008
5009         if (!intel_crtc->config->has_dsi_encoder)
5010                 intel_ddi_enable_pipe_clock(intel_crtc);
5011
5012         if (INTEL_INFO(dev)->gen >= 9)
5013                 skylake_pfit_enable(intel_crtc);
5014         else
5015                 ironlake_pfit_enable(intel_crtc);
5016
5017         /*
5018          * On ILK+ LUT must be loaded before the pipe is running but with
5019          * clocks enabled
5020          */
5021         intel_crtc_load_lut(crtc);
5022
5023         intel_ddi_set_pipe_settings(crtc);
5024         if (!intel_crtc->config->has_dsi_encoder)
5025                 intel_ddi_enable_transcoder_func(crtc);
5026
5027         intel_update_watermarks(crtc);
5028         intel_enable_pipe(intel_crtc);
5029
5030         if (intel_crtc->config->has_pch_encoder)
5031                 lpt_pch_enable(crtc);
5032
5033         if (intel_crtc->config->dp_encoder_is_mst)
5034                 intel_ddi_set_vc_payload_alloc(crtc, true);
5035
5036         assert_vblank_disabled(crtc);
5037         drm_crtc_vblank_on(crtc);
5038
5039         for_each_encoder_on_crtc(dev, crtc, encoder) {
5040                 encoder->enable(encoder);
5041                 intel_opregion_notify_encoder(encoder, true);
5042         }
5043
5044         if (intel_crtc->config->has_pch_encoder) {
5045                 intel_wait_for_vblank(dev, pipe);
5046                 intel_wait_for_vblank(dev, pipe);
5047                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5048                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5049                                                       true);
5050         }
5051
5052         /* If we change the relative order between pipe/planes enabling, we need
5053          * to change the workaround. */
5054         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5055         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5056                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5057                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5058         }
5059 }
5060
5061 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5062 {
5063         struct drm_device *dev = crtc->base.dev;
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065         int pipe = crtc->pipe;
5066
5067         /* To avoid upsetting the power well on haswell only disable the pfit if
5068          * it's in use. The hw state code will make sure we get this right. */
5069         if (force || crtc->config->pch_pfit.enabled) {
5070                 I915_WRITE(PF_CTL(pipe), 0);
5071                 I915_WRITE(PF_WIN_POS(pipe), 0);
5072                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5073         }
5074 }
5075
5076 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->dev;
5079         struct drm_i915_private *dev_priv = dev->dev_private;
5080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5081         struct intel_encoder *encoder;
5082         int pipe = intel_crtc->pipe;
5083
5084         if (intel_crtc->config->has_pch_encoder)
5085                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5086
5087         for_each_encoder_on_crtc(dev, crtc, encoder)
5088                 encoder->disable(encoder);
5089
5090         drm_crtc_vblank_off(crtc);
5091         assert_vblank_disabled(crtc);
5092
5093         /*
5094          * Sometimes spurious CPU pipe underruns happen when the
5095          * pipe is already disabled, but FDI RX/TX is still enabled.
5096          * Happens at least with VGA+HDMI cloning. Suppress them.
5097          */
5098         if (intel_crtc->config->has_pch_encoder)
5099                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5100
5101         intel_disable_pipe(intel_crtc);
5102
5103         ironlake_pfit_disable(intel_crtc, false);
5104
5105         if (intel_crtc->config->has_pch_encoder) {
5106                 ironlake_fdi_disable(crtc);
5107                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5108         }
5109
5110         for_each_encoder_on_crtc(dev, crtc, encoder)
5111                 if (encoder->post_disable)
5112                         encoder->post_disable(encoder);
5113
5114         if (intel_crtc->config->has_pch_encoder) {
5115                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5116
5117                 if (HAS_PCH_CPT(dev)) {
5118                         i915_reg_t reg;
5119                         u32 temp;
5120
5121                         /* disable TRANS_DP_CTL */
5122                         reg = TRANS_DP_CTL(pipe);
5123                         temp = I915_READ(reg);
5124                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5125                                   TRANS_DP_PORT_SEL_MASK);
5126                         temp |= TRANS_DP_PORT_SEL_NONE;
5127                         I915_WRITE(reg, temp);
5128
5129                         /* disable DPLL_SEL */
5130                         temp = I915_READ(PCH_DPLL_SEL);
5131                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5132                         I915_WRITE(PCH_DPLL_SEL, temp);
5133                 }
5134
5135                 ironlake_fdi_pll_disable(intel_crtc);
5136         }
5137
5138         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5139 }
5140
5141 static void haswell_crtc_disable(struct drm_crtc *crtc)
5142 {
5143         struct drm_device *dev = crtc->dev;
5144         struct drm_i915_private *dev_priv = dev->dev_private;
5145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5146         struct intel_encoder *encoder;
5147         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5148
5149         if (intel_crtc->config->has_pch_encoder)
5150                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5151                                                       false);
5152
5153         for_each_encoder_on_crtc(dev, crtc, encoder) {
5154                 intel_opregion_notify_encoder(encoder, false);
5155                 encoder->disable(encoder);
5156         }
5157
5158         drm_crtc_vblank_off(crtc);
5159         assert_vblank_disabled(crtc);
5160
5161         intel_disable_pipe(intel_crtc);
5162
5163         if (intel_crtc->config->dp_encoder_is_mst)
5164                 intel_ddi_set_vc_payload_alloc(crtc, false);
5165
5166         if (!intel_crtc->config->has_dsi_encoder)
5167                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5168
5169         if (INTEL_INFO(dev)->gen >= 9)
5170                 skylake_scaler_disable(intel_crtc);
5171         else
5172                 ironlake_pfit_disable(intel_crtc, false);
5173
5174         if (!intel_crtc->config->has_dsi_encoder)
5175                 intel_ddi_disable_pipe_clock(intel_crtc);
5176
5177         for_each_encoder_on_crtc(dev, crtc, encoder)
5178                 if (encoder->post_disable)
5179                         encoder->post_disable(encoder);
5180
5181         if (intel_crtc->config->has_pch_encoder) {
5182                 lpt_disable_pch_transcoder(dev_priv);
5183                 lpt_disable_iclkip(dev_priv);
5184                 intel_ddi_fdi_disable(crtc);
5185
5186                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5187                                                       true);
5188         }
5189 }
5190
5191 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5192 {
5193         struct drm_device *dev = crtc->base.dev;
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195         struct intel_crtc_state *pipe_config = crtc->config;
5196
5197         if (!pipe_config->gmch_pfit.control)
5198                 return;
5199
5200         /*
5201          * The panel fitter should only be adjusted whilst the pipe is disabled,
5202          * according to register description and PRM.
5203          */
5204         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5205         assert_pipe_disabled(dev_priv, crtc->pipe);
5206
5207         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5208         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5209
5210         /* Border color in case we don't scale up to the full screen. Black by
5211          * default, change to something else for debugging. */
5212         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5213 }
5214
5215 static enum intel_display_power_domain port_to_power_domain(enum port port)
5216 {
5217         switch (port) {
5218         case PORT_A:
5219                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5220         case PORT_B:
5221                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5222         case PORT_C:
5223                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5224         case PORT_D:
5225                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5226         case PORT_E:
5227                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5228         default:
5229                 MISSING_CASE(port);
5230                 return POWER_DOMAIN_PORT_OTHER;
5231         }
5232 }
5233
5234 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5235 {
5236         switch (port) {
5237         case PORT_A:
5238                 return POWER_DOMAIN_AUX_A;
5239         case PORT_B:
5240                 return POWER_DOMAIN_AUX_B;
5241         case PORT_C:
5242                 return POWER_DOMAIN_AUX_C;
5243         case PORT_D:
5244                 return POWER_DOMAIN_AUX_D;
5245         case PORT_E:
5246                 /* FIXME: Check VBT for actual wiring of PORT E */
5247                 return POWER_DOMAIN_AUX_D;
5248         default:
5249                 MISSING_CASE(port);
5250                 return POWER_DOMAIN_AUX_A;
5251         }
5252 }
5253
5254 enum intel_display_power_domain
5255 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5256 {
5257         struct drm_device *dev = intel_encoder->base.dev;
5258         struct intel_digital_port *intel_dig_port;
5259
5260         switch (intel_encoder->type) {
5261         case INTEL_OUTPUT_UNKNOWN:
5262                 /* Only DDI platforms should ever use this output type */
5263                 WARN_ON_ONCE(!HAS_DDI(dev));
5264         case INTEL_OUTPUT_DISPLAYPORT:
5265         case INTEL_OUTPUT_HDMI:
5266         case INTEL_OUTPUT_EDP:
5267                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5268                 return port_to_power_domain(intel_dig_port->port);
5269         case INTEL_OUTPUT_DP_MST:
5270                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5271                 return port_to_power_domain(intel_dig_port->port);
5272         case INTEL_OUTPUT_ANALOG:
5273                 return POWER_DOMAIN_PORT_CRT;
5274         case INTEL_OUTPUT_DSI:
5275                 return POWER_DOMAIN_PORT_DSI;
5276         default:
5277                 return POWER_DOMAIN_PORT_OTHER;
5278         }
5279 }
5280
5281 enum intel_display_power_domain
5282 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5283 {
5284         struct drm_device *dev = intel_encoder->base.dev;
5285         struct intel_digital_port *intel_dig_port;
5286
5287         switch (intel_encoder->type) {
5288         case INTEL_OUTPUT_UNKNOWN:
5289         case INTEL_OUTPUT_HDMI:
5290                 /*
5291                  * Only DDI platforms should ever use these output types.
5292                  * We can get here after the HDMI detect code has already set
5293                  * the type of the shared encoder. Since we can't be sure
5294                  * what's the status of the given connectors, play safe and
5295                  * run the DP detection too.
5296                  */
5297                 WARN_ON_ONCE(!HAS_DDI(dev));
5298         case INTEL_OUTPUT_DISPLAYPORT:
5299         case INTEL_OUTPUT_EDP:
5300                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5301                 return port_to_aux_power_domain(intel_dig_port->port);
5302         case INTEL_OUTPUT_DP_MST:
5303                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5304                 return port_to_aux_power_domain(intel_dig_port->port);
5305         default:
5306                 MISSING_CASE(intel_encoder->type);
5307                 return POWER_DOMAIN_AUX_A;
5308         }
5309 }
5310
5311 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5312                                             struct intel_crtc_state *crtc_state)
5313 {
5314         struct drm_device *dev = crtc->dev;
5315         struct drm_encoder *encoder;
5316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317         enum pipe pipe = intel_crtc->pipe;
5318         unsigned long mask;
5319         enum transcoder transcoder = crtc_state->cpu_transcoder;
5320
5321         if (!crtc_state->base.active)
5322                 return 0;
5323
5324         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5325         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5326         if (crtc_state->pch_pfit.enabled ||
5327             crtc_state->pch_pfit.force_thru)
5328                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5329
5330         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5331                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5332
5333                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5334         }
5335
5336         return mask;
5337 }
5338
5339 static unsigned long
5340 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5341                                struct intel_crtc_state *crtc_state)
5342 {
5343         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5345         enum intel_display_power_domain domain;
5346         unsigned long domains, new_domains, old_domains;
5347
5348         old_domains = intel_crtc->enabled_power_domains;
5349         intel_crtc->enabled_power_domains = new_domains =
5350                 get_crtc_power_domains(crtc, crtc_state);
5351
5352         domains = new_domains & ~old_domains;
5353
5354         for_each_power_domain(domain, domains)
5355                 intel_display_power_get(dev_priv, domain);
5356
5357         return old_domains & ~new_domains;
5358 }
5359
5360 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5361                                       unsigned long domains)
5362 {
5363         enum intel_display_power_domain domain;
5364
5365         for_each_power_domain(domain, domains)
5366                 intel_display_power_put(dev_priv, domain);
5367 }
5368
5369 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5370 {
5371         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5372
5373         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5374             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5375                 return max_cdclk_freq;
5376         else if (IS_CHERRYVIEW(dev_priv))
5377                 return max_cdclk_freq*95/100;
5378         else if (INTEL_INFO(dev_priv)->gen < 4)
5379                 return 2*max_cdclk_freq*90/100;
5380         else
5381                 return max_cdclk_freq*90/100;
5382 }
5383
5384 static void intel_update_max_cdclk(struct drm_device *dev)
5385 {
5386         struct drm_i915_private *dev_priv = dev->dev_private;
5387
5388         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5389                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5390
5391                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5392                         dev_priv->max_cdclk_freq = 675000;
5393                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5394                         dev_priv->max_cdclk_freq = 540000;
5395                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5396                         dev_priv->max_cdclk_freq = 450000;
5397                 else
5398                         dev_priv->max_cdclk_freq = 337500;
5399         } else if (IS_BROADWELL(dev))  {
5400                 /*
5401                  * FIXME with extra cooling we can allow
5402                  * 540 MHz for ULX and 675 Mhz for ULT.
5403                  * How can we know if extra cooling is
5404                  * available? PCI ID, VTB, something else?
5405                  */
5406                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5407                         dev_priv->max_cdclk_freq = 450000;
5408                 else if (IS_BDW_ULX(dev))
5409                         dev_priv->max_cdclk_freq = 450000;
5410                 else if (IS_BDW_ULT(dev))
5411                         dev_priv->max_cdclk_freq = 540000;
5412                 else
5413                         dev_priv->max_cdclk_freq = 675000;
5414         } else if (IS_CHERRYVIEW(dev)) {
5415                 dev_priv->max_cdclk_freq = 320000;
5416         } else if (IS_VALLEYVIEW(dev)) {
5417                 dev_priv->max_cdclk_freq = 400000;
5418         } else {
5419                 /* otherwise assume cdclk is fixed */
5420                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5421         }
5422
5423         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5424
5425         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5426                          dev_priv->max_cdclk_freq);
5427
5428         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5429                          dev_priv->max_dotclk_freq);
5430 }
5431
5432 static void intel_update_cdclk(struct drm_device *dev)
5433 {
5434         struct drm_i915_private *dev_priv = dev->dev_private;
5435
5436         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5437         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5438                          dev_priv->cdclk_freq);
5439
5440         /*
5441          * Program the gmbus_freq based on the cdclk frequency.
5442          * BSpec erroneously claims we should aim for 4MHz, but
5443          * in fact 1MHz is the correct frequency.
5444          */
5445         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5446                 /*
5447                  * Program the gmbus_freq based on the cdclk frequency.
5448                  * BSpec erroneously claims we should aim for 4MHz, but
5449                  * in fact 1MHz is the correct frequency.
5450                  */
5451                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5452         }
5453
5454         if (dev_priv->max_cdclk_freq == 0)
5455                 intel_update_max_cdclk(dev);
5456 }
5457
5458 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5459 {
5460         struct drm_i915_private *dev_priv = dev->dev_private;
5461         uint32_t divider;
5462         uint32_t ratio;
5463         uint32_t current_freq;
5464         int ret;
5465
5466         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5467         switch (frequency) {
5468         case 144000:
5469                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5470                 ratio = BXT_DE_PLL_RATIO(60);
5471                 break;
5472         case 288000:
5473                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5474                 ratio = BXT_DE_PLL_RATIO(60);
5475                 break;
5476         case 384000:
5477                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5478                 ratio = BXT_DE_PLL_RATIO(60);
5479                 break;
5480         case 576000:
5481                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5482                 ratio = BXT_DE_PLL_RATIO(60);
5483                 break;
5484         case 624000:
5485                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5486                 ratio = BXT_DE_PLL_RATIO(65);
5487                 break;
5488         case 19200:
5489                 /*
5490                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5491                  * to suppress GCC warning.
5492                  */
5493                 ratio = 0;
5494                 divider = 0;
5495                 break;
5496         default:
5497                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5498
5499                 return;
5500         }
5501
5502         mutex_lock(&dev_priv->rps.hw_lock);
5503         /* Inform power controller of upcoming frequency change */
5504         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5505                                       0x80000000);
5506         mutex_unlock(&dev_priv->rps.hw_lock);
5507
5508         if (ret) {
5509                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5510                           ret, frequency);
5511                 return;
5512         }
5513
5514         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5515         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5516         current_freq = current_freq * 500 + 1000;
5517
5518         /*
5519          * DE PLL has to be disabled when
5520          * - setting to 19.2MHz (bypass, PLL isn't used)
5521          * - before setting to 624MHz (PLL needs toggling)
5522          * - before setting to any frequency from 624MHz (PLL needs toggling)
5523          */
5524         if (frequency == 19200 || frequency == 624000 ||
5525             current_freq == 624000) {
5526                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5527                 /* Timeout 200us */
5528                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5529                              1))
5530                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5531         }
5532
5533         if (frequency != 19200) {
5534                 uint32_t val;
5535
5536                 val = I915_READ(BXT_DE_PLL_CTL);
5537                 val &= ~BXT_DE_PLL_RATIO_MASK;
5538                 val |= ratio;
5539                 I915_WRITE(BXT_DE_PLL_CTL, val);
5540
5541                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5542                 /* Timeout 200us */
5543                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5544                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5545
5546                 val = I915_READ(CDCLK_CTL);
5547                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5548                 val |= divider;
5549                 /*
5550                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5551                  * enable otherwise.
5552                  */
5553                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5554                 if (frequency >= 500000)
5555                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5556
5557                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5558                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5559                 val |= (frequency - 1000) / 500;
5560                 I915_WRITE(CDCLK_CTL, val);
5561         }
5562
5563         mutex_lock(&dev_priv->rps.hw_lock);
5564         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5565                                       DIV_ROUND_UP(frequency, 25000));
5566         mutex_unlock(&dev_priv->rps.hw_lock);
5567
5568         if (ret) {
5569                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5570                           ret, frequency);
5571                 return;
5572         }
5573
5574         intel_update_cdclk(dev);
5575 }
5576
5577 void broxton_init_cdclk(struct drm_device *dev)
5578 {
5579         struct drm_i915_private *dev_priv = dev->dev_private;
5580         uint32_t val;
5581
5582         /*
5583          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5584          * or else the reset will hang because there is no PCH to respond.
5585          * Move the handshake programming to initialization sequence.
5586          * Previously was left up to BIOS.
5587          */
5588         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5589         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5590         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5591
5592         /* Enable PG1 for cdclk */
5593         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5594
5595         /* check if cd clock is enabled */
5596         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5597                 DRM_DEBUG_KMS("Display already initialized\n");
5598                 return;
5599         }
5600
5601         /*
5602          * FIXME:
5603          * - The initial CDCLK needs to be read from VBT.
5604          *   Need to make this change after VBT has changes for BXT.
5605          * - check if setting the max (or any) cdclk freq is really necessary
5606          *   here, it belongs to modeset time
5607          */
5608         broxton_set_cdclk(dev, 624000);
5609
5610         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5611         POSTING_READ(DBUF_CTL);
5612
5613         udelay(10);
5614
5615         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5616                 DRM_ERROR("DBuf power enable timeout!\n");
5617 }
5618
5619 void broxton_uninit_cdclk(struct drm_device *dev)
5620 {
5621         struct drm_i915_private *dev_priv = dev->dev_private;
5622
5623         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5624         POSTING_READ(DBUF_CTL);
5625
5626         udelay(10);
5627
5628         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5629                 DRM_ERROR("DBuf power disable timeout!\n");
5630
5631         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5632         broxton_set_cdclk(dev, 19200);
5633
5634         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5635 }
5636
5637 static const struct skl_cdclk_entry {
5638         unsigned int freq;
5639         unsigned int vco;
5640 } skl_cdclk_frequencies[] = {
5641         { .freq = 308570, .vco = 8640 },
5642         { .freq = 337500, .vco = 8100 },
5643         { .freq = 432000, .vco = 8640 },
5644         { .freq = 450000, .vco = 8100 },
5645         { .freq = 540000, .vco = 8100 },
5646         { .freq = 617140, .vco = 8640 },
5647         { .freq = 675000, .vco = 8100 },
5648 };
5649
5650 static unsigned int skl_cdclk_decimal(unsigned int freq)
5651 {
5652         return (freq - 1000) / 500;
5653 }
5654
5655 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5656 {
5657         unsigned int i;
5658
5659         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5660                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5661
5662                 if (e->freq == freq)
5663                         return e->vco;
5664         }
5665
5666         return 8100;
5667 }
5668
5669 static void
5670 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5671 {
5672         unsigned int min_freq;
5673         u32 val;
5674
5675         /* select the minimum CDCLK before enabling DPLL 0 */
5676         val = I915_READ(CDCLK_CTL);
5677         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5678         val |= CDCLK_FREQ_337_308;
5679
5680         if (required_vco == 8640)
5681                 min_freq = 308570;
5682         else
5683                 min_freq = 337500;
5684
5685         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5686
5687         I915_WRITE(CDCLK_CTL, val);
5688         POSTING_READ(CDCLK_CTL);
5689
5690         /*
5691          * We always enable DPLL0 with the lowest link rate possible, but still
5692          * taking into account the VCO required to operate the eDP panel at the
5693          * desired frequency. The usual DP link rates operate with a VCO of
5694          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5695          * The modeset code is responsible for the selection of the exact link
5696          * rate later on, with the constraint of choosing a frequency that
5697          * works with required_vco.
5698          */
5699         val = I915_READ(DPLL_CTRL1);
5700
5701         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5702                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5703         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5704         if (required_vco == 8640)
5705                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5706                                             SKL_DPLL0);
5707         else
5708                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5709                                             SKL_DPLL0);
5710
5711         I915_WRITE(DPLL_CTRL1, val);
5712         POSTING_READ(DPLL_CTRL1);
5713
5714         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5715
5716         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5717                 DRM_ERROR("DPLL0 not locked\n");
5718 }
5719
5720 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5721 {
5722         int ret;
5723         u32 val;
5724
5725         /* inform PCU we want to change CDCLK */
5726         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5727         mutex_lock(&dev_priv->rps.hw_lock);
5728         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5729         mutex_unlock(&dev_priv->rps.hw_lock);
5730
5731         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5732 }
5733
5734 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5735 {
5736         unsigned int i;
5737
5738         for (i = 0; i < 15; i++) {
5739                 if (skl_cdclk_pcu_ready(dev_priv))
5740                         return true;
5741                 udelay(10);
5742         }
5743
5744         return false;
5745 }
5746
5747 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5748 {
5749         struct drm_device *dev = dev_priv->dev;
5750         u32 freq_select, pcu_ack;
5751
5752         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5753
5754         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5755                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5756                 return;
5757         }
5758
5759         /* set CDCLK_CTL */
5760         switch(freq) {
5761         case 450000:
5762         case 432000:
5763                 freq_select = CDCLK_FREQ_450_432;
5764                 pcu_ack = 1;
5765                 break;
5766         case 540000:
5767                 freq_select = CDCLK_FREQ_540;
5768                 pcu_ack = 2;
5769                 break;
5770         case 308570:
5771         case 337500:
5772         default:
5773                 freq_select = CDCLK_FREQ_337_308;
5774                 pcu_ack = 0;
5775                 break;
5776         case 617140:
5777         case 675000:
5778                 freq_select = CDCLK_FREQ_675_617;
5779                 pcu_ack = 3;
5780                 break;
5781         }
5782
5783         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5784         POSTING_READ(CDCLK_CTL);
5785
5786         /* inform PCU of the change */
5787         mutex_lock(&dev_priv->rps.hw_lock);
5788         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5789         mutex_unlock(&dev_priv->rps.hw_lock);
5790
5791         intel_update_cdclk(dev);
5792 }
5793
5794 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5795 {
5796         /* disable DBUF power */
5797         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5798         POSTING_READ(DBUF_CTL);
5799
5800         udelay(10);
5801
5802         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5803                 DRM_ERROR("DBuf power disable timeout\n");
5804
5805         /* disable DPLL0 */
5806         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5807         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5808                 DRM_ERROR("Couldn't disable DPLL0\n");
5809 }
5810
5811 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5812 {
5813         unsigned int required_vco;
5814
5815         /* DPLL0 not enabled (happens on early BIOS versions) */
5816         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5817                 /* enable DPLL0 */
5818                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5819                 skl_dpll0_enable(dev_priv, required_vco);
5820         }
5821
5822         /* set CDCLK to the frequency the BIOS chose */
5823         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5824
5825         /* enable DBUF power */
5826         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5827         POSTING_READ(DBUF_CTL);
5828
5829         udelay(10);
5830
5831         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5832                 DRM_ERROR("DBuf power enable timeout\n");
5833 }
5834
5835 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5836 {
5837         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5838         uint32_t cdctl = I915_READ(CDCLK_CTL);
5839         int freq = dev_priv->skl_boot_cdclk;
5840
5841         /*
5842          * check if the pre-os intialized the display
5843          * There is SWF18 scratchpad register defined which is set by the
5844          * pre-os which can be used by the OS drivers to check the status
5845          */
5846         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5847                 goto sanitize;
5848
5849         /* Is PLL enabled and locked ? */
5850         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5851                 goto sanitize;
5852
5853         /* DPLL okay; verify the cdclock
5854          *
5855          * Noticed in some instances that the freq selection is correct but
5856          * decimal part is programmed wrong from BIOS where pre-os does not
5857          * enable display. Verify the same as well.
5858          */
5859         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5860                 /* All well; nothing to sanitize */
5861                 return false;
5862 sanitize:
5863         /*
5864          * As of now initialize with max cdclk till
5865          * we get dynamic cdclk support
5866          * */
5867         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5868         skl_init_cdclk(dev_priv);
5869
5870         /* we did have to sanitize */
5871         return true;
5872 }
5873
5874 /* Adjust CDclk dividers to allow high res or save power if possible */
5875 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5876 {
5877         struct drm_i915_private *dev_priv = dev->dev_private;
5878         u32 val, cmd;
5879
5880         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5881                                         != dev_priv->cdclk_freq);
5882
5883         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5884                 cmd = 2;
5885         else if (cdclk == 266667)
5886                 cmd = 1;
5887         else
5888                 cmd = 0;
5889
5890         mutex_lock(&dev_priv->rps.hw_lock);
5891         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5892         val &= ~DSPFREQGUAR_MASK;
5893         val |= (cmd << DSPFREQGUAR_SHIFT);
5894         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5895         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5896                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5897                      50)) {
5898                 DRM_ERROR("timed out waiting for CDclk change\n");
5899         }
5900         mutex_unlock(&dev_priv->rps.hw_lock);
5901
5902         mutex_lock(&dev_priv->sb_lock);
5903
5904         if (cdclk == 400000) {
5905                 u32 divider;
5906
5907                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5908
5909                 /* adjust cdclk divider */
5910                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5911                 val &= ~CCK_FREQUENCY_VALUES;
5912                 val |= divider;
5913                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5914
5915                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5916                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5917                              50))
5918                         DRM_ERROR("timed out waiting for CDclk change\n");
5919         }
5920
5921         /* adjust self-refresh exit latency value */
5922         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5923         val &= ~0x7f;
5924
5925         /*
5926          * For high bandwidth configs, we set a higher latency in the bunit
5927          * so that the core display fetch happens in time to avoid underruns.
5928          */
5929         if (cdclk == 400000)
5930                 val |= 4500 / 250; /* 4.5 usec */
5931         else
5932                 val |= 3000 / 250; /* 3.0 usec */
5933         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5934
5935         mutex_unlock(&dev_priv->sb_lock);
5936
5937         intel_update_cdclk(dev);
5938 }
5939
5940 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5941 {
5942         struct drm_i915_private *dev_priv = dev->dev_private;
5943         u32 val, cmd;
5944
5945         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5946                                                 != dev_priv->cdclk_freq);
5947
5948         switch (cdclk) {
5949         case 333333:
5950         case 320000:
5951         case 266667:
5952         case 200000:
5953                 break;
5954         default:
5955                 MISSING_CASE(cdclk);
5956                 return;
5957         }
5958
5959         /*
5960          * Specs are full of misinformation, but testing on actual
5961          * hardware has shown that we just need to write the desired
5962          * CCK divider into the Punit register.
5963          */
5964         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5965
5966         mutex_lock(&dev_priv->rps.hw_lock);
5967         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5968         val &= ~DSPFREQGUAR_MASK_CHV;
5969         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5970         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5971         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5972                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5973                      50)) {
5974                 DRM_ERROR("timed out waiting for CDclk change\n");
5975         }
5976         mutex_unlock(&dev_priv->rps.hw_lock);
5977
5978         intel_update_cdclk(dev);
5979 }
5980
5981 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5982                                  int max_pixclk)
5983 {
5984         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5985         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5986
5987         /*
5988          * Really only a few cases to deal with, as only 4 CDclks are supported:
5989          *   200MHz
5990          *   267MHz
5991          *   320/333MHz (depends on HPLL freq)
5992          *   400MHz (VLV only)
5993          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5994          * of the lower bin and adjust if needed.
5995          *
5996          * We seem to get an unstable or solid color picture at 200MHz.
5997          * Not sure what's wrong. For now use 200MHz only when all pipes
5998          * are off.
5999          */
6000         if (!IS_CHERRYVIEW(dev_priv) &&
6001             max_pixclk > freq_320*limit/100)
6002                 return 400000;
6003         else if (max_pixclk > 266667*limit/100)
6004                 return freq_320;
6005         else if (max_pixclk > 0)
6006                 return 266667;
6007         else
6008                 return 200000;
6009 }
6010
6011 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6012                               int max_pixclk)
6013 {
6014         /*
6015          * FIXME:
6016          * - remove the guardband, it's not needed on BXT
6017          * - set 19.2MHz bypass frequency if there are no active pipes
6018          */
6019         if (max_pixclk > 576000*9/10)
6020                 return 624000;
6021         else if (max_pixclk > 384000*9/10)
6022                 return 576000;
6023         else if (max_pixclk > 288000*9/10)
6024                 return 384000;
6025         else if (max_pixclk > 144000*9/10)
6026                 return 288000;
6027         else
6028                 return 144000;
6029 }
6030
6031 /* Compute the max pixel clock for new configuration. */
6032 static int intel_mode_max_pixclk(struct drm_device *dev,
6033                                  struct drm_atomic_state *state)
6034 {
6035         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037         struct drm_crtc *crtc;
6038         struct drm_crtc_state *crtc_state;
6039         unsigned max_pixclk = 0, i;
6040         enum pipe pipe;
6041
6042         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6043                sizeof(intel_state->min_pixclk));
6044
6045         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6046                 int pixclk = 0;
6047
6048                 if (crtc_state->enable)
6049                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6050
6051                 intel_state->min_pixclk[i] = pixclk;
6052         }
6053
6054         for_each_pipe(dev_priv, pipe)
6055                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6056
6057         return max_pixclk;
6058 }
6059
6060 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6061 {
6062         struct drm_device *dev = state->dev;
6063         struct drm_i915_private *dev_priv = dev->dev_private;
6064         int max_pixclk = intel_mode_max_pixclk(dev, state);
6065         struct intel_atomic_state *intel_state =
6066                 to_intel_atomic_state(state);
6067
6068         if (max_pixclk < 0)
6069                 return max_pixclk;
6070
6071         intel_state->cdclk = intel_state->dev_cdclk =
6072                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6073
6074         if (!intel_state->active_crtcs)
6075                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6076
6077         return 0;
6078 }
6079
6080 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6081 {
6082         struct drm_device *dev = state->dev;
6083         struct drm_i915_private *dev_priv = dev->dev_private;
6084         int max_pixclk = intel_mode_max_pixclk(dev, state);
6085         struct intel_atomic_state *intel_state =
6086                 to_intel_atomic_state(state);
6087
6088         if (max_pixclk < 0)
6089                 return max_pixclk;
6090
6091         intel_state->cdclk = intel_state->dev_cdclk =
6092                 broxton_calc_cdclk(dev_priv, max_pixclk);
6093
6094         if (!intel_state->active_crtcs)
6095                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6096
6097         return 0;
6098 }
6099
6100 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6101 {
6102         unsigned int credits, default_credits;
6103
6104         if (IS_CHERRYVIEW(dev_priv))
6105                 default_credits = PFI_CREDIT(12);
6106         else
6107                 default_credits = PFI_CREDIT(8);
6108
6109         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6110                 /* CHV suggested value is 31 or 63 */
6111                 if (IS_CHERRYVIEW(dev_priv))
6112                         credits = PFI_CREDIT_63;
6113                 else
6114                         credits = PFI_CREDIT(15);
6115         } else {
6116                 credits = default_credits;
6117         }
6118
6119         /*
6120          * WA - write default credits before re-programming
6121          * FIXME: should we also set the resend bit here?
6122          */
6123         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6124                    default_credits);
6125
6126         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6127                    credits | PFI_CREDIT_RESEND);
6128
6129         /*
6130          * FIXME is this guaranteed to clear
6131          * immediately or should we poll for it?
6132          */
6133         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6134 }
6135
6136 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6137 {
6138         struct drm_device *dev = old_state->dev;
6139         struct drm_i915_private *dev_priv = dev->dev_private;
6140         struct intel_atomic_state *old_intel_state =
6141                 to_intel_atomic_state(old_state);
6142         unsigned req_cdclk = old_intel_state->dev_cdclk;
6143
6144         /*
6145          * FIXME: We can end up here with all power domains off, yet
6146          * with a CDCLK frequency other than the minimum. To account
6147          * for this take the PIPE-A power domain, which covers the HW
6148          * blocks needed for the following programming. This can be
6149          * removed once it's guaranteed that we get here either with
6150          * the minimum CDCLK set, or the required power domains
6151          * enabled.
6152          */
6153         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6154
6155         if (IS_CHERRYVIEW(dev))
6156                 cherryview_set_cdclk(dev, req_cdclk);
6157         else
6158                 valleyview_set_cdclk(dev, req_cdclk);
6159
6160         vlv_program_pfi_credits(dev_priv);
6161
6162         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6163 }
6164
6165 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6166 {
6167         struct drm_device *dev = crtc->dev;
6168         struct drm_i915_private *dev_priv = to_i915(dev);
6169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6170         struct intel_encoder *encoder;
6171         int pipe = intel_crtc->pipe;
6172
6173         if (WARN_ON(intel_crtc->active))
6174                 return;
6175
6176         if (intel_crtc->config->has_dp_encoder)
6177                 intel_dp_set_m_n(intel_crtc, M1_N1);
6178
6179         intel_set_pipe_timings(intel_crtc);
6180
6181         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6182                 struct drm_i915_private *dev_priv = dev->dev_private;
6183
6184                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6185                 I915_WRITE(CHV_CANVAS(pipe), 0);
6186         }
6187
6188         i9xx_set_pipeconf(intel_crtc);
6189
6190         intel_crtc->active = true;
6191
6192         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6193
6194         for_each_encoder_on_crtc(dev, crtc, encoder)
6195                 if (encoder->pre_pll_enable)
6196                         encoder->pre_pll_enable(encoder);
6197
6198         if (!intel_crtc->config->has_dsi_encoder) {
6199                 if (IS_CHERRYVIEW(dev)) {
6200                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6201                         chv_enable_pll(intel_crtc, intel_crtc->config);
6202                 } else {
6203                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6204                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6205                 }
6206         }
6207
6208         for_each_encoder_on_crtc(dev, crtc, encoder)
6209                 if (encoder->pre_enable)
6210                         encoder->pre_enable(encoder);
6211
6212         i9xx_pfit_enable(intel_crtc);
6213
6214         intel_crtc_load_lut(crtc);
6215
6216         intel_enable_pipe(intel_crtc);
6217
6218         assert_vblank_disabled(crtc);
6219         drm_crtc_vblank_on(crtc);
6220
6221         for_each_encoder_on_crtc(dev, crtc, encoder)
6222                 encoder->enable(encoder);
6223 }
6224
6225 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6226 {
6227         struct drm_device *dev = crtc->base.dev;
6228         struct drm_i915_private *dev_priv = dev->dev_private;
6229
6230         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6231         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6232 }
6233
6234 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6235 {
6236         struct drm_device *dev = crtc->dev;
6237         struct drm_i915_private *dev_priv = to_i915(dev);
6238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6239         struct intel_encoder *encoder;
6240         int pipe = intel_crtc->pipe;
6241
6242         if (WARN_ON(intel_crtc->active))
6243                 return;
6244
6245         i9xx_set_pll_dividers(intel_crtc);
6246
6247         if (intel_crtc->config->has_dp_encoder)
6248                 intel_dp_set_m_n(intel_crtc, M1_N1);
6249
6250         intel_set_pipe_timings(intel_crtc);
6251
6252         i9xx_set_pipeconf(intel_crtc);
6253
6254         intel_crtc->active = true;
6255
6256         if (!IS_GEN2(dev))
6257                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6258
6259         for_each_encoder_on_crtc(dev, crtc, encoder)
6260                 if (encoder->pre_enable)
6261                         encoder->pre_enable(encoder);
6262
6263         i9xx_enable_pll(intel_crtc);
6264
6265         i9xx_pfit_enable(intel_crtc);
6266
6267         intel_crtc_load_lut(crtc);
6268
6269         intel_update_watermarks(crtc);
6270         intel_enable_pipe(intel_crtc);
6271
6272         assert_vblank_disabled(crtc);
6273         drm_crtc_vblank_on(crtc);
6274
6275         for_each_encoder_on_crtc(dev, crtc, encoder)
6276                 encoder->enable(encoder);
6277 }
6278
6279 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6280 {
6281         struct drm_device *dev = crtc->base.dev;
6282         struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284         if (!crtc->config->gmch_pfit.control)
6285                 return;
6286
6287         assert_pipe_disabled(dev_priv, crtc->pipe);
6288
6289         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6290                          I915_READ(PFIT_CONTROL));
6291         I915_WRITE(PFIT_CONTROL, 0);
6292 }
6293
6294 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6295 {
6296         struct drm_device *dev = crtc->dev;
6297         struct drm_i915_private *dev_priv = dev->dev_private;
6298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299         struct intel_encoder *encoder;
6300         int pipe = intel_crtc->pipe;
6301
6302         /*
6303          * On gen2 planes are double buffered but the pipe isn't, so we must
6304          * wait for planes to fully turn off before disabling the pipe.
6305          * We also need to wait on all gmch platforms because of the
6306          * self-refresh mode constraint explained above.
6307          */
6308         intel_wait_for_vblank(dev, pipe);
6309
6310         for_each_encoder_on_crtc(dev, crtc, encoder)
6311                 encoder->disable(encoder);
6312
6313         drm_crtc_vblank_off(crtc);
6314         assert_vblank_disabled(crtc);
6315
6316         intel_disable_pipe(intel_crtc);
6317
6318         i9xx_pfit_disable(intel_crtc);
6319
6320         for_each_encoder_on_crtc(dev, crtc, encoder)
6321                 if (encoder->post_disable)
6322                         encoder->post_disable(encoder);
6323
6324         if (!intel_crtc->config->has_dsi_encoder) {
6325                 if (IS_CHERRYVIEW(dev))
6326                         chv_disable_pll(dev_priv, pipe);
6327                 else if (IS_VALLEYVIEW(dev))
6328                         vlv_disable_pll(dev_priv, pipe);
6329                 else
6330                         i9xx_disable_pll(intel_crtc);
6331         }
6332
6333         for_each_encoder_on_crtc(dev, crtc, encoder)
6334                 if (encoder->post_pll_disable)
6335                         encoder->post_pll_disable(encoder);
6336
6337         if (!IS_GEN2(dev))
6338                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6339 }
6340
6341 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6342 {
6343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6344         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6345         enum intel_display_power_domain domain;
6346         unsigned long domains;
6347
6348         if (!intel_crtc->active)
6349                 return;
6350
6351         if (to_intel_plane_state(crtc->primary->state)->visible) {
6352                 WARN_ON(intel_crtc->unpin_work);
6353
6354                 intel_pre_disable_primary(crtc);
6355
6356                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6357                 to_intel_plane_state(crtc->primary->state)->visible = false;
6358         }
6359
6360         dev_priv->display.crtc_disable(crtc);
6361         intel_crtc->active = false;
6362         intel_fbc_disable(intel_crtc);
6363         intel_update_watermarks(crtc);
6364         intel_disable_shared_dpll(intel_crtc);
6365
6366         domains = intel_crtc->enabled_power_domains;
6367         for_each_power_domain(domain, domains)
6368                 intel_display_power_put(dev_priv, domain);
6369         intel_crtc->enabled_power_domains = 0;
6370
6371         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6372         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6373 }
6374
6375 /*
6376  * turn all crtc's off, but do not adjust state
6377  * This has to be paired with a call to intel_modeset_setup_hw_state.
6378  */
6379 int intel_display_suspend(struct drm_device *dev)
6380 {
6381         struct drm_i915_private *dev_priv = to_i915(dev);
6382         struct drm_atomic_state *state;
6383         int ret;
6384
6385         state = drm_atomic_helper_suspend(dev);
6386         ret = PTR_ERR_OR_ZERO(state);
6387         if (ret)
6388                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6389         else
6390                 dev_priv->modeset_restore_state = state;
6391         return ret;
6392 }
6393
6394 void intel_encoder_destroy(struct drm_encoder *encoder)
6395 {
6396         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6397
6398         drm_encoder_cleanup(encoder);
6399         kfree(intel_encoder);
6400 }
6401
6402 /* Cross check the actual hw state with our own modeset state tracking (and it's
6403  * internal consistency). */
6404 static void intel_connector_check_state(struct intel_connector *connector)
6405 {
6406         struct drm_crtc *crtc = connector->base.state->crtc;
6407
6408         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6409                       connector->base.base.id,
6410                       connector->base.name);
6411
6412         if (connector->get_hw_state(connector)) {
6413                 struct intel_encoder *encoder = connector->encoder;
6414                 struct drm_connector_state *conn_state = connector->base.state;
6415
6416                 I915_STATE_WARN(!crtc,
6417                          "connector enabled without attached crtc\n");
6418
6419                 if (!crtc)
6420                         return;
6421
6422                 I915_STATE_WARN(!crtc->state->active,
6423                       "connector is active, but attached crtc isn't\n");
6424
6425                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6426                         return;
6427
6428                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6429                         "atomic encoder doesn't match attached encoder\n");
6430
6431                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6432                         "attached encoder crtc differs from connector crtc\n");
6433         } else {
6434                 I915_STATE_WARN(crtc && crtc->state->active,
6435                         "attached crtc is active, but connector isn't\n");
6436                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6437                         "best encoder set without crtc!\n");
6438         }
6439 }
6440
6441 int intel_connector_init(struct intel_connector *connector)
6442 {
6443         drm_atomic_helper_connector_reset(&connector->base);
6444
6445         if (!connector->base.state)
6446                 return -ENOMEM;
6447
6448         return 0;
6449 }
6450
6451 struct intel_connector *intel_connector_alloc(void)
6452 {
6453         struct intel_connector *connector;
6454
6455         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6456         if (!connector)
6457                 return NULL;
6458
6459         if (intel_connector_init(connector) < 0) {
6460                 kfree(connector);
6461                 return NULL;
6462         }
6463
6464         return connector;
6465 }
6466
6467 /* Simple connector->get_hw_state implementation for encoders that support only
6468  * one connector and no cloning and hence the encoder state determines the state
6469  * of the connector. */
6470 bool intel_connector_get_hw_state(struct intel_connector *connector)
6471 {
6472         enum pipe pipe = 0;
6473         struct intel_encoder *encoder = connector->encoder;
6474
6475         return encoder->get_hw_state(encoder, &pipe);
6476 }
6477
6478 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6479 {
6480         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6481                 return crtc_state->fdi_lanes;
6482
6483         return 0;
6484 }
6485
6486 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6487                                      struct intel_crtc_state *pipe_config)
6488 {
6489         struct drm_atomic_state *state = pipe_config->base.state;
6490         struct intel_crtc *other_crtc;
6491         struct intel_crtc_state *other_crtc_state;
6492
6493         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6494                       pipe_name(pipe), pipe_config->fdi_lanes);
6495         if (pipe_config->fdi_lanes > 4) {
6496                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6497                               pipe_name(pipe), pipe_config->fdi_lanes);
6498                 return -EINVAL;
6499         }
6500
6501         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6502                 if (pipe_config->fdi_lanes > 2) {
6503                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6504                                       pipe_config->fdi_lanes);
6505                         return -EINVAL;
6506                 } else {
6507                         return 0;
6508                 }
6509         }
6510
6511         if (INTEL_INFO(dev)->num_pipes == 2)
6512                 return 0;
6513
6514         /* Ivybridge 3 pipe is really complicated */
6515         switch (pipe) {
6516         case PIPE_A:
6517                 return 0;
6518         case PIPE_B:
6519                 if (pipe_config->fdi_lanes <= 2)
6520                         return 0;
6521
6522                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6523                 other_crtc_state =
6524                         intel_atomic_get_crtc_state(state, other_crtc);
6525                 if (IS_ERR(other_crtc_state))
6526                         return PTR_ERR(other_crtc_state);
6527
6528                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6529                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6530                                       pipe_name(pipe), pipe_config->fdi_lanes);
6531                         return -EINVAL;
6532                 }
6533                 return 0;
6534         case PIPE_C:
6535                 if (pipe_config->fdi_lanes > 2) {
6536                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6537                                       pipe_name(pipe), pipe_config->fdi_lanes);
6538                         return -EINVAL;
6539                 }
6540
6541                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6542                 other_crtc_state =
6543                         intel_atomic_get_crtc_state(state, other_crtc);
6544                 if (IS_ERR(other_crtc_state))
6545                         return PTR_ERR(other_crtc_state);
6546
6547                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6548                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6549                         return -EINVAL;
6550                 }
6551                 return 0;
6552         default:
6553                 BUG();
6554         }
6555 }
6556
6557 #define RETRY 1
6558 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6559                                        struct intel_crtc_state *pipe_config)
6560 {
6561         struct drm_device *dev = intel_crtc->base.dev;
6562         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6563         int lane, link_bw, fdi_dotclock, ret;
6564         bool needs_recompute = false;
6565
6566 retry:
6567         /* FDI is a binary signal running at ~2.7GHz, encoding
6568          * each output octet as 10 bits. The actual frequency
6569          * is stored as a divider into a 100MHz clock, and the
6570          * mode pixel clock is stored in units of 1KHz.
6571          * Hence the bw of each lane in terms of the mode signal
6572          * is:
6573          */
6574         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6575
6576         fdi_dotclock = adjusted_mode->crtc_clock;
6577
6578         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6579                                            pipe_config->pipe_bpp);
6580
6581         pipe_config->fdi_lanes = lane;
6582
6583         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6584                                link_bw, &pipe_config->fdi_m_n);
6585
6586         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6587                                        intel_crtc->pipe, pipe_config);
6588         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6589                 pipe_config->pipe_bpp -= 2*3;
6590                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6591                               pipe_config->pipe_bpp);
6592                 needs_recompute = true;
6593                 pipe_config->bw_constrained = true;
6594
6595                 goto retry;
6596         }
6597
6598         if (needs_recompute)
6599                 return RETRY;
6600
6601         return ret;
6602 }
6603
6604 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6605                                      struct intel_crtc_state *pipe_config)
6606 {
6607         if (pipe_config->pipe_bpp > 24)
6608                 return false;
6609
6610         /* HSW can handle pixel rate up to cdclk? */
6611         if (IS_HASWELL(dev_priv->dev))
6612                 return true;
6613
6614         /*
6615          * We compare against max which means we must take
6616          * the increased cdclk requirement into account when
6617          * calculating the new cdclk.
6618          *
6619          * Should measure whether using a lower cdclk w/o IPS
6620          */
6621         return ilk_pipe_pixel_rate(pipe_config) <=
6622                 dev_priv->max_cdclk_freq * 95 / 100;
6623 }
6624
6625 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6626                                    struct intel_crtc_state *pipe_config)
6627 {
6628         struct drm_device *dev = crtc->base.dev;
6629         struct drm_i915_private *dev_priv = dev->dev_private;
6630
6631         pipe_config->ips_enabled = i915.enable_ips &&
6632                 hsw_crtc_supports_ips(crtc) &&
6633                 pipe_config_supports_ips(dev_priv, pipe_config);
6634 }
6635
6636 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6637 {
6638         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6639
6640         /* GDG double wide on either pipe, otherwise pipe A only */
6641         return INTEL_INFO(dev_priv)->gen < 4 &&
6642                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6643 }
6644
6645 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6646                                      struct intel_crtc_state *pipe_config)
6647 {
6648         struct drm_device *dev = crtc->base.dev;
6649         struct drm_i915_private *dev_priv = dev->dev_private;
6650         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6651
6652         /* FIXME should check pixel clock limits on all platforms */
6653         if (INTEL_INFO(dev)->gen < 4) {
6654                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6655
6656                 /*
6657                  * Enable double wide mode when the dot clock
6658                  * is > 90% of the (display) core speed.
6659                  */
6660                 if (intel_crtc_supports_double_wide(crtc) &&
6661                     adjusted_mode->crtc_clock > clock_limit) {
6662                         clock_limit *= 2;
6663                         pipe_config->double_wide = true;
6664                 }
6665
6666                 if (adjusted_mode->crtc_clock > clock_limit) {
6667                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6668                                       adjusted_mode->crtc_clock, clock_limit,
6669                                       yesno(pipe_config->double_wide));
6670                         return -EINVAL;
6671                 }
6672         }
6673
6674         /*
6675          * Pipe horizontal size must be even in:
6676          * - DVO ganged mode
6677          * - LVDS dual channel mode
6678          * - Double wide pipe
6679          */
6680         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6681              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6682                 pipe_config->pipe_src_w &= ~1;
6683
6684         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6685          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6686          */
6687         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6688                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6689                 return -EINVAL;
6690
6691         if (HAS_IPS(dev))
6692                 hsw_compute_ips_config(crtc, pipe_config);
6693
6694         if (pipe_config->has_pch_encoder)
6695                 return ironlake_fdi_compute_config(crtc, pipe_config);
6696
6697         return 0;
6698 }
6699
6700 static int skylake_get_display_clock_speed(struct drm_device *dev)
6701 {
6702         struct drm_i915_private *dev_priv = to_i915(dev);
6703         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6704         uint32_t cdctl = I915_READ(CDCLK_CTL);
6705         uint32_t linkrate;
6706
6707         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6708                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6709
6710         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6711                 return 540000;
6712
6713         linkrate = (I915_READ(DPLL_CTRL1) &
6714                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6715
6716         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6717             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6718                 /* vco 8640 */
6719                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6720                 case CDCLK_FREQ_450_432:
6721                         return 432000;
6722                 case CDCLK_FREQ_337_308:
6723                         return 308570;
6724                 case CDCLK_FREQ_675_617:
6725                         return 617140;
6726                 default:
6727                         WARN(1, "Unknown cd freq selection\n");
6728                 }
6729         } else {
6730                 /* vco 8100 */
6731                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6732                 case CDCLK_FREQ_450_432:
6733                         return 450000;
6734                 case CDCLK_FREQ_337_308:
6735                         return 337500;
6736                 case CDCLK_FREQ_675_617:
6737                         return 675000;
6738                 default:
6739                         WARN(1, "Unknown cd freq selection\n");
6740                 }
6741         }
6742
6743         /* error case, do as if DPLL0 isn't enabled */
6744         return 24000;
6745 }
6746
6747 static int broxton_get_display_clock_speed(struct drm_device *dev)
6748 {
6749         struct drm_i915_private *dev_priv = to_i915(dev);
6750         uint32_t cdctl = I915_READ(CDCLK_CTL);
6751         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6752         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6753         int cdclk;
6754
6755         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6756                 return 19200;
6757
6758         cdclk = 19200 * pll_ratio / 2;
6759
6760         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6761         case BXT_CDCLK_CD2X_DIV_SEL_1:
6762                 return cdclk;  /* 576MHz or 624MHz */
6763         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6764                 return cdclk * 2 / 3; /* 384MHz */
6765         case BXT_CDCLK_CD2X_DIV_SEL_2:
6766                 return cdclk / 2; /* 288MHz */
6767         case BXT_CDCLK_CD2X_DIV_SEL_4:
6768                 return cdclk / 4; /* 144MHz */
6769         }
6770
6771         /* error case, do as if DE PLL isn't enabled */
6772         return 19200;
6773 }
6774
6775 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6776 {
6777         struct drm_i915_private *dev_priv = dev->dev_private;
6778         uint32_t lcpll = I915_READ(LCPLL_CTL);
6779         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6780
6781         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6782                 return 800000;
6783         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6784                 return 450000;
6785         else if (freq == LCPLL_CLK_FREQ_450)
6786                 return 450000;
6787         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6788                 return 540000;
6789         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6790                 return 337500;
6791         else
6792                 return 675000;
6793 }
6794
6795 static int haswell_get_display_clock_speed(struct drm_device *dev)
6796 {
6797         struct drm_i915_private *dev_priv = dev->dev_private;
6798         uint32_t lcpll = I915_READ(LCPLL_CTL);
6799         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6800
6801         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6802                 return 800000;
6803         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6804                 return 450000;
6805         else if (freq == LCPLL_CLK_FREQ_450)
6806                 return 450000;
6807         else if (IS_HSW_ULT(dev))
6808                 return 337500;
6809         else
6810                 return 540000;
6811 }
6812
6813 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6814 {
6815         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6816                                       CCK_DISPLAY_CLOCK_CONTROL);
6817 }
6818
6819 static int ilk_get_display_clock_speed(struct drm_device *dev)
6820 {
6821         return 450000;
6822 }
6823
6824 static int i945_get_display_clock_speed(struct drm_device *dev)
6825 {
6826         return 400000;
6827 }
6828
6829 static int i915_get_display_clock_speed(struct drm_device *dev)
6830 {
6831         return 333333;
6832 }
6833
6834 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6835 {
6836         return 200000;
6837 }
6838
6839 static int pnv_get_display_clock_speed(struct drm_device *dev)
6840 {
6841         u16 gcfgc = 0;
6842
6843         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6844
6845         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6846         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6847                 return 266667;
6848         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6849                 return 333333;
6850         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6851                 return 444444;
6852         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6853                 return 200000;
6854         default:
6855                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6856         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6857                 return 133333;
6858         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6859                 return 166667;
6860         }
6861 }
6862
6863 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6864 {
6865         u16 gcfgc = 0;
6866
6867         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6868
6869         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6870                 return 133333;
6871         else {
6872                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6873                 case GC_DISPLAY_CLOCK_333_MHZ:
6874                         return 333333;
6875                 default:
6876                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6877                         return 190000;
6878                 }
6879         }
6880 }
6881
6882 static int i865_get_display_clock_speed(struct drm_device *dev)
6883 {
6884         return 266667;
6885 }
6886
6887 static int i85x_get_display_clock_speed(struct drm_device *dev)
6888 {
6889         u16 hpllcc = 0;
6890
6891         /*
6892          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6893          * encoding is different :(
6894          * FIXME is this the right way to detect 852GM/852GMV?
6895          */
6896         if (dev->pdev->revision == 0x1)
6897                 return 133333;
6898
6899         pci_bus_read_config_word(dev->pdev->bus,
6900                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6901
6902         /* Assume that the hardware is in the high speed state.  This
6903          * should be the default.
6904          */
6905         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6906         case GC_CLOCK_133_200:
6907         case GC_CLOCK_133_200_2:
6908         case GC_CLOCK_100_200:
6909                 return 200000;
6910         case GC_CLOCK_166_250:
6911                 return 250000;
6912         case GC_CLOCK_100_133:
6913                 return 133333;
6914         case GC_CLOCK_133_266:
6915         case GC_CLOCK_133_266_2:
6916         case GC_CLOCK_166_266:
6917                 return 266667;
6918         }
6919
6920         /* Shouldn't happen */
6921         return 0;
6922 }
6923
6924 static int i830_get_display_clock_speed(struct drm_device *dev)
6925 {
6926         return 133333;
6927 }
6928
6929 static unsigned int intel_hpll_vco(struct drm_device *dev)
6930 {
6931         struct drm_i915_private *dev_priv = dev->dev_private;
6932         static const unsigned int blb_vco[8] = {
6933                 [0] = 3200000,
6934                 [1] = 4000000,
6935                 [2] = 5333333,
6936                 [3] = 4800000,
6937                 [4] = 6400000,
6938         };
6939         static const unsigned int pnv_vco[8] = {
6940                 [0] = 3200000,
6941                 [1] = 4000000,
6942                 [2] = 5333333,
6943                 [3] = 4800000,
6944                 [4] = 2666667,
6945         };
6946         static const unsigned int cl_vco[8] = {
6947                 [0] = 3200000,
6948                 [1] = 4000000,
6949                 [2] = 5333333,
6950                 [3] = 6400000,
6951                 [4] = 3333333,
6952                 [5] = 3566667,
6953                 [6] = 4266667,
6954         };
6955         static const unsigned int elk_vco[8] = {
6956                 [0] = 3200000,
6957                 [1] = 4000000,
6958                 [2] = 5333333,
6959                 [3] = 4800000,
6960         };
6961         static const unsigned int ctg_vco[8] = {
6962                 [0] = 3200000,
6963                 [1] = 4000000,
6964                 [2] = 5333333,
6965                 [3] = 6400000,
6966                 [4] = 2666667,
6967                 [5] = 4266667,
6968         };
6969         const unsigned int *vco_table;
6970         unsigned int vco;
6971         uint8_t tmp = 0;
6972
6973         /* FIXME other chipsets? */
6974         if (IS_GM45(dev))
6975                 vco_table = ctg_vco;
6976         else if (IS_G4X(dev))
6977                 vco_table = elk_vco;
6978         else if (IS_CRESTLINE(dev))
6979                 vco_table = cl_vco;
6980         else if (IS_PINEVIEW(dev))
6981                 vco_table = pnv_vco;
6982         else if (IS_G33(dev))
6983                 vco_table = blb_vco;
6984         else
6985                 return 0;
6986
6987         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6988
6989         vco = vco_table[tmp & 0x7];
6990         if (vco == 0)
6991                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6992         else
6993                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6994
6995         return vco;
6996 }
6997
6998 static int gm45_get_display_clock_speed(struct drm_device *dev)
6999 {
7000         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7001         uint16_t tmp = 0;
7002
7003         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7004
7005         cdclk_sel = (tmp >> 12) & 0x1;
7006
7007         switch (vco) {
7008         case 2666667:
7009         case 4000000:
7010         case 5333333:
7011                 return cdclk_sel ? 333333 : 222222;
7012         case 3200000:
7013                 return cdclk_sel ? 320000 : 228571;
7014         default:
7015                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7016                 return 222222;
7017         }
7018 }
7019
7020 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7021 {
7022         static const uint8_t div_3200[] = { 16, 10,  8 };
7023         static const uint8_t div_4000[] = { 20, 12, 10 };
7024         static const uint8_t div_5333[] = { 24, 16, 14 };
7025         const uint8_t *div_table;
7026         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7027         uint16_t tmp = 0;
7028
7029         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7030
7031         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7032
7033         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7034                 goto fail;
7035
7036         switch (vco) {
7037         case 3200000:
7038                 div_table = div_3200;
7039                 break;
7040         case 4000000:
7041                 div_table = div_4000;
7042                 break;
7043         case 5333333:
7044                 div_table = div_5333;
7045                 break;
7046         default:
7047                 goto fail;
7048         }
7049
7050         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7051
7052 fail:
7053         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7054         return 200000;
7055 }
7056
7057 static int g33_get_display_clock_speed(struct drm_device *dev)
7058 {
7059         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7060         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7061         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7062         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7063         const uint8_t *div_table;
7064         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7065         uint16_t tmp = 0;
7066
7067         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7068
7069         cdclk_sel = (tmp >> 4) & 0x7;
7070
7071         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7072                 goto fail;
7073
7074         switch (vco) {
7075         case 3200000:
7076                 div_table = div_3200;
7077                 break;
7078         case 4000000:
7079                 div_table = div_4000;
7080                 break;
7081         case 4800000:
7082                 div_table = div_4800;
7083                 break;
7084         case 5333333:
7085                 div_table = div_5333;
7086                 break;
7087         default:
7088                 goto fail;
7089         }
7090
7091         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7092
7093 fail:
7094         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7095         return 190476;
7096 }
7097
7098 static void
7099 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7100 {
7101         while (*num > DATA_LINK_M_N_MASK ||
7102                *den > DATA_LINK_M_N_MASK) {
7103                 *num >>= 1;
7104                 *den >>= 1;
7105         }
7106 }
7107
7108 static void compute_m_n(unsigned int m, unsigned int n,
7109                         uint32_t *ret_m, uint32_t *ret_n)
7110 {
7111         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7112         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7113         intel_reduce_m_n_ratio(ret_m, ret_n);
7114 }
7115
7116 void
7117 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7118                        int pixel_clock, int link_clock,
7119                        struct intel_link_m_n *m_n)
7120 {
7121         m_n->tu = 64;
7122
7123         compute_m_n(bits_per_pixel * pixel_clock,
7124                     link_clock * nlanes * 8,
7125                     &m_n->gmch_m, &m_n->gmch_n);
7126
7127         compute_m_n(pixel_clock, link_clock,
7128                     &m_n->link_m, &m_n->link_n);
7129 }
7130
7131 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7132 {
7133         if (i915.panel_use_ssc >= 0)
7134                 return i915.panel_use_ssc != 0;
7135         return dev_priv->vbt.lvds_use_ssc
7136                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7137 }
7138
7139 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7140                            int num_connectors)
7141 {
7142         struct drm_device *dev = crtc_state->base.crtc->dev;
7143         struct drm_i915_private *dev_priv = dev->dev_private;
7144         int refclk;
7145
7146         WARN_ON(!crtc_state->base.state);
7147
7148         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7149                 refclk = 100000;
7150         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7151             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7152                 refclk = dev_priv->vbt.lvds_ssc_freq;
7153                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7154         } else if (!IS_GEN2(dev)) {
7155                 refclk = 96000;
7156         } else {
7157                 refclk = 48000;
7158         }
7159
7160         return refclk;
7161 }
7162
7163 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7164 {
7165         return (1 << dpll->n) << 16 | dpll->m2;
7166 }
7167
7168 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7169 {
7170         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7171 }
7172
7173 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7174                                      struct intel_crtc_state *crtc_state,
7175                                      intel_clock_t *reduced_clock)
7176 {
7177         struct drm_device *dev = crtc->base.dev;
7178         u32 fp, fp2 = 0;
7179
7180         if (IS_PINEVIEW(dev)) {
7181                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7182                 if (reduced_clock)
7183                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7184         } else {
7185                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7186                 if (reduced_clock)
7187                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7188         }
7189
7190         crtc_state->dpll_hw_state.fp0 = fp;
7191
7192         crtc->lowfreq_avail = false;
7193         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7194             reduced_clock) {
7195                 crtc_state->dpll_hw_state.fp1 = fp2;
7196                 crtc->lowfreq_avail = true;
7197         } else {
7198                 crtc_state->dpll_hw_state.fp1 = fp;
7199         }
7200 }
7201
7202 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7203                 pipe)
7204 {
7205         u32 reg_val;
7206
7207         /*
7208          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7209          * and set it to a reasonable value instead.
7210          */
7211         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7212         reg_val &= 0xffffff00;
7213         reg_val |= 0x00000030;
7214         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7215
7216         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7217         reg_val &= 0x8cffffff;
7218         reg_val = 0x8c000000;
7219         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7220
7221         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7222         reg_val &= 0xffffff00;
7223         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7224
7225         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7226         reg_val &= 0x00ffffff;
7227         reg_val |= 0xb0000000;
7228         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7229 }
7230
7231 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7232                                          struct intel_link_m_n *m_n)
7233 {
7234         struct drm_device *dev = crtc->base.dev;
7235         struct drm_i915_private *dev_priv = dev->dev_private;
7236         int pipe = crtc->pipe;
7237
7238         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7239         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7240         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7241         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7242 }
7243
7244 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7245                                          struct intel_link_m_n *m_n,
7246                                          struct intel_link_m_n *m2_n2)
7247 {
7248         struct drm_device *dev = crtc->base.dev;
7249         struct drm_i915_private *dev_priv = dev->dev_private;
7250         int pipe = crtc->pipe;
7251         enum transcoder transcoder = crtc->config->cpu_transcoder;
7252
7253         if (INTEL_INFO(dev)->gen >= 5) {
7254                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7255                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7256                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7257                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7258                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7259                  * for gen < 8) and if DRRS is supported (to make sure the
7260                  * registers are not unnecessarily accessed).
7261                  */
7262                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7263                         crtc->config->has_drrs) {
7264                         I915_WRITE(PIPE_DATA_M2(transcoder),
7265                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7266                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7267                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7268                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7269                 }
7270         } else {
7271                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7272                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7273                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7274                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7275         }
7276 }
7277
7278 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7279 {
7280         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7281
7282         if (m_n == M1_N1) {
7283                 dp_m_n = &crtc->config->dp_m_n;
7284                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7285         } else if (m_n == M2_N2) {
7286
7287                 /*
7288                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7289                  * needs to be programmed into M1_N1.
7290                  */
7291                 dp_m_n = &crtc->config->dp_m2_n2;
7292         } else {
7293                 DRM_ERROR("Unsupported divider value\n");
7294                 return;
7295         }
7296
7297         if (crtc->config->has_pch_encoder)
7298                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7299         else
7300                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7301 }
7302
7303 static void vlv_compute_dpll(struct intel_crtc *crtc,
7304                              struct intel_crtc_state *pipe_config)
7305 {
7306         u32 dpll, dpll_md;
7307
7308         /*
7309          * Enable DPIO clock input. We should never disable the reference
7310          * clock for pipe B, since VGA hotplug / manual detection depends
7311          * on it.
7312          */
7313         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7314                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7315         /* We should never disable this, set it here for state tracking */
7316         if (crtc->pipe == PIPE_B)
7317                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7318         dpll |= DPLL_VCO_ENABLE;
7319         pipe_config->dpll_hw_state.dpll = dpll;
7320
7321         dpll_md = (pipe_config->pixel_multiplier - 1)
7322                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7323         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7324 }
7325
7326 static void vlv_prepare_pll(struct intel_crtc *crtc,
7327                             const struct intel_crtc_state *pipe_config)
7328 {
7329         struct drm_device *dev = crtc->base.dev;
7330         struct drm_i915_private *dev_priv = dev->dev_private;
7331         int pipe = crtc->pipe;
7332         u32 mdiv;
7333         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7334         u32 coreclk, reg_val;
7335
7336         mutex_lock(&dev_priv->sb_lock);
7337
7338         bestn = pipe_config->dpll.n;
7339         bestm1 = pipe_config->dpll.m1;
7340         bestm2 = pipe_config->dpll.m2;
7341         bestp1 = pipe_config->dpll.p1;
7342         bestp2 = pipe_config->dpll.p2;
7343
7344         /* See eDP HDMI DPIO driver vbios notes doc */
7345
7346         /* PLL B needs special handling */
7347         if (pipe == PIPE_B)
7348                 vlv_pllb_recal_opamp(dev_priv, pipe);
7349
7350         /* Set up Tx target for periodic Rcomp update */
7351         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7352
7353         /* Disable target IRef on PLL */
7354         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7355         reg_val &= 0x00ffffff;
7356         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7357
7358         /* Disable fast lock */
7359         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7360
7361         /* Set idtafcrecal before PLL is enabled */
7362         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7363         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7364         mdiv |= ((bestn << DPIO_N_SHIFT));
7365         mdiv |= (1 << DPIO_K_SHIFT);
7366
7367         /*
7368          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7369          * but we don't support that).
7370          * Note: don't use the DAC post divider as it seems unstable.
7371          */
7372         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7373         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7374
7375         mdiv |= DPIO_ENABLE_CALIBRATION;
7376         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7377
7378         /* Set HBR and RBR LPF coefficients */
7379         if (pipe_config->port_clock == 162000 ||
7380             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7381             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7382                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7383                                  0x009f0003);
7384         else
7385                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7386                                  0x00d0000f);
7387
7388         if (pipe_config->has_dp_encoder) {
7389                 /* Use SSC source */
7390                 if (pipe == PIPE_A)
7391                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7392                                          0x0df40000);
7393                 else
7394                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7395                                          0x0df70000);
7396         } else { /* HDMI or VGA */
7397                 /* Use bend source */
7398                 if (pipe == PIPE_A)
7399                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7400                                          0x0df70000);
7401                 else
7402                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7403                                          0x0df40000);
7404         }
7405
7406         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7407         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7408         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7409             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7410                 coreclk |= 0x01000000;
7411         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7412
7413         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7414         mutex_unlock(&dev_priv->sb_lock);
7415 }
7416
7417 static void chv_compute_dpll(struct intel_crtc *crtc,
7418                              struct intel_crtc_state *pipe_config)
7419 {
7420         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7421                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7422                 DPLL_VCO_ENABLE;
7423         if (crtc->pipe != PIPE_A)
7424                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7425
7426         pipe_config->dpll_hw_state.dpll_md =
7427                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7428 }
7429
7430 static void chv_prepare_pll(struct intel_crtc *crtc,
7431                             const struct intel_crtc_state *pipe_config)
7432 {
7433         struct drm_device *dev = crtc->base.dev;
7434         struct drm_i915_private *dev_priv = dev->dev_private;
7435         int pipe = crtc->pipe;
7436         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7437         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7438         u32 loopfilter, tribuf_calcntr;
7439         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7440         u32 dpio_val;
7441         int vco;
7442
7443         bestn = pipe_config->dpll.n;
7444         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7445         bestm1 = pipe_config->dpll.m1;
7446         bestm2 = pipe_config->dpll.m2 >> 22;
7447         bestp1 = pipe_config->dpll.p1;
7448         bestp2 = pipe_config->dpll.p2;
7449         vco = pipe_config->dpll.vco;
7450         dpio_val = 0;
7451         loopfilter = 0;
7452
7453         /*
7454          * Enable Refclk and SSC
7455          */
7456         I915_WRITE(dpll_reg,
7457                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7458
7459         mutex_lock(&dev_priv->sb_lock);
7460
7461         /* p1 and p2 divider */
7462         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7463                         5 << DPIO_CHV_S1_DIV_SHIFT |
7464                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7465                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7466                         1 << DPIO_CHV_K_DIV_SHIFT);
7467
7468         /* Feedback post-divider - m2 */
7469         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7470
7471         /* Feedback refclk divider - n and m1 */
7472         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7473                         DPIO_CHV_M1_DIV_BY_2 |
7474                         1 << DPIO_CHV_N_DIV_SHIFT);
7475
7476         /* M2 fraction division */
7477         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7478
7479         /* M2 fraction division enable */
7480         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7481         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7482         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7483         if (bestm2_frac)
7484                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7485         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7486
7487         /* Program digital lock detect threshold */
7488         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7489         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7490                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7491         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7492         if (!bestm2_frac)
7493                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7494         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7495
7496         /* Loop filter */
7497         if (vco == 5400000) {
7498                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7499                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7500                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7501                 tribuf_calcntr = 0x9;
7502         } else if (vco <= 6200000) {
7503                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7504                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7505                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7506                 tribuf_calcntr = 0x9;
7507         } else if (vco <= 6480000) {
7508                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7509                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7510                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7511                 tribuf_calcntr = 0x8;
7512         } else {
7513                 /* Not supported. Apply the same limits as in the max case */
7514                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7515                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7516                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7517                 tribuf_calcntr = 0;
7518         }
7519         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7520
7521         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7522         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7523         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7524         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7525
7526         /* AFC Recal */
7527         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7528                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7529                         DPIO_AFC_RECAL);
7530
7531         mutex_unlock(&dev_priv->sb_lock);
7532 }
7533
7534 /**
7535  * vlv_force_pll_on - forcibly enable just the PLL
7536  * @dev_priv: i915 private structure
7537  * @pipe: pipe PLL to enable
7538  * @dpll: PLL configuration
7539  *
7540  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7541  * in cases where we need the PLL enabled even when @pipe is not going to
7542  * be enabled.
7543  */
7544 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7545                      const struct dpll *dpll)
7546 {
7547         struct intel_crtc *crtc =
7548                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7549         struct intel_crtc_state *pipe_config;
7550
7551         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7552         if (!pipe_config)
7553                 return -ENOMEM;
7554
7555         pipe_config->base.crtc = &crtc->base;
7556         pipe_config->pixel_multiplier = 1;
7557         pipe_config->dpll = *dpll;
7558
7559         if (IS_CHERRYVIEW(dev)) {
7560                 chv_compute_dpll(crtc, pipe_config);
7561                 chv_prepare_pll(crtc, pipe_config);
7562                 chv_enable_pll(crtc, pipe_config);
7563         } else {
7564                 vlv_compute_dpll(crtc, pipe_config);
7565                 vlv_prepare_pll(crtc, pipe_config);
7566                 vlv_enable_pll(crtc, pipe_config);
7567         }
7568
7569         kfree(pipe_config);
7570
7571         return 0;
7572 }
7573
7574 /**
7575  * vlv_force_pll_off - forcibly disable just the PLL
7576  * @dev_priv: i915 private structure
7577  * @pipe: pipe PLL to disable
7578  *
7579  * Disable the PLL for @pipe. To be used in cases where we need
7580  * the PLL enabled even when @pipe is not going to be enabled.
7581  */
7582 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7583 {
7584         if (IS_CHERRYVIEW(dev))
7585                 chv_disable_pll(to_i915(dev), pipe);
7586         else
7587                 vlv_disable_pll(to_i915(dev), pipe);
7588 }
7589
7590 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7591                               struct intel_crtc_state *crtc_state,
7592                               intel_clock_t *reduced_clock,
7593                               int num_connectors)
7594 {
7595         struct drm_device *dev = crtc->base.dev;
7596         struct drm_i915_private *dev_priv = dev->dev_private;
7597         u32 dpll;
7598         bool is_sdvo;
7599         struct dpll *clock = &crtc_state->dpll;
7600
7601         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7602
7603         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7604                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7605
7606         dpll = DPLL_VGA_MODE_DIS;
7607
7608         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7609                 dpll |= DPLLB_MODE_LVDS;
7610         else
7611                 dpll |= DPLLB_MODE_DAC_SERIAL;
7612
7613         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7614                 dpll |= (crtc_state->pixel_multiplier - 1)
7615                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7616         }
7617
7618         if (is_sdvo)
7619                 dpll |= DPLL_SDVO_HIGH_SPEED;
7620
7621         if (crtc_state->has_dp_encoder)
7622                 dpll |= DPLL_SDVO_HIGH_SPEED;
7623
7624         /* compute bitmask from p1 value */
7625         if (IS_PINEVIEW(dev))
7626                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7627         else {
7628                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7629                 if (IS_G4X(dev) && reduced_clock)
7630                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7631         }
7632         switch (clock->p2) {
7633         case 5:
7634                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7635                 break;
7636         case 7:
7637                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7638                 break;
7639         case 10:
7640                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7641                 break;
7642         case 14:
7643                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7644                 break;
7645         }
7646         if (INTEL_INFO(dev)->gen >= 4)
7647                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7648
7649         if (crtc_state->sdvo_tv_clock)
7650                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7651         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7652                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7653                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7654         else
7655                 dpll |= PLL_REF_INPUT_DREFCLK;
7656
7657         dpll |= DPLL_VCO_ENABLE;
7658         crtc_state->dpll_hw_state.dpll = dpll;
7659
7660         if (INTEL_INFO(dev)->gen >= 4) {
7661                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7662                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7663                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7664         }
7665 }
7666
7667 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7668                               struct intel_crtc_state *crtc_state,
7669                               intel_clock_t *reduced_clock,
7670                               int num_connectors)
7671 {
7672         struct drm_device *dev = crtc->base.dev;
7673         struct drm_i915_private *dev_priv = dev->dev_private;
7674         u32 dpll;
7675         struct dpll *clock = &crtc_state->dpll;
7676
7677         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7678
7679         dpll = DPLL_VGA_MODE_DIS;
7680
7681         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7682                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7683         } else {
7684                 if (clock->p1 == 2)
7685                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7686                 else
7687                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7688                 if (clock->p2 == 4)
7689                         dpll |= PLL_P2_DIVIDE_BY_4;
7690         }
7691
7692         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7693                 dpll |= DPLL_DVO_2X_MODE;
7694
7695         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7696                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7697                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7698         else
7699                 dpll |= PLL_REF_INPUT_DREFCLK;
7700
7701         dpll |= DPLL_VCO_ENABLE;
7702         crtc_state->dpll_hw_state.dpll = dpll;
7703 }
7704
7705 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7706 {
7707         struct drm_device *dev = intel_crtc->base.dev;
7708         struct drm_i915_private *dev_priv = dev->dev_private;
7709         enum pipe pipe = intel_crtc->pipe;
7710         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7711         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7712         uint32_t crtc_vtotal, crtc_vblank_end;
7713         int vsyncshift = 0;
7714
7715         /* We need to be careful not to changed the adjusted mode, for otherwise
7716          * the hw state checker will get angry at the mismatch. */
7717         crtc_vtotal = adjusted_mode->crtc_vtotal;
7718         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7719
7720         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7721                 /* the chip adds 2 halflines automatically */
7722                 crtc_vtotal -= 1;
7723                 crtc_vblank_end -= 1;
7724
7725                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7726                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7727                 else
7728                         vsyncshift = adjusted_mode->crtc_hsync_start -
7729                                 adjusted_mode->crtc_htotal / 2;
7730                 if (vsyncshift < 0)
7731                         vsyncshift += adjusted_mode->crtc_htotal;
7732         }
7733
7734         if (INTEL_INFO(dev)->gen > 3)
7735                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7736
7737         I915_WRITE(HTOTAL(cpu_transcoder),
7738                    (adjusted_mode->crtc_hdisplay - 1) |
7739                    ((adjusted_mode->crtc_htotal - 1) << 16));
7740         I915_WRITE(HBLANK(cpu_transcoder),
7741                    (adjusted_mode->crtc_hblank_start - 1) |
7742                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7743         I915_WRITE(HSYNC(cpu_transcoder),
7744                    (adjusted_mode->crtc_hsync_start - 1) |
7745                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7746
7747         I915_WRITE(VTOTAL(cpu_transcoder),
7748                    (adjusted_mode->crtc_vdisplay - 1) |
7749                    ((crtc_vtotal - 1) << 16));
7750         I915_WRITE(VBLANK(cpu_transcoder),
7751                    (adjusted_mode->crtc_vblank_start - 1) |
7752                    ((crtc_vblank_end - 1) << 16));
7753         I915_WRITE(VSYNC(cpu_transcoder),
7754                    (adjusted_mode->crtc_vsync_start - 1) |
7755                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7756
7757         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7758          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7759          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7760          * bits. */
7761         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7762             (pipe == PIPE_B || pipe == PIPE_C))
7763                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7764
7765         /* pipesrc controls the size that is scaled from, which should
7766          * always be the user's requested size.
7767          */
7768         I915_WRITE(PIPESRC(pipe),
7769                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7770                    (intel_crtc->config->pipe_src_h - 1));
7771 }
7772
7773 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7774                                    struct intel_crtc_state *pipe_config)
7775 {
7776         struct drm_device *dev = crtc->base.dev;
7777         struct drm_i915_private *dev_priv = dev->dev_private;
7778         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7779         uint32_t tmp;
7780
7781         tmp = I915_READ(HTOTAL(cpu_transcoder));
7782         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7783         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7784         tmp = I915_READ(HBLANK(cpu_transcoder));
7785         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7786         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7787         tmp = I915_READ(HSYNC(cpu_transcoder));
7788         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7789         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7790
7791         tmp = I915_READ(VTOTAL(cpu_transcoder));
7792         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7793         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7794         tmp = I915_READ(VBLANK(cpu_transcoder));
7795         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7796         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7797         tmp = I915_READ(VSYNC(cpu_transcoder));
7798         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7799         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7800
7801         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7802                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7803                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7804                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7805         }
7806
7807         tmp = I915_READ(PIPESRC(crtc->pipe));
7808         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7809         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7810
7811         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7812         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7813 }
7814
7815 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7816                                  struct intel_crtc_state *pipe_config)
7817 {
7818         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7819         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7820         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7821         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7822
7823         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7824         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7825         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7826         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7827
7828         mode->flags = pipe_config->base.adjusted_mode.flags;
7829         mode->type = DRM_MODE_TYPE_DRIVER;
7830
7831         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7832         mode->flags |= pipe_config->base.adjusted_mode.flags;
7833
7834         mode->hsync = drm_mode_hsync(mode);
7835         mode->vrefresh = drm_mode_vrefresh(mode);
7836         drm_mode_set_name(mode);
7837 }
7838
7839 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7840 {
7841         struct drm_device *dev = intel_crtc->base.dev;
7842         struct drm_i915_private *dev_priv = dev->dev_private;
7843         uint32_t pipeconf;
7844
7845         pipeconf = 0;
7846
7847         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7848             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7849                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7850
7851         if (intel_crtc->config->double_wide)
7852                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7853
7854         /* only g4x and later have fancy bpc/dither controls */
7855         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7856                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7857                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7858                         pipeconf |= PIPECONF_DITHER_EN |
7859                                     PIPECONF_DITHER_TYPE_SP;
7860
7861                 switch (intel_crtc->config->pipe_bpp) {
7862                 case 18:
7863                         pipeconf |= PIPECONF_6BPC;
7864                         break;
7865                 case 24:
7866                         pipeconf |= PIPECONF_8BPC;
7867                         break;
7868                 case 30:
7869                         pipeconf |= PIPECONF_10BPC;
7870                         break;
7871                 default:
7872                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7873                         BUG();
7874                 }
7875         }
7876
7877         if (HAS_PIPE_CXSR(dev)) {
7878                 if (intel_crtc->lowfreq_avail) {
7879                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7880                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7881                 } else {
7882                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7883                 }
7884         }
7885
7886         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7887                 if (INTEL_INFO(dev)->gen < 4 ||
7888                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7889                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7890                 else
7891                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7892         } else
7893                 pipeconf |= PIPECONF_PROGRESSIVE;
7894
7895         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7896              intel_crtc->config->limited_color_range)
7897                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7898
7899         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7900         POSTING_READ(PIPECONF(intel_crtc->pipe));
7901 }
7902
7903 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7904                                    struct intel_crtc_state *crtc_state)
7905 {
7906         struct drm_device *dev = crtc->base.dev;
7907         struct drm_i915_private *dev_priv = dev->dev_private;
7908         int refclk, num_connectors = 0;
7909         intel_clock_t clock;
7910         bool ok;
7911         const intel_limit_t *limit;
7912         struct drm_atomic_state *state = crtc_state->base.state;
7913         struct drm_connector *connector;
7914         struct drm_connector_state *connector_state;
7915         int i;
7916
7917         memset(&crtc_state->dpll_hw_state, 0,
7918                sizeof(crtc_state->dpll_hw_state));
7919
7920         if (crtc_state->has_dsi_encoder)
7921                 return 0;
7922
7923         for_each_connector_in_state(state, connector, connector_state, i) {
7924                 if (connector_state->crtc == &crtc->base)
7925                         num_connectors++;
7926         }
7927
7928         if (!crtc_state->clock_set) {
7929                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7930
7931                 /*
7932                  * Returns a set of divisors for the desired target clock with
7933                  * the given refclk, or FALSE.  The returned values represent
7934                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7935                  * 2) / p1 / p2.
7936                  */
7937                 limit = intel_limit(crtc_state, refclk);
7938                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7939                                                  crtc_state->port_clock,
7940                                                  refclk, NULL, &clock);
7941                 if (!ok) {
7942                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7943                         return -EINVAL;
7944                 }
7945
7946                 /* Compat-code for transition, will disappear. */
7947                 crtc_state->dpll.n = clock.n;
7948                 crtc_state->dpll.m1 = clock.m1;
7949                 crtc_state->dpll.m2 = clock.m2;
7950                 crtc_state->dpll.p1 = clock.p1;
7951                 crtc_state->dpll.p2 = clock.p2;
7952         }
7953
7954         if (IS_GEN2(dev)) {
7955                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7956                                   num_connectors);
7957         } else if (IS_CHERRYVIEW(dev)) {
7958                 chv_compute_dpll(crtc, crtc_state);
7959         } else if (IS_VALLEYVIEW(dev)) {
7960                 vlv_compute_dpll(crtc, crtc_state);
7961         } else {
7962                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7963                                   num_connectors);
7964         }
7965
7966         return 0;
7967 }
7968
7969 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7970                                  struct intel_crtc_state *pipe_config)
7971 {
7972         struct drm_device *dev = crtc->base.dev;
7973         struct drm_i915_private *dev_priv = dev->dev_private;
7974         uint32_t tmp;
7975
7976         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7977                 return;
7978
7979         tmp = I915_READ(PFIT_CONTROL);
7980         if (!(tmp & PFIT_ENABLE))
7981                 return;
7982
7983         /* Check whether the pfit is attached to our pipe. */
7984         if (INTEL_INFO(dev)->gen < 4) {
7985                 if (crtc->pipe != PIPE_B)
7986                         return;
7987         } else {
7988                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7989                         return;
7990         }
7991
7992         pipe_config->gmch_pfit.control = tmp;
7993         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7994         if (INTEL_INFO(dev)->gen < 5)
7995                 pipe_config->gmch_pfit.lvds_border_bits =
7996                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7997 }
7998
7999 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8000                                struct intel_crtc_state *pipe_config)
8001 {
8002         struct drm_device *dev = crtc->base.dev;
8003         struct drm_i915_private *dev_priv = dev->dev_private;
8004         int pipe = pipe_config->cpu_transcoder;
8005         intel_clock_t clock;
8006         u32 mdiv;
8007         int refclk = 100000;
8008
8009         /* In case of MIPI DPLL will not even be used */
8010         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8011                 return;
8012
8013         mutex_lock(&dev_priv->sb_lock);
8014         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8015         mutex_unlock(&dev_priv->sb_lock);
8016
8017         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8018         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8019         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8020         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8021         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8022
8023         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8024 }
8025
8026 static void
8027 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8028                               struct intel_initial_plane_config *plane_config)
8029 {
8030         struct drm_device *dev = crtc->base.dev;
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032         u32 val, base, offset;
8033         int pipe = crtc->pipe, plane = crtc->plane;
8034         int fourcc, pixel_format;
8035         unsigned int aligned_height;
8036         struct drm_framebuffer *fb;
8037         struct intel_framebuffer *intel_fb;
8038
8039         val = I915_READ(DSPCNTR(plane));
8040         if (!(val & DISPLAY_PLANE_ENABLE))
8041                 return;
8042
8043         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8044         if (!intel_fb) {
8045                 DRM_DEBUG_KMS("failed to alloc fb\n");
8046                 return;
8047         }
8048
8049         fb = &intel_fb->base;
8050
8051         if (INTEL_INFO(dev)->gen >= 4) {
8052                 if (val & DISPPLANE_TILED) {
8053                         plane_config->tiling = I915_TILING_X;
8054                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8055                 }
8056         }
8057
8058         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8059         fourcc = i9xx_format_to_fourcc(pixel_format);
8060         fb->pixel_format = fourcc;
8061         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8062
8063         if (INTEL_INFO(dev)->gen >= 4) {
8064                 if (plane_config->tiling)
8065                         offset = I915_READ(DSPTILEOFF(plane));
8066                 else
8067                         offset = I915_READ(DSPLINOFF(plane));
8068                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8069         } else {
8070                 base = I915_READ(DSPADDR(plane));
8071         }
8072         plane_config->base = base;
8073
8074         val = I915_READ(PIPESRC(pipe));
8075         fb->width = ((val >> 16) & 0xfff) + 1;
8076         fb->height = ((val >> 0) & 0xfff) + 1;
8077
8078         val = I915_READ(DSPSTRIDE(pipe));
8079         fb->pitches[0] = val & 0xffffffc0;
8080
8081         aligned_height = intel_fb_align_height(dev, fb->height,
8082                                                fb->pixel_format,
8083                                                fb->modifier[0]);
8084
8085         plane_config->size = fb->pitches[0] * aligned_height;
8086
8087         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8088                       pipe_name(pipe), plane, fb->width, fb->height,
8089                       fb->bits_per_pixel, base, fb->pitches[0],
8090                       plane_config->size);
8091
8092         plane_config->fb = intel_fb;
8093 }
8094
8095 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8096                                struct intel_crtc_state *pipe_config)
8097 {
8098         struct drm_device *dev = crtc->base.dev;
8099         struct drm_i915_private *dev_priv = dev->dev_private;
8100         int pipe = pipe_config->cpu_transcoder;
8101         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8102         intel_clock_t clock;
8103         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8104         int refclk = 100000;
8105
8106         mutex_lock(&dev_priv->sb_lock);
8107         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8108         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8109         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8110         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8111         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8112         mutex_unlock(&dev_priv->sb_lock);
8113
8114         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8115         clock.m2 = (pll_dw0 & 0xff) << 22;
8116         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8117                 clock.m2 |= pll_dw2 & 0x3fffff;
8118         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8119         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8120         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8121
8122         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8123 }
8124
8125 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8126                                  struct intel_crtc_state *pipe_config)
8127 {
8128         struct drm_device *dev = crtc->base.dev;
8129         struct drm_i915_private *dev_priv = dev->dev_private;
8130         enum intel_display_power_domain power_domain;
8131         uint32_t tmp;
8132         bool ret;
8133
8134         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8135         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8136                 return false;
8137
8138         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8139         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8140
8141         ret = false;
8142
8143         tmp = I915_READ(PIPECONF(crtc->pipe));
8144         if (!(tmp & PIPECONF_ENABLE))
8145                 goto out;
8146
8147         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8148                 switch (tmp & PIPECONF_BPC_MASK) {
8149                 case PIPECONF_6BPC:
8150                         pipe_config->pipe_bpp = 18;
8151                         break;
8152                 case PIPECONF_8BPC:
8153                         pipe_config->pipe_bpp = 24;
8154                         break;
8155                 case PIPECONF_10BPC:
8156                         pipe_config->pipe_bpp = 30;
8157                         break;
8158                 default:
8159                         break;
8160                 }
8161         }
8162
8163         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8164             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8165                 pipe_config->limited_color_range = true;
8166
8167         if (INTEL_INFO(dev)->gen < 4)
8168                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8169
8170         intel_get_pipe_timings(crtc, pipe_config);
8171
8172         i9xx_get_pfit_config(crtc, pipe_config);
8173
8174         if (INTEL_INFO(dev)->gen >= 4) {
8175                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8176                 pipe_config->pixel_multiplier =
8177                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8178                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8179                 pipe_config->dpll_hw_state.dpll_md = tmp;
8180         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8181                 tmp = I915_READ(DPLL(crtc->pipe));
8182                 pipe_config->pixel_multiplier =
8183                         ((tmp & SDVO_MULTIPLIER_MASK)
8184                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8185         } else {
8186                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8187                  * port and will be fixed up in the encoder->get_config
8188                  * function. */
8189                 pipe_config->pixel_multiplier = 1;
8190         }
8191         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8192         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8193                 /*
8194                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8195                  * on 830. Filter it out here so that we don't
8196                  * report errors due to that.
8197                  */
8198                 if (IS_I830(dev))
8199                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8200
8201                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8202                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8203         } else {
8204                 /* Mask out read-only status bits. */
8205                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8206                                                      DPLL_PORTC_READY_MASK |
8207                                                      DPLL_PORTB_READY_MASK);
8208         }
8209
8210         if (IS_CHERRYVIEW(dev))
8211                 chv_crtc_clock_get(crtc, pipe_config);
8212         else if (IS_VALLEYVIEW(dev))
8213                 vlv_crtc_clock_get(crtc, pipe_config);
8214         else
8215                 i9xx_crtc_clock_get(crtc, pipe_config);
8216
8217         /*
8218          * Normally the dotclock is filled in by the encoder .get_config()
8219          * but in case the pipe is enabled w/o any ports we need a sane
8220          * default.
8221          */
8222         pipe_config->base.adjusted_mode.crtc_clock =
8223                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8224
8225         ret = true;
8226
8227 out:
8228         intel_display_power_put(dev_priv, power_domain);
8229
8230         return ret;
8231 }
8232
8233 static void ironlake_init_pch_refclk(struct drm_device *dev)
8234 {
8235         struct drm_i915_private *dev_priv = dev->dev_private;
8236         struct intel_encoder *encoder;
8237         u32 val, final;
8238         bool has_lvds = false;
8239         bool has_cpu_edp = false;
8240         bool has_panel = false;
8241         bool has_ck505 = false;
8242         bool can_ssc = false;
8243
8244         /* We need to take the global config into account */
8245         for_each_intel_encoder(dev, encoder) {
8246                 switch (encoder->type) {
8247                 case INTEL_OUTPUT_LVDS:
8248                         has_panel = true;
8249                         has_lvds = true;
8250                         break;
8251                 case INTEL_OUTPUT_EDP:
8252                         has_panel = true;
8253                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8254                                 has_cpu_edp = true;
8255                         break;
8256                 default:
8257                         break;
8258                 }
8259         }
8260
8261         if (HAS_PCH_IBX(dev)) {
8262                 has_ck505 = dev_priv->vbt.display_clock_mode;
8263                 can_ssc = has_ck505;
8264         } else {
8265                 has_ck505 = false;
8266                 can_ssc = true;
8267         }
8268
8269         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8270                       has_panel, has_lvds, has_ck505);
8271
8272         /* Ironlake: try to setup display ref clock before DPLL
8273          * enabling. This is only under driver's control after
8274          * PCH B stepping, previous chipset stepping should be
8275          * ignoring this setting.
8276          */
8277         val = I915_READ(PCH_DREF_CONTROL);
8278
8279         /* As we must carefully and slowly disable/enable each source in turn,
8280          * compute the final state we want first and check if we need to
8281          * make any changes at all.
8282          */
8283         final = val;
8284         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8285         if (has_ck505)
8286                 final |= DREF_NONSPREAD_CK505_ENABLE;
8287         else
8288                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8289
8290         final &= ~DREF_SSC_SOURCE_MASK;
8291         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8292         final &= ~DREF_SSC1_ENABLE;
8293
8294         if (has_panel) {
8295                 final |= DREF_SSC_SOURCE_ENABLE;
8296
8297                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8298                         final |= DREF_SSC1_ENABLE;
8299
8300                 if (has_cpu_edp) {
8301                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8302                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8303                         else
8304                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8305                 } else
8306                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8307         } else {
8308                 final |= DREF_SSC_SOURCE_DISABLE;
8309                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8310         }
8311
8312         if (final == val)
8313                 return;
8314
8315         /* Always enable nonspread source */
8316         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8317
8318         if (has_ck505)
8319                 val |= DREF_NONSPREAD_CK505_ENABLE;
8320         else
8321                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8322
8323         if (has_panel) {
8324                 val &= ~DREF_SSC_SOURCE_MASK;
8325                 val |= DREF_SSC_SOURCE_ENABLE;
8326
8327                 /* SSC must be turned on before enabling the CPU output  */
8328                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8329                         DRM_DEBUG_KMS("Using SSC on panel\n");
8330                         val |= DREF_SSC1_ENABLE;
8331                 } else
8332                         val &= ~DREF_SSC1_ENABLE;
8333
8334                 /* Get SSC going before enabling the outputs */
8335                 I915_WRITE(PCH_DREF_CONTROL, val);
8336                 POSTING_READ(PCH_DREF_CONTROL);
8337                 udelay(200);
8338
8339                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8340
8341                 /* Enable CPU source on CPU attached eDP */
8342                 if (has_cpu_edp) {
8343                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8344                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8345                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8346                         } else
8347                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8348                 } else
8349                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8350
8351                 I915_WRITE(PCH_DREF_CONTROL, val);
8352                 POSTING_READ(PCH_DREF_CONTROL);
8353                 udelay(200);
8354         } else {
8355                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8356
8357                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8358
8359                 /* Turn off CPU output */
8360                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8361
8362                 I915_WRITE(PCH_DREF_CONTROL, val);
8363                 POSTING_READ(PCH_DREF_CONTROL);
8364                 udelay(200);
8365
8366                 /* Turn off the SSC source */
8367                 val &= ~DREF_SSC_SOURCE_MASK;
8368                 val |= DREF_SSC_SOURCE_DISABLE;
8369
8370                 /* Turn off SSC1 */
8371                 val &= ~DREF_SSC1_ENABLE;
8372
8373                 I915_WRITE(PCH_DREF_CONTROL, val);
8374                 POSTING_READ(PCH_DREF_CONTROL);
8375                 udelay(200);
8376         }
8377
8378         BUG_ON(val != final);
8379 }
8380
8381 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8382 {
8383         uint32_t tmp;
8384
8385         tmp = I915_READ(SOUTH_CHICKEN2);
8386         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8387         I915_WRITE(SOUTH_CHICKEN2, tmp);
8388
8389         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8390                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8391                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8392
8393         tmp = I915_READ(SOUTH_CHICKEN2);
8394         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8395         I915_WRITE(SOUTH_CHICKEN2, tmp);
8396
8397         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8398                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8399                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8400 }
8401
8402 /* WaMPhyProgramming:hsw */
8403 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8404 {
8405         uint32_t tmp;
8406
8407         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8408         tmp &= ~(0xFF << 24);
8409         tmp |= (0x12 << 24);
8410         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8411
8412         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8413         tmp |= (1 << 11);
8414         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8415
8416         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8417         tmp |= (1 << 11);
8418         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8419
8420         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8421         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8422         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8423
8424         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8425         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8426         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8427
8428         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8429         tmp &= ~(7 << 13);
8430         tmp |= (5 << 13);
8431         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8432
8433         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8434         tmp &= ~(7 << 13);
8435         tmp |= (5 << 13);
8436         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8439         tmp &= ~0xFF;
8440         tmp |= 0x1C;
8441         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8442
8443         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8444         tmp &= ~0xFF;
8445         tmp |= 0x1C;
8446         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8447
8448         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8449         tmp &= ~(0xFF << 16);
8450         tmp |= (0x1C << 16);
8451         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8452
8453         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8454         tmp &= ~(0xFF << 16);
8455         tmp |= (0x1C << 16);
8456         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8457
8458         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8459         tmp |= (1 << 27);
8460         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8461
8462         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8463         tmp |= (1 << 27);
8464         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8465
8466         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8467         tmp &= ~(0xF << 28);
8468         tmp |= (4 << 28);
8469         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8470
8471         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8472         tmp &= ~(0xF << 28);
8473         tmp |= (4 << 28);
8474         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8475 }
8476
8477 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8478  * Programming" based on the parameters passed:
8479  * - Sequence to enable CLKOUT_DP
8480  * - Sequence to enable CLKOUT_DP without spread
8481  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8482  */
8483 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8484                                  bool with_fdi)
8485 {
8486         struct drm_i915_private *dev_priv = dev->dev_private;
8487         uint32_t reg, tmp;
8488
8489         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8490                 with_spread = true;
8491         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8492                 with_fdi = false;
8493
8494         mutex_lock(&dev_priv->sb_lock);
8495
8496         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8497         tmp &= ~SBI_SSCCTL_DISABLE;
8498         tmp |= SBI_SSCCTL_PATHALT;
8499         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8500
8501         udelay(24);
8502
8503         if (with_spread) {
8504                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8505                 tmp &= ~SBI_SSCCTL_PATHALT;
8506                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8507
8508                 if (with_fdi) {
8509                         lpt_reset_fdi_mphy(dev_priv);
8510                         lpt_program_fdi_mphy(dev_priv);
8511                 }
8512         }
8513
8514         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8515         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8516         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8517         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8518
8519         mutex_unlock(&dev_priv->sb_lock);
8520 }
8521
8522 /* Sequence to disable CLKOUT_DP */
8523 static void lpt_disable_clkout_dp(struct drm_device *dev)
8524 {
8525         struct drm_i915_private *dev_priv = dev->dev_private;
8526         uint32_t reg, tmp;
8527
8528         mutex_lock(&dev_priv->sb_lock);
8529
8530         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8531         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8532         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8533         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8534
8535         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8536         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8537                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8538                         tmp |= SBI_SSCCTL_PATHALT;
8539                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8540                         udelay(32);
8541                 }
8542                 tmp |= SBI_SSCCTL_DISABLE;
8543                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8544         }
8545
8546         mutex_unlock(&dev_priv->sb_lock);
8547 }
8548
8549 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8550
8551 static const uint16_t sscdivintphase[] = {
8552         [BEND_IDX( 50)] = 0x3B23,
8553         [BEND_IDX( 45)] = 0x3B23,
8554         [BEND_IDX( 40)] = 0x3C23,
8555         [BEND_IDX( 35)] = 0x3C23,
8556         [BEND_IDX( 30)] = 0x3D23,
8557         [BEND_IDX( 25)] = 0x3D23,
8558         [BEND_IDX( 20)] = 0x3E23,
8559         [BEND_IDX( 15)] = 0x3E23,
8560         [BEND_IDX( 10)] = 0x3F23,
8561         [BEND_IDX(  5)] = 0x3F23,
8562         [BEND_IDX(  0)] = 0x0025,
8563         [BEND_IDX( -5)] = 0x0025,
8564         [BEND_IDX(-10)] = 0x0125,
8565         [BEND_IDX(-15)] = 0x0125,
8566         [BEND_IDX(-20)] = 0x0225,
8567         [BEND_IDX(-25)] = 0x0225,
8568         [BEND_IDX(-30)] = 0x0325,
8569         [BEND_IDX(-35)] = 0x0325,
8570         [BEND_IDX(-40)] = 0x0425,
8571         [BEND_IDX(-45)] = 0x0425,
8572         [BEND_IDX(-50)] = 0x0525,
8573 };
8574
8575 /*
8576  * Bend CLKOUT_DP
8577  * steps -50 to 50 inclusive, in steps of 5
8578  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8579  * change in clock period = -(steps / 10) * 5.787 ps
8580  */
8581 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8582 {
8583         uint32_t tmp;
8584         int idx = BEND_IDX(steps);
8585
8586         if (WARN_ON(steps % 5 != 0))
8587                 return;
8588
8589         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8590                 return;
8591
8592         mutex_lock(&dev_priv->sb_lock);
8593
8594         if (steps % 10 != 0)
8595                 tmp = 0xAAAAAAAB;
8596         else
8597                 tmp = 0x00000000;
8598         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8599
8600         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8601         tmp &= 0xffff0000;
8602         tmp |= sscdivintphase[idx];
8603         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8604
8605         mutex_unlock(&dev_priv->sb_lock);
8606 }
8607
8608 #undef BEND_IDX
8609
8610 static void lpt_init_pch_refclk(struct drm_device *dev)
8611 {
8612         struct intel_encoder *encoder;
8613         bool has_vga = false;
8614
8615         for_each_intel_encoder(dev, encoder) {
8616                 switch (encoder->type) {
8617                 case INTEL_OUTPUT_ANALOG:
8618                         has_vga = true;
8619                         break;
8620                 default:
8621                         break;
8622                 }
8623         }
8624
8625         if (has_vga) {
8626                 lpt_bend_clkout_dp(to_i915(dev), 0);
8627                 lpt_enable_clkout_dp(dev, true, true);
8628         } else {
8629                 lpt_disable_clkout_dp(dev);
8630         }
8631 }
8632
8633 /*
8634  * Initialize reference clocks when the driver loads
8635  */
8636 void intel_init_pch_refclk(struct drm_device *dev)
8637 {
8638         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8639                 ironlake_init_pch_refclk(dev);
8640         else if (HAS_PCH_LPT(dev))
8641                 lpt_init_pch_refclk(dev);
8642 }
8643
8644 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8645 {
8646         struct drm_device *dev = crtc_state->base.crtc->dev;
8647         struct drm_i915_private *dev_priv = dev->dev_private;
8648         struct drm_atomic_state *state = crtc_state->base.state;
8649         struct drm_connector *connector;
8650         struct drm_connector_state *connector_state;
8651         struct intel_encoder *encoder;
8652         int num_connectors = 0, i;
8653         bool is_lvds = false;
8654
8655         for_each_connector_in_state(state, connector, connector_state, i) {
8656                 if (connector_state->crtc != crtc_state->base.crtc)
8657                         continue;
8658
8659                 encoder = to_intel_encoder(connector_state->best_encoder);
8660
8661                 switch (encoder->type) {
8662                 case INTEL_OUTPUT_LVDS:
8663                         is_lvds = true;
8664                         break;
8665                 default:
8666                         break;
8667                 }
8668                 num_connectors++;
8669         }
8670
8671         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8672                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8673                               dev_priv->vbt.lvds_ssc_freq);
8674                 return dev_priv->vbt.lvds_ssc_freq;
8675         }
8676
8677         return 120000;
8678 }
8679
8680 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8681 {
8682         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8684         int pipe = intel_crtc->pipe;
8685         uint32_t val;
8686
8687         val = 0;
8688
8689         switch (intel_crtc->config->pipe_bpp) {
8690         case 18:
8691                 val |= PIPECONF_6BPC;
8692                 break;
8693         case 24:
8694                 val |= PIPECONF_8BPC;
8695                 break;
8696         case 30:
8697                 val |= PIPECONF_10BPC;
8698                 break;
8699         case 36:
8700                 val |= PIPECONF_12BPC;
8701                 break;
8702         default:
8703                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8704                 BUG();
8705         }
8706
8707         if (intel_crtc->config->dither)
8708                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8709
8710         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8711                 val |= PIPECONF_INTERLACED_ILK;
8712         else
8713                 val |= PIPECONF_PROGRESSIVE;
8714
8715         if (intel_crtc->config->limited_color_range)
8716                 val |= PIPECONF_COLOR_RANGE_SELECT;
8717
8718         I915_WRITE(PIPECONF(pipe), val);
8719         POSTING_READ(PIPECONF(pipe));
8720 }
8721
8722 /*
8723  * Set up the pipe CSC unit.
8724  *
8725  * Currently only full range RGB to limited range RGB conversion
8726  * is supported, but eventually this should handle various
8727  * RGB<->YCbCr scenarios as well.
8728  */
8729 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8730 {
8731         struct drm_device *dev = crtc->dev;
8732         struct drm_i915_private *dev_priv = dev->dev_private;
8733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8734         int pipe = intel_crtc->pipe;
8735         uint16_t coeff = 0x7800; /* 1.0 */
8736
8737         /*
8738          * TODO: Check what kind of values actually come out of the pipe
8739          * with these coeff/postoff values and adjust to get the best
8740          * accuracy. Perhaps we even need to take the bpc value into
8741          * consideration.
8742          */
8743
8744         if (intel_crtc->config->limited_color_range)
8745                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8746
8747         /*
8748          * GY/GU and RY/RU should be the other way around according
8749          * to BSpec, but reality doesn't agree. Just set them up in
8750          * a way that results in the correct picture.
8751          */
8752         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8753         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8754
8755         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8756         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8757
8758         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8759         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8760
8761         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8762         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8763         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8764
8765         if (INTEL_INFO(dev)->gen > 6) {
8766                 uint16_t postoff = 0;
8767
8768                 if (intel_crtc->config->limited_color_range)
8769                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8770
8771                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8772                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8773                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8774
8775                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8776         } else {
8777                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8778
8779                 if (intel_crtc->config->limited_color_range)
8780                         mode |= CSC_BLACK_SCREEN_OFFSET;
8781
8782                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8783         }
8784 }
8785
8786 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8787 {
8788         struct drm_device *dev = crtc->dev;
8789         struct drm_i915_private *dev_priv = dev->dev_private;
8790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8791         enum pipe pipe = intel_crtc->pipe;
8792         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8793         uint32_t val;
8794
8795         val = 0;
8796
8797         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8798                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8799
8800         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8801                 val |= PIPECONF_INTERLACED_ILK;
8802         else
8803                 val |= PIPECONF_PROGRESSIVE;
8804
8805         I915_WRITE(PIPECONF(cpu_transcoder), val);
8806         POSTING_READ(PIPECONF(cpu_transcoder));
8807
8808         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8809         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8810
8811         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8812                 val = 0;
8813
8814                 switch (intel_crtc->config->pipe_bpp) {
8815                 case 18:
8816                         val |= PIPEMISC_DITHER_6_BPC;
8817                         break;
8818                 case 24:
8819                         val |= PIPEMISC_DITHER_8_BPC;
8820                         break;
8821                 case 30:
8822                         val |= PIPEMISC_DITHER_10_BPC;
8823                         break;
8824                 case 36:
8825                         val |= PIPEMISC_DITHER_12_BPC;
8826                         break;
8827                 default:
8828                         /* Case prevented by pipe_config_set_bpp. */
8829                         BUG();
8830                 }
8831
8832                 if (intel_crtc->config->dither)
8833                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8834
8835                 I915_WRITE(PIPEMISC(pipe), val);
8836         }
8837 }
8838
8839 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8840                                     struct intel_crtc_state *crtc_state,
8841                                     intel_clock_t *clock,
8842                                     bool *has_reduced_clock,
8843                                     intel_clock_t *reduced_clock)
8844 {
8845         struct drm_device *dev = crtc->dev;
8846         struct drm_i915_private *dev_priv = dev->dev_private;
8847         int refclk;
8848         const intel_limit_t *limit;
8849         bool ret;
8850
8851         refclk = ironlake_get_refclk(crtc_state);
8852
8853         /*
8854          * Returns a set of divisors for the desired target clock with the given
8855          * refclk, or FALSE.  The returned values represent the clock equation:
8856          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8857          */
8858         limit = intel_limit(crtc_state, refclk);
8859         ret = dev_priv->display.find_dpll(limit, crtc_state,
8860                                           crtc_state->port_clock,
8861                                           refclk, NULL, clock);
8862         if (!ret)
8863                 return false;
8864
8865         return true;
8866 }
8867
8868 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8869 {
8870         /*
8871          * Account for spread spectrum to avoid
8872          * oversubscribing the link. Max center spread
8873          * is 2.5%; use 5% for safety's sake.
8874          */
8875         u32 bps = target_clock * bpp * 21 / 20;
8876         return DIV_ROUND_UP(bps, link_bw * 8);
8877 }
8878
8879 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8880 {
8881         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8882 }
8883
8884 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8885                                       struct intel_crtc_state *crtc_state,
8886                                       u32 *fp,
8887                                       intel_clock_t *reduced_clock, u32 *fp2)
8888 {
8889         struct drm_crtc *crtc = &intel_crtc->base;
8890         struct drm_device *dev = crtc->dev;
8891         struct drm_i915_private *dev_priv = dev->dev_private;
8892         struct drm_atomic_state *state = crtc_state->base.state;
8893         struct drm_connector *connector;
8894         struct drm_connector_state *connector_state;
8895         struct intel_encoder *encoder;
8896         uint32_t dpll;
8897         int factor, num_connectors = 0, i;
8898         bool is_lvds = false, is_sdvo = false;
8899
8900         for_each_connector_in_state(state, connector, connector_state, i) {
8901                 if (connector_state->crtc != crtc_state->base.crtc)
8902                         continue;
8903
8904                 encoder = to_intel_encoder(connector_state->best_encoder);
8905
8906                 switch (encoder->type) {
8907                 case INTEL_OUTPUT_LVDS:
8908                         is_lvds = true;
8909                         break;
8910                 case INTEL_OUTPUT_SDVO:
8911                 case INTEL_OUTPUT_HDMI:
8912                         is_sdvo = true;
8913                         break;
8914                 default:
8915                         break;
8916                 }
8917
8918                 num_connectors++;
8919         }
8920
8921         /* Enable autotuning of the PLL clock (if permissible) */
8922         factor = 21;
8923         if (is_lvds) {
8924                 if ((intel_panel_use_ssc(dev_priv) &&
8925                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8926                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8927                         factor = 25;
8928         } else if (crtc_state->sdvo_tv_clock)
8929                 factor = 20;
8930
8931         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8932                 *fp |= FP_CB_TUNE;
8933
8934         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8935                 *fp2 |= FP_CB_TUNE;
8936
8937         dpll = 0;
8938
8939         if (is_lvds)
8940                 dpll |= DPLLB_MODE_LVDS;
8941         else
8942                 dpll |= DPLLB_MODE_DAC_SERIAL;
8943
8944         dpll |= (crtc_state->pixel_multiplier - 1)
8945                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8946
8947         if (is_sdvo)
8948                 dpll |= DPLL_SDVO_HIGH_SPEED;
8949         if (crtc_state->has_dp_encoder)
8950                 dpll |= DPLL_SDVO_HIGH_SPEED;
8951
8952         /* compute bitmask from p1 value */
8953         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8954         /* also FPA1 */
8955         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8956
8957         switch (crtc_state->dpll.p2) {
8958         case 5:
8959                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8960                 break;
8961         case 7:
8962                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8963                 break;
8964         case 10:
8965                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8966                 break;
8967         case 14:
8968                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8969                 break;
8970         }
8971
8972         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8973                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8974         else
8975                 dpll |= PLL_REF_INPUT_DREFCLK;
8976
8977         return dpll | DPLL_VCO_ENABLE;
8978 }
8979
8980 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8981                                        struct intel_crtc_state *crtc_state)
8982 {
8983         struct drm_device *dev = crtc->base.dev;
8984         intel_clock_t clock, reduced_clock;
8985         u32 dpll = 0, fp = 0, fp2 = 0;
8986         bool ok, has_reduced_clock = false;
8987         bool is_lvds = false;
8988         struct intel_shared_dpll *pll;
8989
8990         memset(&crtc_state->dpll_hw_state, 0,
8991                sizeof(crtc_state->dpll_hw_state));
8992
8993         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8994
8995         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8996              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8997
8998         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8999                                      &has_reduced_clock, &reduced_clock);
9000         if (!ok && !crtc_state->clock_set) {
9001                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9002                 return -EINVAL;
9003         }
9004         /* Compat-code for transition, will disappear. */
9005         if (!crtc_state->clock_set) {
9006                 crtc_state->dpll.n = clock.n;
9007                 crtc_state->dpll.m1 = clock.m1;
9008                 crtc_state->dpll.m2 = clock.m2;
9009                 crtc_state->dpll.p1 = clock.p1;
9010                 crtc_state->dpll.p2 = clock.p2;
9011         }
9012
9013         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9014         if (crtc_state->has_pch_encoder) {
9015                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9016                 if (has_reduced_clock)
9017                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9018
9019                 dpll = ironlake_compute_dpll(crtc, crtc_state,
9020                                              &fp, &reduced_clock,
9021                                              has_reduced_clock ? &fp2 : NULL);
9022
9023                 crtc_state->dpll_hw_state.dpll = dpll;
9024                 crtc_state->dpll_hw_state.fp0 = fp;
9025                 if (has_reduced_clock)
9026                         crtc_state->dpll_hw_state.fp1 = fp2;
9027                 else
9028                         crtc_state->dpll_hw_state.fp1 = fp;
9029
9030                 pll = intel_get_shared_dpll(crtc, crtc_state);
9031                 if (pll == NULL) {
9032                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9033                                          pipe_name(crtc->pipe));
9034                         return -EINVAL;
9035                 }
9036         }
9037
9038         if (is_lvds && has_reduced_clock)
9039                 crtc->lowfreq_avail = true;
9040         else
9041                 crtc->lowfreq_avail = false;
9042
9043         return 0;
9044 }
9045
9046 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9047                                          struct intel_link_m_n *m_n)
9048 {
9049         struct drm_device *dev = crtc->base.dev;
9050         struct drm_i915_private *dev_priv = dev->dev_private;
9051         enum pipe pipe = crtc->pipe;
9052
9053         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9054         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9055         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9056                 & ~TU_SIZE_MASK;
9057         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9058         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9059                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9060 }
9061
9062 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9063                                          enum transcoder transcoder,
9064                                          struct intel_link_m_n *m_n,
9065                                          struct intel_link_m_n *m2_n2)
9066 {
9067         struct drm_device *dev = crtc->base.dev;
9068         struct drm_i915_private *dev_priv = dev->dev_private;
9069         enum pipe pipe = crtc->pipe;
9070
9071         if (INTEL_INFO(dev)->gen >= 5) {
9072                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9073                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9074                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9075                         & ~TU_SIZE_MASK;
9076                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9077                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9078                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9079                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9080                  * gen < 8) and if DRRS is supported (to make sure the
9081                  * registers are not unnecessarily read).
9082                  */
9083                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9084                         crtc->config->has_drrs) {
9085                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9086                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9087                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9088                                         & ~TU_SIZE_MASK;
9089                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9090                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9091                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9092                 }
9093         } else {
9094                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9095                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9096                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9097                         & ~TU_SIZE_MASK;
9098                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9099                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9100                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9101         }
9102 }
9103
9104 void intel_dp_get_m_n(struct intel_crtc *crtc,
9105                       struct intel_crtc_state *pipe_config)
9106 {
9107         if (pipe_config->has_pch_encoder)
9108                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9109         else
9110                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9111                                              &pipe_config->dp_m_n,
9112                                              &pipe_config->dp_m2_n2);
9113 }
9114
9115 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9116                                         struct intel_crtc_state *pipe_config)
9117 {
9118         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9119                                      &pipe_config->fdi_m_n, NULL);
9120 }
9121
9122 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9123                                     struct intel_crtc_state *pipe_config)
9124 {
9125         struct drm_device *dev = crtc->base.dev;
9126         struct drm_i915_private *dev_priv = dev->dev_private;
9127         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9128         uint32_t ps_ctrl = 0;
9129         int id = -1;
9130         int i;
9131
9132         /* find scaler attached to this pipe */
9133         for (i = 0; i < crtc->num_scalers; i++) {
9134                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9135                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9136                         id = i;
9137                         pipe_config->pch_pfit.enabled = true;
9138                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9139                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9140                         break;
9141                 }
9142         }
9143
9144         scaler_state->scaler_id = id;
9145         if (id >= 0) {
9146                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9147         } else {
9148                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9149         }
9150 }
9151
9152 static void
9153 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9154                                  struct intel_initial_plane_config *plane_config)
9155 {
9156         struct drm_device *dev = crtc->base.dev;
9157         struct drm_i915_private *dev_priv = dev->dev_private;
9158         u32 val, base, offset, stride_mult, tiling;
9159         int pipe = crtc->pipe;
9160         int fourcc, pixel_format;
9161         unsigned int aligned_height;
9162         struct drm_framebuffer *fb;
9163         struct intel_framebuffer *intel_fb;
9164
9165         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9166         if (!intel_fb) {
9167                 DRM_DEBUG_KMS("failed to alloc fb\n");
9168                 return;
9169         }
9170
9171         fb = &intel_fb->base;
9172
9173         val = I915_READ(PLANE_CTL(pipe, 0));
9174         if (!(val & PLANE_CTL_ENABLE))
9175                 goto error;
9176
9177         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9178         fourcc = skl_format_to_fourcc(pixel_format,
9179                                       val & PLANE_CTL_ORDER_RGBX,
9180                                       val & PLANE_CTL_ALPHA_MASK);
9181         fb->pixel_format = fourcc;
9182         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9183
9184         tiling = val & PLANE_CTL_TILED_MASK;
9185         switch (tiling) {
9186         case PLANE_CTL_TILED_LINEAR:
9187                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9188                 break;
9189         case PLANE_CTL_TILED_X:
9190                 plane_config->tiling = I915_TILING_X;
9191                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9192                 break;
9193         case PLANE_CTL_TILED_Y:
9194                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9195                 break;
9196         case PLANE_CTL_TILED_YF:
9197                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9198                 break;
9199         default:
9200                 MISSING_CASE(tiling);
9201                 goto error;
9202         }
9203
9204         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9205         plane_config->base = base;
9206
9207         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9208
9209         val = I915_READ(PLANE_SIZE(pipe, 0));
9210         fb->height = ((val >> 16) & 0xfff) + 1;
9211         fb->width = ((val >> 0) & 0x1fff) + 1;
9212
9213         val = I915_READ(PLANE_STRIDE(pipe, 0));
9214         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9215                                                 fb->pixel_format);
9216         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9217
9218         aligned_height = intel_fb_align_height(dev, fb->height,
9219                                                fb->pixel_format,
9220                                                fb->modifier[0]);
9221
9222         plane_config->size = fb->pitches[0] * aligned_height;
9223
9224         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9225                       pipe_name(pipe), fb->width, fb->height,
9226                       fb->bits_per_pixel, base, fb->pitches[0],
9227                       plane_config->size);
9228
9229         plane_config->fb = intel_fb;
9230         return;
9231
9232 error:
9233         kfree(fb);
9234 }
9235
9236 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9237                                      struct intel_crtc_state *pipe_config)
9238 {
9239         struct drm_device *dev = crtc->base.dev;
9240         struct drm_i915_private *dev_priv = dev->dev_private;
9241         uint32_t tmp;
9242
9243         tmp = I915_READ(PF_CTL(crtc->pipe));
9244
9245         if (tmp & PF_ENABLE) {
9246                 pipe_config->pch_pfit.enabled = true;
9247                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9248                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9249
9250                 /* We currently do not free assignements of panel fitters on
9251                  * ivb/hsw (since we don't use the higher upscaling modes which
9252                  * differentiates them) so just WARN about this case for now. */
9253                 if (IS_GEN7(dev)) {
9254                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9255                                 PF_PIPE_SEL_IVB(crtc->pipe));
9256                 }
9257         }
9258 }
9259
9260 static void
9261 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9262                                   struct intel_initial_plane_config *plane_config)
9263 {
9264         struct drm_device *dev = crtc->base.dev;
9265         struct drm_i915_private *dev_priv = dev->dev_private;
9266         u32 val, base, offset;
9267         int pipe = crtc->pipe;
9268         int fourcc, pixel_format;
9269         unsigned int aligned_height;
9270         struct drm_framebuffer *fb;
9271         struct intel_framebuffer *intel_fb;
9272
9273         val = I915_READ(DSPCNTR(pipe));
9274         if (!(val & DISPLAY_PLANE_ENABLE))
9275                 return;
9276
9277         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9278         if (!intel_fb) {
9279                 DRM_DEBUG_KMS("failed to alloc fb\n");
9280                 return;
9281         }
9282
9283         fb = &intel_fb->base;
9284
9285         if (INTEL_INFO(dev)->gen >= 4) {
9286                 if (val & DISPPLANE_TILED) {
9287                         plane_config->tiling = I915_TILING_X;
9288                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9289                 }
9290         }
9291
9292         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9293         fourcc = i9xx_format_to_fourcc(pixel_format);
9294         fb->pixel_format = fourcc;
9295         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9296
9297         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9298         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9299                 offset = I915_READ(DSPOFFSET(pipe));
9300         } else {
9301                 if (plane_config->tiling)
9302                         offset = I915_READ(DSPTILEOFF(pipe));
9303                 else
9304                         offset = I915_READ(DSPLINOFF(pipe));
9305         }
9306         plane_config->base = base;
9307
9308         val = I915_READ(PIPESRC(pipe));
9309         fb->width = ((val >> 16) & 0xfff) + 1;
9310         fb->height = ((val >> 0) & 0xfff) + 1;
9311
9312         val = I915_READ(DSPSTRIDE(pipe));
9313         fb->pitches[0] = val & 0xffffffc0;
9314
9315         aligned_height = intel_fb_align_height(dev, fb->height,
9316                                                fb->pixel_format,
9317                                                fb->modifier[0]);
9318
9319         plane_config->size = fb->pitches[0] * aligned_height;
9320
9321         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9322                       pipe_name(pipe), fb->width, fb->height,
9323                       fb->bits_per_pixel, base, fb->pitches[0],
9324                       plane_config->size);
9325
9326         plane_config->fb = intel_fb;
9327 }
9328
9329 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9330                                      struct intel_crtc_state *pipe_config)
9331 {
9332         struct drm_device *dev = crtc->base.dev;
9333         struct drm_i915_private *dev_priv = dev->dev_private;
9334         enum intel_display_power_domain power_domain;
9335         uint32_t tmp;
9336         bool ret;
9337
9338         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9339         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9340                 return false;
9341
9342         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9343         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9344
9345         ret = false;
9346         tmp = I915_READ(PIPECONF(crtc->pipe));
9347         if (!(tmp & PIPECONF_ENABLE))
9348                 goto out;
9349
9350         switch (tmp & PIPECONF_BPC_MASK) {
9351         case PIPECONF_6BPC:
9352                 pipe_config->pipe_bpp = 18;
9353                 break;
9354         case PIPECONF_8BPC:
9355                 pipe_config->pipe_bpp = 24;
9356                 break;
9357         case PIPECONF_10BPC:
9358                 pipe_config->pipe_bpp = 30;
9359                 break;
9360         case PIPECONF_12BPC:
9361                 pipe_config->pipe_bpp = 36;
9362                 break;
9363         default:
9364                 break;
9365         }
9366
9367         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9368                 pipe_config->limited_color_range = true;
9369
9370         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9371                 struct intel_shared_dpll *pll;
9372
9373                 pipe_config->has_pch_encoder = true;
9374
9375                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9376                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9377                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9378
9379                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9380
9381                 if (HAS_PCH_IBX(dev_priv->dev)) {
9382                         pipe_config->shared_dpll =
9383                                 (enum intel_dpll_id) crtc->pipe;
9384                 } else {
9385                         tmp = I915_READ(PCH_DPLL_SEL);
9386                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9387                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9388                         else
9389                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9390                 }
9391
9392                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9393
9394                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9395                                            &pipe_config->dpll_hw_state));
9396
9397                 tmp = pipe_config->dpll_hw_state.dpll;
9398                 pipe_config->pixel_multiplier =
9399                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9400                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9401
9402                 ironlake_pch_clock_get(crtc, pipe_config);
9403         } else {
9404                 pipe_config->pixel_multiplier = 1;
9405         }
9406
9407         intel_get_pipe_timings(crtc, pipe_config);
9408
9409         ironlake_get_pfit_config(crtc, pipe_config);
9410
9411         ret = true;
9412
9413 out:
9414         intel_display_power_put(dev_priv, power_domain);
9415
9416         return ret;
9417 }
9418
9419 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9420 {
9421         struct drm_device *dev = dev_priv->dev;
9422         struct intel_crtc *crtc;
9423
9424         for_each_intel_crtc(dev, crtc)
9425                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9426                      pipe_name(crtc->pipe));
9427
9428         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9429         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9430         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9431         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9432         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9433         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9434              "CPU PWM1 enabled\n");
9435         if (IS_HASWELL(dev))
9436                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9437                      "CPU PWM2 enabled\n");
9438         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9439              "PCH PWM1 enabled\n");
9440         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9441              "Utility pin enabled\n");
9442         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9443
9444         /*
9445          * In theory we can still leave IRQs enabled, as long as only the HPD
9446          * interrupts remain enabled. We used to check for that, but since it's
9447          * gen-specific and since we only disable LCPLL after we fully disable
9448          * the interrupts, the check below should be enough.
9449          */
9450         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9451 }
9452
9453 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9454 {
9455         struct drm_device *dev = dev_priv->dev;
9456
9457         if (IS_HASWELL(dev))
9458                 return I915_READ(D_COMP_HSW);
9459         else
9460                 return I915_READ(D_COMP_BDW);
9461 }
9462
9463 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9464 {
9465         struct drm_device *dev = dev_priv->dev;
9466
9467         if (IS_HASWELL(dev)) {
9468                 mutex_lock(&dev_priv->rps.hw_lock);
9469                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9470                                             val))
9471                         DRM_ERROR("Failed to write to D_COMP\n");
9472                 mutex_unlock(&dev_priv->rps.hw_lock);
9473         } else {
9474                 I915_WRITE(D_COMP_BDW, val);
9475                 POSTING_READ(D_COMP_BDW);
9476         }
9477 }
9478
9479 /*
9480  * This function implements pieces of two sequences from BSpec:
9481  * - Sequence for display software to disable LCPLL
9482  * - Sequence for display software to allow package C8+
9483  * The steps implemented here are just the steps that actually touch the LCPLL
9484  * register. Callers should take care of disabling all the display engine
9485  * functions, doing the mode unset, fixing interrupts, etc.
9486  */
9487 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9488                               bool switch_to_fclk, bool allow_power_down)
9489 {
9490         uint32_t val;
9491
9492         assert_can_disable_lcpll(dev_priv);
9493
9494         val = I915_READ(LCPLL_CTL);
9495
9496         if (switch_to_fclk) {
9497                 val |= LCPLL_CD_SOURCE_FCLK;
9498                 I915_WRITE(LCPLL_CTL, val);
9499
9500                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9501                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9502                         DRM_ERROR("Switching to FCLK failed\n");
9503
9504                 val = I915_READ(LCPLL_CTL);
9505         }
9506
9507         val |= LCPLL_PLL_DISABLE;
9508         I915_WRITE(LCPLL_CTL, val);
9509         POSTING_READ(LCPLL_CTL);
9510
9511         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9512                 DRM_ERROR("LCPLL still locked\n");
9513
9514         val = hsw_read_dcomp(dev_priv);
9515         val |= D_COMP_COMP_DISABLE;
9516         hsw_write_dcomp(dev_priv, val);
9517         ndelay(100);
9518
9519         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9520                      1))
9521                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9522
9523         if (allow_power_down) {
9524                 val = I915_READ(LCPLL_CTL);
9525                 val |= LCPLL_POWER_DOWN_ALLOW;
9526                 I915_WRITE(LCPLL_CTL, val);
9527                 POSTING_READ(LCPLL_CTL);
9528         }
9529 }
9530
9531 /*
9532  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9533  * source.
9534  */
9535 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9536 {
9537         uint32_t val;
9538
9539         val = I915_READ(LCPLL_CTL);
9540
9541         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9542                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9543                 return;
9544
9545         /*
9546          * Make sure we're not on PC8 state before disabling PC8, otherwise
9547          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9548          */
9549         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9550
9551         if (val & LCPLL_POWER_DOWN_ALLOW) {
9552                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9553                 I915_WRITE(LCPLL_CTL, val);
9554                 POSTING_READ(LCPLL_CTL);
9555         }
9556
9557         val = hsw_read_dcomp(dev_priv);
9558         val |= D_COMP_COMP_FORCE;
9559         val &= ~D_COMP_COMP_DISABLE;
9560         hsw_write_dcomp(dev_priv, val);
9561
9562         val = I915_READ(LCPLL_CTL);
9563         val &= ~LCPLL_PLL_DISABLE;
9564         I915_WRITE(LCPLL_CTL, val);
9565
9566         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9567                 DRM_ERROR("LCPLL not locked yet\n");
9568
9569         if (val & LCPLL_CD_SOURCE_FCLK) {
9570                 val = I915_READ(LCPLL_CTL);
9571                 val &= ~LCPLL_CD_SOURCE_FCLK;
9572                 I915_WRITE(LCPLL_CTL, val);
9573
9574                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9575                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9576                         DRM_ERROR("Switching back to LCPLL failed\n");
9577         }
9578
9579         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9580         intel_update_cdclk(dev_priv->dev);
9581 }
9582
9583 /*
9584  * Package states C8 and deeper are really deep PC states that can only be
9585  * reached when all the devices on the system allow it, so even if the graphics
9586  * device allows PC8+, it doesn't mean the system will actually get to these
9587  * states. Our driver only allows PC8+ when going into runtime PM.
9588  *
9589  * The requirements for PC8+ are that all the outputs are disabled, the power
9590  * well is disabled and most interrupts are disabled, and these are also
9591  * requirements for runtime PM. When these conditions are met, we manually do
9592  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9593  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9594  * hang the machine.
9595  *
9596  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9597  * the state of some registers, so when we come back from PC8+ we need to
9598  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9599  * need to take care of the registers kept by RC6. Notice that this happens even
9600  * if we don't put the device in PCI D3 state (which is what currently happens
9601  * because of the runtime PM support).
9602  *
9603  * For more, read "Display Sequences for Package C8" on the hardware
9604  * documentation.
9605  */
9606 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9607 {
9608         struct drm_device *dev = dev_priv->dev;
9609         uint32_t val;
9610
9611         DRM_DEBUG_KMS("Enabling package C8+\n");
9612
9613         if (HAS_PCH_LPT_LP(dev)) {
9614                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9615                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9616                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9617         }
9618
9619         lpt_disable_clkout_dp(dev);
9620         hsw_disable_lcpll(dev_priv, true, true);
9621 }
9622
9623 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9624 {
9625         struct drm_device *dev = dev_priv->dev;
9626         uint32_t val;
9627
9628         DRM_DEBUG_KMS("Disabling package C8+\n");
9629
9630         hsw_restore_lcpll(dev_priv);
9631         lpt_init_pch_refclk(dev);
9632
9633         if (HAS_PCH_LPT_LP(dev)) {
9634                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9635                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9636                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9637         }
9638 }
9639
9640 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9641 {
9642         struct drm_device *dev = old_state->dev;
9643         struct intel_atomic_state *old_intel_state =
9644                 to_intel_atomic_state(old_state);
9645         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9646
9647         broxton_set_cdclk(dev, req_cdclk);
9648 }
9649
9650 /* compute the max rate for new configuration */
9651 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9652 {
9653         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9654         struct drm_i915_private *dev_priv = state->dev->dev_private;
9655         struct drm_crtc *crtc;
9656         struct drm_crtc_state *cstate;
9657         struct intel_crtc_state *crtc_state;
9658         unsigned max_pixel_rate = 0, i;
9659         enum pipe pipe;
9660
9661         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9662                sizeof(intel_state->min_pixclk));
9663
9664         for_each_crtc_in_state(state, crtc, cstate, i) {
9665                 int pixel_rate;
9666
9667                 crtc_state = to_intel_crtc_state(cstate);
9668                 if (!crtc_state->base.enable) {
9669                         intel_state->min_pixclk[i] = 0;
9670                         continue;
9671                 }
9672
9673                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9674
9675                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9676                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9677                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9678
9679                 intel_state->min_pixclk[i] = pixel_rate;
9680         }
9681
9682         for_each_pipe(dev_priv, pipe)
9683                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9684
9685         return max_pixel_rate;
9686 }
9687
9688 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9689 {
9690         struct drm_i915_private *dev_priv = dev->dev_private;
9691         uint32_t val, data;
9692         int ret;
9693
9694         if (WARN((I915_READ(LCPLL_CTL) &
9695                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9696                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9697                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9698                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9699                  "trying to change cdclk frequency with cdclk not enabled\n"))
9700                 return;
9701
9702         mutex_lock(&dev_priv->rps.hw_lock);
9703         ret = sandybridge_pcode_write(dev_priv,
9704                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9705         mutex_unlock(&dev_priv->rps.hw_lock);
9706         if (ret) {
9707                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9708                 return;
9709         }
9710
9711         val = I915_READ(LCPLL_CTL);
9712         val |= LCPLL_CD_SOURCE_FCLK;
9713         I915_WRITE(LCPLL_CTL, val);
9714
9715         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9716                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9717                 DRM_ERROR("Switching to FCLK failed\n");
9718
9719         val = I915_READ(LCPLL_CTL);
9720         val &= ~LCPLL_CLK_FREQ_MASK;
9721
9722         switch (cdclk) {
9723         case 450000:
9724                 val |= LCPLL_CLK_FREQ_450;
9725                 data = 0;
9726                 break;
9727         case 540000:
9728                 val |= LCPLL_CLK_FREQ_54O_BDW;
9729                 data = 1;
9730                 break;
9731         case 337500:
9732                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9733                 data = 2;
9734                 break;
9735         case 675000:
9736                 val |= LCPLL_CLK_FREQ_675_BDW;
9737                 data = 3;
9738                 break;
9739         default:
9740                 WARN(1, "invalid cdclk frequency\n");
9741                 return;
9742         }
9743
9744         I915_WRITE(LCPLL_CTL, val);
9745
9746         val = I915_READ(LCPLL_CTL);
9747         val &= ~LCPLL_CD_SOURCE_FCLK;
9748         I915_WRITE(LCPLL_CTL, val);
9749
9750         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9751                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9752                 DRM_ERROR("Switching back to LCPLL failed\n");
9753
9754         mutex_lock(&dev_priv->rps.hw_lock);
9755         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9756         mutex_unlock(&dev_priv->rps.hw_lock);
9757
9758         intel_update_cdclk(dev);
9759
9760         WARN(cdclk != dev_priv->cdclk_freq,
9761              "cdclk requested %d kHz but got %d kHz\n",
9762              cdclk, dev_priv->cdclk_freq);
9763 }
9764
9765 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9766 {
9767         struct drm_i915_private *dev_priv = to_i915(state->dev);
9768         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9769         int max_pixclk = ilk_max_pixel_rate(state);
9770         int cdclk;
9771
9772         /*
9773          * FIXME should also account for plane ratio
9774          * once 64bpp pixel formats are supported.
9775          */
9776         if (max_pixclk > 540000)
9777                 cdclk = 675000;
9778         else if (max_pixclk > 450000)
9779                 cdclk = 540000;
9780         else if (max_pixclk > 337500)
9781                 cdclk = 450000;
9782         else
9783                 cdclk = 337500;
9784
9785         if (cdclk > dev_priv->max_cdclk_freq) {
9786                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9787                               cdclk, dev_priv->max_cdclk_freq);
9788                 return -EINVAL;
9789         }
9790
9791         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9792         if (!intel_state->active_crtcs)
9793                 intel_state->dev_cdclk = 337500;
9794
9795         return 0;
9796 }
9797
9798 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9799 {
9800         struct drm_device *dev = old_state->dev;
9801         struct intel_atomic_state *old_intel_state =
9802                 to_intel_atomic_state(old_state);
9803         unsigned req_cdclk = old_intel_state->dev_cdclk;
9804
9805         broadwell_set_cdclk(dev, req_cdclk);
9806 }
9807
9808 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9809                                       struct intel_crtc_state *crtc_state)
9810 {
9811         struct intel_encoder *intel_encoder =
9812                 intel_ddi_get_crtc_new_encoder(crtc_state);
9813
9814         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9815                 if (!intel_ddi_pll_select(crtc, crtc_state))
9816                         return -EINVAL;
9817         }
9818
9819         crtc->lowfreq_avail = false;
9820
9821         return 0;
9822 }
9823
9824 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9825                                 enum port port,
9826                                 struct intel_crtc_state *pipe_config)
9827 {
9828         switch (port) {
9829         case PORT_A:
9830                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9831                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9832                 break;
9833         case PORT_B:
9834                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9835                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9836                 break;
9837         case PORT_C:
9838                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9839                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9840                 break;
9841         default:
9842                 DRM_ERROR("Incorrect port type\n");
9843         }
9844 }
9845
9846 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9847                                 enum port port,
9848                                 struct intel_crtc_state *pipe_config)
9849 {
9850         u32 temp, dpll_ctl1;
9851
9852         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9853         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9854
9855         switch (pipe_config->ddi_pll_sel) {
9856         case SKL_DPLL0:
9857                 /*
9858                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9859                  * of the shared DPLL framework and thus needs to be read out
9860                  * separately
9861                  */
9862                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9863                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9864                 break;
9865         case SKL_DPLL1:
9866                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9867                 break;
9868         case SKL_DPLL2:
9869                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9870                 break;
9871         case SKL_DPLL3:
9872                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9873                 break;
9874         }
9875 }
9876
9877 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9878                                 enum port port,
9879                                 struct intel_crtc_state *pipe_config)
9880 {
9881         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9882
9883         switch (pipe_config->ddi_pll_sel) {
9884         case PORT_CLK_SEL_WRPLL1:
9885                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9886                 break;
9887         case PORT_CLK_SEL_WRPLL2:
9888                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9889                 break;
9890         case PORT_CLK_SEL_SPLL:
9891                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9892                 break;
9893         }
9894 }
9895
9896 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9897                                        struct intel_crtc_state *pipe_config)
9898 {
9899         struct drm_device *dev = crtc->base.dev;
9900         struct drm_i915_private *dev_priv = dev->dev_private;
9901         struct intel_shared_dpll *pll;
9902         enum port port;
9903         uint32_t tmp;
9904
9905         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9906
9907         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9908
9909         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9910                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9911         else if (IS_BROXTON(dev))
9912                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9913         else
9914                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9915
9916         if (pipe_config->shared_dpll >= 0) {
9917                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9918
9919                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9920                                            &pipe_config->dpll_hw_state));
9921         }
9922
9923         /*
9924          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9925          * DDI E. So just check whether this pipe is wired to DDI E and whether
9926          * the PCH transcoder is on.
9927          */
9928         if (INTEL_INFO(dev)->gen < 9 &&
9929             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9930                 pipe_config->has_pch_encoder = true;
9931
9932                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9933                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9934                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9935
9936                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9937         }
9938 }
9939
9940 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9941                                     struct intel_crtc_state *pipe_config)
9942 {
9943         struct drm_device *dev = crtc->base.dev;
9944         struct drm_i915_private *dev_priv = dev->dev_private;
9945         enum intel_display_power_domain power_domain;
9946         unsigned long power_domain_mask;
9947         uint32_t tmp;
9948         bool ret;
9949
9950         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9951         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9952                 return false;
9953         power_domain_mask = BIT(power_domain);
9954
9955         ret = false;
9956
9957         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9958         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9959
9960         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9961         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9962                 enum pipe trans_edp_pipe;
9963                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9964                 default:
9965                         WARN(1, "unknown pipe linked to edp transcoder\n");
9966                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9967                 case TRANS_DDI_EDP_INPUT_A_ON:
9968                         trans_edp_pipe = PIPE_A;
9969                         break;
9970                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9971                         trans_edp_pipe = PIPE_B;
9972                         break;
9973                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9974                         trans_edp_pipe = PIPE_C;
9975                         break;
9976                 }
9977
9978                 if (trans_edp_pipe == crtc->pipe)
9979                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9980         }
9981
9982         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9983         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9984                 goto out;
9985         power_domain_mask |= BIT(power_domain);
9986
9987         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9988         if (!(tmp & PIPECONF_ENABLE))
9989                 goto out;
9990
9991         haswell_get_ddi_port_state(crtc, pipe_config);
9992
9993         intel_get_pipe_timings(crtc, pipe_config);
9994
9995         if (INTEL_INFO(dev)->gen >= 9) {
9996                 skl_init_scalers(dev, crtc, pipe_config);
9997         }
9998
9999         if (INTEL_INFO(dev)->gen >= 9) {
10000                 pipe_config->scaler_state.scaler_id = -1;
10001                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10002         }
10003
10004         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10005         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10006                 power_domain_mask |= BIT(power_domain);
10007                 if (INTEL_INFO(dev)->gen >= 9)
10008                         skylake_get_pfit_config(crtc, pipe_config);
10009                 else
10010                         ironlake_get_pfit_config(crtc, pipe_config);
10011         }
10012
10013         if (IS_HASWELL(dev))
10014                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10015                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10016
10017         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10018                 pipe_config->pixel_multiplier =
10019                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10020         } else {
10021                 pipe_config->pixel_multiplier = 1;
10022         }
10023
10024         ret = true;
10025
10026 out:
10027         for_each_power_domain(power_domain, power_domain_mask)
10028                 intel_display_power_put(dev_priv, power_domain);
10029
10030         return ret;
10031 }
10032
10033 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10034                                const struct intel_plane_state *plane_state)
10035 {
10036         struct drm_device *dev = crtc->dev;
10037         struct drm_i915_private *dev_priv = dev->dev_private;
10038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10039         uint32_t cntl = 0, size = 0;
10040
10041         if (plane_state && plane_state->visible) {
10042                 unsigned int width = plane_state->base.crtc_w;
10043                 unsigned int height = plane_state->base.crtc_h;
10044                 unsigned int stride = roundup_pow_of_two(width) * 4;
10045
10046                 switch (stride) {
10047                 default:
10048                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10049                                   width, stride);
10050                         stride = 256;
10051                         /* fallthrough */
10052                 case 256:
10053                 case 512:
10054                 case 1024:
10055                 case 2048:
10056                         break;
10057                 }
10058
10059                 cntl |= CURSOR_ENABLE |
10060                         CURSOR_GAMMA_ENABLE |
10061                         CURSOR_FORMAT_ARGB |
10062                         CURSOR_STRIDE(stride);
10063
10064                 size = (height << 12) | width;
10065         }
10066
10067         if (intel_crtc->cursor_cntl != 0 &&
10068             (intel_crtc->cursor_base != base ||
10069              intel_crtc->cursor_size != size ||
10070              intel_crtc->cursor_cntl != cntl)) {
10071                 /* On these chipsets we can only modify the base/size/stride
10072                  * whilst the cursor is disabled.
10073                  */
10074                 I915_WRITE(CURCNTR(PIPE_A), 0);
10075                 POSTING_READ(CURCNTR(PIPE_A));
10076                 intel_crtc->cursor_cntl = 0;
10077         }
10078
10079         if (intel_crtc->cursor_base != base) {
10080                 I915_WRITE(CURBASE(PIPE_A), base);
10081                 intel_crtc->cursor_base = base;
10082         }
10083
10084         if (intel_crtc->cursor_size != size) {
10085                 I915_WRITE(CURSIZE, size);
10086                 intel_crtc->cursor_size = size;
10087         }
10088
10089         if (intel_crtc->cursor_cntl != cntl) {
10090                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10091                 POSTING_READ(CURCNTR(PIPE_A));
10092                 intel_crtc->cursor_cntl = cntl;
10093         }
10094 }
10095
10096 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10097                                const struct intel_plane_state *plane_state)
10098 {
10099         struct drm_device *dev = crtc->dev;
10100         struct drm_i915_private *dev_priv = dev->dev_private;
10101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10102         int pipe = intel_crtc->pipe;
10103         uint32_t cntl = 0;
10104
10105         if (plane_state && plane_state->visible) {
10106                 cntl = MCURSOR_GAMMA_ENABLE;
10107                 switch (plane_state->base.crtc_w) {
10108                         case 64:
10109                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10110                                 break;
10111                         case 128:
10112                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10113                                 break;
10114                         case 256:
10115                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10116                                 break;
10117                         default:
10118                                 MISSING_CASE(plane_state->base.crtc_w);
10119                                 return;
10120                 }
10121                 cntl |= pipe << 28; /* Connect to correct pipe */
10122
10123                 if (HAS_DDI(dev))
10124                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10125
10126                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10127                         cntl |= CURSOR_ROTATE_180;
10128         }
10129
10130         if (intel_crtc->cursor_cntl != cntl) {
10131                 I915_WRITE(CURCNTR(pipe), cntl);
10132                 POSTING_READ(CURCNTR(pipe));
10133                 intel_crtc->cursor_cntl = cntl;
10134         }
10135
10136         /* and commit changes on next vblank */
10137         I915_WRITE(CURBASE(pipe), base);
10138         POSTING_READ(CURBASE(pipe));
10139
10140         intel_crtc->cursor_base = base;
10141 }
10142
10143 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10144 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10145                                      const struct intel_plane_state *plane_state)
10146 {
10147         struct drm_device *dev = crtc->dev;
10148         struct drm_i915_private *dev_priv = dev->dev_private;
10149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10150         int pipe = intel_crtc->pipe;
10151         u32 base = intel_crtc->cursor_addr;
10152         u32 pos = 0;
10153
10154         if (plane_state) {
10155                 int x = plane_state->base.crtc_x;
10156                 int y = plane_state->base.crtc_y;
10157
10158                 if (x < 0) {
10159                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10160                         x = -x;
10161                 }
10162                 pos |= x << CURSOR_X_SHIFT;
10163
10164                 if (y < 0) {
10165                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10166                         y = -y;
10167                 }
10168                 pos |= y << CURSOR_Y_SHIFT;
10169
10170                 /* ILK+ do this automagically */
10171                 if (HAS_GMCH_DISPLAY(dev) &&
10172                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10173                         base += (plane_state->base.crtc_h *
10174                                  plane_state->base.crtc_w - 1) * 4;
10175                 }
10176         }
10177
10178         I915_WRITE(CURPOS(pipe), pos);
10179
10180         if (IS_845G(dev) || IS_I865G(dev))
10181                 i845_update_cursor(crtc, base, plane_state);
10182         else
10183                 i9xx_update_cursor(crtc, base, plane_state);
10184 }
10185
10186 static bool cursor_size_ok(struct drm_device *dev,
10187                            uint32_t width, uint32_t height)
10188 {
10189         if (width == 0 || height == 0)
10190                 return false;
10191
10192         /*
10193          * 845g/865g are special in that they are only limited by
10194          * the width of their cursors, the height is arbitrary up to
10195          * the precision of the register. Everything else requires
10196          * square cursors, limited to a few power-of-two sizes.
10197          */
10198         if (IS_845G(dev) || IS_I865G(dev)) {
10199                 if ((width & 63) != 0)
10200                         return false;
10201
10202                 if (width > (IS_845G(dev) ? 64 : 512))
10203                         return false;
10204
10205                 if (height > 1023)
10206                         return false;
10207         } else {
10208                 switch (width | height) {
10209                 case 256:
10210                 case 128:
10211                         if (IS_GEN2(dev))
10212                                 return false;
10213                 case 64:
10214                         break;
10215                 default:
10216                         return false;
10217                 }
10218         }
10219
10220         return true;
10221 }
10222
10223 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10224                                  u16 *blue, uint32_t start, uint32_t size)
10225 {
10226         int end = (start + size > 256) ? 256 : start + size, i;
10227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10228
10229         for (i = start; i < end; i++) {
10230                 intel_crtc->lut_r[i] = red[i] >> 8;
10231                 intel_crtc->lut_g[i] = green[i] >> 8;
10232                 intel_crtc->lut_b[i] = blue[i] >> 8;
10233         }
10234
10235         intel_crtc_load_lut(crtc);
10236 }
10237
10238 /* VESA 640x480x72Hz mode to set on the pipe */
10239 static struct drm_display_mode load_detect_mode = {
10240         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10241                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10242 };
10243
10244 struct drm_framebuffer *
10245 __intel_framebuffer_create(struct drm_device *dev,
10246                            struct drm_mode_fb_cmd2 *mode_cmd,
10247                            struct drm_i915_gem_object *obj)
10248 {
10249         struct intel_framebuffer *intel_fb;
10250         int ret;
10251
10252         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10253         if (!intel_fb)
10254                 return ERR_PTR(-ENOMEM);
10255
10256         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10257         if (ret)
10258                 goto err;
10259
10260         return &intel_fb->base;
10261
10262 err:
10263         kfree(intel_fb);
10264         return ERR_PTR(ret);
10265 }
10266
10267 static struct drm_framebuffer *
10268 intel_framebuffer_create(struct drm_device *dev,
10269                          struct drm_mode_fb_cmd2 *mode_cmd,
10270                          struct drm_i915_gem_object *obj)
10271 {
10272         struct drm_framebuffer *fb;
10273         int ret;
10274
10275         ret = i915_mutex_lock_interruptible(dev);
10276         if (ret)
10277                 return ERR_PTR(ret);
10278         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10279         mutex_unlock(&dev->struct_mutex);
10280
10281         return fb;
10282 }
10283
10284 static u32
10285 intel_framebuffer_pitch_for_width(int width, int bpp)
10286 {
10287         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10288         return ALIGN(pitch, 64);
10289 }
10290
10291 static u32
10292 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10293 {
10294         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10295         return PAGE_ALIGN(pitch * mode->vdisplay);
10296 }
10297
10298 static struct drm_framebuffer *
10299 intel_framebuffer_create_for_mode(struct drm_device *dev,
10300                                   struct drm_display_mode *mode,
10301                                   int depth, int bpp)
10302 {
10303         struct drm_framebuffer *fb;
10304         struct drm_i915_gem_object *obj;
10305         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10306
10307         obj = i915_gem_alloc_object(dev,
10308                                     intel_framebuffer_size_for_mode(mode, bpp));
10309         if (obj == NULL)
10310                 return ERR_PTR(-ENOMEM);
10311
10312         mode_cmd.width = mode->hdisplay;
10313         mode_cmd.height = mode->vdisplay;
10314         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10315                                                                 bpp);
10316         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10317
10318         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10319         if (IS_ERR(fb))
10320                 drm_gem_object_unreference_unlocked(&obj->base);
10321
10322         return fb;
10323 }
10324
10325 static struct drm_framebuffer *
10326 mode_fits_in_fbdev(struct drm_device *dev,
10327                    struct drm_display_mode *mode)
10328 {
10329 #ifdef CONFIG_DRM_FBDEV_EMULATION
10330         struct drm_i915_private *dev_priv = dev->dev_private;
10331         struct drm_i915_gem_object *obj;
10332         struct drm_framebuffer *fb;
10333
10334         if (!dev_priv->fbdev)
10335                 return NULL;
10336
10337         if (!dev_priv->fbdev->fb)
10338                 return NULL;
10339
10340         obj = dev_priv->fbdev->fb->obj;
10341         BUG_ON(!obj);
10342
10343         fb = &dev_priv->fbdev->fb->base;
10344         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10345                                                                fb->bits_per_pixel))
10346                 return NULL;
10347
10348         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10349                 return NULL;
10350
10351         drm_framebuffer_reference(fb);
10352         return fb;
10353 #else
10354         return NULL;
10355 #endif
10356 }
10357
10358 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10359                                            struct drm_crtc *crtc,
10360                                            struct drm_display_mode *mode,
10361                                            struct drm_framebuffer *fb,
10362                                            int x, int y)
10363 {
10364         struct drm_plane_state *plane_state;
10365         int hdisplay, vdisplay;
10366         int ret;
10367
10368         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10369         if (IS_ERR(plane_state))
10370                 return PTR_ERR(plane_state);
10371
10372         if (mode)
10373                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10374         else
10375                 hdisplay = vdisplay = 0;
10376
10377         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10378         if (ret)
10379                 return ret;
10380         drm_atomic_set_fb_for_plane(plane_state, fb);
10381         plane_state->crtc_x = 0;
10382         plane_state->crtc_y = 0;
10383         plane_state->crtc_w = hdisplay;
10384         plane_state->crtc_h = vdisplay;
10385         plane_state->src_x = x << 16;
10386         plane_state->src_y = y << 16;
10387         plane_state->src_w = hdisplay << 16;
10388         plane_state->src_h = vdisplay << 16;
10389
10390         return 0;
10391 }
10392
10393 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10394                                 struct drm_display_mode *mode,
10395                                 struct intel_load_detect_pipe *old,
10396                                 struct drm_modeset_acquire_ctx *ctx)
10397 {
10398         struct intel_crtc *intel_crtc;
10399         struct intel_encoder *intel_encoder =
10400                 intel_attached_encoder(connector);
10401         struct drm_crtc *possible_crtc;
10402         struct drm_encoder *encoder = &intel_encoder->base;
10403         struct drm_crtc *crtc = NULL;
10404         struct drm_device *dev = encoder->dev;
10405         struct drm_framebuffer *fb;
10406         struct drm_mode_config *config = &dev->mode_config;
10407         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10408         struct drm_connector_state *connector_state;
10409         struct intel_crtc_state *crtc_state;
10410         int ret, i = -1;
10411
10412         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10413                       connector->base.id, connector->name,
10414                       encoder->base.id, encoder->name);
10415
10416         old->restore_state = NULL;
10417
10418 retry:
10419         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10420         if (ret)
10421                 goto fail;
10422
10423         /*
10424          * Algorithm gets a little messy:
10425          *
10426          *   - if the connector already has an assigned crtc, use it (but make
10427          *     sure it's on first)
10428          *
10429          *   - try to find the first unused crtc that can drive this connector,
10430          *     and use that if we find one
10431          */
10432
10433         /* See if we already have a CRTC for this connector */
10434         if (connector->state->crtc) {
10435                 crtc = connector->state->crtc;
10436
10437                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10438                 if (ret)
10439                         goto fail;
10440
10441                 /* Make sure the crtc and connector are running */
10442                 goto found;
10443         }
10444
10445         /* Find an unused one (if possible) */
10446         for_each_crtc(dev, possible_crtc) {
10447                 i++;
10448                 if (!(encoder->possible_crtcs & (1 << i)))
10449                         continue;
10450
10451                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10452                 if (ret)
10453                         goto fail;
10454
10455                 if (possible_crtc->state->enable) {
10456                         drm_modeset_unlock(&possible_crtc->mutex);
10457                         continue;
10458                 }
10459
10460                 crtc = possible_crtc;
10461                 break;
10462         }
10463
10464         /*
10465          * If we didn't find an unused CRTC, don't use any.
10466          */
10467         if (!crtc) {
10468                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10469                 goto fail;
10470         }
10471
10472 found:
10473         intel_crtc = to_intel_crtc(crtc);
10474
10475         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10476         if (ret)
10477                 goto fail;
10478
10479         state = drm_atomic_state_alloc(dev);
10480         restore_state = drm_atomic_state_alloc(dev);
10481         if (!state || !restore_state) {
10482                 ret = -ENOMEM;
10483                 goto fail;
10484         }
10485
10486         state->acquire_ctx = ctx;
10487         restore_state->acquire_ctx = ctx;
10488
10489         connector_state = drm_atomic_get_connector_state(state, connector);
10490         if (IS_ERR(connector_state)) {
10491                 ret = PTR_ERR(connector_state);
10492                 goto fail;
10493         }
10494
10495         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10496         if (ret)
10497                 goto fail;
10498
10499         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10500         if (IS_ERR(crtc_state)) {
10501                 ret = PTR_ERR(crtc_state);
10502                 goto fail;
10503         }
10504
10505         crtc_state->base.active = crtc_state->base.enable = true;
10506
10507         if (!mode)
10508                 mode = &load_detect_mode;
10509
10510         /* We need a framebuffer large enough to accommodate all accesses
10511          * that the plane may generate whilst we perform load detection.
10512          * We can not rely on the fbcon either being present (we get called
10513          * during its initialisation to detect all boot displays, or it may
10514          * not even exist) or that it is large enough to satisfy the
10515          * requested mode.
10516          */
10517         fb = mode_fits_in_fbdev(dev, mode);
10518         if (fb == NULL) {
10519                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10520                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10521         } else
10522                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10523         if (IS_ERR(fb)) {
10524                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10525                 goto fail;
10526         }
10527
10528         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10529         if (ret)
10530                 goto fail;
10531
10532         drm_framebuffer_unreference(fb);
10533
10534         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10535         if (ret)
10536                 goto fail;
10537
10538         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10539         if (!ret)
10540                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10541         if (!ret)
10542                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10543         if (ret) {
10544                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10545                 goto fail;
10546         }
10547
10548         if (drm_atomic_commit(state)) {
10549                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10550                 goto fail;
10551         }
10552
10553         old->restore_state = restore_state;
10554
10555         /* let the connector get through one full cycle before testing */
10556         intel_wait_for_vblank(dev, intel_crtc->pipe);
10557         return true;
10558
10559 fail:
10560         drm_atomic_state_free(state);
10561         drm_atomic_state_free(restore_state);
10562         restore_state = state = NULL;
10563
10564         if (ret == -EDEADLK) {
10565                 drm_modeset_backoff(ctx);
10566                 goto retry;
10567         }
10568
10569         return false;
10570 }
10571
10572 void intel_release_load_detect_pipe(struct drm_connector *connector,
10573                                     struct intel_load_detect_pipe *old,
10574                                     struct drm_modeset_acquire_ctx *ctx)
10575 {
10576         struct intel_encoder *intel_encoder =
10577                 intel_attached_encoder(connector);
10578         struct drm_encoder *encoder = &intel_encoder->base;
10579         struct drm_atomic_state *state = old->restore_state;
10580         int ret;
10581
10582         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10583                       connector->base.id, connector->name,
10584                       encoder->base.id, encoder->name);
10585
10586         if (!state)
10587                 return;
10588
10589         ret = drm_atomic_commit(state);
10590         if (ret) {
10591                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10592                 drm_atomic_state_free(state);
10593         }
10594 }
10595
10596 static int i9xx_pll_refclk(struct drm_device *dev,
10597                            const struct intel_crtc_state *pipe_config)
10598 {
10599         struct drm_i915_private *dev_priv = dev->dev_private;
10600         u32 dpll = pipe_config->dpll_hw_state.dpll;
10601
10602         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10603                 return dev_priv->vbt.lvds_ssc_freq;
10604         else if (HAS_PCH_SPLIT(dev))
10605                 return 120000;
10606         else if (!IS_GEN2(dev))
10607                 return 96000;
10608         else
10609                 return 48000;
10610 }
10611
10612 /* Returns the clock of the currently programmed mode of the given pipe. */
10613 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10614                                 struct intel_crtc_state *pipe_config)
10615 {
10616         struct drm_device *dev = crtc->base.dev;
10617         struct drm_i915_private *dev_priv = dev->dev_private;
10618         int pipe = pipe_config->cpu_transcoder;
10619         u32 dpll = pipe_config->dpll_hw_state.dpll;
10620         u32 fp;
10621         intel_clock_t clock;
10622         int port_clock;
10623         int refclk = i9xx_pll_refclk(dev, pipe_config);
10624
10625         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10626                 fp = pipe_config->dpll_hw_state.fp0;
10627         else
10628                 fp = pipe_config->dpll_hw_state.fp1;
10629
10630         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10631         if (IS_PINEVIEW(dev)) {
10632                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10633                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10634         } else {
10635                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10636                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10637         }
10638
10639         if (!IS_GEN2(dev)) {
10640                 if (IS_PINEVIEW(dev))
10641                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10642                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10643                 else
10644                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10645                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10646
10647                 switch (dpll & DPLL_MODE_MASK) {
10648                 case DPLLB_MODE_DAC_SERIAL:
10649                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10650                                 5 : 10;
10651                         break;
10652                 case DPLLB_MODE_LVDS:
10653                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10654                                 7 : 14;
10655                         break;
10656                 default:
10657                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10658                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10659                         return;
10660                 }
10661
10662                 if (IS_PINEVIEW(dev))
10663                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10664                 else
10665                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10666         } else {
10667                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10668                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10669
10670                 if (is_lvds) {
10671                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10672                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10673
10674                         if (lvds & LVDS_CLKB_POWER_UP)
10675                                 clock.p2 = 7;
10676                         else
10677                                 clock.p2 = 14;
10678                 } else {
10679                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10680                                 clock.p1 = 2;
10681                         else {
10682                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10683                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10684                         }
10685                         if (dpll & PLL_P2_DIVIDE_BY_4)
10686                                 clock.p2 = 4;
10687                         else
10688                                 clock.p2 = 2;
10689                 }
10690
10691                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10692         }
10693
10694         /*
10695          * This value includes pixel_multiplier. We will use
10696          * port_clock to compute adjusted_mode.crtc_clock in the
10697          * encoder's get_config() function.
10698          */
10699         pipe_config->port_clock = port_clock;
10700 }
10701
10702 int intel_dotclock_calculate(int link_freq,
10703                              const struct intel_link_m_n *m_n)
10704 {
10705         /*
10706          * The calculation for the data clock is:
10707          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10708          * But we want to avoid losing precison if possible, so:
10709          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10710          *
10711          * and the link clock is simpler:
10712          * link_clock = (m * link_clock) / n
10713          */
10714
10715         if (!m_n->link_n)
10716                 return 0;
10717
10718         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10719 }
10720
10721 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10722                                    struct intel_crtc_state *pipe_config)
10723 {
10724         struct drm_device *dev = crtc->base.dev;
10725
10726         /* read out port_clock from the DPLL */
10727         i9xx_crtc_clock_get(crtc, pipe_config);
10728
10729         /*
10730          * This value does not include pixel_multiplier.
10731          * We will check that port_clock and adjusted_mode.crtc_clock
10732          * agree once we know their relationship in the encoder's
10733          * get_config() function.
10734          */
10735         pipe_config->base.adjusted_mode.crtc_clock =
10736                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10737                                          &pipe_config->fdi_m_n);
10738 }
10739
10740 /** Returns the currently programmed mode of the given pipe. */
10741 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10742                                              struct drm_crtc *crtc)
10743 {
10744         struct drm_i915_private *dev_priv = dev->dev_private;
10745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10746         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10747         struct drm_display_mode *mode;
10748         struct intel_crtc_state *pipe_config;
10749         int htot = I915_READ(HTOTAL(cpu_transcoder));
10750         int hsync = I915_READ(HSYNC(cpu_transcoder));
10751         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10752         int vsync = I915_READ(VSYNC(cpu_transcoder));
10753         enum pipe pipe = intel_crtc->pipe;
10754
10755         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10756         if (!mode)
10757                 return NULL;
10758
10759         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10760         if (!pipe_config) {
10761                 kfree(mode);
10762                 return NULL;
10763         }
10764
10765         /*
10766          * Construct a pipe_config sufficient for getting the clock info
10767          * back out of crtc_clock_get.
10768          *
10769          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10770          * to use a real value here instead.
10771          */
10772         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10773         pipe_config->pixel_multiplier = 1;
10774         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10775         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10776         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10777         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10778
10779         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10780         mode->hdisplay = (htot & 0xffff) + 1;
10781         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10782         mode->hsync_start = (hsync & 0xffff) + 1;
10783         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10784         mode->vdisplay = (vtot & 0xffff) + 1;
10785         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10786         mode->vsync_start = (vsync & 0xffff) + 1;
10787         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10788
10789         drm_mode_set_name(mode);
10790
10791         kfree(pipe_config);
10792
10793         return mode;
10794 }
10795
10796 void intel_mark_busy(struct drm_device *dev)
10797 {
10798         struct drm_i915_private *dev_priv = dev->dev_private;
10799
10800         if (dev_priv->mm.busy)
10801                 return;
10802
10803         intel_runtime_pm_get(dev_priv);
10804         i915_update_gfx_val(dev_priv);
10805         if (INTEL_INFO(dev)->gen >= 6)
10806                 gen6_rps_busy(dev_priv);
10807         dev_priv->mm.busy = true;
10808 }
10809
10810 void intel_mark_idle(struct drm_device *dev)
10811 {
10812         struct drm_i915_private *dev_priv = dev->dev_private;
10813
10814         if (!dev_priv->mm.busy)
10815                 return;
10816
10817         dev_priv->mm.busy = false;
10818
10819         if (INTEL_INFO(dev)->gen >= 6)
10820                 gen6_rps_idle(dev->dev_private);
10821
10822         intel_runtime_pm_put(dev_priv);
10823 }
10824
10825 static void intel_crtc_destroy(struct drm_crtc *crtc)
10826 {
10827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10828         struct drm_device *dev = crtc->dev;
10829         struct intel_unpin_work *work;
10830
10831         spin_lock_irq(&dev->event_lock);
10832         work = intel_crtc->unpin_work;
10833         intel_crtc->unpin_work = NULL;
10834         spin_unlock_irq(&dev->event_lock);
10835
10836         if (work) {
10837                 cancel_work_sync(&work->work);
10838                 kfree(work);
10839         }
10840
10841         drm_crtc_cleanup(crtc);
10842
10843         kfree(intel_crtc);
10844 }
10845
10846 static void intel_unpin_work_fn(struct work_struct *__work)
10847 {
10848         struct intel_unpin_work *work =
10849                 container_of(__work, struct intel_unpin_work, work);
10850         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10851         struct drm_device *dev = crtc->base.dev;
10852         struct drm_plane *primary = crtc->base.primary;
10853
10854         mutex_lock(&dev->struct_mutex);
10855         intel_unpin_fb_obj(work->old_fb, primary->state);
10856         drm_gem_object_unreference(&work->pending_flip_obj->base);
10857
10858         if (work->flip_queued_req)
10859                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10860         mutex_unlock(&dev->struct_mutex);
10861
10862         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10863         intel_fbc_post_update(crtc);
10864         drm_framebuffer_unreference(work->old_fb);
10865
10866         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10867         atomic_dec(&crtc->unpin_work_count);
10868
10869         kfree(work);
10870 }
10871
10872 static void do_intel_finish_page_flip(struct drm_device *dev,
10873                                       struct drm_crtc *crtc)
10874 {
10875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10876         struct intel_unpin_work *work;
10877         unsigned long flags;
10878
10879         /* Ignore early vblank irqs */
10880         if (intel_crtc == NULL)
10881                 return;
10882
10883         /*
10884          * This is called both by irq handlers and the reset code (to complete
10885          * lost pageflips) so needs the full irqsave spinlocks.
10886          */
10887         spin_lock_irqsave(&dev->event_lock, flags);
10888         work = intel_crtc->unpin_work;
10889
10890         /* Ensure we don't miss a work->pending update ... */
10891         smp_rmb();
10892
10893         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10894                 spin_unlock_irqrestore(&dev->event_lock, flags);
10895                 return;
10896         }
10897
10898         page_flip_completed(intel_crtc);
10899
10900         spin_unlock_irqrestore(&dev->event_lock, flags);
10901 }
10902
10903 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10904 {
10905         struct drm_i915_private *dev_priv = dev->dev_private;
10906         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10907
10908         do_intel_finish_page_flip(dev, crtc);
10909 }
10910
10911 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10912 {
10913         struct drm_i915_private *dev_priv = dev->dev_private;
10914         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10915
10916         do_intel_finish_page_flip(dev, crtc);
10917 }
10918
10919 /* Is 'a' after or equal to 'b'? */
10920 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10921 {
10922         return !((a - b) & 0x80000000);
10923 }
10924
10925 static bool page_flip_finished(struct intel_crtc *crtc)
10926 {
10927         struct drm_device *dev = crtc->base.dev;
10928         struct drm_i915_private *dev_priv = dev->dev_private;
10929
10930         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10931             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10932                 return true;
10933
10934         /*
10935          * The relevant registers doen't exist on pre-ctg.
10936          * As the flip done interrupt doesn't trigger for mmio
10937          * flips on gmch platforms, a flip count check isn't
10938          * really needed there. But since ctg has the registers,
10939          * include it in the check anyway.
10940          */
10941         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10942                 return true;
10943
10944         /*
10945          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10946          * used the same base address. In that case the mmio flip might
10947          * have completed, but the CS hasn't even executed the flip yet.
10948          *
10949          * A flip count check isn't enough as the CS might have updated
10950          * the base address just after start of vblank, but before we
10951          * managed to process the interrupt. This means we'd complete the
10952          * CS flip too soon.
10953          *
10954          * Combining both checks should get us a good enough result. It may
10955          * still happen that the CS flip has been executed, but has not
10956          * yet actually completed. But in case the base address is the same
10957          * anyway, we don't really care.
10958          */
10959         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10960                 crtc->unpin_work->gtt_offset &&
10961                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10962                                     crtc->unpin_work->flip_count);
10963 }
10964
10965 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10966 {
10967         struct drm_i915_private *dev_priv = dev->dev_private;
10968         struct intel_crtc *intel_crtc =
10969                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10970         unsigned long flags;
10971
10972
10973         /*
10974          * This is called both by irq handlers and the reset code (to complete
10975          * lost pageflips) so needs the full irqsave spinlocks.
10976          *
10977          * NB: An MMIO update of the plane base pointer will also
10978          * generate a page-flip completion irq, i.e. every modeset
10979          * is also accompanied by a spurious intel_prepare_page_flip().
10980          */
10981         spin_lock_irqsave(&dev->event_lock, flags);
10982         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10983                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10984         spin_unlock_irqrestore(&dev->event_lock, flags);
10985 }
10986
10987 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10988 {
10989         /* Ensure that the work item is consistent when activating it ... */
10990         smp_wmb();
10991         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10992         /* and that it is marked active as soon as the irq could fire. */
10993         smp_wmb();
10994 }
10995
10996 static int intel_gen2_queue_flip(struct drm_device *dev,
10997                                  struct drm_crtc *crtc,
10998                                  struct drm_framebuffer *fb,
10999                                  struct drm_i915_gem_object *obj,
11000                                  struct drm_i915_gem_request *req,
11001                                  uint32_t flags)
11002 {
11003         struct intel_engine_cs *ring = req->ring;
11004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11005         u32 flip_mask;
11006         int ret;
11007
11008         ret = intel_ring_begin(req, 6);
11009         if (ret)
11010                 return ret;
11011
11012         /* Can't queue multiple flips, so wait for the previous
11013          * one to finish before executing the next.
11014          */
11015         if (intel_crtc->plane)
11016                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11017         else
11018                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11019         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11020         intel_ring_emit(ring, MI_NOOP);
11021         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11022                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11023         intel_ring_emit(ring, fb->pitches[0]);
11024         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11025         intel_ring_emit(ring, 0); /* aux display base address, unused */
11026
11027         intel_mark_page_flip_active(intel_crtc->unpin_work);
11028         return 0;
11029 }
11030
11031 static int intel_gen3_queue_flip(struct drm_device *dev,
11032                                  struct drm_crtc *crtc,
11033                                  struct drm_framebuffer *fb,
11034                                  struct drm_i915_gem_object *obj,
11035                                  struct drm_i915_gem_request *req,
11036                                  uint32_t flags)
11037 {
11038         struct intel_engine_cs *ring = req->ring;
11039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11040         u32 flip_mask;
11041         int ret;
11042
11043         ret = intel_ring_begin(req, 6);
11044         if (ret)
11045                 return ret;
11046
11047         if (intel_crtc->plane)
11048                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11049         else
11050                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11051         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11052         intel_ring_emit(ring, MI_NOOP);
11053         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11054                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11055         intel_ring_emit(ring, fb->pitches[0]);
11056         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11057         intel_ring_emit(ring, MI_NOOP);
11058
11059         intel_mark_page_flip_active(intel_crtc->unpin_work);
11060         return 0;
11061 }
11062
11063 static int intel_gen4_queue_flip(struct drm_device *dev,
11064                                  struct drm_crtc *crtc,
11065                                  struct drm_framebuffer *fb,
11066                                  struct drm_i915_gem_object *obj,
11067                                  struct drm_i915_gem_request *req,
11068                                  uint32_t flags)
11069 {
11070         struct intel_engine_cs *ring = req->ring;
11071         struct drm_i915_private *dev_priv = dev->dev_private;
11072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11073         uint32_t pf, pipesrc;
11074         int ret;
11075
11076         ret = intel_ring_begin(req, 4);
11077         if (ret)
11078                 return ret;
11079
11080         /* i965+ uses the linear or tiled offsets from the
11081          * Display Registers (which do not change across a page-flip)
11082          * so we need only reprogram the base address.
11083          */
11084         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11085                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11086         intel_ring_emit(ring, fb->pitches[0]);
11087         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11088                         obj->tiling_mode);
11089
11090         /* XXX Enabling the panel-fitter across page-flip is so far
11091          * untested on non-native modes, so ignore it for now.
11092          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11093          */
11094         pf = 0;
11095         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11096         intel_ring_emit(ring, pf | pipesrc);
11097
11098         intel_mark_page_flip_active(intel_crtc->unpin_work);
11099         return 0;
11100 }
11101
11102 static int intel_gen6_queue_flip(struct drm_device *dev,
11103                                  struct drm_crtc *crtc,
11104                                  struct drm_framebuffer *fb,
11105                                  struct drm_i915_gem_object *obj,
11106                                  struct drm_i915_gem_request *req,
11107                                  uint32_t flags)
11108 {
11109         struct intel_engine_cs *ring = req->ring;
11110         struct drm_i915_private *dev_priv = dev->dev_private;
11111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11112         uint32_t pf, pipesrc;
11113         int ret;
11114
11115         ret = intel_ring_begin(req, 4);
11116         if (ret)
11117                 return ret;
11118
11119         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11120                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11121         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11122         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11123
11124         /* Contrary to the suggestions in the documentation,
11125          * "Enable Panel Fitter" does not seem to be required when page
11126          * flipping with a non-native mode, and worse causes a normal
11127          * modeset to fail.
11128          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11129          */
11130         pf = 0;
11131         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11132         intel_ring_emit(ring, pf | pipesrc);
11133
11134         intel_mark_page_flip_active(intel_crtc->unpin_work);
11135         return 0;
11136 }
11137
11138 static int intel_gen7_queue_flip(struct drm_device *dev,
11139                                  struct drm_crtc *crtc,
11140                                  struct drm_framebuffer *fb,
11141                                  struct drm_i915_gem_object *obj,
11142                                  struct drm_i915_gem_request *req,
11143                                  uint32_t flags)
11144 {
11145         struct intel_engine_cs *ring = req->ring;
11146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11147         uint32_t plane_bit = 0;
11148         int len, ret;
11149
11150         switch (intel_crtc->plane) {
11151         case PLANE_A:
11152                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11153                 break;
11154         case PLANE_B:
11155                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11156                 break;
11157         case PLANE_C:
11158                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11159                 break;
11160         default:
11161                 WARN_ONCE(1, "unknown plane in flip command\n");
11162                 return -ENODEV;
11163         }
11164
11165         len = 4;
11166         if (ring->id == RCS) {
11167                 len += 6;
11168                 /*
11169                  * On Gen 8, SRM is now taking an extra dword to accommodate
11170                  * 48bits addresses, and we need a NOOP for the batch size to
11171                  * stay even.
11172                  */
11173                 if (IS_GEN8(dev))
11174                         len += 2;
11175         }
11176
11177         /*
11178          * BSpec MI_DISPLAY_FLIP for IVB:
11179          * "The full packet must be contained within the same cache line."
11180          *
11181          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11182          * cacheline, if we ever start emitting more commands before
11183          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11184          * then do the cacheline alignment, and finally emit the
11185          * MI_DISPLAY_FLIP.
11186          */
11187         ret = intel_ring_cacheline_align(req);
11188         if (ret)
11189                 return ret;
11190
11191         ret = intel_ring_begin(req, len);
11192         if (ret)
11193                 return ret;
11194
11195         /* Unmask the flip-done completion message. Note that the bspec says that
11196          * we should do this for both the BCS and RCS, and that we must not unmask
11197          * more than one flip event at any time (or ensure that one flip message
11198          * can be sent by waiting for flip-done prior to queueing new flips).
11199          * Experimentation says that BCS works despite DERRMR masking all
11200          * flip-done completion events and that unmasking all planes at once
11201          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11202          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11203          */
11204         if (ring->id == RCS) {
11205                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11206                 intel_ring_emit_reg(ring, DERRMR);
11207                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11208                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11209                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11210                 if (IS_GEN8(dev))
11211                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11212                                               MI_SRM_LRM_GLOBAL_GTT);
11213                 else
11214                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11215                                               MI_SRM_LRM_GLOBAL_GTT);
11216                 intel_ring_emit_reg(ring, DERRMR);
11217                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11218                 if (IS_GEN8(dev)) {
11219                         intel_ring_emit(ring, 0);
11220                         intel_ring_emit(ring, MI_NOOP);
11221                 }
11222         }
11223
11224         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11225         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11226         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11227         intel_ring_emit(ring, (MI_NOOP));
11228
11229         intel_mark_page_flip_active(intel_crtc->unpin_work);
11230         return 0;
11231 }
11232
11233 static bool use_mmio_flip(struct intel_engine_cs *ring,
11234                           struct drm_i915_gem_object *obj)
11235 {
11236         /*
11237          * This is not being used for older platforms, because
11238          * non-availability of flip done interrupt forces us to use
11239          * CS flips. Older platforms derive flip done using some clever
11240          * tricks involving the flip_pending status bits and vblank irqs.
11241          * So using MMIO flips there would disrupt this mechanism.
11242          */
11243
11244         if (ring == NULL)
11245                 return true;
11246
11247         if (INTEL_INFO(ring->dev)->gen < 5)
11248                 return false;
11249
11250         if (i915.use_mmio_flip < 0)
11251                 return false;
11252         else if (i915.use_mmio_flip > 0)
11253                 return true;
11254         else if (i915.enable_execlists)
11255                 return true;
11256         else if (obj->base.dma_buf &&
11257                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11258                                                        false))
11259                 return true;
11260         else
11261                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11262 }
11263
11264 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11265                              unsigned int rotation,
11266                              struct intel_unpin_work *work)
11267 {
11268         struct drm_device *dev = intel_crtc->base.dev;
11269         struct drm_i915_private *dev_priv = dev->dev_private;
11270         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11271         const enum pipe pipe = intel_crtc->pipe;
11272         u32 ctl, stride, tile_height;
11273
11274         ctl = I915_READ(PLANE_CTL(pipe, 0));
11275         ctl &= ~PLANE_CTL_TILED_MASK;
11276         switch (fb->modifier[0]) {
11277         case DRM_FORMAT_MOD_NONE:
11278                 break;
11279         case I915_FORMAT_MOD_X_TILED:
11280                 ctl |= PLANE_CTL_TILED_X;
11281                 break;
11282         case I915_FORMAT_MOD_Y_TILED:
11283                 ctl |= PLANE_CTL_TILED_Y;
11284                 break;
11285         case I915_FORMAT_MOD_Yf_TILED:
11286                 ctl |= PLANE_CTL_TILED_YF;
11287                 break;
11288         default:
11289                 MISSING_CASE(fb->modifier[0]);
11290         }
11291
11292         /*
11293          * The stride is either expressed as a multiple of 64 bytes chunks for
11294          * linear buffers or in number of tiles for tiled buffers.
11295          */
11296         if (intel_rotation_90_or_270(rotation)) {
11297                 /* stride = Surface height in tiles */
11298                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11299                 stride = DIV_ROUND_UP(fb->height, tile_height);
11300         } else {
11301                 stride = fb->pitches[0] /
11302                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11303                                                   fb->pixel_format);
11304         }
11305
11306         /*
11307          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11308          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11309          */
11310         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11311         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11312
11313         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11314         POSTING_READ(PLANE_SURF(pipe, 0));
11315 }
11316
11317 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11318                              struct intel_unpin_work *work)
11319 {
11320         struct drm_device *dev = intel_crtc->base.dev;
11321         struct drm_i915_private *dev_priv = dev->dev_private;
11322         struct intel_framebuffer *intel_fb =
11323                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11324         struct drm_i915_gem_object *obj = intel_fb->obj;
11325         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11326         u32 dspcntr;
11327
11328         dspcntr = I915_READ(reg);
11329
11330         if (obj->tiling_mode != I915_TILING_NONE)
11331                 dspcntr |= DISPPLANE_TILED;
11332         else
11333                 dspcntr &= ~DISPPLANE_TILED;
11334
11335         I915_WRITE(reg, dspcntr);
11336
11337         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11338         POSTING_READ(DSPSURF(intel_crtc->plane));
11339 }
11340
11341 /*
11342  * XXX: This is the temporary way to update the plane registers until we get
11343  * around to using the usual plane update functions for MMIO flips
11344  */
11345 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11346 {
11347         struct intel_crtc *crtc = mmio_flip->crtc;
11348         struct intel_unpin_work *work;
11349
11350         spin_lock_irq(&crtc->base.dev->event_lock);
11351         work = crtc->unpin_work;
11352         spin_unlock_irq(&crtc->base.dev->event_lock);
11353         if (work == NULL)
11354                 return;
11355
11356         intel_mark_page_flip_active(work);
11357
11358         intel_pipe_update_start(crtc);
11359
11360         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11361                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11362         else
11363                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11364                 ilk_do_mmio_flip(crtc, work);
11365
11366         intel_pipe_update_end(crtc);
11367 }
11368
11369 static void intel_mmio_flip_work_func(struct work_struct *work)
11370 {
11371         struct intel_mmio_flip *mmio_flip =
11372                 container_of(work, struct intel_mmio_flip, work);
11373         struct intel_framebuffer *intel_fb =
11374                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11375         struct drm_i915_gem_object *obj = intel_fb->obj;
11376
11377         if (mmio_flip->req) {
11378                 WARN_ON(__i915_wait_request(mmio_flip->req,
11379                                             mmio_flip->crtc->reset_counter,
11380                                             false, NULL,
11381                                             &mmio_flip->i915->rps.mmioflips));
11382                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11383         }
11384
11385         /* For framebuffer backed by dmabuf, wait for fence */
11386         if (obj->base.dma_buf)
11387                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11388                                                             false, false,
11389                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11390
11391         intel_do_mmio_flip(mmio_flip);
11392         kfree(mmio_flip);
11393 }
11394
11395 static int intel_queue_mmio_flip(struct drm_device *dev,
11396                                  struct drm_crtc *crtc,
11397                                  struct drm_i915_gem_object *obj)
11398 {
11399         struct intel_mmio_flip *mmio_flip;
11400
11401         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11402         if (mmio_flip == NULL)
11403                 return -ENOMEM;
11404
11405         mmio_flip->i915 = to_i915(dev);
11406         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11407         mmio_flip->crtc = to_intel_crtc(crtc);
11408         mmio_flip->rotation = crtc->primary->state->rotation;
11409
11410         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11411         schedule_work(&mmio_flip->work);
11412
11413         return 0;
11414 }
11415
11416 static int intel_default_queue_flip(struct drm_device *dev,
11417                                     struct drm_crtc *crtc,
11418                                     struct drm_framebuffer *fb,
11419                                     struct drm_i915_gem_object *obj,
11420                                     struct drm_i915_gem_request *req,
11421                                     uint32_t flags)
11422 {
11423         return -ENODEV;
11424 }
11425
11426 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11427                                          struct drm_crtc *crtc)
11428 {
11429         struct drm_i915_private *dev_priv = dev->dev_private;
11430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11431         struct intel_unpin_work *work = intel_crtc->unpin_work;
11432         u32 addr;
11433
11434         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11435                 return true;
11436
11437         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11438                 return false;
11439
11440         if (!work->enable_stall_check)
11441                 return false;
11442
11443         if (work->flip_ready_vblank == 0) {
11444                 if (work->flip_queued_req &&
11445                     !i915_gem_request_completed(work->flip_queued_req, true))
11446                         return false;
11447
11448                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11449         }
11450
11451         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11452                 return false;
11453
11454         /* Potential stall - if we see that the flip has happened,
11455          * assume a missed interrupt. */
11456         if (INTEL_INFO(dev)->gen >= 4)
11457                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11458         else
11459                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11460
11461         /* There is a potential issue here with a false positive after a flip
11462          * to the same address. We could address this by checking for a
11463          * non-incrementing frame counter.
11464          */
11465         return addr == work->gtt_offset;
11466 }
11467
11468 void intel_check_page_flip(struct drm_device *dev, int pipe)
11469 {
11470         struct drm_i915_private *dev_priv = dev->dev_private;
11471         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11473         struct intel_unpin_work *work;
11474
11475         WARN_ON(!in_interrupt());
11476
11477         if (crtc == NULL)
11478                 return;
11479
11480         spin_lock(&dev->event_lock);
11481         work = intel_crtc->unpin_work;
11482         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11483                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11484                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11485                 page_flip_completed(intel_crtc);
11486                 work = NULL;
11487         }
11488         if (work != NULL &&
11489             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11490                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11491         spin_unlock(&dev->event_lock);
11492 }
11493
11494 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11495                                 struct drm_framebuffer *fb,
11496                                 struct drm_pending_vblank_event *event,
11497                                 uint32_t page_flip_flags)
11498 {
11499         struct drm_device *dev = crtc->dev;
11500         struct drm_i915_private *dev_priv = dev->dev_private;
11501         struct drm_framebuffer *old_fb = crtc->primary->fb;
11502         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11504         struct drm_plane *primary = crtc->primary;
11505         enum pipe pipe = intel_crtc->pipe;
11506         struct intel_unpin_work *work;
11507         struct intel_engine_cs *ring;
11508         bool mmio_flip;
11509         struct drm_i915_gem_request *request = NULL;
11510         int ret;
11511
11512         /*
11513          * drm_mode_page_flip_ioctl() should already catch this, but double
11514          * check to be safe.  In the future we may enable pageflipping from
11515          * a disabled primary plane.
11516          */
11517         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11518                 return -EBUSY;
11519
11520         /* Can't change pixel format via MI display flips. */
11521         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11522                 return -EINVAL;
11523
11524         /*
11525          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11526          * Note that pitch changes could also affect these register.
11527          */
11528         if (INTEL_INFO(dev)->gen > 3 &&
11529             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11530              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11531                 return -EINVAL;
11532
11533         if (i915_terminally_wedged(&dev_priv->gpu_error))
11534                 goto out_hang;
11535
11536         work = kzalloc(sizeof(*work), GFP_KERNEL);
11537         if (work == NULL)
11538                 return -ENOMEM;
11539
11540         work->event = event;
11541         work->crtc = crtc;
11542         work->old_fb = old_fb;
11543         INIT_WORK(&work->work, intel_unpin_work_fn);
11544
11545         ret = drm_crtc_vblank_get(crtc);
11546         if (ret)
11547                 goto free_work;
11548
11549         /* We borrow the event spin lock for protecting unpin_work */
11550         spin_lock_irq(&dev->event_lock);
11551         if (intel_crtc->unpin_work) {
11552                 /* Before declaring the flip queue wedged, check if
11553                  * the hardware completed the operation behind our backs.
11554                  */
11555                 if (__intel_pageflip_stall_check(dev, crtc)) {
11556                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11557                         page_flip_completed(intel_crtc);
11558                 } else {
11559                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11560                         spin_unlock_irq(&dev->event_lock);
11561
11562                         drm_crtc_vblank_put(crtc);
11563                         kfree(work);
11564                         return -EBUSY;
11565                 }
11566         }
11567         intel_crtc->unpin_work = work;
11568         spin_unlock_irq(&dev->event_lock);
11569
11570         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11571                 flush_workqueue(dev_priv->wq);
11572
11573         /* Reference the objects for the scheduled work. */
11574         drm_framebuffer_reference(work->old_fb);
11575         drm_gem_object_reference(&obj->base);
11576
11577         crtc->primary->fb = fb;
11578         update_state_fb(crtc->primary);
11579         intel_fbc_pre_update(intel_crtc);
11580
11581         work->pending_flip_obj = obj;
11582
11583         ret = i915_mutex_lock_interruptible(dev);
11584         if (ret)
11585                 goto cleanup;
11586
11587         atomic_inc(&intel_crtc->unpin_work_count);
11588         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11589
11590         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11591                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11592
11593         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11594                 ring = &dev_priv->ring[BCS];
11595                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11596                         /* vlv: DISPLAY_FLIP fails to change tiling */
11597                         ring = NULL;
11598         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11599                 ring = &dev_priv->ring[BCS];
11600         } else if (INTEL_INFO(dev)->gen >= 7) {
11601                 ring = i915_gem_request_get_ring(obj->last_write_req);
11602                 if (ring == NULL || ring->id != RCS)
11603                         ring = &dev_priv->ring[BCS];
11604         } else {
11605                 ring = &dev_priv->ring[RCS];
11606         }
11607
11608         mmio_flip = use_mmio_flip(ring, obj);
11609
11610         /* When using CS flips, we want to emit semaphores between rings.
11611          * However, when using mmio flips we will create a task to do the
11612          * synchronisation, so all we want here is to pin the framebuffer
11613          * into the display plane and skip any waits.
11614          */
11615         if (!mmio_flip) {
11616                 ret = i915_gem_object_sync(obj, ring, &request);
11617                 if (ret)
11618                         goto cleanup_pending;
11619         }
11620
11621         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11622                                          crtc->primary->state);
11623         if (ret)
11624                 goto cleanup_pending;
11625
11626         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11627                                                   obj, 0);
11628         work->gtt_offset += intel_crtc->dspaddr_offset;
11629
11630         if (mmio_flip) {
11631                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11632                 if (ret)
11633                         goto cleanup_unpin;
11634
11635                 i915_gem_request_assign(&work->flip_queued_req,
11636                                         obj->last_write_req);
11637         } else {
11638                 if (!request) {
11639                         request = i915_gem_request_alloc(ring, NULL);
11640                         if (IS_ERR(request)) {
11641                                 ret = PTR_ERR(request);
11642                                 goto cleanup_unpin;
11643                         }
11644                 }
11645
11646                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11647                                                    page_flip_flags);
11648                 if (ret)
11649                         goto cleanup_unpin;
11650
11651                 i915_gem_request_assign(&work->flip_queued_req, request);
11652         }
11653
11654         if (request)
11655                 i915_add_request_no_flush(request);
11656
11657         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11658         work->enable_stall_check = true;
11659
11660         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11661                           to_intel_plane(primary)->frontbuffer_bit);
11662         mutex_unlock(&dev->struct_mutex);
11663
11664         intel_frontbuffer_flip_prepare(dev,
11665                                        to_intel_plane(primary)->frontbuffer_bit);
11666
11667         trace_i915_flip_request(intel_crtc->plane, obj);
11668
11669         return 0;
11670
11671 cleanup_unpin:
11672         intel_unpin_fb_obj(fb, crtc->primary->state);
11673 cleanup_pending:
11674         if (!IS_ERR_OR_NULL(request))
11675                 i915_gem_request_cancel(request);
11676         atomic_dec(&intel_crtc->unpin_work_count);
11677         mutex_unlock(&dev->struct_mutex);
11678 cleanup:
11679         crtc->primary->fb = old_fb;
11680         update_state_fb(crtc->primary);
11681
11682         drm_gem_object_unreference_unlocked(&obj->base);
11683         drm_framebuffer_unreference(work->old_fb);
11684
11685         spin_lock_irq(&dev->event_lock);
11686         intel_crtc->unpin_work = NULL;
11687         spin_unlock_irq(&dev->event_lock);
11688
11689         drm_crtc_vblank_put(crtc);
11690 free_work:
11691         kfree(work);
11692
11693         if (ret == -EIO) {
11694                 struct drm_atomic_state *state;
11695                 struct drm_plane_state *plane_state;
11696
11697 out_hang:
11698                 state = drm_atomic_state_alloc(dev);
11699                 if (!state)
11700                         return -ENOMEM;
11701                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11702
11703 retry:
11704                 plane_state = drm_atomic_get_plane_state(state, primary);
11705                 ret = PTR_ERR_OR_ZERO(plane_state);
11706                 if (!ret) {
11707                         drm_atomic_set_fb_for_plane(plane_state, fb);
11708
11709                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11710                         if (!ret)
11711                                 ret = drm_atomic_commit(state);
11712                 }
11713
11714                 if (ret == -EDEADLK) {
11715                         drm_modeset_backoff(state->acquire_ctx);
11716                         drm_atomic_state_clear(state);
11717                         goto retry;
11718                 }
11719
11720                 if (ret)
11721                         drm_atomic_state_free(state);
11722
11723                 if (ret == 0 && event) {
11724                         spin_lock_irq(&dev->event_lock);
11725                         drm_send_vblank_event(dev, pipe, event);
11726                         spin_unlock_irq(&dev->event_lock);
11727                 }
11728         }
11729         return ret;
11730 }
11731
11732
11733 /**
11734  * intel_wm_need_update - Check whether watermarks need updating
11735  * @plane: drm plane
11736  * @state: new plane state
11737  *
11738  * Check current plane state versus the new one to determine whether
11739  * watermarks need to be recalculated.
11740  *
11741  * Returns true or false.
11742  */
11743 static bool intel_wm_need_update(struct drm_plane *plane,
11744                                  struct drm_plane_state *state)
11745 {
11746         struct intel_plane_state *new = to_intel_plane_state(state);
11747         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11748
11749         /* Update watermarks on tiling or size changes. */
11750         if (new->visible != cur->visible)
11751                 return true;
11752
11753         if (!cur->base.fb || !new->base.fb)
11754                 return false;
11755
11756         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11757             cur->base.rotation != new->base.rotation ||
11758             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11759             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11760             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11761             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11762                 return true;
11763
11764         return false;
11765 }
11766
11767 static bool needs_scaling(struct intel_plane_state *state)
11768 {
11769         int src_w = drm_rect_width(&state->src) >> 16;
11770         int src_h = drm_rect_height(&state->src) >> 16;
11771         int dst_w = drm_rect_width(&state->dst);
11772         int dst_h = drm_rect_height(&state->dst);
11773
11774         return (src_w != dst_w || src_h != dst_h);
11775 }
11776
11777 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11778                                     struct drm_plane_state *plane_state)
11779 {
11780         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11781         struct drm_crtc *crtc = crtc_state->crtc;
11782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11783         struct drm_plane *plane = plane_state->plane;
11784         struct drm_device *dev = crtc->dev;
11785         struct intel_plane_state *old_plane_state =
11786                 to_intel_plane_state(plane->state);
11787         int idx = intel_crtc->base.base.id, ret;
11788         int i = drm_plane_index(plane);
11789         bool mode_changed = needs_modeset(crtc_state);
11790         bool was_crtc_enabled = crtc->state->active;
11791         bool is_crtc_enabled = crtc_state->active;
11792         bool turn_off, turn_on, visible, was_visible;
11793         struct drm_framebuffer *fb = plane_state->fb;
11794
11795         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11796             plane->type != DRM_PLANE_TYPE_CURSOR) {
11797                 ret = skl_update_scaler_plane(
11798                         to_intel_crtc_state(crtc_state),
11799                         to_intel_plane_state(plane_state));
11800                 if (ret)
11801                         return ret;
11802         }
11803
11804         was_visible = old_plane_state->visible;
11805         visible = to_intel_plane_state(plane_state)->visible;
11806
11807         if (!was_crtc_enabled && WARN_ON(was_visible))
11808                 was_visible = false;
11809
11810         /*
11811          * Visibility is calculated as if the crtc was on, but
11812          * after scaler setup everything depends on it being off
11813          * when the crtc isn't active.
11814          */
11815         if (!is_crtc_enabled)
11816                 to_intel_plane_state(plane_state)->visible = visible = false;
11817
11818         if (!was_visible && !visible)
11819                 return 0;
11820
11821         turn_off = was_visible && (!visible || mode_changed);
11822         turn_on = visible && (!was_visible || mode_changed);
11823
11824         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11825                          plane->base.id, fb ? fb->base.id : -1);
11826
11827         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11828                          plane->base.id, was_visible, visible,
11829                          turn_off, turn_on, mode_changed);
11830
11831         if (turn_on || turn_off) {
11832                 pipe_config->wm_changed = true;
11833
11834                 /* must disable cxsr around plane enable/disable */
11835                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11836                         if (is_crtc_enabled)
11837                                 intel_crtc->atomic.wait_vblank = true;
11838                         pipe_config->disable_cxsr = true;
11839                 }
11840         } else if (intel_wm_need_update(plane, plane_state)) {
11841                 pipe_config->wm_changed = true;
11842         }
11843
11844         if (visible || was_visible)
11845                 intel_crtc->atomic.fb_bits |=
11846                         to_intel_plane(plane)->frontbuffer_bit;
11847
11848         switch (plane->type) {
11849         case DRM_PLANE_TYPE_PRIMARY:
11850                 intel_crtc->atomic.post_enable_primary = turn_on;
11851                 intel_crtc->atomic.update_fbc = true;
11852
11853                 /*
11854                  * BDW signals flip done immediately if the plane
11855                  * is disabled, even if the plane enable is already
11856                  * armed to occur at the next vblank :(
11857                  */
11858                 if (turn_on && IS_BROADWELL(dev))
11859                         intel_crtc->atomic.wait_vblank = true;
11860
11861                 break;
11862         case DRM_PLANE_TYPE_CURSOR:
11863                 break;
11864         case DRM_PLANE_TYPE_OVERLAY:
11865                 /*
11866                  * WaCxSRDisabledForSpriteScaling:ivb
11867                  *
11868                  * cstate->update_wm was already set above, so this flag will
11869                  * take effect when we commit and program watermarks.
11870                  */
11871                 if (IS_IVYBRIDGE(dev) &&
11872                     needs_scaling(to_intel_plane_state(plane_state)) &&
11873                     !needs_scaling(old_plane_state)) {
11874                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11875                 } else if (turn_off && !mode_changed) {
11876                         intel_crtc->atomic.wait_vblank = true;
11877                         intel_crtc->atomic.update_sprite_watermarks |=
11878                                 1 << i;
11879                 }
11880
11881                 break;
11882         }
11883         return 0;
11884 }
11885
11886 static bool encoders_cloneable(const struct intel_encoder *a,
11887                                const struct intel_encoder *b)
11888 {
11889         /* masks could be asymmetric, so check both ways */
11890         return a == b || (a->cloneable & (1 << b->type) &&
11891                           b->cloneable & (1 << a->type));
11892 }
11893
11894 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11895                                          struct intel_crtc *crtc,
11896                                          struct intel_encoder *encoder)
11897 {
11898         struct intel_encoder *source_encoder;
11899         struct drm_connector *connector;
11900         struct drm_connector_state *connector_state;
11901         int i;
11902
11903         for_each_connector_in_state(state, connector, connector_state, i) {
11904                 if (connector_state->crtc != &crtc->base)
11905                         continue;
11906
11907                 source_encoder =
11908                         to_intel_encoder(connector_state->best_encoder);
11909                 if (!encoders_cloneable(encoder, source_encoder))
11910                         return false;
11911         }
11912
11913         return true;
11914 }
11915
11916 static bool check_encoder_cloning(struct drm_atomic_state *state,
11917                                   struct intel_crtc *crtc)
11918 {
11919         struct intel_encoder *encoder;
11920         struct drm_connector *connector;
11921         struct drm_connector_state *connector_state;
11922         int i;
11923
11924         for_each_connector_in_state(state, connector, connector_state, i) {
11925                 if (connector_state->crtc != &crtc->base)
11926                         continue;
11927
11928                 encoder = to_intel_encoder(connector_state->best_encoder);
11929                 if (!check_single_encoder_cloning(state, crtc, encoder))
11930                         return false;
11931         }
11932
11933         return true;
11934 }
11935
11936 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11937                                    struct drm_crtc_state *crtc_state)
11938 {
11939         struct drm_device *dev = crtc->dev;
11940         struct drm_i915_private *dev_priv = dev->dev_private;
11941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11942         struct intel_crtc_state *pipe_config =
11943                 to_intel_crtc_state(crtc_state);
11944         struct drm_atomic_state *state = crtc_state->state;
11945         int ret;
11946         bool mode_changed = needs_modeset(crtc_state);
11947
11948         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11949                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11950                 return -EINVAL;
11951         }
11952
11953         if (mode_changed && !crtc_state->active)
11954                 pipe_config->wm_changed = true;
11955
11956         if (mode_changed && crtc_state->enable &&
11957             dev_priv->display.crtc_compute_clock &&
11958             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11959                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11960                                                            pipe_config);
11961                 if (ret)
11962                         return ret;
11963         }
11964
11965         ret = 0;
11966         if (dev_priv->display.compute_pipe_wm) {
11967                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11968                 if (ret)
11969                         return ret;
11970         }
11971
11972         if (INTEL_INFO(dev)->gen >= 9) {
11973                 if (mode_changed)
11974                         ret = skl_update_scaler_crtc(pipe_config);
11975
11976                 if (!ret)
11977                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11978                                                          pipe_config);
11979         }
11980
11981         return ret;
11982 }
11983
11984 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11985         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11986         .load_lut = intel_crtc_load_lut,
11987         .atomic_begin = intel_begin_crtc_commit,
11988         .atomic_flush = intel_finish_crtc_commit,
11989         .atomic_check = intel_crtc_atomic_check,
11990 };
11991
11992 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11993 {
11994         struct intel_connector *connector;
11995
11996         for_each_intel_connector(dev, connector) {
11997                 if (connector->base.encoder) {
11998                         connector->base.state->best_encoder =
11999                                 connector->base.encoder;
12000                         connector->base.state->crtc =
12001                                 connector->base.encoder->crtc;
12002                 } else {
12003                         connector->base.state->best_encoder = NULL;
12004                         connector->base.state->crtc = NULL;
12005                 }
12006         }
12007 }
12008
12009 static void
12010 connected_sink_compute_bpp(struct intel_connector *connector,
12011                            struct intel_crtc_state *pipe_config)
12012 {
12013         int bpp = pipe_config->pipe_bpp;
12014
12015         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12016                 connector->base.base.id,
12017                 connector->base.name);
12018
12019         /* Don't use an invalid EDID bpc value */
12020         if (connector->base.display_info.bpc &&
12021             connector->base.display_info.bpc * 3 < bpp) {
12022                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12023                               bpp, connector->base.display_info.bpc*3);
12024                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12025         }
12026
12027         /* Clamp bpp to default limit on screens without EDID 1.4 */
12028         if (connector->base.display_info.bpc == 0) {
12029                 int type = connector->base.connector_type;
12030                 int clamp_bpp = 24;
12031
12032                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12033                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12034                     type == DRM_MODE_CONNECTOR_eDP)
12035                         clamp_bpp = 18;
12036
12037                 if (bpp > clamp_bpp) {
12038                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12039                                       bpp, clamp_bpp);
12040                         pipe_config->pipe_bpp = clamp_bpp;
12041                 }
12042         }
12043 }
12044
12045 static int
12046 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12047                           struct intel_crtc_state *pipe_config)
12048 {
12049         struct drm_device *dev = crtc->base.dev;
12050         struct drm_atomic_state *state;
12051         struct drm_connector *connector;
12052         struct drm_connector_state *connector_state;
12053         int bpp, i;
12054
12055         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12056                 bpp = 10*3;
12057         else if (INTEL_INFO(dev)->gen >= 5)
12058                 bpp = 12*3;
12059         else
12060                 bpp = 8*3;
12061
12062
12063         pipe_config->pipe_bpp = bpp;
12064
12065         state = pipe_config->base.state;
12066
12067         /* Clamp display bpp to EDID value */
12068         for_each_connector_in_state(state, connector, connector_state, i) {
12069                 if (connector_state->crtc != &crtc->base)
12070                         continue;
12071
12072                 connected_sink_compute_bpp(to_intel_connector(connector),
12073                                            pipe_config);
12074         }
12075
12076         return bpp;
12077 }
12078
12079 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12080 {
12081         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12082                         "type: 0x%x flags: 0x%x\n",
12083                 mode->crtc_clock,
12084                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12085                 mode->crtc_hsync_end, mode->crtc_htotal,
12086                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12087                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12088 }
12089
12090 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12091                                    struct intel_crtc_state *pipe_config,
12092                                    const char *context)
12093 {
12094         struct drm_device *dev = crtc->base.dev;
12095         struct drm_plane *plane;
12096         struct intel_plane *intel_plane;
12097         struct intel_plane_state *state;
12098         struct drm_framebuffer *fb;
12099
12100         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12101                       context, pipe_config, pipe_name(crtc->pipe));
12102
12103         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12104         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12105                       pipe_config->pipe_bpp, pipe_config->dither);
12106         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12107                       pipe_config->has_pch_encoder,
12108                       pipe_config->fdi_lanes,
12109                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12110                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12111                       pipe_config->fdi_m_n.tu);
12112         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12113                       pipe_config->has_dp_encoder,
12114                       pipe_config->lane_count,
12115                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12116                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12117                       pipe_config->dp_m_n.tu);
12118
12119         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12120                       pipe_config->has_dp_encoder,
12121                       pipe_config->lane_count,
12122                       pipe_config->dp_m2_n2.gmch_m,
12123                       pipe_config->dp_m2_n2.gmch_n,
12124                       pipe_config->dp_m2_n2.link_m,
12125                       pipe_config->dp_m2_n2.link_n,
12126                       pipe_config->dp_m2_n2.tu);
12127
12128         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12129                       pipe_config->has_audio,
12130                       pipe_config->has_infoframe);
12131
12132         DRM_DEBUG_KMS("requested mode:\n");
12133         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12134         DRM_DEBUG_KMS("adjusted mode:\n");
12135         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12136         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12137         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12138         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12139                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12140         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12141                       crtc->num_scalers,
12142                       pipe_config->scaler_state.scaler_users,
12143                       pipe_config->scaler_state.scaler_id);
12144         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12145                       pipe_config->gmch_pfit.control,
12146                       pipe_config->gmch_pfit.pgm_ratios,
12147                       pipe_config->gmch_pfit.lvds_border_bits);
12148         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12149                       pipe_config->pch_pfit.pos,
12150                       pipe_config->pch_pfit.size,
12151                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12152         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12153         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12154
12155         if (IS_BROXTON(dev)) {
12156                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12157                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12158                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12159                               pipe_config->ddi_pll_sel,
12160                               pipe_config->dpll_hw_state.ebb0,
12161                               pipe_config->dpll_hw_state.ebb4,
12162                               pipe_config->dpll_hw_state.pll0,
12163                               pipe_config->dpll_hw_state.pll1,
12164                               pipe_config->dpll_hw_state.pll2,
12165                               pipe_config->dpll_hw_state.pll3,
12166                               pipe_config->dpll_hw_state.pll6,
12167                               pipe_config->dpll_hw_state.pll8,
12168                               pipe_config->dpll_hw_state.pll9,
12169                               pipe_config->dpll_hw_state.pll10,
12170                               pipe_config->dpll_hw_state.pcsdw12);
12171         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12172                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12173                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12174                               pipe_config->ddi_pll_sel,
12175                               pipe_config->dpll_hw_state.ctrl1,
12176                               pipe_config->dpll_hw_state.cfgcr1,
12177                               pipe_config->dpll_hw_state.cfgcr2);
12178         } else if (HAS_DDI(dev)) {
12179                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12180                               pipe_config->ddi_pll_sel,
12181                               pipe_config->dpll_hw_state.wrpll,
12182                               pipe_config->dpll_hw_state.spll);
12183         } else {
12184                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12185                               "fp0: 0x%x, fp1: 0x%x\n",
12186                               pipe_config->dpll_hw_state.dpll,
12187                               pipe_config->dpll_hw_state.dpll_md,
12188                               pipe_config->dpll_hw_state.fp0,
12189                               pipe_config->dpll_hw_state.fp1);
12190         }
12191
12192         DRM_DEBUG_KMS("planes on this crtc\n");
12193         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12194                 intel_plane = to_intel_plane(plane);
12195                 if (intel_plane->pipe != crtc->pipe)
12196                         continue;
12197
12198                 state = to_intel_plane_state(plane->state);
12199                 fb = state->base.fb;
12200                 if (!fb) {
12201                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12202                                 "disabled, scaler_id = %d\n",
12203                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12204                                 plane->base.id, intel_plane->pipe,
12205                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12206                                 drm_plane_index(plane), state->scaler_id);
12207                         continue;
12208                 }
12209
12210                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12211                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12212                         plane->base.id, intel_plane->pipe,
12213                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12214                         drm_plane_index(plane));
12215                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12216                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12217                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12218                         state->scaler_id,
12219                         state->src.x1 >> 16, state->src.y1 >> 16,
12220                         drm_rect_width(&state->src) >> 16,
12221                         drm_rect_height(&state->src) >> 16,
12222                         state->dst.x1, state->dst.y1,
12223                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12224         }
12225 }
12226
12227 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12228 {
12229         struct drm_device *dev = state->dev;
12230         struct drm_connector *connector;
12231         unsigned int used_ports = 0;
12232
12233         /*
12234          * Walk the connector list instead of the encoder
12235          * list to detect the problem on ddi platforms
12236          * where there's just one encoder per digital port.
12237          */
12238         drm_for_each_connector(connector, dev) {
12239                 struct drm_connector_state *connector_state;
12240                 struct intel_encoder *encoder;
12241
12242                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12243                 if (!connector_state)
12244                         connector_state = connector->state;
12245
12246                 if (!connector_state->best_encoder)
12247                         continue;
12248
12249                 encoder = to_intel_encoder(connector_state->best_encoder);
12250
12251                 WARN_ON(!connector_state->crtc);
12252
12253                 switch (encoder->type) {
12254                         unsigned int port_mask;
12255                 case INTEL_OUTPUT_UNKNOWN:
12256                         if (WARN_ON(!HAS_DDI(dev)))
12257                                 break;
12258                 case INTEL_OUTPUT_DISPLAYPORT:
12259                 case INTEL_OUTPUT_HDMI:
12260                 case INTEL_OUTPUT_EDP:
12261                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12262
12263                         /* the same port mustn't appear more than once */
12264                         if (used_ports & port_mask)
12265                                 return false;
12266
12267                         used_ports |= port_mask;
12268                 default:
12269                         break;
12270                 }
12271         }
12272
12273         return true;
12274 }
12275
12276 static void
12277 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12278 {
12279         struct drm_crtc_state tmp_state;
12280         struct intel_crtc_scaler_state scaler_state;
12281         struct intel_dpll_hw_state dpll_hw_state;
12282         enum intel_dpll_id shared_dpll;
12283         uint32_t ddi_pll_sel;
12284         bool force_thru;
12285
12286         /* FIXME: before the switch to atomic started, a new pipe_config was
12287          * kzalloc'd. Code that depends on any field being zero should be
12288          * fixed, so that the crtc_state can be safely duplicated. For now,
12289          * only fields that are know to not cause problems are preserved. */
12290
12291         tmp_state = crtc_state->base;
12292         scaler_state = crtc_state->scaler_state;
12293         shared_dpll = crtc_state->shared_dpll;
12294         dpll_hw_state = crtc_state->dpll_hw_state;
12295         ddi_pll_sel = crtc_state->ddi_pll_sel;
12296         force_thru = crtc_state->pch_pfit.force_thru;
12297
12298         memset(crtc_state, 0, sizeof *crtc_state);
12299
12300         crtc_state->base = tmp_state;
12301         crtc_state->scaler_state = scaler_state;
12302         crtc_state->shared_dpll = shared_dpll;
12303         crtc_state->dpll_hw_state = dpll_hw_state;
12304         crtc_state->ddi_pll_sel = ddi_pll_sel;
12305         crtc_state->pch_pfit.force_thru = force_thru;
12306 }
12307
12308 static int
12309 intel_modeset_pipe_config(struct drm_crtc *crtc,
12310                           struct intel_crtc_state *pipe_config)
12311 {
12312         struct drm_atomic_state *state = pipe_config->base.state;
12313         struct intel_encoder *encoder;
12314         struct drm_connector *connector;
12315         struct drm_connector_state *connector_state;
12316         int base_bpp, ret = -EINVAL;
12317         int i;
12318         bool retry = true;
12319
12320         clear_intel_crtc_state(pipe_config);
12321
12322         pipe_config->cpu_transcoder =
12323                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12324
12325         /*
12326          * Sanitize sync polarity flags based on requested ones. If neither
12327          * positive or negative polarity is requested, treat this as meaning
12328          * negative polarity.
12329          */
12330         if (!(pipe_config->base.adjusted_mode.flags &
12331               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12332                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12333
12334         if (!(pipe_config->base.adjusted_mode.flags &
12335               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12336                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12337
12338         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12339                                              pipe_config);
12340         if (base_bpp < 0)
12341                 goto fail;
12342
12343         /*
12344          * Determine the real pipe dimensions. Note that stereo modes can
12345          * increase the actual pipe size due to the frame doubling and
12346          * insertion of additional space for blanks between the frame. This
12347          * is stored in the crtc timings. We use the requested mode to do this
12348          * computation to clearly distinguish it from the adjusted mode, which
12349          * can be changed by the connectors in the below retry loop.
12350          */
12351         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12352                                &pipe_config->pipe_src_w,
12353                                &pipe_config->pipe_src_h);
12354
12355 encoder_retry:
12356         /* Ensure the port clock defaults are reset when retrying. */
12357         pipe_config->port_clock = 0;
12358         pipe_config->pixel_multiplier = 1;
12359
12360         /* Fill in default crtc timings, allow encoders to overwrite them. */
12361         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12362                               CRTC_STEREO_DOUBLE);
12363
12364         /* Pass our mode to the connectors and the CRTC to give them a chance to
12365          * adjust it according to limitations or connector properties, and also
12366          * a chance to reject the mode entirely.
12367          */
12368         for_each_connector_in_state(state, connector, connector_state, i) {
12369                 if (connector_state->crtc != crtc)
12370                         continue;
12371
12372                 encoder = to_intel_encoder(connector_state->best_encoder);
12373
12374                 if (!(encoder->compute_config(encoder, pipe_config))) {
12375                         DRM_DEBUG_KMS("Encoder config failure\n");
12376                         goto fail;
12377                 }
12378         }
12379
12380         /* Set default port clock if not overwritten by the encoder. Needs to be
12381          * done afterwards in case the encoder adjusts the mode. */
12382         if (!pipe_config->port_clock)
12383                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12384                         * pipe_config->pixel_multiplier;
12385
12386         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12387         if (ret < 0) {
12388                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12389                 goto fail;
12390         }
12391
12392         if (ret == RETRY) {
12393                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12394                         ret = -EINVAL;
12395                         goto fail;
12396                 }
12397
12398                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12399                 retry = false;
12400                 goto encoder_retry;
12401         }
12402
12403         /* Dithering seems to not pass-through bits correctly when it should, so
12404          * only enable it on 6bpc panels. */
12405         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12406         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12407                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12408
12409 fail:
12410         return ret;
12411 }
12412
12413 static void
12414 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12415 {
12416         struct drm_crtc *crtc;
12417         struct drm_crtc_state *crtc_state;
12418         int i;
12419
12420         /* Double check state. */
12421         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12422                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12423
12424                 /* Update hwmode for vblank functions */
12425                 if (crtc->state->active)
12426                         crtc->hwmode = crtc->state->adjusted_mode;
12427                 else
12428                         crtc->hwmode.crtc_clock = 0;
12429
12430                 /*
12431                  * Update legacy state to satisfy fbc code. This can
12432                  * be removed when fbc uses the atomic state.
12433                  */
12434                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12435                         struct drm_plane_state *plane_state = crtc->primary->state;
12436
12437                         crtc->primary->fb = plane_state->fb;
12438                         crtc->x = plane_state->src_x >> 16;
12439                         crtc->y = plane_state->src_y >> 16;
12440                 }
12441         }
12442 }
12443
12444 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12445 {
12446         int diff;
12447
12448         if (clock1 == clock2)
12449                 return true;
12450
12451         if (!clock1 || !clock2)
12452                 return false;
12453
12454         diff = abs(clock1 - clock2);
12455
12456         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12457                 return true;
12458
12459         return false;
12460 }
12461
12462 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12463         list_for_each_entry((intel_crtc), \
12464                             &(dev)->mode_config.crtc_list, \
12465                             base.head) \
12466                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12467
12468 static bool
12469 intel_compare_m_n(unsigned int m, unsigned int n,
12470                   unsigned int m2, unsigned int n2,
12471                   bool exact)
12472 {
12473         if (m == m2 && n == n2)
12474                 return true;
12475
12476         if (exact || !m || !n || !m2 || !n2)
12477                 return false;
12478
12479         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12480
12481         if (n > n2) {
12482                 while (n > n2) {
12483                         m2 <<= 1;
12484                         n2 <<= 1;
12485                 }
12486         } else if (n < n2) {
12487                 while (n < n2) {
12488                         m <<= 1;
12489                         n <<= 1;
12490                 }
12491         }
12492
12493         if (n != n2)
12494                 return false;
12495
12496         return intel_fuzzy_clock_check(m, m2);
12497 }
12498
12499 static bool
12500 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12501                        struct intel_link_m_n *m2_n2,
12502                        bool adjust)
12503 {
12504         if (m_n->tu == m2_n2->tu &&
12505             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12506                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12507             intel_compare_m_n(m_n->link_m, m_n->link_n,
12508                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12509                 if (adjust)
12510                         *m2_n2 = *m_n;
12511
12512                 return true;
12513         }
12514
12515         return false;
12516 }
12517
12518 static bool
12519 intel_pipe_config_compare(struct drm_device *dev,
12520                           struct intel_crtc_state *current_config,
12521                           struct intel_crtc_state *pipe_config,
12522                           bool adjust)
12523 {
12524         bool ret = true;
12525
12526 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12527         do { \
12528                 if (!adjust) \
12529                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12530                 else \
12531                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12532         } while (0)
12533
12534 #define PIPE_CONF_CHECK_X(name) \
12535         if (current_config->name != pipe_config->name) { \
12536                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12537                           "(expected 0x%08x, found 0x%08x)\n", \
12538                           current_config->name, \
12539                           pipe_config->name); \
12540                 ret = false; \
12541         }
12542
12543 #define PIPE_CONF_CHECK_I(name) \
12544         if (current_config->name != pipe_config->name) { \
12545                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12546                           "(expected %i, found %i)\n", \
12547                           current_config->name, \
12548                           pipe_config->name); \
12549                 ret = false; \
12550         }
12551
12552 #define PIPE_CONF_CHECK_M_N(name) \
12553         if (!intel_compare_link_m_n(&current_config->name, \
12554                                     &pipe_config->name,\
12555                                     adjust)) { \
12556                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12557                           "(expected tu %i gmch %i/%i link %i/%i, " \
12558                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12559                           current_config->name.tu, \
12560                           current_config->name.gmch_m, \
12561                           current_config->name.gmch_n, \
12562                           current_config->name.link_m, \
12563                           current_config->name.link_n, \
12564                           pipe_config->name.tu, \
12565                           pipe_config->name.gmch_m, \
12566                           pipe_config->name.gmch_n, \
12567                           pipe_config->name.link_m, \
12568                           pipe_config->name.link_n); \
12569                 ret = false; \
12570         }
12571
12572 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12573         if (!intel_compare_link_m_n(&current_config->name, \
12574                                     &pipe_config->name, adjust) && \
12575             !intel_compare_link_m_n(&current_config->alt_name, \
12576                                     &pipe_config->name, adjust)) { \
12577                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12578                           "(expected tu %i gmch %i/%i link %i/%i, " \
12579                           "or tu %i gmch %i/%i link %i/%i, " \
12580                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12581                           current_config->name.tu, \
12582                           current_config->name.gmch_m, \
12583                           current_config->name.gmch_n, \
12584                           current_config->name.link_m, \
12585                           current_config->name.link_n, \
12586                           current_config->alt_name.tu, \
12587                           current_config->alt_name.gmch_m, \
12588                           current_config->alt_name.gmch_n, \
12589                           current_config->alt_name.link_m, \
12590                           current_config->alt_name.link_n, \
12591                           pipe_config->name.tu, \
12592                           pipe_config->name.gmch_m, \
12593                           pipe_config->name.gmch_n, \
12594                           pipe_config->name.link_m, \
12595                           pipe_config->name.link_n); \
12596                 ret = false; \
12597         }
12598
12599 /* This is required for BDW+ where there is only one set of registers for
12600  * switching between high and low RR.
12601  * This macro can be used whenever a comparison has to be made between one
12602  * hw state and multiple sw state variables.
12603  */
12604 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12605         if ((current_config->name != pipe_config->name) && \
12606                 (current_config->alt_name != pipe_config->name)) { \
12607                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12608                                   "(expected %i or %i, found %i)\n", \
12609                                   current_config->name, \
12610                                   current_config->alt_name, \
12611                                   pipe_config->name); \
12612                         ret = false; \
12613         }
12614
12615 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12616         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12617                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12618                           "(expected %i, found %i)\n", \
12619                           current_config->name & (mask), \
12620                           pipe_config->name & (mask)); \
12621                 ret = false; \
12622         }
12623
12624 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12625         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12626                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12627                           "(expected %i, found %i)\n", \
12628                           current_config->name, \
12629                           pipe_config->name); \
12630                 ret = false; \
12631         }
12632
12633 #define PIPE_CONF_QUIRK(quirk)  \
12634         ((current_config->quirks | pipe_config->quirks) & (quirk))
12635
12636         PIPE_CONF_CHECK_I(cpu_transcoder);
12637
12638         PIPE_CONF_CHECK_I(has_pch_encoder);
12639         PIPE_CONF_CHECK_I(fdi_lanes);
12640         PIPE_CONF_CHECK_M_N(fdi_m_n);
12641
12642         PIPE_CONF_CHECK_I(has_dp_encoder);
12643         PIPE_CONF_CHECK_I(lane_count);
12644
12645         if (INTEL_INFO(dev)->gen < 8) {
12646                 PIPE_CONF_CHECK_M_N(dp_m_n);
12647
12648                 if (current_config->has_drrs)
12649                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12650         } else
12651                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12652
12653         PIPE_CONF_CHECK_I(has_dsi_encoder);
12654
12655         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12656         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12657         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12658         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12659         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12660         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12661
12662         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12663         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12664         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12665         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12666         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12667         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12668
12669         PIPE_CONF_CHECK_I(pixel_multiplier);
12670         PIPE_CONF_CHECK_I(has_hdmi_sink);
12671         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12672             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12673                 PIPE_CONF_CHECK_I(limited_color_range);
12674         PIPE_CONF_CHECK_I(has_infoframe);
12675
12676         PIPE_CONF_CHECK_I(has_audio);
12677
12678         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12679                               DRM_MODE_FLAG_INTERLACE);
12680
12681         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12682                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12683                                       DRM_MODE_FLAG_PHSYNC);
12684                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12685                                       DRM_MODE_FLAG_NHSYNC);
12686                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12687                                       DRM_MODE_FLAG_PVSYNC);
12688                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12689                                       DRM_MODE_FLAG_NVSYNC);
12690         }
12691
12692         PIPE_CONF_CHECK_X(gmch_pfit.control);
12693         /* pfit ratios are autocomputed by the hw on gen4+ */
12694         if (INTEL_INFO(dev)->gen < 4)
12695                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12696         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12697
12698         if (!adjust) {
12699                 PIPE_CONF_CHECK_I(pipe_src_w);
12700                 PIPE_CONF_CHECK_I(pipe_src_h);
12701
12702                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12703                 if (current_config->pch_pfit.enabled) {
12704                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12705                         PIPE_CONF_CHECK_X(pch_pfit.size);
12706                 }
12707
12708                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12709         }
12710
12711         /* BDW+ don't expose a synchronous way to read the state */
12712         if (IS_HASWELL(dev))
12713                 PIPE_CONF_CHECK_I(ips_enabled);
12714
12715         PIPE_CONF_CHECK_I(double_wide);
12716
12717         PIPE_CONF_CHECK_X(ddi_pll_sel);
12718
12719         PIPE_CONF_CHECK_I(shared_dpll);
12720         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12721         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12722         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12723         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12724         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12725         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12726         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12727         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12728         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12729
12730         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12731                 PIPE_CONF_CHECK_I(pipe_bpp);
12732
12733         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12734         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12735
12736 #undef PIPE_CONF_CHECK_X
12737 #undef PIPE_CONF_CHECK_I
12738 #undef PIPE_CONF_CHECK_I_ALT
12739 #undef PIPE_CONF_CHECK_FLAGS
12740 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12741 #undef PIPE_CONF_QUIRK
12742 #undef INTEL_ERR_OR_DBG_KMS
12743
12744         return ret;
12745 }
12746
12747 static void check_wm_state(struct drm_device *dev)
12748 {
12749         struct drm_i915_private *dev_priv = dev->dev_private;
12750         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12751         struct intel_crtc *intel_crtc;
12752         int plane;
12753
12754         if (INTEL_INFO(dev)->gen < 9)
12755                 return;
12756
12757         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12758         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12759
12760         for_each_intel_crtc(dev, intel_crtc) {
12761                 struct skl_ddb_entry *hw_entry, *sw_entry;
12762                 const enum pipe pipe = intel_crtc->pipe;
12763
12764                 if (!intel_crtc->active)
12765                         continue;
12766
12767                 /* planes */
12768                 for_each_plane(dev_priv, pipe, plane) {
12769                         hw_entry = &hw_ddb.plane[pipe][plane];
12770                         sw_entry = &sw_ddb->plane[pipe][plane];
12771
12772                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12773                                 continue;
12774
12775                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12776                                   "(expected (%u,%u), found (%u,%u))\n",
12777                                   pipe_name(pipe), plane + 1,
12778                                   sw_entry->start, sw_entry->end,
12779                                   hw_entry->start, hw_entry->end);
12780                 }
12781
12782                 /* cursor */
12783                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12784                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12785
12786                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12787                         continue;
12788
12789                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12790                           "(expected (%u,%u), found (%u,%u))\n",
12791                           pipe_name(pipe),
12792                           sw_entry->start, sw_entry->end,
12793                           hw_entry->start, hw_entry->end);
12794         }
12795 }
12796
12797 static void
12798 check_connector_state(struct drm_device *dev,
12799                       struct drm_atomic_state *old_state)
12800 {
12801         struct drm_connector_state *old_conn_state;
12802         struct drm_connector *connector;
12803         int i;
12804
12805         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12806                 struct drm_encoder *encoder = connector->encoder;
12807                 struct drm_connector_state *state = connector->state;
12808
12809                 /* This also checks the encoder/connector hw state with the
12810                  * ->get_hw_state callbacks. */
12811                 intel_connector_check_state(to_intel_connector(connector));
12812
12813                 I915_STATE_WARN(state->best_encoder != encoder,
12814                      "connector's atomic encoder doesn't match legacy encoder\n");
12815         }
12816 }
12817
12818 static void
12819 check_encoder_state(struct drm_device *dev)
12820 {
12821         struct intel_encoder *encoder;
12822         struct intel_connector *connector;
12823
12824         for_each_intel_encoder(dev, encoder) {
12825                 bool enabled = false;
12826                 enum pipe pipe;
12827
12828                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12829                               encoder->base.base.id,
12830                               encoder->base.name);
12831
12832                 for_each_intel_connector(dev, connector) {
12833                         if (connector->base.state->best_encoder != &encoder->base)
12834                                 continue;
12835                         enabled = true;
12836
12837                         I915_STATE_WARN(connector->base.state->crtc !=
12838                                         encoder->base.crtc,
12839                              "connector's crtc doesn't match encoder crtc\n");
12840                 }
12841
12842                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12843                      "encoder's enabled state mismatch "
12844                      "(expected %i, found %i)\n",
12845                      !!encoder->base.crtc, enabled);
12846
12847                 if (!encoder->base.crtc) {
12848                         bool active;
12849
12850                         active = encoder->get_hw_state(encoder, &pipe);
12851                         I915_STATE_WARN(active,
12852                              "encoder detached but still enabled on pipe %c.\n",
12853                              pipe_name(pipe));
12854                 }
12855         }
12856 }
12857
12858 static void
12859 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12860 {
12861         struct drm_i915_private *dev_priv = dev->dev_private;
12862         struct intel_encoder *encoder;
12863         struct drm_crtc_state *old_crtc_state;
12864         struct drm_crtc *crtc;
12865         int i;
12866
12867         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12868                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12869                 struct intel_crtc_state *pipe_config, *sw_config;
12870                 bool active;
12871
12872                 if (!needs_modeset(crtc->state) &&
12873                     !to_intel_crtc_state(crtc->state)->update_pipe)
12874                         continue;
12875
12876                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12877                 pipe_config = to_intel_crtc_state(old_crtc_state);
12878                 memset(pipe_config, 0, sizeof(*pipe_config));
12879                 pipe_config->base.crtc = crtc;
12880                 pipe_config->base.state = old_state;
12881
12882                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12883                               crtc->base.id);
12884
12885                 active = dev_priv->display.get_pipe_config(intel_crtc,
12886                                                            pipe_config);
12887
12888                 /* hw state is inconsistent with the pipe quirk */
12889                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12890                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12891                         active = crtc->state->active;
12892
12893                 I915_STATE_WARN(crtc->state->active != active,
12894                      "crtc active state doesn't match with hw state "
12895                      "(expected %i, found %i)\n", crtc->state->active, active);
12896
12897                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12898                      "transitional active state does not match atomic hw state "
12899                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12900
12901                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12902                         enum pipe pipe;
12903
12904                         active = encoder->get_hw_state(encoder, &pipe);
12905                         I915_STATE_WARN(active != crtc->state->active,
12906                                 "[ENCODER:%i] active %i with crtc active %i\n",
12907                                 encoder->base.base.id, active, crtc->state->active);
12908
12909                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12910                                         "Encoder connected to wrong pipe %c\n",
12911                                         pipe_name(pipe));
12912
12913                         if (active)
12914                                 encoder->get_config(encoder, pipe_config);
12915                 }
12916
12917                 if (!crtc->state->active)
12918                         continue;
12919
12920                 sw_config = to_intel_crtc_state(crtc->state);
12921                 if (!intel_pipe_config_compare(dev, sw_config,
12922                                                pipe_config, false)) {
12923                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12924                         intel_dump_pipe_config(intel_crtc, pipe_config,
12925                                                "[hw state]");
12926                         intel_dump_pipe_config(intel_crtc, sw_config,
12927                                                "[sw state]");
12928                 }
12929         }
12930 }
12931
12932 static void
12933 check_shared_dpll_state(struct drm_device *dev)
12934 {
12935         struct drm_i915_private *dev_priv = dev->dev_private;
12936         struct intel_crtc *crtc;
12937         struct intel_dpll_hw_state dpll_hw_state;
12938         int i;
12939
12940         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12941                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12942                 int enabled_crtcs = 0, active_crtcs = 0;
12943                 bool active;
12944
12945                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12946
12947                 DRM_DEBUG_KMS("%s\n", pll->name);
12948
12949                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12950
12951                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12952                      "more active pll users than references: %i vs %i\n",
12953                      pll->active, hweight32(pll->config.crtc_mask));
12954                 I915_STATE_WARN(pll->active && !pll->on,
12955                      "pll in active use but not on in sw tracking\n");
12956                 I915_STATE_WARN(pll->on && !pll->active,
12957                      "pll in on but not on in use in sw tracking\n");
12958                 I915_STATE_WARN(pll->on != active,
12959                      "pll on state mismatch (expected %i, found %i)\n",
12960                      pll->on, active);
12961
12962                 for_each_intel_crtc(dev, crtc) {
12963                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12964                                 enabled_crtcs++;
12965                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12966                                 active_crtcs++;
12967                 }
12968                 I915_STATE_WARN(pll->active != active_crtcs,
12969                      "pll active crtcs mismatch (expected %i, found %i)\n",
12970                      pll->active, active_crtcs);
12971                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12972                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12973                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12974
12975                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12976                                        sizeof(dpll_hw_state)),
12977                      "pll hw state mismatch\n");
12978         }
12979 }
12980
12981 static void
12982 intel_modeset_check_state(struct drm_device *dev,
12983                           struct drm_atomic_state *old_state)
12984 {
12985         check_wm_state(dev);
12986         check_connector_state(dev, old_state);
12987         check_encoder_state(dev);
12988         check_crtc_state(dev, old_state);
12989         check_shared_dpll_state(dev);
12990 }
12991
12992 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12993                                      int dotclock)
12994 {
12995         /*
12996          * FDI already provided one idea for the dotclock.
12997          * Yell if the encoder disagrees.
12998          */
12999         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13000              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13001              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13002 }
13003
13004 static void update_scanline_offset(struct intel_crtc *crtc)
13005 {
13006         struct drm_device *dev = crtc->base.dev;
13007
13008         /*
13009          * The scanline counter increments at the leading edge of hsync.
13010          *
13011          * On most platforms it starts counting from vtotal-1 on the
13012          * first active line. That means the scanline counter value is
13013          * always one less than what we would expect. Ie. just after
13014          * start of vblank, which also occurs at start of hsync (on the
13015          * last active line), the scanline counter will read vblank_start-1.
13016          *
13017          * On gen2 the scanline counter starts counting from 1 instead
13018          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13019          * to keep the value positive), instead of adding one.
13020          *
13021          * On HSW+ the behaviour of the scanline counter depends on the output
13022          * type. For DP ports it behaves like most other platforms, but on HDMI
13023          * there's an extra 1 line difference. So we need to add two instead of
13024          * one to the value.
13025          */
13026         if (IS_GEN2(dev)) {
13027                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13028                 int vtotal;
13029
13030                 vtotal = adjusted_mode->crtc_vtotal;
13031                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13032                         vtotal /= 2;
13033
13034                 crtc->scanline_offset = vtotal - 1;
13035         } else if (HAS_DDI(dev) &&
13036                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13037                 crtc->scanline_offset = 2;
13038         } else
13039                 crtc->scanline_offset = 1;
13040 }
13041
13042 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13043 {
13044         struct drm_device *dev = state->dev;
13045         struct drm_i915_private *dev_priv = to_i915(dev);
13046         struct intel_shared_dpll_config *shared_dpll = NULL;
13047         struct drm_crtc *crtc;
13048         struct drm_crtc_state *crtc_state;
13049         int i;
13050
13051         if (!dev_priv->display.crtc_compute_clock)
13052                 return;
13053
13054         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13055                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13056                 int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll;
13057
13058                 if (!needs_modeset(crtc_state))
13059                         continue;
13060
13061                 to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE;
13062
13063                 if (old_dpll == DPLL_ID_PRIVATE)
13064                         continue;
13065
13066                 if (!shared_dpll)
13067                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13068
13069                 shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13070         }
13071 }
13072
13073 /*
13074  * This implements the workaround described in the "notes" section of the mode
13075  * set sequence documentation. When going from no pipes or single pipe to
13076  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13077  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13078  */
13079 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13080 {
13081         struct drm_crtc_state *crtc_state;
13082         struct intel_crtc *intel_crtc;
13083         struct drm_crtc *crtc;
13084         struct intel_crtc_state *first_crtc_state = NULL;
13085         struct intel_crtc_state *other_crtc_state = NULL;
13086         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13087         int i;
13088
13089         /* look at all crtc's that are going to be enabled in during modeset */
13090         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13091                 intel_crtc = to_intel_crtc(crtc);
13092
13093                 if (!crtc_state->active || !needs_modeset(crtc_state))
13094                         continue;
13095
13096                 if (first_crtc_state) {
13097                         other_crtc_state = to_intel_crtc_state(crtc_state);
13098                         break;
13099                 } else {
13100                         first_crtc_state = to_intel_crtc_state(crtc_state);
13101                         first_pipe = intel_crtc->pipe;
13102                 }
13103         }
13104
13105         /* No workaround needed? */
13106         if (!first_crtc_state)
13107                 return 0;
13108
13109         /* w/a possibly needed, check how many crtc's are already enabled. */
13110         for_each_intel_crtc(state->dev, intel_crtc) {
13111                 struct intel_crtc_state *pipe_config;
13112
13113                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13114                 if (IS_ERR(pipe_config))
13115                         return PTR_ERR(pipe_config);
13116
13117                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13118
13119                 if (!pipe_config->base.active ||
13120                     needs_modeset(&pipe_config->base))
13121                         continue;
13122
13123                 /* 2 or more enabled crtcs means no need for w/a */
13124                 if (enabled_pipe != INVALID_PIPE)
13125                         return 0;
13126
13127                 enabled_pipe = intel_crtc->pipe;
13128         }
13129
13130         if (enabled_pipe != INVALID_PIPE)
13131                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13132         else if (other_crtc_state)
13133                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13134
13135         return 0;
13136 }
13137
13138 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13139 {
13140         struct drm_crtc *crtc;
13141         struct drm_crtc_state *crtc_state;
13142         int ret = 0;
13143
13144         /* add all active pipes to the state */
13145         for_each_crtc(state->dev, crtc) {
13146                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13147                 if (IS_ERR(crtc_state))
13148                         return PTR_ERR(crtc_state);
13149
13150                 if (!crtc_state->active || needs_modeset(crtc_state))
13151                         continue;
13152
13153                 crtc_state->mode_changed = true;
13154
13155                 ret = drm_atomic_add_affected_connectors(state, crtc);
13156                 if (ret)
13157                         break;
13158
13159                 ret = drm_atomic_add_affected_planes(state, crtc);
13160                 if (ret)
13161                         break;
13162         }
13163
13164         return ret;
13165 }
13166
13167 static int intel_modeset_checks(struct drm_atomic_state *state)
13168 {
13169         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13170         struct drm_i915_private *dev_priv = state->dev->dev_private;
13171         struct drm_crtc *crtc;
13172         struct drm_crtc_state *crtc_state;
13173         int ret = 0, i;
13174
13175         if (!check_digital_port_conflicts(state)) {
13176                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13177                 return -EINVAL;
13178         }
13179
13180         intel_state->modeset = true;
13181         intel_state->active_crtcs = dev_priv->active_crtcs;
13182
13183         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13184                 if (crtc_state->active)
13185                         intel_state->active_crtcs |= 1 << i;
13186                 else
13187                         intel_state->active_crtcs &= ~(1 << i);
13188         }
13189
13190         /*
13191          * See if the config requires any additional preparation, e.g.
13192          * to adjust global state with pipes off.  We need to do this
13193          * here so we can get the modeset_pipe updated config for the new
13194          * mode set on this crtc.  For other crtcs we need to use the
13195          * adjusted_mode bits in the crtc directly.
13196          */
13197         if (dev_priv->display.modeset_calc_cdclk) {
13198                 ret = dev_priv->display.modeset_calc_cdclk(state);
13199
13200                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13201                         ret = intel_modeset_all_pipes(state);
13202
13203                 if (ret < 0)
13204                         return ret;
13205
13206                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13207                               intel_state->cdclk, intel_state->dev_cdclk);
13208         } else
13209                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13210
13211         intel_modeset_clear_plls(state);
13212
13213         if (IS_HASWELL(dev_priv))
13214                 return haswell_mode_set_planes_workaround(state);
13215
13216         return 0;
13217 }
13218
13219 /*
13220  * Handle calculation of various watermark data at the end of the atomic check
13221  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13222  * handlers to ensure that all derived state has been updated.
13223  */
13224 static void calc_watermark_data(struct drm_atomic_state *state)
13225 {
13226         struct drm_device *dev = state->dev;
13227         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13228         struct drm_crtc *crtc;
13229         struct drm_crtc_state *cstate;
13230         struct drm_plane *plane;
13231         struct drm_plane_state *pstate;
13232
13233         /*
13234          * Calculate watermark configuration details now that derived
13235          * plane/crtc state is all properly updated.
13236          */
13237         drm_for_each_crtc(crtc, dev) {
13238                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13239                         crtc->state;
13240
13241                 if (cstate->active)
13242                         intel_state->wm_config.num_pipes_active++;
13243         }
13244         drm_for_each_legacy_plane(plane, dev) {
13245                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13246                         plane->state;
13247
13248                 if (!to_intel_plane_state(pstate)->visible)
13249                         continue;
13250
13251                 intel_state->wm_config.sprites_enabled = true;
13252                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13253                     pstate->crtc_h != pstate->src_h >> 16)
13254                         intel_state->wm_config.sprites_scaled = true;
13255         }
13256 }
13257
13258 /**
13259  * intel_atomic_check - validate state object
13260  * @dev: drm device
13261  * @state: state to validate
13262  */
13263 static int intel_atomic_check(struct drm_device *dev,
13264                               struct drm_atomic_state *state)
13265 {
13266         struct drm_i915_private *dev_priv = to_i915(dev);
13267         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13268         struct drm_crtc *crtc;
13269         struct drm_crtc_state *crtc_state;
13270         int ret, i;
13271         bool any_ms = false;
13272
13273         ret = drm_atomic_helper_check_modeset(dev, state);
13274         if (ret)
13275                 return ret;
13276
13277         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13278                 struct intel_crtc_state *pipe_config =
13279                         to_intel_crtc_state(crtc_state);
13280
13281                 memset(&to_intel_crtc(crtc)->atomic, 0,
13282                        sizeof(struct intel_crtc_atomic_commit));
13283
13284                 /* Catch I915_MODE_FLAG_INHERITED */
13285                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13286                         crtc_state->mode_changed = true;
13287
13288                 if (!crtc_state->enable) {
13289                         if (needs_modeset(crtc_state))
13290                                 any_ms = true;
13291                         continue;
13292                 }
13293
13294                 if (!needs_modeset(crtc_state))
13295                         continue;
13296
13297                 /* FIXME: For only active_changed we shouldn't need to do any
13298                  * state recomputation at all. */
13299
13300                 ret = drm_atomic_add_affected_connectors(state, crtc);
13301                 if (ret)
13302                         return ret;
13303
13304                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13305                 if (ret)
13306                         return ret;
13307
13308                 if (i915.fastboot &&
13309                     intel_pipe_config_compare(dev,
13310                                         to_intel_crtc_state(crtc->state),
13311                                         pipe_config, true)) {
13312                         crtc_state->mode_changed = false;
13313                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13314                 }
13315
13316                 if (needs_modeset(crtc_state)) {
13317                         any_ms = true;
13318
13319                         ret = drm_atomic_add_affected_planes(state, crtc);
13320                         if (ret)
13321                                 return ret;
13322                 }
13323
13324                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13325                                        needs_modeset(crtc_state) ?
13326                                        "[modeset]" : "[fastset]");
13327         }
13328
13329         if (any_ms) {
13330                 ret = intel_modeset_checks(state);
13331
13332                 if (ret)
13333                         return ret;
13334         } else
13335                 intel_state->cdclk = dev_priv->cdclk_freq;
13336
13337         ret = drm_atomic_helper_check_planes(dev, state);
13338         if (ret)
13339                 return ret;
13340
13341         intel_fbc_choose_crtc(dev_priv, state);
13342         calc_watermark_data(state);
13343
13344         return 0;
13345 }
13346
13347 static int intel_atomic_prepare_commit(struct drm_device *dev,
13348                                        struct drm_atomic_state *state,
13349                                        bool async)
13350 {
13351         struct drm_i915_private *dev_priv = dev->dev_private;
13352         struct drm_plane_state *plane_state;
13353         struct drm_crtc_state *crtc_state;
13354         struct drm_plane *plane;
13355         struct drm_crtc *crtc;
13356         int i, ret;
13357
13358         if (async) {
13359                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13360                 return -EINVAL;
13361         }
13362
13363         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13364                 ret = intel_crtc_wait_for_pending_flips(crtc);
13365                 if (ret)
13366                         return ret;
13367
13368                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13369                         flush_workqueue(dev_priv->wq);
13370         }
13371
13372         ret = mutex_lock_interruptible(&dev->struct_mutex);
13373         if (ret)
13374                 return ret;
13375
13376         ret = drm_atomic_helper_prepare_planes(dev, state);
13377         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13378                 u32 reset_counter;
13379
13380                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13381                 mutex_unlock(&dev->struct_mutex);
13382
13383                 for_each_plane_in_state(state, plane, plane_state, i) {
13384                         struct intel_plane_state *intel_plane_state =
13385                                 to_intel_plane_state(plane_state);
13386
13387                         if (!intel_plane_state->wait_req)
13388                                 continue;
13389
13390                         ret = __i915_wait_request(intel_plane_state->wait_req,
13391                                                   reset_counter, true,
13392                                                   NULL, NULL);
13393
13394                         /* Swallow -EIO errors to allow updates during hw lockup. */
13395                         if (ret == -EIO)
13396                                 ret = 0;
13397
13398                         if (ret)
13399                                 break;
13400                 }
13401
13402                 if (!ret)
13403                         return 0;
13404
13405                 mutex_lock(&dev->struct_mutex);
13406                 drm_atomic_helper_cleanup_planes(dev, state);
13407         }
13408
13409         mutex_unlock(&dev->struct_mutex);
13410         return ret;
13411 }
13412
13413 /**
13414  * intel_atomic_commit - commit validated state object
13415  * @dev: DRM device
13416  * @state: the top-level driver state object
13417  * @async: asynchronous commit
13418  *
13419  * This function commits a top-level state object that has been validated
13420  * with drm_atomic_helper_check().
13421  *
13422  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13423  * we can only handle plane-related operations and do not yet support
13424  * asynchronous commit.
13425  *
13426  * RETURNS
13427  * Zero for success or -errno.
13428  */
13429 static int intel_atomic_commit(struct drm_device *dev,
13430                                struct drm_atomic_state *state,
13431                                bool async)
13432 {
13433         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13434         struct drm_i915_private *dev_priv = dev->dev_private;
13435         struct drm_crtc_state *crtc_state;
13436         struct drm_crtc *crtc;
13437         int ret = 0, i;
13438         bool hw_check = intel_state->modeset;
13439         unsigned long put_domains[I915_MAX_PIPES] = {};
13440
13441         ret = intel_atomic_prepare_commit(dev, state, async);
13442         if (ret) {
13443                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13444                 return ret;
13445         }
13446
13447         drm_atomic_helper_swap_state(dev, state);
13448         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13449
13450         if (intel_state->modeset) {
13451                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13452                        sizeof(intel_state->min_pixclk));
13453                 dev_priv->active_crtcs = intel_state->active_crtcs;
13454                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13455
13456                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13457         }
13458
13459         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13460                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13461
13462                 if (needs_modeset(crtc->state) ||
13463                     to_intel_crtc_state(crtc->state)->update_pipe) {
13464                         hw_check = true;
13465
13466                         put_domains[to_intel_crtc(crtc)->pipe] =
13467                                 modeset_get_crtc_power_domains(crtc,
13468                                         to_intel_crtc_state(crtc->state));
13469                 }
13470
13471                 if (!needs_modeset(crtc->state))
13472                         continue;
13473
13474                 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13475
13476                 if (crtc_state->active) {
13477                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13478                         dev_priv->display.crtc_disable(crtc);
13479                         intel_crtc->active = false;
13480                         intel_fbc_disable(intel_crtc);
13481                         intel_disable_shared_dpll(intel_crtc);
13482
13483                         /*
13484                          * Underruns don't always raise
13485                          * interrupts, so check manually.
13486                          */
13487                         intel_check_cpu_fifo_underruns(dev_priv);
13488                         intel_check_pch_fifo_underruns(dev_priv);
13489
13490                         if (!crtc->state->active)
13491                                 intel_update_watermarks(crtc);
13492                 }
13493         }
13494
13495         /* Only after disabling all output pipelines that will be changed can we
13496          * update the the output configuration. */
13497         intel_modeset_update_crtc_state(state);
13498
13499         if (intel_state->modeset) {
13500                 intel_shared_dpll_commit(state);
13501
13502                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13503
13504                 if (dev_priv->display.modeset_commit_cdclk &&
13505                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13506                         dev_priv->display.modeset_commit_cdclk(state);
13507         }
13508
13509         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13510         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13511                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13512                 bool modeset = needs_modeset(crtc->state);
13513                 bool update_pipe = !modeset &&
13514                         to_intel_crtc_state(crtc->state)->update_pipe;
13515
13516                 if (modeset && crtc->state->active) {
13517                         update_scanline_offset(to_intel_crtc(crtc));
13518                         dev_priv->display.crtc_enable(crtc);
13519                 }
13520
13521                 if (!modeset)
13522                         intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13523
13524                 if (crtc->state->active && intel_crtc->atomic.update_fbc)
13525                         intel_fbc_enable(intel_crtc);
13526
13527                 if (crtc->state->active &&
13528                     (crtc->state->planes_changed || update_pipe))
13529                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13530
13531                 intel_post_plane_update(intel_crtc);
13532         }
13533
13534         /* FIXME: add subpixel order */
13535
13536         drm_atomic_helper_wait_for_vblanks(dev, state);
13537
13538         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13539                 if (put_domains[i])
13540                         modeset_put_power_domains(dev_priv, put_domains[i]);
13541         }
13542
13543         if (intel_state->modeset)
13544                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13545
13546         mutex_lock(&dev->struct_mutex);
13547         drm_atomic_helper_cleanup_planes(dev, state);
13548         mutex_unlock(&dev->struct_mutex);
13549
13550         if (hw_check)
13551                 intel_modeset_check_state(dev, state);
13552
13553         drm_atomic_state_free(state);
13554
13555         /* As one of the primary mmio accessors, KMS has a high likelihood
13556          * of triggering bugs in unclaimed access. After we finish
13557          * modesetting, see if an error has been flagged, and if so
13558          * enable debugging for the next modeset - and hope we catch
13559          * the culprit.
13560          *
13561          * XXX note that we assume display power is on at this point.
13562          * This might hold true now but we need to add pm helper to check
13563          * unclaimed only when the hardware is on, as atomic commits
13564          * can happen also when the device is completely off.
13565          */
13566         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13567
13568         return 0;
13569 }
13570
13571 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13572 {
13573         struct drm_device *dev = crtc->dev;
13574         struct drm_atomic_state *state;
13575         struct drm_crtc_state *crtc_state;
13576         int ret;
13577
13578         state = drm_atomic_state_alloc(dev);
13579         if (!state) {
13580                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13581                               crtc->base.id);
13582                 return;
13583         }
13584
13585         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13586
13587 retry:
13588         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13589         ret = PTR_ERR_OR_ZERO(crtc_state);
13590         if (!ret) {
13591                 if (!crtc_state->active)
13592                         goto out;
13593
13594                 crtc_state->mode_changed = true;
13595                 ret = drm_atomic_commit(state);
13596         }
13597
13598         if (ret == -EDEADLK) {
13599                 drm_atomic_state_clear(state);
13600                 drm_modeset_backoff(state->acquire_ctx);
13601                 goto retry;
13602         }
13603
13604         if (ret)
13605 out:
13606                 drm_atomic_state_free(state);
13607 }
13608
13609 #undef for_each_intel_crtc_masked
13610
13611 static const struct drm_crtc_funcs intel_crtc_funcs = {
13612         .gamma_set = intel_crtc_gamma_set,
13613         .set_config = drm_atomic_helper_set_config,
13614         .destroy = intel_crtc_destroy,
13615         .page_flip = intel_crtc_page_flip,
13616         .atomic_duplicate_state = intel_crtc_duplicate_state,
13617         .atomic_destroy_state = intel_crtc_destroy_state,
13618 };
13619
13620 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13621                                       struct intel_shared_dpll *pll,
13622                                       struct intel_dpll_hw_state *hw_state)
13623 {
13624         uint32_t val;
13625
13626         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
13627                 return false;
13628
13629         val = I915_READ(PCH_DPLL(pll->id));
13630         hw_state->dpll = val;
13631         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13632         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13633
13634         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
13635
13636         return val & DPLL_VCO_ENABLE;
13637 }
13638
13639 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13640                                   struct intel_shared_dpll *pll)
13641 {
13642         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13643         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13644 }
13645
13646 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13647                                 struct intel_shared_dpll *pll)
13648 {
13649         /* PCH refclock must be enabled first */
13650         ibx_assert_pch_refclk_enabled(dev_priv);
13651
13652         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13653
13654         /* Wait for the clocks to stabilize. */
13655         POSTING_READ(PCH_DPLL(pll->id));
13656         udelay(150);
13657
13658         /* The pixel multiplier can only be updated once the
13659          * DPLL is enabled and the clocks are stable.
13660          *
13661          * So write it again.
13662          */
13663         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13664         POSTING_READ(PCH_DPLL(pll->id));
13665         udelay(200);
13666 }
13667
13668 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13669                                  struct intel_shared_dpll *pll)
13670 {
13671         struct drm_device *dev = dev_priv->dev;
13672         struct intel_crtc *crtc;
13673
13674         /* Make sure no transcoder isn't still depending on us. */
13675         for_each_intel_crtc(dev, crtc) {
13676                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13677                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13678         }
13679
13680         I915_WRITE(PCH_DPLL(pll->id), 0);
13681         POSTING_READ(PCH_DPLL(pll->id));
13682         udelay(200);
13683 }
13684
13685 static char *ibx_pch_dpll_names[] = {
13686         "PCH DPLL A",
13687         "PCH DPLL B",
13688 };
13689
13690 static void ibx_pch_dpll_init(struct drm_device *dev)
13691 {
13692         struct drm_i915_private *dev_priv = dev->dev_private;
13693         int i;
13694
13695         dev_priv->num_shared_dpll = 2;
13696
13697         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13698                 dev_priv->shared_dplls[i].id = i;
13699                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13700                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13701                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13702                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13703                 dev_priv->shared_dplls[i].get_hw_state =
13704                         ibx_pch_dpll_get_hw_state;
13705         }
13706 }
13707
13708 static void intel_shared_dpll_init(struct drm_device *dev)
13709 {
13710         struct drm_i915_private *dev_priv = dev->dev_private;
13711
13712         if (HAS_DDI(dev))
13713                 intel_ddi_pll_init(dev);
13714         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13715                 ibx_pch_dpll_init(dev);
13716         else
13717                 dev_priv->num_shared_dpll = 0;
13718
13719         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13720 }
13721
13722 /**
13723  * intel_prepare_plane_fb - Prepare fb for usage on plane
13724  * @plane: drm plane to prepare for
13725  * @fb: framebuffer to prepare for presentation
13726  *
13727  * Prepares a framebuffer for usage on a display plane.  Generally this
13728  * involves pinning the underlying object and updating the frontbuffer tracking
13729  * bits.  Some older platforms need special physical address handling for
13730  * cursor planes.
13731  *
13732  * Must be called with struct_mutex held.
13733  *
13734  * Returns 0 on success, negative error code on failure.
13735  */
13736 int
13737 intel_prepare_plane_fb(struct drm_plane *plane,
13738                        const struct drm_plane_state *new_state)
13739 {
13740         struct drm_device *dev = plane->dev;
13741         struct drm_framebuffer *fb = new_state->fb;
13742         struct intel_plane *intel_plane = to_intel_plane(plane);
13743         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13744         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13745         int ret = 0;
13746
13747         if (!obj && !old_obj)
13748                 return 0;
13749
13750         if (old_obj) {
13751                 struct drm_crtc_state *crtc_state =
13752                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13753
13754                 /* Big Hammer, we also need to ensure that any pending
13755                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13756                  * current scanout is retired before unpinning the old
13757                  * framebuffer. Note that we rely on userspace rendering
13758                  * into the buffer attached to the pipe they are waiting
13759                  * on. If not, userspace generates a GPU hang with IPEHR
13760                  * point to the MI_WAIT_FOR_EVENT.
13761                  *
13762                  * This should only fail upon a hung GPU, in which case we
13763                  * can safely continue.
13764                  */
13765                 if (needs_modeset(crtc_state))
13766                         ret = i915_gem_object_wait_rendering(old_obj, true);
13767
13768                 /* Swallow -EIO errors to allow updates during hw lockup. */
13769                 if (ret && ret != -EIO)
13770                         return ret;
13771         }
13772
13773         /* For framebuffer backed by dmabuf, wait for fence */
13774         if (obj && obj->base.dma_buf) {
13775                 long lret;
13776
13777                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13778                                                            false, true,
13779                                                            MAX_SCHEDULE_TIMEOUT);
13780                 if (lret == -ERESTARTSYS)
13781                         return lret;
13782
13783                 WARN(lret < 0, "waiting returns %li\n", lret);
13784         }
13785
13786         if (!obj) {
13787                 ret = 0;
13788         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13789             INTEL_INFO(dev)->cursor_needs_physical) {
13790                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13791                 ret = i915_gem_object_attach_phys(obj, align);
13792                 if (ret)
13793                         DRM_DEBUG_KMS("failed to attach phys object\n");
13794         } else {
13795                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13796         }
13797
13798         if (ret == 0) {
13799                 if (obj) {
13800                         struct intel_plane_state *plane_state =
13801                                 to_intel_plane_state(new_state);
13802
13803                         i915_gem_request_assign(&plane_state->wait_req,
13804                                                 obj->last_write_req);
13805                 }
13806
13807                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13808         }
13809
13810         return ret;
13811 }
13812
13813 /**
13814  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13815  * @plane: drm plane to clean up for
13816  * @fb: old framebuffer that was on plane
13817  *
13818  * Cleans up a framebuffer that has just been removed from a plane.
13819  *
13820  * Must be called with struct_mutex held.
13821  */
13822 void
13823 intel_cleanup_plane_fb(struct drm_plane *plane,
13824                        const struct drm_plane_state *old_state)
13825 {
13826         struct drm_device *dev = plane->dev;
13827         struct intel_plane *intel_plane = to_intel_plane(plane);
13828         struct intel_plane_state *old_intel_state;
13829         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13830         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13831
13832         old_intel_state = to_intel_plane_state(old_state);
13833
13834         if (!obj && !old_obj)
13835                 return;
13836
13837         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13838             !INTEL_INFO(dev)->cursor_needs_physical))
13839                 intel_unpin_fb_obj(old_state->fb, old_state);
13840
13841         /* prepare_fb aborted? */
13842         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13843             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13844                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13845
13846         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13847
13848 }
13849
13850 int
13851 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13852 {
13853         int max_scale;
13854         struct drm_device *dev;
13855         struct drm_i915_private *dev_priv;
13856         int crtc_clock, cdclk;
13857
13858         if (!intel_crtc || !crtc_state->base.enable)
13859                 return DRM_PLANE_HELPER_NO_SCALING;
13860
13861         dev = intel_crtc->base.dev;
13862         dev_priv = dev->dev_private;
13863         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13864         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13865
13866         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13867                 return DRM_PLANE_HELPER_NO_SCALING;
13868
13869         /*
13870          * skl max scale is lower of:
13871          *    close to 3 but not 3, -1 is for that purpose
13872          *            or
13873          *    cdclk/crtc_clock
13874          */
13875         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13876
13877         return max_scale;
13878 }
13879
13880 static int
13881 intel_check_primary_plane(struct drm_plane *plane,
13882                           struct intel_crtc_state *crtc_state,
13883                           struct intel_plane_state *state)
13884 {
13885         struct drm_crtc *crtc = state->base.crtc;
13886         struct drm_framebuffer *fb = state->base.fb;
13887         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13888         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13889         bool can_position = false;
13890
13891         if (INTEL_INFO(plane->dev)->gen >= 9) {
13892                 /* use scaler when colorkey is not required */
13893                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13894                         min_scale = 1;
13895                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13896                 }
13897                 can_position = true;
13898         }
13899
13900         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13901                                              &state->dst, &state->clip,
13902                                              min_scale, max_scale,
13903                                              can_position, true,
13904                                              &state->visible);
13905 }
13906
13907 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13908                                     struct drm_crtc_state *old_crtc_state)
13909 {
13910         struct drm_device *dev = crtc->dev;
13911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13912         struct intel_crtc_state *old_intel_state =
13913                 to_intel_crtc_state(old_crtc_state);
13914         bool modeset = needs_modeset(crtc->state);
13915
13916         /* Perform vblank evasion around commit operation */
13917         intel_pipe_update_start(intel_crtc);
13918
13919         if (modeset)
13920                 return;
13921
13922         if (to_intel_crtc_state(crtc->state)->update_pipe)
13923                 intel_update_pipe_config(intel_crtc, old_intel_state);
13924         else if (INTEL_INFO(dev)->gen >= 9)
13925                 skl_detach_scalers(intel_crtc);
13926 }
13927
13928 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13929                                      struct drm_crtc_state *old_crtc_state)
13930 {
13931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13932
13933         intel_pipe_update_end(intel_crtc);
13934 }
13935
13936 /**
13937  * intel_plane_destroy - destroy a plane
13938  * @plane: plane to destroy
13939  *
13940  * Common destruction function for all types of planes (primary, cursor,
13941  * sprite).
13942  */
13943 void intel_plane_destroy(struct drm_plane *plane)
13944 {
13945         struct intel_plane *intel_plane = to_intel_plane(plane);
13946         drm_plane_cleanup(plane);
13947         kfree(intel_plane);
13948 }
13949
13950 const struct drm_plane_funcs intel_plane_funcs = {
13951         .update_plane = drm_atomic_helper_update_plane,
13952         .disable_plane = drm_atomic_helper_disable_plane,
13953         .destroy = intel_plane_destroy,
13954         .set_property = drm_atomic_helper_plane_set_property,
13955         .atomic_get_property = intel_plane_atomic_get_property,
13956         .atomic_set_property = intel_plane_atomic_set_property,
13957         .atomic_duplicate_state = intel_plane_duplicate_state,
13958         .atomic_destroy_state = intel_plane_destroy_state,
13959
13960 };
13961
13962 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13963                                                     int pipe)
13964 {
13965         struct intel_plane *primary;
13966         struct intel_plane_state *state;
13967         const uint32_t *intel_primary_formats;
13968         unsigned int num_formats;
13969
13970         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13971         if (primary == NULL)
13972                 return NULL;
13973
13974         state = intel_create_plane_state(&primary->base);
13975         if (!state) {
13976                 kfree(primary);
13977                 return NULL;
13978         }
13979         primary->base.state = &state->base;
13980
13981         primary->can_scale = false;
13982         primary->max_downscale = 1;
13983         if (INTEL_INFO(dev)->gen >= 9) {
13984                 primary->can_scale = true;
13985                 state->scaler_id = -1;
13986         }
13987         primary->pipe = pipe;
13988         primary->plane = pipe;
13989         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13990         primary->check_plane = intel_check_primary_plane;
13991         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13992                 primary->plane = !pipe;
13993
13994         if (INTEL_INFO(dev)->gen >= 9) {
13995                 intel_primary_formats = skl_primary_formats;
13996                 num_formats = ARRAY_SIZE(skl_primary_formats);
13997
13998                 primary->update_plane = skylake_update_primary_plane;
13999                 primary->disable_plane = skylake_disable_primary_plane;
14000         } else if (HAS_PCH_SPLIT(dev)) {
14001                 intel_primary_formats = i965_primary_formats;
14002                 num_formats = ARRAY_SIZE(i965_primary_formats);
14003
14004                 primary->update_plane = ironlake_update_primary_plane;
14005                 primary->disable_plane = i9xx_disable_primary_plane;
14006         } else if (INTEL_INFO(dev)->gen >= 4) {
14007                 intel_primary_formats = i965_primary_formats;
14008                 num_formats = ARRAY_SIZE(i965_primary_formats);
14009
14010                 primary->update_plane = i9xx_update_primary_plane;
14011                 primary->disable_plane = i9xx_disable_primary_plane;
14012         } else {
14013                 intel_primary_formats = i8xx_primary_formats;
14014                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14015
14016                 primary->update_plane = i9xx_update_primary_plane;
14017                 primary->disable_plane = i9xx_disable_primary_plane;
14018         }
14019
14020         drm_universal_plane_init(dev, &primary->base, 0,
14021                                  &intel_plane_funcs,
14022                                  intel_primary_formats, num_formats,
14023                                  DRM_PLANE_TYPE_PRIMARY, NULL);
14024
14025         if (INTEL_INFO(dev)->gen >= 4)
14026                 intel_create_rotation_property(dev, primary);
14027
14028         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14029
14030         return &primary->base;
14031 }
14032
14033 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14034 {
14035         if (!dev->mode_config.rotation_property) {
14036                 unsigned long flags = BIT(DRM_ROTATE_0) |
14037                         BIT(DRM_ROTATE_180);
14038
14039                 if (INTEL_INFO(dev)->gen >= 9)
14040                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14041
14042                 dev->mode_config.rotation_property =
14043                         drm_mode_create_rotation_property(dev, flags);
14044         }
14045         if (dev->mode_config.rotation_property)
14046                 drm_object_attach_property(&plane->base.base,
14047                                 dev->mode_config.rotation_property,
14048                                 plane->base.state->rotation);
14049 }
14050
14051 static int
14052 intel_check_cursor_plane(struct drm_plane *plane,
14053                          struct intel_crtc_state *crtc_state,
14054                          struct intel_plane_state *state)
14055 {
14056         struct drm_crtc *crtc = crtc_state->base.crtc;
14057         struct drm_framebuffer *fb = state->base.fb;
14058         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14059         enum pipe pipe = to_intel_plane(plane)->pipe;
14060         unsigned stride;
14061         int ret;
14062
14063         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14064                                             &state->dst, &state->clip,
14065                                             DRM_PLANE_HELPER_NO_SCALING,
14066                                             DRM_PLANE_HELPER_NO_SCALING,
14067                                             true, true, &state->visible);
14068         if (ret)
14069                 return ret;
14070
14071         /* if we want to turn off the cursor ignore width and height */
14072         if (!obj)
14073                 return 0;
14074
14075         /* Check for which cursor types we support */
14076         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14077                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14078                           state->base.crtc_w, state->base.crtc_h);
14079                 return -EINVAL;
14080         }
14081
14082         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14083         if (obj->base.size < stride * state->base.crtc_h) {
14084                 DRM_DEBUG_KMS("buffer is too small\n");
14085                 return -ENOMEM;
14086         }
14087
14088         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14089                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14090                 return -EINVAL;
14091         }
14092
14093         /*
14094          * There's something wrong with the cursor on CHV pipe C.
14095          * If it straddles the left edge of the screen then
14096          * moving it away from the edge or disabling it often
14097          * results in a pipe underrun, and often that can lead to
14098          * dead pipe (constant underrun reported, and it scans
14099          * out just a solid color). To recover from that, the
14100          * display power well must be turned off and on again.
14101          * Refuse the put the cursor into that compromised position.
14102          */
14103         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14104             state->visible && state->base.crtc_x < 0) {
14105                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14106                 return -EINVAL;
14107         }
14108
14109         return 0;
14110 }
14111
14112 static void
14113 intel_disable_cursor_plane(struct drm_plane *plane,
14114                            struct drm_crtc *crtc)
14115 {
14116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14117
14118         intel_crtc->cursor_addr = 0;
14119         intel_crtc_update_cursor(crtc, NULL);
14120 }
14121
14122 static void
14123 intel_update_cursor_plane(struct drm_plane *plane,
14124                           const struct intel_crtc_state *crtc_state,
14125                           const struct intel_plane_state *state)
14126 {
14127         struct drm_crtc *crtc = crtc_state->base.crtc;
14128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14129         struct drm_device *dev = plane->dev;
14130         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14131         uint32_t addr;
14132
14133         if (!obj)
14134                 addr = 0;
14135         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14136                 addr = i915_gem_obj_ggtt_offset(obj);
14137         else
14138                 addr = obj->phys_handle->busaddr;
14139
14140         intel_crtc->cursor_addr = addr;
14141         intel_crtc_update_cursor(crtc, state);
14142 }
14143
14144 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14145                                                    int pipe)
14146 {
14147         struct intel_plane *cursor;
14148         struct intel_plane_state *state;
14149
14150         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14151         if (cursor == NULL)
14152                 return NULL;
14153
14154         state = intel_create_plane_state(&cursor->base);
14155         if (!state) {
14156                 kfree(cursor);
14157                 return NULL;
14158         }
14159         cursor->base.state = &state->base;
14160
14161         cursor->can_scale = false;
14162         cursor->max_downscale = 1;
14163         cursor->pipe = pipe;
14164         cursor->plane = pipe;
14165         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14166         cursor->check_plane = intel_check_cursor_plane;
14167         cursor->update_plane = intel_update_cursor_plane;
14168         cursor->disable_plane = intel_disable_cursor_plane;
14169
14170         drm_universal_plane_init(dev, &cursor->base, 0,
14171                                  &intel_plane_funcs,
14172                                  intel_cursor_formats,
14173                                  ARRAY_SIZE(intel_cursor_formats),
14174                                  DRM_PLANE_TYPE_CURSOR, NULL);
14175
14176         if (INTEL_INFO(dev)->gen >= 4) {
14177                 if (!dev->mode_config.rotation_property)
14178                         dev->mode_config.rotation_property =
14179                                 drm_mode_create_rotation_property(dev,
14180                                                         BIT(DRM_ROTATE_0) |
14181                                                         BIT(DRM_ROTATE_180));
14182                 if (dev->mode_config.rotation_property)
14183                         drm_object_attach_property(&cursor->base.base,
14184                                 dev->mode_config.rotation_property,
14185                                 state->base.rotation);
14186         }
14187
14188         if (INTEL_INFO(dev)->gen >=9)
14189                 state->scaler_id = -1;
14190
14191         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14192
14193         return &cursor->base;
14194 }
14195
14196 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14197         struct intel_crtc_state *crtc_state)
14198 {
14199         int i;
14200         struct intel_scaler *intel_scaler;
14201         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14202
14203         for (i = 0; i < intel_crtc->num_scalers; i++) {
14204                 intel_scaler = &scaler_state->scalers[i];
14205                 intel_scaler->in_use = 0;
14206                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14207         }
14208
14209         scaler_state->scaler_id = -1;
14210 }
14211
14212 static void intel_crtc_init(struct drm_device *dev, int pipe)
14213 {
14214         struct drm_i915_private *dev_priv = dev->dev_private;
14215         struct intel_crtc *intel_crtc;
14216         struct intel_crtc_state *crtc_state = NULL;
14217         struct drm_plane *primary = NULL;
14218         struct drm_plane *cursor = NULL;
14219         int i, ret;
14220
14221         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14222         if (intel_crtc == NULL)
14223                 return;
14224
14225         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14226         if (!crtc_state)
14227                 goto fail;
14228         intel_crtc->config = crtc_state;
14229         intel_crtc->base.state = &crtc_state->base;
14230         crtc_state->base.crtc = &intel_crtc->base;
14231
14232         /* initialize shared scalers */
14233         if (INTEL_INFO(dev)->gen >= 9) {
14234                 if (pipe == PIPE_C)
14235                         intel_crtc->num_scalers = 1;
14236                 else
14237                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14238
14239                 skl_init_scalers(dev, intel_crtc, crtc_state);
14240         }
14241
14242         primary = intel_primary_plane_create(dev, pipe);
14243         if (!primary)
14244                 goto fail;
14245
14246         cursor = intel_cursor_plane_create(dev, pipe);
14247         if (!cursor)
14248                 goto fail;
14249
14250         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14251                                         cursor, &intel_crtc_funcs, NULL);
14252         if (ret)
14253                 goto fail;
14254
14255         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14256         for (i = 0; i < 256; i++) {
14257                 intel_crtc->lut_r[i] = i;
14258                 intel_crtc->lut_g[i] = i;
14259                 intel_crtc->lut_b[i] = i;
14260         }
14261
14262         /*
14263          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14264          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14265          */
14266         intel_crtc->pipe = pipe;
14267         intel_crtc->plane = pipe;
14268         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14269                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14270                 intel_crtc->plane = !pipe;
14271         }
14272
14273         intel_crtc->cursor_base = ~0;
14274         intel_crtc->cursor_cntl = ~0;
14275         intel_crtc->cursor_size = ~0;
14276
14277         intel_crtc->wm.cxsr_allowed = true;
14278
14279         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14280                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14281         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14282         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14283
14284         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14285
14286         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14287         return;
14288
14289 fail:
14290         if (primary)
14291                 drm_plane_cleanup(primary);
14292         if (cursor)
14293                 drm_plane_cleanup(cursor);
14294         kfree(crtc_state);
14295         kfree(intel_crtc);
14296 }
14297
14298 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14299 {
14300         struct drm_encoder *encoder = connector->base.encoder;
14301         struct drm_device *dev = connector->base.dev;
14302
14303         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14304
14305         if (!encoder || WARN_ON(!encoder->crtc))
14306                 return INVALID_PIPE;
14307
14308         return to_intel_crtc(encoder->crtc)->pipe;
14309 }
14310
14311 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14312                                 struct drm_file *file)
14313 {
14314         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14315         struct drm_crtc *drmmode_crtc;
14316         struct intel_crtc *crtc;
14317
14318         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14319
14320         if (!drmmode_crtc) {
14321                 DRM_ERROR("no such CRTC id\n");
14322                 return -ENOENT;
14323         }
14324
14325         crtc = to_intel_crtc(drmmode_crtc);
14326         pipe_from_crtc_id->pipe = crtc->pipe;
14327
14328         return 0;
14329 }
14330
14331 static int intel_encoder_clones(struct intel_encoder *encoder)
14332 {
14333         struct drm_device *dev = encoder->base.dev;
14334         struct intel_encoder *source_encoder;
14335         int index_mask = 0;
14336         int entry = 0;
14337
14338         for_each_intel_encoder(dev, source_encoder) {
14339                 if (encoders_cloneable(encoder, source_encoder))
14340                         index_mask |= (1 << entry);
14341
14342                 entry++;
14343         }
14344
14345         return index_mask;
14346 }
14347
14348 static bool has_edp_a(struct drm_device *dev)
14349 {
14350         struct drm_i915_private *dev_priv = dev->dev_private;
14351
14352         if (!IS_MOBILE(dev))
14353                 return false;
14354
14355         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14356                 return false;
14357
14358         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14359                 return false;
14360
14361         return true;
14362 }
14363
14364 static bool intel_crt_present(struct drm_device *dev)
14365 {
14366         struct drm_i915_private *dev_priv = dev->dev_private;
14367
14368         if (INTEL_INFO(dev)->gen >= 9)
14369                 return false;
14370
14371         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14372                 return false;
14373
14374         if (IS_CHERRYVIEW(dev))
14375                 return false;
14376
14377         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14378                 return false;
14379
14380         /* DDI E can't be used if DDI A requires 4 lanes */
14381         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14382                 return false;
14383
14384         if (!dev_priv->vbt.int_crt_support)
14385                 return false;
14386
14387         return true;
14388 }
14389
14390 static void intel_setup_outputs(struct drm_device *dev)
14391 {
14392         struct drm_i915_private *dev_priv = dev->dev_private;
14393         struct intel_encoder *encoder;
14394         bool dpd_is_edp = false;
14395
14396         intel_lvds_init(dev);
14397
14398         if (intel_crt_present(dev))
14399                 intel_crt_init(dev);
14400
14401         if (IS_BROXTON(dev)) {
14402                 /*
14403                  * FIXME: Broxton doesn't support port detection via the
14404                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14405                  * detect the ports.
14406                  */
14407                 intel_ddi_init(dev, PORT_A);
14408                 intel_ddi_init(dev, PORT_B);
14409                 intel_ddi_init(dev, PORT_C);
14410         } else if (HAS_DDI(dev)) {
14411                 int found;
14412
14413                 /*
14414                  * Haswell uses DDI functions to detect digital outputs.
14415                  * On SKL pre-D0 the strap isn't connected, so we assume
14416                  * it's there.
14417                  */
14418                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14419                 /* WaIgnoreDDIAStrap: skl */
14420                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14421                         intel_ddi_init(dev, PORT_A);
14422
14423                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14424                  * register */
14425                 found = I915_READ(SFUSE_STRAP);
14426
14427                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14428                         intel_ddi_init(dev, PORT_B);
14429                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14430                         intel_ddi_init(dev, PORT_C);
14431                 if (found & SFUSE_STRAP_DDID_DETECTED)
14432                         intel_ddi_init(dev, PORT_D);
14433                 /*
14434                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14435                  */
14436                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14437                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14438                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14439                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14440                         intel_ddi_init(dev, PORT_E);
14441
14442         } else if (HAS_PCH_SPLIT(dev)) {
14443                 int found;
14444                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14445
14446                 if (has_edp_a(dev))
14447                         intel_dp_init(dev, DP_A, PORT_A);
14448
14449                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14450                         /* PCH SDVOB multiplex with HDMIB */
14451                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14452                         if (!found)
14453                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14454                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14455                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14456                 }
14457
14458                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14459                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14460
14461                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14462                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14463
14464                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14465                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14466
14467                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14468                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14469         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14470                 /*
14471                  * The DP_DETECTED bit is the latched state of the DDC
14472                  * SDA pin at boot. However since eDP doesn't require DDC
14473                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14474                  * eDP ports may have been muxed to an alternate function.
14475                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14476                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14477                  * detect eDP ports.
14478                  */
14479                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14480                     !intel_dp_is_edp(dev, PORT_B))
14481                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14482                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14483                     intel_dp_is_edp(dev, PORT_B))
14484                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14485
14486                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14487                     !intel_dp_is_edp(dev, PORT_C))
14488                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14489                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14490                     intel_dp_is_edp(dev, PORT_C))
14491                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14492
14493                 if (IS_CHERRYVIEW(dev)) {
14494                         /* eDP not supported on port D, so don't check VBT */
14495                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14496                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14497                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14498                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14499                 }
14500
14501                 intel_dsi_init(dev);
14502         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14503                 bool found = false;
14504
14505                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14506                         DRM_DEBUG_KMS("probing SDVOB\n");
14507                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14508                         if (!found && IS_G4X(dev)) {
14509                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14510                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14511                         }
14512
14513                         if (!found && IS_G4X(dev))
14514                                 intel_dp_init(dev, DP_B, PORT_B);
14515                 }
14516
14517                 /* Before G4X SDVOC doesn't have its own detect register */
14518
14519                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14520                         DRM_DEBUG_KMS("probing SDVOC\n");
14521                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14522                 }
14523
14524                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14525
14526                         if (IS_G4X(dev)) {
14527                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14528                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14529                         }
14530                         if (IS_G4X(dev))
14531                                 intel_dp_init(dev, DP_C, PORT_C);
14532                 }
14533
14534                 if (IS_G4X(dev) &&
14535                     (I915_READ(DP_D) & DP_DETECTED))
14536                         intel_dp_init(dev, DP_D, PORT_D);
14537         } else if (IS_GEN2(dev))
14538                 intel_dvo_init(dev);
14539
14540         if (SUPPORTS_TV(dev))
14541                 intel_tv_init(dev);
14542
14543         intel_psr_init(dev);
14544
14545         for_each_intel_encoder(dev, encoder) {
14546                 encoder->base.possible_crtcs = encoder->crtc_mask;
14547                 encoder->base.possible_clones =
14548                         intel_encoder_clones(encoder);
14549         }
14550
14551         intel_init_pch_refclk(dev);
14552
14553         drm_helper_move_panel_connectors_to_head(dev);
14554 }
14555
14556 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14557 {
14558         struct drm_device *dev = fb->dev;
14559         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14560
14561         drm_framebuffer_cleanup(fb);
14562         mutex_lock(&dev->struct_mutex);
14563         WARN_ON(!intel_fb->obj->framebuffer_references--);
14564         drm_gem_object_unreference(&intel_fb->obj->base);
14565         mutex_unlock(&dev->struct_mutex);
14566         kfree(intel_fb);
14567 }
14568
14569 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14570                                                 struct drm_file *file,
14571                                                 unsigned int *handle)
14572 {
14573         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14574         struct drm_i915_gem_object *obj = intel_fb->obj;
14575
14576         if (obj->userptr.mm) {
14577                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14578                 return -EINVAL;
14579         }
14580
14581         return drm_gem_handle_create(file, &obj->base, handle);
14582 }
14583
14584 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14585                                         struct drm_file *file,
14586                                         unsigned flags, unsigned color,
14587                                         struct drm_clip_rect *clips,
14588                                         unsigned num_clips)
14589 {
14590         struct drm_device *dev = fb->dev;
14591         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14592         struct drm_i915_gem_object *obj = intel_fb->obj;
14593
14594         mutex_lock(&dev->struct_mutex);
14595         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14596         mutex_unlock(&dev->struct_mutex);
14597
14598         return 0;
14599 }
14600
14601 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14602         .destroy = intel_user_framebuffer_destroy,
14603         .create_handle = intel_user_framebuffer_create_handle,
14604         .dirty = intel_user_framebuffer_dirty,
14605 };
14606
14607 static
14608 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14609                          uint32_t pixel_format)
14610 {
14611         u32 gen = INTEL_INFO(dev)->gen;
14612
14613         if (gen >= 9) {
14614                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14615
14616                 /* "The stride in bytes must not exceed the of the size of 8K
14617                  *  pixels and 32K bytes."
14618                  */
14619                 return min(8192 * cpp, 32768);
14620         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14621                 return 32*1024;
14622         } else if (gen >= 4) {
14623                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14624                         return 16*1024;
14625                 else
14626                         return 32*1024;
14627         } else if (gen >= 3) {
14628                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14629                         return 8*1024;
14630                 else
14631                         return 16*1024;
14632         } else {
14633                 /* XXX DSPC is limited to 4k tiled */
14634                 return 8*1024;
14635         }
14636 }
14637
14638 static int intel_framebuffer_init(struct drm_device *dev,
14639                                   struct intel_framebuffer *intel_fb,
14640                                   struct drm_mode_fb_cmd2 *mode_cmd,
14641                                   struct drm_i915_gem_object *obj)
14642 {
14643         struct drm_i915_private *dev_priv = to_i915(dev);
14644         unsigned int aligned_height;
14645         int ret;
14646         u32 pitch_limit, stride_alignment;
14647
14648         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14649
14650         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14651                 /* Enforce that fb modifier and tiling mode match, but only for
14652                  * X-tiled. This is needed for FBC. */
14653                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14654                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14655                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14656                         return -EINVAL;
14657                 }
14658         } else {
14659                 if (obj->tiling_mode == I915_TILING_X)
14660                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14661                 else if (obj->tiling_mode == I915_TILING_Y) {
14662                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14663                         return -EINVAL;
14664                 }
14665         }
14666
14667         /* Passed in modifier sanity checking. */
14668         switch (mode_cmd->modifier[0]) {
14669         case I915_FORMAT_MOD_Y_TILED:
14670         case I915_FORMAT_MOD_Yf_TILED:
14671                 if (INTEL_INFO(dev)->gen < 9) {
14672                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14673                                   mode_cmd->modifier[0]);
14674                         return -EINVAL;
14675                 }
14676         case DRM_FORMAT_MOD_NONE:
14677         case I915_FORMAT_MOD_X_TILED:
14678                 break;
14679         default:
14680                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14681                           mode_cmd->modifier[0]);
14682                 return -EINVAL;
14683         }
14684
14685         stride_alignment = intel_fb_stride_alignment(dev_priv,
14686                                                      mode_cmd->modifier[0],
14687                                                      mode_cmd->pixel_format);
14688         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14689                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14690                           mode_cmd->pitches[0], stride_alignment);
14691                 return -EINVAL;
14692         }
14693
14694         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14695                                            mode_cmd->pixel_format);
14696         if (mode_cmd->pitches[0] > pitch_limit) {
14697                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14698                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14699                           "tiled" : "linear",
14700                           mode_cmd->pitches[0], pitch_limit);
14701                 return -EINVAL;
14702         }
14703
14704         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14705             mode_cmd->pitches[0] != obj->stride) {
14706                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14707                           mode_cmd->pitches[0], obj->stride);
14708                 return -EINVAL;
14709         }
14710
14711         /* Reject formats not supported by any plane early. */
14712         switch (mode_cmd->pixel_format) {
14713         case DRM_FORMAT_C8:
14714         case DRM_FORMAT_RGB565:
14715         case DRM_FORMAT_XRGB8888:
14716         case DRM_FORMAT_ARGB8888:
14717                 break;
14718         case DRM_FORMAT_XRGB1555:
14719                 if (INTEL_INFO(dev)->gen > 3) {
14720                         DRM_DEBUG("unsupported pixel format: %s\n",
14721                                   drm_get_format_name(mode_cmd->pixel_format));
14722                         return -EINVAL;
14723                 }
14724                 break;
14725         case DRM_FORMAT_ABGR8888:
14726                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14727                     INTEL_INFO(dev)->gen < 9) {
14728                         DRM_DEBUG("unsupported pixel format: %s\n",
14729                                   drm_get_format_name(mode_cmd->pixel_format));
14730                         return -EINVAL;
14731                 }
14732                 break;
14733         case DRM_FORMAT_XBGR8888:
14734         case DRM_FORMAT_XRGB2101010:
14735         case DRM_FORMAT_XBGR2101010:
14736                 if (INTEL_INFO(dev)->gen < 4) {
14737                         DRM_DEBUG("unsupported pixel format: %s\n",
14738                                   drm_get_format_name(mode_cmd->pixel_format));
14739                         return -EINVAL;
14740                 }
14741                 break;
14742         case DRM_FORMAT_ABGR2101010:
14743                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14744                         DRM_DEBUG("unsupported pixel format: %s\n",
14745                                   drm_get_format_name(mode_cmd->pixel_format));
14746                         return -EINVAL;
14747                 }
14748                 break;
14749         case DRM_FORMAT_YUYV:
14750         case DRM_FORMAT_UYVY:
14751         case DRM_FORMAT_YVYU:
14752         case DRM_FORMAT_VYUY:
14753                 if (INTEL_INFO(dev)->gen < 5) {
14754                         DRM_DEBUG("unsupported pixel format: %s\n",
14755                                   drm_get_format_name(mode_cmd->pixel_format));
14756                         return -EINVAL;
14757                 }
14758                 break;
14759         default:
14760                 DRM_DEBUG("unsupported pixel format: %s\n",
14761                           drm_get_format_name(mode_cmd->pixel_format));
14762                 return -EINVAL;
14763         }
14764
14765         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14766         if (mode_cmd->offsets[0] != 0)
14767                 return -EINVAL;
14768
14769         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14770                                                mode_cmd->pixel_format,
14771                                                mode_cmd->modifier[0]);
14772         /* FIXME drm helper for size checks (especially planar formats)? */
14773         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14774                 return -EINVAL;
14775
14776         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14777         intel_fb->obj = obj;
14778
14779         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14780         if (ret) {
14781                 DRM_ERROR("framebuffer init failed %d\n", ret);
14782                 return ret;
14783         }
14784
14785         intel_fb->obj->framebuffer_references++;
14786
14787         return 0;
14788 }
14789
14790 static struct drm_framebuffer *
14791 intel_user_framebuffer_create(struct drm_device *dev,
14792                               struct drm_file *filp,
14793                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14794 {
14795         struct drm_framebuffer *fb;
14796         struct drm_i915_gem_object *obj;
14797         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14798
14799         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14800                                                 mode_cmd.handles[0]));
14801         if (&obj->base == NULL)
14802                 return ERR_PTR(-ENOENT);
14803
14804         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14805         if (IS_ERR(fb))
14806                 drm_gem_object_unreference_unlocked(&obj->base);
14807
14808         return fb;
14809 }
14810
14811 #ifndef CONFIG_DRM_FBDEV_EMULATION
14812 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14813 {
14814 }
14815 #endif
14816
14817 static const struct drm_mode_config_funcs intel_mode_funcs = {
14818         .fb_create = intel_user_framebuffer_create,
14819         .output_poll_changed = intel_fbdev_output_poll_changed,
14820         .atomic_check = intel_atomic_check,
14821         .atomic_commit = intel_atomic_commit,
14822         .atomic_state_alloc = intel_atomic_state_alloc,
14823         .atomic_state_clear = intel_atomic_state_clear,
14824 };
14825
14826 /* Set up chip specific display functions */
14827 static void intel_init_display(struct drm_device *dev)
14828 {
14829         struct drm_i915_private *dev_priv = dev->dev_private;
14830
14831         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14832                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14833         else if (IS_CHERRYVIEW(dev))
14834                 dev_priv->display.find_dpll = chv_find_best_dpll;
14835         else if (IS_VALLEYVIEW(dev))
14836                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14837         else if (IS_PINEVIEW(dev))
14838                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14839         else
14840                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14841
14842         if (INTEL_INFO(dev)->gen >= 9) {
14843                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14844                 dev_priv->display.get_initial_plane_config =
14845                         skylake_get_initial_plane_config;
14846                 dev_priv->display.crtc_compute_clock =
14847                         haswell_crtc_compute_clock;
14848                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14849                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14850         } else if (HAS_DDI(dev)) {
14851                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14852                 dev_priv->display.get_initial_plane_config =
14853                         ironlake_get_initial_plane_config;
14854                 dev_priv->display.crtc_compute_clock =
14855                         haswell_crtc_compute_clock;
14856                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14857                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14858         } else if (HAS_PCH_SPLIT(dev)) {
14859                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14860                 dev_priv->display.get_initial_plane_config =
14861                         ironlake_get_initial_plane_config;
14862                 dev_priv->display.crtc_compute_clock =
14863                         ironlake_crtc_compute_clock;
14864                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14865                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14866         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14867                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14868                 dev_priv->display.get_initial_plane_config =
14869                         i9xx_get_initial_plane_config;
14870                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14871                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14872                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14873         } else {
14874                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14875                 dev_priv->display.get_initial_plane_config =
14876                         i9xx_get_initial_plane_config;
14877                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14878                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14879                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14880         }
14881
14882         /* Returns the core display clock speed */
14883         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14884                 dev_priv->display.get_display_clock_speed =
14885                         skylake_get_display_clock_speed;
14886         else if (IS_BROXTON(dev))
14887                 dev_priv->display.get_display_clock_speed =
14888                         broxton_get_display_clock_speed;
14889         else if (IS_BROADWELL(dev))
14890                 dev_priv->display.get_display_clock_speed =
14891                         broadwell_get_display_clock_speed;
14892         else if (IS_HASWELL(dev))
14893                 dev_priv->display.get_display_clock_speed =
14894                         haswell_get_display_clock_speed;
14895         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14896                 dev_priv->display.get_display_clock_speed =
14897                         valleyview_get_display_clock_speed;
14898         else if (IS_GEN5(dev))
14899                 dev_priv->display.get_display_clock_speed =
14900                         ilk_get_display_clock_speed;
14901         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14902                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14903                 dev_priv->display.get_display_clock_speed =
14904                         i945_get_display_clock_speed;
14905         else if (IS_GM45(dev))
14906                 dev_priv->display.get_display_clock_speed =
14907                         gm45_get_display_clock_speed;
14908         else if (IS_CRESTLINE(dev))
14909                 dev_priv->display.get_display_clock_speed =
14910                         i965gm_get_display_clock_speed;
14911         else if (IS_PINEVIEW(dev))
14912                 dev_priv->display.get_display_clock_speed =
14913                         pnv_get_display_clock_speed;
14914         else if (IS_G33(dev) || IS_G4X(dev))
14915                 dev_priv->display.get_display_clock_speed =
14916                         g33_get_display_clock_speed;
14917         else if (IS_I915G(dev))
14918                 dev_priv->display.get_display_clock_speed =
14919                         i915_get_display_clock_speed;
14920         else if (IS_I945GM(dev) || IS_845G(dev))
14921                 dev_priv->display.get_display_clock_speed =
14922                         i9xx_misc_get_display_clock_speed;
14923         else if (IS_I915GM(dev))
14924                 dev_priv->display.get_display_clock_speed =
14925                         i915gm_get_display_clock_speed;
14926         else if (IS_I865G(dev))
14927                 dev_priv->display.get_display_clock_speed =
14928                         i865_get_display_clock_speed;
14929         else if (IS_I85X(dev))
14930                 dev_priv->display.get_display_clock_speed =
14931                         i85x_get_display_clock_speed;
14932         else { /* 830 */
14933                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14934                 dev_priv->display.get_display_clock_speed =
14935                         i830_get_display_clock_speed;
14936         }
14937
14938         if (IS_GEN5(dev)) {
14939                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14940         } else if (IS_GEN6(dev)) {
14941                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14942         } else if (IS_IVYBRIDGE(dev)) {
14943                 /* FIXME: detect B0+ stepping and use auto training */
14944                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14945         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14946                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14947                 if (IS_BROADWELL(dev)) {
14948                         dev_priv->display.modeset_commit_cdclk =
14949                                 broadwell_modeset_commit_cdclk;
14950                         dev_priv->display.modeset_calc_cdclk =
14951                                 broadwell_modeset_calc_cdclk;
14952                 }
14953         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14954                 dev_priv->display.modeset_commit_cdclk =
14955                         valleyview_modeset_commit_cdclk;
14956                 dev_priv->display.modeset_calc_cdclk =
14957                         valleyview_modeset_calc_cdclk;
14958         } else if (IS_BROXTON(dev)) {
14959                 dev_priv->display.modeset_commit_cdclk =
14960                         broxton_modeset_commit_cdclk;
14961                 dev_priv->display.modeset_calc_cdclk =
14962                         broxton_modeset_calc_cdclk;
14963         }
14964
14965         switch (INTEL_INFO(dev)->gen) {
14966         case 2:
14967                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14968                 break;
14969
14970         case 3:
14971                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14972                 break;
14973
14974         case 4:
14975         case 5:
14976                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14977                 break;
14978
14979         case 6:
14980                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14981                 break;
14982         case 7:
14983         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14984                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14985                 break;
14986         case 9:
14987                 /* Drop through - unsupported since execlist only. */
14988         default:
14989                 /* Default just returns -ENODEV to indicate unsupported */
14990                 dev_priv->display.queue_flip = intel_default_queue_flip;
14991         }
14992
14993         mutex_init(&dev_priv->pps_mutex);
14994 }
14995
14996 /*
14997  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14998  * resume, or other times.  This quirk makes sure that's the case for
14999  * affected systems.
15000  */
15001 static void quirk_pipea_force(struct drm_device *dev)
15002 {
15003         struct drm_i915_private *dev_priv = dev->dev_private;
15004
15005         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15006         DRM_INFO("applying pipe a force quirk\n");
15007 }
15008
15009 static void quirk_pipeb_force(struct drm_device *dev)
15010 {
15011         struct drm_i915_private *dev_priv = dev->dev_private;
15012
15013         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15014         DRM_INFO("applying pipe b force quirk\n");
15015 }
15016
15017 /*
15018  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15019  */
15020 static void quirk_ssc_force_disable(struct drm_device *dev)
15021 {
15022         struct drm_i915_private *dev_priv = dev->dev_private;
15023         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15024         DRM_INFO("applying lvds SSC disable quirk\n");
15025 }
15026
15027 /*
15028  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15029  * brightness value
15030  */
15031 static void quirk_invert_brightness(struct drm_device *dev)
15032 {
15033         struct drm_i915_private *dev_priv = dev->dev_private;
15034         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15035         DRM_INFO("applying inverted panel brightness quirk\n");
15036 }
15037
15038 /* Some VBT's incorrectly indicate no backlight is present */
15039 static void quirk_backlight_present(struct drm_device *dev)
15040 {
15041         struct drm_i915_private *dev_priv = dev->dev_private;
15042         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15043         DRM_INFO("applying backlight present quirk\n");
15044 }
15045
15046 struct intel_quirk {
15047         int device;
15048         int subsystem_vendor;
15049         int subsystem_device;
15050         void (*hook)(struct drm_device *dev);
15051 };
15052
15053 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15054 struct intel_dmi_quirk {
15055         void (*hook)(struct drm_device *dev);
15056         const struct dmi_system_id (*dmi_id_list)[];
15057 };
15058
15059 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15060 {
15061         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15062         return 1;
15063 }
15064
15065 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15066         {
15067                 .dmi_id_list = &(const struct dmi_system_id[]) {
15068                         {
15069                                 .callback = intel_dmi_reverse_brightness,
15070                                 .ident = "NCR Corporation",
15071                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15072                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15073                                 },
15074                         },
15075                         { }  /* terminating entry */
15076                 },
15077                 .hook = quirk_invert_brightness,
15078         },
15079 };
15080
15081 static struct intel_quirk intel_quirks[] = {
15082         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15083         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15084
15085         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15086         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15087
15088         /* 830 needs to leave pipe A & dpll A up */
15089         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15090
15091         /* 830 needs to leave pipe B & dpll B up */
15092         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15093
15094         /* Lenovo U160 cannot use SSC on LVDS */
15095         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15096
15097         /* Sony Vaio Y cannot use SSC on LVDS */
15098         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15099
15100         /* Acer Aspire 5734Z must invert backlight brightness */
15101         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15102
15103         /* Acer/eMachines G725 */
15104         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15105
15106         /* Acer/eMachines e725 */
15107         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15108
15109         /* Acer/Packard Bell NCL20 */
15110         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15111
15112         /* Acer Aspire 4736Z */
15113         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15114
15115         /* Acer Aspire 5336 */
15116         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15117
15118         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15119         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15120
15121         /* Acer C720 Chromebook (Core i3 4005U) */
15122         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15123
15124         /* Apple Macbook 2,1 (Core 2 T7400) */
15125         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15126
15127         /* Apple Macbook 4,1 */
15128         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15129
15130         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15131         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15132
15133         /* HP Chromebook 14 (Celeron 2955U) */
15134         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15135
15136         /* Dell Chromebook 11 */
15137         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15138
15139         /* Dell Chromebook 11 (2015 version) */
15140         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15141 };
15142
15143 static void intel_init_quirks(struct drm_device *dev)
15144 {
15145         struct pci_dev *d = dev->pdev;
15146         int i;
15147
15148         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15149                 struct intel_quirk *q = &intel_quirks[i];
15150
15151                 if (d->device == q->device &&
15152                     (d->subsystem_vendor == q->subsystem_vendor ||
15153                      q->subsystem_vendor == PCI_ANY_ID) &&
15154                     (d->subsystem_device == q->subsystem_device ||
15155                      q->subsystem_device == PCI_ANY_ID))
15156                         q->hook(dev);
15157         }
15158         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15159                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15160                         intel_dmi_quirks[i].hook(dev);
15161         }
15162 }
15163
15164 /* Disable the VGA plane that we never use */
15165 static void i915_disable_vga(struct drm_device *dev)
15166 {
15167         struct drm_i915_private *dev_priv = dev->dev_private;
15168         u8 sr1;
15169         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15170
15171         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15172         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15173         outb(SR01, VGA_SR_INDEX);
15174         sr1 = inb(VGA_SR_DATA);
15175         outb(sr1 | 1<<5, VGA_SR_DATA);
15176         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15177         udelay(300);
15178
15179         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15180         POSTING_READ(vga_reg);
15181 }
15182
15183 void intel_modeset_init_hw(struct drm_device *dev)
15184 {
15185         struct drm_i915_private *dev_priv = dev->dev_private;
15186
15187         intel_update_cdclk(dev);
15188
15189         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15190
15191         intel_init_clock_gating(dev);
15192         intel_enable_gt_powersave(dev);
15193 }
15194
15195 /*
15196  * Calculate what we think the watermarks should be for the state we've read
15197  * out of the hardware and then immediately program those watermarks so that
15198  * we ensure the hardware settings match our internal state.
15199  *
15200  * We can calculate what we think WM's should be by creating a duplicate of the
15201  * current state (which was constructed during hardware readout) and running it
15202  * through the atomic check code to calculate new watermark values in the
15203  * state object.
15204  */
15205 static void sanitize_watermarks(struct drm_device *dev)
15206 {
15207         struct drm_i915_private *dev_priv = to_i915(dev);
15208         struct drm_atomic_state *state;
15209         struct drm_crtc *crtc;
15210         struct drm_crtc_state *cstate;
15211         struct drm_modeset_acquire_ctx ctx;
15212         int ret;
15213         int i;
15214
15215         /* Only supported on platforms that use atomic watermark design */
15216         if (!dev_priv->display.program_watermarks)
15217                 return;
15218
15219         /*
15220          * We need to hold connection_mutex before calling duplicate_state so
15221          * that the connector loop is protected.
15222          */
15223         drm_modeset_acquire_init(&ctx, 0);
15224 retry:
15225         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15226         if (ret == -EDEADLK) {
15227                 drm_modeset_backoff(&ctx);
15228                 goto retry;
15229         } else if (WARN_ON(ret)) {
15230                 goto fail;
15231         }
15232
15233         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15234         if (WARN_ON(IS_ERR(state)))
15235                 goto fail;
15236
15237         ret = intel_atomic_check(dev, state);
15238         if (ret) {
15239                 /*
15240                  * If we fail here, it means that the hardware appears to be
15241                  * programmed in a way that shouldn't be possible, given our
15242                  * understanding of watermark requirements.  This might mean a
15243                  * mistake in the hardware readout code or a mistake in the
15244                  * watermark calculations for a given platform.  Raise a WARN
15245                  * so that this is noticeable.
15246                  *
15247                  * If this actually happens, we'll have to just leave the
15248                  * BIOS-programmed watermarks untouched and hope for the best.
15249                  */
15250                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15251                 goto fail;
15252         }
15253
15254         /* Write calculated watermark values back */
15255         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15256         for_each_crtc_in_state(state, crtc, cstate, i) {
15257                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15258
15259                 dev_priv->display.program_watermarks(cs);
15260         }
15261
15262         drm_atomic_state_free(state);
15263 fail:
15264         drm_modeset_drop_locks(&ctx);
15265         drm_modeset_acquire_fini(&ctx);
15266 }
15267
15268 void intel_modeset_init(struct drm_device *dev)
15269 {
15270         struct drm_i915_private *dev_priv = dev->dev_private;
15271         int sprite, ret;
15272         enum pipe pipe;
15273         struct intel_crtc *crtc;
15274
15275         drm_mode_config_init(dev);
15276
15277         dev->mode_config.min_width = 0;
15278         dev->mode_config.min_height = 0;
15279
15280         dev->mode_config.preferred_depth = 24;
15281         dev->mode_config.prefer_shadow = 1;
15282
15283         dev->mode_config.allow_fb_modifiers = true;
15284
15285         dev->mode_config.funcs = &intel_mode_funcs;
15286
15287         intel_init_quirks(dev);
15288
15289         intel_init_pm(dev);
15290
15291         if (INTEL_INFO(dev)->num_pipes == 0)
15292                 return;
15293
15294         /*
15295          * There may be no VBT; and if the BIOS enabled SSC we can
15296          * just keep using it to avoid unnecessary flicker.  Whereas if the
15297          * BIOS isn't using it, don't assume it will work even if the VBT
15298          * indicates as much.
15299          */
15300         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15301                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15302                                             DREF_SSC1_ENABLE);
15303
15304                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15305                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15306                                      bios_lvds_use_ssc ? "en" : "dis",
15307                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15308                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15309                 }
15310         }
15311
15312         intel_init_display(dev);
15313         intel_init_audio(dev);
15314
15315         if (IS_GEN2(dev)) {
15316                 dev->mode_config.max_width = 2048;
15317                 dev->mode_config.max_height = 2048;
15318         } else if (IS_GEN3(dev)) {
15319                 dev->mode_config.max_width = 4096;
15320                 dev->mode_config.max_height = 4096;
15321         } else {
15322                 dev->mode_config.max_width = 8192;
15323                 dev->mode_config.max_height = 8192;
15324         }
15325
15326         if (IS_845G(dev) || IS_I865G(dev)) {
15327                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15328                 dev->mode_config.cursor_height = 1023;
15329         } else if (IS_GEN2(dev)) {
15330                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15331                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15332         } else {
15333                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15334                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15335         }
15336
15337         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15338
15339         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15340                       INTEL_INFO(dev)->num_pipes,
15341                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15342
15343         for_each_pipe(dev_priv, pipe) {
15344                 intel_crtc_init(dev, pipe);
15345                 for_each_sprite(dev_priv, pipe, sprite) {
15346                         ret = intel_plane_init(dev, pipe, sprite);
15347                         if (ret)
15348                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15349                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15350                 }
15351         }
15352
15353         intel_update_czclk(dev_priv);
15354         intel_update_cdclk(dev);
15355
15356         intel_shared_dpll_init(dev);
15357
15358         /* Just disable it once at startup */
15359         i915_disable_vga(dev);
15360         intel_setup_outputs(dev);
15361
15362         drm_modeset_lock_all(dev);
15363         intel_modeset_setup_hw_state(dev);
15364         drm_modeset_unlock_all(dev);
15365
15366         for_each_intel_crtc(dev, crtc) {
15367                 struct intel_initial_plane_config plane_config = {};
15368
15369                 if (!crtc->active)
15370                         continue;
15371
15372                 /*
15373                  * Note that reserving the BIOS fb up front prevents us
15374                  * from stuffing other stolen allocations like the ring
15375                  * on top.  This prevents some ugliness at boot time, and
15376                  * can even allow for smooth boot transitions if the BIOS
15377                  * fb is large enough for the active pipe configuration.
15378                  */
15379                 dev_priv->display.get_initial_plane_config(crtc,
15380                                                            &plane_config);
15381
15382                 /*
15383                  * If the fb is shared between multiple heads, we'll
15384                  * just get the first one.
15385                  */
15386                 intel_find_initial_plane_obj(crtc, &plane_config);
15387         }
15388
15389         /*
15390          * Make sure hardware watermarks really match the state we read out.
15391          * Note that we need to do this after reconstructing the BIOS fb's
15392          * since the watermark calculation done here will use pstate->fb.
15393          */
15394         sanitize_watermarks(dev);
15395 }
15396
15397 static void intel_enable_pipe_a(struct drm_device *dev)
15398 {
15399         struct intel_connector *connector;
15400         struct drm_connector *crt = NULL;
15401         struct intel_load_detect_pipe load_detect_temp;
15402         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15403
15404         /* We can't just switch on the pipe A, we need to set things up with a
15405          * proper mode and output configuration. As a gross hack, enable pipe A
15406          * by enabling the load detect pipe once. */
15407         for_each_intel_connector(dev, connector) {
15408                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15409                         crt = &connector->base;
15410                         break;
15411                 }
15412         }
15413
15414         if (!crt)
15415                 return;
15416
15417         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15418                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15419 }
15420
15421 static bool
15422 intel_check_plane_mapping(struct intel_crtc *crtc)
15423 {
15424         struct drm_device *dev = crtc->base.dev;
15425         struct drm_i915_private *dev_priv = dev->dev_private;
15426         u32 val;
15427
15428         if (INTEL_INFO(dev)->num_pipes == 1)
15429                 return true;
15430
15431         val = I915_READ(DSPCNTR(!crtc->plane));
15432
15433         if ((val & DISPLAY_PLANE_ENABLE) &&
15434             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15435                 return false;
15436
15437         return true;
15438 }
15439
15440 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15441 {
15442         struct drm_device *dev = crtc->base.dev;
15443         struct intel_encoder *encoder;
15444
15445         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15446                 return true;
15447
15448         return false;
15449 }
15450
15451 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15452 {
15453         struct drm_device *dev = encoder->base.dev;
15454         struct intel_connector *connector;
15455
15456         for_each_connector_on_encoder(dev, &encoder->base, connector)
15457                 return true;
15458
15459         return false;
15460 }
15461
15462 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15463 {
15464         struct drm_device *dev = crtc->base.dev;
15465         struct drm_i915_private *dev_priv = dev->dev_private;
15466         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15467
15468         /* Clear any frame start delays used for debugging left by the BIOS */
15469         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15470
15471         /* restore vblank interrupts to correct state */
15472         drm_crtc_vblank_reset(&crtc->base);
15473         if (crtc->active) {
15474                 struct intel_plane *plane;
15475
15476                 drm_crtc_vblank_on(&crtc->base);
15477
15478                 /* Disable everything but the primary plane */
15479                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15480                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15481                                 continue;
15482
15483                         plane->disable_plane(&plane->base, &crtc->base);
15484                 }
15485         }
15486
15487         /* We need to sanitize the plane -> pipe mapping first because this will
15488          * disable the crtc (and hence change the state) if it is wrong. Note
15489          * that gen4+ has a fixed plane -> pipe mapping.  */
15490         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15491                 bool plane;
15492
15493                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15494                               crtc->base.base.id);
15495
15496                 /* Pipe has the wrong plane attached and the plane is active.
15497                  * Temporarily change the plane mapping and disable everything
15498                  * ...  */
15499                 plane = crtc->plane;
15500                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15501                 crtc->plane = !plane;
15502                 intel_crtc_disable_noatomic(&crtc->base);
15503                 crtc->plane = plane;
15504         }
15505
15506         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15507             crtc->pipe == PIPE_A && !crtc->active) {
15508                 /* BIOS forgot to enable pipe A, this mostly happens after
15509                  * resume. Force-enable the pipe to fix this, the update_dpms
15510                  * call below we restore the pipe to the right state, but leave
15511                  * the required bits on. */
15512                 intel_enable_pipe_a(dev);
15513         }
15514
15515         /* Adjust the state of the output pipe according to whether we
15516          * have active connectors/encoders. */
15517         if (!intel_crtc_has_encoders(crtc))
15518                 intel_crtc_disable_noatomic(&crtc->base);
15519
15520         if (crtc->active != crtc->base.state->active) {
15521                 struct intel_encoder *encoder;
15522
15523                 /* This can happen either due to bugs in the get_hw_state
15524                  * functions or because of calls to intel_crtc_disable_noatomic,
15525                  * or because the pipe is force-enabled due to the
15526                  * pipe A quirk. */
15527                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15528                               crtc->base.base.id,
15529                               crtc->base.state->enable ? "enabled" : "disabled",
15530                               crtc->active ? "enabled" : "disabled");
15531
15532                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15533                 crtc->base.state->active = crtc->active;
15534                 crtc->base.enabled = crtc->active;
15535                 crtc->base.state->connector_mask = 0;
15536                 crtc->base.state->encoder_mask = 0;
15537
15538                 /* Because we only establish the connector -> encoder ->
15539                  * crtc links if something is active, this means the
15540                  * crtc is now deactivated. Break the links. connector
15541                  * -> encoder links are only establish when things are
15542                  *  actually up, hence no need to break them. */
15543                 WARN_ON(crtc->active);
15544
15545                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15546                         encoder->base.crtc = NULL;
15547         }
15548
15549         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15550                 /*
15551                  * We start out with underrun reporting disabled to avoid races.
15552                  * For correct bookkeeping mark this on active crtcs.
15553                  *
15554                  * Also on gmch platforms we dont have any hardware bits to
15555                  * disable the underrun reporting. Which means we need to start
15556                  * out with underrun reporting disabled also on inactive pipes,
15557                  * since otherwise we'll complain about the garbage we read when
15558                  * e.g. coming up after runtime pm.
15559                  *
15560                  * No protection against concurrent access is required - at
15561                  * worst a fifo underrun happens which also sets this to false.
15562                  */
15563                 crtc->cpu_fifo_underrun_disabled = true;
15564                 crtc->pch_fifo_underrun_disabled = true;
15565         }
15566 }
15567
15568 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15569 {
15570         struct intel_connector *connector;
15571         struct drm_device *dev = encoder->base.dev;
15572
15573         /* We need to check both for a crtc link (meaning that the
15574          * encoder is active and trying to read from a pipe) and the
15575          * pipe itself being active. */
15576         bool has_active_crtc = encoder->base.crtc &&
15577                 to_intel_crtc(encoder->base.crtc)->active;
15578
15579         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15580                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15581                               encoder->base.base.id,
15582                               encoder->base.name);
15583
15584                 /* Connector is active, but has no active pipe. This is
15585                  * fallout from our resume register restoring. Disable
15586                  * the encoder manually again. */
15587                 if (encoder->base.crtc) {
15588                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15589                                       encoder->base.base.id,
15590                                       encoder->base.name);
15591                         encoder->disable(encoder);
15592                         if (encoder->post_disable)
15593                                 encoder->post_disable(encoder);
15594                 }
15595                 encoder->base.crtc = NULL;
15596
15597                 /* Inconsistent output/port/pipe state happens presumably due to
15598                  * a bug in one of the get_hw_state functions. Or someplace else
15599                  * in our code, like the register restore mess on resume. Clamp
15600                  * things to off as a safer default. */
15601                 for_each_intel_connector(dev, connector) {
15602                         if (connector->encoder != encoder)
15603                                 continue;
15604                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15605                         connector->base.encoder = NULL;
15606                 }
15607         }
15608         /* Enabled encoders without active connectors will be fixed in
15609          * the crtc fixup. */
15610 }
15611
15612 void i915_redisable_vga_power_on(struct drm_device *dev)
15613 {
15614         struct drm_i915_private *dev_priv = dev->dev_private;
15615         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15616
15617         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15618                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15619                 i915_disable_vga(dev);
15620         }
15621 }
15622
15623 void i915_redisable_vga(struct drm_device *dev)
15624 {
15625         struct drm_i915_private *dev_priv = dev->dev_private;
15626
15627         /* This function can be called both from intel_modeset_setup_hw_state or
15628          * at a very early point in our resume sequence, where the power well
15629          * structures are not yet restored. Since this function is at a very
15630          * paranoid "someone might have enabled VGA while we were not looking"
15631          * level, just check if the power well is enabled instead of trying to
15632          * follow the "don't touch the power well if we don't need it" policy
15633          * the rest of the driver uses. */
15634         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15635                 return;
15636
15637         i915_redisable_vga_power_on(dev);
15638
15639         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15640 }
15641
15642 static bool primary_get_hw_state(struct intel_plane *plane)
15643 {
15644         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15645
15646         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15647 }
15648
15649 /* FIXME read out full plane state for all planes */
15650 static void readout_plane_state(struct intel_crtc *crtc)
15651 {
15652         struct drm_plane *primary = crtc->base.primary;
15653         struct intel_plane_state *plane_state =
15654                 to_intel_plane_state(primary->state);
15655
15656         plane_state->visible = crtc->active &&
15657                 primary_get_hw_state(to_intel_plane(primary));
15658
15659         if (plane_state->visible)
15660                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15661 }
15662
15663 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15664 {
15665         struct drm_i915_private *dev_priv = dev->dev_private;
15666         enum pipe pipe;
15667         struct intel_crtc *crtc;
15668         struct intel_encoder *encoder;
15669         struct intel_connector *connector;
15670         int i;
15671
15672         dev_priv->active_crtcs = 0;
15673
15674         for_each_intel_crtc(dev, crtc) {
15675                 struct intel_crtc_state *crtc_state = crtc->config;
15676                 int pixclk = 0;
15677
15678                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15679                 memset(crtc_state, 0, sizeof(*crtc_state));
15680                 crtc_state->base.crtc = &crtc->base;
15681
15682                 crtc_state->base.active = crtc_state->base.enable =
15683                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15684
15685                 crtc->base.enabled = crtc_state->base.enable;
15686                 crtc->active = crtc_state->base.active;
15687
15688                 if (crtc_state->base.active) {
15689                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15690
15691                         if (IS_BROADWELL(dev_priv)) {
15692                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15693
15694                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15695                                 if (crtc_state->ips_enabled)
15696                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15697                         } else if (IS_VALLEYVIEW(dev_priv) ||
15698                                    IS_CHERRYVIEW(dev_priv) ||
15699                                    IS_BROXTON(dev_priv))
15700                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15701                         else
15702                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15703                 }
15704
15705                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15706
15707                 readout_plane_state(crtc);
15708
15709                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15710                               crtc->base.base.id,
15711                               crtc->active ? "enabled" : "disabled");
15712         }
15713
15714         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15715                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15716
15717                 pll->on = pll->get_hw_state(dev_priv, pll,
15718                                             &pll->config.hw_state);
15719                 pll->active = 0;
15720                 pll->config.crtc_mask = 0;
15721                 for_each_intel_crtc(dev, crtc) {
15722                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15723                                 pll->active++;
15724                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15725                         }
15726                 }
15727
15728                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15729                               pll->name, pll->config.crtc_mask, pll->on);
15730
15731                 if (pll->config.crtc_mask)
15732                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15733         }
15734
15735         for_each_intel_encoder(dev, encoder) {
15736                 pipe = 0;
15737
15738                 if (encoder->get_hw_state(encoder, &pipe)) {
15739                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15740                         encoder->base.crtc = &crtc->base;
15741                         encoder->get_config(encoder, crtc->config);
15742                 } else {
15743                         encoder->base.crtc = NULL;
15744                 }
15745
15746                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15747                               encoder->base.base.id,
15748                               encoder->base.name,
15749                               encoder->base.crtc ? "enabled" : "disabled",
15750                               pipe_name(pipe));
15751         }
15752
15753         for_each_intel_connector(dev, connector) {
15754                 if (connector->get_hw_state(connector)) {
15755                         connector->base.dpms = DRM_MODE_DPMS_ON;
15756
15757                         encoder = connector->encoder;
15758                         connector->base.encoder = &encoder->base;
15759
15760                         if (encoder->base.crtc &&
15761                             encoder->base.crtc->state->active) {
15762                                 /*
15763                                  * This has to be done during hardware readout
15764                                  * because anything calling .crtc_disable may
15765                                  * rely on the connector_mask being accurate.
15766                                  */
15767                                 encoder->base.crtc->state->connector_mask |=
15768                                         1 << drm_connector_index(&connector->base);
15769                                 encoder->base.crtc->state->encoder_mask |=
15770                                         1 << drm_encoder_index(&encoder->base);
15771                         }
15772
15773                 } else {
15774                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15775                         connector->base.encoder = NULL;
15776                 }
15777                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15778                               connector->base.base.id,
15779                               connector->base.name,
15780                               connector->base.encoder ? "enabled" : "disabled");
15781         }
15782
15783         for_each_intel_crtc(dev, crtc) {
15784                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15785
15786                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15787                 if (crtc->base.state->active) {
15788                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15789                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15790                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15791
15792                         /*
15793                          * The initial mode needs to be set in order to keep
15794                          * the atomic core happy. It wants a valid mode if the
15795                          * crtc's enabled, so we do the above call.
15796                          *
15797                          * At this point some state updated by the connectors
15798                          * in their ->detect() callback has not run yet, so
15799                          * no recalculation can be done yet.
15800                          *
15801                          * Even if we could do a recalculation and modeset
15802                          * right now it would cause a double modeset if
15803                          * fbdev or userspace chooses a different initial mode.
15804                          *
15805                          * If that happens, someone indicated they wanted a
15806                          * mode change, which means it's safe to do a full
15807                          * recalculation.
15808                          */
15809                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15810
15811                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15812                         update_scanline_offset(crtc);
15813                 }
15814         }
15815 }
15816
15817 /* Scan out the current hw modeset state,
15818  * and sanitizes it to the current state
15819  */
15820 static void
15821 intel_modeset_setup_hw_state(struct drm_device *dev)
15822 {
15823         struct drm_i915_private *dev_priv = dev->dev_private;
15824         enum pipe pipe;
15825         struct intel_crtc *crtc;
15826         struct intel_encoder *encoder;
15827         int i;
15828
15829         intel_modeset_readout_hw_state(dev);
15830
15831         /* HW state is read out, now we need to sanitize this mess. */
15832         for_each_intel_encoder(dev, encoder) {
15833                 intel_sanitize_encoder(encoder);
15834         }
15835
15836         for_each_pipe(dev_priv, pipe) {
15837                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15838                 intel_sanitize_crtc(crtc);
15839                 intel_dump_pipe_config(crtc, crtc->config,
15840                                        "[setup_hw_state]");
15841         }
15842
15843         intel_modeset_update_connector_atomic_state(dev);
15844
15845         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15846                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15847
15848                 if (!pll->on || pll->active)
15849                         continue;
15850
15851                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15852
15853                 pll->disable(dev_priv, pll);
15854                 pll->on = false;
15855         }
15856
15857         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15858                 vlv_wm_get_hw_state(dev);
15859         else if (IS_GEN9(dev))
15860                 skl_wm_get_hw_state(dev);
15861         else if (HAS_PCH_SPLIT(dev))
15862                 ilk_wm_get_hw_state(dev);
15863
15864         for_each_intel_crtc(dev, crtc) {
15865                 unsigned long put_domains;
15866
15867                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15868                 if (WARN_ON(put_domains))
15869                         modeset_put_power_domains(dev_priv, put_domains);
15870         }
15871         intel_display_set_init_power(dev_priv, false);
15872
15873         intel_fbc_init_pipe_state(dev_priv);
15874 }
15875
15876 void intel_display_resume(struct drm_device *dev)
15877 {
15878         struct drm_i915_private *dev_priv = to_i915(dev);
15879         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15880         struct drm_modeset_acquire_ctx ctx;
15881         int ret;
15882         bool setup = false;
15883
15884         dev_priv->modeset_restore_state = NULL;
15885
15886         /*
15887          * This is a cludge because with real atomic modeset mode_config.mutex
15888          * won't be taken. Unfortunately some probed state like
15889          * audio_codec_enable is still protected by mode_config.mutex, so lock
15890          * it here for now.
15891          */
15892         mutex_lock(&dev->mode_config.mutex);
15893         drm_modeset_acquire_init(&ctx, 0);
15894
15895 retry:
15896         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15897
15898         if (ret == 0 && !setup) {
15899                 setup = true;
15900
15901                 intel_modeset_setup_hw_state(dev);
15902                 i915_redisable_vga(dev);
15903         }
15904
15905         if (ret == 0 && state) {
15906                 struct drm_crtc_state *crtc_state;
15907                 struct drm_crtc *crtc;
15908                 int i;
15909
15910                 state->acquire_ctx = &ctx;
15911
15912                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15913                         /*
15914                          * Force recalculation even if we restore
15915                          * current state. With fast modeset this may not result
15916                          * in a modeset when the state is compatible.
15917                          */
15918                         crtc_state->mode_changed = true;
15919                 }
15920
15921                 ret = drm_atomic_commit(state);
15922         }
15923
15924         if (ret == -EDEADLK) {
15925                 drm_modeset_backoff(&ctx);
15926                 goto retry;
15927         }
15928
15929         drm_modeset_drop_locks(&ctx);
15930         drm_modeset_acquire_fini(&ctx);
15931         mutex_unlock(&dev->mode_config.mutex);
15932
15933         if (ret) {
15934                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15935                 drm_atomic_state_free(state);
15936         }
15937 }
15938
15939 void intel_modeset_gem_init(struct drm_device *dev)
15940 {
15941         struct drm_crtc *c;
15942         struct drm_i915_gem_object *obj;
15943         int ret;
15944
15945         intel_init_gt_powersave(dev);
15946
15947         intel_modeset_init_hw(dev);
15948
15949         intel_setup_overlay(dev);
15950
15951         /*
15952          * Make sure any fbs we allocated at startup are properly
15953          * pinned & fenced.  When we do the allocation it's too early
15954          * for this.
15955          */
15956         for_each_crtc(dev, c) {
15957                 obj = intel_fb_obj(c->primary->fb);
15958                 if (obj == NULL)
15959                         continue;
15960
15961                 mutex_lock(&dev->struct_mutex);
15962                 ret = intel_pin_and_fence_fb_obj(c->primary,
15963                                                  c->primary->fb,
15964                                                  c->primary->state);
15965                 mutex_unlock(&dev->struct_mutex);
15966                 if (ret) {
15967                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15968                                   to_intel_crtc(c)->pipe);
15969                         drm_framebuffer_unreference(c->primary->fb);
15970                         c->primary->fb = NULL;
15971                         c->primary->crtc = c->primary->state->crtc = NULL;
15972                         update_state_fb(c->primary);
15973                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15974                 }
15975         }
15976
15977         intel_backlight_register(dev);
15978 }
15979
15980 void intel_connector_unregister(struct intel_connector *intel_connector)
15981 {
15982         struct drm_connector *connector = &intel_connector->base;
15983
15984         intel_panel_destroy_backlight(connector);
15985         drm_connector_unregister(connector);
15986 }
15987
15988 void intel_modeset_cleanup(struct drm_device *dev)
15989 {
15990         struct drm_i915_private *dev_priv = dev->dev_private;
15991         struct intel_connector *connector;
15992
15993         intel_disable_gt_powersave(dev);
15994
15995         intel_backlight_unregister(dev);
15996
15997         /*
15998          * Interrupts and polling as the first thing to avoid creating havoc.
15999          * Too much stuff here (turning of connectors, ...) would
16000          * experience fancy races otherwise.
16001          */
16002         intel_irq_uninstall(dev_priv);
16003
16004         /*
16005          * Due to the hpd irq storm handling the hotplug work can re-arm the
16006          * poll handlers. Hence disable polling after hpd handling is shut down.
16007          */
16008         drm_kms_helper_poll_fini(dev);
16009
16010         intel_unregister_dsm_handler();
16011
16012         intel_fbc_global_disable(dev_priv);
16013
16014         /* flush any delayed tasks or pending work */
16015         flush_scheduled_work();
16016
16017         /* destroy the backlight and sysfs files before encoders/connectors */
16018         for_each_intel_connector(dev, connector)
16019                 connector->unregister(connector);
16020
16021         drm_mode_config_cleanup(dev);
16022
16023         intel_cleanup_overlay(dev);
16024
16025         intel_cleanup_gt_powersave(dev);
16026
16027         intel_teardown_gmbus(dev);
16028 }
16029
16030 /*
16031  * Return which encoder is currently attached for connector.
16032  */
16033 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16034 {
16035         return &intel_attached_encoder(connector)->base;
16036 }
16037
16038 void intel_connector_attach_encoder(struct intel_connector *connector,
16039                                     struct intel_encoder *encoder)
16040 {
16041         connector->encoder = encoder;
16042         drm_mode_connector_attach_encoder(&connector->base,
16043                                           &encoder->base);
16044 }
16045
16046 /*
16047  * set vga decode state - true == enable VGA decode
16048  */
16049 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16050 {
16051         struct drm_i915_private *dev_priv = dev->dev_private;
16052         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16053         u16 gmch_ctrl;
16054
16055         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16056                 DRM_ERROR("failed to read control word\n");
16057                 return -EIO;
16058         }
16059
16060         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16061                 return 0;
16062
16063         if (state)
16064                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16065         else
16066                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16067
16068         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16069                 DRM_ERROR("failed to write control word\n");
16070                 return -EIO;
16071         }
16072
16073         return 0;
16074 }
16075
16076 struct intel_display_error_state {
16077
16078         u32 power_well_driver;
16079
16080         int num_transcoders;
16081
16082         struct intel_cursor_error_state {
16083                 u32 control;
16084                 u32 position;
16085                 u32 base;
16086                 u32 size;
16087         } cursor[I915_MAX_PIPES];
16088
16089         struct intel_pipe_error_state {
16090                 bool power_domain_on;
16091                 u32 source;
16092                 u32 stat;
16093         } pipe[I915_MAX_PIPES];
16094
16095         struct intel_plane_error_state {
16096                 u32 control;
16097                 u32 stride;
16098                 u32 size;
16099                 u32 pos;
16100                 u32 addr;
16101                 u32 surface;
16102                 u32 tile_offset;
16103         } plane[I915_MAX_PIPES];
16104
16105         struct intel_transcoder_error_state {
16106                 bool power_domain_on;
16107                 enum transcoder cpu_transcoder;
16108
16109                 u32 conf;
16110
16111                 u32 htotal;
16112                 u32 hblank;
16113                 u32 hsync;
16114                 u32 vtotal;
16115                 u32 vblank;
16116                 u32 vsync;
16117         } transcoder[4];
16118 };
16119
16120 struct intel_display_error_state *
16121 intel_display_capture_error_state(struct drm_device *dev)
16122 {
16123         struct drm_i915_private *dev_priv = dev->dev_private;
16124         struct intel_display_error_state *error;
16125         int transcoders[] = {
16126                 TRANSCODER_A,
16127                 TRANSCODER_B,
16128                 TRANSCODER_C,
16129                 TRANSCODER_EDP,
16130         };
16131         int i;
16132
16133         if (INTEL_INFO(dev)->num_pipes == 0)
16134                 return NULL;
16135
16136         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16137         if (error == NULL)
16138                 return NULL;
16139
16140         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16141                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16142
16143         for_each_pipe(dev_priv, i) {
16144                 error->pipe[i].power_domain_on =
16145                         __intel_display_power_is_enabled(dev_priv,
16146                                                          POWER_DOMAIN_PIPE(i));
16147                 if (!error->pipe[i].power_domain_on)
16148                         continue;
16149
16150                 error->cursor[i].control = I915_READ(CURCNTR(i));
16151                 error->cursor[i].position = I915_READ(CURPOS(i));
16152                 error->cursor[i].base = I915_READ(CURBASE(i));
16153
16154                 error->plane[i].control = I915_READ(DSPCNTR(i));
16155                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16156                 if (INTEL_INFO(dev)->gen <= 3) {
16157                         error->plane[i].size = I915_READ(DSPSIZE(i));
16158                         error->plane[i].pos = I915_READ(DSPPOS(i));
16159                 }
16160                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16161                         error->plane[i].addr = I915_READ(DSPADDR(i));
16162                 if (INTEL_INFO(dev)->gen >= 4) {
16163                         error->plane[i].surface = I915_READ(DSPSURF(i));
16164                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16165                 }
16166
16167                 error->pipe[i].source = I915_READ(PIPESRC(i));
16168
16169                 if (HAS_GMCH_DISPLAY(dev))
16170                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16171         }
16172
16173         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16174         if (HAS_DDI(dev_priv->dev))
16175                 error->num_transcoders++; /* Account for eDP. */
16176
16177         for (i = 0; i < error->num_transcoders; i++) {
16178                 enum transcoder cpu_transcoder = transcoders[i];
16179
16180                 error->transcoder[i].power_domain_on =
16181                         __intel_display_power_is_enabled(dev_priv,
16182                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16183                 if (!error->transcoder[i].power_domain_on)
16184                         continue;
16185
16186                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16187
16188                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16189                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16190                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16191                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16192                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16193                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16194                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16195         }
16196
16197         return error;
16198 }
16199
16200 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16201
16202 void
16203 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16204                                 struct drm_device *dev,
16205                                 struct intel_display_error_state *error)
16206 {
16207         struct drm_i915_private *dev_priv = dev->dev_private;
16208         int i;
16209
16210         if (!error)
16211                 return;
16212
16213         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16214         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16215                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16216                            error->power_well_driver);
16217         for_each_pipe(dev_priv, i) {
16218                 err_printf(m, "Pipe [%d]:\n", i);
16219                 err_printf(m, "  Power: %s\n",
16220                            onoff(error->pipe[i].power_domain_on));
16221                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16222                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16223
16224                 err_printf(m, "Plane [%d]:\n", i);
16225                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16226                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16227                 if (INTEL_INFO(dev)->gen <= 3) {
16228                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16229                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16230                 }
16231                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16232                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16233                 if (INTEL_INFO(dev)->gen >= 4) {
16234                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16235                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16236                 }
16237
16238                 err_printf(m, "Cursor [%d]:\n", i);
16239                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16240                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16241                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16242         }
16243
16244         for (i = 0; i < error->num_transcoders; i++) {
16245                 err_printf(m, "CPU transcoder: %c\n",
16246                            transcoder_name(error->transcoder[i].cpu_transcoder));
16247                 err_printf(m, "  Power: %s\n",
16248                            onoff(error->transcoder[i].power_domain_on));
16249                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16250                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16251                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16252                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16253                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16254                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16255                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16256         }
16257 }