drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336 }
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 limit = &intel_limits_vlv;
 414         } else if (!IS_GEN2(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 416                         limit = &intel_limits_i9xx_lvds;
 417                 else
 418                         limit = &intel_limits_i9xx_sdvo;
 419         } else {
 420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 421                         limit = &intel_limits_i8xx_lvds;
 422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 423                         limit = &intel_limits_i8xx_dvo;
 424                 else
 425                         limit = &intel_limits_i8xx_dac;
 426         }
 427         return limit;
 428 }
 429
 430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 431 static void pineview_clock(int refclk, intel_clock_t *clock)
 432 {
 433         clock->m = clock->m2 + 2;
 434         clock->p = clock->p1 * clock->p2;
 435         if (WARN_ON(clock->n == 0 || clock->p == 0))
 436                 return;
 437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 439 }
 440
 441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 442 {
 443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 444 }
 445
 446 static void i9xx_clock(int refclk, intel_clock_t *clock)
 447 {
 448         clock->m = i9xx_dpll_compute_m(clock);
 449         clock->p = clock->p1 * clock->p2;
 450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 451                 return;
 452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 467                 INTELPllInvalid("n out of range\n");
 468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 469                 INTELPllInvalid("p1 out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474
 475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 476                 if (clock->m1 <= clock->m2)
 477                         INTELPllInvalid("m1 <= m2\n");
 478
 479         if (!IS_VALLEYVIEW(dev)) {
 480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 481                         INTELPllInvalid("p out of range\n");
 482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 483                         INTELPllInvalid("m out of range\n");
 484         }
 485
 486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 487                 INTELPllInvalid("vco out of range\n");
 488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 489          * connector, etc., rather than just a single range.
 490          */
 491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 492                 INTELPllInvalid("dot out of range\n");
 493
 494         return true;
 495 }
 496
 497 static bool
 498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 499                     int target, int refclk, intel_clock_t *match_clock,
 500                     intel_clock_t *best_clock)
 501 {
 502         struct drm_device *dev = crtc->dev;
 503         intel_clock_t clock;
 504         int err = target;
 505
 506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 507                 /*
 508                  * For LVDS just rely on its current settings for dual-channel.
 509                  * We haven't figured out how to reliably set up different
 510                  * single/dual channel state, if we even can.
 511                  */
 512                 if (intel_is_dual_link_lvds(dev))
 513                         clock.p2 = limit->p2.p2_fast;
 514                 else
 515                         clock.p2 = limit->p2.p2_slow;
 516         } else {
 517                 if (target < limit->p2.dot_limit)
 518                         clock.p2 = limit->p2.p2_slow;
 519                 else
 520                         clock.p2 = limit->p2.p2_fast;
 521         }
 522
 523         memset(best_clock, 0, sizeof(*best_clock));
 524
 525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 526              clock.m1++) {
 527                 for (clock.m2 = limit->m2.min;
 528                      clock.m2 <= limit->m2.max; clock.m2++) {
 529                         if (clock.m2 >= clock.m1)
 530                                 break;
 531                         for (clock.n = limit->n.min;
 532                              clock.n <= limit->n.max; clock.n++) {
 533                                 for (clock.p1 = limit->p1.min;
 534                                         clock.p1 <= limit->p1.max; clock.p1++) {
 535                                         int this_err;
 536
 537                                         i9xx_clock(refclk, &clock);
 538                                         if (!intel_PLL_is_valid(dev, limit,
 539                                                                 &clock))
 540                                                 continue;
 541                                         if (match_clock &&
 542                                             clock.p != match_clock->p)
 543                                                 continue;
 544
 545                                         this_err = abs(clock.dot - target);
 546                                         if (this_err < err) {
 547                                                 *best_clock = clock;
 548                                                 err = this_err;
 549                                         }
 550                                 }
 551                         }
 552                 }
 553         }
 554
 555         return (err != target);
 556 }
 557
 558 static bool
 559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 560                    int target, int refclk, intel_clock_t *match_clock,
 561                    intel_clock_t *best_clock)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         intel_clock_t clock;
 565         int err = target;
 566
 567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 568                 /*
 569                  * For LVDS just rely on its current settings for dual-channel.
 570                  * We haven't figured out how to reliably set up different
 571                  * single/dual channel state, if we even can.
 572                  */
 573                 if (intel_is_dual_link_lvds(dev))
 574                         clock.p2 = limit->p2.p2_fast;
 575                 else
 576                         clock.p2 = limit->p2.p2_slow;
 577         } else {
 578                 if (target < limit->p2.dot_limit)
 579                         clock.p2 = limit->p2.p2_slow;
 580                 else
 581                         clock.p2 = limit->p2.p2_fast;
 582         }
 583
 584         memset(best_clock, 0, sizeof(*best_clock));
 585
 586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 587              clock.m1++) {
 588                 for (clock.m2 = limit->m2.min;
 589                      clock.m2 <= limit->m2.max; clock.m2++) {
 590                         for (clock.n = limit->n.min;
 591                              clock.n <= limit->n.max; clock.n++) {
 592                                 for (clock.p1 = limit->p1.min;
 593                                         clock.p1 <= limit->p1.max; clock.p1++) {
 594                                         int this_err;
 595
 596                                         pineview_clock(refclk, &clock);
 597                                         if (!intel_PLL_is_valid(dev, limit,
 598                                                                 &clock))
 599                                                 continue;
 600                                         if (match_clock &&
 601                                             clock.p != match_clock->p)
 602                                                 continue;
 603
 604                                         this_err = abs(clock.dot - target);
 605                                         if (this_err < err) {
 606                                                 *best_clock = clock;
 607                                                 err = this_err;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612         }
 613
 614         return (err != target);
 615 }
 616
 617 static bool
 618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                    int target, int refclk, intel_clock_t *match_clock,
 620                    intel_clock_t *best_clock)
 621 {
 622         struct drm_device *dev = crtc->dev;
 623         intel_clock_t clock;
 624         int max_n;
 625         bool found;
 626         /* approximately equals target * 0.00585 */
 627         int err_most = (target >> 8) + (target >> 9);
 628         found = false;
 629
 630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 631                 if (intel_is_dual_link_lvds(dev))
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         i9xx_clock(refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659
 660                                         this_err = abs(clock.dot - target);
 661                                         if (this_err < err_most) {
 662                                                 *best_clock = clock;
 663                                                 err_most = this_err;
 664                                                 max_n = clock.n;
 665                                                 found = true;
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671         return found;
 672 }
 673
 674 static bool
 675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                    int target, int refclk, intel_clock_t *match_clock,
 677                    intel_clock_t *best_clock)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         intel_clock_t clock;
 681         unsigned int bestppm = 1000000;
 682         /* min update 19.2 MHz */
 683         int max_n = min(limit->n.max, refclk / 19200);
 684         bool found = false;
 685
 686         target *= 5; /* fast clock */
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 695                                 clock.p = clock.p1 * clock.p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 698                                         unsigned int ppm, diff;
 699
 700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 701                                                                      refclk * clock.m1);
 702
 703                                         vlv_clock(refclk, &clock);
 704
 705                                         if (!intel_PLL_is_valid(dev, limit,
 706                                                                 &clock))
 707                                                 continue;
 708
 709                                         diff = abs(clock.dot - target);
 710                                         ppm = div_u64(1000000ULL * diff, target);
 711
 712                                         if (ppm < 100 && clock.p > best_clock->p) {
 713                                                 bestppm = 0;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717
 718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 719                                                 bestppm = ppm;
 720                                                 *best_clock = clock;
 721                                                 found = true;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         return found;
 729 }
 730
 731 bool intel_crtc_active(struct drm_crtc *crtc)
 732 {
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         /* Be paranoid as we can arrive here with only partial
 736          * state retrieved from the hardware during setup.
 737          *
 738          * We can ditch the adjusted_mode.crtc_clock check as soon
 739          * as Haswell has gained clock readout/fastboot support.
 740          *
 741          * We can ditch the crtc->fb check as soon as we can
 742          * properly reconstruct framebuffers.
 743          */
 744         return intel_crtc->active && crtc->fb &&
 745                 intel_crtc->config.adjusted_mode.crtc_clock;
 746 }
 747
 748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 749                                              enum pipe pipe)
 750 {
 751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 753
 754         return intel_crtc->config.cpu_transcoder;
 755 }
 756
 757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 761
 762         frame = I915_READ(frame_reg);
 763
 764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 765                 DRM_DEBUG_KMS("vblank wait timed out\n");
 766 }
 767
 768 /**
 769  * intel_wait_for_vblank - wait for vblank on a given pipe
 770  * @dev: drm device
 771  * @pipe: pipe to wait for
 772  *
 773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 774  * mode setting code.
 775  */
 776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         int pipestat_reg = PIPESTAT(pipe);
 780
 781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 782                 g4x_wait_for_vblank(dev, pipe);
 783                 return;
 784         }
 785
 786         /* Clear existing vblank status. Note this will clear any other
 787          * sticky status fields as well.
 788          *
 789          * This races with i915_driver_irq_handler() with the result
 790          * that either function could miss a vblank event.  Here it is not
 791          * fatal, as we will either wait upon the next vblank interrupt or
 792          * timeout.  Generally speaking intel_wait_for_vblank() is only
 793          * called during modeset at which time the GPU should be idle and
 794          * should *not* be performing page flips and thus not waiting on
 795          * vblanks...
 796          * Currently, the result of us stealing a vblank from the irq
 797          * handler is that a single frame will be skipped during swapbuffers.
 798          */
 799         I915_WRITE(pipestat_reg,
 800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 801
 802         /* Wait for vblank interrupt bit to set */
 803         if (wait_for(I915_READ(pipestat_reg) &
 804                      PIPE_VBLANK_INTERRUPT_STATUS,
 805                      50))
 806                 DRM_DEBUG_KMS("vblank wait timed out\n");
 807 }
 808
 809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 reg = PIPEDSL(pipe);
 813         u32 line1, line2;
 814         u32 line_mask;
 815
 816         if (IS_GEN2(dev))
 817                 line_mask = DSL_LINEMASK_GEN2;
 818         else
 819                 line_mask = DSL_LINEMASK_GEN3;
 820
 821         line1 = I915_READ(reg) & line_mask;
 822         mdelay(5);
 823         line2 = I915_READ(reg) & line_mask;
 824
 825         return line1 == line2;
 826 }
 827
 828 /*
 829  * intel_wait_for_pipe_off - wait for pipe to turn off
 830  * @dev: drm device
 831  * @pipe: pipe to wait for
 832  *
 833  * After disabling a pipe, we can't wait for vblank in the usual way,
 834  * spinning on the vblank interrupt status bit, since we won't actually
 835  * see an interrupt when the pipe is disabled.
 836  *
 837  * On Gen4 and above:
 838  *   wait for the pipe register state bit to turn off
 839  *
 840  * Otherwise:
 841  *   wait for the display line value to settle (it usually
 842  *   ends up stopping at the start of the next frame).
 843  *
 844  */
 845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 849                                                                       pipe);
 850
 851         if (INTEL_INFO(dev)->gen >= 4) {
 852                 int reg = PIPECONF(cpu_transcoder);
 853
 854                 /* Wait for the Pipe State to go off */
 855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 856                              100))
 857                         WARN(1, "pipe_off wait timed out\n");
 858         } else {
 859                 /* Wait for the display line to settle */
 860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371         /*
1372          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1373          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1374          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1375          *   b. The other bits such as sfr settings / modesel may all be set
1376          *      to 0.
1377          *
1378          * This should only be done on init and resume from S3 with both
1379          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1380          */
1381         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1382 }
1383
1384 static void vlv_enable_pll(struct intel_crtc *crtc)
1385 {
1386         struct drm_device *dev = crtc->base.dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         int reg = DPLL(crtc->pipe);
1389         u32 dpll = crtc->config.dpll_hw_state.dpll;
1390
1391         assert_pipe_disabled(dev_priv, crtc->pipe);
1392
1393         /* No really, not for ILK+ */
1394         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1395
1396         /* PLL is protected by panel, make sure we can write it */
1397         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1398                 assert_panel_unlocked(dev_priv, crtc->pipe);
1399
1400         I915_WRITE(reg, dpll);
1401         POSTING_READ(reg);
1402         udelay(150);
1403
1404         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1405                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1406
1407         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1408         POSTING_READ(DPLL_MD(crtc->pipe));
1409
1410         /* We do this three times for luck */
1411         I915_WRITE(reg, dpll);
1412         POSTING_READ(reg);
1413         udelay(150); /* wait for warmup */
1414         I915_WRITE(reg, dpll);
1415         POSTING_READ(reg);
1416         udelay(150); /* wait for warmup */
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150); /* wait for warmup */
1420 }
1421
1422 static void i9xx_enable_pll(struct intel_crtc *crtc)
1423 {
1424         struct drm_device *dev = crtc->base.dev;
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         int reg = DPLL(crtc->pipe);
1427         u32 dpll = crtc->config.dpll_hw_state.dpll;
1428
1429         assert_pipe_disabled(dev_priv, crtc->pipe);
1430
1431         /* No really, not for ILK+ */
1432         BUG_ON(dev_priv->info->gen >= 5);
1433
1434         /* PLL is protected by panel, make sure we can write it */
1435         if (IS_MOBILE(dev) && !IS_I830(dev))
1436                 assert_panel_unlocked(dev_priv, crtc->pipe);
1437
1438         I915_WRITE(reg, dpll);
1439
1440         /* Wait for the clocks to stabilize. */
1441         POSTING_READ(reg);
1442         udelay(150);
1443
1444         if (INTEL_INFO(dev)->gen >= 4) {
1445                 I915_WRITE(DPLL_MD(crtc->pipe),
1446                            crtc->config.dpll_hw_state.dpll_md);
1447         } else {
1448                 /* The pixel multiplier can only be updated once the
1449                  * DPLL is enabled and the clocks are stable.
1450                  *
1451                  * So write it again.
1452                  */
1453                 I915_WRITE(reg, dpll);
1454         }
1455
1456         /* We do this three times for luck */
1457         I915_WRITE(reg, dpll);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, dpll);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463         I915_WRITE(reg, dpll);
1464         POSTING_READ(reg);
1465         udelay(150); /* wait for warmup */
1466 }
1467
1468 /**
1469  * i9xx_disable_pll - disable a PLL
1470  * @dev_priv: i915 private structure
1471  * @pipe: pipe PLL to disable
1472  *
1473  * Disable the PLL for @pipe, making sure the pipe is off first.
1474  *
1475  * Note!  This is for pre-ILK only.
1476  */
1477 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478 {
1479         /* Don't disable pipe A or pipe A PLLs if needed */
1480         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481                 return;
1482
1483         /* Make sure the pipe isn't still relying on us */
1484         assert_pipe_disabled(dev_priv, pipe);
1485
1486         I915_WRITE(DPLL(pipe), 0);
1487         POSTING_READ(DPLL(pipe));
1488 }
1489
1490 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491 {
1492         u32 val = 0;
1493
1494         /* Make sure the pipe isn't still relying on us */
1495         assert_pipe_disabled(dev_priv, pipe);
1496
1497         /* Leave integrated clock source enabled */
1498         if (pipe == PIPE_B)
1499                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1500         I915_WRITE(DPLL(pipe), val);
1501         POSTING_READ(DPLL(pipe));
1502 }
1503
1504 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1505                 struct intel_digital_port *dport)
1506 {
1507         u32 port_mask;
1508
1509         switch (dport->port) {
1510         case PORT_B:
1511                 port_mask = DPLL_PORTB_READY_MASK;
1512                 break;
1513         case PORT_C:
1514                 port_mask = DPLL_PORTC_READY_MASK;
1515                 break;
1516         default:
1517                 BUG();
1518         }
1519
1520         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1521                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1522                      port_name(dport->port), I915_READ(DPLL(0)));
1523 }
1524
1525 /**
1526  * ironlake_enable_shared_dpll - enable PCH PLL
1527  * @dev_priv: i915 private structure
1528  * @pipe: pipe PLL to enable
1529  *
1530  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1531  * drives the transcoder clock.
1532  */
1533 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1534 {
1535         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1536         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1537
1538         /* PCH PLLs only available on ILK, SNB and IVB */
1539         BUG_ON(dev_priv->info->gen < 5);
1540         if (WARN_ON(pll == NULL))
1541                 return;
1542
1543         if (WARN_ON(pll->refcount == 0))
1544                 return;
1545
1546         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1547                       pll->name, pll->active, pll->on,
1548                       crtc->base.base.id);
1549
1550         if (pll->active++) {
1551                 WARN_ON(!pll->on);
1552                 assert_shared_dpll_enabled(dev_priv, pll);
1553                 return;
1554         }
1555         WARN_ON(pll->on);
1556
1557         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1558         pll->enable(dev_priv, pll);
1559         pll->on = true;
1560 }
1561
1562 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1563 {
1564         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1565         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1566
1567         /* PCH only available on ILK+ */
1568         BUG_ON(dev_priv->info->gen < 5);
1569         if (WARN_ON(pll == NULL))
1570                return;
1571
1572         if (WARN_ON(pll->refcount == 0))
1573                 return;
1574
1575         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1576                       pll->name, pll->active, pll->on,
1577                       crtc->base.base.id);
1578
1579         if (WARN_ON(pll->active == 0)) {
1580                 assert_shared_dpll_disabled(dev_priv, pll);
1581                 return;
1582         }
1583
1584         assert_shared_dpll_enabled(dev_priv, pll);
1585         WARN_ON(!pll->on);
1586         if (--pll->active)
1587                 return;
1588
1589         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1590         pll->disable(dev_priv, pll);
1591         pll->on = false;
1592 }
1593
1594 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1595                                            enum pipe pipe)
1596 {
1597         struct drm_device *dev = dev_priv->dev;
1598         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1600         uint32_t reg, val, pipeconf_val;
1601
1602         /* PCH only available on ILK+ */
1603         BUG_ON(dev_priv->info->gen < 5);
1604
1605         /* Make sure PCH DPLL is enabled */
1606         assert_shared_dpll_enabled(dev_priv,
1607                                    intel_crtc_to_shared_dpll(intel_crtc));
1608
1609         /* FDI must be feeding us bits for PCH ports */
1610         assert_fdi_tx_enabled(dev_priv, pipe);
1611         assert_fdi_rx_enabled(dev_priv, pipe);
1612
1613         if (HAS_PCH_CPT(dev)) {
1614                 /* Workaround: Set the timing override bit before enabling the
1615                  * pch transcoder. */
1616                 reg = TRANS_CHICKEN2(pipe);
1617                 val = I915_READ(reg);
1618                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1619                 I915_WRITE(reg, val);
1620         }
1621
1622         reg = PCH_TRANSCONF(pipe);
1623         val = I915_READ(reg);
1624         pipeconf_val = I915_READ(PIPECONF(pipe));
1625
1626         if (HAS_PCH_IBX(dev_priv->dev)) {
1627                 /*
1628                  * make the BPC in transcoder be consistent with
1629                  * that in pipeconf reg.
1630                  */
1631                 val &= ~PIPECONF_BPC_MASK;
1632                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1633         }
1634
1635         val &= ~TRANS_INTERLACE_MASK;
1636         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1637                 if (HAS_PCH_IBX(dev_priv->dev) &&
1638                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1639                         val |= TRANS_LEGACY_INTERLACED_ILK;
1640                 else
1641                         val |= TRANS_INTERLACED;
1642         else
1643                 val |= TRANS_PROGRESSIVE;
1644
1645         I915_WRITE(reg, val | TRANS_ENABLE);
1646         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1647                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1648 }
1649
1650 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1651                                       enum transcoder cpu_transcoder)
1652 {
1653         u32 val, pipeconf_val;
1654
1655         /* PCH only available on ILK+ */
1656         BUG_ON(dev_priv->info->gen < 5);
1657
1658         /* FDI must be feeding us bits for PCH ports */
1659         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1660         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1661
1662         /* Workaround: set timing override bit. */
1663         val = I915_READ(_TRANSA_CHICKEN2);
1664         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1665         I915_WRITE(_TRANSA_CHICKEN2, val);
1666
1667         val = TRANS_ENABLE;
1668         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1669
1670         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1671             PIPECONF_INTERLACED_ILK)
1672                 val |= TRANS_INTERLACED;
1673         else
1674                 val |= TRANS_PROGRESSIVE;
1675
1676         I915_WRITE(LPT_TRANSCONF, val);
1677         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1678                 DRM_ERROR("Failed to enable PCH transcoder\n");
1679 }
1680
1681 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1682                                             enum pipe pipe)
1683 {
1684         struct drm_device *dev = dev_priv->dev;
1685         uint32_t reg, val;
1686
1687         /* FDI relies on the transcoder */
1688         assert_fdi_tx_disabled(dev_priv, pipe);
1689         assert_fdi_rx_disabled(dev_priv, pipe);
1690
1691         /* Ports must be off as well */
1692         assert_pch_ports_disabled(dev_priv, pipe);
1693
1694         reg = PCH_TRANSCONF(pipe);
1695         val = I915_READ(reg);
1696         val &= ~TRANS_ENABLE;
1697         I915_WRITE(reg, val);
1698         /* wait for PCH transcoder off, transcoder state */
1699         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1700                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1701
1702         if (!HAS_PCH_IBX(dev)) {
1703                 /* Workaround: Clear the timing override chicken bit again. */
1704                 reg = TRANS_CHICKEN2(pipe);
1705                 val = I915_READ(reg);
1706                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1707                 I915_WRITE(reg, val);
1708         }
1709 }
1710
1711 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1712 {
1713         u32 val;
1714
1715         val = I915_READ(LPT_TRANSCONF);
1716         val &= ~TRANS_ENABLE;
1717         I915_WRITE(LPT_TRANSCONF, val);
1718         /* wait for PCH transcoder off, transcoder state */
1719         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1720                 DRM_ERROR("Failed to disable PCH transcoder\n");
1721
1722         /* Workaround: clear timing override bit. */
1723         val = I915_READ(_TRANSA_CHICKEN2);
1724         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1725         I915_WRITE(_TRANSA_CHICKEN2, val);
1726 }
1727
1728 /**
1729  * intel_enable_pipe - enable a pipe, asserting requirements
1730  * @dev_priv: i915 private structure
1731  * @pipe: pipe to enable
1732  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1733  *
1734  * Enable @pipe, making sure that various hardware specific requirements
1735  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1736  *
1737  * @pipe should be %PIPE_A or %PIPE_B.
1738  *
1739  * Will wait until the pipe is actually running (i.e. first vblank) before
1740  * returning.
1741  */
1742 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1743                               bool pch_port, bool dsi)
1744 {
1745         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1746                                                                       pipe);
1747         enum pipe pch_transcoder;
1748         int reg;
1749         u32 val;
1750
1751         assert_planes_disabled(dev_priv, pipe);
1752         assert_cursor_disabled(dev_priv, pipe);
1753         assert_sprites_disabled(dev_priv, pipe);
1754
1755         if (HAS_PCH_LPT(dev_priv->dev))
1756                 pch_transcoder = TRANSCODER_A;
1757         else
1758                 pch_transcoder = pipe;
1759
1760         /*
1761          * A pipe without a PLL won't actually be able to drive bits from
1762          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1763          * need the check.
1764          */
1765         if (!HAS_PCH_SPLIT(dev_priv->dev))
1766                 if (dsi)
1767                         assert_dsi_pll_enabled(dev_priv);
1768                 else
1769                         assert_pll_enabled(dev_priv, pipe);
1770         else {
1771                 if (pch_port) {
1772                         /* if driving the PCH, we need FDI enabled */
1773                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1774                         assert_fdi_tx_pll_enabled(dev_priv,
1775                                                   (enum pipe) cpu_transcoder);
1776                 }
1777                 /* FIXME: assert CPU port conditions for SNB+ */
1778         }
1779
1780         reg = PIPECONF(cpu_transcoder);
1781         val = I915_READ(reg);
1782         if (val & PIPECONF_ENABLE)
1783                 return;
1784
1785         I915_WRITE(reg, val | PIPECONF_ENABLE);
1786         intel_wait_for_vblank(dev_priv->dev, pipe);
1787 }
1788
1789 /**
1790  * intel_disable_pipe - disable a pipe, asserting requirements
1791  * @dev_priv: i915 private structure
1792  * @pipe: pipe to disable
1793  *
1794  * Disable @pipe, making sure that various hardware specific requirements
1795  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1796  *
1797  * @pipe should be %PIPE_A or %PIPE_B.
1798  *
1799  * Will wait until the pipe has shut down before returning.
1800  */
1801 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1802                                enum pipe pipe)
1803 {
1804         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1805                                                                       pipe);
1806         int reg;
1807         u32 val;
1808
1809         /*
1810          * Make sure planes won't keep trying to pump pixels to us,
1811          * or we might hang the display.
1812          */
1813         assert_planes_disabled(dev_priv, pipe);
1814         assert_cursor_disabled(dev_priv, pipe);
1815         assert_sprites_disabled(dev_priv, pipe);
1816
1817         /* Don't disable pipe A or pipe A PLLs if needed */
1818         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1819                 return;
1820
1821         reg = PIPECONF(cpu_transcoder);
1822         val = I915_READ(reg);
1823         if ((val & PIPECONF_ENABLE) == 0)
1824                 return;
1825
1826         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1827         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1828 }
1829
1830 /*
1831  * Plane regs are double buffered, going from enabled->disabled needs a
1832  * trigger in order to latch.  The display address reg provides this.
1833  */
1834 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1835                                enum plane plane)
1836 {
1837         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1838
1839         I915_WRITE(reg, I915_READ(reg));
1840         POSTING_READ(reg);
1841 }
1842
1843 /**
1844  * intel_enable_primary_plane - enable the primary plane on a given pipe
1845  * @dev_priv: i915 private structure
1846  * @plane: plane to enable
1847  * @pipe: pipe being fed
1848  *
1849  * Enable @plane on @pipe, making sure that @pipe is running first.
1850  */
1851 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1852                                        enum plane plane, enum pipe pipe)
1853 {
1854         struct intel_crtc *intel_crtc =
1855                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1856         int reg;
1857         u32 val;
1858
1859         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860         assert_pipe_enabled(dev_priv, pipe);
1861
1862         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1863
1864         intel_crtc->primary_enabled = true;
1865
1866         reg = DSPCNTR(plane);
1867         val = I915_READ(reg);
1868         if (val & DISPLAY_PLANE_ENABLE)
1869                 return;
1870
1871         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1872         intel_flush_primary_plane(dev_priv, plane);
1873         intel_wait_for_vblank(dev_priv->dev, pipe);
1874 }
1875
1876 /**
1877  * intel_disable_primary_plane - disable the primary plane
1878  * @dev_priv: i915 private structure
1879  * @plane: plane to disable
1880  * @pipe: pipe consuming the data
1881  *
1882  * Disable @plane; should be an independent operation.
1883  */
1884 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1885                                         enum plane plane, enum pipe pipe)
1886 {
1887         struct intel_crtc *intel_crtc =
1888                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1889         int reg;
1890         u32 val;
1891
1892         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1893
1894         intel_crtc->primary_enabled = false;
1895
1896         reg = DSPCNTR(plane);
1897         val = I915_READ(reg);
1898         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1899                 return;
1900
1901         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1902         intel_flush_primary_plane(dev_priv, plane);
1903         intel_wait_for_vblank(dev_priv->dev, pipe);
1904 }
1905
1906 static bool need_vtd_wa(struct drm_device *dev)
1907 {
1908 #ifdef CONFIG_INTEL_IOMMU
1909         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1910                 return true;
1911 #endif
1912         return false;
1913 }
1914
1915 int
1916 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1917                            struct drm_i915_gem_object *obj,
1918                            struct intel_ring_buffer *pipelined)
1919 {
1920         struct drm_i915_private *dev_priv = dev->dev_private;
1921         u32 alignment;
1922         int ret;
1923
1924         switch (obj->tiling_mode) {
1925         case I915_TILING_NONE:
1926                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1927                         alignment = 128 * 1024;
1928                 else if (INTEL_INFO(dev)->gen >= 4)
1929                         alignment = 4 * 1024;
1930                 else
1931                         alignment = 64 * 1024;
1932                 break;
1933         case I915_TILING_X:
1934                 /* pin() will align the object as required by fence */
1935                 alignment = 0;
1936                 break;
1937         case I915_TILING_Y:
1938                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1939                 return -EINVAL;
1940         default:
1941                 BUG();
1942         }
1943
1944         /* Note that the w/a also requires 64 PTE of padding following the
1945          * bo. We currently fill all unused PTE with the shadow page and so
1946          * we should always have valid PTE following the scanout preventing
1947          * the VT-d warning.
1948          */
1949         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1950                 alignment = 256 * 1024;
1951
1952         dev_priv->mm.interruptible = false;
1953         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1954         if (ret)
1955                 goto err_interruptible;
1956
1957         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1958          * fence, whereas 965+ only requires a fence if using
1959          * framebuffer compression.  For simplicity, we always install
1960          * a fence as the cost is not that onerous.
1961          */
1962         ret = i915_gem_object_get_fence(obj);
1963         if (ret)
1964                 goto err_unpin;
1965
1966         i915_gem_object_pin_fence(obj);
1967
1968         dev_priv->mm.interruptible = true;
1969         return 0;
1970
1971 err_unpin:
1972         i915_gem_object_unpin_from_display_plane(obj);
1973 err_interruptible:
1974         dev_priv->mm.interruptible = true;
1975         return ret;
1976 }
1977
1978 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1979 {
1980         i915_gem_object_unpin_fence(obj);
1981         i915_gem_object_unpin_from_display_plane(obj);
1982 }
1983
1984 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1985  * is assumed to be a power-of-two. */
1986 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1987                                              unsigned int tiling_mode,
1988                                              unsigned int cpp,
1989                                              unsigned int pitch)
1990 {
1991         if (tiling_mode != I915_TILING_NONE) {
1992                 unsigned int tile_rows, tiles;
1993
1994                 tile_rows = *y / 8;
1995                 *y %= 8;
1996
1997                 tiles = *x / (512/cpp);
1998                 *x %= 512/cpp;
1999
2000                 return tile_rows * pitch * 8 + tiles * 4096;
2001         } else {
2002                 unsigned int offset;
2003
2004                 offset = *y * pitch + *x * cpp;
2005                 *y = 0;
2006                 *x = (offset & 4095) / cpp;
2007                 return offset & -4096;
2008         }
2009 }
2010
2011 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2012                              int x, int y)
2013 {
2014         struct drm_device *dev = crtc->dev;
2015         struct drm_i915_private *dev_priv = dev->dev_private;
2016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2017         struct intel_framebuffer *intel_fb;
2018         struct drm_i915_gem_object *obj;
2019         int plane = intel_crtc->plane;
2020         unsigned long linear_offset;
2021         u32 dspcntr;
2022         u32 reg;
2023
2024         switch (plane) {
2025         case 0:
2026         case 1:
2027                 break;
2028         default:
2029                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2030                 return -EINVAL;
2031         }
2032
2033         intel_fb = to_intel_framebuffer(fb);
2034         obj = intel_fb->obj;
2035
2036         reg = DSPCNTR(plane);
2037         dspcntr = I915_READ(reg);
2038         /* Mask out pixel format bits in case we change it */
2039         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2040         switch (fb->pixel_format) {
2041         case DRM_FORMAT_C8:
2042                 dspcntr |= DISPPLANE_8BPP;
2043                 break;
2044         case DRM_FORMAT_XRGB1555:
2045         case DRM_FORMAT_ARGB1555:
2046                 dspcntr |= DISPPLANE_BGRX555;
2047                 break;
2048         case DRM_FORMAT_RGB565:
2049                 dspcntr |= DISPPLANE_BGRX565;
2050                 break;
2051         case DRM_FORMAT_XRGB8888:
2052         case DRM_FORMAT_ARGB8888:
2053                 dspcntr |= DISPPLANE_BGRX888;
2054                 break;
2055         case DRM_FORMAT_XBGR8888:
2056         case DRM_FORMAT_ABGR8888:
2057                 dspcntr |= DISPPLANE_RGBX888;
2058                 break;
2059         case DRM_FORMAT_XRGB2101010:
2060         case DRM_FORMAT_ARGB2101010:
2061                 dspcntr |= DISPPLANE_BGRX101010;
2062                 break;
2063         case DRM_FORMAT_XBGR2101010:
2064         case DRM_FORMAT_ABGR2101010:
2065                 dspcntr |= DISPPLANE_RGBX101010;
2066                 break;
2067         default:
2068                 BUG();
2069         }
2070
2071         if (INTEL_INFO(dev)->gen >= 4) {
2072                 if (obj->tiling_mode != I915_TILING_NONE)
2073                         dspcntr |= DISPPLANE_TILED;
2074                 else
2075                         dspcntr &= ~DISPPLANE_TILED;
2076         }
2077
2078         if (IS_G4X(dev))
2079                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2080
2081         I915_WRITE(reg, dspcntr);
2082
2083         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2084
2085         if (INTEL_INFO(dev)->gen >= 4) {
2086                 intel_crtc->dspaddr_offset =
2087                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2088                                                        fb->bits_per_pixel / 8,
2089                                                        fb->pitches[0]);
2090                 linear_offset -= intel_crtc->dspaddr_offset;
2091         } else {
2092                 intel_crtc->dspaddr_offset = linear_offset;
2093         }
2094
2095         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2096                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2097                       fb->pitches[0]);
2098         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2099         if (INTEL_INFO(dev)->gen >= 4) {
2100                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2102                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         } else
2105                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2106         POSTING_READ(reg);
2107
2108         return 0;
2109 }
2110
2111 static int ironlake_update_plane(struct drm_crtc *crtc,
2112                                  struct drm_framebuffer *fb, int x, int y)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2117         struct intel_framebuffer *intel_fb;
2118         struct drm_i915_gem_object *obj;
2119         int plane = intel_crtc->plane;
2120         unsigned long linear_offset;
2121         u32 dspcntr;
2122         u32 reg;
2123
2124         switch (plane) {
2125         case 0:
2126         case 1:
2127         case 2:
2128                 break;
2129         default:
2130                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2131                 return -EINVAL;
2132         }
2133
2134         intel_fb = to_intel_framebuffer(fb);
2135         obj = intel_fb->obj;
2136
2137         reg = DSPCNTR(plane);
2138         dspcntr = I915_READ(reg);
2139         /* Mask out pixel format bits in case we change it */
2140         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2141         switch (fb->pixel_format) {
2142         case DRM_FORMAT_C8:
2143                 dspcntr |= DISPPLANE_8BPP;
2144                 break;
2145         case DRM_FORMAT_RGB565:
2146                 dspcntr |= DISPPLANE_BGRX565;
2147                 break;
2148         case DRM_FORMAT_XRGB8888:
2149         case DRM_FORMAT_ARGB8888:
2150                 dspcntr |= DISPPLANE_BGRX888;
2151                 break;
2152         case DRM_FORMAT_XBGR8888:
2153         case DRM_FORMAT_ABGR8888:
2154                 dspcntr |= DISPPLANE_RGBX888;
2155                 break;
2156         case DRM_FORMAT_XRGB2101010:
2157         case DRM_FORMAT_ARGB2101010:
2158                 dspcntr |= DISPPLANE_BGRX101010;
2159                 break;
2160         case DRM_FORMAT_XBGR2101010:
2161         case DRM_FORMAT_ABGR2101010:
2162                 dspcntr |= DISPPLANE_RGBX101010;
2163                 break;
2164         default:
2165                 BUG();
2166         }
2167
2168         if (obj->tiling_mode != I915_TILING_NONE)
2169                 dspcntr |= DISPPLANE_TILED;
2170         else
2171                 dspcntr &= ~DISPPLANE_TILED;
2172
2173         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2174                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2175         else
2176                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2177
2178         I915_WRITE(reg, dspcntr);
2179
2180         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2181         intel_crtc->dspaddr_offset =
2182                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2183                                                fb->bits_per_pixel / 8,
2184                                                fb->pitches[0]);
2185         linear_offset -= intel_crtc->dspaddr_offset;
2186
2187         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2188                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2189                       fb->pitches[0]);
2190         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2191         I915_MODIFY_DISPBASE(DSPSURF(plane),
2192                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2193         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2194                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2195         } else {
2196                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2197                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2198         }
2199         POSTING_READ(reg);
2200
2201         return 0;
2202 }
2203
2204 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2205 static int
2206 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2207                            int x, int y, enum mode_set_atomic state)
2208 {
2209         struct drm_device *dev = crtc->dev;
2210         struct drm_i915_private *dev_priv = dev->dev_private;
2211
2212         if (dev_priv->display.disable_fbc)
2213                 dev_priv->display.disable_fbc(dev);
2214         intel_increase_pllclock(crtc);
2215
2216         return dev_priv->display.update_plane(crtc, fb, x, y);
2217 }
2218
2219 void intel_display_handle_reset(struct drm_device *dev)
2220 {
2221         struct drm_i915_private *dev_priv = dev->dev_private;
2222         struct drm_crtc *crtc;
2223
2224         /*
2225          * Flips in the rings have been nuked by the reset,
2226          * so complete all pending flips so that user space
2227          * will get its events and not get stuck.
2228          *
2229          * Also update the base address of all primary
2230          * planes to the the last fb to make sure we're
2231          * showing the correct fb after a reset.
2232          *
2233          * Need to make two loops over the crtcs so that we
2234          * don't try to grab a crtc mutex before the
2235          * pending_flip_queue really got woken up.
2236          */
2237
2238         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2239                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2240                 enum plane plane = intel_crtc->plane;
2241
2242                 intel_prepare_page_flip(dev, plane);
2243                 intel_finish_page_flip_plane(dev, plane);
2244         }
2245
2246         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2247                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2248
2249                 mutex_lock(&crtc->mutex);
2250                 /*
2251                  * FIXME: Once we have proper support for primary planes (and
2252                  * disabling them without disabling the entire crtc) allow again
2253                  * a NULL crtc->fb.
2254                  */
2255                 if (intel_crtc->active && crtc->fb)
2256                         dev_priv->display.update_plane(crtc, crtc->fb,
2257                                                        crtc->x, crtc->y);
2258                 mutex_unlock(&crtc->mutex);
2259         }
2260 }
2261
2262 static int
2263 intel_finish_fb(struct drm_framebuffer *old_fb)
2264 {
2265         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2266         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2267         bool was_interruptible = dev_priv->mm.interruptible;
2268         int ret;
2269
2270         /* Big Hammer, we also need to ensure that any pending
2271          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2272          * current scanout is retired before unpinning the old
2273          * framebuffer.
2274          *
2275          * This should only fail upon a hung GPU, in which case we
2276          * can safely continue.
2277          */
2278         dev_priv->mm.interruptible = false;
2279         ret = i915_gem_object_finish_gpu(obj);
2280         dev_priv->mm.interruptible = was_interruptible;
2281
2282         return ret;
2283 }
2284
2285 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2286 {
2287         struct drm_device *dev = crtc->dev;
2288         struct drm_i915_master_private *master_priv;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290
2291         if (!dev->primary->master)
2292                 return;
2293
2294         master_priv = dev->primary->master->driver_priv;
2295         if (!master_priv->sarea_priv)
2296                 return;
2297
2298         switch (intel_crtc->pipe) {
2299         case 0:
2300                 master_priv->sarea_priv->pipeA_x = x;
2301                 master_priv->sarea_priv->pipeA_y = y;
2302                 break;
2303         case 1:
2304                 master_priv->sarea_priv->pipeB_x = x;
2305                 master_priv->sarea_priv->pipeB_y = y;
2306                 break;
2307         default:
2308                 break;
2309         }
2310 }
2311
2312 static int
2313 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2314                     struct drm_framebuffer *fb)
2315 {
2316         struct drm_device *dev = crtc->dev;
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319         struct drm_framebuffer *old_fb;
2320         int ret;
2321
2322         /* no fb bound */
2323         if (!fb) {
2324                 DRM_ERROR("No FB bound\n");
2325                 return 0;
2326         }
2327
2328         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2329                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2330                           plane_name(intel_crtc->plane),
2331                           INTEL_INFO(dev)->num_pipes);
2332                 return -EINVAL;
2333         }
2334
2335         mutex_lock(&dev->struct_mutex);
2336         ret = intel_pin_and_fence_fb_obj(dev,
2337                                          to_intel_framebuffer(fb)->obj,
2338                                          NULL);
2339         if (ret != 0) {
2340                 mutex_unlock(&dev->struct_mutex);
2341                 DRM_ERROR("pin & fence failed\n");
2342                 return ret;
2343         }
2344
2345         /*
2346          * Update pipe size and adjust fitter if needed: the reason for this is
2347          * that in compute_mode_changes we check the native mode (not the pfit
2348          * mode) to see if we can flip rather than do a full mode set. In the
2349          * fastboot case, we'll flip, but if we don't update the pipesrc and
2350          * pfit state, we'll end up with a big fb scanned out into the wrong
2351          * sized surface.
2352          *
2353          * To fix this properly, we need to hoist the checks up into
2354          * compute_mode_changes (or above), check the actual pfit state and
2355          * whether the platform allows pfit disable with pipe active, and only
2356          * then update the pipesrc and pfit state, even on the flip path.
2357          */
2358         if (i915_fastboot) {
2359                 const struct drm_display_mode *adjusted_mode =
2360                         &intel_crtc->config.adjusted_mode;
2361
2362                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2363                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2364                            (adjusted_mode->crtc_vdisplay - 1));
2365                 if (!intel_crtc->config.pch_pfit.enabled &&
2366                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2367                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2368                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2369                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2370                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2371                 }
2372         }
2373
2374         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2375         if (ret) {
2376                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2377                 mutex_unlock(&dev->struct_mutex);
2378                 DRM_ERROR("failed to update base address\n");
2379                 return ret;
2380         }
2381
2382         old_fb = crtc->fb;
2383         crtc->fb = fb;
2384         crtc->x = x;
2385         crtc->y = y;
2386
2387         if (old_fb) {
2388                 if (intel_crtc->active && old_fb != fb)
2389                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2390                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2391         }
2392
2393         intel_update_fbc(dev);
2394         intel_edp_psr_update(dev);
2395         mutex_unlock(&dev->struct_mutex);
2396
2397         intel_crtc_update_sarea_pos(crtc, x, y);
2398
2399         return 0;
2400 }
2401
2402 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2403 {
2404         struct drm_device *dev = crtc->dev;
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407         int pipe = intel_crtc->pipe;
2408         u32 reg, temp;
2409
2410         /* enable normal train */
2411         reg = FDI_TX_CTL(pipe);
2412         temp = I915_READ(reg);
2413         if (IS_IVYBRIDGE(dev)) {
2414                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2415                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2416         } else {
2417                 temp &= ~FDI_LINK_TRAIN_NONE;
2418                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2419         }
2420         I915_WRITE(reg, temp);
2421
2422         reg = FDI_RX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         if (HAS_PCH_CPT(dev)) {
2425                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2427         } else {
2428                 temp &= ~FDI_LINK_TRAIN_NONE;
2429                 temp |= FDI_LINK_TRAIN_NONE;
2430         }
2431         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2432
2433         /* wait one idle pattern time */
2434         POSTING_READ(reg);
2435         udelay(1000);
2436
2437         /* IVB wants error correction enabled */
2438         if (IS_IVYBRIDGE(dev))
2439                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2440                            FDI_FE_ERRC_ENABLE);
2441 }
2442
2443 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2444 {
2445         return crtc->base.enabled && crtc->active &&
2446                 crtc->config.has_pch_encoder;
2447 }
2448
2449 static void ivb_modeset_global_resources(struct drm_device *dev)
2450 {
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452         struct intel_crtc *pipe_B_crtc =
2453                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2454         struct intel_crtc *pipe_C_crtc =
2455                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2456         uint32_t temp;
2457
2458         /*
2459          * When everything is off disable fdi C so that we could enable fdi B
2460          * with all lanes. Note that we don't care about enabled pipes without
2461          * an enabled pch encoder.
2462          */
2463         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2464             !pipe_has_enabled_pch(pipe_C_crtc)) {
2465                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2466                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2467
2468                 temp = I915_READ(SOUTH_CHICKEN1);
2469                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2470                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2471                 I915_WRITE(SOUTH_CHICKEN1, temp);
2472         }
2473 }
2474
2475 /* The FDI link training functions for ILK/Ibexpeak. */
2476 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2477 {
2478         struct drm_device *dev = crtc->dev;
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481         int pipe = intel_crtc->pipe;
2482         int plane = intel_crtc->plane;
2483         u32 reg, temp, tries;
2484
2485         /* FDI needs bits from pipe & plane first */
2486         assert_pipe_enabled(dev_priv, pipe);
2487         assert_plane_enabled(dev_priv, plane);
2488
2489         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2490            for train result */
2491         reg = FDI_RX_IMR(pipe);
2492         temp = I915_READ(reg);
2493         temp &= ~FDI_RX_SYMBOL_LOCK;
2494         temp &= ~FDI_RX_BIT_LOCK;
2495         I915_WRITE(reg, temp);
2496         I915_READ(reg);
2497         udelay(150);
2498
2499         /* enable CPU FDI TX and PCH FDI RX */
2500         reg = FDI_TX_CTL(pipe);
2501         temp = I915_READ(reg);
2502         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2503         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2504         temp &= ~FDI_LINK_TRAIN_NONE;
2505         temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2507
2508         reg = FDI_RX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         temp &= ~FDI_LINK_TRAIN_NONE;
2511         temp |= FDI_LINK_TRAIN_PATTERN_1;
2512         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2513
2514         POSTING_READ(reg);
2515         udelay(150);
2516
2517         /* Ironlake workaround, enable clock pointer after FDI enable*/
2518         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2519         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2520                    FDI_RX_PHASE_SYNC_POINTER_EN);
2521
2522         reg = FDI_RX_IIR(pipe);
2523         for (tries = 0; tries < 5; tries++) {
2524                 temp = I915_READ(reg);
2525                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2526
2527                 if ((temp & FDI_RX_BIT_LOCK)) {
2528                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2529                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2530                         break;
2531                 }
2532         }
2533         if (tries == 5)
2534                 DRM_ERROR("FDI train 1 fail!\n");
2535
2536         /* Train 2 */
2537         reg = FDI_TX_CTL(pipe);
2538         temp = I915_READ(reg);
2539         temp &= ~FDI_LINK_TRAIN_NONE;
2540         temp |= FDI_LINK_TRAIN_PATTERN_2;
2541         I915_WRITE(reg, temp);
2542
2543         reg = FDI_RX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~FDI_LINK_TRAIN_NONE;
2546         temp |= FDI_LINK_TRAIN_PATTERN_2;
2547         I915_WRITE(reg, temp);
2548
2549         POSTING_READ(reg);
2550         udelay(150);
2551
2552         reg = FDI_RX_IIR(pipe);
2553         for (tries = 0; tries < 5; tries++) {
2554                 temp = I915_READ(reg);
2555                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2556
2557                 if (temp & FDI_RX_SYMBOL_LOCK) {
2558                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2559                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2560                         break;
2561                 }
2562         }
2563         if (tries == 5)
2564                 DRM_ERROR("FDI train 2 fail!\n");
2565
2566         DRM_DEBUG_KMS("FDI train done\n");
2567
2568 }
2569
2570 static const int snb_b_fdi_train_param[] = {
2571         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2572         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2573         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2574         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2575 };
2576
2577 /* The FDI link training functions for SNB/Cougarpoint. */
2578 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2579 {
2580         struct drm_device *dev = crtc->dev;
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2583         int pipe = intel_crtc->pipe;
2584         u32 reg, temp, i, retry;
2585
2586         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2587            for train result */
2588         reg = FDI_RX_IMR(pipe);
2589         temp = I915_READ(reg);
2590         temp &= ~FDI_RX_SYMBOL_LOCK;
2591         temp &= ~FDI_RX_BIT_LOCK;
2592         I915_WRITE(reg, temp);
2593
2594         POSTING_READ(reg);
2595         udelay(150);
2596
2597         /* enable CPU FDI TX and PCH FDI RX */
2598         reg = FDI_TX_CTL(pipe);
2599         temp = I915_READ(reg);
2600         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2601         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2602         temp &= ~FDI_LINK_TRAIN_NONE;
2603         temp |= FDI_LINK_TRAIN_PATTERN_1;
2604         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605         /* SNB-B */
2606         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2607         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2608
2609         I915_WRITE(FDI_RX_MISC(pipe),
2610                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2611
2612         reg = FDI_RX_CTL(pipe);
2613         temp = I915_READ(reg);
2614         if (HAS_PCH_CPT(dev)) {
2615                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2616                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2617         } else {
2618                 temp &= ~FDI_LINK_TRAIN_NONE;
2619                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620         }
2621         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2622
2623         POSTING_READ(reg);
2624         udelay(150);
2625
2626         for (i = 0; i < 4; i++) {
2627                 reg = FDI_TX_CTL(pipe);
2628                 temp = I915_READ(reg);
2629                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630                 temp |= snb_b_fdi_train_param[i];
2631                 I915_WRITE(reg, temp);
2632
2633                 POSTING_READ(reg);
2634                 udelay(500);
2635
2636                 for (retry = 0; retry < 5; retry++) {
2637                         reg = FDI_RX_IIR(pipe);
2638                         temp = I915_READ(reg);
2639                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2640                         if (temp & FDI_RX_BIT_LOCK) {
2641                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2642                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2643                                 break;
2644                         }
2645                         udelay(50);
2646                 }
2647                 if (retry < 5)
2648                         break;
2649         }
2650         if (i == 4)
2651                 DRM_ERROR("FDI train 1 fail!\n");
2652
2653         /* Train 2 */
2654         reg = FDI_TX_CTL(pipe);
2655         temp = I915_READ(reg);
2656         temp &= ~FDI_LINK_TRAIN_NONE;
2657         temp |= FDI_LINK_TRAIN_PATTERN_2;
2658         if (IS_GEN6(dev)) {
2659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660                 /* SNB-B */
2661                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2662         }
2663         I915_WRITE(reg, temp);
2664
2665         reg = FDI_RX_CTL(pipe);
2666         temp = I915_READ(reg);
2667         if (HAS_PCH_CPT(dev)) {
2668                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2669                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2670         } else {
2671                 temp &= ~FDI_LINK_TRAIN_NONE;
2672                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2673         }
2674         I915_WRITE(reg, temp);
2675
2676         POSTING_READ(reg);
2677         udelay(150);
2678
2679         for (i = 0; i < 4; i++) {
2680                 reg = FDI_TX_CTL(pipe);
2681                 temp = I915_READ(reg);
2682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683                 temp |= snb_b_fdi_train_param[i];
2684                 I915_WRITE(reg, temp);
2685
2686                 POSTING_READ(reg);
2687                 udelay(500);
2688
2689                 for (retry = 0; retry < 5; retry++) {
2690                         reg = FDI_RX_IIR(pipe);
2691                         temp = I915_READ(reg);
2692                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693                         if (temp & FDI_RX_SYMBOL_LOCK) {
2694                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2695                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2696                                 break;
2697                         }
2698                         udelay(50);
2699                 }
2700                 if (retry < 5)
2701                         break;
2702         }
2703         if (i == 4)
2704                 DRM_ERROR("FDI train 2 fail!\n");
2705
2706         DRM_DEBUG_KMS("FDI train done.\n");
2707 }
2708
2709 /* Manual link training for Ivy Bridge A0 parts */
2710 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2711 {
2712         struct drm_device *dev = crtc->dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp, i, j;
2717
2718         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2719            for train result */
2720         reg = FDI_RX_IMR(pipe);
2721         temp = I915_READ(reg);
2722         temp &= ~FDI_RX_SYMBOL_LOCK;
2723         temp &= ~FDI_RX_BIT_LOCK;
2724         I915_WRITE(reg, temp);
2725
2726         POSTING_READ(reg);
2727         udelay(150);
2728
2729         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2730                       I915_READ(FDI_RX_IIR(pipe)));
2731
2732         /* Try each vswing and preemphasis setting twice before moving on */
2733         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2734                 /* disable first in case we need to retry */
2735                 reg = FDI_TX_CTL(pipe);
2736                 temp = I915_READ(reg);
2737                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2738                 temp &= ~FDI_TX_ENABLE;
2739                 I915_WRITE(reg, temp);
2740
2741                 reg = FDI_RX_CTL(pipe);
2742                 temp = I915_READ(reg);
2743                 temp &= ~FDI_LINK_TRAIN_AUTO;
2744                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2745                 temp &= ~FDI_RX_ENABLE;
2746                 I915_WRITE(reg, temp);
2747
2748                 /* enable CPU FDI TX and PCH FDI RX */
2749                 reg = FDI_TX_CTL(pipe);
2750                 temp = I915_READ(reg);
2751                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2752                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2753                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2754                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2755                 temp |= snb_b_fdi_train_param[j/2];
2756                 temp |= FDI_COMPOSITE_SYNC;
2757                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2758
2759                 I915_WRITE(FDI_RX_MISC(pipe),
2760                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2761
2762                 reg = FDI_RX_CTL(pipe);
2763                 temp = I915_READ(reg);
2764                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2765                 temp |= FDI_COMPOSITE_SYNC;
2766                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2767
2768                 POSTING_READ(reg);
2769                 udelay(1); /* should be 0.5us */
2770
2771                 for (i = 0; i < 4; i++) {
2772                         reg = FDI_RX_IIR(pipe);
2773                         temp = I915_READ(reg);
2774                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2775
2776                         if (temp & FDI_RX_BIT_LOCK ||
2777                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2778                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2779                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2780                                               i);
2781                                 break;
2782                         }
2783                         udelay(1); /* should be 0.5us */
2784                 }
2785                 if (i == 4) {
2786                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2787                         continue;
2788                 }
2789
2790                 /* Train 2 */
2791                 reg = FDI_TX_CTL(pipe);
2792                 temp = I915_READ(reg);
2793                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2794                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2795                 I915_WRITE(reg, temp);
2796
2797                 reg = FDI_RX_CTL(pipe);
2798                 temp = I915_READ(reg);
2799                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2800                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2801                 I915_WRITE(reg, temp);
2802
2803                 POSTING_READ(reg);
2804                 udelay(2); /* should be 1.5us */
2805
2806                 for (i = 0; i < 4; i++) {
2807                         reg = FDI_RX_IIR(pipe);
2808                         temp = I915_READ(reg);
2809                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2810
2811                         if (temp & FDI_RX_SYMBOL_LOCK ||
2812                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2813                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2814                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2815                                               i);
2816                                 goto train_done;
2817                         }
2818                         udelay(2); /* should be 1.5us */
2819                 }
2820                 if (i == 4)
2821                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2822         }
2823
2824 train_done:
2825         DRM_DEBUG_KMS("FDI train done.\n");
2826 }
2827
2828 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2829 {
2830         struct drm_device *dev = intel_crtc->base.dev;
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         int pipe = intel_crtc->pipe;
2833         u32 reg, temp;
2834
2835
2836         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2837         reg = FDI_RX_CTL(pipe);
2838         temp = I915_READ(reg);
2839         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2840         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2841         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2842         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2843
2844         POSTING_READ(reg);
2845         udelay(200);
2846
2847         /* Switch from Rawclk to PCDclk */
2848         temp = I915_READ(reg);
2849         I915_WRITE(reg, temp | FDI_PCDCLK);
2850
2851         POSTING_READ(reg);
2852         udelay(200);
2853
2854         /* Enable CPU FDI TX PLL, always on for Ironlake */
2855         reg = FDI_TX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2858                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2859
2860                 POSTING_READ(reg);
2861                 udelay(100);
2862         }
2863 }
2864
2865 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2866 {
2867         struct drm_device *dev = intel_crtc->base.dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         int pipe = intel_crtc->pipe;
2870         u32 reg, temp;
2871
2872         /* Switch from PCDclk to Rawclk */
2873         reg = FDI_RX_CTL(pipe);
2874         temp = I915_READ(reg);
2875         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2876
2877         /* Disable CPU FDI TX PLL */
2878         reg = FDI_TX_CTL(pipe);
2879         temp = I915_READ(reg);
2880         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2881
2882         POSTING_READ(reg);
2883         udelay(100);
2884
2885         reg = FDI_RX_CTL(pipe);
2886         temp = I915_READ(reg);
2887         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2888
2889         /* Wait for the clocks to turn off. */
2890         POSTING_READ(reg);
2891         udelay(100);
2892 }
2893
2894 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2895 {
2896         struct drm_device *dev = crtc->dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2899         int pipe = intel_crtc->pipe;
2900         u32 reg, temp;
2901
2902         /* disable CPU FDI tx and PCH FDI rx */
2903         reg = FDI_TX_CTL(pipe);
2904         temp = I915_READ(reg);
2905         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2906         POSTING_READ(reg);
2907
2908         reg = FDI_RX_CTL(pipe);
2909         temp = I915_READ(reg);
2910         temp &= ~(0x7 << 16);
2911         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2912         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2913
2914         POSTING_READ(reg);
2915         udelay(100);
2916
2917         /* Ironlake workaround, disable clock pointer after downing FDI */
2918         if (HAS_PCH_IBX(dev)) {
2919                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2920         }
2921
2922         /* still set train pattern 1 */
2923         reg = FDI_TX_CTL(pipe);
2924         temp = I915_READ(reg);
2925         temp &= ~FDI_LINK_TRAIN_NONE;
2926         temp |= FDI_LINK_TRAIN_PATTERN_1;
2927         I915_WRITE(reg, temp);
2928
2929         reg = FDI_RX_CTL(pipe);
2930         temp = I915_READ(reg);
2931         if (HAS_PCH_CPT(dev)) {
2932                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2933                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2934         } else {
2935                 temp &= ~FDI_LINK_TRAIN_NONE;
2936                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2937         }
2938         /* BPC in FDI rx is consistent with that in PIPECONF */
2939         temp &= ~(0x07 << 16);
2940         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2941         I915_WRITE(reg, temp);
2942
2943         POSTING_READ(reg);
2944         udelay(100);
2945 }
2946
2947 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2948 {
2949         struct drm_device *dev = crtc->dev;
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2952         unsigned long flags;
2953         bool pending;
2954
2955         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2956             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2957                 return false;
2958
2959         spin_lock_irqsave(&dev->event_lock, flags);
2960         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2961         spin_unlock_irqrestore(&dev->event_lock, flags);
2962
2963         return pending;
2964 }
2965
2966 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970
2971         if (crtc->fb == NULL)
2972                 return;
2973
2974         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2975
2976         wait_event(dev_priv->pending_flip_queue,
2977                    !intel_crtc_has_pending_flip(crtc));
2978
2979         mutex_lock(&dev->struct_mutex);
2980         intel_finish_fb(crtc->fb);
2981         mutex_unlock(&dev->struct_mutex);
2982 }
2983
2984 /* Program iCLKIP clock to the desired frequency */
2985 static void lpt_program_iclkip(struct drm_crtc *crtc)
2986 {
2987         struct drm_device *dev = crtc->dev;
2988         struct drm_i915_private *dev_priv = dev->dev_private;
2989         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2990         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2991         u32 temp;
2992
2993         mutex_lock(&dev_priv->dpio_lock);
2994
2995         /* It is necessary to ungate the pixclk gate prior to programming
2996          * the divisors, and gate it back when it is done.
2997          */
2998         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000         /* Disable SSCCTL */
3001         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3002                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003                                 SBI_SSCCTL_DISABLE,
3004                         SBI_ICLK);
3005
3006         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007         if (clock == 20000) {
3008                 auxdiv = 1;
3009                 divsel = 0x41;
3010                 phaseinc = 0x20;
3011         } else {
3012                 /* The iCLK virtual clock root frequency is in MHz,
3013                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3014                  * divisors, it is necessary to divide one by another, so we
3015                  * convert the virtual clock precision to KHz here for higher
3016                  * precision.
3017                  */
3018                 u32 iclk_virtual_root_freq = 172800 * 1000;
3019                 u32 iclk_pi_range = 64;
3020                 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022                 desired_divisor = (iclk_virtual_root_freq / clock);
3023                 msb_divisor_value = desired_divisor / iclk_pi_range;
3024                 pi_value = desired_divisor % iclk_pi_range;
3025
3026                 auxdiv = 0;
3027                 divsel = msb_divisor_value - 2;
3028                 phaseinc = pi_value;
3029         }
3030
3031         /* This should not happen with any sane values */
3032         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038                         clock,
3039                         auxdiv,
3040                         divsel,
3041                         phasedir,
3042                         phaseinc);
3043
3044         /* Program SSCDIVINTPHASE6 */
3045         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3046         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3052         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3053
3054         /* Program SSCAUXDIV */
3055         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3056         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3058         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3059
3060         /* Enable modulator and associated divider */
3061         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3062         temp &= ~SBI_SSCCTL_DISABLE;
3063         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3064
3065         /* Wait for initialization time */
3066         udelay(24);
3067
3068         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3069
3070         mutex_unlock(&dev_priv->dpio_lock);
3071 }
3072
3073 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3074                                                 enum pipe pch_transcoder)
3075 {
3076         struct drm_device *dev = crtc->base.dev;
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3079
3080         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3081                    I915_READ(HTOTAL(cpu_transcoder)));
3082         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3083                    I915_READ(HBLANK(cpu_transcoder)));
3084         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3085                    I915_READ(HSYNC(cpu_transcoder)));
3086
3087         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3088                    I915_READ(VTOTAL(cpu_transcoder)));
3089         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3090                    I915_READ(VBLANK(cpu_transcoder)));
3091         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3092                    I915_READ(VSYNC(cpu_transcoder)));
3093         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3094                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3095 }
3096
3097 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3098 {
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         uint32_t temp;
3101
3102         temp = I915_READ(SOUTH_CHICKEN1);
3103         if (temp & FDI_BC_BIFURCATION_SELECT)
3104                 return;
3105
3106         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3107         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3108
3109         temp |= FDI_BC_BIFURCATION_SELECT;
3110         DRM_DEBUG_KMS("enabling fdi C rx\n");
3111         I915_WRITE(SOUTH_CHICKEN1, temp);
3112         POSTING_READ(SOUTH_CHICKEN1);
3113 }
3114
3115 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3116 {
3117         struct drm_device *dev = intel_crtc->base.dev;
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119
3120         switch (intel_crtc->pipe) {
3121         case PIPE_A:
3122                 break;
3123         case PIPE_B:
3124                 if (intel_crtc->config.fdi_lanes > 2)
3125                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3126                 else
3127                         cpt_enable_fdi_bc_bifurcation(dev);
3128
3129                 break;
3130         case PIPE_C:
3131                 cpt_enable_fdi_bc_bifurcation(dev);
3132
3133                 break;
3134         default:
3135                 BUG();
3136         }
3137 }
3138
3139 /*
3140  * Enable PCH resources required for PCH ports:
3141  *   - PCH PLLs
3142  *   - FDI training & RX/TX
3143  *   - update transcoder timings
3144  *   - DP transcoding bits
3145  *   - transcoder
3146  */
3147 static void ironlake_pch_enable(struct drm_crtc *crtc)
3148 {
3149         struct drm_device *dev = crtc->dev;
3150         struct drm_i915_private *dev_priv = dev->dev_private;
3151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3152         int pipe = intel_crtc->pipe;
3153         u32 reg, temp;
3154
3155         assert_pch_transcoder_disabled(dev_priv, pipe);
3156
3157         if (IS_IVYBRIDGE(dev))
3158                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3159
3160         /* Write the TU size bits before fdi link training, so that error
3161          * detection works. */
3162         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3163                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3164
3165         /* For PCH output, training FDI link */
3166         dev_priv->display.fdi_link_train(crtc);
3167
3168         /* We need to program the right clock selection before writing the pixel
3169          * mutliplier into the DPLL. */
3170         if (HAS_PCH_CPT(dev)) {
3171                 u32 sel;
3172
3173                 temp = I915_READ(PCH_DPLL_SEL);
3174                 temp |= TRANS_DPLL_ENABLE(pipe);
3175                 sel = TRANS_DPLLB_SEL(pipe);
3176                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3177                         temp |= sel;
3178                 else
3179                         temp &= ~sel;
3180                 I915_WRITE(PCH_DPLL_SEL, temp);
3181         }
3182
3183         /* XXX: pch pll's can be enabled any time before we enable the PCH
3184          * transcoder, and we actually should do this to not upset any PCH
3185          * transcoder that already use the clock when we share it.
3186          *
3187          * Note that enable_shared_dpll tries to do the right thing, but
3188          * get_shared_dpll unconditionally resets the pll - we need that to have
3189          * the right LVDS enable sequence. */
3190         ironlake_enable_shared_dpll(intel_crtc);
3191
3192         /* set transcoder timing, panel must allow it */
3193         assert_panel_unlocked(dev_priv, pipe);
3194         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3195
3196         intel_fdi_normal_train(crtc);
3197
3198         /* For PCH DP, enable TRANS_DP_CTL */
3199         if (HAS_PCH_CPT(dev) &&
3200             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3201              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3202                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3203                 reg = TRANS_DP_CTL(pipe);
3204                 temp = I915_READ(reg);
3205                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3206                           TRANS_DP_SYNC_MASK |
3207                           TRANS_DP_BPC_MASK);
3208                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3209                          TRANS_DP_ENH_FRAMING);
3210                 temp |= bpc << 9; /* same format but at 11:9 */
3211
3212                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3213                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3214                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3215                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3216
3217                 switch (intel_trans_dp_port_sel(crtc)) {
3218                 case PCH_DP_B:
3219                         temp |= TRANS_DP_PORT_SEL_B;
3220                         break;
3221                 case PCH_DP_C:
3222                         temp |= TRANS_DP_PORT_SEL_C;
3223                         break;
3224                 case PCH_DP_D:
3225                         temp |= TRANS_DP_PORT_SEL_D;
3226                         break;
3227                 default:
3228                         BUG();
3229                 }
3230
3231                 I915_WRITE(reg, temp);
3232         }
3233
3234         ironlake_enable_pch_transcoder(dev_priv, pipe);
3235 }
3236
3237 static void lpt_pch_enable(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3243
3244         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3245
3246         lpt_program_iclkip(crtc);
3247
3248         /* Set transcoder timing. */
3249         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3250
3251         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3252 }
3253
3254 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3255 {
3256         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3257
3258         if (pll == NULL)
3259                 return;
3260
3261         if (pll->refcount == 0) {
3262                 WARN(1, "bad %s refcount\n", pll->name);
3263                 return;
3264         }
3265
3266         if (--pll->refcount == 0) {
3267                 WARN_ON(pll->on);
3268                 WARN_ON(pll->active);
3269         }
3270
3271         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3272 }
3273
3274 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3275 {
3276         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3277         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3278         enum intel_dpll_id i;
3279
3280         if (pll) {
3281                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3282                               crtc->base.base.id, pll->name);
3283                 intel_put_shared_dpll(crtc);
3284         }
3285
3286         if (HAS_PCH_IBX(dev_priv->dev)) {
3287                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3288                 i = (enum intel_dpll_id) crtc->pipe;
3289                 pll = &dev_priv->shared_dplls[i];
3290
3291                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3292                               crtc->base.base.id, pll->name);
3293
3294                 goto found;
3295         }
3296
3297         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3298                 pll = &dev_priv->shared_dplls[i];
3299
3300                 /* Only want to check enabled timings first */
3301                 if (pll->refcount == 0)
3302                         continue;
3303
3304                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3305                            sizeof(pll->hw_state)) == 0) {
3306                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3307                                       crtc->base.base.id,
3308                                       pll->name, pll->refcount, pll->active);
3309
3310                         goto found;
3311                 }
3312         }
3313
3314         /* Ok no matching timings, maybe there's a free one? */
3315         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3316                 pll = &dev_priv->shared_dplls[i];
3317                 if (pll->refcount == 0) {
3318                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3319                                       crtc->base.base.id, pll->name);
3320                         goto found;
3321                 }
3322         }
3323
3324         return NULL;
3325
3326 found:
3327         crtc->config.shared_dpll = i;
3328         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3329                          pipe_name(crtc->pipe));
3330
3331         if (pll->active == 0) {
3332                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3333                        sizeof(pll->hw_state));
3334
3335                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3336                 WARN_ON(pll->on);
3337                 assert_shared_dpll_disabled(dev_priv, pll);
3338
3339                 pll->mode_set(dev_priv, pll);
3340         }
3341         pll->refcount++;
3342
3343         return pll;
3344 }
3345
3346 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3347 {
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         int dslreg = PIPEDSL(pipe);
3350         u32 temp;
3351
3352         temp = I915_READ(dslreg);
3353         udelay(500);
3354         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3355                 if (wait_for(I915_READ(dslreg) != temp, 5))
3356                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3357         }
3358 }
3359
3360 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3361 {
3362         struct drm_device *dev = crtc->base.dev;
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         int pipe = crtc->pipe;
3365
3366         if (crtc->config.pch_pfit.enabled) {
3367                 /* Force use of hard-coded filter coefficients
3368                  * as some pre-programmed values are broken,
3369                  * e.g. x201.
3370                  */
3371                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3372                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3373                                                  PF_PIPE_SEL_IVB(pipe));
3374                 else
3375                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3376                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3377                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3378         }
3379 }
3380
3381 static void intel_enable_planes(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3385         struct intel_plane *intel_plane;
3386
3387         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3388                 if (intel_plane->pipe == pipe)
3389                         intel_plane_restore(&intel_plane->base);
3390 }
3391
3392 static void intel_disable_planes(struct drm_crtc *crtc)
3393 {
3394         struct drm_device *dev = crtc->dev;
3395         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3396         struct intel_plane *intel_plane;
3397
3398         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3399                 if (intel_plane->pipe == pipe)
3400                         intel_plane_disable(&intel_plane->base);
3401 }
3402
3403 void hsw_enable_ips(struct intel_crtc *crtc)
3404 {
3405         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3406
3407         if (!crtc->config.ips_enabled)
3408                 return;
3409
3410         /* We can only enable IPS after we enable a plane and wait for a vblank.
3411          * We guarantee that the plane is enabled by calling intel_enable_ips
3412          * only after intel_enable_plane. And intel_enable_plane already waits
3413          * for a vblank, so all we need to do here is to enable the IPS bit. */
3414         assert_plane_enabled(dev_priv, crtc->plane);
3415         if (IS_BROADWELL(crtc->base.dev)) {
3416                 mutex_lock(&dev_priv->rps.hw_lock);
3417                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3418                 mutex_unlock(&dev_priv->rps.hw_lock);
3419                 /* Quoting Art Runyan: "its not safe to expect any particular
3420                  * value in IPS_CTL bit 31 after enabling IPS through the
3421                  * mailbox." Therefore we need to defer waiting on the state
3422                  * change.
3423                  * TODO: need to fix this for state checker
3424                  */
3425         } else {
3426                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3427                 /* The bit only becomes 1 in the next vblank, so this wait here
3428                  * is essentially intel_wait_for_vblank. If we don't have this
3429                  * and don't wait for vblanks until the end of crtc_enable, then
3430                  * the HW state readout code will complain that the expected
3431                  * IPS_CTL value is not the one we read. */
3432                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3433                         DRM_ERROR("Timed out waiting for IPS enable\n");
3434         }
3435 }
3436
3437 void hsw_disable_ips(struct intel_crtc *crtc)
3438 {
3439         struct drm_device *dev = crtc->base.dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441
3442         if (!crtc->config.ips_enabled)
3443                 return;
3444
3445         assert_plane_enabled(dev_priv, crtc->plane);
3446         if (IS_BROADWELL(crtc->base.dev)) {
3447                 mutex_lock(&dev_priv->rps.hw_lock);
3448                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3449                 mutex_unlock(&dev_priv->rps.hw_lock);
3450         } else
3451                 I915_WRITE(IPS_CTL, 0);
3452         POSTING_READ(IPS_CTL);
3453
3454         /* We need to wait for a vblank before we can disable the plane. */
3455         intel_wait_for_vblank(dev, crtc->pipe);
3456 }
3457
3458 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3459 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3460 {
3461         struct drm_device *dev = crtc->dev;
3462         struct drm_i915_private *dev_priv = dev->dev_private;
3463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3464         enum pipe pipe = intel_crtc->pipe;
3465         int palreg = PALETTE(pipe);
3466         int i;
3467         bool reenable_ips = false;
3468
3469         /* The clocks have to be on to load the palette. */
3470         if (!crtc->enabled || !intel_crtc->active)
3471                 return;
3472
3473         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3474                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3475                         assert_dsi_pll_enabled(dev_priv);
3476                 else
3477                         assert_pll_enabled(dev_priv, pipe);
3478         }
3479
3480         /* use legacy palette for Ironlake */
3481         if (HAS_PCH_SPLIT(dev))
3482                 palreg = LGC_PALETTE(pipe);
3483
3484         /* Workaround : Do not read or write the pipe palette/gamma data while
3485          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3486          */
3487         if (intel_crtc->config.ips_enabled &&
3488             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3489              GAMMA_MODE_MODE_SPLIT)) {
3490                 hsw_disable_ips(intel_crtc);
3491                 reenable_ips = true;
3492         }
3493
3494         for (i = 0; i < 256; i++) {
3495                 I915_WRITE(palreg + 4 * i,
3496                            (intel_crtc->lut_r[i] << 16) |
3497                            (intel_crtc->lut_g[i] << 8) |
3498                            intel_crtc->lut_b[i]);
3499         }
3500
3501         if (reenable_ips)
3502                 hsw_enable_ips(intel_crtc);
3503 }
3504
3505 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3506 {
3507         struct drm_device *dev = crtc->dev;
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510         struct intel_encoder *encoder;
3511         int pipe = intel_crtc->pipe;
3512         int plane = intel_crtc->plane;
3513
3514         WARN_ON(!crtc->enabled);
3515
3516         if (intel_crtc->active)
3517                 return;
3518
3519         intel_crtc->active = true;
3520
3521         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3522         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3523
3524         for_each_encoder_on_crtc(dev, crtc, encoder)
3525                 if (encoder->pre_enable)
3526                         encoder->pre_enable(encoder);
3527
3528         if (intel_crtc->config.has_pch_encoder) {
3529                 /* Note: FDI PLL enabling _must_ be done before we enable the
3530                  * cpu pipes, hence this is separate from all the other fdi/pch
3531                  * enabling. */
3532                 ironlake_fdi_pll_enable(intel_crtc);
3533         } else {
3534                 assert_fdi_tx_disabled(dev_priv, pipe);
3535                 assert_fdi_rx_disabled(dev_priv, pipe);
3536         }
3537
3538         ironlake_pfit_enable(intel_crtc);
3539
3540         /*
3541          * On ILK+ LUT must be loaded before the pipe is running but with
3542          * clocks enabled
3543          */
3544         intel_crtc_load_lut(crtc);
3545
3546         intel_update_watermarks(crtc);
3547         intel_enable_pipe(dev_priv, pipe,
3548                           intel_crtc->config.has_pch_encoder, false);
3549         intel_enable_primary_plane(dev_priv, plane, pipe);
3550         intel_enable_planes(crtc);
3551         intel_crtc_update_cursor(crtc, true);
3552
3553         if (intel_crtc->config.has_pch_encoder)
3554                 ironlake_pch_enable(crtc);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559
3560         for_each_encoder_on_crtc(dev, crtc, encoder)
3561                 encoder->enable(encoder);
3562
3563         if (HAS_PCH_CPT(dev))
3564                 cpt_verify_modeset(dev, intel_crtc->pipe);
3565
3566         /*
3567          * There seems to be a race in PCH platform hw (at least on some
3568          * outputs) where an enabled pipe still completes any pageflip right
3569          * away (as if the pipe is off) instead of waiting for vblank. As soon
3570          * as the first vblank happend, everything works as expected. Hence just
3571          * wait for one vblank before returning to avoid strange things
3572          * happening.
3573          */
3574         intel_wait_for_vblank(dev, intel_crtc->pipe);
3575 }
3576
3577 /* IPS only exists on ULT machines and is tied to pipe A. */
3578 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3579 {
3580         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3581 }
3582
3583 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3584 {
3585         struct drm_device *dev = crtc->dev;
3586         struct drm_i915_private *dev_priv = dev->dev_private;
3587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588         int pipe = intel_crtc->pipe;
3589         int plane = intel_crtc->plane;
3590
3591         intel_enable_primary_plane(dev_priv, plane, pipe);
3592         intel_enable_planes(crtc);
3593         intel_crtc_update_cursor(crtc, true);
3594
3595         hsw_enable_ips(intel_crtc);
3596
3597         mutex_lock(&dev->struct_mutex);
3598         intel_update_fbc(dev);
3599         mutex_unlock(&dev->struct_mutex);
3600 }
3601
3602 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3603 {
3604         struct drm_device *dev = crtc->dev;
3605         struct drm_i915_private *dev_priv = dev->dev_private;
3606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607         int pipe = intel_crtc->pipe;
3608         int plane = intel_crtc->plane;
3609
3610         intel_crtc_wait_for_pending_flips(crtc);
3611         drm_vblank_off(dev, pipe);
3612
3613         /* FBC must be disabled before disabling the plane on HSW. */
3614         if (dev_priv->fbc.plane == plane)
3615                 intel_disable_fbc(dev);
3616
3617         hsw_disable_ips(intel_crtc);
3618
3619         intel_crtc_update_cursor(crtc, false);
3620         intel_disable_planes(crtc);
3621         intel_disable_primary_plane(dev_priv, plane, pipe);
3622 }
3623
3624 /*
3625  * This implements the workaround described in the "notes" section of the mode
3626  * set sequence documentation. When going from no pipes or single pipe to
3627  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3628  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3629  */
3630 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3631 {
3632         struct drm_device *dev = crtc->base.dev;
3633         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3634
3635         /* We want to get the other_active_crtc only if there's only 1 other
3636          * active crtc. */
3637         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3638                 if (!crtc_it->active || crtc_it == crtc)
3639                         continue;
3640
3641                 if (other_active_crtc)
3642                         return;
3643
3644                 other_active_crtc = crtc_it;
3645         }
3646         if (!other_active_crtc)
3647                 return;
3648
3649         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3650         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3651 }
3652
3653 static void haswell_crtc_enable(struct drm_crtc *crtc)
3654 {
3655         struct drm_device *dev = crtc->dev;
3656         struct drm_i915_private *dev_priv = dev->dev_private;
3657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658         struct intel_encoder *encoder;
3659         int pipe = intel_crtc->pipe;
3660
3661         WARN_ON(!crtc->enabled);
3662
3663         if (intel_crtc->active)
3664                 return;
3665
3666         intel_crtc->active = true;
3667
3668         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3669         if (intel_crtc->config.has_pch_encoder)
3670                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3671
3672         if (intel_crtc->config.has_pch_encoder)
3673                 dev_priv->display.fdi_link_train(crtc);
3674
3675         for_each_encoder_on_crtc(dev, crtc, encoder)
3676                 if (encoder->pre_enable)
3677                         encoder->pre_enable(encoder);
3678
3679         intel_ddi_enable_pipe_clock(intel_crtc);
3680
3681         ironlake_pfit_enable(intel_crtc);
3682
3683         /*
3684          * On ILK+ LUT must be loaded before the pipe is running but with
3685          * clocks enabled
3686          */
3687         intel_crtc_load_lut(crtc);
3688
3689         intel_ddi_set_pipe_settings(crtc);
3690         intel_ddi_enable_transcoder_func(crtc);
3691
3692         intel_update_watermarks(crtc);
3693         intel_enable_pipe(dev_priv, pipe,
3694                           intel_crtc->config.has_pch_encoder, false);
3695
3696         if (intel_crtc->config.has_pch_encoder)
3697                 lpt_pch_enable(crtc);
3698
3699         for_each_encoder_on_crtc(dev, crtc, encoder) {
3700                 encoder->enable(encoder);
3701                 intel_opregion_notify_encoder(encoder, true);
3702         }
3703
3704         /* If we change the relative order between pipe/planes enabling, we need
3705          * to change the workaround. */
3706         haswell_mode_set_planes_workaround(intel_crtc);
3707         haswell_crtc_enable_planes(crtc);
3708
3709         /*
3710          * There seems to be a race in PCH platform hw (at least on some
3711          * outputs) where an enabled pipe still completes any pageflip right
3712          * away (as if the pipe is off) instead of waiting for vblank. As soon
3713          * as the first vblank happend, everything works as expected. Hence just
3714          * wait for one vblank before returning to avoid strange things
3715          * happening.
3716          */
3717         intel_wait_for_vblank(dev, intel_crtc->pipe);
3718 }
3719
3720 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3721 {
3722         struct drm_device *dev = crtc->base.dev;
3723         struct drm_i915_private *dev_priv = dev->dev_private;
3724         int pipe = crtc->pipe;
3725
3726         /* To avoid upsetting the power well on haswell only disable the pfit if
3727          * it's in use. The hw state code will make sure we get this right. */
3728         if (crtc->config.pch_pfit.enabled) {
3729                 I915_WRITE(PF_CTL(pipe), 0);
3730                 I915_WRITE(PF_WIN_POS(pipe), 0);
3731                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3732         }
3733 }
3734
3735 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3736 {
3737         struct drm_device *dev = crtc->dev;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740         struct intel_encoder *encoder;
3741         int pipe = intel_crtc->pipe;
3742         int plane = intel_crtc->plane;
3743         u32 reg, temp;
3744
3745
3746         if (!intel_crtc->active)
3747                 return;
3748
3749         for_each_encoder_on_crtc(dev, crtc, encoder)
3750                 encoder->disable(encoder);
3751
3752         intel_crtc_wait_for_pending_flips(crtc);
3753         drm_vblank_off(dev, pipe);
3754
3755         if (dev_priv->fbc.plane == plane)
3756                 intel_disable_fbc(dev);
3757
3758         intel_crtc_update_cursor(crtc, false);
3759         intel_disable_planes(crtc);
3760         intel_disable_primary_plane(dev_priv, plane, pipe);
3761
3762         if (intel_crtc->config.has_pch_encoder)
3763                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3764
3765         intel_disable_pipe(dev_priv, pipe);
3766
3767         ironlake_pfit_disable(intel_crtc);
3768
3769         for_each_encoder_on_crtc(dev, crtc, encoder)
3770                 if (encoder->post_disable)
3771                         encoder->post_disable(encoder);
3772
3773         if (intel_crtc->config.has_pch_encoder) {
3774                 ironlake_fdi_disable(crtc);
3775
3776                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3777                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3778
3779                 if (HAS_PCH_CPT(dev)) {
3780                         /* disable TRANS_DP_CTL */
3781                         reg = TRANS_DP_CTL(pipe);
3782                         temp = I915_READ(reg);
3783                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3784                                   TRANS_DP_PORT_SEL_MASK);
3785                         temp |= TRANS_DP_PORT_SEL_NONE;
3786                         I915_WRITE(reg, temp);
3787
3788                         /* disable DPLL_SEL */
3789                         temp = I915_READ(PCH_DPLL_SEL);
3790                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3791                         I915_WRITE(PCH_DPLL_SEL, temp);
3792                 }
3793
3794                 /* disable PCH DPLL */
3795                 intel_disable_shared_dpll(intel_crtc);
3796
3797                 ironlake_fdi_pll_disable(intel_crtc);
3798         }
3799
3800         intel_crtc->active = false;
3801         intel_update_watermarks(crtc);
3802
3803         mutex_lock(&dev->struct_mutex);
3804         intel_update_fbc(dev);
3805         mutex_unlock(&dev->struct_mutex);
3806 }
3807
3808 static void haswell_crtc_disable(struct drm_crtc *crtc)
3809 {
3810         struct drm_device *dev = crtc->dev;
3811         struct drm_i915_private *dev_priv = dev->dev_private;
3812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813         struct intel_encoder *encoder;
3814         int pipe = intel_crtc->pipe;
3815         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3816
3817         if (!intel_crtc->active)
3818                 return;
3819
3820         haswell_crtc_disable_planes(crtc);
3821
3822         for_each_encoder_on_crtc(dev, crtc, encoder) {
3823                 intel_opregion_notify_encoder(encoder, false);
3824                 encoder->disable(encoder);
3825         }
3826
3827         if (intel_crtc->config.has_pch_encoder)
3828                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3829         intel_disable_pipe(dev_priv, pipe);
3830
3831         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3832
3833         ironlake_pfit_disable(intel_crtc);
3834
3835         intel_ddi_disable_pipe_clock(intel_crtc);
3836
3837         for_each_encoder_on_crtc(dev, crtc, encoder)
3838                 if (encoder->post_disable)
3839                         encoder->post_disable(encoder);
3840
3841         if (intel_crtc->config.has_pch_encoder) {
3842                 lpt_disable_pch_transcoder(dev_priv);
3843                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3844                 intel_ddi_fdi_disable(crtc);
3845         }
3846
3847         intel_crtc->active = false;
3848         intel_update_watermarks(crtc);
3849
3850         mutex_lock(&dev->struct_mutex);
3851         intel_update_fbc(dev);
3852         mutex_unlock(&dev->struct_mutex);
3853 }
3854
3855 static void ironlake_crtc_off(struct drm_crtc *crtc)
3856 {
3857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3858         intel_put_shared_dpll(intel_crtc);
3859 }
3860
3861 static void haswell_crtc_off(struct drm_crtc *crtc)
3862 {
3863         intel_ddi_put_crtc_pll(crtc);
3864 }
3865
3866 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3867 {
3868         if (!enable && intel_crtc->overlay) {
3869                 struct drm_device *dev = intel_crtc->base.dev;
3870                 struct drm_i915_private *dev_priv = dev->dev_private;
3871
3872                 mutex_lock(&dev->struct_mutex);
3873                 dev_priv->mm.interruptible = false;
3874                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3875                 dev_priv->mm.interruptible = true;
3876                 mutex_unlock(&dev->struct_mutex);
3877         }
3878
3879         /* Let userspace switch the overlay on again. In most cases userspace
3880          * has to recompute where to put it anyway.
3881          */
3882 }
3883
3884 /**
3885  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3886  * cursor plane briefly if not already running after enabling the display
3887  * plane.
3888  * This workaround avoids occasional blank screens when self refresh is
3889  * enabled.
3890  */
3891 static void
3892 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3893 {
3894         u32 cntl = I915_READ(CURCNTR(pipe));
3895
3896         if ((cntl & CURSOR_MODE) == 0) {
3897                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3898
3899                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3900                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3901                 intel_wait_for_vblank(dev_priv->dev, pipe);
3902                 I915_WRITE(CURCNTR(pipe), cntl);
3903                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3904                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3905         }
3906 }
3907
3908 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3909 {
3910         struct drm_device *dev = crtc->base.dev;
3911         struct drm_i915_private *dev_priv = dev->dev_private;
3912         struct intel_crtc_config *pipe_config = &crtc->config;
3913
3914         if (!crtc->config.gmch_pfit.control)
3915                 return;
3916
3917         /*
3918          * The panel fitter should only be adjusted whilst the pipe is disabled,
3919          * according to register description and PRM.
3920          */
3921         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3922         assert_pipe_disabled(dev_priv, crtc->pipe);
3923
3924         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3925         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3926
3927         /* Border color in case we don't scale up to the full screen. Black by
3928          * default, change to something else for debugging. */
3929         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3930 }
3931
3932 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3933 {
3934         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3935
3936         /* Obtain SKU information */
3937         mutex_lock(&dev_priv->dpio_lock);
3938         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3939                 CCK_FUSE_HPLL_FREQ_MASK;
3940         mutex_unlock(&dev_priv->dpio_lock);
3941
3942         return vco_freq[hpll_freq];
3943 }
3944
3945 /* Adjust CDclk dividers to allow high res or save power if possible */
3946 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3947 {
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         u32 val, cmd;
3950
3951         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3952                 cmd = 2;
3953         else if (cdclk == 266)
3954                 cmd = 1;
3955         else
3956                 cmd = 0;
3957
3958         mutex_lock(&dev_priv->rps.hw_lock);
3959         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3960         val &= ~DSPFREQGUAR_MASK;
3961         val |= (cmd << DSPFREQGUAR_SHIFT);
3962         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3963         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3964                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3965                      50)) {
3966                 DRM_ERROR("timed out waiting for CDclk change\n");
3967         }
3968         mutex_unlock(&dev_priv->rps.hw_lock);
3969
3970         if (cdclk == 400) {
3971                 u32 divider, vco;
3972
3973                 vco = valleyview_get_vco(dev_priv);
3974                 divider = ((vco << 1) / cdclk) - 1;
3975
3976                 mutex_lock(&dev_priv->dpio_lock);
3977                 /* adjust cdclk divider */
3978                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3979                 val &= ~0xf;
3980                 val |= divider;
3981                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3982                 mutex_unlock(&dev_priv->dpio_lock);
3983         }
3984
3985         mutex_lock(&dev_priv->dpio_lock);
3986         /* adjust self-refresh exit latency value */
3987         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
3988         val &= ~0x7f;
3989
3990         /*
3991          * For high bandwidth configs, we set a higher latency in the bunit
3992          * so that the core display fetch happens in time to avoid underruns.
3993          */
3994         if (cdclk == 400)
3995                 val |= 4500 / 250; /* 4.5 usec */
3996         else
3997                 val |= 3000 / 250; /* 3.0 usec */
3998         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
3999         mutex_unlock(&dev_priv->dpio_lock);
4000
4001         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4002         intel_i2c_reset(dev);
4003 }
4004
4005 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4006 {
4007         int cur_cdclk, vco;
4008         int divider;
4009
4010         vco = valleyview_get_vco(dev_priv);
4011
4012         mutex_lock(&dev_priv->dpio_lock);
4013         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4014         mutex_unlock(&dev_priv->dpio_lock);
4015
4016         divider &= 0xf;
4017
4018         cur_cdclk = (vco << 1) / (divider + 1);
4019
4020         return cur_cdclk;
4021 }
4022
4023 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4024                                  int max_pixclk)
4025 {
4026         int cur_cdclk;
4027
4028         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4029
4030         /*
4031          * Really only a few cases to deal with, as only 4 CDclks are supported:
4032          *   200MHz
4033          *   267MHz
4034          *   320MHz
4035          *   400MHz
4036          * So we check to see whether we're above 90% of the lower bin and
4037          * adjust if needed.
4038          */
4039         if (max_pixclk > 288000) {
4040                 return 400;
4041         } else if (max_pixclk > 240000) {
4042                 return 320;
4043         } else
4044                 return 266;
4045         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4046 }
4047
4048 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4049                                  unsigned modeset_pipes,
4050                                  struct intel_crtc_config *pipe_config)
4051 {
4052         struct drm_device *dev = dev_priv->dev;
4053         struct intel_crtc *intel_crtc;
4054         int max_pixclk = 0;
4055
4056         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4057                             base.head) {
4058                 if (modeset_pipes & (1 << intel_crtc->pipe))
4059                         max_pixclk = max(max_pixclk,
4060                                          pipe_config->adjusted_mode.crtc_clock);
4061                 else if (intel_crtc->base.enabled)
4062                         max_pixclk = max(max_pixclk,
4063                                          intel_crtc->config.adjusted_mode.crtc_clock);
4064         }
4065
4066         return max_pixclk;
4067 }
4068
4069 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4070                                             unsigned *prepare_pipes,
4071                                             unsigned modeset_pipes,
4072                                             struct intel_crtc_config *pipe_config)
4073 {
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         struct intel_crtc *intel_crtc;
4076         int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4077                                                pipe_config);
4078         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4079
4080         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4081                 return;
4082
4083         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4084                             base.head)
4085                 if (intel_crtc->base.enabled)
4086                         *prepare_pipes |= (1 << intel_crtc->pipe);
4087 }
4088
4089 static void valleyview_modeset_global_resources(struct drm_device *dev)
4090 {
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092         int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4093         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4094         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4095
4096         if (req_cdclk != cur_cdclk)
4097                 valleyview_set_cdclk(dev, req_cdclk);
4098 }
4099
4100 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105         struct intel_encoder *encoder;
4106         int pipe = intel_crtc->pipe;
4107         int plane = intel_crtc->plane;
4108         bool is_dsi;
4109
4110         WARN_ON(!crtc->enabled);
4111
4112         if (intel_crtc->active)
4113                 return;
4114
4115         intel_crtc->active = true;
4116
4117         for_each_encoder_on_crtc(dev, crtc, encoder)
4118                 if (encoder->pre_pll_enable)
4119                         encoder->pre_pll_enable(encoder);
4120
4121         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4122
4123         if (!is_dsi)
4124                 vlv_enable_pll(intel_crtc);
4125
4126         for_each_encoder_on_crtc(dev, crtc, encoder)
4127                 if (encoder->pre_enable)
4128                         encoder->pre_enable(encoder);
4129
4130         i9xx_pfit_enable(intel_crtc);
4131
4132         intel_crtc_load_lut(crtc);
4133
4134         intel_update_watermarks(crtc);
4135         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4136         intel_enable_primary_plane(dev_priv, plane, pipe);
4137         intel_enable_planes(crtc);
4138         intel_crtc_update_cursor(crtc, true);
4139
4140         intel_update_fbc(dev);
4141
4142         for_each_encoder_on_crtc(dev, crtc, encoder)
4143                 encoder->enable(encoder);
4144 }
4145
4146 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4147 {
4148         struct drm_device *dev = crtc->dev;
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151         struct intel_encoder *encoder;
4152         int pipe = intel_crtc->pipe;
4153         int plane = intel_crtc->plane;
4154
4155         WARN_ON(!crtc->enabled);
4156
4157         if (intel_crtc->active)
4158                 return;
4159
4160         intel_crtc->active = true;
4161
4162         for_each_encoder_on_crtc(dev, crtc, encoder)
4163                 if (encoder->pre_enable)
4164                         encoder->pre_enable(encoder);
4165
4166         i9xx_enable_pll(intel_crtc);
4167
4168         i9xx_pfit_enable(intel_crtc);
4169
4170         intel_crtc_load_lut(crtc);
4171
4172         intel_update_watermarks(crtc);
4173         intel_enable_pipe(dev_priv, pipe, false, false);
4174         intel_enable_primary_plane(dev_priv, plane, pipe);
4175         intel_enable_planes(crtc);
4176         /* The fixup needs to happen before cursor is enabled */
4177         if (IS_G4X(dev))
4178                 g4x_fixup_plane(dev_priv, pipe);
4179         intel_crtc_update_cursor(crtc, true);
4180
4181         /* Give the overlay scaler a chance to enable if it's on this pipe */
4182         intel_crtc_dpms_overlay(intel_crtc, true);
4183
4184         intel_update_fbc(dev);
4185
4186         for_each_encoder_on_crtc(dev, crtc, encoder)
4187                 encoder->enable(encoder);
4188 }
4189
4190 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4191 {
4192         struct drm_device *dev = crtc->base.dev;
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194
4195         if (!crtc->config.gmch_pfit.control)
4196                 return;
4197
4198         assert_pipe_disabled(dev_priv, crtc->pipe);
4199
4200         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4201                          I915_READ(PFIT_CONTROL));
4202         I915_WRITE(PFIT_CONTROL, 0);
4203 }
4204
4205 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4206 {
4207         struct drm_device *dev = crtc->dev;
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4210         struct intel_encoder *encoder;
4211         int pipe = intel_crtc->pipe;
4212         int plane = intel_crtc->plane;
4213
4214         if (!intel_crtc->active)
4215                 return;
4216
4217         for_each_encoder_on_crtc(dev, crtc, encoder)
4218                 encoder->disable(encoder);
4219
4220         /* Give the overlay scaler a chance to disable if it's on this pipe */
4221         intel_crtc_wait_for_pending_flips(crtc);
4222         drm_vblank_off(dev, pipe);
4223
4224         if (dev_priv->fbc.plane == plane)
4225                 intel_disable_fbc(dev);
4226
4227         intel_crtc_dpms_overlay(intel_crtc, false);
4228         intel_crtc_update_cursor(crtc, false);
4229         intel_disable_planes(crtc);
4230         intel_disable_primary_plane(dev_priv, plane, pipe);
4231
4232         intel_disable_pipe(dev_priv, pipe);
4233
4234         i9xx_pfit_disable(intel_crtc);
4235
4236         for_each_encoder_on_crtc(dev, crtc, encoder)
4237                 if (encoder->post_disable)
4238                         encoder->post_disable(encoder);
4239
4240         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4241                 vlv_disable_pll(dev_priv, pipe);
4242         else if (!IS_VALLEYVIEW(dev))
4243                 i9xx_disable_pll(dev_priv, pipe);
4244
4245         intel_crtc->active = false;
4246         intel_update_watermarks(crtc);
4247
4248         intel_update_fbc(dev);
4249 }
4250
4251 static void i9xx_crtc_off(struct drm_crtc *crtc)
4252 {
4253 }
4254
4255 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4256                                     bool enabled)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct drm_i915_master_private *master_priv;
4260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4261         int pipe = intel_crtc->pipe;
4262
4263         if (!dev->primary->master)
4264                 return;
4265
4266         master_priv = dev->primary->master->driver_priv;
4267         if (!master_priv->sarea_priv)
4268                 return;
4269
4270         switch (pipe) {
4271         case 0:
4272                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4273                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4274                 break;
4275         case 1:
4276                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4277                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4278                 break;
4279         default:
4280                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4281                 break;
4282         }
4283 }
4284
4285 /**
4286  * Sets the power management mode of the pipe and plane.
4287  */
4288 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4289 {
4290         struct drm_device *dev = crtc->dev;
4291         struct drm_i915_private *dev_priv = dev->dev_private;
4292         struct intel_encoder *intel_encoder;
4293         bool enable = false;
4294
4295         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4296                 enable |= intel_encoder->connectors_active;
4297
4298         if (enable)
4299                 dev_priv->display.crtc_enable(crtc);
4300         else
4301                 dev_priv->display.crtc_disable(crtc);
4302
4303         intel_crtc_update_sarea(crtc, enable);
4304 }
4305
4306 static void intel_crtc_disable(struct drm_crtc *crtc)
4307 {
4308         struct drm_device *dev = crtc->dev;
4309         struct drm_connector *connector;
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4312
4313         /* crtc should still be enabled when we disable it. */
4314         WARN_ON(!crtc->enabled);
4315
4316         dev_priv->display.crtc_disable(crtc);
4317         intel_crtc->eld_vld = false;
4318         intel_crtc_update_sarea(crtc, false);
4319         dev_priv->display.off(crtc);
4320
4321         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4322         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4323         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4324
4325         if (crtc->fb) {
4326                 mutex_lock(&dev->struct_mutex);
4327                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4328                 mutex_unlock(&dev->struct_mutex);
4329                 crtc->fb = NULL;
4330         }
4331
4332         /* Update computed state. */
4333         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4334                 if (!connector->encoder || !connector->encoder->crtc)
4335                         continue;
4336
4337                 if (connector->encoder->crtc != crtc)
4338                         continue;
4339
4340                 connector->dpms = DRM_MODE_DPMS_OFF;
4341                 to_intel_encoder(connector->encoder)->connectors_active = false;
4342         }
4343 }
4344
4345 void intel_encoder_destroy(struct drm_encoder *encoder)
4346 {
4347         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4348
4349         drm_encoder_cleanup(encoder);
4350         kfree(intel_encoder);
4351 }
4352
4353 /* Simple dpms helper for encoders with just one connector, no cloning and only
4354  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4355  * state of the entire output pipe. */
4356 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4357 {
4358         if (mode == DRM_MODE_DPMS_ON) {
4359                 encoder->connectors_active = true;
4360
4361                 intel_crtc_update_dpms(encoder->base.crtc);
4362         } else {
4363                 encoder->connectors_active = false;
4364
4365                 intel_crtc_update_dpms(encoder->base.crtc);
4366         }
4367 }
4368
4369 /* Cross check the actual hw state with our own modeset state tracking (and it's
4370  * internal consistency). */
4371 static void intel_connector_check_state(struct intel_connector *connector)
4372 {
4373         if (connector->get_hw_state(connector)) {
4374                 struct intel_encoder *encoder = connector->encoder;
4375                 struct drm_crtc *crtc;
4376                 bool encoder_enabled;
4377                 enum pipe pipe;
4378
4379                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4380                               connector->base.base.id,
4381                               drm_get_connector_name(&connector->base));
4382
4383                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4384                      "wrong connector dpms state\n");
4385                 WARN(connector->base.encoder != &encoder->base,
4386                      "active connector not linked to encoder\n");
4387                 WARN(!encoder->connectors_active,
4388                      "encoder->connectors_active not set\n");
4389
4390                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4391                 WARN(!encoder_enabled, "encoder not enabled\n");
4392                 if (WARN_ON(!encoder->base.crtc))
4393                         return;
4394
4395                 crtc = encoder->base.crtc;
4396
4397                 WARN(!crtc->enabled, "crtc not enabled\n");
4398                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4399                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4400                      "encoder active on the wrong pipe\n");
4401         }
4402 }
4403
4404 /* Even simpler default implementation, if there's really no special case to
4405  * consider. */
4406 void intel_connector_dpms(struct drm_connector *connector, int mode)
4407 {
4408         /* All the simple cases only support two dpms states. */
4409         if (mode != DRM_MODE_DPMS_ON)
4410                 mode = DRM_MODE_DPMS_OFF;
4411
4412         if (mode == connector->dpms)
4413                 return;
4414
4415         connector->dpms = mode;
4416
4417         /* Only need to change hw state when actually enabled */
4418         if (connector->encoder)
4419                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4420
4421         intel_modeset_check_state(connector->dev);
4422 }
4423
4424 /* Simple connector->get_hw_state implementation for encoders that support only
4425  * one connector and no cloning and hence the encoder state determines the state
4426  * of the connector. */
4427 bool intel_connector_get_hw_state(struct intel_connector *connector)
4428 {
4429         enum pipe pipe = 0;
4430         struct intel_encoder *encoder = connector->encoder;
4431
4432         return encoder->get_hw_state(encoder, &pipe);
4433 }
4434
4435 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4436                                      struct intel_crtc_config *pipe_config)
4437 {
4438         struct drm_i915_private *dev_priv = dev->dev_private;
4439         struct intel_crtc *pipe_B_crtc =
4440                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4441
4442         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4443                       pipe_name(pipe), pipe_config->fdi_lanes);
4444         if (pipe_config->fdi_lanes > 4) {
4445                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4446                               pipe_name(pipe), pipe_config->fdi_lanes);
4447                 return false;
4448         }
4449
4450         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4451                 if (pipe_config->fdi_lanes > 2) {
4452                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4453                                       pipe_config->fdi_lanes);
4454                         return false;
4455                 } else {
4456                         return true;
4457                 }
4458         }
4459
4460         if (INTEL_INFO(dev)->num_pipes == 2)
4461                 return true;
4462
4463         /* Ivybridge 3 pipe is really complicated */
4464         switch (pipe) {
4465         case PIPE_A:
4466                 return true;
4467         case PIPE_B:
4468                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4469                     pipe_config->fdi_lanes > 2) {
4470                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4471                                       pipe_name(pipe), pipe_config->fdi_lanes);
4472                         return false;
4473                 }
4474                 return true;
4475         case PIPE_C:
4476                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4477                     pipe_B_crtc->config.fdi_lanes <= 2) {
4478                         if (pipe_config->fdi_lanes > 2) {
4479                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4480                                               pipe_name(pipe), pipe_config->fdi_lanes);
4481                                 return false;
4482                         }
4483                 } else {
4484                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4485                         return false;
4486                 }
4487                 return true;
4488         default:
4489                 BUG();
4490         }
4491 }
4492
4493 #define RETRY 1
4494 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4495                                        struct intel_crtc_config *pipe_config)
4496 {
4497         struct drm_device *dev = intel_crtc->base.dev;
4498         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4499         int lane, link_bw, fdi_dotclock;
4500         bool setup_ok, needs_recompute = false;
4501
4502 retry:
4503         /* FDI is a binary signal running at ~2.7GHz, encoding
4504          * each output octet as 10 bits. The actual frequency
4505          * is stored as a divider into a 100MHz clock, and the
4506          * mode pixel clock is stored in units of 1KHz.
4507          * Hence the bw of each lane in terms of the mode signal
4508          * is:
4509          */
4510         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4511
4512         fdi_dotclock = adjusted_mode->crtc_clock;
4513
4514         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4515                                            pipe_config->pipe_bpp);
4516
4517         pipe_config->fdi_lanes = lane;
4518
4519         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4520                                link_bw, &pipe_config->fdi_m_n);
4521
4522         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4523                                             intel_crtc->pipe, pipe_config);
4524         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4525                 pipe_config->pipe_bpp -= 2*3;
4526                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4527                               pipe_config->pipe_bpp);
4528                 needs_recompute = true;
4529                 pipe_config->bw_constrained = true;
4530
4531                 goto retry;
4532         }
4533
4534         if (needs_recompute)
4535                 return RETRY;
4536
4537         return setup_ok ? 0 : -EINVAL;
4538 }
4539
4540 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4541                                    struct intel_crtc_config *pipe_config)
4542 {
4543         pipe_config->ips_enabled = i915_enable_ips &&
4544                                    hsw_crtc_supports_ips(crtc) &&
4545                                    pipe_config->pipe_bpp <= 24;
4546 }
4547
4548 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4549                                      struct intel_crtc_config *pipe_config)
4550 {
4551         struct drm_device *dev = crtc->base.dev;
4552         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4553
4554         /* FIXME should check pixel clock limits on all platforms */
4555         if (INTEL_INFO(dev)->gen < 4) {
4556                 struct drm_i915_private *dev_priv = dev->dev_private;
4557                 int clock_limit =
4558                         dev_priv->display.get_display_clock_speed(dev);
4559
4560                 /*
4561                  * Enable pixel doubling when the dot clock
4562                  * is > 90% of the (display) core speed.
4563                  *
4564                  * GDG double wide on either pipe,
4565                  * otherwise pipe A only.
4566                  */
4567                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4568                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4569                         clock_limit *= 2;
4570                         pipe_config->double_wide = true;
4571                 }
4572
4573                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4574                         return -EINVAL;
4575         }
4576
4577         /*
4578          * Pipe horizontal size must be even in:
4579          * - DVO ganged mode
4580          * - LVDS dual channel mode
4581          * - Double wide pipe
4582          */
4583         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4584              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4585                 pipe_config->pipe_src_w &= ~1;
4586
4587         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4588          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4589          */
4590         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4591                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4592                 return -EINVAL;
4593
4594         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4595                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4596         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4597                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4598                  * for lvds. */
4599                 pipe_config->pipe_bpp = 8*3;
4600         }
4601
4602         if (HAS_IPS(dev))
4603                 hsw_compute_ips_config(crtc, pipe_config);
4604
4605         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4606          * clock survives for now. */
4607         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4608                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4609
4610         if (pipe_config->has_pch_encoder)
4611                 return ironlake_fdi_compute_config(crtc, pipe_config);
4612
4613         return 0;
4614 }
4615
4616 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4617 {
4618         return 400000; /* FIXME */
4619 }
4620
4621 static int i945_get_display_clock_speed(struct drm_device *dev)
4622 {
4623         return 400000;
4624 }
4625
4626 static int i915_get_display_clock_speed(struct drm_device *dev)
4627 {
4628         return 333000;
4629 }
4630
4631 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4632 {
4633         return 200000;
4634 }
4635
4636 static int pnv_get_display_clock_speed(struct drm_device *dev)
4637 {
4638         u16 gcfgc = 0;
4639
4640         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4641
4642         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4643         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4644                 return 267000;
4645         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4646                 return 333000;
4647         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4648                 return 444000;
4649         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4650                 return 200000;
4651         default:
4652                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4653         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4654                 return 133000;
4655         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4656                 return 167000;
4657         }
4658 }
4659
4660 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4661 {
4662         u16 gcfgc = 0;
4663
4664         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4665
4666         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4667                 return 133000;
4668         else {
4669                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4670                 case GC_DISPLAY_CLOCK_333_MHZ:
4671                         return 333000;
4672                 default:
4673                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4674                         return 190000;
4675                 }
4676         }
4677 }
4678
4679 static int i865_get_display_clock_speed(struct drm_device *dev)
4680 {
4681         return 266000;
4682 }
4683
4684 static int i855_get_display_clock_speed(struct drm_device *dev)
4685 {
4686         u16 hpllcc = 0;
4687         /* Assume that the hardware is in the high speed state.  This
4688          * should be the default.
4689          */
4690         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4691         case GC_CLOCK_133_200:
4692         case GC_CLOCK_100_200:
4693                 return 200000;
4694         case GC_CLOCK_166_250:
4695                 return 250000;
4696         case GC_CLOCK_100_133:
4697                 return 133000;
4698         }
4699
4700         /* Shouldn't happen */
4701         return 0;
4702 }
4703
4704 static int i830_get_display_clock_speed(struct drm_device *dev)
4705 {
4706         return 133000;
4707 }
4708
4709 static void
4710 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4711 {
4712         while (*num > DATA_LINK_M_N_MASK ||
4713                *den > DATA_LINK_M_N_MASK) {
4714                 *num >>= 1;
4715                 *den >>= 1;
4716         }
4717 }
4718
4719 static void compute_m_n(unsigned int m, unsigned int n,
4720                         uint32_t *ret_m, uint32_t *ret_n)
4721 {
4722         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4723         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4724         intel_reduce_m_n_ratio(ret_m, ret_n);
4725 }
4726
4727 void
4728 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4729                        int pixel_clock, int link_clock,
4730                        struct intel_link_m_n *m_n)
4731 {
4732         m_n->tu = 64;
4733
4734         compute_m_n(bits_per_pixel * pixel_clock,
4735                     link_clock * nlanes * 8,
4736                     &m_n->gmch_m, &m_n->gmch_n);
4737
4738         compute_m_n(pixel_clock, link_clock,
4739                     &m_n->link_m, &m_n->link_n);
4740 }
4741
4742 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4743 {
4744         if (i915_panel_use_ssc >= 0)
4745                 return i915_panel_use_ssc != 0;
4746         return dev_priv->vbt.lvds_use_ssc
4747                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4748 }
4749
4750 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4751 {
4752         struct drm_device *dev = crtc->dev;
4753         struct drm_i915_private *dev_priv = dev->dev_private;
4754         int refclk;
4755
4756         if (IS_VALLEYVIEW(dev)) {
4757                 refclk = 100000;
4758         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4759             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4760                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4761                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4762                               refclk / 1000);
4763         } else if (!IS_GEN2(dev)) {
4764                 refclk = 96000;
4765         } else {
4766                 refclk = 48000;
4767         }
4768
4769         return refclk;
4770 }
4771
4772 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4773 {
4774         return (1 << dpll->n) << 16 | dpll->m2;
4775 }
4776
4777 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4778 {
4779         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4780 }
4781
4782 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4783                                      intel_clock_t *reduced_clock)
4784 {
4785         struct drm_device *dev = crtc->base.dev;
4786         struct drm_i915_private *dev_priv = dev->dev_private;
4787         int pipe = crtc->pipe;
4788         u32 fp, fp2 = 0;
4789
4790         if (IS_PINEVIEW(dev)) {
4791                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4792                 if (reduced_clock)
4793                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4794         } else {
4795                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4796                 if (reduced_clock)
4797                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4798         }
4799
4800         I915_WRITE(FP0(pipe), fp);
4801         crtc->config.dpll_hw_state.fp0 = fp;
4802
4803         crtc->lowfreq_avail = false;
4804         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4805             reduced_clock && i915_powersave) {
4806                 I915_WRITE(FP1(pipe), fp2);
4807                 crtc->config.dpll_hw_state.fp1 = fp2;
4808                 crtc->lowfreq_avail = true;
4809         } else {
4810                 I915_WRITE(FP1(pipe), fp);
4811                 crtc->config.dpll_hw_state.fp1 = fp;
4812         }
4813 }
4814
4815 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4816                 pipe)
4817 {
4818         u32 reg_val;
4819
4820         /*
4821          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4822          * and set it to a reasonable value instead.
4823          */
4824         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4825         reg_val &= 0xffffff00;
4826         reg_val |= 0x00000030;
4827         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4828
4829         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4830         reg_val &= 0x8cffffff;
4831         reg_val = 0x8c000000;
4832         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4833
4834         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4835         reg_val &= 0xffffff00;
4836         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4837
4838         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4839         reg_val &= 0x00ffffff;
4840         reg_val |= 0xb0000000;
4841         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4842 }
4843
4844 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4845                                          struct intel_link_m_n *m_n)
4846 {
4847         struct drm_device *dev = crtc->base.dev;
4848         struct drm_i915_private *dev_priv = dev->dev_private;
4849         int pipe = crtc->pipe;
4850
4851         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4852         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4853         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4854         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4855 }
4856
4857 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4858                                          struct intel_link_m_n *m_n)
4859 {
4860         struct drm_device *dev = crtc->base.dev;
4861         struct drm_i915_private *dev_priv = dev->dev_private;
4862         int pipe = crtc->pipe;
4863         enum transcoder transcoder = crtc->config.cpu_transcoder;
4864
4865         if (INTEL_INFO(dev)->gen >= 5) {
4866                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4867                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4868                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4869                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4870         } else {
4871                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4872                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4873                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4874                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4875         }
4876 }
4877
4878 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4879 {
4880         if (crtc->config.has_pch_encoder)
4881                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4882         else
4883                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4884 }
4885
4886 static void vlv_update_pll(struct intel_crtc *crtc)
4887 {
4888         struct drm_device *dev = crtc->base.dev;
4889         struct drm_i915_private *dev_priv = dev->dev_private;
4890         int pipe = crtc->pipe;
4891         u32 dpll, mdiv;
4892         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4893         u32 coreclk, reg_val, dpll_md;
4894
4895         mutex_lock(&dev_priv->dpio_lock);
4896
4897         bestn = crtc->config.dpll.n;
4898         bestm1 = crtc->config.dpll.m1;
4899         bestm2 = crtc->config.dpll.m2;
4900         bestp1 = crtc->config.dpll.p1;
4901         bestp2 = crtc->config.dpll.p2;
4902
4903         /* See eDP HDMI DPIO driver vbios notes doc */
4904
4905         /* PLL B needs special handling */
4906         if (pipe)
4907                 vlv_pllb_recal_opamp(dev_priv, pipe);
4908
4909         /* Set up Tx target for periodic Rcomp update */
4910         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4911
4912         /* Disable target IRef on PLL */
4913         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4914         reg_val &= 0x00ffffff;
4915         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4916
4917         /* Disable fast lock */
4918         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4919
4920         /* Set idtafcrecal before PLL is enabled */
4921         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4922         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4923         mdiv |= ((bestn << DPIO_N_SHIFT));
4924         mdiv |= (1 << DPIO_K_SHIFT);
4925
4926         /*
4927          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4928          * but we don't support that).
4929          * Note: don't use the DAC post divider as it seems unstable.
4930          */
4931         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4932         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4933
4934         mdiv |= DPIO_ENABLE_CALIBRATION;
4935         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4936
4937         /* Set HBR and RBR LPF coefficients */
4938         if (crtc->config.port_clock == 162000 ||
4939             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4940             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4941                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4942                                  0x009f0003);
4943         else
4944                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4945                                  0x00d0000f);
4946
4947         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4948             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4949                 /* Use SSC source */
4950                 if (!pipe)
4951                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4952                                          0x0df40000);
4953                 else
4954                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4955                                          0x0df70000);
4956         } else { /* HDMI or VGA */
4957                 /* Use bend source */
4958                 if (!pipe)
4959                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4960                                          0x0df70000);
4961                 else
4962                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4963                                          0x0df40000);
4964         }
4965
4966         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4967         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4968         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4969             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4970                 coreclk |= 0x01000000;
4971         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4972
4973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4974
4975         /* Enable DPIO clock input */
4976         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4977                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4978         /* We should never disable this, set it here for state tracking */
4979         if (pipe == PIPE_B)
4980                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4981         dpll |= DPLL_VCO_ENABLE;
4982         crtc->config.dpll_hw_state.dpll = dpll;
4983
4984         dpll_md = (crtc->config.pixel_multiplier - 1)
4985                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4986         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4987
4988         if (crtc->config.has_dp_encoder)
4989                 intel_dp_set_m_n(crtc);
4990
4991         mutex_unlock(&dev_priv->dpio_lock);
4992 }
4993
4994 static void i9xx_update_pll(struct intel_crtc *crtc,
4995                             intel_clock_t *reduced_clock,
4996                             int num_connectors)
4997 {
4998         struct drm_device *dev = crtc->base.dev;
4999         struct drm_i915_private *dev_priv = dev->dev_private;
5000         u32 dpll;
5001         bool is_sdvo;
5002         struct dpll *clock = &crtc->config.dpll;
5003
5004         i9xx_update_pll_dividers(crtc, reduced_clock);
5005
5006         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5007                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5008
5009         dpll = DPLL_VGA_MODE_DIS;
5010
5011         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5012                 dpll |= DPLLB_MODE_LVDS;
5013         else
5014                 dpll |= DPLLB_MODE_DAC_SERIAL;
5015
5016         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5017                 dpll |= (crtc->config.pixel_multiplier - 1)
5018                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5019         }
5020
5021         if (is_sdvo)
5022                 dpll |= DPLL_SDVO_HIGH_SPEED;
5023
5024         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5025                 dpll |= DPLL_SDVO_HIGH_SPEED;
5026
5027         /* compute bitmask from p1 value */
5028         if (IS_PINEVIEW(dev))
5029                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5030         else {
5031                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5032                 if (IS_G4X(dev) && reduced_clock)
5033                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5034         }
5035         switch (clock->p2) {
5036         case 5:
5037                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5038                 break;
5039         case 7:
5040                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5041                 break;
5042         case 10:
5043                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5044                 break;
5045         case 14:
5046                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5047                 break;
5048         }
5049         if (INTEL_INFO(dev)->gen >= 4)
5050                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5051
5052         if (crtc->config.sdvo_tv_clock)
5053                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5054         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5055                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5056                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5057         else
5058                 dpll |= PLL_REF_INPUT_DREFCLK;
5059
5060         dpll |= DPLL_VCO_ENABLE;
5061         crtc->config.dpll_hw_state.dpll = dpll;
5062
5063         if (INTEL_INFO(dev)->gen >= 4) {
5064                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5065                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5066                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5067         }
5068
5069         if (crtc->config.has_dp_encoder)
5070                 intel_dp_set_m_n(crtc);
5071 }
5072
5073 static void i8xx_update_pll(struct intel_crtc *crtc,
5074                             intel_clock_t *reduced_clock,
5075                             int num_connectors)
5076 {
5077         struct drm_device *dev = crtc->base.dev;
5078         struct drm_i915_private *dev_priv = dev->dev_private;
5079         u32 dpll;
5080         struct dpll *clock = &crtc->config.dpll;
5081
5082         i9xx_update_pll_dividers(crtc, reduced_clock);
5083
5084         dpll = DPLL_VGA_MODE_DIS;
5085
5086         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5087                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5088         } else {
5089                 if (clock->p1 == 2)
5090                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5091                 else
5092                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5093                 if (clock->p2 == 4)
5094                         dpll |= PLL_P2_DIVIDE_BY_4;
5095         }
5096
5097         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5098                 dpll |= DPLL_DVO_2X_MODE;
5099
5100         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5101                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5102                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5103         else
5104                 dpll |= PLL_REF_INPUT_DREFCLK;
5105
5106         dpll |= DPLL_VCO_ENABLE;
5107         crtc->config.dpll_hw_state.dpll = dpll;
5108 }
5109
5110 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5111 {
5112         struct drm_device *dev = intel_crtc->base.dev;
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114         enum pipe pipe = intel_crtc->pipe;
5115         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5116         struct drm_display_mode *adjusted_mode =
5117                 &intel_crtc->config.adjusted_mode;
5118         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5119
5120         /* We need to be careful not to changed the adjusted mode, for otherwise
5121          * the hw state checker will get angry at the mismatch. */
5122         crtc_vtotal = adjusted_mode->crtc_vtotal;
5123         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5124
5125         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5126                 /* the chip adds 2 halflines automatically */
5127                 crtc_vtotal -= 1;
5128                 crtc_vblank_end -= 1;
5129                 vsyncshift = adjusted_mode->crtc_hsync_start
5130                              - adjusted_mode->crtc_htotal / 2;
5131         } else {
5132                 vsyncshift = 0;
5133         }
5134
5135         if (INTEL_INFO(dev)->gen > 3)
5136                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5137
5138         I915_WRITE(HTOTAL(cpu_transcoder),
5139                    (adjusted_mode->crtc_hdisplay - 1) |
5140                    ((adjusted_mode->crtc_htotal - 1) << 16));
5141         I915_WRITE(HBLANK(cpu_transcoder),
5142                    (adjusted_mode->crtc_hblank_start - 1) |
5143                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5144         I915_WRITE(HSYNC(cpu_transcoder),
5145                    (adjusted_mode->crtc_hsync_start - 1) |
5146                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5147
5148         I915_WRITE(VTOTAL(cpu_transcoder),
5149                    (adjusted_mode->crtc_vdisplay - 1) |
5150                    ((crtc_vtotal - 1) << 16));
5151         I915_WRITE(VBLANK(cpu_transcoder),
5152                    (adjusted_mode->crtc_vblank_start - 1) |
5153                    ((crtc_vblank_end - 1) << 16));
5154         I915_WRITE(VSYNC(cpu_transcoder),
5155                    (adjusted_mode->crtc_vsync_start - 1) |
5156                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5157
5158         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5159          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5160          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5161          * bits. */
5162         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5163             (pipe == PIPE_B || pipe == PIPE_C))
5164                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5165
5166         /* pipesrc controls the size that is scaled from, which should
5167          * always be the user's requested size.
5168          */
5169         I915_WRITE(PIPESRC(pipe),
5170                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5171                    (intel_crtc->config.pipe_src_h - 1));
5172 }
5173
5174 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5175                                    struct intel_crtc_config *pipe_config)
5176 {
5177         struct drm_device *dev = crtc->base.dev;
5178         struct drm_i915_private *dev_priv = dev->dev_private;
5179         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5180         uint32_t tmp;
5181
5182         tmp = I915_READ(HTOTAL(cpu_transcoder));
5183         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5184         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5185         tmp = I915_READ(HBLANK(cpu_transcoder));
5186         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5187         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5188         tmp = I915_READ(HSYNC(cpu_transcoder));
5189         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5190         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5191
5192         tmp = I915_READ(VTOTAL(cpu_transcoder));
5193         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5194         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5195         tmp = I915_READ(VBLANK(cpu_transcoder));
5196         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5197         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5198         tmp = I915_READ(VSYNC(cpu_transcoder));
5199         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5200         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5201
5202         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5203                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5204                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5205                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5206         }
5207
5208         tmp = I915_READ(PIPESRC(crtc->pipe));
5209         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5210         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5211
5212         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5213         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5214 }
5215
5216 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5217                                              struct intel_crtc_config *pipe_config)
5218 {
5219         struct drm_crtc *crtc = &intel_crtc->base;
5220
5221         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5222         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5223         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5224         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5225
5226         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5227         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5228         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5229         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5230
5231         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5232
5233         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5234         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5235 }
5236
5237 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5238 {
5239         struct drm_device *dev = intel_crtc->base.dev;
5240         struct drm_i915_private *dev_priv = dev->dev_private;
5241         uint32_t pipeconf;
5242
5243         pipeconf = 0;
5244
5245         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5246             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5247                 pipeconf |= PIPECONF_ENABLE;
5248
5249         if (intel_crtc->config.double_wide)
5250                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5251
5252         /* only g4x and later have fancy bpc/dither controls */
5253         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5254                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5255                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5256                         pipeconf |= PIPECONF_DITHER_EN |
5257                                     PIPECONF_DITHER_TYPE_SP;
5258
5259                 switch (intel_crtc->config.pipe_bpp) {
5260                 case 18:
5261                         pipeconf |= PIPECONF_6BPC;
5262                         break;
5263                 case 24:
5264                         pipeconf |= PIPECONF_8BPC;
5265                         break;
5266                 case 30:
5267                         pipeconf |= PIPECONF_10BPC;
5268                         break;
5269                 default:
5270                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5271                         BUG();
5272                 }
5273         }
5274
5275         if (HAS_PIPE_CXSR(dev)) {
5276                 if (intel_crtc->lowfreq_avail) {
5277                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5278                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5279                 } else {
5280                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5281                 }
5282         }
5283
5284         if (!IS_GEN2(dev) &&
5285             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5286                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5287         else
5288                 pipeconf |= PIPECONF_PROGRESSIVE;
5289
5290         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5291                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5292
5293         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5294         POSTING_READ(PIPECONF(intel_crtc->pipe));
5295 }
5296
5297 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5298                               int x, int y,
5299                               struct drm_framebuffer *fb)
5300 {
5301         struct drm_device *dev = crtc->dev;
5302         struct drm_i915_private *dev_priv = dev->dev_private;
5303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304         int pipe = intel_crtc->pipe;
5305         int plane = intel_crtc->plane;
5306         int refclk, num_connectors = 0;
5307         intel_clock_t clock, reduced_clock;
5308         u32 dspcntr;
5309         bool ok, has_reduced_clock = false;
5310         bool is_lvds = false, is_dsi = false;
5311         struct intel_encoder *encoder;
5312         const intel_limit_t *limit;
5313         int ret;
5314
5315         for_each_encoder_on_crtc(dev, crtc, encoder) {
5316                 switch (encoder->type) {
5317                 case INTEL_OUTPUT_LVDS:
5318                         is_lvds = true;
5319                         break;
5320                 case INTEL_OUTPUT_DSI:
5321                         is_dsi = true;
5322                         break;
5323                 }
5324
5325                 num_connectors++;
5326         }
5327
5328         if (is_dsi)
5329                 goto skip_dpll;
5330
5331         if (!intel_crtc->config.clock_set) {
5332                 refclk = i9xx_get_refclk(crtc, num_connectors);
5333
5334                 /*
5335                  * Returns a set of divisors for the desired target clock with
5336                  * the given refclk, or FALSE.  The returned values represent
5337                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5338                  * 2) / p1 / p2.
5339                  */
5340                 limit = intel_limit(crtc, refclk);
5341                 ok = dev_priv->display.find_dpll(limit, crtc,
5342                                                  intel_crtc->config.port_clock,
5343                                                  refclk, NULL, &clock);
5344                 if (!ok) {
5345                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5346                         return -EINVAL;
5347                 }
5348
5349                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5350                         /*
5351                          * Ensure we match the reduced clock's P to the target
5352                          * clock.  If the clocks don't match, we can't switch
5353                          * the display clock by using the FP0/FP1. In such case
5354                          * we will disable the LVDS downclock feature.
5355                          */
5356                         has_reduced_clock =
5357                                 dev_priv->display.find_dpll(limit, crtc,
5358                                                             dev_priv->lvds_downclock,
5359                                                             refclk, &clock,
5360                                                             &reduced_clock);
5361                 }
5362                 /* Compat-code for transition, will disappear. */
5363                 intel_crtc->config.dpll.n = clock.n;
5364                 intel_crtc->config.dpll.m1 = clock.m1;
5365                 intel_crtc->config.dpll.m2 = clock.m2;
5366                 intel_crtc->config.dpll.p1 = clock.p1;
5367                 intel_crtc->config.dpll.p2 = clock.p2;
5368         }
5369
5370         if (IS_GEN2(dev)) {
5371                 i8xx_update_pll(intel_crtc,
5372                                 has_reduced_clock ? &reduced_clock : NULL,
5373                                 num_connectors);
5374         } else if (IS_VALLEYVIEW(dev)) {
5375                 vlv_update_pll(intel_crtc);
5376         } else {
5377                 i9xx_update_pll(intel_crtc,
5378                                 has_reduced_clock ? &reduced_clock : NULL,
5379                                 num_connectors);
5380         }
5381
5382 skip_dpll:
5383         /* Set up the display plane register */
5384         dspcntr = DISPPLANE_GAMMA_ENABLE;
5385
5386         if (!IS_VALLEYVIEW(dev)) {
5387                 if (pipe == 0)
5388                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5389                 else
5390                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5391         }
5392
5393         intel_set_pipe_timings(intel_crtc);
5394
5395         /* pipesrc and dspsize control the size that is scaled from,
5396          * which should always be the user's requested size.
5397          */
5398         I915_WRITE(DSPSIZE(plane),
5399                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5400                    (intel_crtc->config.pipe_src_w - 1));
5401         I915_WRITE(DSPPOS(plane), 0);
5402
5403         i9xx_set_pipeconf(intel_crtc);
5404
5405         I915_WRITE(DSPCNTR(plane), dspcntr);
5406         POSTING_READ(DSPCNTR(plane));
5407
5408         ret = intel_pipe_set_base(crtc, x, y, fb);
5409
5410         return ret;
5411 }
5412
5413 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5414                                  struct intel_crtc_config *pipe_config)
5415 {
5416         struct drm_device *dev = crtc->base.dev;
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         uint32_t tmp;
5419
5420         tmp = I915_READ(PFIT_CONTROL);
5421         if (!(tmp & PFIT_ENABLE))
5422                 return;
5423
5424         /* Check whether the pfit is attached to our pipe. */
5425         if (INTEL_INFO(dev)->gen < 4) {
5426                 if (crtc->pipe != PIPE_B)
5427                         return;
5428         } else {
5429                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5430                         return;
5431         }
5432
5433         pipe_config->gmch_pfit.control = tmp;
5434         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5435         if (INTEL_INFO(dev)->gen < 5)
5436                 pipe_config->gmch_pfit.lvds_border_bits =
5437                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5438 }
5439
5440 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5441                                struct intel_crtc_config *pipe_config)
5442 {
5443         struct drm_device *dev = crtc->base.dev;
5444         struct drm_i915_private *dev_priv = dev->dev_private;
5445         int pipe = pipe_config->cpu_transcoder;
5446         intel_clock_t clock;
5447         u32 mdiv;
5448         int refclk = 100000;
5449
5450         mutex_lock(&dev_priv->dpio_lock);
5451         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5452         mutex_unlock(&dev_priv->dpio_lock);
5453
5454         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5455         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5456         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5457         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5458         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5459
5460         vlv_clock(refclk, &clock);
5461
5462         /* clock.dot is the fast clock */
5463         pipe_config->port_clock = clock.dot / 5;
5464 }
5465
5466 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5467                                  struct intel_crtc_config *pipe_config)
5468 {
5469         struct drm_device *dev = crtc->base.dev;
5470         struct drm_i915_private *dev_priv = dev->dev_private;
5471         uint32_t tmp;
5472
5473         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5474         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5475
5476         tmp = I915_READ(PIPECONF(crtc->pipe));
5477         if (!(tmp & PIPECONF_ENABLE))
5478                 return false;
5479
5480         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5481                 switch (tmp & PIPECONF_BPC_MASK) {
5482                 case PIPECONF_6BPC:
5483                         pipe_config->pipe_bpp = 18;
5484                         break;
5485                 case PIPECONF_8BPC:
5486                         pipe_config->pipe_bpp = 24;
5487                         break;
5488                 case PIPECONF_10BPC:
5489                         pipe_config->pipe_bpp = 30;
5490                         break;
5491                 default:
5492                         break;
5493                 }
5494         }
5495
5496         if (INTEL_INFO(dev)->gen < 4)
5497                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5498
5499         intel_get_pipe_timings(crtc, pipe_config);
5500
5501         i9xx_get_pfit_config(crtc, pipe_config);
5502
5503         if (INTEL_INFO(dev)->gen >= 4) {
5504                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5505                 pipe_config->pixel_multiplier =
5506                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5507                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5508                 pipe_config->dpll_hw_state.dpll_md = tmp;
5509         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5510                 tmp = I915_READ(DPLL(crtc->pipe));
5511                 pipe_config->pixel_multiplier =
5512                         ((tmp & SDVO_MULTIPLIER_MASK)
5513                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5514         } else {
5515                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5516                  * port and will be fixed up in the encoder->get_config
5517                  * function. */
5518                 pipe_config->pixel_multiplier = 1;
5519         }
5520         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5521         if (!IS_VALLEYVIEW(dev)) {
5522                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5523                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5524         } else {
5525                 /* Mask out read-only status bits. */
5526                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5527                                                      DPLL_PORTC_READY_MASK |
5528                                                      DPLL_PORTB_READY_MASK);
5529         }
5530
5531         if (IS_VALLEYVIEW(dev))
5532                 vlv_crtc_clock_get(crtc, pipe_config);
5533         else
5534                 i9xx_crtc_clock_get(crtc, pipe_config);
5535
5536         return true;
5537 }
5538
5539 static void ironlake_init_pch_refclk(struct drm_device *dev)
5540 {
5541         struct drm_i915_private *dev_priv = dev->dev_private;
5542         struct drm_mode_config *mode_config = &dev->mode_config;
5543         struct intel_encoder *encoder;
5544         u32 val, final;
5545         bool has_lvds = false;
5546         bool has_cpu_edp = false;
5547         bool has_panel = false;
5548         bool has_ck505 = false;
5549         bool can_ssc = false;
5550
5551         /* We need to take the global config into account */
5552         list_for_each_entry(encoder, &mode_config->encoder_list,
5553                             base.head) {
5554                 switch (encoder->type) {
5555                 case INTEL_OUTPUT_LVDS:
5556                         has_panel = true;
5557                         has_lvds = true;
5558                         break;
5559                 case INTEL_OUTPUT_EDP:
5560                         has_panel = true;
5561                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5562                                 has_cpu_edp = true;
5563                         break;
5564                 }
5565         }
5566
5567         if (HAS_PCH_IBX(dev)) {
5568                 has_ck505 = dev_priv->vbt.display_clock_mode;
5569                 can_ssc = has_ck505;
5570         } else {
5571                 has_ck505 = false;
5572                 can_ssc = true;
5573         }
5574
5575         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5576                       has_panel, has_lvds, has_ck505);
5577
5578         /* Ironlake: try to setup display ref clock before DPLL
5579          * enabling. This is only under driver's control after
5580          * PCH B stepping, previous chipset stepping should be
5581          * ignoring this setting.
5582          */
5583         val = I915_READ(PCH_DREF_CONTROL);
5584
5585         /* As we must carefully and slowly disable/enable each source in turn,
5586          * compute the final state we want first and check if we need to
5587          * make any changes at all.
5588          */
5589         final = val;
5590         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5591         if (has_ck505)
5592                 final |= DREF_NONSPREAD_CK505_ENABLE;
5593         else
5594                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5595
5596         final &= ~DREF_SSC_SOURCE_MASK;
5597         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5598         final &= ~DREF_SSC1_ENABLE;
5599
5600         if (has_panel) {
5601                 final |= DREF_SSC_SOURCE_ENABLE;
5602
5603                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5604                         final |= DREF_SSC1_ENABLE;
5605
5606                 if (has_cpu_edp) {
5607                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5608                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5609                         else
5610                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5611                 } else
5612                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5613         } else {
5614                 final |= DREF_SSC_SOURCE_DISABLE;
5615                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5616         }
5617
5618         if (final == val)
5619                 return;
5620
5621         /* Always enable nonspread source */
5622         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5623
5624         if (has_ck505)
5625                 val |= DREF_NONSPREAD_CK505_ENABLE;
5626         else
5627                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5628
5629         if (has_panel) {
5630                 val &= ~DREF_SSC_SOURCE_MASK;
5631                 val |= DREF_SSC_SOURCE_ENABLE;
5632
5633                 /* SSC must be turned on before enabling the CPU output  */
5634                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5635                         DRM_DEBUG_KMS("Using SSC on panel\n");
5636                         val |= DREF_SSC1_ENABLE;
5637                 } else
5638                         val &= ~DREF_SSC1_ENABLE;
5639
5640                 /* Get SSC going before enabling the outputs */
5641                 I915_WRITE(PCH_DREF_CONTROL, val);
5642                 POSTING_READ(PCH_DREF_CONTROL);
5643                 udelay(200);
5644
5645                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5646
5647                 /* Enable CPU source on CPU attached eDP */
5648                 if (has_cpu_edp) {
5649                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5650                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5651                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5652                         }
5653                         else
5654                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5655                 } else
5656                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5657
5658                 I915_WRITE(PCH_DREF_CONTROL, val);
5659                 POSTING_READ(PCH_DREF_CONTROL);
5660                 udelay(200);
5661         } else {
5662                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5663
5664                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5665
5666                 /* Turn off CPU output */
5667                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5668
5669                 I915_WRITE(PCH_DREF_CONTROL, val);
5670                 POSTING_READ(PCH_DREF_CONTROL);
5671                 udelay(200);
5672
5673                 /* Turn off the SSC source */
5674                 val &= ~DREF_SSC_SOURCE_MASK;
5675                 val |= DREF_SSC_SOURCE_DISABLE;
5676
5677                 /* Turn off SSC1 */
5678                 val &= ~DREF_SSC1_ENABLE;
5679
5680                 I915_WRITE(PCH_DREF_CONTROL, val);
5681                 POSTING_READ(PCH_DREF_CONTROL);
5682                 udelay(200);
5683         }
5684
5685         BUG_ON(val != final);
5686 }
5687
5688 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5689 {
5690         uint32_t tmp;
5691
5692         tmp = I915_READ(SOUTH_CHICKEN2);
5693         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5694         I915_WRITE(SOUTH_CHICKEN2, tmp);
5695
5696         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5697                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5698                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5699
5700         tmp = I915_READ(SOUTH_CHICKEN2);
5701         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5702         I915_WRITE(SOUTH_CHICKEN2, tmp);
5703
5704         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5705                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5706                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5707 }
5708
5709 /* WaMPhyProgramming:hsw */
5710 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5711 {
5712         uint32_t tmp;
5713
5714         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5715         tmp &= ~(0xFF << 24);
5716         tmp |= (0x12 << 24);
5717         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5718
5719         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5720         tmp |= (1 << 11);
5721         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5722
5723         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5724         tmp |= (1 << 11);
5725         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5726
5727         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5728         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5729         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5730
5731         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5732         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5733         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5734
5735         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5736         tmp &= ~(7 << 13);
5737         tmp |= (5 << 13);
5738         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5739
5740         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5741         tmp &= ~(7 << 13);
5742         tmp |= (5 << 13);
5743         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5744
5745         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5746         tmp &= ~0xFF;
5747         tmp |= 0x1C;
5748         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5749
5750         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5751         tmp &= ~0xFF;
5752         tmp |= 0x1C;
5753         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5754
5755         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5756         tmp &= ~(0xFF << 16);
5757         tmp |= (0x1C << 16);
5758         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5759
5760         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5761         tmp &= ~(0xFF << 16);
5762         tmp |= (0x1C << 16);
5763         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5764
5765         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5766         tmp |= (1 << 27);
5767         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5768
5769         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5770         tmp |= (1 << 27);
5771         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5772
5773         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5774         tmp &= ~(0xF << 28);
5775         tmp |= (4 << 28);
5776         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5777
5778         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5779         tmp &= ~(0xF << 28);
5780         tmp |= (4 << 28);
5781         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5782 }
5783
5784 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5785  * Programming" based on the parameters passed:
5786  * - Sequence to enable CLKOUT_DP
5787  * - Sequence to enable CLKOUT_DP without spread
5788  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5789  */
5790 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5791                                  bool with_fdi)
5792 {
5793         struct drm_i915_private *dev_priv = dev->dev_private;
5794         uint32_t reg, tmp;
5795
5796         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5797                 with_spread = true;
5798         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5799                  with_fdi, "LP PCH doesn't have FDI\n"))
5800                 with_fdi = false;
5801
5802         mutex_lock(&dev_priv->dpio_lock);
5803
5804         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5805         tmp &= ~SBI_SSCCTL_DISABLE;
5806         tmp |= SBI_SSCCTL_PATHALT;
5807         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5808
5809         udelay(24);
5810
5811         if (with_spread) {
5812                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5813                 tmp &= ~SBI_SSCCTL_PATHALT;
5814                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5815
5816                 if (with_fdi) {
5817                         lpt_reset_fdi_mphy(dev_priv);
5818                         lpt_program_fdi_mphy(dev_priv);
5819                 }
5820         }
5821
5822         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5823                SBI_GEN0 : SBI_DBUFF0;
5824         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5825         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5826         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5827
5828         mutex_unlock(&dev_priv->dpio_lock);
5829 }
5830
5831 /* Sequence to disable CLKOUT_DP */
5832 static void lpt_disable_clkout_dp(struct drm_device *dev)
5833 {
5834         struct drm_i915_private *dev_priv = dev->dev_private;
5835         uint32_t reg, tmp;
5836
5837         mutex_lock(&dev_priv->dpio_lock);
5838
5839         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5840                SBI_GEN0 : SBI_DBUFF0;
5841         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5842         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5843         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5844
5845         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5846         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5847                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5848                         tmp |= SBI_SSCCTL_PATHALT;
5849                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5850                         udelay(32);
5851                 }
5852                 tmp |= SBI_SSCCTL_DISABLE;
5853                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5854         }
5855
5856         mutex_unlock(&dev_priv->dpio_lock);
5857 }
5858
5859 static void lpt_init_pch_refclk(struct drm_device *dev)
5860 {
5861         struct drm_mode_config *mode_config = &dev->mode_config;
5862         struct intel_encoder *encoder;
5863         bool has_vga = false;
5864
5865         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5866                 switch (encoder->type) {
5867                 case INTEL_OUTPUT_ANALOG:
5868                         has_vga = true;
5869                         break;
5870                 }
5871         }
5872
5873         if (has_vga)
5874                 lpt_enable_clkout_dp(dev, true, true);
5875         else
5876                 lpt_disable_clkout_dp(dev);
5877 }
5878
5879 /*
5880  * Initialize reference clocks when the driver loads
5881  */
5882 void intel_init_pch_refclk(struct drm_device *dev)
5883 {
5884         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5885                 ironlake_init_pch_refclk(dev);
5886         else if (HAS_PCH_LPT(dev))
5887                 lpt_init_pch_refclk(dev);
5888 }
5889
5890 static int ironlake_get_refclk(struct drm_crtc *crtc)
5891 {
5892         struct drm_device *dev = crtc->dev;
5893         struct drm_i915_private *dev_priv = dev->dev_private;
5894         struct intel_encoder *encoder;
5895         int num_connectors = 0;
5896         bool is_lvds = false;
5897
5898         for_each_encoder_on_crtc(dev, crtc, encoder) {
5899                 switch (encoder->type) {
5900                 case INTEL_OUTPUT_LVDS:
5901                         is_lvds = true;
5902                         break;
5903                 }
5904                 num_connectors++;
5905         }
5906
5907         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5908                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5909                               dev_priv->vbt.lvds_ssc_freq);
5910                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5911         }
5912
5913         return 120000;
5914 }
5915
5916 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5917 {
5918         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5920         int pipe = intel_crtc->pipe;
5921         uint32_t val;
5922
5923         val = 0;
5924
5925         switch (intel_crtc->config.pipe_bpp) {
5926         case 18:
5927                 val |= PIPECONF_6BPC;
5928                 break;
5929         case 24:
5930                 val |= PIPECONF_8BPC;
5931                 break;
5932         case 30:
5933                 val |= PIPECONF_10BPC;
5934                 break;
5935         case 36:
5936                 val |= PIPECONF_12BPC;
5937                 break;
5938         default:
5939                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5940                 BUG();
5941         }
5942
5943         if (intel_crtc->config.dither)
5944                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5945
5946         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5947                 val |= PIPECONF_INTERLACED_ILK;
5948         else
5949                 val |= PIPECONF_PROGRESSIVE;
5950
5951         if (intel_crtc->config.limited_color_range)
5952                 val |= PIPECONF_COLOR_RANGE_SELECT;
5953
5954         I915_WRITE(PIPECONF(pipe), val);
5955         POSTING_READ(PIPECONF(pipe));
5956 }
5957
5958 /*
5959  * Set up the pipe CSC unit.
5960  *
5961  * Currently only full range RGB to limited range RGB conversion
5962  * is supported, but eventually this should handle various
5963  * RGB<->YCbCr scenarios as well.
5964  */
5965 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5966 {
5967         struct drm_device *dev = crtc->dev;
5968         struct drm_i915_private *dev_priv = dev->dev_private;
5969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970         int pipe = intel_crtc->pipe;
5971         uint16_t coeff = 0x7800; /* 1.0 */
5972
5973         /*
5974          * TODO: Check what kind of values actually come out of the pipe
5975          * with these coeff/postoff values and adjust to get the best
5976          * accuracy. Perhaps we even need to take the bpc value into
5977          * consideration.
5978          */
5979
5980         if (intel_crtc->config.limited_color_range)
5981                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5982
5983         /*
5984          * GY/GU and RY/RU should be the other way around according
5985          * to BSpec, but reality doesn't agree. Just set them up in
5986          * a way that results in the correct picture.
5987          */
5988         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5989         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5990
5991         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5992         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5993
5994         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5995         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5996
5997         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5998         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5999         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6000
6001         if (INTEL_INFO(dev)->gen > 6) {
6002                 uint16_t postoff = 0;
6003
6004                 if (intel_crtc->config.limited_color_range)
6005                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6006
6007                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6008                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6009                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6010
6011                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6012         } else {
6013                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6014
6015                 if (intel_crtc->config.limited_color_range)
6016                         mode |= CSC_BLACK_SCREEN_OFFSET;
6017
6018                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6019         }
6020 }
6021
6022 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6023 {
6024         struct drm_device *dev = crtc->dev;
6025         struct drm_i915_private *dev_priv = dev->dev_private;
6026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6027         enum pipe pipe = intel_crtc->pipe;
6028         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6029         uint32_t val;
6030
6031         val = 0;
6032
6033         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6034                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6035
6036         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6037                 val |= PIPECONF_INTERLACED_ILK;
6038         else
6039                 val |= PIPECONF_PROGRESSIVE;
6040
6041         I915_WRITE(PIPECONF(cpu_transcoder), val);
6042         POSTING_READ(PIPECONF(cpu_transcoder));
6043
6044         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6045         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6046
6047         if (IS_BROADWELL(dev)) {
6048                 val = 0;
6049
6050                 switch (intel_crtc->config.pipe_bpp) {
6051                 case 18:
6052                         val |= PIPEMISC_DITHER_6_BPC;
6053                         break;
6054                 case 24:
6055                         val |= PIPEMISC_DITHER_8_BPC;
6056                         break;
6057                 case 30:
6058                         val |= PIPEMISC_DITHER_10_BPC;
6059                         break;
6060                 case 36:
6061                         val |= PIPEMISC_DITHER_12_BPC;
6062                         break;
6063                 default:
6064                         /* Case prevented by pipe_config_set_bpp. */
6065                         BUG();
6066                 }
6067
6068                 if (intel_crtc->config.dither)
6069                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6070
6071                 I915_WRITE(PIPEMISC(pipe), val);
6072         }
6073 }
6074
6075 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6076                                     intel_clock_t *clock,
6077                                     bool *has_reduced_clock,
6078                                     intel_clock_t *reduced_clock)
6079 {
6080         struct drm_device *dev = crtc->dev;
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082         struct intel_encoder *intel_encoder;
6083         int refclk;
6084         const intel_limit_t *limit;
6085         bool ret, is_lvds = false;
6086
6087         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6088                 switch (intel_encoder->type) {
6089                 case INTEL_OUTPUT_LVDS:
6090                         is_lvds = true;
6091                         break;
6092                 }
6093         }
6094
6095         refclk = ironlake_get_refclk(crtc);
6096
6097         /*
6098          * Returns a set of divisors for the desired target clock with the given
6099          * refclk, or FALSE.  The returned values represent the clock equation:
6100          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6101          */
6102         limit = intel_limit(crtc, refclk);
6103         ret = dev_priv->display.find_dpll(limit, crtc,
6104                                           to_intel_crtc(crtc)->config.port_clock,
6105                                           refclk, NULL, clock);
6106         if (!ret)
6107                 return false;
6108
6109         if (is_lvds && dev_priv->lvds_downclock_avail) {
6110                 /*
6111                  * Ensure we match the reduced clock's P to the target clock.
6112                  * If the clocks don't match, we can't switch the display clock
6113                  * by using the FP0/FP1. In such case we will disable the LVDS
6114                  * downclock feature.
6115                 */
6116                 *has_reduced_clock =
6117                         dev_priv->display.find_dpll(limit, crtc,
6118                                                     dev_priv->lvds_downclock,
6119                                                     refclk, clock,
6120                                                     reduced_clock);
6121         }
6122
6123         return true;
6124 }
6125
6126 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6127 {
6128         /*
6129          * Account for spread spectrum to avoid
6130          * oversubscribing the link. Max center spread
6131          * is 2.5%; use 5% for safety's sake.
6132          */
6133         u32 bps = target_clock * bpp * 21 / 20;
6134         return bps / (link_bw * 8) + 1;
6135 }
6136
6137 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6138 {
6139         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6140 }
6141
6142 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6143                                       u32 *fp,
6144                                       intel_clock_t *reduced_clock, u32 *fp2)
6145 {
6146         struct drm_crtc *crtc = &intel_crtc->base;
6147         struct drm_device *dev = crtc->dev;
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149         struct intel_encoder *intel_encoder;
6150         uint32_t dpll;
6151         int factor, num_connectors = 0;
6152         bool is_lvds = false, is_sdvo = false;
6153
6154         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6155                 switch (intel_encoder->type) {
6156                 case INTEL_OUTPUT_LVDS:
6157                         is_lvds = true;
6158                         break;
6159                 case INTEL_OUTPUT_SDVO:
6160                 case INTEL_OUTPUT_HDMI:
6161                         is_sdvo = true;
6162                         break;
6163                 }
6164
6165                 num_connectors++;
6166         }
6167
6168         /* Enable autotuning of the PLL clock (if permissible) */
6169         factor = 21;
6170         if (is_lvds) {
6171                 if ((intel_panel_use_ssc(dev_priv) &&
6172                      dev_priv->vbt.lvds_ssc_freq == 100) ||
6173                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6174                         factor = 25;
6175         } else if (intel_crtc->config.sdvo_tv_clock)
6176                 factor = 20;
6177
6178         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6179                 *fp |= FP_CB_TUNE;
6180
6181         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6182                 *fp2 |= FP_CB_TUNE;
6183
6184         dpll = 0;
6185
6186         if (is_lvds)
6187                 dpll |= DPLLB_MODE_LVDS;
6188         else
6189                 dpll |= DPLLB_MODE_DAC_SERIAL;
6190
6191         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6192                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6193
6194         if (is_sdvo)
6195                 dpll |= DPLL_SDVO_HIGH_SPEED;
6196         if (intel_crtc->config.has_dp_encoder)
6197                 dpll |= DPLL_SDVO_HIGH_SPEED;
6198
6199         /* compute bitmask from p1 value */
6200         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6201         /* also FPA1 */
6202         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6203
6204         switch (intel_crtc->config.dpll.p2) {
6205         case 5:
6206                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6207                 break;
6208         case 7:
6209                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6210                 break;
6211         case 10:
6212                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6213                 break;
6214         case 14:
6215                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6216                 break;
6217         }
6218
6219         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6220                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6221         else
6222                 dpll |= PLL_REF_INPUT_DREFCLK;
6223
6224         return dpll | DPLL_VCO_ENABLE;
6225 }
6226
6227 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6228                                   int x, int y,
6229                                   struct drm_framebuffer *fb)
6230 {
6231         struct drm_device *dev = crtc->dev;
6232         struct drm_i915_private *dev_priv = dev->dev_private;
6233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234         int pipe = intel_crtc->pipe;
6235         int plane = intel_crtc->plane;
6236         int num_connectors = 0;
6237         intel_clock_t clock, reduced_clock;
6238         u32 dpll = 0, fp = 0, fp2 = 0;
6239         bool ok, has_reduced_clock = false;
6240         bool is_lvds = false;
6241         struct intel_encoder *encoder;
6242         struct intel_shared_dpll *pll;
6243         int ret;
6244
6245         for_each_encoder_on_crtc(dev, crtc, encoder) {
6246                 switch (encoder->type) {
6247                 case INTEL_OUTPUT_LVDS:
6248                         is_lvds = true;
6249                         break;
6250                 }
6251
6252                 num_connectors++;
6253         }
6254
6255         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6256              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6257
6258         ok = ironlake_compute_clocks(crtc, &clock,
6259                                      &has_reduced_clock, &reduced_clock);
6260         if (!ok && !intel_crtc->config.clock_set) {
6261                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6262                 return -EINVAL;
6263         }
6264         /* Compat-code for transition, will disappear. */
6265         if (!intel_crtc->config.clock_set) {
6266                 intel_crtc->config.dpll.n = clock.n;
6267                 intel_crtc->config.dpll.m1 = clock.m1;
6268                 intel_crtc->config.dpll.m2 = clock.m2;
6269                 intel_crtc->config.dpll.p1 = clock.p1;
6270                 intel_crtc->config.dpll.p2 = clock.p2;
6271         }
6272
6273         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6274         if (intel_crtc->config.has_pch_encoder) {
6275                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6276                 if (has_reduced_clock)
6277                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6278
6279                 dpll = ironlake_compute_dpll(intel_crtc,
6280                                              &fp, &reduced_clock,
6281                                              has_reduced_clock ? &fp2 : NULL);
6282
6283                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6284                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6285                 if (has_reduced_clock)
6286                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6287                 else
6288                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6289
6290                 pll = intel_get_shared_dpll(intel_crtc);
6291                 if (pll == NULL) {
6292                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6293                                          pipe_name(pipe));
6294                         return -EINVAL;
6295                 }
6296         } else
6297                 intel_put_shared_dpll(intel_crtc);
6298
6299         if (intel_crtc->config.has_dp_encoder)
6300                 intel_dp_set_m_n(intel_crtc);
6301
6302         if (is_lvds && has_reduced_clock && i915_powersave)
6303                 intel_crtc->lowfreq_avail = true;
6304         else
6305                 intel_crtc->lowfreq_avail = false;
6306
6307         intel_set_pipe_timings(intel_crtc);
6308
6309         if (intel_crtc->config.has_pch_encoder) {
6310                 intel_cpu_transcoder_set_m_n(intel_crtc,
6311                                              &intel_crtc->config.fdi_m_n);
6312         }
6313
6314         ironlake_set_pipeconf(crtc);
6315
6316         /* Set up the display plane register */
6317         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6318         POSTING_READ(DSPCNTR(plane));
6319
6320         ret = intel_pipe_set_base(crtc, x, y, fb);
6321
6322         return ret;
6323 }
6324
6325 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6326                                          struct intel_link_m_n *m_n)
6327 {
6328         struct drm_device *dev = crtc->base.dev;
6329         struct drm_i915_private *dev_priv = dev->dev_private;
6330         enum pipe pipe = crtc->pipe;
6331
6332         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6333         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6334         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6335                 & ~TU_SIZE_MASK;
6336         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6337         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6338                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6339 }
6340
6341 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6342                                          enum transcoder transcoder,
6343                                          struct intel_link_m_n *m_n)
6344 {
6345         struct drm_device *dev = crtc->base.dev;
6346         struct drm_i915_private *dev_priv = dev->dev_private;
6347         enum pipe pipe = crtc->pipe;
6348
6349         if (INTEL_INFO(dev)->gen >= 5) {
6350                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6351                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6352                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6353                         & ~TU_SIZE_MASK;
6354                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6355                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6356                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6357         } else {
6358                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6359                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6360                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6361                         & ~TU_SIZE_MASK;
6362                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6363                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6364                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6365         }
6366 }
6367
6368 void intel_dp_get_m_n(struct intel_crtc *crtc,
6369                       struct intel_crtc_config *pipe_config)
6370 {
6371         if (crtc->config.has_pch_encoder)
6372                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6373         else
6374                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6375                                              &pipe_config->dp_m_n);
6376 }
6377
6378 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6379                                         struct intel_crtc_config *pipe_config)
6380 {
6381         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6382                                      &pipe_config->fdi_m_n);
6383 }
6384
6385 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6386                                      struct intel_crtc_config *pipe_config)
6387 {
6388         struct drm_device *dev = crtc->base.dev;
6389         struct drm_i915_private *dev_priv = dev->dev_private;
6390         uint32_t tmp;
6391
6392         tmp = I915_READ(PF_CTL(crtc->pipe));
6393
6394         if (tmp & PF_ENABLE) {
6395                 pipe_config->pch_pfit.enabled = true;
6396                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6397                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6398
6399                 /* We currently do not free assignements of panel fitters on
6400                  * ivb/hsw (since we don't use the higher upscaling modes which
6401                  * differentiates them) so just WARN about this case for now. */
6402                 if (IS_GEN7(dev)) {
6403                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6404                                 PF_PIPE_SEL_IVB(crtc->pipe));
6405                 }
6406         }
6407 }
6408
6409 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6410                                      struct intel_crtc_config *pipe_config)
6411 {
6412         struct drm_device *dev = crtc->base.dev;
6413         struct drm_i915_private *dev_priv = dev->dev_private;
6414         uint32_t tmp;
6415
6416         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6417         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6418
6419         tmp = I915_READ(PIPECONF(crtc->pipe));
6420         if (!(tmp & PIPECONF_ENABLE))
6421                 return false;
6422
6423         switch (tmp & PIPECONF_BPC_MASK) {
6424         case PIPECONF_6BPC:
6425                 pipe_config->pipe_bpp = 18;
6426                 break;
6427         case PIPECONF_8BPC:
6428                 pipe_config->pipe_bpp = 24;
6429                 break;
6430         case PIPECONF_10BPC:
6431                 pipe_config->pipe_bpp = 30;
6432                 break;
6433         case PIPECONF_12BPC:
6434                 pipe_config->pipe_bpp = 36;
6435                 break;
6436         default:
6437                 break;
6438         }
6439
6440         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6441                 struct intel_shared_dpll *pll;
6442
6443                 pipe_config->has_pch_encoder = true;
6444
6445                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6446                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6447                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6448
6449                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6450
6451                 if (HAS_PCH_IBX(dev_priv->dev)) {
6452                         pipe_config->shared_dpll =
6453                                 (enum intel_dpll_id) crtc->pipe;
6454                 } else {
6455                         tmp = I915_READ(PCH_DPLL_SEL);
6456                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6457                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6458                         else
6459                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6460                 }
6461
6462                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6463
6464                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6465                                            &pipe_config->dpll_hw_state));
6466
6467                 tmp = pipe_config->dpll_hw_state.dpll;
6468                 pipe_config->pixel_multiplier =
6469                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6470                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6471
6472                 ironlake_pch_clock_get(crtc, pipe_config);
6473         } else {
6474                 pipe_config->pixel_multiplier = 1;
6475         }
6476
6477         intel_get_pipe_timings(crtc, pipe_config);
6478
6479         ironlake_get_pfit_config(crtc, pipe_config);
6480
6481         return true;
6482 }
6483
6484 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6485 {
6486         struct drm_device *dev = dev_priv->dev;
6487         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6488         struct intel_crtc *crtc;
6489         unsigned long irqflags;
6490         uint32_t val;
6491
6492         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6493                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6494                      pipe_name(crtc->pipe));
6495
6496         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6497         WARN(plls->spll_refcount, "SPLL enabled\n");
6498         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6499         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6500         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6501         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6502              "CPU PWM1 enabled\n");
6503         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6504              "CPU PWM2 enabled\n");
6505         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6506              "PCH PWM1 enabled\n");
6507         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6508              "Utility pin enabled\n");
6509         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6510
6511         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6512         val = I915_READ(DEIMR);
6513         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6514              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6515         val = I915_READ(SDEIMR);
6516         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6517              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6518         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6519 }
6520
6521 /*
6522  * This function implements pieces of two sequences from BSpec:
6523  * - Sequence for display software to disable LCPLL
6524  * - Sequence for display software to allow package C8+
6525  * The steps implemented here are just the steps that actually touch the LCPLL
6526  * register. Callers should take care of disabling all the display engine
6527  * functions, doing the mode unset, fixing interrupts, etc.
6528  */
6529 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6530                               bool switch_to_fclk, bool allow_power_down)
6531 {
6532         uint32_t val;
6533
6534         assert_can_disable_lcpll(dev_priv);
6535
6536         val = I915_READ(LCPLL_CTL);
6537
6538         if (switch_to_fclk) {
6539                 val |= LCPLL_CD_SOURCE_FCLK;
6540                 I915_WRITE(LCPLL_CTL, val);
6541
6542                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6543                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6544                         DRM_ERROR("Switching to FCLK failed\n");
6545
6546                 val = I915_READ(LCPLL_CTL);
6547         }
6548
6549         val |= LCPLL_PLL_DISABLE;
6550         I915_WRITE(LCPLL_CTL, val);
6551         POSTING_READ(LCPLL_CTL);
6552
6553         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6554                 DRM_ERROR("LCPLL still locked\n");
6555
6556         val = I915_READ(D_COMP);
6557         val |= D_COMP_COMP_DISABLE;
6558         mutex_lock(&dev_priv->rps.hw_lock);
6559         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6560                 DRM_ERROR("Failed to disable D_COMP\n");
6561         mutex_unlock(&dev_priv->rps.hw_lock);
6562         POSTING_READ(D_COMP);
6563         ndelay(100);
6564
6565         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6566                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6567
6568         if (allow_power_down) {
6569                 val = I915_READ(LCPLL_CTL);
6570                 val |= LCPLL_POWER_DOWN_ALLOW;
6571                 I915_WRITE(LCPLL_CTL, val);
6572                 POSTING_READ(LCPLL_CTL);
6573         }
6574 }
6575
6576 /*
6577  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6578  * source.
6579  */
6580 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6581 {
6582         uint32_t val;
6583
6584         val = I915_READ(LCPLL_CTL);
6585
6586         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6587                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6588                 return;
6589
6590         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6591          * we'll hang the machine! */
6592         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6593
6594         if (val & LCPLL_POWER_DOWN_ALLOW) {
6595                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6596                 I915_WRITE(LCPLL_CTL, val);
6597                 POSTING_READ(LCPLL_CTL);
6598         }
6599
6600         val = I915_READ(D_COMP);
6601         val |= D_COMP_COMP_FORCE;
6602         val &= ~D_COMP_COMP_DISABLE;
6603         mutex_lock(&dev_priv->rps.hw_lock);
6604         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6605                 DRM_ERROR("Failed to enable D_COMP\n");
6606         mutex_unlock(&dev_priv->rps.hw_lock);
6607         POSTING_READ(D_COMP);
6608
6609         val = I915_READ(LCPLL_CTL);
6610         val &= ~LCPLL_PLL_DISABLE;
6611         I915_WRITE(LCPLL_CTL, val);
6612
6613         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6614                 DRM_ERROR("LCPLL not locked yet\n");
6615
6616         if (val & LCPLL_CD_SOURCE_FCLK) {
6617                 val = I915_READ(LCPLL_CTL);
6618                 val &= ~LCPLL_CD_SOURCE_FCLK;
6619                 I915_WRITE(LCPLL_CTL, val);
6620
6621                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6622                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6623                         DRM_ERROR("Switching back to LCPLL failed\n");
6624         }
6625
6626         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6627 }
6628
6629 void hsw_enable_pc8_work(struct work_struct *__work)
6630 {
6631         struct drm_i915_private *dev_priv =
6632                 container_of(to_delayed_work(__work), struct drm_i915_private,
6633                              pc8.enable_work);
6634         struct drm_device *dev = dev_priv->dev;
6635         uint32_t val;
6636
6637         if (dev_priv->pc8.enabled)
6638                 return;
6639
6640         DRM_DEBUG_KMS("Enabling package C8+\n");
6641
6642         dev_priv->pc8.enabled = true;
6643
6644         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6645                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6646                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6647                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6648         }
6649
6650         lpt_disable_clkout_dp(dev);
6651         hsw_pc8_disable_interrupts(dev);
6652         hsw_disable_lcpll(dev_priv, true, true);
6653 }
6654
6655 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6656 {
6657         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6658         WARN(dev_priv->pc8.disable_count < 1,
6659              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6660
6661         dev_priv->pc8.disable_count--;
6662         if (dev_priv->pc8.disable_count != 0)
6663                 return;
6664
6665         schedule_delayed_work(&dev_priv->pc8.enable_work,
6666                               msecs_to_jiffies(i915_pc8_timeout));
6667 }
6668
6669 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6670 {
6671         struct drm_device *dev = dev_priv->dev;
6672         uint32_t val;
6673
6674         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6675         WARN(dev_priv->pc8.disable_count < 0,
6676              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6677
6678         dev_priv->pc8.disable_count++;
6679         if (dev_priv->pc8.disable_count != 1)
6680                 return;
6681
6682         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6683         if (!dev_priv->pc8.enabled)
6684                 return;
6685
6686         DRM_DEBUG_KMS("Disabling package C8+\n");
6687
6688         hsw_restore_lcpll(dev_priv);
6689         hsw_pc8_restore_interrupts(dev);
6690         lpt_init_pch_refclk(dev);
6691
6692         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6693                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6694                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6695                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6696         }
6697
6698         intel_prepare_ddi(dev);
6699         i915_gem_init_swizzling(dev);
6700         mutex_lock(&dev_priv->rps.hw_lock);
6701         gen6_update_ring_freq(dev);
6702         mutex_unlock(&dev_priv->rps.hw_lock);
6703         dev_priv->pc8.enabled = false;
6704 }
6705
6706 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6707 {
6708         if (!HAS_PC8(dev_priv->dev))
6709                 return;
6710
6711         mutex_lock(&dev_priv->pc8.lock);
6712         __hsw_enable_package_c8(dev_priv);
6713         mutex_unlock(&dev_priv->pc8.lock);
6714 }
6715
6716 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6717 {
6718         if (!HAS_PC8(dev_priv->dev))
6719                 return;
6720
6721         mutex_lock(&dev_priv->pc8.lock);
6722         __hsw_disable_package_c8(dev_priv);
6723         mutex_unlock(&dev_priv->pc8.lock);
6724 }
6725
6726 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6727 {
6728         struct drm_device *dev = dev_priv->dev;
6729         struct intel_crtc *crtc;
6730         uint32_t val;
6731
6732         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6733                 if (crtc->base.enabled)
6734                         return false;
6735
6736         /* This case is still possible since we have the i915.disable_power_well
6737          * parameter and also the KVMr or something else might be requesting the
6738          * power well. */
6739         val = I915_READ(HSW_PWR_WELL_DRIVER);
6740         if (val != 0) {
6741                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6742                 return false;
6743         }
6744
6745         return true;
6746 }
6747
6748 /* Since we're called from modeset_global_resources there's no way to
6749  * symmetrically increase and decrease the refcount, so we use
6750  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6751  * or not.
6752  */
6753 static void hsw_update_package_c8(struct drm_device *dev)
6754 {
6755         struct drm_i915_private *dev_priv = dev->dev_private;
6756         bool allow;
6757
6758         if (!HAS_PC8(dev_priv->dev))
6759                 return;
6760
6761         if (!i915_enable_pc8)
6762                 return;
6763
6764         mutex_lock(&dev_priv->pc8.lock);
6765
6766         allow = hsw_can_enable_package_c8(dev_priv);
6767
6768         if (allow == dev_priv->pc8.requirements_met)
6769                 goto done;
6770
6771         dev_priv->pc8.requirements_met = allow;
6772
6773         if (allow)
6774                 __hsw_enable_package_c8(dev_priv);
6775         else
6776                 __hsw_disable_package_c8(dev_priv);
6777
6778 done:
6779         mutex_unlock(&dev_priv->pc8.lock);
6780 }
6781
6782 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6783 {
6784         if (!HAS_PC8(dev_priv->dev))
6785                 return;
6786
6787         mutex_lock(&dev_priv->pc8.lock);
6788         if (!dev_priv->pc8.gpu_idle) {
6789                 dev_priv->pc8.gpu_idle = true;
6790                 __hsw_enable_package_c8(dev_priv);
6791         }
6792         mutex_unlock(&dev_priv->pc8.lock);
6793 }
6794
6795 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6796 {
6797         if (!HAS_PC8(dev_priv->dev))
6798                 return;
6799
6800         mutex_lock(&dev_priv->pc8.lock);
6801         if (dev_priv->pc8.gpu_idle) {
6802                 dev_priv->pc8.gpu_idle = false;
6803                 __hsw_disable_package_c8(dev_priv);
6804         }
6805         mutex_unlock(&dev_priv->pc8.lock);
6806 }
6807
6808 #define for_each_power_domain(domain, mask)                             \
6809         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6810                 if ((1 << (domain)) & (mask))
6811
6812 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6813                                             enum pipe pipe, bool pfit_enabled)
6814 {
6815         unsigned long mask;
6816         enum transcoder transcoder;
6817
6818         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6819
6820         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6821         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6822         if (pfit_enabled)
6823                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6824
6825         return mask;
6826 }
6827
6828 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6829 {
6830         struct drm_i915_private *dev_priv = dev->dev_private;
6831
6832         if (dev_priv->power_domains.init_power_on == enable)
6833                 return;
6834
6835         if (enable)
6836                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6837         else
6838                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6839
6840         dev_priv->power_domains.init_power_on = enable;
6841 }
6842
6843 static void modeset_update_power_wells(struct drm_device *dev)
6844 {
6845         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6846         struct intel_crtc *crtc;
6847
6848         /*
6849          * First get all needed power domains, then put all unneeded, to avoid
6850          * any unnecessary toggling of the power wells.
6851          */
6852         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6853                 enum intel_display_power_domain domain;
6854
6855                 if (!crtc->base.enabled)
6856                         continue;
6857
6858                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6859                                                 crtc->pipe,
6860                                                 crtc->config.pch_pfit.enabled);
6861
6862                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6863                         intel_display_power_get(dev, domain);
6864         }
6865
6866         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6867                 enum intel_display_power_domain domain;
6868
6869                 for_each_power_domain(domain, crtc->enabled_power_domains)
6870                         intel_display_power_put(dev, domain);
6871
6872                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6873         }
6874
6875         intel_display_set_init_power(dev, false);
6876 }
6877
6878 static void haswell_modeset_global_resources(struct drm_device *dev)
6879 {
6880         modeset_update_power_wells(dev);
6881         hsw_update_package_c8(dev);
6882 }
6883
6884 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6885                                  int x, int y,
6886                                  struct drm_framebuffer *fb)
6887 {
6888         struct drm_device *dev = crtc->dev;
6889         struct drm_i915_private *dev_priv = dev->dev_private;
6890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6891         int plane = intel_crtc->plane;
6892         int ret;
6893
6894         if (!intel_ddi_pll_mode_set(crtc))
6895                 return -EINVAL;
6896
6897         if (intel_crtc->config.has_dp_encoder)
6898                 intel_dp_set_m_n(intel_crtc);
6899
6900         intel_crtc->lowfreq_avail = false;
6901
6902         intel_set_pipe_timings(intel_crtc);
6903
6904         if (intel_crtc->config.has_pch_encoder) {
6905                 intel_cpu_transcoder_set_m_n(intel_crtc,
6906                                              &intel_crtc->config.fdi_m_n);
6907         }
6908
6909         haswell_set_pipeconf(crtc);
6910
6911         intel_set_pipe_csc(crtc);
6912
6913         /* Set up the display plane register */
6914         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6915         POSTING_READ(DSPCNTR(plane));
6916
6917         ret = intel_pipe_set_base(crtc, x, y, fb);
6918
6919         return ret;
6920 }
6921
6922 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6923                                     struct intel_crtc_config *pipe_config)
6924 {
6925         struct drm_device *dev = crtc->base.dev;
6926         struct drm_i915_private *dev_priv = dev->dev_private;
6927         enum intel_display_power_domain pfit_domain;
6928         uint32_t tmp;
6929
6930         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6931         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6932
6933         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6934         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6935                 enum pipe trans_edp_pipe;
6936                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6937                 default:
6938                         WARN(1, "unknown pipe linked to edp transcoder\n");
6939                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6940                 case TRANS_DDI_EDP_INPUT_A_ON:
6941                         trans_edp_pipe = PIPE_A;
6942                         break;
6943                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6944                         trans_edp_pipe = PIPE_B;
6945                         break;
6946                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6947                         trans_edp_pipe = PIPE_C;
6948                         break;
6949                 }
6950
6951                 if (trans_edp_pipe == crtc->pipe)
6952                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6953         }
6954
6955         if (!intel_display_power_enabled(dev,
6956                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6957                 return false;
6958
6959         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6960         if (!(tmp & PIPECONF_ENABLE))
6961                 return false;
6962
6963         /*
6964          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6965          * DDI E. So just check whether this pipe is wired to DDI E and whether
6966          * the PCH transcoder is on.
6967          */
6968         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6969         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6970             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6971                 pipe_config->has_pch_encoder = true;
6972
6973                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6974                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6975                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6976
6977                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6978         }
6979
6980         intel_get_pipe_timings(crtc, pipe_config);
6981
6982         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6983         if (intel_display_power_enabled(dev, pfit_domain))
6984                 ironlake_get_pfit_config(crtc, pipe_config);
6985
6986         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6987                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6988
6989         pipe_config->pixel_multiplier = 1;
6990
6991         return true;
6992 }
6993
6994 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6995                                int x, int y,
6996                                struct drm_framebuffer *fb)
6997 {
6998         struct drm_device *dev = crtc->dev;
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000         struct intel_encoder *encoder;
7001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7003         int pipe = intel_crtc->pipe;
7004         int ret;
7005
7006         drm_vblank_pre_modeset(dev, pipe);
7007
7008         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7009
7010         drm_vblank_post_modeset(dev, pipe);
7011
7012         if (ret != 0)
7013                 return ret;
7014
7015         for_each_encoder_on_crtc(dev, crtc, encoder) {
7016                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7017                         encoder->base.base.id,
7018                         drm_get_encoder_name(&encoder->base),
7019                         mode->base.id, mode->name);
7020                 encoder->mode_set(encoder);
7021         }
7022
7023         return 0;
7024 }
7025
7026 static struct {
7027         int clock;
7028         u32 config;
7029 } hdmi_audio_clock[] = {
7030         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7031         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7032         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7033         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7034         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7035         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7036         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7037         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7038         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7039         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7040 };
7041
7042 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7043 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7044 {
7045         int i;
7046
7047         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7048                 if (mode->clock == hdmi_audio_clock[i].clock)
7049                         break;
7050         }
7051
7052         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7053                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7054                 i = 1;
7055         }
7056
7057         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7058                       hdmi_audio_clock[i].clock,
7059                       hdmi_audio_clock[i].config);
7060
7061         return hdmi_audio_clock[i].config;
7062 }
7063
7064 static bool intel_eld_uptodate(struct drm_connector *connector,
7065                                int reg_eldv, uint32_t bits_eldv,
7066                                int reg_elda, uint32_t bits_elda,
7067                                int reg_edid)
7068 {
7069         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7070         uint8_t *eld = connector->eld;
7071         uint32_t i;
7072
7073         i = I915_READ(reg_eldv);
7074         i &= bits_eldv;
7075
7076         if (!eld[0])
7077                 return !i;
7078
7079         if (!i)
7080                 return false;
7081
7082         i = I915_READ(reg_elda);
7083         i &= ~bits_elda;
7084         I915_WRITE(reg_elda, i);
7085
7086         for (i = 0; i < eld[2]; i++)
7087                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7088                         return false;
7089
7090         return true;
7091 }
7092
7093 static void g4x_write_eld(struct drm_connector *connector,
7094                           struct drm_crtc *crtc,
7095                           struct drm_display_mode *mode)
7096 {
7097         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7098         uint8_t *eld = connector->eld;
7099         uint32_t eldv;
7100         uint32_t len;
7101         uint32_t i;
7102
7103         i = I915_READ(G4X_AUD_VID_DID);
7104
7105         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7106                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7107         else
7108                 eldv = G4X_ELDV_DEVCTG;
7109
7110         if (intel_eld_uptodate(connector,
7111                                G4X_AUD_CNTL_ST, eldv,
7112                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7113                                G4X_HDMIW_HDMIEDID))
7114                 return;
7115
7116         i = I915_READ(G4X_AUD_CNTL_ST);
7117         i &= ~(eldv | G4X_ELD_ADDR);
7118         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7119         I915_WRITE(G4X_AUD_CNTL_ST, i);
7120
7121         if (!eld[0])
7122                 return;
7123
7124         len = min_t(uint8_t, eld[2], len);
7125         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7126         for (i = 0; i < len; i++)
7127                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7128
7129         i = I915_READ(G4X_AUD_CNTL_ST);
7130         i |= eldv;
7131         I915_WRITE(G4X_AUD_CNTL_ST, i);
7132 }
7133
7134 static void haswell_write_eld(struct drm_connector *connector,
7135                               struct drm_crtc *crtc,
7136                               struct drm_display_mode *mode)
7137 {
7138         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7139         uint8_t *eld = connector->eld;
7140         struct drm_device *dev = crtc->dev;
7141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7142         uint32_t eldv;
7143         uint32_t i;
7144         int len;
7145         int pipe = to_intel_crtc(crtc)->pipe;
7146         int tmp;
7147
7148         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7149         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7150         int aud_config = HSW_AUD_CFG(pipe);
7151         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7152
7153
7154         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7155
7156         /* Audio output enable */
7157         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7158         tmp = I915_READ(aud_cntrl_st2);
7159         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7160         I915_WRITE(aud_cntrl_st2, tmp);
7161
7162         /* Wait for 1 vertical blank */
7163         intel_wait_for_vblank(dev, pipe);
7164
7165         /* Set ELD valid state */
7166         tmp = I915_READ(aud_cntrl_st2);
7167         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7168         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7169         I915_WRITE(aud_cntrl_st2, tmp);
7170         tmp = I915_READ(aud_cntrl_st2);
7171         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7172
7173         /* Enable HDMI mode */
7174         tmp = I915_READ(aud_config);
7175         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7176         /* clear N_programing_enable and N_value_index */
7177         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7178         I915_WRITE(aud_config, tmp);
7179
7180         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7181
7182         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7183         intel_crtc->eld_vld = true;
7184
7185         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7186                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7187                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7188                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7189         } else {
7190                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7191         }
7192
7193         if (intel_eld_uptodate(connector,
7194                                aud_cntrl_st2, eldv,
7195                                aud_cntl_st, IBX_ELD_ADDRESS,
7196                                hdmiw_hdmiedid))
7197                 return;
7198
7199         i = I915_READ(aud_cntrl_st2);
7200         i &= ~eldv;
7201         I915_WRITE(aud_cntrl_st2, i);
7202
7203         if (!eld[0])
7204                 return;
7205
7206         i = I915_READ(aud_cntl_st);
7207         i &= ~IBX_ELD_ADDRESS;
7208         I915_WRITE(aud_cntl_st, i);
7209         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7210         DRM_DEBUG_DRIVER("port num:%d\n", i);
7211
7212         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7213         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7214         for (i = 0; i < len; i++)
7215                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7216
7217         i = I915_READ(aud_cntrl_st2);
7218         i |= eldv;
7219         I915_WRITE(aud_cntrl_st2, i);
7220
7221 }
7222
7223 static void ironlake_write_eld(struct drm_connector *connector,
7224                                struct drm_crtc *crtc,
7225                                struct drm_display_mode *mode)
7226 {
7227         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7228         uint8_t *eld = connector->eld;
7229         uint32_t eldv;
7230         uint32_t i;
7231         int len;
7232         int hdmiw_hdmiedid;
7233         int aud_config;
7234         int aud_cntl_st;
7235         int aud_cntrl_st2;
7236         int pipe = to_intel_crtc(crtc)->pipe;
7237
7238         if (HAS_PCH_IBX(connector->dev)) {
7239                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7240                 aud_config = IBX_AUD_CFG(pipe);
7241                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7242                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7243         } else if (IS_VALLEYVIEW(connector->dev)) {
7244                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7245                 aud_config = VLV_AUD_CFG(pipe);
7246                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7247                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7248         } else {
7249                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7250                 aud_config = CPT_AUD_CFG(pipe);
7251                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7252                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7253         }
7254
7255         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7256
7257         if (IS_VALLEYVIEW(connector->dev))  {
7258                 struct intel_encoder *intel_encoder;
7259                 struct intel_digital_port *intel_dig_port;
7260
7261                 intel_encoder = intel_attached_encoder(connector);
7262                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7263                 i = intel_dig_port->port;
7264         } else {
7265                 i = I915_READ(aud_cntl_st);
7266                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7267                 /* DIP_Port_Select, 0x1 = PortB */
7268         }
7269
7270         if (!i) {
7271                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7272                 /* operate blindly on all ports */
7273                 eldv = IBX_ELD_VALIDB;
7274                 eldv |= IBX_ELD_VALIDB << 4;
7275                 eldv |= IBX_ELD_VALIDB << 8;
7276         } else {
7277                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7278                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7279         }
7280
7281         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7282                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7283                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7284                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7285         } else {
7286                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7287         }
7288
7289         if (intel_eld_uptodate(connector,
7290                                aud_cntrl_st2, eldv,
7291                                aud_cntl_st, IBX_ELD_ADDRESS,
7292                                hdmiw_hdmiedid))
7293                 return;
7294
7295         i = I915_READ(aud_cntrl_st2);
7296         i &= ~eldv;
7297         I915_WRITE(aud_cntrl_st2, i);
7298
7299         if (!eld[0])
7300                 return;
7301
7302         i = I915_READ(aud_cntl_st);
7303         i &= ~IBX_ELD_ADDRESS;
7304         I915_WRITE(aud_cntl_st, i);
7305
7306         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7307         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7308         for (i = 0; i < len; i++)
7309                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7310
7311         i = I915_READ(aud_cntrl_st2);
7312         i |= eldv;
7313         I915_WRITE(aud_cntrl_st2, i);
7314 }
7315
7316 void intel_write_eld(struct drm_encoder *encoder,
7317                      struct drm_display_mode *mode)
7318 {
7319         struct drm_crtc *crtc = encoder->crtc;
7320         struct drm_connector *connector;
7321         struct drm_device *dev = encoder->dev;
7322         struct drm_i915_private *dev_priv = dev->dev_private;
7323
7324         connector = drm_select_eld(encoder, mode);
7325         if (!connector)
7326                 return;
7327
7328         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7329                          connector->base.id,
7330                          drm_get_connector_name(connector),
7331                          connector->encoder->base.id,
7332                          drm_get_encoder_name(connector->encoder));
7333
7334         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7335
7336         if (dev_priv->display.write_eld)
7337                 dev_priv->display.write_eld(connector, crtc, mode);
7338 }
7339
7340 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7341 {
7342         struct drm_device *dev = crtc->dev;
7343         struct drm_i915_private *dev_priv = dev->dev_private;
7344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7345         bool visible = base != 0;
7346         u32 cntl;
7347
7348         if (intel_crtc->cursor_visible == visible)
7349                 return;
7350
7351         cntl = I915_READ(_CURACNTR);
7352         if (visible) {
7353                 /* On these chipsets we can only modify the base whilst
7354                  * the cursor is disabled.
7355                  */
7356                 I915_WRITE(_CURABASE, base);
7357
7358                 cntl &= ~(CURSOR_FORMAT_MASK);
7359                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7360                 cntl |= CURSOR_ENABLE |
7361                         CURSOR_GAMMA_ENABLE |
7362                         CURSOR_FORMAT_ARGB;
7363         } else
7364                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7365         I915_WRITE(_CURACNTR, cntl);
7366
7367         intel_crtc->cursor_visible = visible;
7368 }
7369
7370 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7371 {
7372         struct drm_device *dev = crtc->dev;
7373         struct drm_i915_private *dev_priv = dev->dev_private;
7374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7375         int pipe = intel_crtc->pipe;
7376         bool visible = base != 0;
7377
7378         if (intel_crtc->cursor_visible != visible) {
7379                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7380                 if (base) {
7381                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7382                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7383                         cntl |= pipe << 28; /* Connect to correct pipe */
7384                 } else {
7385                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7386                         cntl |= CURSOR_MODE_DISABLE;
7387                 }
7388                 I915_WRITE(CURCNTR(pipe), cntl);
7389
7390                 intel_crtc->cursor_visible = visible;
7391         }
7392         /* and commit changes on next vblank */
7393         POSTING_READ(CURCNTR(pipe));
7394         I915_WRITE(CURBASE(pipe), base);
7395         POSTING_READ(CURBASE(pipe));
7396 }
7397
7398 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7399 {
7400         struct drm_device *dev = crtc->dev;
7401         struct drm_i915_private *dev_priv = dev->dev_private;
7402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403         int pipe = intel_crtc->pipe;
7404         bool visible = base != 0;
7405
7406         if (intel_crtc->cursor_visible != visible) {
7407                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7408                 if (base) {
7409                         cntl &= ~CURSOR_MODE;
7410                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7411                 } else {
7412                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7413                         cntl |= CURSOR_MODE_DISABLE;
7414                 }
7415                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7416                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7417                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7418                 }
7419                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7420
7421                 intel_crtc->cursor_visible = visible;
7422         }
7423         /* and commit changes on next vblank */
7424         POSTING_READ(CURCNTR_IVB(pipe));
7425         I915_WRITE(CURBASE_IVB(pipe), base);
7426         POSTING_READ(CURBASE_IVB(pipe));
7427 }
7428
7429 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7430 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7431                                      bool on)
7432 {
7433         struct drm_device *dev = crtc->dev;
7434         struct drm_i915_private *dev_priv = dev->dev_private;
7435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7436         int pipe = intel_crtc->pipe;
7437         int x = intel_crtc->cursor_x;
7438         int y = intel_crtc->cursor_y;
7439         u32 base = 0, pos = 0;
7440         bool visible;
7441
7442         if (on)
7443                 base = intel_crtc->cursor_addr;
7444
7445         if (x >= intel_crtc->config.pipe_src_w)
7446                 base = 0;
7447
7448         if (y >= intel_crtc->config.pipe_src_h)
7449                 base = 0;
7450
7451         if (x < 0) {
7452                 if (x + intel_crtc->cursor_width <= 0)
7453                         base = 0;
7454
7455                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7456                 x = -x;
7457         }
7458         pos |= x << CURSOR_X_SHIFT;
7459
7460         if (y < 0) {
7461                 if (y + intel_crtc->cursor_height <= 0)
7462                         base = 0;
7463
7464                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7465                 y = -y;
7466         }
7467         pos |= y << CURSOR_Y_SHIFT;
7468
7469         visible = base != 0;
7470         if (!visible && !intel_crtc->cursor_visible)
7471                 return;
7472
7473         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7474                 I915_WRITE(CURPOS_IVB(pipe), pos);
7475                 ivb_update_cursor(crtc, base);
7476         } else {
7477                 I915_WRITE(CURPOS(pipe), pos);
7478                 if (IS_845G(dev) || IS_I865G(dev))
7479                         i845_update_cursor(crtc, base);
7480                 else
7481                         i9xx_update_cursor(crtc, base);
7482         }
7483 }
7484
7485 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7486                                  struct drm_file *file,
7487                                  uint32_t handle,
7488                                  uint32_t width, uint32_t height)
7489 {
7490         struct drm_device *dev = crtc->dev;
7491         struct drm_i915_private *dev_priv = dev->dev_private;
7492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7493         struct drm_i915_gem_object *obj;
7494         uint32_t addr;
7495         int ret;
7496
7497         /* if we want to turn off the cursor ignore width and height */
7498         if (!handle) {
7499                 DRM_DEBUG_KMS("cursor off\n");
7500                 addr = 0;
7501                 obj = NULL;
7502                 mutex_lock(&dev->struct_mutex);
7503                 goto finish;
7504         }
7505
7506         /* Currently we only support 64x64 cursors */
7507         if (width != 64 || height != 64) {
7508                 DRM_ERROR("we currently only support 64x64 cursors\n");
7509                 return -EINVAL;
7510         }
7511
7512         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7513         if (&obj->base == NULL)
7514                 return -ENOENT;
7515
7516         if (obj->base.size < width * height * 4) {
7517                 DRM_ERROR("buffer is to small\n");
7518                 ret = -ENOMEM;
7519                 goto fail;
7520         }
7521
7522         /* we only need to pin inside GTT if cursor is non-phy */
7523         mutex_lock(&dev->struct_mutex);
7524         if (!dev_priv->info->cursor_needs_physical) {
7525                 unsigned alignment;
7526
7527                 if (obj->tiling_mode) {
7528                         DRM_ERROR("cursor cannot be tiled\n");
7529                         ret = -EINVAL;
7530                         goto fail_locked;
7531                 }
7532
7533                 /* Note that the w/a also requires 2 PTE of padding following
7534                  * the bo. We currently fill all unused PTE with the shadow
7535                  * page and so we should always have valid PTE following the
7536                  * cursor preventing the VT-d warning.
7537                  */
7538                 alignment = 0;
7539                 if (need_vtd_wa(dev))
7540                         alignment = 64*1024;
7541
7542                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7543                 if (ret) {
7544                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7545                         goto fail_locked;
7546                 }
7547
7548                 ret = i915_gem_object_put_fence(obj);
7549                 if (ret) {
7550                         DRM_ERROR("failed to release fence for cursor");
7551                         goto fail_unpin;
7552                 }
7553
7554                 addr = i915_gem_obj_ggtt_offset(obj);
7555         } else {
7556                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7557                 ret = i915_gem_attach_phys_object(dev, obj,
7558                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7559                                                   align);
7560                 if (ret) {
7561                         DRM_ERROR("failed to attach phys object\n");
7562                         goto fail_locked;
7563                 }
7564                 addr = obj->phys_obj->handle->busaddr;
7565         }
7566
7567         if (IS_GEN2(dev))
7568                 I915_WRITE(CURSIZE, (height << 12) | width);
7569
7570  finish:
7571         if (intel_crtc->cursor_bo) {
7572                 if (dev_priv->info->cursor_needs_physical) {
7573                         if (intel_crtc->cursor_bo != obj)
7574                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7575                 } else
7576                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7577                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7578         }
7579
7580         mutex_unlock(&dev->struct_mutex);
7581
7582         intel_crtc->cursor_addr = addr;
7583         intel_crtc->cursor_bo = obj;
7584         intel_crtc->cursor_width = width;
7585         intel_crtc->cursor_height = height;
7586
7587         if (intel_crtc->active)
7588                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7589
7590         return 0;
7591 fail_unpin:
7592         i915_gem_object_unpin_from_display_plane(obj);
7593 fail_locked:
7594         mutex_unlock(&dev->struct_mutex);
7595 fail:
7596         drm_gem_object_unreference_unlocked(&obj->base);
7597         return ret;
7598 }
7599
7600 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7601 {
7602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7603
7604         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7605         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7606
7607         if (intel_crtc->active)
7608                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7609
7610         return 0;
7611 }
7612
7613 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7614                                  u16 *blue, uint32_t start, uint32_t size)
7615 {
7616         int end = (start + size > 256) ? 256 : start + size, i;
7617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7618
7619         for (i = start; i < end; i++) {
7620                 intel_crtc->lut_r[i] = red[i] >> 8;
7621                 intel_crtc->lut_g[i] = green[i] >> 8;
7622                 intel_crtc->lut_b[i] = blue[i] >> 8;
7623         }
7624
7625         intel_crtc_load_lut(crtc);
7626 }
7627
7628 /* VESA 640x480x72Hz mode to set on the pipe */
7629 static struct drm_display_mode load_detect_mode = {
7630         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7631                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7632 };
7633
7634 static struct drm_framebuffer *
7635 intel_framebuffer_create(struct drm_device *dev,
7636                          struct drm_mode_fb_cmd2 *mode_cmd,
7637                          struct drm_i915_gem_object *obj)
7638 {
7639         struct intel_framebuffer *intel_fb;
7640         int ret;
7641
7642         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7643         if (!intel_fb) {
7644                 drm_gem_object_unreference_unlocked(&obj->base);
7645                 return ERR_PTR(-ENOMEM);
7646         }
7647
7648         ret = i915_mutex_lock_interruptible(dev);
7649         if (ret)
7650                 goto err;
7651
7652         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7653         mutex_unlock(&dev->struct_mutex);
7654         if (ret)
7655                 goto err;
7656
7657         return &intel_fb->base;
7658 err:
7659         drm_gem_object_unreference_unlocked(&obj->base);
7660         kfree(intel_fb);
7661
7662         return ERR_PTR(ret);
7663 }
7664
7665 static u32
7666 intel_framebuffer_pitch_for_width(int width, int bpp)
7667 {
7668         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7669         return ALIGN(pitch, 64);
7670 }
7671
7672 static u32
7673 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7674 {
7675         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7676         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7677 }
7678
7679 static struct drm_framebuffer *
7680 intel_framebuffer_create_for_mode(struct drm_device *dev,
7681                                   struct drm_display_mode *mode,
7682                                   int depth, int bpp)
7683 {
7684         struct drm_i915_gem_object *obj;
7685         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7686
7687         obj = i915_gem_alloc_object(dev,
7688                                     intel_framebuffer_size_for_mode(mode, bpp));
7689         if (obj == NULL)
7690                 return ERR_PTR(-ENOMEM);
7691
7692         mode_cmd.width = mode->hdisplay;
7693         mode_cmd.height = mode->vdisplay;
7694         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7695                                                                 bpp);
7696         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7697
7698         return intel_framebuffer_create(dev, &mode_cmd, obj);
7699 }
7700
7701 static struct drm_framebuffer *
7702 mode_fits_in_fbdev(struct drm_device *dev,
7703                    struct drm_display_mode *mode)
7704 {
7705 #ifdef CONFIG_DRM_I915_FBDEV
7706         struct drm_i915_private *dev_priv = dev->dev_private;
7707         struct drm_i915_gem_object *obj;
7708         struct drm_framebuffer *fb;
7709
7710         if (dev_priv->fbdev == NULL)
7711                 return NULL;
7712
7713         obj = dev_priv->fbdev->ifb.obj;
7714         if (obj == NULL)
7715                 return NULL;
7716
7717         fb = &dev_priv->fbdev->ifb.base;
7718         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7719                                                                fb->bits_per_pixel))
7720                 return NULL;
7721
7722         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7723                 return NULL;
7724
7725         return fb;
7726 #else
7727         return NULL;
7728 #endif
7729 }
7730
7731 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7732                                 struct drm_display_mode *mode,
7733                                 struct intel_load_detect_pipe *old)
7734 {
7735         struct intel_crtc *intel_crtc;
7736         struct intel_encoder *intel_encoder =
7737                 intel_attached_encoder(connector);
7738         struct drm_crtc *possible_crtc;
7739         struct drm_encoder *encoder = &intel_encoder->base;
7740         struct drm_crtc *crtc = NULL;
7741         struct drm_device *dev = encoder->dev;
7742         struct drm_framebuffer *fb;
7743         int i = -1;
7744
7745         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7746                       connector->base.id, drm_get_connector_name(connector),
7747                       encoder->base.id, drm_get_encoder_name(encoder));
7748
7749         /*
7750          * Algorithm gets a little messy:
7751          *
7752          *   - if the connector already has an assigned crtc, use it (but make
7753          *     sure it's on first)
7754          *
7755          *   - try to find the first unused crtc that can drive this connector,
7756          *     and use that if we find one
7757          */
7758
7759         /* See if we already have a CRTC for this connector */
7760         if (encoder->crtc) {
7761                 crtc = encoder->crtc;
7762
7763                 mutex_lock(&crtc->mutex);
7764
7765                 old->dpms_mode = connector->dpms;
7766                 old->load_detect_temp = false;
7767
7768                 /* Make sure the crtc and connector are running */
7769                 if (connector->dpms != DRM_MODE_DPMS_ON)
7770                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7771
7772                 return true;
7773         }
7774
7775         /* Find an unused one (if possible) */
7776         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7777                 i++;
7778                 if (!(encoder->possible_crtcs & (1 << i)))
7779                         continue;
7780                 if (!possible_crtc->enabled) {
7781                         crtc = possible_crtc;
7782                         break;
7783                 }
7784         }
7785
7786         /*
7787          * If we didn't find an unused CRTC, don't use any.
7788          */
7789         if (!crtc) {
7790                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7791                 return false;
7792         }
7793
7794         mutex_lock(&crtc->mutex);
7795         intel_encoder->new_crtc = to_intel_crtc(crtc);
7796         to_intel_connector(connector)->new_encoder = intel_encoder;
7797
7798         intel_crtc = to_intel_crtc(crtc);
7799         old->dpms_mode = connector->dpms;
7800         old->load_detect_temp = true;
7801         old->release_fb = NULL;
7802
7803         if (!mode)
7804                 mode = &load_detect_mode;
7805
7806         /* We need a framebuffer large enough to accommodate all accesses
7807          * that the plane may generate whilst we perform load detection.
7808          * We can not rely on the fbcon either being present (we get called
7809          * during its initialisation to detect all boot displays, or it may
7810          * not even exist) or that it is large enough to satisfy the
7811          * requested mode.
7812          */
7813         fb = mode_fits_in_fbdev(dev, mode);
7814         if (fb == NULL) {
7815                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7816                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7817                 old->release_fb = fb;
7818         } else
7819                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7820         if (IS_ERR(fb)) {
7821                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7822                 mutex_unlock(&crtc->mutex);
7823                 return false;
7824         }
7825
7826         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7827                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7828                 if (old->release_fb)
7829                         old->release_fb->funcs->destroy(old->release_fb);
7830                 mutex_unlock(&crtc->mutex);
7831                 return false;
7832         }
7833
7834         /* let the connector get through one full cycle before testing */
7835         intel_wait_for_vblank(dev, intel_crtc->pipe);
7836         return true;
7837 }
7838
7839 void intel_release_load_detect_pipe(struct drm_connector *connector,
7840                                     struct intel_load_detect_pipe *old)
7841 {
7842         struct intel_encoder *intel_encoder =
7843                 intel_attached_encoder(connector);
7844         struct drm_encoder *encoder = &intel_encoder->base;
7845         struct drm_crtc *crtc = encoder->crtc;
7846
7847         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7848                       connector->base.id, drm_get_connector_name(connector),
7849                       encoder->base.id, drm_get_encoder_name(encoder));
7850
7851         if (old->load_detect_temp) {
7852                 to_intel_connector(connector)->new_encoder = NULL;
7853                 intel_encoder->new_crtc = NULL;
7854                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7855
7856                 if (old->release_fb) {
7857                         drm_framebuffer_unregister_private(old->release_fb);
7858                         drm_framebuffer_unreference(old->release_fb);
7859                 }
7860
7861                 mutex_unlock(&crtc->mutex);
7862                 return;
7863         }
7864
7865         /* Switch crtc and encoder back off if necessary */
7866         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7867                 connector->funcs->dpms(connector, old->dpms_mode);
7868
7869         mutex_unlock(&crtc->mutex);
7870 }
7871
7872 static int i9xx_pll_refclk(struct drm_device *dev,
7873                            const struct intel_crtc_config *pipe_config)
7874 {
7875         struct drm_i915_private *dev_priv = dev->dev_private;
7876         u32 dpll = pipe_config->dpll_hw_state.dpll;
7877
7878         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7879                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7880         else if (HAS_PCH_SPLIT(dev))
7881                 return 120000;
7882         else if (!IS_GEN2(dev))
7883                 return 96000;
7884         else
7885                 return 48000;
7886 }
7887
7888 /* Returns the clock of the currently programmed mode of the given pipe. */
7889 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7890                                 struct intel_crtc_config *pipe_config)
7891 {
7892         struct drm_device *dev = crtc->base.dev;
7893         struct drm_i915_private *dev_priv = dev->dev_private;
7894         int pipe = pipe_config->cpu_transcoder;
7895         u32 dpll = pipe_config->dpll_hw_state.dpll;
7896         u32 fp;
7897         intel_clock_t clock;
7898         int refclk = i9xx_pll_refclk(dev, pipe_config);
7899
7900         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7901                 fp = pipe_config->dpll_hw_state.fp0;
7902         else
7903                 fp = pipe_config->dpll_hw_state.fp1;
7904
7905         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7906         if (IS_PINEVIEW(dev)) {
7907                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7908                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7909         } else {
7910                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7911                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7912         }
7913
7914         if (!IS_GEN2(dev)) {
7915                 if (IS_PINEVIEW(dev))
7916                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7917                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7918                 else
7919                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7920                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7921
7922                 switch (dpll & DPLL_MODE_MASK) {
7923                 case DPLLB_MODE_DAC_SERIAL:
7924                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7925                                 5 : 10;
7926                         break;
7927                 case DPLLB_MODE_LVDS:
7928                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7929                                 7 : 14;
7930                         break;
7931                 default:
7932                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7933                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7934                         return;
7935                 }
7936
7937                 if (IS_PINEVIEW(dev))
7938                         pineview_clock(refclk, &clock);
7939                 else
7940                         i9xx_clock(refclk, &clock);
7941         } else {
7942                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7943
7944                 if (is_lvds) {
7945                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7946                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7947                         clock.p2 = 14;
7948                 } else {
7949                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7950                                 clock.p1 = 2;
7951                         else {
7952                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7953                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7954                         }
7955                         if (dpll & PLL_P2_DIVIDE_BY_4)
7956                                 clock.p2 = 4;
7957                         else
7958                                 clock.p2 = 2;
7959                 }
7960
7961                 i9xx_clock(refclk, &clock);
7962         }
7963
7964         /*
7965          * This value includes pixel_multiplier. We will use
7966          * port_clock to compute adjusted_mode.crtc_clock in the
7967          * encoder's get_config() function.
7968          */
7969         pipe_config->port_clock = clock.dot;
7970 }
7971
7972 int intel_dotclock_calculate(int link_freq,
7973                              const struct intel_link_m_n *m_n)
7974 {
7975         /*
7976          * The calculation for the data clock is:
7977          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7978          * But we want to avoid losing precison if possible, so:
7979          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7980          *
7981          * and the link clock is simpler:
7982          * link_clock = (m * link_clock) / n
7983          */
7984
7985         if (!m_n->link_n)
7986                 return 0;
7987
7988         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7989 }
7990
7991 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7992                                    struct intel_crtc_config *pipe_config)
7993 {
7994         struct drm_device *dev = crtc->base.dev;
7995
7996         /* read out port_clock from the DPLL */
7997         i9xx_crtc_clock_get(crtc, pipe_config);
7998
7999         /*
8000          * This value does not include pixel_multiplier.
8001          * We will check that port_clock and adjusted_mode.crtc_clock
8002          * agree once we know their relationship in the encoder's
8003          * get_config() function.
8004          */
8005         pipe_config->adjusted_mode.crtc_clock =
8006                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8007                                          &pipe_config->fdi_m_n);
8008 }
8009
8010 /** Returns the currently programmed mode of the given pipe. */
8011 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8012                                              struct drm_crtc *crtc)
8013 {
8014         struct drm_i915_private *dev_priv = dev->dev_private;
8015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8016         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8017         struct drm_display_mode *mode;
8018         struct intel_crtc_config pipe_config;
8019         int htot = I915_READ(HTOTAL(cpu_transcoder));
8020         int hsync = I915_READ(HSYNC(cpu_transcoder));
8021         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8022         int vsync = I915_READ(VSYNC(cpu_transcoder));
8023         enum pipe pipe = intel_crtc->pipe;
8024
8025         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8026         if (!mode)
8027                 return NULL;
8028
8029         /*
8030          * Construct a pipe_config sufficient for getting the clock info
8031          * back out of crtc_clock_get.
8032          *
8033          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8034          * to use a real value here instead.
8035          */
8036         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8037         pipe_config.pixel_multiplier = 1;
8038         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8039         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8040         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8041         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8042
8043         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8044         mode->hdisplay = (htot & 0xffff) + 1;
8045         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8046         mode->hsync_start = (hsync & 0xffff) + 1;
8047         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8048         mode->vdisplay = (vtot & 0xffff) + 1;
8049         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8050         mode->vsync_start = (vsync & 0xffff) + 1;
8051         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8052
8053         drm_mode_set_name(mode);
8054
8055         return mode;
8056 }
8057
8058 static void intel_increase_pllclock(struct drm_crtc *crtc)
8059 {
8060         struct drm_device *dev = crtc->dev;
8061         drm_i915_private_t *dev_priv = dev->dev_private;
8062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8063         int pipe = intel_crtc->pipe;
8064         int dpll_reg = DPLL(pipe);
8065         int dpll;
8066
8067         if (HAS_PCH_SPLIT(dev))
8068                 return;
8069
8070         if (!dev_priv->lvds_downclock_avail)
8071                 return;
8072
8073         dpll = I915_READ(dpll_reg);
8074         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8075                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8076
8077                 assert_panel_unlocked(dev_priv, pipe);
8078
8079                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8080                 I915_WRITE(dpll_reg, dpll);
8081                 intel_wait_for_vblank(dev, pipe);
8082
8083                 dpll = I915_READ(dpll_reg);
8084                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8085                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8086         }
8087 }
8088
8089 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8090 {
8091         struct drm_device *dev = crtc->dev;
8092         drm_i915_private_t *dev_priv = dev->dev_private;
8093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8094
8095         if (HAS_PCH_SPLIT(dev))
8096                 return;
8097
8098         if (!dev_priv->lvds_downclock_avail)
8099                 return;
8100
8101         /*
8102          * Since this is called by a timer, we should never get here in
8103          * the manual case.
8104          */
8105         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8106                 int pipe = intel_crtc->pipe;
8107                 int dpll_reg = DPLL(pipe);
8108                 int dpll;
8109
8110                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8111
8112                 assert_panel_unlocked(dev_priv, pipe);
8113
8114                 dpll = I915_READ(dpll_reg);
8115                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8116                 I915_WRITE(dpll_reg, dpll);
8117                 intel_wait_for_vblank(dev, pipe);
8118                 dpll = I915_READ(dpll_reg);
8119                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8120                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8121         }
8122
8123 }
8124
8125 void intel_mark_busy(struct drm_device *dev)
8126 {
8127         struct drm_i915_private *dev_priv = dev->dev_private;
8128
8129         hsw_package_c8_gpu_busy(dev_priv);
8130         i915_update_gfx_val(dev_priv);
8131 }
8132
8133 void intel_mark_idle(struct drm_device *dev)
8134 {
8135         struct drm_i915_private *dev_priv = dev->dev_private;
8136         struct drm_crtc *crtc;
8137
8138         hsw_package_c8_gpu_idle(dev_priv);
8139
8140         if (!i915_powersave)
8141                 return;
8142
8143         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8144                 if (!crtc->fb)
8145                         continue;
8146
8147                 intel_decrease_pllclock(crtc);
8148         }
8149
8150         if (dev_priv->info->gen >= 6)
8151                 gen6_rps_idle(dev->dev_private);
8152 }
8153
8154 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8155                         struct intel_ring_buffer *ring)
8156 {
8157         struct drm_device *dev = obj->base.dev;
8158         struct drm_crtc *crtc;
8159
8160         if (!i915_powersave)
8161                 return;
8162
8163         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8164                 if (!crtc->fb)
8165                         continue;
8166
8167                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8168                         continue;
8169
8170                 intel_increase_pllclock(crtc);
8171                 if (ring && intel_fbc_enabled(dev))
8172                         ring->fbc_dirty = true;
8173         }
8174 }
8175
8176 static void intel_crtc_destroy(struct drm_crtc *crtc)
8177 {
8178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8179         struct drm_device *dev = crtc->dev;
8180         struct intel_unpin_work *work;
8181         unsigned long flags;
8182
8183         spin_lock_irqsave(&dev->event_lock, flags);
8184         work = intel_crtc->unpin_work;
8185         intel_crtc->unpin_work = NULL;
8186         spin_unlock_irqrestore(&dev->event_lock, flags);
8187
8188         if (work) {
8189                 cancel_work_sync(&work->work);
8190                 kfree(work);
8191         }
8192
8193         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8194
8195         drm_crtc_cleanup(crtc);
8196
8197         kfree(intel_crtc);
8198 }
8199
8200 static void intel_unpin_work_fn(struct work_struct *__work)
8201 {
8202         struct intel_unpin_work *work =
8203                 container_of(__work, struct intel_unpin_work, work);
8204         struct drm_device *dev = work->crtc->dev;
8205
8206         mutex_lock(&dev->struct_mutex);
8207         intel_unpin_fb_obj(work->old_fb_obj);
8208         drm_gem_object_unreference(&work->pending_flip_obj->base);
8209         drm_gem_object_unreference(&work->old_fb_obj->base);
8210
8211         intel_update_fbc(dev);
8212         mutex_unlock(&dev->struct_mutex);
8213
8214         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8215         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8216
8217         kfree(work);
8218 }
8219
8220 static void do_intel_finish_page_flip(struct drm_device *dev,
8221                                       struct drm_crtc *crtc)
8222 {
8223         drm_i915_private_t *dev_priv = dev->dev_private;
8224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8225         struct intel_unpin_work *work;
8226         unsigned long flags;
8227
8228         /* Ignore early vblank irqs */
8229         if (intel_crtc == NULL)
8230                 return;
8231
8232         spin_lock_irqsave(&dev->event_lock, flags);
8233         work = intel_crtc->unpin_work;
8234
8235         /* Ensure we don't miss a work->pending update ... */
8236         smp_rmb();
8237
8238         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8239                 spin_unlock_irqrestore(&dev->event_lock, flags);
8240                 return;
8241         }
8242
8243         /* and that the unpin work is consistent wrt ->pending. */
8244         smp_rmb();
8245
8246         intel_crtc->unpin_work = NULL;
8247
8248         if (work->event)
8249                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8250
8251         drm_vblank_put(dev, intel_crtc->pipe);
8252
8253         spin_unlock_irqrestore(&dev->event_lock, flags);
8254
8255         wake_up_all(&dev_priv->pending_flip_queue);
8256
8257         queue_work(dev_priv->wq, &work->work);
8258
8259         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8260 }
8261
8262 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8263 {
8264         drm_i915_private_t *dev_priv = dev->dev_private;
8265         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8266
8267         do_intel_finish_page_flip(dev, crtc);
8268 }
8269
8270 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8271 {
8272         drm_i915_private_t *dev_priv = dev->dev_private;
8273         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8274
8275         do_intel_finish_page_flip(dev, crtc);
8276 }
8277
8278 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8279 {
8280         drm_i915_private_t *dev_priv = dev->dev_private;
8281         struct intel_crtc *intel_crtc =
8282                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8283         unsigned long flags;
8284
8285         /* NB: An MMIO update of the plane base pointer will also
8286          * generate a page-flip completion irq, i.e. every modeset
8287          * is also accompanied by a spurious intel_prepare_page_flip().
8288          */
8289         spin_lock_irqsave(&dev->event_lock, flags);
8290         if (intel_crtc->unpin_work)
8291                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8292         spin_unlock_irqrestore(&dev->event_lock, flags);
8293 }
8294
8295 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8296 {
8297         /* Ensure that the work item is consistent when activating it ... */
8298         smp_wmb();
8299         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8300         /* and that it is marked active as soon as the irq could fire. */
8301         smp_wmb();
8302 }
8303
8304 static int intel_gen2_queue_flip(struct drm_device *dev,
8305                                  struct drm_crtc *crtc,
8306                                  struct drm_framebuffer *fb,
8307                                  struct drm_i915_gem_object *obj,
8308                                  uint32_t flags)
8309 {
8310         struct drm_i915_private *dev_priv = dev->dev_private;
8311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8312         u32 flip_mask;
8313         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8314         int ret;
8315
8316         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8317         if (ret)
8318                 goto err;
8319
8320         ret = intel_ring_begin(ring, 6);
8321         if (ret)
8322                 goto err_unpin;
8323
8324         /* Can't queue multiple flips, so wait for the previous
8325          * one to finish before executing the next.
8326          */
8327         if (intel_crtc->plane)
8328                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8329         else
8330                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8331         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8332         intel_ring_emit(ring, MI_NOOP);
8333         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8334                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8335         intel_ring_emit(ring, fb->pitches[0]);
8336         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8337         intel_ring_emit(ring, 0); /* aux display base address, unused */
8338
8339         intel_mark_page_flip_active(intel_crtc);
8340         __intel_ring_advance(ring);
8341         return 0;
8342
8343 err_unpin:
8344         intel_unpin_fb_obj(obj);
8345 err:
8346         return ret;
8347 }
8348
8349 static int intel_gen3_queue_flip(struct drm_device *dev,
8350                                  struct drm_crtc *crtc,
8351                                  struct drm_framebuffer *fb,
8352                                  struct drm_i915_gem_object *obj,
8353                                  uint32_t flags)
8354 {
8355         struct drm_i915_private *dev_priv = dev->dev_private;
8356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8357         u32 flip_mask;
8358         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8359         int ret;
8360
8361         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8362         if (ret)
8363                 goto err;
8364
8365         ret = intel_ring_begin(ring, 6);
8366         if (ret)
8367                 goto err_unpin;
8368
8369         if (intel_crtc->plane)
8370                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8371         else
8372                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8373         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8374         intel_ring_emit(ring, MI_NOOP);
8375         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8376                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8377         intel_ring_emit(ring, fb->pitches[0]);
8378         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8379         intel_ring_emit(ring, MI_NOOP);
8380
8381         intel_mark_page_flip_active(intel_crtc);
8382         __intel_ring_advance(ring);
8383         return 0;
8384
8385 err_unpin:
8386         intel_unpin_fb_obj(obj);
8387 err:
8388         return ret;
8389 }
8390
8391 static int intel_gen4_queue_flip(struct drm_device *dev,
8392                                  struct drm_crtc *crtc,
8393                                  struct drm_framebuffer *fb,
8394                                  struct drm_i915_gem_object *obj,
8395                                  uint32_t flags)
8396 {
8397         struct drm_i915_private *dev_priv = dev->dev_private;
8398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8399         uint32_t pf, pipesrc;
8400         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8401         int ret;
8402
8403         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8404         if (ret)
8405                 goto err;
8406
8407         ret = intel_ring_begin(ring, 4);
8408         if (ret)
8409                 goto err_unpin;
8410
8411         /* i965+ uses the linear or tiled offsets from the
8412          * Display Registers (which do not change across a page-flip)
8413          * so we need only reprogram the base address.
8414          */
8415         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8416                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8417         intel_ring_emit(ring, fb->pitches[0]);
8418         intel_ring_emit(ring,
8419                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8420                         obj->tiling_mode);
8421
8422         /* XXX Enabling the panel-fitter across page-flip is so far
8423          * untested on non-native modes, so ignore it for now.
8424          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8425          */
8426         pf = 0;
8427         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8428         intel_ring_emit(ring, pf | pipesrc);
8429
8430         intel_mark_page_flip_active(intel_crtc);
8431         __intel_ring_advance(ring);
8432         return 0;
8433
8434 err_unpin:
8435         intel_unpin_fb_obj(obj);
8436 err:
8437         return ret;
8438 }
8439
8440 static int intel_gen6_queue_flip(struct drm_device *dev,
8441                                  struct drm_crtc *crtc,
8442                                  struct drm_framebuffer *fb,
8443                                  struct drm_i915_gem_object *obj,
8444                                  uint32_t flags)
8445 {
8446         struct drm_i915_private *dev_priv = dev->dev_private;
8447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8448         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8449         uint32_t pf, pipesrc;
8450         int ret;
8451
8452         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8453         if (ret)
8454                 goto err;
8455
8456         ret = intel_ring_begin(ring, 4);
8457         if (ret)
8458                 goto err_unpin;
8459
8460         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8461                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8462         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8463         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8464
8465         /* Contrary to the suggestions in the documentation,
8466          * "Enable Panel Fitter" does not seem to be required when page
8467          * flipping with a non-native mode, and worse causes a normal
8468          * modeset to fail.
8469          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8470          */
8471         pf = 0;
8472         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8473         intel_ring_emit(ring, pf | pipesrc);
8474
8475         intel_mark_page_flip_active(intel_crtc);
8476         __intel_ring_advance(ring);
8477         return 0;
8478
8479 err_unpin:
8480         intel_unpin_fb_obj(obj);
8481 err:
8482         return ret;
8483 }
8484
8485 static int intel_gen7_queue_flip(struct drm_device *dev,
8486                                  struct drm_crtc *crtc,
8487                                  struct drm_framebuffer *fb,
8488                                  struct drm_i915_gem_object *obj,
8489                                  uint32_t flags)
8490 {
8491         struct drm_i915_private *dev_priv = dev->dev_private;
8492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8493         struct intel_ring_buffer *ring;
8494         uint32_t plane_bit = 0;
8495         int len, ret;
8496
8497         ring = obj->ring;
8498         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8499                 ring = &dev_priv->ring[BCS];
8500
8501         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8502         if (ret)
8503                 goto err;
8504
8505         switch(intel_crtc->plane) {
8506         case PLANE_A:
8507                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8508                 break;
8509         case PLANE_B:
8510                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8511                 break;
8512         case PLANE_C:
8513                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8514                 break;
8515         default:
8516                 WARN_ONCE(1, "unknown plane in flip command\n");
8517                 ret = -ENODEV;
8518                 goto err_unpin;
8519         }
8520
8521         len = 4;
8522         if (ring->id == RCS)
8523                 len += 6;
8524
8525         ret = intel_ring_begin(ring, len);
8526         if (ret)
8527                 goto err_unpin;
8528
8529         /* Unmask the flip-done completion message. Note that the bspec says that
8530          * we should do this for both the BCS and RCS, and that we must not unmask
8531          * more than one flip event at any time (or ensure that one flip message
8532          * can be sent by waiting for flip-done prior to queueing new flips).
8533          * Experimentation says that BCS works despite DERRMR masking all
8534          * flip-done completion events and that unmasking all planes at once
8535          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8536          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8537          */
8538         if (ring->id == RCS) {
8539                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8540                 intel_ring_emit(ring, DERRMR);
8541                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8542                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8543                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8544                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8545                                 MI_SRM_LRM_GLOBAL_GTT);
8546                 intel_ring_emit(ring, DERRMR);
8547                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8548         }
8549
8550         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8551         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8552         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8553         intel_ring_emit(ring, (MI_NOOP));
8554
8555         intel_mark_page_flip_active(intel_crtc);
8556         __intel_ring_advance(ring);
8557         return 0;
8558
8559 err_unpin:
8560         intel_unpin_fb_obj(obj);
8561 err:
8562         return ret;
8563 }
8564
8565 static int intel_default_queue_flip(struct drm_device *dev,
8566                                     struct drm_crtc *crtc,
8567                                     struct drm_framebuffer *fb,
8568                                     struct drm_i915_gem_object *obj,
8569                                     uint32_t flags)
8570 {
8571         return -ENODEV;
8572 }
8573
8574 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8575                                 struct drm_framebuffer *fb,
8576                                 struct drm_pending_vblank_event *event,
8577                                 uint32_t page_flip_flags)
8578 {
8579         struct drm_device *dev = crtc->dev;
8580         struct drm_i915_private *dev_priv = dev->dev_private;
8581         struct drm_framebuffer *old_fb = crtc->fb;
8582         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8584         struct intel_unpin_work *work;
8585         unsigned long flags;
8586         int ret;
8587
8588         /* Can't change pixel format via MI display flips. */
8589         if (fb->pixel_format != crtc->fb->pixel_format)
8590                 return -EINVAL;
8591
8592         /*
8593          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8594          * Note that pitch changes could also affect these register.
8595          */
8596         if (INTEL_INFO(dev)->gen > 3 &&
8597             (fb->offsets[0] != crtc->fb->offsets[0] ||
8598              fb->pitches[0] != crtc->fb->pitches[0]))
8599                 return -EINVAL;
8600
8601         work = kzalloc(sizeof(*work), GFP_KERNEL);
8602         if (work == NULL)
8603                 return -ENOMEM;
8604
8605         work->event = event;
8606         work->crtc = crtc;
8607         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8608         INIT_WORK(&work->work, intel_unpin_work_fn);
8609
8610         ret = drm_vblank_get(dev, intel_crtc->pipe);
8611         if (ret)
8612                 goto free_work;
8613
8614         /* We borrow the event spin lock for protecting unpin_work */
8615         spin_lock_irqsave(&dev->event_lock, flags);
8616         if (intel_crtc->unpin_work) {
8617                 spin_unlock_irqrestore(&dev->event_lock, flags);
8618                 kfree(work);
8619                 drm_vblank_put(dev, intel_crtc->pipe);
8620
8621                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8622                 return -EBUSY;
8623         }
8624         intel_crtc->unpin_work = work;
8625         spin_unlock_irqrestore(&dev->event_lock, flags);
8626
8627         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8628                 flush_workqueue(dev_priv->wq);
8629
8630         ret = i915_mutex_lock_interruptible(dev);
8631         if (ret)
8632                 goto cleanup;
8633
8634         /* Reference the objects for the scheduled work. */
8635         drm_gem_object_reference(&work->old_fb_obj->base);
8636         drm_gem_object_reference(&obj->base);
8637
8638         crtc->fb = fb;
8639
8640         work->pending_flip_obj = obj;
8641
8642         work->enable_stall_check = true;
8643
8644         atomic_inc(&intel_crtc->unpin_work_count);
8645         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8646
8647         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8648         if (ret)
8649                 goto cleanup_pending;
8650
8651         intel_disable_fbc(dev);
8652         intel_mark_fb_busy(obj, NULL);
8653         mutex_unlock(&dev->struct_mutex);
8654
8655         trace_i915_flip_request(intel_crtc->plane, obj);
8656
8657         return 0;
8658
8659 cleanup_pending:
8660         atomic_dec(&intel_crtc->unpin_work_count);
8661         crtc->fb = old_fb;
8662         drm_gem_object_unreference(&work->old_fb_obj->base);
8663         drm_gem_object_unreference(&obj->base);
8664         mutex_unlock(&dev->struct_mutex);
8665
8666 cleanup:
8667         spin_lock_irqsave(&dev->event_lock, flags);
8668         intel_crtc->unpin_work = NULL;
8669         spin_unlock_irqrestore(&dev->event_lock, flags);
8670
8671         drm_vblank_put(dev, intel_crtc->pipe);
8672 free_work:
8673         kfree(work);
8674
8675         return ret;
8676 }
8677
8678 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8679         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8680         .load_lut = intel_crtc_load_lut,
8681 };
8682
8683 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8684                                   struct drm_crtc *crtc)
8685 {
8686         struct drm_device *dev;
8687         struct drm_crtc *tmp;
8688         int crtc_mask = 1;
8689
8690         WARN(!crtc, "checking null crtc?\n");
8691
8692         dev = crtc->dev;
8693
8694         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8695                 if (tmp == crtc)
8696                         break;
8697                 crtc_mask <<= 1;
8698         }
8699
8700         if (encoder->possible_crtcs & crtc_mask)
8701                 return true;
8702         return false;
8703 }
8704
8705 /**
8706  * intel_modeset_update_staged_output_state
8707  *
8708  * Updates the staged output configuration state, e.g. after we've read out the
8709  * current hw state.
8710  */
8711 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8712 {
8713         struct intel_encoder *encoder;
8714         struct intel_connector *connector;
8715
8716         list_for_each_entry(connector, &dev->mode_config.connector_list,
8717                             base.head) {
8718                 connector->new_encoder =
8719                         to_intel_encoder(connector->base.encoder);
8720         }
8721
8722         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8723                             base.head) {
8724                 encoder->new_crtc =
8725                         to_intel_crtc(encoder->base.crtc);
8726         }
8727 }
8728
8729 /**
8730  * intel_modeset_commit_output_state
8731  *
8732  * This function copies the stage display pipe configuration to the real one.
8733  */
8734 static void intel_modeset_commit_output_state(struct drm_device *dev)
8735 {
8736         struct intel_encoder *encoder;
8737         struct intel_connector *connector;
8738
8739         list_for_each_entry(connector, &dev->mode_config.connector_list,
8740                             base.head) {
8741                 connector->base.encoder = &connector->new_encoder->base;
8742         }
8743
8744         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8745                             base.head) {
8746                 encoder->base.crtc = &encoder->new_crtc->base;
8747         }
8748 }
8749
8750 static void
8751 connected_sink_compute_bpp(struct intel_connector * connector,
8752                            struct intel_crtc_config *pipe_config)
8753 {
8754         int bpp = pipe_config->pipe_bpp;
8755
8756         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8757                 connector->base.base.id,
8758                 drm_get_connector_name(&connector->base));
8759
8760         /* Don't use an invalid EDID bpc value */
8761         if (connector->base.display_info.bpc &&
8762             connector->base.display_info.bpc * 3 < bpp) {
8763                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8764                               bpp, connector->base.display_info.bpc*3);
8765                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8766         }
8767
8768         /* Clamp bpp to 8 on screens without EDID 1.4 */
8769         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8770                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8771                               bpp);
8772                 pipe_config->pipe_bpp = 24;
8773         }
8774 }
8775
8776 static int
8777 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8778                           struct drm_framebuffer *fb,
8779                           struct intel_crtc_config *pipe_config)
8780 {
8781         struct drm_device *dev = crtc->base.dev;
8782         struct intel_connector *connector;
8783         int bpp;
8784
8785         switch (fb->pixel_format) {
8786         case DRM_FORMAT_C8:
8787                 bpp = 8*3; /* since we go through a colormap */
8788                 break;
8789         case DRM_FORMAT_XRGB1555:
8790         case DRM_FORMAT_ARGB1555:
8791                 /* checked in intel_framebuffer_init already */
8792                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8793                         return -EINVAL;
8794         case DRM_FORMAT_RGB565:
8795                 bpp = 6*3; /* min is 18bpp */
8796                 break;
8797         case DRM_FORMAT_XBGR8888:
8798         case DRM_FORMAT_ABGR8888:
8799                 /* checked in intel_framebuffer_init already */
8800                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8801                         return -EINVAL;
8802         case DRM_FORMAT_XRGB8888:
8803         case DRM_FORMAT_ARGB8888:
8804                 bpp = 8*3;
8805                 break;
8806         case DRM_FORMAT_XRGB2101010:
8807         case DRM_FORMAT_ARGB2101010:
8808         case DRM_FORMAT_XBGR2101010:
8809         case DRM_FORMAT_ABGR2101010:
8810                 /* checked in intel_framebuffer_init already */
8811                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8812                         return -EINVAL;
8813                 bpp = 10*3;
8814                 break;
8815         /* TODO: gen4+ supports 16 bpc floating point, too. */
8816         default:
8817                 DRM_DEBUG_KMS("unsupported depth\n");
8818                 return -EINVAL;
8819         }
8820
8821         pipe_config->pipe_bpp = bpp;
8822
8823         /* Clamp display bpp to EDID value */
8824         list_for_each_entry(connector, &dev->mode_config.connector_list,
8825                             base.head) {
8826                 if (!connector->new_encoder ||
8827                     connector->new_encoder->new_crtc != crtc)
8828                         continue;
8829
8830                 connected_sink_compute_bpp(connector, pipe_config);
8831         }
8832
8833         return bpp;
8834 }
8835
8836 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8837 {
8838         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8839                         "type: 0x%x flags: 0x%x\n",
8840                 mode->crtc_clock,
8841                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8842                 mode->crtc_hsync_end, mode->crtc_htotal,
8843                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8844                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8845 }
8846
8847 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8848                                    struct intel_crtc_config *pipe_config,
8849                                    const char *context)
8850 {
8851         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8852                       context, pipe_name(crtc->pipe));
8853
8854         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8855         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8856                       pipe_config->pipe_bpp, pipe_config->dither);
8857         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8858                       pipe_config->has_pch_encoder,
8859                       pipe_config->fdi_lanes,
8860                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8861                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8862                       pipe_config->fdi_m_n.tu);
8863         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8864                       pipe_config->has_dp_encoder,
8865                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8866                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8867                       pipe_config->dp_m_n.tu);
8868         DRM_DEBUG_KMS("requested mode:\n");
8869         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8870         DRM_DEBUG_KMS("adjusted mode:\n");
8871         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8872         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8873         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8874         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8875                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8876         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8877                       pipe_config->gmch_pfit.control,
8878                       pipe_config->gmch_pfit.pgm_ratios,
8879                       pipe_config->gmch_pfit.lvds_border_bits);
8880         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8881                       pipe_config->pch_pfit.pos,
8882                       pipe_config->pch_pfit.size,
8883                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8884         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8885         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8886 }
8887
8888 static bool check_encoder_cloning(struct drm_crtc *crtc)
8889 {
8890         int num_encoders = 0;
8891         bool uncloneable_encoders = false;
8892         struct intel_encoder *encoder;
8893
8894         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8895                             base.head) {
8896                 if (&encoder->new_crtc->base != crtc)
8897                         continue;
8898
8899                 num_encoders++;
8900                 if (!encoder->cloneable)
8901                         uncloneable_encoders = true;
8902         }
8903
8904         return !(num_encoders > 1 && uncloneable_encoders);
8905 }
8906
8907 static struct intel_crtc_config *
8908 intel_modeset_pipe_config(struct drm_crtc *crtc,
8909                           struct drm_framebuffer *fb,
8910                           struct drm_display_mode *mode)
8911 {
8912         struct drm_device *dev = crtc->dev;
8913         struct intel_encoder *encoder;
8914         struct intel_crtc_config *pipe_config;
8915         int plane_bpp, ret = -EINVAL;
8916         bool retry = true;
8917
8918         if (!check_encoder_cloning(crtc)) {
8919                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8920                 return ERR_PTR(-EINVAL);
8921         }
8922
8923         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8924         if (!pipe_config)
8925                 return ERR_PTR(-ENOMEM);
8926
8927         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8928         drm_mode_copy(&pipe_config->requested_mode, mode);
8929
8930         pipe_config->cpu_transcoder =
8931                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8932         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8933
8934         /*
8935          * Sanitize sync polarity flags based on requested ones. If neither
8936          * positive or negative polarity is requested, treat this as meaning
8937          * negative polarity.
8938          */
8939         if (!(pipe_config->adjusted_mode.flags &
8940               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8941                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8942
8943         if (!(pipe_config->adjusted_mode.flags &
8944               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8945                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8946
8947         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8948          * plane pixel format and any sink constraints into account. Returns the
8949          * source plane bpp so that dithering can be selected on mismatches
8950          * after encoders and crtc also have had their say. */
8951         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8952                                               fb, pipe_config);
8953         if (plane_bpp < 0)
8954                 goto fail;
8955
8956         /*
8957          * Determine the real pipe dimensions. Note that stereo modes can
8958          * increase the actual pipe size due to the frame doubling and
8959          * insertion of additional space for blanks between the frame. This
8960          * is stored in the crtc timings. We use the requested mode to do this
8961          * computation to clearly distinguish it from the adjusted mode, which
8962          * can be changed by the connectors in the below retry loop.
8963          */
8964         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8965         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8966         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8967
8968 encoder_retry:
8969         /* Ensure the port clock defaults are reset when retrying. */
8970         pipe_config->port_clock = 0;
8971         pipe_config->pixel_multiplier = 1;
8972
8973         /* Fill in default crtc timings, allow encoders to overwrite them. */
8974         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8975
8976         /* Pass our mode to the connectors and the CRTC to give them a chance to
8977          * adjust it according to limitations or connector properties, and also
8978          * a chance to reject the mode entirely.
8979          */
8980         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8981                             base.head) {
8982
8983                 if (&encoder->new_crtc->base != crtc)
8984                         continue;
8985
8986                 if (!(encoder->compute_config(encoder, pipe_config))) {
8987                         DRM_DEBUG_KMS("Encoder config failure\n");
8988                         goto fail;
8989                 }
8990         }
8991
8992         /* Set default port clock if not overwritten by the encoder. Needs to be
8993          * done afterwards in case the encoder adjusts the mode. */
8994         if (!pipe_config->port_clock)
8995                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8996                         * pipe_config->pixel_multiplier;
8997
8998         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8999         if (ret < 0) {
9000                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9001                 goto fail;
9002         }
9003
9004         if (ret == RETRY) {
9005                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9006                         ret = -EINVAL;
9007                         goto fail;
9008                 }
9009
9010                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9011                 retry = false;
9012                 goto encoder_retry;
9013         }
9014
9015         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9016         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9017                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9018
9019         return pipe_config;
9020 fail:
9021         kfree(pipe_config);
9022         return ERR_PTR(ret);
9023 }
9024
9025 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9026  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9027 static void
9028 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9029                              unsigned *prepare_pipes, unsigned *disable_pipes)
9030 {
9031         struct intel_crtc *intel_crtc;
9032         struct drm_device *dev = crtc->dev;
9033         struct intel_encoder *encoder;
9034         struct intel_connector *connector;
9035         struct drm_crtc *tmp_crtc;
9036
9037         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9038
9039         /* Check which crtcs have changed outputs connected to them, these need
9040          * to be part of the prepare_pipes mask. We don't (yet) support global
9041          * modeset across multiple crtcs, so modeset_pipes will only have one
9042          * bit set at most. */
9043         list_for_each_entry(connector, &dev->mode_config.connector_list,
9044                             base.head) {
9045                 if (connector->base.encoder == &connector->new_encoder->base)
9046                         continue;
9047
9048                 if (connector->base.encoder) {
9049                         tmp_crtc = connector->base.encoder->crtc;
9050
9051                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9052                 }
9053
9054                 if (connector->new_encoder)
9055                         *prepare_pipes |=
9056                                 1 << connector->new_encoder->new_crtc->pipe;
9057         }
9058
9059         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9060                             base.head) {
9061                 if (encoder->base.crtc == &encoder->new_crtc->base)
9062                         continue;
9063
9064                 if (encoder->base.crtc) {
9065                         tmp_crtc = encoder->base.crtc;
9066
9067                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9068                 }
9069
9070                 if (encoder->new_crtc)
9071                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9072         }
9073
9074         /* Check for any pipes that will be fully disabled ... */
9075         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9076                             base.head) {
9077                 bool used = false;
9078
9079                 /* Don't try to disable disabled crtcs. */
9080                 if (!intel_crtc->base.enabled)
9081                         continue;
9082
9083                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9084                                     base.head) {
9085                         if (encoder->new_crtc == intel_crtc)
9086                                 used = true;
9087                 }
9088
9089                 if (!used)
9090                         *disable_pipes |= 1 << intel_crtc->pipe;
9091         }
9092
9093
9094         /* set_mode is also used to update properties on life display pipes. */
9095         intel_crtc = to_intel_crtc(crtc);
9096         if (crtc->enabled)
9097                 *prepare_pipes |= 1 << intel_crtc->pipe;
9098
9099         /*
9100          * For simplicity do a full modeset on any pipe where the output routing
9101          * changed. We could be more clever, but that would require us to be
9102          * more careful with calling the relevant encoder->mode_set functions.
9103          */
9104         if (*prepare_pipes)
9105                 *modeset_pipes = *prepare_pipes;
9106
9107         /* ... and mask these out. */
9108         *modeset_pipes &= ~(*disable_pipes);
9109         *prepare_pipes &= ~(*disable_pipes);
9110
9111         /*
9112          * HACK: We don't (yet) fully support global modesets. intel_set_config
9113          * obies this rule, but the modeset restore mode of
9114          * intel_modeset_setup_hw_state does not.
9115          */
9116         *modeset_pipes &= 1 << intel_crtc->pipe;
9117         *prepare_pipes &= 1 << intel_crtc->pipe;
9118
9119         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9120                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9121 }
9122
9123 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9124 {
9125         struct drm_encoder *encoder;
9126         struct drm_device *dev = crtc->dev;
9127
9128         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9129                 if (encoder->crtc == crtc)
9130                         return true;
9131
9132         return false;
9133 }
9134
9135 static void
9136 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9137 {
9138         struct intel_encoder *intel_encoder;
9139         struct intel_crtc *intel_crtc;
9140         struct drm_connector *connector;
9141
9142         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9143                             base.head) {
9144                 if (!intel_encoder->base.crtc)
9145                         continue;
9146
9147                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9148
9149                 if (prepare_pipes & (1 << intel_crtc->pipe))
9150                         intel_encoder->connectors_active = false;
9151         }
9152
9153         intel_modeset_commit_output_state(dev);
9154
9155         /* Update computed state. */
9156         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9157                             base.head) {
9158                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9159         }
9160
9161         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9162                 if (!connector->encoder || !connector->encoder->crtc)
9163                         continue;
9164
9165                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9166
9167                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9168                         struct drm_property *dpms_property =
9169                                 dev->mode_config.dpms_property;
9170
9171                         connector->dpms = DRM_MODE_DPMS_ON;
9172                         drm_object_property_set_value(&connector->base,
9173                                                          dpms_property,
9174                                                          DRM_MODE_DPMS_ON);
9175
9176                         intel_encoder = to_intel_encoder(connector->encoder);
9177                         intel_encoder->connectors_active = true;
9178                 }
9179         }
9180
9181 }
9182
9183 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9184 {
9185         int diff;
9186
9187         if (clock1 == clock2)
9188                 return true;
9189
9190         if (!clock1 || !clock2)
9191                 return false;
9192
9193         diff = abs(clock1 - clock2);
9194
9195         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9196                 return true;
9197
9198         return false;
9199 }
9200
9201 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9202         list_for_each_entry((intel_crtc), \
9203                             &(dev)->mode_config.crtc_list, \
9204                             base.head) \
9205                 if (mask & (1 <<(intel_crtc)->pipe))
9206
9207 static bool
9208 intel_pipe_config_compare(struct drm_device *dev,
9209                           struct intel_crtc_config *current_config,
9210                           struct intel_crtc_config *pipe_config)
9211 {
9212 #define PIPE_CONF_CHECK_X(name) \
9213         if (current_config->name != pipe_config->name) { \
9214                 DRM_ERROR("mismatch in " #name " " \
9215                           "(expected 0x%08x, found 0x%08x)\n", \
9216                           current_config->name, \
9217                           pipe_config->name); \
9218                 return false; \
9219         }
9220
9221 #define PIPE_CONF_CHECK_I(name) \
9222         if (current_config->name != pipe_config->name) { \
9223                 DRM_ERROR("mismatch in " #name " " \
9224                           "(expected %i, found %i)\n", \
9225                           current_config->name, \
9226                           pipe_config->name); \
9227                 return false; \
9228         }
9229
9230 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9231         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9232                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9233                           "(expected %i, found %i)\n", \
9234                           current_config->name & (mask), \
9235                           pipe_config->name & (mask)); \
9236                 return false; \
9237         }
9238
9239 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9240         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9241                 DRM_ERROR("mismatch in " #name " " \
9242                           "(expected %i, found %i)\n", \
9243                           current_config->name, \
9244                           pipe_config->name); \
9245                 return false; \
9246         }
9247
9248 #define PIPE_CONF_QUIRK(quirk)  \
9249         ((current_config->quirks | pipe_config->quirks) & (quirk))
9250
9251         PIPE_CONF_CHECK_I(cpu_transcoder);
9252
9253         PIPE_CONF_CHECK_I(has_pch_encoder);
9254         PIPE_CONF_CHECK_I(fdi_lanes);
9255         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9256         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9257         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9258         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9259         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9260
9261         PIPE_CONF_CHECK_I(has_dp_encoder);
9262         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9263         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9264         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9265         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9266         PIPE_CONF_CHECK_I(dp_m_n.tu);
9267
9268         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9269         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9270         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9271         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9272         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9273         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9274
9275         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9276         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9277         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9278         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9279         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9280         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9281
9282         PIPE_CONF_CHECK_I(pixel_multiplier);
9283
9284         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9285                               DRM_MODE_FLAG_INTERLACE);
9286
9287         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9288                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9289                                       DRM_MODE_FLAG_PHSYNC);
9290                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9291                                       DRM_MODE_FLAG_NHSYNC);
9292                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9293                                       DRM_MODE_FLAG_PVSYNC);
9294                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9295                                       DRM_MODE_FLAG_NVSYNC);
9296         }
9297
9298         PIPE_CONF_CHECK_I(pipe_src_w);
9299         PIPE_CONF_CHECK_I(pipe_src_h);
9300
9301         PIPE_CONF_CHECK_I(gmch_pfit.control);
9302         /* pfit ratios are autocomputed by the hw on gen4+ */
9303         if (INTEL_INFO(dev)->gen < 4)
9304                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9305         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9306         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9307         if (current_config->pch_pfit.enabled) {
9308                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9309                 PIPE_CONF_CHECK_I(pch_pfit.size);
9310         }
9311
9312         PIPE_CONF_CHECK_I(ips_enabled);
9313
9314         PIPE_CONF_CHECK_I(double_wide);
9315
9316         PIPE_CONF_CHECK_I(shared_dpll);
9317         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9318         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9319         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9320         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9321
9322         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9323                 PIPE_CONF_CHECK_I(pipe_bpp);
9324
9325         if (!HAS_DDI(dev)) {
9326                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9327                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9328         }
9329
9330 #undef PIPE_CONF_CHECK_X
9331 #undef PIPE_CONF_CHECK_I
9332 #undef PIPE_CONF_CHECK_FLAGS
9333 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9334 #undef PIPE_CONF_QUIRK
9335
9336         return true;
9337 }
9338
9339 static void
9340 check_connector_state(struct drm_device *dev)
9341 {
9342         struct intel_connector *connector;
9343
9344         list_for_each_entry(connector, &dev->mode_config.connector_list,
9345                             base.head) {
9346                 /* This also checks the encoder/connector hw state with the
9347                  * ->get_hw_state callbacks. */
9348                 intel_connector_check_state(connector);
9349
9350                 WARN(&connector->new_encoder->base != connector->base.encoder,
9351                      "connector's staged encoder doesn't match current encoder\n");
9352         }
9353 }
9354
9355 static void
9356 check_encoder_state(struct drm_device *dev)
9357 {
9358         struct intel_encoder *encoder;
9359         struct intel_connector *connector;
9360
9361         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9362                             base.head) {
9363                 bool enabled = false;
9364                 bool active = false;
9365                 enum pipe pipe, tracked_pipe;
9366
9367                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9368                               encoder->base.base.id,
9369                               drm_get_encoder_name(&encoder->base));
9370
9371                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9372                      "encoder's stage crtc doesn't match current crtc\n");
9373                 WARN(encoder->connectors_active && !encoder->base.crtc,
9374                      "encoder's active_connectors set, but no crtc\n");
9375
9376                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9377                                     base.head) {
9378                         if (connector->base.encoder != &encoder->base)
9379                                 continue;
9380                         enabled = true;
9381                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9382                                 active = true;
9383                 }
9384                 WARN(!!encoder->base.crtc != enabled,
9385                      "encoder's enabled state mismatch "
9386                      "(expected %i, found %i)\n",
9387                      !!encoder->base.crtc, enabled);
9388                 WARN(active && !encoder->base.crtc,
9389                      "active encoder with no crtc\n");
9390
9391                 WARN(encoder->connectors_active != active,
9392                      "encoder's computed active state doesn't match tracked active state "
9393                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9394
9395                 active = encoder->get_hw_state(encoder, &pipe);
9396                 WARN(active != encoder->connectors_active,
9397                      "encoder's hw state doesn't match sw tracking "
9398                      "(expected %i, found %i)\n",
9399                      encoder->connectors_active, active);
9400
9401                 if (!encoder->base.crtc)
9402                         continue;
9403
9404                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9405                 WARN(active && pipe != tracked_pipe,
9406                      "active encoder's pipe doesn't match"
9407                      "(expected %i, found %i)\n",
9408                      tracked_pipe, pipe);
9409
9410         }
9411 }
9412
9413 static void
9414 check_crtc_state(struct drm_device *dev)
9415 {
9416         drm_i915_private_t *dev_priv = dev->dev_private;
9417         struct intel_crtc *crtc;
9418         struct intel_encoder *encoder;
9419         struct intel_crtc_config pipe_config;
9420
9421         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9422                             base.head) {
9423                 bool enabled = false;
9424                 bool active = false;
9425
9426                 memset(&pipe_config, 0, sizeof(pipe_config));
9427
9428                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9429                               crtc->base.base.id);
9430
9431                 WARN(crtc->active && !crtc->base.enabled,
9432                      "active crtc, but not enabled in sw tracking\n");
9433
9434                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9435                                     base.head) {
9436                         if (encoder->base.crtc != &crtc->base)
9437                                 continue;
9438                         enabled = true;
9439                         if (encoder->connectors_active)
9440                                 active = true;
9441                 }
9442
9443                 WARN(active != crtc->active,
9444                      "crtc's computed active state doesn't match tracked active state "
9445                      "(expected %i, found %i)\n", active, crtc->active);
9446                 WARN(enabled != crtc->base.enabled,
9447                      "crtc's computed enabled state doesn't match tracked enabled state "
9448                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9449
9450                 active = dev_priv->display.get_pipe_config(crtc,
9451                                                            &pipe_config);
9452
9453                 /* hw state is inconsistent with the pipe A quirk */
9454                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9455                         active = crtc->active;
9456
9457                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9458                                     base.head) {
9459                         enum pipe pipe;
9460                         if (encoder->base.crtc != &crtc->base)
9461                                 continue;
9462                         if (encoder->get_hw_state(encoder, &pipe))
9463                                 encoder->get_config(encoder, &pipe_config);
9464                 }
9465
9466                 WARN(crtc->active != active,
9467                      "crtc active state doesn't match with hw state "
9468                      "(expected %i, found %i)\n", crtc->active, active);
9469
9470                 if (active &&
9471                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9472                         WARN(1, "pipe state doesn't match!\n");
9473                         intel_dump_pipe_config(crtc, &pipe_config,
9474                                                "[hw state]");
9475                         intel_dump_pipe_config(crtc, &crtc->config,
9476                                                "[sw state]");
9477                 }
9478         }
9479 }
9480
9481 static void
9482 check_shared_dpll_state(struct drm_device *dev)
9483 {
9484         drm_i915_private_t *dev_priv = dev->dev_private;
9485         struct intel_crtc *crtc;
9486         struct intel_dpll_hw_state dpll_hw_state;
9487         int i;
9488
9489         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9490                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9491                 int enabled_crtcs = 0, active_crtcs = 0;
9492                 bool active;
9493
9494                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9495
9496                 DRM_DEBUG_KMS("%s\n", pll->name);
9497
9498                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9499
9500                 WARN(pll->active > pll->refcount,
9501                      "more active pll users than references: %i vs %i\n",
9502                      pll->active, pll->refcount);
9503                 WARN(pll->active && !pll->on,
9504                      "pll in active use but not on in sw tracking\n");
9505                 WARN(pll->on && !pll->active,
9506                      "pll in on but not on in use in sw tracking\n");
9507                 WARN(pll->on != active,
9508                      "pll on state mismatch (expected %i, found %i)\n",
9509                      pll->on, active);
9510
9511                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9512                                     base.head) {
9513                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9514                                 enabled_crtcs++;
9515                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9516                                 active_crtcs++;
9517                 }
9518                 WARN(pll->active != active_crtcs,
9519                      "pll active crtcs mismatch (expected %i, found %i)\n",
9520                      pll->active, active_crtcs);
9521                 WARN(pll->refcount != enabled_crtcs,
9522                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9523                      pll->refcount, enabled_crtcs);
9524
9525                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9526                                        sizeof(dpll_hw_state)),
9527                      "pll hw state mismatch\n");
9528         }
9529 }
9530
9531 void
9532 intel_modeset_check_state(struct drm_device *dev)
9533 {
9534         check_connector_state(dev);
9535         check_encoder_state(dev);
9536         check_crtc_state(dev);
9537         check_shared_dpll_state(dev);
9538 }
9539
9540 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9541                                      int dotclock)
9542 {
9543         /*
9544          * FDI already provided one idea for the dotclock.
9545          * Yell if the encoder disagrees.
9546          */
9547         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9548              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9549              pipe_config->adjusted_mode.crtc_clock, dotclock);
9550 }
9551
9552 static int __intel_set_mode(struct drm_crtc *crtc,
9553                             struct drm_display_mode *mode,
9554                             int x, int y, struct drm_framebuffer *fb)
9555 {
9556         struct drm_device *dev = crtc->dev;
9557         drm_i915_private_t *dev_priv = dev->dev_private;
9558         struct drm_display_mode *saved_mode, *saved_hwmode;
9559         struct intel_crtc_config *pipe_config = NULL;
9560         struct intel_crtc *intel_crtc;
9561         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9562         int ret = 0;
9563
9564         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9565         if (!saved_mode)
9566                 return -ENOMEM;
9567         saved_hwmode = saved_mode + 1;
9568
9569         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9570                                      &prepare_pipes, &disable_pipes);
9571
9572         *saved_hwmode = crtc->hwmode;
9573         *saved_mode = crtc->mode;
9574
9575         /* Hack: Because we don't (yet) support global modeset on multiple
9576          * crtcs, we don't keep track of the new mode for more than one crtc.
9577          * Hence simply check whether any bit is set in modeset_pipes in all the
9578          * pieces of code that are not yet converted to deal with mutliple crtcs
9579          * changing their mode at the same time. */
9580         if (modeset_pipes) {
9581                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9582                 if (IS_ERR(pipe_config)) {
9583                         ret = PTR_ERR(pipe_config);
9584                         pipe_config = NULL;
9585
9586                         goto out;
9587                 }
9588                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9589                                        "[modeset]");
9590         }
9591
9592         /*
9593          * See if the config requires any additional preparation, e.g.
9594          * to adjust global state with pipes off.  We need to do this
9595          * here so we can get the modeset_pipe updated config for the new
9596          * mode set on this crtc.  For other crtcs we need to use the
9597          * adjusted_mode bits in the crtc directly.
9598          */
9599         if (IS_VALLEYVIEW(dev)) {
9600                 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9601                                                 modeset_pipes, pipe_config);
9602
9603                 /* may have added more to prepare_pipes than we should */
9604                 prepare_pipes &= ~disable_pipes;
9605         }
9606
9607         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9608                 intel_crtc_disable(&intel_crtc->base);
9609
9610         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9611                 if (intel_crtc->base.enabled)
9612                         dev_priv->display.crtc_disable(&intel_crtc->base);
9613         }
9614
9615         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9616          * to set it here already despite that we pass it down the callchain.
9617          */
9618         if (modeset_pipes) {
9619                 crtc->mode = *mode;
9620                 /* mode_set/enable/disable functions rely on a correct pipe
9621                  * config. */
9622                 to_intel_crtc(crtc)->config = *pipe_config;
9623         }
9624
9625         /* Only after disabling all output pipelines that will be changed can we
9626          * update the the output configuration. */
9627         intel_modeset_update_state(dev, prepare_pipes);
9628
9629         if (dev_priv->display.modeset_global_resources)
9630                 dev_priv->display.modeset_global_resources(dev);
9631
9632         /* Set up the DPLL and any encoders state that needs to adjust or depend
9633          * on the DPLL.
9634          */
9635         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9636                 ret = intel_crtc_mode_set(&intel_crtc->base,
9637                                           x, y, fb);
9638                 if (ret)
9639                         goto done;
9640         }
9641
9642         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9643         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9644                 dev_priv->display.crtc_enable(&intel_crtc->base);
9645
9646         if (modeset_pipes) {
9647                 /* Store real post-adjustment hardware mode. */
9648                 crtc->hwmode = pipe_config->adjusted_mode;
9649
9650                 /* Calculate and store various constants which
9651                  * are later needed by vblank and swap-completion
9652                  * timestamping. They are derived from true hwmode.
9653                  */
9654                 drm_calc_timestamping_constants(crtc);
9655         }
9656
9657         /* FIXME: add subpixel order */
9658 done:
9659         if (ret && crtc->enabled) {
9660                 crtc->hwmode = *saved_hwmode;
9661                 crtc->mode = *saved_mode;
9662         }
9663
9664 out:
9665         kfree(pipe_config);
9666         kfree(saved_mode);
9667         return ret;
9668 }
9669
9670 static int intel_set_mode(struct drm_crtc *crtc,
9671                           struct drm_display_mode *mode,
9672                           int x, int y, struct drm_framebuffer *fb)
9673 {
9674         int ret;
9675
9676         ret = __intel_set_mode(crtc, mode, x, y, fb);
9677
9678         if (ret == 0)
9679                 intel_modeset_check_state(crtc->dev);
9680
9681         return ret;
9682 }
9683
9684 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9685 {
9686         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9687 }
9688
9689 #undef for_each_intel_crtc_masked
9690
9691 static void intel_set_config_free(struct intel_set_config *config)
9692 {
9693         if (!config)
9694                 return;
9695
9696         kfree(config->save_connector_encoders);
9697         kfree(config->save_encoder_crtcs);
9698         kfree(config);
9699 }
9700
9701 static int intel_set_config_save_state(struct drm_device *dev,
9702                                        struct intel_set_config *config)
9703 {
9704         struct drm_encoder *encoder;
9705         struct drm_connector *connector;
9706         int count;
9707
9708         config->save_encoder_crtcs =
9709                 kcalloc(dev->mode_config.num_encoder,
9710                         sizeof(struct drm_crtc *), GFP_KERNEL);
9711         if (!config->save_encoder_crtcs)
9712                 return -ENOMEM;
9713
9714         config->save_connector_encoders =
9715                 kcalloc(dev->mode_config.num_connector,
9716                         sizeof(struct drm_encoder *), GFP_KERNEL);
9717         if (!config->save_connector_encoders)
9718                 return -ENOMEM;
9719
9720         /* Copy data. Note that driver private data is not affected.
9721          * Should anything bad happen only the expected state is
9722          * restored, not the drivers personal bookkeeping.
9723          */
9724         count = 0;
9725         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9726                 config->save_encoder_crtcs[count++] = encoder->crtc;
9727         }
9728
9729         count = 0;
9730         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9731                 config->save_connector_encoders[count++] = connector->encoder;
9732         }
9733
9734         return 0;
9735 }
9736
9737 static void intel_set_config_restore_state(struct drm_device *dev,
9738                                            struct intel_set_config *config)
9739 {
9740         struct intel_encoder *encoder;
9741         struct intel_connector *connector;
9742         int count;
9743
9744         count = 0;
9745         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9746                 encoder->new_crtc =
9747                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9748         }
9749
9750         count = 0;
9751         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9752                 connector->new_encoder =
9753                         to_intel_encoder(config->save_connector_encoders[count++]);
9754         }
9755 }
9756
9757 static bool
9758 is_crtc_connector_off(struct drm_mode_set *set)
9759 {
9760         int i;
9761
9762         if (set->num_connectors == 0)
9763                 return false;
9764
9765         if (WARN_ON(set->connectors == NULL))
9766                 return false;
9767
9768         for (i = 0; i < set->num_connectors; i++)
9769                 if (set->connectors[i]->encoder &&
9770                     set->connectors[i]->encoder->crtc == set->crtc &&
9771                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9772                         return true;
9773
9774         return false;
9775 }
9776
9777 static void
9778 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9779                                       struct intel_set_config *config)
9780 {
9781
9782         /* We should be able to check here if the fb has the same properties
9783          * and then just flip_or_move it */
9784         if (is_crtc_connector_off(set)) {
9785                 config->mode_changed = true;
9786         } else if (set->crtc->fb != set->fb) {
9787                 /* If we have no fb then treat it as a full mode set */
9788                 if (set->crtc->fb == NULL) {
9789                         struct intel_crtc *intel_crtc =
9790                                 to_intel_crtc(set->crtc);
9791
9792                         if (intel_crtc->active && i915_fastboot) {
9793                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9794                                 config->fb_changed = true;
9795                         } else {
9796                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9797                                 config->mode_changed = true;
9798                         }
9799                 } else if (set->fb == NULL) {
9800                         config->mode_changed = true;
9801                 } else if (set->fb->pixel_format !=
9802                            set->crtc->fb->pixel_format) {
9803                         config->mode_changed = true;
9804                 } else {
9805                         config->fb_changed = true;
9806                 }
9807         }
9808
9809         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9810                 config->fb_changed = true;
9811
9812         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9813                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9814                 drm_mode_debug_printmodeline(&set->crtc->mode);
9815                 drm_mode_debug_printmodeline(set->mode);
9816                 config->mode_changed = true;
9817         }
9818
9819         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9820                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9821 }
9822
9823 static int
9824 intel_modeset_stage_output_state(struct drm_device *dev,
9825                                  struct drm_mode_set *set,
9826                                  struct intel_set_config *config)
9827 {
9828         struct drm_crtc *new_crtc;
9829         struct intel_connector *connector;
9830         struct intel_encoder *encoder;
9831         int ro;
9832
9833         /* The upper layers ensure that we either disable a crtc or have a list
9834          * of connectors. For paranoia, double-check this. */
9835         WARN_ON(!set->fb && (set->num_connectors != 0));
9836         WARN_ON(set->fb && (set->num_connectors == 0));
9837
9838         list_for_each_entry(connector, &dev->mode_config.connector_list,
9839                             base.head) {
9840                 /* Otherwise traverse passed in connector list and get encoders
9841                  * for them. */
9842                 for (ro = 0; ro < set->num_connectors; ro++) {
9843                         if (set->connectors[ro] == &connector->base) {
9844                                 connector->new_encoder = connector->encoder;
9845                                 break;
9846                         }
9847                 }
9848
9849                 /* If we disable the crtc, disable all its connectors. Also, if
9850                  * the connector is on the changing crtc but not on the new
9851                  * connector list, disable it. */
9852                 if ((!set->fb || ro == set->num_connectors) &&
9853                     connector->base.encoder &&
9854                     connector->base.encoder->crtc == set->crtc) {
9855                         connector->new_encoder = NULL;
9856
9857                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9858                                 connector->base.base.id,
9859                                 drm_get_connector_name(&connector->base));
9860                 }
9861
9862
9863                 if (&connector->new_encoder->base != connector->base.encoder) {
9864                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9865                         config->mode_changed = true;
9866                 }
9867         }
9868         /* connector->new_encoder is now updated for all connectors. */
9869
9870         /* Update crtc of enabled connectors. */
9871         list_for_each_entry(connector, &dev->mode_config.connector_list,
9872                             base.head) {
9873                 if (!connector->new_encoder)
9874                         continue;
9875
9876                 new_crtc = connector->new_encoder->base.crtc;
9877
9878                 for (ro = 0; ro < set->num_connectors; ro++) {
9879                         if (set->connectors[ro] == &connector->base)
9880                                 new_crtc = set->crtc;
9881                 }
9882
9883                 /* Make sure the new CRTC will work with the encoder */
9884                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9885                                            new_crtc)) {
9886                         return -EINVAL;
9887                 }
9888                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9889
9890                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9891                         connector->base.base.id,
9892                         drm_get_connector_name(&connector->base),
9893                         new_crtc->base.id);
9894         }
9895
9896         /* Check for any encoders that needs to be disabled. */
9897         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9898                             base.head) {
9899                 list_for_each_entry(connector,
9900                                     &dev->mode_config.connector_list,
9901                                     base.head) {
9902                         if (connector->new_encoder == encoder) {
9903                                 WARN_ON(!connector->new_encoder->new_crtc);
9904
9905                                 goto next_encoder;
9906                         }
9907                 }
9908                 encoder->new_crtc = NULL;
9909 next_encoder:
9910                 /* Only now check for crtc changes so we don't miss encoders
9911                  * that will be disabled. */
9912                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9913                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9914                         config->mode_changed = true;
9915                 }
9916         }
9917         /* Now we've also updated encoder->new_crtc for all encoders. */
9918
9919         return 0;
9920 }
9921
9922 static int intel_crtc_set_config(struct drm_mode_set *set)
9923 {
9924         struct drm_device *dev;
9925         struct drm_mode_set save_set;
9926         struct intel_set_config *config;
9927         int ret;
9928
9929         BUG_ON(!set);
9930         BUG_ON(!set->crtc);
9931         BUG_ON(!set->crtc->helper_private);
9932
9933         /* Enforce sane interface api - has been abused by the fb helper. */
9934         BUG_ON(!set->mode && set->fb);
9935         BUG_ON(set->fb && set->num_connectors == 0);
9936
9937         if (set->fb) {
9938                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9939                                 set->crtc->base.id, set->fb->base.id,
9940                                 (int)set->num_connectors, set->x, set->y);
9941         } else {
9942                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9943         }
9944
9945         dev = set->crtc->dev;
9946
9947         ret = -ENOMEM;
9948         config = kzalloc(sizeof(*config), GFP_KERNEL);
9949         if (!config)
9950                 goto out_config;
9951
9952         ret = intel_set_config_save_state(dev, config);
9953         if (ret)
9954                 goto out_config;
9955
9956         save_set.crtc = set->crtc;
9957         save_set.mode = &set->crtc->mode;
9958         save_set.x = set->crtc->x;
9959         save_set.y = set->crtc->y;
9960         save_set.fb = set->crtc->fb;
9961
9962         /* Compute whether we need a full modeset, only an fb base update or no
9963          * change at all. In the future we might also check whether only the
9964          * mode changed, e.g. for LVDS where we only change the panel fitter in
9965          * such cases. */
9966         intel_set_config_compute_mode_changes(set, config);
9967
9968         ret = intel_modeset_stage_output_state(dev, set, config);
9969         if (ret)
9970                 goto fail;
9971
9972         if (config->mode_changed) {
9973                 ret = intel_set_mode(set->crtc, set->mode,
9974                                      set->x, set->y, set->fb);
9975         } else if (config->fb_changed) {
9976                 intel_crtc_wait_for_pending_flips(set->crtc);
9977
9978                 ret = intel_pipe_set_base(set->crtc,
9979                                           set->x, set->y, set->fb);
9980         }
9981
9982         if (ret) {
9983                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9984                               set->crtc->base.id, ret);
9985 fail:
9986                 intel_set_config_restore_state(dev, config);
9987
9988                 /* Try to restore the config */
9989                 if (config->mode_changed &&
9990                     intel_set_mode(save_set.crtc, save_set.mode,
9991                                    save_set.x, save_set.y, save_set.fb))
9992                         DRM_ERROR("failed to restore config after modeset failure\n");
9993         }
9994
9995 out_config:
9996         intel_set_config_free(config);
9997         return ret;
9998 }
9999
10000 static const struct drm_crtc_funcs intel_crtc_funcs = {
10001         .cursor_set = intel_crtc_cursor_set,
10002         .cursor_move = intel_crtc_cursor_move,
10003         .gamma_set = intel_crtc_gamma_set,
10004         .set_config = intel_crtc_set_config,
10005         .destroy = intel_crtc_destroy,
10006         .page_flip = intel_crtc_page_flip,
10007 };
10008
10009 static void intel_cpu_pll_init(struct drm_device *dev)
10010 {
10011         if (HAS_DDI(dev))
10012                 intel_ddi_pll_init(dev);
10013 }
10014
10015 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10016                                       struct intel_shared_dpll *pll,
10017                                       struct intel_dpll_hw_state *hw_state)
10018 {
10019         uint32_t val;
10020
10021         val = I915_READ(PCH_DPLL(pll->id));
10022         hw_state->dpll = val;
10023         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10024         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10025
10026         return val & DPLL_VCO_ENABLE;
10027 }
10028
10029 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10030                                   struct intel_shared_dpll *pll)
10031 {
10032         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10033         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10034 }
10035
10036 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10037                                 struct intel_shared_dpll *pll)
10038 {
10039         /* PCH refclock must be enabled first */
10040         assert_pch_refclk_enabled(dev_priv);
10041
10042         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10043
10044         /* Wait for the clocks to stabilize. */
10045         POSTING_READ(PCH_DPLL(pll->id));
10046         udelay(150);
10047
10048         /* The pixel multiplier can only be updated once the
10049          * DPLL is enabled and the clocks are stable.
10050          *
10051          * So write it again.
10052          */
10053         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10054         POSTING_READ(PCH_DPLL(pll->id));
10055         udelay(200);
10056 }
10057
10058 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10059                                  struct intel_shared_dpll *pll)
10060 {
10061         struct drm_device *dev = dev_priv->dev;
10062         struct intel_crtc *crtc;
10063
10064         /* Make sure no transcoder isn't still depending on us. */
10065         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10066                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10067                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10068         }
10069
10070         I915_WRITE(PCH_DPLL(pll->id), 0);
10071         POSTING_READ(PCH_DPLL(pll->id));
10072         udelay(200);
10073 }
10074
10075 static char *ibx_pch_dpll_names[] = {
10076         "PCH DPLL A",
10077         "PCH DPLL B",
10078 };
10079
10080 static void ibx_pch_dpll_init(struct drm_device *dev)
10081 {
10082         struct drm_i915_private *dev_priv = dev->dev_private;
10083         int i;
10084
10085         dev_priv->num_shared_dpll = 2;
10086
10087         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10088                 dev_priv->shared_dplls[i].id = i;
10089                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10090                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10091                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10092                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10093                 dev_priv->shared_dplls[i].get_hw_state =
10094                         ibx_pch_dpll_get_hw_state;
10095         }
10096 }
10097
10098 static void intel_shared_dpll_init(struct drm_device *dev)
10099 {
10100         struct drm_i915_private *dev_priv = dev->dev_private;
10101
10102         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10103                 ibx_pch_dpll_init(dev);
10104         else
10105                 dev_priv->num_shared_dpll = 0;
10106
10107         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10108         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10109                       dev_priv->num_shared_dpll);
10110 }
10111
10112 static void intel_crtc_init(struct drm_device *dev, int pipe)
10113 {
10114         drm_i915_private_t *dev_priv = dev->dev_private;
10115         struct intel_crtc *intel_crtc;
10116         int i;
10117
10118         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10119         if (intel_crtc == NULL)
10120                 return;
10121
10122         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10123
10124         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10125         for (i = 0; i < 256; i++) {
10126                 intel_crtc->lut_r[i] = i;
10127                 intel_crtc->lut_g[i] = i;
10128                 intel_crtc->lut_b[i] = i;
10129         }
10130
10131         /*
10132          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10133          * is hooked to plane B. Hence we want plane A feeding pipe B.
10134          */
10135         intel_crtc->pipe = pipe;
10136         intel_crtc->plane = pipe;
10137         if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10138                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10139                 intel_crtc->plane = !pipe;
10140         }
10141
10142         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10143                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10144         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10145         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10146
10147         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10148 }
10149
10150 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10151 {
10152         struct drm_encoder *encoder = connector->base.encoder;
10153
10154         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10155
10156         if (!encoder)
10157                 return INVALID_PIPE;
10158
10159         return to_intel_crtc(encoder->crtc)->pipe;
10160 }
10161
10162 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10163                                 struct drm_file *file)
10164 {
10165         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10166         struct drm_mode_object *drmmode_obj;
10167         struct intel_crtc *crtc;
10168
10169         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10170                 return -ENODEV;
10171
10172         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10173                         DRM_MODE_OBJECT_CRTC);
10174
10175         if (!drmmode_obj) {
10176                 DRM_ERROR("no such CRTC id\n");
10177                 return -ENOENT;
10178         }
10179
10180         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10181         pipe_from_crtc_id->pipe = crtc->pipe;
10182
10183         return 0;
10184 }
10185
10186 static int intel_encoder_clones(struct intel_encoder *encoder)
10187 {
10188         struct drm_device *dev = encoder->base.dev;
10189         struct intel_encoder *source_encoder;
10190         int index_mask = 0;
10191         int entry = 0;
10192
10193         list_for_each_entry(source_encoder,
10194                             &dev->mode_config.encoder_list, base.head) {
10195
10196                 if (encoder == source_encoder)
10197                         index_mask |= (1 << entry);
10198
10199                 /* Intel hw has only one MUX where enocoders could be cloned. */
10200                 if (encoder->cloneable && source_encoder->cloneable)
10201                         index_mask |= (1 << entry);
10202
10203                 entry++;
10204         }
10205
10206         return index_mask;
10207 }
10208
10209 static bool has_edp_a(struct drm_device *dev)
10210 {
10211         struct drm_i915_private *dev_priv = dev->dev_private;
10212
10213         if (!IS_MOBILE(dev))
10214                 return false;
10215
10216         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10217                 return false;
10218
10219         if (IS_GEN5(dev) &&
10220             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10221                 return false;
10222
10223         return true;
10224 }
10225
10226 static void intel_setup_outputs(struct drm_device *dev)
10227 {
10228         struct drm_i915_private *dev_priv = dev->dev_private;
10229         struct intel_encoder *encoder;
10230         bool dpd_is_edp = false;
10231
10232         intel_lvds_init(dev);
10233
10234         if (!IS_ULT(dev))
10235                 intel_crt_init(dev);
10236
10237         if (HAS_DDI(dev)) {
10238                 int found;
10239
10240                 /* Haswell uses DDI functions to detect digital outputs */
10241                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10242                 /* DDI A only supports eDP */
10243                 if (found)
10244                         intel_ddi_init(dev, PORT_A);
10245
10246                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10247                  * register */
10248                 found = I915_READ(SFUSE_STRAP);
10249
10250                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10251                         intel_ddi_init(dev, PORT_B);
10252                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10253                         intel_ddi_init(dev, PORT_C);
10254                 if (found & SFUSE_STRAP_DDID_DETECTED)
10255                         intel_ddi_init(dev, PORT_D);
10256         } else if (HAS_PCH_SPLIT(dev)) {
10257                 int found;
10258                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10259
10260                 if (has_edp_a(dev))
10261                         intel_dp_init(dev, DP_A, PORT_A);
10262
10263                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10264                         /* PCH SDVOB multiplex with HDMIB */
10265                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10266                         if (!found)
10267                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10268                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10269                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10270                 }
10271
10272                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10273                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10274
10275                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10276                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10277
10278                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10279                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10280
10281                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10282                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10283         } else if (IS_VALLEYVIEW(dev)) {
10284                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10285                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10286                                         PORT_B);
10287                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10288                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10289                 }
10290
10291                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10292                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10293                                         PORT_C);
10294                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10295                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10296                 }
10297
10298                 intel_dsi_init(dev);
10299         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10300                 bool found = false;
10301
10302                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10303                         DRM_DEBUG_KMS("probing SDVOB\n");
10304                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10305                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10306                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10307                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10308                         }
10309
10310                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10311                                 intel_dp_init(dev, DP_B, PORT_B);
10312                 }
10313
10314                 /* Before G4X SDVOC doesn't have its own detect register */
10315
10316                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10317                         DRM_DEBUG_KMS("probing SDVOC\n");
10318                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10319                 }
10320
10321                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10322
10323                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10324                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10325                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10326                         }
10327                         if (SUPPORTS_INTEGRATED_DP(dev))
10328                                 intel_dp_init(dev, DP_C, PORT_C);
10329                 }
10330
10331                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10332                     (I915_READ(DP_D) & DP_DETECTED))
10333                         intel_dp_init(dev, DP_D, PORT_D);
10334         } else if (IS_GEN2(dev))
10335                 intel_dvo_init(dev);
10336
10337         if (SUPPORTS_TV(dev))
10338                 intel_tv_init(dev);
10339
10340         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10341                 encoder->base.possible_crtcs = encoder->crtc_mask;
10342                 encoder->base.possible_clones =
10343                         intel_encoder_clones(encoder);
10344         }
10345
10346         intel_init_pch_refclk(dev);
10347
10348         drm_helper_move_panel_connectors_to_head(dev);
10349 }
10350
10351 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10352 {
10353         drm_framebuffer_cleanup(&fb->base);
10354         WARN_ON(!fb->obj->framebuffer_references--);
10355         drm_gem_object_unreference_unlocked(&fb->obj->base);
10356 }
10357
10358 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10359 {
10360         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10361
10362         intel_framebuffer_fini(intel_fb);
10363         kfree(intel_fb);
10364 }
10365
10366 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10367                                                 struct drm_file *file,
10368                                                 unsigned int *handle)
10369 {
10370         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10371         struct drm_i915_gem_object *obj = intel_fb->obj;
10372
10373         return drm_gem_handle_create(file, &obj->base, handle);
10374 }
10375
10376 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10377         .destroy = intel_user_framebuffer_destroy,
10378         .create_handle = intel_user_framebuffer_create_handle,
10379 };
10380
10381 int intel_framebuffer_init(struct drm_device *dev,
10382                            struct intel_framebuffer *intel_fb,
10383                            struct drm_mode_fb_cmd2 *mode_cmd,
10384                            struct drm_i915_gem_object *obj)
10385 {
10386         int aligned_height, tile_height;
10387         int pitch_limit;
10388         int ret;
10389
10390         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10391
10392         if (obj->tiling_mode == I915_TILING_Y) {
10393                 DRM_DEBUG("hardware does not support tiling Y\n");
10394                 return -EINVAL;
10395         }
10396
10397         if (mode_cmd->pitches[0] & 63) {
10398                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10399                           mode_cmd->pitches[0]);
10400                 return -EINVAL;
10401         }
10402
10403         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10404                 pitch_limit = 32*1024;
10405         } else if (INTEL_INFO(dev)->gen >= 4) {
10406                 if (obj->tiling_mode)
10407                         pitch_limit = 16*1024;
10408                 else
10409                         pitch_limit = 32*1024;
10410         } else if (INTEL_INFO(dev)->gen >= 3) {
10411                 if (obj->tiling_mode)
10412                         pitch_limit = 8*1024;
10413                 else
10414                         pitch_limit = 16*1024;
10415         } else
10416                 /* XXX DSPC is limited to 4k tiled */
10417                 pitch_limit = 8*1024;
10418
10419         if (mode_cmd->pitches[0] > pitch_limit) {
10420                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10421                           obj->tiling_mode ? "tiled" : "linear",
10422                           mode_cmd->pitches[0], pitch_limit);
10423                 return -EINVAL;
10424         }
10425
10426         if (obj->tiling_mode != I915_TILING_NONE &&
10427             mode_cmd->pitches[0] != obj->stride) {
10428                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10429                           mode_cmd->pitches[0], obj->stride);
10430                 return -EINVAL;
10431         }
10432
10433         /* Reject formats not supported by any plane early. */
10434         switch (mode_cmd->pixel_format) {
10435         case DRM_FORMAT_C8:
10436         case DRM_FORMAT_RGB565:
10437         case DRM_FORMAT_XRGB8888:
10438         case DRM_FORMAT_ARGB8888:
10439                 break;
10440         case DRM_FORMAT_XRGB1555:
10441         case DRM_FORMAT_ARGB1555:
10442                 if (INTEL_INFO(dev)->gen > 3) {
10443                         DRM_DEBUG("unsupported pixel format: %s\n",
10444                                   drm_get_format_name(mode_cmd->pixel_format));
10445                         return -EINVAL;
10446                 }
10447                 break;
10448         case DRM_FORMAT_XBGR8888:
10449         case DRM_FORMAT_ABGR8888:
10450         case DRM_FORMAT_XRGB2101010:
10451         case DRM_FORMAT_ARGB2101010:
10452         case DRM_FORMAT_XBGR2101010:
10453         case DRM_FORMAT_ABGR2101010:
10454                 if (INTEL_INFO(dev)->gen < 4) {
10455                         DRM_DEBUG("unsupported pixel format: %s\n",
10456                                   drm_get_format_name(mode_cmd->pixel_format));
10457                         return -EINVAL;
10458                 }
10459                 break;
10460         case DRM_FORMAT_YUYV:
10461         case DRM_FORMAT_UYVY:
10462         case DRM_FORMAT_YVYU:
10463         case DRM_FORMAT_VYUY:
10464                 if (INTEL_INFO(dev)->gen < 5) {
10465                         DRM_DEBUG("unsupported pixel format: %s\n",
10466                                   drm_get_format_name(mode_cmd->pixel_format));
10467                         return -EINVAL;
10468                 }
10469                 break;
10470         default:
10471                 DRM_DEBUG("unsupported pixel format: %s\n",
10472                           drm_get_format_name(mode_cmd->pixel_format));
10473                 return -EINVAL;
10474         }
10475
10476         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10477         if (mode_cmd->offsets[0] != 0)
10478                 return -EINVAL;
10479
10480         tile_height = IS_GEN2(dev) ? 16 : 8;
10481         aligned_height = ALIGN(mode_cmd->height,
10482                                obj->tiling_mode ? tile_height : 1);
10483         /* FIXME drm helper for size checks (especially planar formats)? */
10484         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10485                 return -EINVAL;
10486
10487         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10488         intel_fb->obj = obj;
10489         intel_fb->obj->framebuffer_references++;
10490
10491         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10492         if (ret) {
10493                 DRM_ERROR("framebuffer init failed %d\n", ret);
10494                 return ret;
10495         }
10496
10497         return 0;
10498 }
10499
10500 static struct drm_framebuffer *
10501 intel_user_framebuffer_create(struct drm_device *dev,
10502                               struct drm_file *filp,
10503                               struct drm_mode_fb_cmd2 *mode_cmd)
10504 {
10505         struct drm_i915_gem_object *obj;
10506
10507         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10508                                                 mode_cmd->handles[0]));
10509         if (&obj->base == NULL)
10510                 return ERR_PTR(-ENOENT);
10511
10512         return intel_framebuffer_create(dev, mode_cmd, obj);
10513 }
10514
10515 #ifndef CONFIG_DRM_I915_FBDEV
10516 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10517 {
10518 }
10519 #endif
10520
10521 static const struct drm_mode_config_funcs intel_mode_funcs = {
10522         .fb_create = intel_user_framebuffer_create,
10523         .output_poll_changed = intel_fbdev_output_poll_changed,
10524 };
10525
10526 /* Set up chip specific display functions */
10527 static void intel_init_display(struct drm_device *dev)
10528 {
10529         struct drm_i915_private *dev_priv = dev->dev_private;
10530
10531         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10532                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10533         else if (IS_VALLEYVIEW(dev))
10534                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10535         else if (IS_PINEVIEW(dev))
10536                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10537         else
10538                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10539
10540         if (HAS_DDI(dev)) {
10541                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10542                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10543                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10544                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10545                 dev_priv->display.off = haswell_crtc_off;
10546                 dev_priv->display.update_plane = ironlake_update_plane;
10547         } else if (HAS_PCH_SPLIT(dev)) {
10548                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10549                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10550                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10551                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10552                 dev_priv->display.off = ironlake_crtc_off;
10553                 dev_priv->display.update_plane = ironlake_update_plane;
10554         } else if (IS_VALLEYVIEW(dev)) {
10555                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10556                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10557                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10558                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10559                 dev_priv->display.off = i9xx_crtc_off;
10560                 dev_priv->display.update_plane = i9xx_update_plane;
10561         } else {
10562                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10563                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10564                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10565                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10566                 dev_priv->display.off = i9xx_crtc_off;
10567                 dev_priv->display.update_plane = i9xx_update_plane;
10568         }
10569
10570         /* Returns the core display clock speed */
10571         if (IS_VALLEYVIEW(dev))
10572                 dev_priv->display.get_display_clock_speed =
10573                         valleyview_get_display_clock_speed;
10574         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10575                 dev_priv->display.get_display_clock_speed =
10576                         i945_get_display_clock_speed;
10577         else if (IS_I915G(dev))
10578                 dev_priv->display.get_display_clock_speed =
10579                         i915_get_display_clock_speed;
10580         else if (IS_I945GM(dev) || IS_845G(dev))
10581                 dev_priv->display.get_display_clock_speed =
10582                         i9xx_misc_get_display_clock_speed;
10583         else if (IS_PINEVIEW(dev))
10584                 dev_priv->display.get_display_clock_speed =
10585                         pnv_get_display_clock_speed;
10586         else if (IS_I915GM(dev))
10587                 dev_priv->display.get_display_clock_speed =
10588                         i915gm_get_display_clock_speed;
10589         else if (IS_I865G(dev))
10590                 dev_priv->display.get_display_clock_speed =
10591                         i865_get_display_clock_speed;
10592         else if (IS_I85X(dev))
10593                 dev_priv->display.get_display_clock_speed =
10594                         i855_get_display_clock_speed;
10595         else /* 852, 830 */
10596                 dev_priv->display.get_display_clock_speed =
10597                         i830_get_display_clock_speed;
10598
10599         if (HAS_PCH_SPLIT(dev)) {
10600                 if (IS_GEN5(dev)) {
10601                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10602                         dev_priv->display.write_eld = ironlake_write_eld;
10603                 } else if (IS_GEN6(dev)) {
10604                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10605                         dev_priv->display.write_eld = ironlake_write_eld;
10606                 } else if (IS_IVYBRIDGE(dev)) {
10607                         /* FIXME: detect B0+ stepping and use auto training */
10608                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10609                         dev_priv->display.write_eld = ironlake_write_eld;
10610                         dev_priv->display.modeset_global_resources =
10611                                 ivb_modeset_global_resources;
10612                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10613                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10614                         dev_priv->display.write_eld = haswell_write_eld;
10615                         dev_priv->display.modeset_global_resources =
10616                                 haswell_modeset_global_resources;
10617                 }
10618         } else if (IS_G4X(dev)) {
10619                 dev_priv->display.write_eld = g4x_write_eld;
10620         } else if (IS_VALLEYVIEW(dev)) {
10621                 dev_priv->display.modeset_global_resources =
10622                         valleyview_modeset_global_resources;
10623                 dev_priv->display.write_eld = ironlake_write_eld;
10624         }
10625
10626         /* Default just returns -ENODEV to indicate unsupported */
10627         dev_priv->display.queue_flip = intel_default_queue_flip;
10628
10629         switch (INTEL_INFO(dev)->gen) {
10630         case 2:
10631                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10632                 break;
10633
10634         case 3:
10635                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10636                 break;
10637
10638         case 4:
10639         case 5:
10640                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10641                 break;
10642
10643         case 6:
10644                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10645                 break;
10646         case 7:
10647         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10648                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10649                 break;
10650         }
10651
10652         intel_panel_init_backlight_funcs(dev);
10653 }
10654
10655 /*
10656  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10657  * resume, or other times.  This quirk makes sure that's the case for
10658  * affected systems.
10659  */
10660 static void quirk_pipea_force(struct drm_device *dev)
10661 {
10662         struct drm_i915_private *dev_priv = dev->dev_private;
10663
10664         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10665         DRM_INFO("applying pipe a force quirk\n");
10666 }
10667
10668 /*
10669  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10670  */
10671 static void quirk_ssc_force_disable(struct drm_device *dev)
10672 {
10673         struct drm_i915_private *dev_priv = dev->dev_private;
10674         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10675         DRM_INFO("applying lvds SSC disable quirk\n");
10676 }
10677
10678 /*
10679  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10680  * brightness value
10681  */
10682 static void quirk_invert_brightness(struct drm_device *dev)
10683 {
10684         struct drm_i915_private *dev_priv = dev->dev_private;
10685         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10686         DRM_INFO("applying inverted panel brightness quirk\n");
10687 }
10688
10689 struct intel_quirk {
10690         int device;
10691         int subsystem_vendor;
10692         int subsystem_device;
10693         void (*hook)(struct drm_device *dev);
10694 };
10695
10696 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10697 struct intel_dmi_quirk {
10698         void (*hook)(struct drm_device *dev);
10699         const struct dmi_system_id (*dmi_id_list)[];
10700 };
10701
10702 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10703 {
10704         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10705         return 1;
10706 }
10707
10708 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10709         {
10710                 .dmi_id_list = &(const struct dmi_system_id[]) {
10711                         {
10712                                 .callback = intel_dmi_reverse_brightness,
10713                                 .ident = "NCR Corporation",
10714                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10715                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10716                                 },
10717                         },
10718                         { }  /* terminating entry */
10719                 },
10720                 .hook = quirk_invert_brightness,
10721         },
10722 };
10723
10724 static struct intel_quirk intel_quirks[] = {
10725         /* HP Mini needs pipe A force quirk (LP: #322104) */
10726         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10727
10728         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10729         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10730
10731         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10732         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10733
10734         /* 830 needs to leave pipe A & dpll A up */
10735         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10736
10737         /* Lenovo U160 cannot use SSC on LVDS */
10738         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10739
10740         /* Sony Vaio Y cannot use SSC on LVDS */
10741         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10742
10743         /*
10744          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10745          * seem to use inverted backlight PWM.
10746          */
10747         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10748 };
10749
10750 static void intel_init_quirks(struct drm_device *dev)
10751 {
10752         struct pci_dev *d = dev->pdev;
10753         int i;
10754
10755         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10756                 struct intel_quirk *q = &intel_quirks[i];
10757
10758                 if (d->device == q->device &&
10759                     (d->subsystem_vendor == q->subsystem_vendor ||
10760                      q->subsystem_vendor == PCI_ANY_ID) &&
10761                     (d->subsystem_device == q->subsystem_device ||
10762                      q->subsystem_device == PCI_ANY_ID))
10763                         q->hook(dev);
10764         }
10765         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10766                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10767                         intel_dmi_quirks[i].hook(dev);
10768         }
10769 }
10770
10771 /* Disable the VGA plane that we never use */
10772 static void i915_disable_vga(struct drm_device *dev)
10773 {
10774         struct drm_i915_private *dev_priv = dev->dev_private;
10775         u8 sr1;
10776         u32 vga_reg = i915_vgacntrl_reg(dev);
10777
10778         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10779         outb(SR01, VGA_SR_INDEX);
10780         sr1 = inb(VGA_SR_DATA);
10781         outb(sr1 | 1<<5, VGA_SR_DATA);
10782         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10783         udelay(300);
10784
10785         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10786         POSTING_READ(vga_reg);
10787 }
10788
10789 void intel_modeset_init_hw(struct drm_device *dev)
10790 {
10791         struct drm_i915_private *dev_priv = dev->dev_private;
10792
10793         intel_prepare_ddi(dev);
10794
10795         intel_init_clock_gating(dev);
10796
10797         /* Enable the CRI clock source so we can get at the display */
10798         if (IS_VALLEYVIEW(dev))
10799                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10800                            DPLL_INTEGRATED_CRI_CLK_VLV);
10801
10802         intel_init_dpio(dev);
10803
10804         mutex_lock(&dev->struct_mutex);
10805         intel_enable_gt_powersave(dev);
10806         mutex_unlock(&dev->struct_mutex);
10807 }
10808
10809 void intel_modeset_suspend_hw(struct drm_device *dev)
10810 {
10811         intel_suspend_hw(dev);
10812 }
10813
10814 void intel_modeset_init(struct drm_device *dev)
10815 {
10816         struct drm_i915_private *dev_priv = dev->dev_private;
10817         int i, j, ret;
10818
10819         drm_mode_config_init(dev);
10820
10821         dev->mode_config.min_width = 0;
10822         dev->mode_config.min_height = 0;
10823
10824         dev->mode_config.preferred_depth = 24;
10825         dev->mode_config.prefer_shadow = 1;
10826
10827         dev->mode_config.funcs = &intel_mode_funcs;
10828
10829         intel_init_quirks(dev);
10830
10831         intel_init_pm(dev);
10832
10833         if (INTEL_INFO(dev)->num_pipes == 0)
10834                 return;
10835
10836         intel_init_display(dev);
10837
10838         if (IS_GEN2(dev)) {
10839                 dev->mode_config.max_width = 2048;
10840                 dev->mode_config.max_height = 2048;
10841         } else if (IS_GEN3(dev)) {
10842                 dev->mode_config.max_width = 4096;
10843                 dev->mode_config.max_height = 4096;
10844         } else {
10845                 dev->mode_config.max_width = 8192;
10846                 dev->mode_config.max_height = 8192;
10847         }
10848         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10849
10850         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10851                       INTEL_INFO(dev)->num_pipes,
10852                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10853
10854         for_each_pipe(i) {
10855                 intel_crtc_init(dev, i);
10856                 for (j = 0; j < dev_priv->num_plane; j++) {
10857                         ret = intel_plane_init(dev, i, j);
10858                         if (ret)
10859                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10860                                               pipe_name(i), sprite_name(i, j), ret);
10861                 }
10862         }
10863
10864         intel_cpu_pll_init(dev);
10865         intel_shared_dpll_init(dev);
10866
10867         /* Just disable it once at startup */
10868         i915_disable_vga(dev);
10869         intel_setup_outputs(dev);
10870
10871         /* Just in case the BIOS is doing something questionable. */
10872         intel_disable_fbc(dev);
10873 }
10874
10875 static void
10876 intel_connector_break_all_links(struct intel_connector *connector)
10877 {
10878         connector->base.dpms = DRM_MODE_DPMS_OFF;
10879         connector->base.encoder = NULL;
10880         connector->encoder->connectors_active = false;
10881         connector->encoder->base.crtc = NULL;
10882 }
10883
10884 static void intel_enable_pipe_a(struct drm_device *dev)
10885 {
10886         struct intel_connector *connector;
10887         struct drm_connector *crt = NULL;
10888         struct intel_load_detect_pipe load_detect_temp;
10889
10890         /* We can't just switch on the pipe A, we need to set things up with a
10891          * proper mode and output configuration. As a gross hack, enable pipe A
10892          * by enabling the load detect pipe once. */
10893         list_for_each_entry(connector,
10894                             &dev->mode_config.connector_list,
10895                             base.head) {
10896                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10897                         crt = &connector->base;
10898                         break;
10899                 }
10900         }
10901
10902         if (!crt)
10903                 return;
10904
10905         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10906                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10907
10908
10909 }
10910
10911 static bool
10912 intel_check_plane_mapping(struct intel_crtc *crtc)
10913 {
10914         struct drm_device *dev = crtc->base.dev;
10915         struct drm_i915_private *dev_priv = dev->dev_private;
10916         u32 reg, val;
10917
10918         if (INTEL_INFO(dev)->num_pipes == 1)
10919                 return true;
10920
10921         reg = DSPCNTR(!crtc->plane);
10922         val = I915_READ(reg);
10923
10924         if ((val & DISPLAY_PLANE_ENABLE) &&
10925             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10926                 return false;
10927
10928         return true;
10929 }
10930
10931 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10932 {
10933         struct drm_device *dev = crtc->base.dev;
10934         struct drm_i915_private *dev_priv = dev->dev_private;
10935         u32 reg;
10936
10937         /* Clear any frame start delays used for debugging left by the BIOS */
10938         reg = PIPECONF(crtc->config.cpu_transcoder);
10939         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10940
10941         /* We need to sanitize the plane -> pipe mapping first because this will
10942          * disable the crtc (and hence change the state) if it is wrong. Note
10943          * that gen4+ has a fixed plane -> pipe mapping.  */
10944         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10945                 struct intel_connector *connector;
10946                 bool plane;
10947
10948                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10949                               crtc->base.base.id);
10950
10951                 /* Pipe has the wrong plane attached and the plane is active.
10952                  * Temporarily change the plane mapping and disable everything
10953                  * ...  */
10954                 plane = crtc->plane;
10955                 crtc->plane = !plane;
10956                 dev_priv->display.crtc_disable(&crtc->base);
10957                 crtc->plane = plane;
10958
10959                 /* ... and break all links. */
10960                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10961                                     base.head) {
10962                         if (connector->encoder->base.crtc != &crtc->base)
10963                                 continue;
10964
10965                         intel_connector_break_all_links(connector);
10966                 }
10967
10968                 WARN_ON(crtc->active);
10969                 crtc->base.enabled = false;
10970         }
10971
10972         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10973             crtc->pipe == PIPE_A && !crtc->active) {
10974                 /* BIOS forgot to enable pipe A, this mostly happens after
10975                  * resume. Force-enable the pipe to fix this, the update_dpms
10976                  * call below we restore the pipe to the right state, but leave
10977                  * the required bits on. */
10978                 intel_enable_pipe_a(dev);
10979         }
10980
10981         /* Adjust the state of the output pipe according to whether we
10982          * have active connectors/encoders. */
10983         intel_crtc_update_dpms(&crtc->base);
10984
10985         if (crtc->active != crtc->base.enabled) {
10986                 struct intel_encoder *encoder;
10987
10988                 /* This can happen either due to bugs in the get_hw_state
10989                  * functions or because the pipe is force-enabled due to the
10990                  * pipe A quirk. */
10991                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10992                               crtc->base.base.id,
10993                               crtc->base.enabled ? "enabled" : "disabled",
10994                               crtc->active ? "enabled" : "disabled");
10995
10996                 crtc->base.enabled = crtc->active;
10997
10998                 /* Because we only establish the connector -> encoder ->
10999                  * crtc links if something is active, this means the
11000                  * crtc is now deactivated. Break the links. connector
11001                  * -> encoder links are only establish when things are
11002                  *  actually up, hence no need to break them. */
11003                 WARN_ON(crtc->active);
11004
11005                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11006                         WARN_ON(encoder->connectors_active);
11007                         encoder->base.crtc = NULL;
11008                 }
11009         }
11010 }
11011
11012 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11013 {
11014         struct intel_connector *connector;
11015         struct drm_device *dev = encoder->base.dev;
11016
11017         /* We need to check both for a crtc link (meaning that the
11018          * encoder is active and trying to read from a pipe) and the
11019          * pipe itself being active. */
11020         bool has_active_crtc = encoder->base.crtc &&
11021                 to_intel_crtc(encoder->base.crtc)->active;
11022
11023         if (encoder->connectors_active && !has_active_crtc) {
11024                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11025                               encoder->base.base.id,
11026                               drm_get_encoder_name(&encoder->base));
11027
11028                 /* Connector is active, but has no active pipe. This is
11029                  * fallout from our resume register restoring. Disable
11030                  * the encoder manually again. */
11031                 if (encoder->base.crtc) {
11032                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11033                                       encoder->base.base.id,
11034                                       drm_get_encoder_name(&encoder->base));
11035                         encoder->disable(encoder);
11036                 }
11037
11038                 /* Inconsistent output/port/pipe state happens presumably due to
11039                  * a bug in one of the get_hw_state functions. Or someplace else
11040                  * in our code, like the register restore mess on resume. Clamp
11041                  * things to off as a safer default. */
11042                 list_for_each_entry(connector,
11043                                     &dev->mode_config.connector_list,
11044                                     base.head) {
11045                         if (connector->encoder != encoder)
11046                                 continue;
11047
11048                         intel_connector_break_all_links(connector);
11049                 }
11050         }
11051         /* Enabled encoders without active connectors will be fixed in
11052          * the crtc fixup. */
11053 }
11054
11055 void i915_redisable_vga(struct drm_device *dev)
11056 {
11057         struct drm_i915_private *dev_priv = dev->dev_private;
11058         u32 vga_reg = i915_vgacntrl_reg(dev);
11059
11060         /* This function can be called both from intel_modeset_setup_hw_state or
11061          * at a very early point in our resume sequence, where the power well
11062          * structures are not yet restored. Since this function is at a very
11063          * paranoid "someone might have enabled VGA while we were not looking"
11064          * level, just check if the power well is enabled instead of trying to
11065          * follow the "don't touch the power well if we don't need it" policy
11066          * the rest of the driver uses. */
11067         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11068             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11069                 return;
11070
11071         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11072                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11073                 i915_disable_vga(dev);
11074         }
11075 }
11076
11077 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11078 {
11079         struct drm_i915_private *dev_priv = dev->dev_private;
11080         enum pipe pipe;
11081         struct intel_crtc *crtc;
11082         struct intel_encoder *encoder;
11083         struct intel_connector *connector;
11084         int i;
11085
11086         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11087                             base.head) {
11088                 memset(&crtc->config, 0, sizeof(crtc->config));
11089
11090                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11091                                                                  &crtc->config);
11092
11093                 crtc->base.enabled = crtc->active;
11094                 crtc->primary_enabled = crtc->active;
11095
11096                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11097                               crtc->base.base.id,
11098                               crtc->active ? "enabled" : "disabled");
11099         }
11100
11101         /* FIXME: Smash this into the new shared dpll infrastructure. */
11102         if (HAS_DDI(dev))
11103                 intel_ddi_setup_hw_pll_state(dev);
11104
11105         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11106                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11107
11108                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11109                 pll->active = 0;
11110                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11111                                     base.head) {
11112                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11113                                 pll->active++;
11114                 }
11115                 pll->refcount = pll->active;
11116
11117                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11118                               pll->name, pll->refcount, pll->on);
11119         }
11120
11121         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11122                             base.head) {
11123                 pipe = 0;
11124
11125                 if (encoder->get_hw_state(encoder, &pipe)) {
11126                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11127                         encoder->base.crtc = &crtc->base;
11128                         encoder->get_config(encoder, &crtc->config);
11129                 } else {
11130                         encoder->base.crtc = NULL;
11131                 }
11132
11133                 encoder->connectors_active = false;
11134                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11135                               encoder->base.base.id,
11136                               drm_get_encoder_name(&encoder->base),
11137                               encoder->base.crtc ? "enabled" : "disabled",
11138                               pipe_name(pipe));
11139         }
11140
11141         list_for_each_entry(connector, &dev->mode_config.connector_list,
11142                             base.head) {
11143                 if (connector->get_hw_state(connector)) {
11144                         connector->base.dpms = DRM_MODE_DPMS_ON;
11145                         connector->encoder->connectors_active = true;
11146                         connector->base.encoder = &connector->encoder->base;
11147                 } else {
11148                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11149                         connector->base.encoder = NULL;
11150                 }
11151                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11152                               connector->base.base.id,
11153                               drm_get_connector_name(&connector->base),
11154                               connector->base.encoder ? "enabled" : "disabled");
11155         }
11156 }
11157
11158 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11159  * and i915 state tracking structures. */
11160 void intel_modeset_setup_hw_state(struct drm_device *dev,
11161                                   bool force_restore)
11162 {
11163         struct drm_i915_private *dev_priv = dev->dev_private;
11164         enum pipe pipe;
11165         struct intel_crtc *crtc;
11166         struct intel_encoder *encoder;
11167         int i;
11168
11169         intel_modeset_readout_hw_state(dev);
11170
11171         /*
11172          * Now that we have the config, copy it to each CRTC struct
11173          * Note that this could go away if we move to using crtc_config
11174          * checking everywhere.
11175          */
11176         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11177                             base.head) {
11178                 if (crtc->active && i915_fastboot) {
11179                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11180
11181                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11182                                       crtc->base.base.id);
11183                         drm_mode_debug_printmodeline(&crtc->base.mode);
11184                 }
11185         }
11186
11187         /* HW state is read out, now we need to sanitize this mess. */
11188         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11189                             base.head) {
11190                 intel_sanitize_encoder(encoder);
11191         }
11192
11193         for_each_pipe(pipe) {
11194                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11195                 intel_sanitize_crtc(crtc);
11196                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11197         }
11198
11199         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11200                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11201
11202                 if (!pll->on || pll->active)
11203                         continue;
11204
11205                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11206
11207                 pll->disable(dev_priv, pll);
11208                 pll->on = false;
11209         }
11210
11211         if (IS_HASWELL(dev))
11212                 ilk_wm_get_hw_state(dev);
11213
11214         if (force_restore) {
11215                 i915_redisable_vga(dev);
11216
11217                 /*
11218                  * We need to use raw interfaces for restoring state to avoid
11219                  * checking (bogus) intermediate states.
11220                  */
11221                 for_each_pipe(pipe) {
11222                         struct drm_crtc *crtc =
11223                                 dev_priv->pipe_to_crtc_mapping[pipe];
11224
11225                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11226                                          crtc->fb);
11227                 }
11228         } else {
11229                 intel_modeset_update_staged_output_state(dev);
11230         }
11231
11232         intel_modeset_check_state(dev);
11233 }
11234
11235 void intel_modeset_gem_init(struct drm_device *dev)
11236 {
11237         intel_modeset_init_hw(dev);
11238
11239         intel_setup_overlay(dev);
11240
11241         drm_modeset_lock_all(dev);
11242         drm_mode_config_reset(dev);
11243         intel_modeset_setup_hw_state(dev, false);
11244         drm_modeset_unlock_all(dev);
11245 }
11246
11247 void intel_modeset_cleanup(struct drm_device *dev)
11248 {
11249         struct drm_i915_private *dev_priv = dev->dev_private;
11250         struct drm_crtc *crtc;
11251         struct drm_connector *connector;
11252
11253         /*
11254          * Interrupts and polling as the first thing to avoid creating havoc.
11255          * Too much stuff here (turning of rps, connectors, ...) would
11256          * experience fancy races otherwise.
11257          */
11258         drm_irq_uninstall(dev);
11259         cancel_work_sync(&dev_priv->hotplug_work);
11260         /*
11261          * Due to the hpd irq storm handling the hotplug work can re-arm the
11262          * poll handlers. Hence disable polling after hpd handling is shut down.
11263          */
11264         drm_kms_helper_poll_fini(dev);
11265
11266         mutex_lock(&dev->struct_mutex);
11267
11268         intel_unregister_dsm_handler();
11269
11270         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11271                 /* Skip inactive CRTCs */
11272                 if (!crtc->fb)
11273                         continue;
11274
11275                 intel_increase_pllclock(crtc);
11276         }
11277
11278         intel_disable_fbc(dev);
11279
11280         intel_disable_gt_powersave(dev);
11281
11282         ironlake_teardown_rc6(dev);
11283
11284         mutex_unlock(&dev->struct_mutex);
11285
11286         /* flush any delayed tasks or pending work */
11287         flush_scheduled_work();
11288
11289         /* destroy the backlight and sysfs files before encoders/connectors */
11290         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11291                 intel_panel_destroy_backlight(connector);
11292                 drm_sysfs_connector_remove(connector);
11293         }
11294
11295         drm_mode_config_cleanup(dev);
11296
11297         intel_cleanup_overlay(dev);
11298 }
11299
11300 /*
11301  * Return which encoder is currently attached for connector.
11302  */
11303 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11304 {
11305         return &intel_attached_encoder(connector)->base;
11306 }
11307
11308 void intel_connector_attach_encoder(struct intel_connector *connector,
11309                                     struct intel_encoder *encoder)
11310 {
11311         connector->encoder = encoder;
11312         drm_mode_connector_attach_encoder(&connector->base,
11313                                           &encoder->base);
11314 }
11315
11316 /*
11317  * set vga decode state - true == enable VGA decode
11318  */
11319 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11320 {
11321         struct drm_i915_private *dev_priv = dev->dev_private;
11322         u16 gmch_ctrl;
11323
11324         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11325         if (state)
11326                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11327         else
11328                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11329         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11330         return 0;
11331 }
11332
11333 struct intel_display_error_state {
11334
11335         u32 power_well_driver;
11336
11337         int num_transcoders;
11338
11339         struct intel_cursor_error_state {
11340                 u32 control;
11341                 u32 position;
11342                 u32 base;
11343                 u32 size;
11344         } cursor[I915_MAX_PIPES];
11345
11346         struct intel_pipe_error_state {
11347                 bool power_domain_on;
11348                 u32 source;
11349         } pipe[I915_MAX_PIPES];
11350
11351         struct intel_plane_error_state {
11352                 u32 control;
11353                 u32 stride;
11354                 u32 size;
11355                 u32 pos;
11356                 u32 addr;
11357                 u32 surface;
11358                 u32 tile_offset;
11359         } plane[I915_MAX_PIPES];
11360
11361         struct intel_transcoder_error_state {
11362                 bool power_domain_on;
11363                 enum transcoder cpu_transcoder;
11364
11365                 u32 conf;
11366
11367                 u32 htotal;
11368                 u32 hblank;
11369                 u32 hsync;
11370                 u32 vtotal;
11371                 u32 vblank;
11372                 u32 vsync;
11373         } transcoder[4];
11374 };
11375
11376 struct intel_display_error_state *
11377 intel_display_capture_error_state(struct drm_device *dev)
11378 {
11379         drm_i915_private_t *dev_priv = dev->dev_private;
11380         struct intel_display_error_state *error;
11381         int transcoders[] = {
11382                 TRANSCODER_A,
11383                 TRANSCODER_B,
11384                 TRANSCODER_C,
11385                 TRANSCODER_EDP,
11386         };
11387         int i;
11388
11389         if (INTEL_INFO(dev)->num_pipes == 0)
11390                 return NULL;
11391
11392         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11393         if (error == NULL)
11394                 return NULL;
11395
11396         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11397                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11398
11399         for_each_pipe(i) {
11400                 error->pipe[i].power_domain_on =
11401                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11402                 if (!error->pipe[i].power_domain_on)
11403                         continue;
11404
11405                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11406                         error->cursor[i].control = I915_READ(CURCNTR(i));
11407                         error->cursor[i].position = I915_READ(CURPOS(i));
11408                         error->cursor[i].base = I915_READ(CURBASE(i));
11409                 } else {
11410                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11411                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11412                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11413                 }
11414
11415                 error->plane[i].control = I915_READ(DSPCNTR(i));
11416                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11417                 if (INTEL_INFO(dev)->gen <= 3) {
11418                         error->plane[i].size = I915_READ(DSPSIZE(i));
11419                         error->plane[i].pos = I915_READ(DSPPOS(i));
11420                 }
11421                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11422                         error->plane[i].addr = I915_READ(DSPADDR(i));
11423                 if (INTEL_INFO(dev)->gen >= 4) {
11424                         error->plane[i].surface = I915_READ(DSPSURF(i));
11425                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11426                 }
11427
11428                 error->pipe[i].source = I915_READ(PIPESRC(i));
11429         }
11430
11431         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11432         if (HAS_DDI(dev_priv->dev))
11433                 error->num_transcoders++; /* Account for eDP. */
11434
11435         for (i = 0; i < error->num_transcoders; i++) {
11436                 enum transcoder cpu_transcoder = transcoders[i];
11437
11438                 error->transcoder[i].power_domain_on =
11439                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11440                 if (!error->transcoder[i].power_domain_on)
11441                         continue;
11442
11443                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11444
11445                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11446                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11447                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11448                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11449                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11450                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11451                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11452         }
11453
11454         return error;
11455 }
11456
11457 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11458
11459 void
11460 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11461                                 struct drm_device *dev,
11462                                 struct intel_display_error_state *error)
11463 {
11464         int i;
11465
11466         if (!error)
11467                 return;
11468
11469         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11470         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11471                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11472                            error->power_well_driver);
11473         for_each_pipe(i) {
11474                 err_printf(m, "Pipe [%d]:\n", i);
11475                 err_printf(m, "  Power: %s\n",
11476                            error->pipe[i].power_domain_on ? "on" : "off");
11477                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11478
11479                 err_printf(m, "Plane [%d]:\n", i);
11480                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11481                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11482                 if (INTEL_INFO(dev)->gen <= 3) {
11483                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11484                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11485                 }
11486                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11487                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11488                 if (INTEL_INFO(dev)->gen >= 4) {
11489                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11490                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11491                 }
11492
11493                 err_printf(m, "Cursor [%d]:\n", i);
11494                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11495                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11496                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11497         }
11498
11499         for (i = 0; i < error->num_transcoders; i++) {
11500                 err_printf(m, "CPU transcoder: %c\n",
11501                            transcoder_name(error->transcoder[i].cpu_transcoder));
11502                 err_printf(m, "  Power: %s\n",
11503                            error->transcoder[i].power_domain_on ? "on" : "off");
11504                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11505                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11506                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11507                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11508                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11509                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11510                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11511         }
11512 }