drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 364                                                 int refclk)
 365 {
 366         struct drm_device *dev = crtc->dev;
 367         struct drm_i915_private *dev_priv = dev->dev_private;
 368         const intel_limit_t *limit;
 369
 370         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 371                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 372                     LVDS_CLKB_POWER_UP) {
 373                         /* LVDS dual channel */
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_dual_lvds;
 378                 } else {
 379                         if (refclk == 100000)
 380                                 limit = &intel_limits_ironlake_single_lvds_100m;
 381                         else
 382                                 limit = &intel_limits_ironlake_single_lvds;
 383                 }
 384         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 385                         HAS_eDP)
 386                 limit = &intel_limits_ironlake_display_port;
 387         else
 388                 limit = &intel_limits_ironlake_dac;
 389
 390         return limit;
 391 }
 392
 393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 394 {
 395         struct drm_device *dev = crtc->dev;
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397         const intel_limit_t *limit;
 398
 399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 400                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 401                     LVDS_CLKB_POWER_UP)
 402                         /* LVDS with dual channel */
 403                         limit = &intel_limits_g4x_dual_channel_lvds;
 404                 else
 405                         /* LVDS with dual channel */
 406                         limit = &intel_limits_g4x_single_channel_lvds;
 407         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 408                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 409                 limit = &intel_limits_g4x_hdmi;
 410         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 411                 limit = &intel_limits_g4x_sdvo;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 413                 limit = &intel_limits_g4x_display_port;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (!IS_GEN2(dev)) {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i9xx_lvds;
 437                 else
 438                         limit = &intel_limits_i9xx_sdvo;
 439         } else {
 440                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 441                         limit = &intel_limits_i8xx_lvds;
 442                 else
 443                         limit = &intel_limits_i8xx_dvo;
 444         }
 445         return limit;
 446 }
 447
 448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 449 static void pineview_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = clock->m2 + 2;
 452         clock->p = clock->p1 * clock->p2;
 453         clock->vco = refclk * clock->m / clock->n;
 454         clock->dot = clock->vco / clock->p;
 455 }
 456
 457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 458 {
 459         if (IS_PINEVIEW(dev)) {
 460                 pineview_clock(refclk, clock);
 461                 return;
 462         }
 463         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 464         clock->p = clock->p1 * clock->p2;
 465         clock->vco = refclk * clock->m / (clock->n + 2);
 466         clock->dot = clock->vco / clock->p;
 467 }
 468
 469 /**
 470  * Returns whether any output on the specified pipe is of the specified type
 471  */
 472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 473 {
 474         struct drm_device *dev = crtc->dev;
 475         struct drm_mode_config *mode_config = &dev->mode_config;
 476         struct intel_encoder *encoder;
 477
 478         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 479                 if (encoder->base.crtc == crtc && encoder->type == type)
 480                         return true;
 481
 482         return false;
 483 }
 484
 485 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 486 /**
 487  * Returns whether the given set of divisors are valid for a given refclk with
 488  * the given connectors.
 489  */
 490
 491 static bool intel_PLL_is_valid(struct drm_device *dev,
 492                                const intel_limit_t *limit,
 493                                const intel_clock_t *clock)
 494 {
 495         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 496                 INTELPllInvalid("p1 out of range\n");
 497         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 498                 INTELPllInvalid("p out of range\n");
 499         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 500                 INTELPllInvalid("m2 out of range\n");
 501         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 502                 INTELPllInvalid("m1 out of range\n");
 503         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 504                 INTELPllInvalid("m1 <= m2\n");
 505         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 506                 INTELPllInvalid("m out of range\n");
 507         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 508                 INTELPllInvalid("n out of range\n");
 509         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 510                 INTELPllInvalid("vco out of range\n");
 511         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 512          * connector, etc., rather than just a single range.
 513          */
 514         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 515                 INTELPllInvalid("dot out of range\n");
 516
 517         return true;
 518 }
 519
 520 static bool
 521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 522                     int target, int refclk, intel_clock_t *match_clock,
 523                     intel_clock_t *best_clock)
 524
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         intel_clock_t clock;
 529         int err = target;
 530
 531         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 532             (I915_READ(LVDS)) != 0) {
 533                 /*
 534                  * For LVDS, if the panel is on, just rely on its current
 535                  * settings for dual-channel.  We haven't figured out how to
 536                  * reliably set up different single/dual channel state, if we
 537                  * even can.
 538                  */
 539                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 540                     LVDS_CLKB_POWER_UP)
 541                         clock.p2 = limit->p2.p2_fast;
 542                 else
 543                         clock.p2 = limit->p2.p2_slow;
 544         } else {
 545                 if (target < limit->p2.dot_limit)
 546                         clock.p2 = limit->p2.p2_slow;
 547                 else
 548                         clock.p2 = limit->p2.p2_fast;
 549         }
 550
 551         memset(best_clock, 0, sizeof(*best_clock));
 552
 553         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 554              clock.m1++) {
 555                 for (clock.m2 = limit->m2.min;
 556                      clock.m2 <= limit->m2.max; clock.m2++) {
 557                         /* m1 is always 0 in Pineview */
 558                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 559                                 break;
 560                         for (clock.n = limit->n.min;
 561                              clock.n <= limit->n.max; clock.n++) {
 562                                 for (clock.p1 = limit->p1.min;
 563                                         clock.p1 <= limit->p1.max; clock.p1++) {
 564                                         int this_err;
 565
 566                                         intel_clock(dev, refclk, &clock);
 567                                         if (!intel_PLL_is_valid(dev, limit,
 568                                                                 &clock))
 569                                                 continue;
 570                                         if (match_clock &&
 571                                             clock.p != match_clock->p)
 572                                                 continue;
 573
 574                                         this_err = abs(clock.dot - target);
 575                                         if (this_err < err) {
 576                                                 *best_clock = clock;
 577                                                 err = this_err;
 578                                         }
 579                                 }
 580                         }
 581                 }
 582         }
 583
 584         return (err != target);
 585 }
 586
 587 static bool
 588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 589                         int target, int refclk, intel_clock_t *match_clock,
 590                         intel_clock_t *best_clock)
 591 {
 592         struct drm_device *dev = crtc->dev;
 593         struct drm_i915_private *dev_priv = dev->dev_private;
 594         intel_clock_t clock;
 595         int max_n;
 596         bool found;
 597         /* approximately equals target * 0.00585 */
 598         int err_most = (target >> 8) + (target >> 9);
 599         found = false;
 600
 601         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 602                 int lvds_reg;
 603
 604                 if (HAS_PCH_SPLIT(dev))
 605                         lvds_reg = PCH_LVDS;
 606                 else
 607                         lvds_reg = LVDS;
 608                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 609                     LVDS_CLKB_POWER_UP)
 610                         clock.p2 = limit->p2.p2_fast;
 611                 else
 612                         clock.p2 = limit->p2.p2_slow;
 613         } else {
 614                 if (target < limit->p2.dot_limit)
 615                         clock.p2 = limit->p2.p2_slow;
 616                 else
 617                         clock.p2 = limit->p2.p2_fast;
 618         }
 619
 620         memset(best_clock, 0, sizeof(*best_clock));
 621         max_n = limit->n.max;
 622         /* based on hardware requirement, prefer smaller n to precision */
 623         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 624                 /* based on hardware requirement, prefere larger m1,m2 */
 625                 for (clock.m1 = limit->m1.max;
 626                      clock.m1 >= limit->m1.min; clock.m1--) {
 627                         for (clock.m2 = limit->m2.max;
 628                              clock.m2 >= limit->m2.min; clock.m2--) {
 629                                 for (clock.p1 = limit->p1.max;
 630                                      clock.p1 >= limit->p1.min; clock.p1--) {
 631                                         int this_err;
 632
 633                                         intel_clock(dev, refclk, &clock);
 634                                         if (!intel_PLL_is_valid(dev, limit,
 635                                                                 &clock))
 636                                                 continue;
 637                                         if (match_clock &&
 638                                             clock.p != match_clock->p)
 639                                                 continue;
 640
 641                                         this_err = abs(clock.dot - target);
 642                                         if (this_err < err_most) {
 643                                                 *best_clock = clock;
 644                                                 err_most = this_err;
 645                                                 max_n = clock.n;
 646                                                 found = true;
 647                                         }
 648                                 }
 649                         }
 650                 }
 651         }
 652         return found;
 653 }
 654
 655 static bool
 656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 657                            int target, int refclk, intel_clock_t *match_clock,
 658                            intel_clock_t *best_clock)
 659 {
 660         struct drm_device *dev = crtc->dev;
 661         intel_clock_t clock;
 662
 663         if (target < 200000) {
 664                 clock.n = 1;
 665                 clock.p1 = 2;
 666                 clock.p2 = 10;
 667                 clock.m1 = 12;
 668                 clock.m2 = 9;
 669         } else {
 670                 clock.n = 2;
 671                 clock.p1 = 1;
 672                 clock.p2 = 10;
 673                 clock.m1 = 14;
 674                 clock.m2 = 8;
 675         }
 676         intel_clock(dev, refclk, &clock);
 677         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 678         return true;
 679 }
 680
 681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 682 static bool
 683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                       int target, int refclk, intel_clock_t *match_clock,
 685                       intel_clock_t *best_clock)
 686 {
 687         intel_clock_t clock;
 688         if (target < 200000) {
 689                 clock.p1 = 2;
 690                 clock.p2 = 10;
 691                 clock.n = 2;
 692                 clock.m1 = 23;
 693                 clock.m2 = 8;
 694         } else {
 695                 clock.p1 = 1;
 696                 clock.p2 = 10;
 697                 clock.n = 1;
 698                 clock.m1 = 14;
 699                 clock.m2 = 2;
 700         }
 701         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 702         clock.p = (clock.p1 * clock.p2);
 703         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 704         clock.vco = 0;
 705         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 706         return true;
 707 }
 708
 709 /**
 710  * intel_wait_for_vblank - wait for vblank on a given pipe
 711  * @dev: drm device
 712  * @pipe: pipe to wait for
 713  *
 714  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 715  * mode setting code.
 716  */
 717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 718 {
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         int pipestat_reg = PIPESTAT(pipe);
 721
 722         /* Clear existing vblank status. Note this will clear any other
 723          * sticky status fields as well.
 724          *
 725          * This races with i915_driver_irq_handler() with the result
 726          * that either function could miss a vblank event.  Here it is not
 727          * fatal, as we will either wait upon the next vblank interrupt or
 728          * timeout.  Generally speaking intel_wait_for_vblank() is only
 729          * called during modeset at which time the GPU should be idle and
 730          * should *not* be performing page flips and thus not waiting on
 731          * vblanks...
 732          * Currently, the result of us stealing a vblank from the irq
 733          * handler is that a single frame will be skipped during swapbuffers.
 734          */
 735         I915_WRITE(pipestat_reg,
 736                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 737
 738         /* Wait for vblank interrupt bit to set */
 739         if (wait_for(I915_READ(pipestat_reg) &
 740                      PIPE_VBLANK_INTERRUPT_STATUS,
 741                      50))
 742                 DRM_DEBUG_KMS("vblank wait timed out\n");
 743 }
 744
 745 /*
 746  * intel_wait_for_pipe_off - wait for pipe to turn off
 747  * @dev: drm device
 748  * @pipe: pipe to wait for
 749  *
 750  * After disabling a pipe, we can't wait for vblank in the usual way,
 751  * spinning on the vblank interrupt status bit, since we won't actually
 752  * see an interrupt when the pipe is disabled.
 753  *
 754  * On Gen4 and above:
 755  *   wait for the pipe register state bit to turn off
 756  *
 757  * Otherwise:
 758  *   wait for the display line value to settle (it usually
 759  *   ends up stopping at the start of the next frame).
 760  *
 761  */
 762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765
 766         if (INTEL_INFO(dev)->gen >= 4) {
 767                 int reg = PIPECONF(pipe);
 768
 769                 /* Wait for the Pipe State to go off */
 770                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 771                              100))
 772                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 773         } else {
 774                 u32 last_line;
 775                 int reg = PIPEDSL(pipe);
 776                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 777
 778                 /* Wait for the display line to settle */
 779                 do {
 780                         last_line = I915_READ(reg) & DSL_LINEMASK;
 781                         mdelay(5);
 782                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 783                          time_after(timeout, jiffies));
 784                 if (time_after(jiffies, timeout))
 785                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 786         }
 787 }
 788
 789 static const char *state_string(bool enabled)
 790 {
 791         return enabled ? "on" : "off";
 792 }
 793
 794 /* Only for pre-ILK configs */
 795 static void assert_pll(struct drm_i915_private *dev_priv,
 796                        enum pipe pipe, bool state)
 797 {
 798         int reg;
 799         u32 val;
 800         bool cur_state;
 801
 802         reg = DPLL(pipe);
 803         val = I915_READ(reg);
 804         cur_state = !!(val & DPLL_VCO_ENABLE);
 805         WARN(cur_state != state,
 806              "PLL state assertion failure (expected %s, current %s)\n",
 807              state_string(state), state_string(cur_state));
 808 }
 809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 811
 812 /* For ILK+ */
 813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 814                            enum pipe pipe, bool state)
 815 {
 816         int reg;
 817         u32 val;
 818         bool cur_state;
 819
 820         if (HAS_PCH_CPT(dev_priv->dev)) {
 821                 u32 pch_dpll;
 822
 823                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 824
 825                 /* Make sure the selected PLL is enabled to the transcoder */
 826                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 827                      "transcoder %d PLL not enabled\n", pipe);
 828
 829                 /* Convert the transcoder pipe number to a pll pipe number */
 830                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 831         }
 832
 833         reg = PCH_DPLL(pipe);
 834         val = I915_READ(reg);
 835         cur_state = !!(val & DPLL_VCO_ENABLE);
 836         WARN(cur_state != state,
 837              "PCH PLL state assertion failure (expected %s, current %s)\n",
 838              state_string(state), state_string(cur_state));
 839 }
 840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 842
 843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 844                           enum pipe pipe, bool state)
 845 {
 846         int reg;
 847         u32 val;
 848         bool cur_state;
 849
 850         reg = FDI_TX_CTL(pipe);
 851         val = I915_READ(reg);
 852         cur_state = !!(val & FDI_TX_ENABLE);
 853         WARN(cur_state != state,
 854              "FDI TX state assertion failure (expected %s, current %s)\n",
 855              state_string(state), state_string(cur_state));
 856 }
 857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 859
 860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 861                           enum pipe pipe, bool state)
 862 {
 863         int reg;
 864         u32 val;
 865         bool cur_state;
 866
 867         reg = FDI_RX_CTL(pipe);
 868         val = I915_READ(reg);
 869         cur_state = !!(val & FDI_RX_ENABLE);
 870         WARN(cur_state != state,
 871              "FDI RX state assertion failure (expected %s, current %s)\n",
 872              state_string(state), state_string(cur_state));
 873 }
 874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 876
 877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 878                                       enum pipe pipe)
 879 {
 880         int reg;
 881         u32 val;
 882
 883         /* ILK FDI PLL is always enabled */
 884         if (dev_priv->info->gen == 5)
 885                 return;
 886
 887         reg = FDI_TX_CTL(pipe);
 888         val = I915_READ(reg);
 889         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 890 }
 891
 892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 893                                       enum pipe pipe)
 894 {
 895         int reg;
 896         u32 val;
 897
 898         reg = FDI_RX_CTL(pipe);
 899         val = I915_READ(reg);
 900         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 901 }
 902
 903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 904                                   enum pipe pipe)
 905 {
 906         int pp_reg, lvds_reg;
 907         u32 val;
 908         enum pipe panel_pipe = PIPE_A;
 909         bool locked = true;
 910
 911         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 912                 pp_reg = PCH_PP_CONTROL;
 913                 lvds_reg = PCH_LVDS;
 914         } else {
 915                 pp_reg = PP_CONTROL;
 916                 lvds_reg = LVDS;
 917         }
 918
 919         val = I915_READ(pp_reg);
 920         if (!(val & PANEL_POWER_ON) ||
 921             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 922                 locked = false;
 923
 924         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 925                 panel_pipe = PIPE_B;
 926
 927         WARN(panel_pipe == pipe && locked,
 928              "panel assertion failure, pipe %c regs locked\n",
 929              pipe_name(pipe));
 930 }
 931
 932 void assert_pipe(struct drm_i915_private *dev_priv,
 933                  enum pipe pipe, bool state)
 934 {
 935         int reg;
 936         u32 val;
 937         bool cur_state;
 938
 939         /* if we need the pipe A quirk it must be always on */
 940         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 941                 state = true;
 942
 943         reg = PIPECONF(pipe);
 944         val = I915_READ(reg);
 945         cur_state = !!(val & PIPECONF_ENABLE);
 946         WARN(cur_state != state,
 947              "pipe %c assertion failure (expected %s, current %s)\n",
 948              pipe_name(pipe), state_string(state), state_string(cur_state));
 949 }
 950
 951 static void assert_plane(struct drm_i915_private *dev_priv,
 952                          enum plane plane, bool state)
 953 {
 954         int reg;
 955         u32 val;
 956         bool cur_state;
 957
 958         reg = DSPCNTR(plane);
 959         val = I915_READ(reg);
 960         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 961         WARN(cur_state != state,
 962              "plane %c assertion failure (expected %s, current %s)\n",
 963              plane_name(plane), state_string(state), state_string(cur_state));
 964 }
 965
 966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 968
 969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 970                                    enum pipe pipe)
 971 {
 972         int reg, i;
 973         u32 val;
 974         int cur_pipe;
 975
 976         /* Planes are fixed to pipes on ILK+ */
 977         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 978                 reg = DSPCNTR(pipe);
 979                 val = I915_READ(reg);
 980                 WARN((val & DISPLAY_PLANE_ENABLE),
 981                      "plane %c assertion failure, should be disabled but not\n",
 982                      plane_name(pipe));
 983                 return;
 984         }
 985
 986         /* Need to check both planes against the pipe */
 987         for (i = 0; i < 2; i++) {
 988                 reg = DSPCNTR(i);
 989                 val = I915_READ(reg);
 990                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 991                         DISPPLANE_SEL_PIPE_SHIFT;
 992                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 993                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 994                      plane_name(i), pipe_name(pipe));
 995         }
 996 }
 997
 998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 999 {
1000         u32 val;
1001         bool enabled;
1002
1003         val = I915_READ(PCH_DREF_CONTROL);
1004         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005                             DREF_SUPERSPREAD_SOURCE_MASK));
1006         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010                                        enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014         bool enabled;
1015
1016         reg = TRANSCONF(pipe);
1017         val = I915_READ(reg);
1018         enabled = !!(val & TRANS_ENABLE);
1019         WARN(enabled,
1020              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021              pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025                             enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027         if ((val & DP_PORT_EN) == 0)
1028                 return false;
1029
1030         if (HAS_PCH_CPT(dev_priv->dev)) {
1031                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034                         return false;
1035         } else {
1036                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037                         return false;
1038         }
1039         return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043                               enum pipe pipe, u32 val)
1044 {
1045         if ((val & PORT_ENABLE) == 0)
1046                 return false;
1047
1048         if (HAS_PCH_CPT(dev_priv->dev)) {
1049                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050                         return false;
1051         } else {
1052                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053                         return false;
1054         }
1055         return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059                               enum pipe pipe, u32 val)
1060 {
1061         if ((val & LVDS_PORT_EN) == 0)
1062                 return false;
1063
1064         if (HAS_PCH_CPT(dev_priv->dev)) {
1065                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066                         return false;
1067         } else {
1068                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069                         return false;
1070         }
1071         return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075                               enum pipe pipe, u32 val)
1076 {
1077         if ((val & ADPA_DAC_ENABLE) == 0)
1078                 return false;
1079         if (HAS_PCH_CPT(dev_priv->dev)) {
1080                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081                         return false;
1082         } else {
1083                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084                         return false;
1085         }
1086         return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090                                    enum pipe pipe, int reg, u32 port_sel)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099                                      enum pipe pipe, int reg)
1100 {
1101         u32 val = I915_READ(reg);
1102         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104              reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108                                       enum pipe pipe)
1109 {
1110         int reg;
1111         u32 val;
1112
1113         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117         reg = PCH_ADPA;
1118         val = I915_READ(reg);
1119         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120              "PCH VGA enabled on transcoder %c, should be disabled\n",
1121              pipe_name(pipe));
1122
1123         reg = PCH_LVDS;
1124         val = I915_READ(reg);
1125         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127              pipe_name(pipe));
1128
1129         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135  * intel_enable_pll - enable a PLL
1136  * @dev_priv: i915 private structure
1137  * @pipe: pipe PLL to enable
1138  *
1139  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1140  * make sure the PLL reg is writable first though, since the panel write
1141  * protect mechanism may be enabled.
1142  *
1143  * Note!  This is for pre-ILK only.
1144  */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147         int reg;
1148         u32 val;
1149
1150         /* No really, not for ILK+ */
1151         BUG_ON(dev_priv->info->gen >= 5);
1152
1153         /* PLL is protected by panel, make sure we can write it */
1154         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155                 assert_panel_unlocked(dev_priv, pipe);
1156
1157         reg = DPLL(pipe);
1158         val = I915_READ(reg);
1159         val |= DPLL_VCO_ENABLE;
1160
1161         /* We do this three times for luck */
1162         I915_WRITE(reg, val);
1163         POSTING_READ(reg);
1164         udelay(150); /* wait for warmup */
1165         I915_WRITE(reg, val);
1166         POSTING_READ(reg);
1167         udelay(150); /* wait for warmup */
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170         udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174  * intel_disable_pll - disable a PLL
1175  * @dev_priv: i915 private structure
1176  * @pipe: pipe PLL to disable
1177  *
1178  * Disable the PLL for @pipe, making sure the pipe is off first.
1179  *
1180  * Note!  This is for pre-ILK only.
1181  */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         /* Don't disable pipe A or pipe A PLLs if needed */
1188         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189                 return;
1190
1191         /* Make sure the pipe isn't still relying on us */
1192         assert_pipe_disabled(dev_priv, pipe);
1193
1194         reg = DPLL(pipe);
1195         val = I915_READ(reg);
1196         val &= ~DPLL_VCO_ENABLE;
1197         I915_WRITE(reg, val);
1198         POSTING_READ(reg);
1199 }
1200
1201 /**
1202  * intel_enable_pch_pll - enable PCH PLL
1203  * @dev_priv: i915 private structure
1204  * @pipe: pipe PLL to enable
1205  *
1206  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207  * drives the transcoder clock.
1208  */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210                                  enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         if (pipe > 1)
1216                 return;
1217
1218         /* PCH only available on ILK+ */
1219         BUG_ON(dev_priv->info->gen < 5);
1220
1221         /* PCH refclock must be enabled first */
1222         assert_pch_refclk_enabled(dev_priv);
1223
1224         reg = PCH_DPLL(pipe);
1225         val = I915_READ(reg);
1226         val |= DPLL_VCO_ENABLE;
1227         I915_WRITE(reg, val);
1228         POSTING_READ(reg);
1229         udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233                                   enum pipe pipe)
1234 {
1235         int reg;
1236         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237                 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239         if (pipe > 1)
1240                 return;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure transcoder isn't still depending on us */
1246         assert_transcoder_disabled(dev_priv, pipe);
1247
1248         if (pipe == 0)
1249                 pll_sel |= TRANSC_DPLLA_SEL;
1250         else if (pipe == 1)
1251                 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255                 return;
1256
1257         reg = PCH_DPLL(pipe);
1258         val = I915_READ(reg);
1259         val &= ~DPLL_VCO_ENABLE;
1260         I915_WRITE(reg, val);
1261         POSTING_READ(reg);
1262         udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266                                     enum pipe pipe)
1267 {
1268         int reg;
1269         u32 val, pipeconf_val;
1270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1271
1272         /* PCH only available on ILK+ */
1273         BUG_ON(dev_priv->info->gen < 5);
1274
1275         /* Make sure PCH DPLL is enabled */
1276         assert_pch_pll_enabled(dev_priv, pipe);
1277
1278         /* FDI must be feeding us bits for PCH ports */
1279         assert_fdi_tx_enabled(dev_priv, pipe);
1280         assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282         reg = TRANSCONF(pipe);
1283         val = I915_READ(reg);
1284         pipeconf_val = I915_READ(PIPECONF(pipe));
1285
1286         if (HAS_PCH_IBX(dev_priv->dev)) {
1287                 /*
1288                  * make the BPC in transcoder be consistent with
1289                  * that in pipeconf reg.
1290                  */
1291                 val &= ~PIPE_BPC_MASK;
1292                 val |= pipeconf_val & PIPE_BPC_MASK;
1293         }
1294
1295         val &= ~TRANS_INTERLACE_MASK;
1296         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1297                 if (HAS_PCH_IBX(dev_priv->dev) &&
1298                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299                         val |= TRANS_LEGACY_INTERLACED_ILK;
1300                 else
1301                         val |= TRANS_INTERLACED;
1302         else
1303                 val |= TRANS_PROGRESSIVE;
1304
1305         I915_WRITE(reg, val | TRANS_ENABLE);
1306         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308 }
1309
1310 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311                                      enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315
1316         /* FDI relies on the transcoder */
1317         assert_fdi_tx_disabled(dev_priv, pipe);
1318         assert_fdi_rx_disabled(dev_priv, pipe);
1319
1320         /* Ports must be off as well */
1321         assert_pch_ports_disabled(dev_priv, pipe);
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         val &= ~TRANS_ENABLE;
1326         I915_WRITE(reg, val);
1327         /* wait for PCH transcoder off, transcoder state */
1328         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1329                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1330 }
1331
1332 /**
1333  * intel_enable_pipe - enable a pipe, asserting requirements
1334  * @dev_priv: i915 private structure
1335  * @pipe: pipe to enable
1336  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1337  *
1338  * Enable @pipe, making sure that various hardware specific requirements
1339  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340  *
1341  * @pipe should be %PIPE_A or %PIPE_B.
1342  *
1343  * Will wait until the pipe is actually running (i.e. first vblank) before
1344  * returning.
1345  */
1346 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347                               bool pch_port)
1348 {
1349         int reg;
1350         u32 val;
1351
1352         /*
1353          * A pipe without a PLL won't actually be able to drive bits from
1354          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1355          * need the check.
1356          */
1357         if (!HAS_PCH_SPLIT(dev_priv->dev))
1358                 assert_pll_enabled(dev_priv, pipe);
1359         else {
1360                 if (pch_port) {
1361                         /* if driving the PCH, we need FDI enabled */
1362                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364                 }
1365                 /* FIXME: assert CPU port conditions for SNB+ */
1366         }
1367
1368         reg = PIPECONF(pipe);
1369         val = I915_READ(reg);
1370         if (val & PIPECONF_ENABLE)
1371                 return;
1372
1373         I915_WRITE(reg, val | PIPECONF_ENABLE);
1374         intel_wait_for_vblank(dev_priv->dev, pipe);
1375 }
1376
1377 /**
1378  * intel_disable_pipe - disable a pipe, asserting requirements
1379  * @dev_priv: i915 private structure
1380  * @pipe: pipe to disable
1381  *
1382  * Disable @pipe, making sure that various hardware specific requirements
1383  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384  *
1385  * @pipe should be %PIPE_A or %PIPE_B.
1386  *
1387  * Will wait until the pipe has shut down before returning.
1388  */
1389 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390                                enum pipe pipe)
1391 {
1392         int reg;
1393         u32 val;
1394
1395         /*
1396          * Make sure planes won't keep trying to pump pixels to us,
1397          * or we might hang the display.
1398          */
1399         assert_planes_disabled(dev_priv, pipe);
1400
1401         /* Don't disable pipe A or pipe A PLLs if needed */
1402         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403                 return;
1404
1405         reg = PIPECONF(pipe);
1406         val = I915_READ(reg);
1407         if ((val & PIPECONF_ENABLE) == 0)
1408                 return;
1409
1410         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1411         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412 }
1413
1414 /*
1415  * Plane regs are double buffered, going from enabled->disabled needs a
1416  * trigger in order to latch.  The display address reg provides this.
1417  */
1418 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419                                       enum plane plane)
1420 {
1421         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423 }
1424
1425 /**
1426  * intel_enable_plane - enable a display plane on a given pipe
1427  * @dev_priv: i915 private structure
1428  * @plane: plane to enable
1429  * @pipe: pipe being fed
1430  *
1431  * Enable @plane on @pipe, making sure that @pipe is running first.
1432  */
1433 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434                                enum plane plane, enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440         assert_pipe_enabled(dev_priv, pipe);
1441
1442         reg = DSPCNTR(plane);
1443         val = I915_READ(reg);
1444         if (val & DISPLAY_PLANE_ENABLE)
1445                 return;
1446
1447         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1448         intel_flush_display_plane(dev_priv, plane);
1449         intel_wait_for_vblank(dev_priv->dev, pipe);
1450 }
1451
1452 /**
1453  * intel_disable_plane - disable a display plane
1454  * @dev_priv: i915 private structure
1455  * @plane: plane to disable
1456  * @pipe: pipe consuming the data
1457  *
1458  * Disable @plane; should be an independent operation.
1459  */
1460 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461                                 enum plane plane, enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         reg = DSPCNTR(plane);
1467         val = I915_READ(reg);
1468         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469                 return;
1470
1471         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1472         intel_flush_display_plane(dev_priv, plane);
1473         intel_wait_for_vblank(dev_priv->dev, pipe);
1474 }
1475
1476 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1477                            enum pipe pipe, int reg, u32 port_sel)
1478 {
1479         u32 val = I915_READ(reg);
1480         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1481                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1482                 I915_WRITE(reg, val & ~DP_PORT_EN);
1483         }
1484 }
1485
1486 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487                              enum pipe pipe, int reg)
1488 {
1489         u32 val = I915_READ(reg);
1490         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1491                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492                               reg, pipe);
1493                 I915_WRITE(reg, val & ~PORT_ENABLE);
1494         }
1495 }
1496
1497 /* Disable any ports connected to this transcoder */
1498 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499                                     enum pipe pipe)
1500 {
1501         u32 reg, val;
1502
1503         val = I915_READ(PCH_PP_CONTROL);
1504         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
1506         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1509
1510         reg = PCH_ADPA;
1511         val = I915_READ(reg);
1512         if (adpa_pipe_enabled(dev_priv, val, pipe))
1513                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515         reg = PCH_LVDS;
1516         val = I915_READ(reg);
1517         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1519                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520                 POSTING_READ(reg);
1521                 udelay(100);
1522         }
1523
1524         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526         disable_pch_hdmi(dev_priv, pipe, HDMID);
1527 }
1528
1529 static void i8xx_disable_fbc(struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         u32 fbc_ctl;
1533
1534         /* Disable compression */
1535         fbc_ctl = I915_READ(FBC_CONTROL);
1536         if ((fbc_ctl & FBC_CTL_EN) == 0)
1537                 return;
1538
1539         fbc_ctl &= ~FBC_CTL_EN;
1540         I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542         /* Wait for compressing bit to clear */
1543         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544                 DRM_DEBUG_KMS("FBC idle timed out\n");
1545                 return;
1546         }
1547
1548         DRM_DEBUG_KMS("disabled FBC\n");
1549 }
1550
1551 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int cfb_pitch;
1560         int plane, i;
1561         u32 fbc_ctl, fbc_ctl2;
1562
1563         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1564         if (fb->pitches[0] < cfb_pitch)
1565                 cfb_pitch = fb->pitches[0];
1566
1567         /* FBC_CTL wants 64B units */
1568         cfb_pitch = (cfb_pitch / 64) - 1;
1569         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1570
1571         /* Clear old tags */
1572         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573                 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575         /* Set it up... */
1576         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577         fbc_ctl2 |= plane;
1578         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581         /* enable it... */
1582         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1583         if (IS_I945GM(dev))
1584                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1585         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1586         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1587         fbc_ctl |= obj->fence_reg;
1588         I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
1590         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591                       cfb_pitch, crtc->y, intel_crtc->plane);
1592 }
1593
1594 static bool i8xx_fbc_enabled(struct drm_device *dev)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599 }
1600
1601 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603         struct drm_device *dev = crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         struct drm_framebuffer *fb = crtc->fb;
1606         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607         struct drm_i915_gem_object *obj = intel_fb->obj;
1608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610         unsigned long stall_watermark = 200;
1611         u32 dpfc_ctl;
1612
1613         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1614         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1615         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1616
1617         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622         /* enable it... */
1623         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
1625         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1626 }
1627
1628 static void g4x_disable_fbc(struct drm_device *dev)
1629 {
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         u32 dpfc_ctl;
1632
1633         /* Disable compression */
1634         dpfc_ctl = I915_READ(DPFC_CONTROL);
1635         if (dpfc_ctl & DPFC_CTL_EN) {
1636                 dpfc_ctl &= ~DPFC_CTL_EN;
1637                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1638
1639                 DRM_DEBUG_KMS("disabled FBC\n");
1640         }
1641 }
1642
1643 static bool g4x_fbc_enabled(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648 }
1649
1650 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 blt_ecoskpd;
1654
1655         /* Make sure blitter notifies FBC of writes */
1656         gen6_gt_force_wake_get(dev_priv);
1657         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659                 GEN6_BLITTER_LOCK_SHIFT;
1660         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664                          GEN6_BLITTER_LOCK_SHIFT);
1665         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1667         gen6_gt_force_wake_put(dev_priv);
1668 }
1669
1670 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct drm_framebuffer *fb = crtc->fb;
1675         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1676         struct drm_i915_gem_object *obj = intel_fb->obj;
1677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1678         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1679         unsigned long stall_watermark = 200;
1680         u32 dpfc_ctl;
1681
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         dpfc_ctl &= DPFC_RESERVED;
1684         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1685         /* Set persistent mode for front-buffer rendering, ala X. */
1686         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1687         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1688         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1689
1690         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1694         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1695         /* enable it... */
1696         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1697
1698         if (IS_GEN6(dev)) {
1699                 I915_WRITE(SNB_DPFC_CTL_SA,
1700                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1701                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1702                 sandybridge_blit_fbc_update(dev);
1703         }
1704
1705         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706 }
1707
1708 static void ironlake_disable_fbc(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         u32 dpfc_ctl;
1712
1713         /* Disable compression */
1714         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1715         if (dpfc_ctl & DPFC_CTL_EN) {
1716                 dpfc_ctl &= ~DPFC_CTL_EN;
1717                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1718
1719                 DRM_DEBUG_KMS("disabled FBC\n");
1720         }
1721 }
1722
1723 static bool ironlake_fbc_enabled(struct drm_device *dev)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728 }
1729
1730 bool intel_fbc_enabled(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734         if (!dev_priv->display.fbc_enabled)
1735                 return false;
1736
1737         return dev_priv->display.fbc_enabled(dev);
1738 }
1739
1740 static void intel_fbc_work_fn(struct work_struct *__work)
1741 {
1742         struct intel_fbc_work *work =
1743                 container_of(to_delayed_work(__work),
1744                              struct intel_fbc_work, work);
1745         struct drm_device *dev = work->crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         mutex_lock(&dev->struct_mutex);
1749         if (work == dev_priv->fbc_work) {
1750                 /* Double check that we haven't switched fb without cancelling
1751                  * the prior work.
1752                  */
1753                 if (work->crtc->fb == work->fb) {
1754                         dev_priv->display.enable_fbc(work->crtc,
1755                                                      work->interval);
1756
1757                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1759                         dev_priv->cfb_y = work->crtc->y;
1760                 }
1761
1762                 dev_priv->fbc_work = NULL;
1763         }
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         kfree(work);
1767 }
1768
1769 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770 {
1771         if (dev_priv->fbc_work == NULL)
1772                 return;
1773
1774         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776         /* Synchronisation is provided by struct_mutex and checking of
1777          * dev_priv->fbc_work, so we can perform the cancellation
1778          * entirely asynchronously.
1779          */
1780         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781                 /* tasklet was killed before being run, clean up */
1782                 kfree(dev_priv->fbc_work);
1783
1784         /* Mark the work as no longer wanted so that if it does
1785          * wake-up (because the work was already running and waiting
1786          * for our mutex), it will discover that is no longer
1787          * necessary to run.
1788          */
1789         dev_priv->fbc_work = NULL;
1790 }
1791
1792 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1793 {
1794         struct intel_fbc_work *work;
1795         struct drm_device *dev = crtc->dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798         if (!dev_priv->display.enable_fbc)
1799                 return;
1800
1801         intel_cancel_fbc_work(dev_priv);
1802
1803         work = kzalloc(sizeof *work, GFP_KERNEL);
1804         if (work == NULL) {
1805                 dev_priv->display.enable_fbc(crtc, interval);
1806                 return;
1807         }
1808
1809         work->crtc = crtc;
1810         work->fb = crtc->fb;
1811         work->interval = interval;
1812         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814         dev_priv->fbc_work = work;
1815
1816         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818         /* Delay the actual enabling to let pageflipping cease and the
1819          * display to settle before starting the compression. Note that
1820          * this delay also serves a second purpose: it allows for a
1821          * vblank to pass after disabling the FBC before we attempt
1822          * to modify the control registers.
1823          *
1824          * A more complicated solution would involve tracking vblanks
1825          * following the termination of the page-flipping sequence
1826          * and indeed performing the enable as a co-routine and not
1827          * waiting synchronously upon the vblank.
1828          */
1829         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1830 }
1831
1832 void intel_disable_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836         intel_cancel_fbc_work(dev_priv);
1837
1838         if (!dev_priv->display.disable_fbc)
1839                 return;
1840
1841         dev_priv->display.disable_fbc(dev);
1842         dev_priv->cfb_plane = -1;
1843 }
1844
1845 /**
1846  * intel_update_fbc - enable/disable FBC as needed
1847  * @dev: the drm_device
1848  *
1849  * Set up the framebuffer compression hardware at mode set time.  We
1850  * enable it if possible:
1851  *   - plane A only (on pre-965)
1852  *   - no pixel mulitply/line duplication
1853  *   - no alpha buffer discard
1854  *   - no dual wide
1855  *   - framebuffer <= 2048 in width, 1536 in height
1856  *
1857  * We can't assume that any compression will take place (worst case),
1858  * so the compressed buffer has to be the same size as the uncompressed
1859  * one.  It also must reside (along with the line length buffer) in
1860  * stolen memory.
1861  *
1862  * We need to enable/disable FBC on a global basis.
1863  */
1864 static void intel_update_fbc(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         struct drm_crtc *crtc = NULL, *tmp_crtc;
1868         struct intel_crtc *intel_crtc;
1869         struct drm_framebuffer *fb;
1870         struct intel_framebuffer *intel_fb;
1871         struct drm_i915_gem_object *obj;
1872         int enable_fbc;
1873
1874         DRM_DEBUG_KMS("\n");
1875
1876         if (!i915_powersave)
1877                 return;
1878
1879         if (!I915_HAS_FBC(dev))
1880                 return;
1881
1882         /*
1883          * If FBC is already on, we just have to verify that we can
1884          * keep it that way...
1885          * Need to disable if:
1886          *   - more than one pipe is active
1887          *   - changing FBC params (stride, fence, mode)
1888          *   - new fb is too large to fit in compressed buffer
1889          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1890          */
1891         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1892                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1893                         if (crtc) {
1894                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896                                 goto out_disable;
1897                         }
1898                         crtc = tmp_crtc;
1899                 }
1900         }
1901
1902         if (!crtc || crtc->fb == NULL) {
1903                 DRM_DEBUG_KMS("no output, disabling\n");
1904                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1905                 goto out_disable;
1906         }
1907
1908         intel_crtc = to_intel_crtc(crtc);
1909         fb = crtc->fb;
1910         intel_fb = to_intel_framebuffer(fb);
1911         obj = intel_fb->obj;
1912
1913         enable_fbc = i915_enable_fbc;
1914         if (enable_fbc < 0) {
1915                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916                 enable_fbc = 1;
1917                 if (INTEL_INFO(dev)->gen <= 6)
1918                         enable_fbc = 0;
1919         }
1920         if (!enable_fbc) {
1921                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923                 goto out_disable;
1924         }
1925         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1926                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1927                               "compression\n");
1928                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1929                 goto out_disable;
1930         }
1931         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1933                 DRM_DEBUG_KMS("mode incompatible with compression, "
1934                               "disabling\n");
1935                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1936                 goto out_disable;
1937         }
1938         if ((crtc->mode.hdisplay > 2048) ||
1939             (crtc->mode.vdisplay > 1536)) {
1940                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1942                 goto out_disable;
1943         }
1944         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1945                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1947                 goto out_disable;
1948         }
1949
1950         /* The use of a CPU fence is mandatory in order to detect writes
1951          * by the CPU to the scanout and trigger updates to the FBC.
1952          */
1953         if (obj->tiling_mode != I915_TILING_X ||
1954             obj->fence_reg == I915_FENCE_REG_NONE) {
1955                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1957                 goto out_disable;
1958         }
1959
1960         /* If the kernel debugger is active, always disable compression */
1961         if (in_dbg_master())
1962                 goto out_disable;
1963
1964         /* If the scanout has not changed, don't modify the FBC settings.
1965          * Note that we make the fundamental assumption that the fb->obj
1966          * cannot be unpinned (and have its GTT offset and fence revoked)
1967          * without first being decoupled from the scanout and FBC disabled.
1968          */
1969         if (dev_priv->cfb_plane == intel_crtc->plane &&
1970             dev_priv->cfb_fb == fb->base.id &&
1971             dev_priv->cfb_y == crtc->y)
1972                 return;
1973
1974         if (intel_fbc_enabled(dev)) {
1975                 /* We update FBC along two paths, after changing fb/crtc
1976                  * configuration (modeswitching) and after page-flipping
1977                  * finishes. For the latter, we know that not only did
1978                  * we disable the FBC at the start of the page-flip
1979                  * sequence, but also more than one vblank has passed.
1980                  *
1981                  * For the former case of modeswitching, it is possible
1982                  * to switch between two FBC valid configurations
1983                  * instantaneously so we do need to disable the FBC
1984                  * before we can modify its control registers. We also
1985                  * have to wait for the next vblank for that to take
1986                  * effect. However, since we delay enabling FBC we can
1987                  * assume that a vblank has passed since disabling and
1988                  * that we can safely alter the registers in the deferred
1989                  * callback.
1990                  *
1991                  * In the scenario that we go from a valid to invalid
1992                  * and then back to valid FBC configuration we have
1993                  * no strict enforcement that a vblank occurred since
1994                  * disabling the FBC. However, along all current pipe
1995                  * disabling paths we do need to wait for a vblank at
1996                  * some point. And we wait before enabling FBC anyway.
1997                  */
1998                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999                 intel_disable_fbc(dev);
2000         }
2001
2002         intel_enable_fbc(crtc, 500);
2003         return;
2004
2005 out_disable:
2006         /* Multiple disables should be harmless */
2007         if (intel_fbc_enabled(dev)) {
2008                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009                 intel_disable_fbc(dev);
2010         }
2011 }
2012
2013 int
2014 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2015                            struct drm_i915_gem_object *obj,
2016                            struct intel_ring_buffer *pipelined)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         u32 alignment;
2020         int ret;
2021
2022         switch (obj->tiling_mode) {
2023         case I915_TILING_NONE:
2024                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025                         alignment = 128 * 1024;
2026                 else if (INTEL_INFO(dev)->gen >= 4)
2027                         alignment = 4 * 1024;
2028                 else
2029                         alignment = 64 * 1024;
2030                 break;
2031         case I915_TILING_X:
2032                 /* pin() will align the object as required by fence */
2033                 alignment = 0;
2034                 break;
2035         case I915_TILING_Y:
2036                 /* FIXME: Is this true? */
2037                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038                 return -EINVAL;
2039         default:
2040                 BUG();
2041         }
2042
2043         dev_priv->mm.interruptible = false;
2044         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2045         if (ret)
2046                 goto err_interruptible;
2047
2048         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049          * fence, whereas 965+ only requires a fence if using
2050          * framebuffer compression.  For simplicity, we always install
2051          * a fence as the cost is not that onerous.
2052          */
2053         if (obj->tiling_mode != I915_TILING_NONE) {
2054                 ret = i915_gem_object_get_fence(obj, pipelined);
2055                 if (ret)
2056                         goto err_unpin;
2057
2058                 i915_gem_object_pin_fence(obj);
2059         }
2060
2061         dev_priv->mm.interruptible = true;
2062         return 0;
2063
2064 err_unpin:
2065         i915_gem_object_unpin(obj);
2066 err_interruptible:
2067         dev_priv->mm.interruptible = true;
2068         return ret;
2069 }
2070
2071 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072 {
2073         i915_gem_object_unpin_fence(obj);
2074         i915_gem_object_unpin(obj);
2075 }
2076
2077 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078                              int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long Start, Offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093                 break;
2094         default:
2095                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096                 return -EINVAL;
2097         }
2098
2099         intel_fb = to_intel_framebuffer(fb);
2100         obj = intel_fb->obj;
2101
2102         reg = DSPCNTR(plane);
2103         dspcntr = I915_READ(reg);
2104         /* Mask out pixel format bits in case we change it */
2105         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106         switch (fb->bits_per_pixel) {
2107         case 8:
2108                 dspcntr |= DISPPLANE_8BPP;
2109                 break;
2110         case 16:
2111                 if (fb->depth == 15)
2112                         dspcntr |= DISPPLANE_15_16BPP;
2113                 else
2114                         dspcntr |= DISPPLANE_16BPP;
2115                 break;
2116         case 24:
2117         case 32:
2118                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119                 break;
2120         default:
2121                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122                 return -EINVAL;
2123         }
2124         if (INTEL_INFO(dev)->gen >= 4) {
2125                 if (obj->tiling_mode != I915_TILING_NONE)
2126                         dspcntr |= DISPPLANE_TILED;
2127                 else
2128                         dspcntr &= ~DISPPLANE_TILED;
2129         }
2130
2131         I915_WRITE(reg, dspcntr);
2132
2133         Start = obj->gtt_offset;
2134         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       Start, Offset, x, y, fb->pitches[0]);
2138         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2139         if (INTEL_INFO(dev)->gen >= 4) {
2140                 I915_WRITE(DSPSURF(plane), Start);
2141                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142                 I915_WRITE(DSPADDR(plane), Offset);
2143         } else
2144                 I915_WRITE(DSPADDR(plane), Start + Offset);
2145         POSTING_READ(reg);
2146
2147         return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151                                  struct drm_framebuffer *fb, int x, int y)
2152 {
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156         struct intel_framebuffer *intel_fb;
2157         struct drm_i915_gem_object *obj;
2158         int plane = intel_crtc->plane;
2159         unsigned long Start, Offset;
2160         u32 dspcntr;
2161         u32 reg;
2162
2163         switch (plane) {
2164         case 0:
2165         case 1:
2166         case 2:
2167                 break;
2168         default:
2169                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170                 return -EINVAL;
2171         }
2172
2173         intel_fb = to_intel_framebuffer(fb);
2174         obj = intel_fb->obj;
2175
2176         reg = DSPCNTR(plane);
2177         dspcntr = I915_READ(reg);
2178         /* Mask out pixel format bits in case we change it */
2179         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180         switch (fb->bits_per_pixel) {
2181         case 8:
2182                 dspcntr |= DISPPLANE_8BPP;
2183                 break;
2184         case 16:
2185                 if (fb->depth != 16)
2186                         return -EINVAL;
2187
2188                 dspcntr |= DISPPLANE_16BPP;
2189                 break;
2190         case 24:
2191         case 32:
2192                 if (fb->depth == 24)
2193                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194                 else if (fb->depth == 30)
2195                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196                 else
2197                         return -EINVAL;
2198                 break;
2199         default:
2200                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201                 return -EINVAL;
2202         }
2203
2204         if (obj->tiling_mode != I915_TILING_NONE)
2205                 dspcntr |= DISPPLANE_TILED;
2206         else
2207                 dspcntr &= ~DISPPLANE_TILED;
2208
2209         /* must disable */
2210         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212         I915_WRITE(reg, dspcntr);
2213
2214         Start = obj->gtt_offset;
2215         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2216
2217         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218                       Start, Offset, x, y, fb->pitches[0]);
2219         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2220         I915_WRITE(DSPSURF(plane), Start);
2221         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222         I915_WRITE(DSPADDR(plane), Offset);
2223         POSTING_READ(reg);
2224
2225         return 0;
2226 }
2227
2228 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2229 static int
2230 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231                            int x, int y, enum mode_set_atomic state)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         int ret;
2236
2237         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238         if (ret)
2239                 return ret;
2240
2241         intel_update_fbc(dev);
2242         intel_increase_pllclock(crtc);
2243
2244         return 0;
2245 }
2246
2247 static int
2248 intel_finish_fb(struct drm_framebuffer *old_fb)
2249 {
2250         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2251         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2252         bool was_interruptible = dev_priv->mm.interruptible;
2253         int ret;
2254
2255         wait_event(dev_priv->pending_flip_queue,
2256                    atomic_read(&dev_priv->mm.wedged) ||
2257                    atomic_read(&obj->pending_flip) == 0);
2258
2259         /* Big Hammer, we also need to ensure that any pending
2260          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2261          * current scanout is retired before unpinning the old
2262          * framebuffer.
2263          *
2264          * This should only fail upon a hung GPU, in which case we
2265          * can safely continue.
2266          */
2267         dev_priv->mm.interruptible = false;
2268         ret = i915_gem_object_finish_gpu(obj);
2269         dev_priv->mm.interruptible = was_interruptible;
2270
2271         return ret;
2272 }
2273
2274 static int
2275 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2276                     struct drm_framebuffer *old_fb)
2277 {
2278         struct drm_device *dev = crtc->dev;
2279         struct drm_i915_master_private *master_priv;
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int ret;
2282
2283         /* no fb bound */
2284         if (!crtc->fb) {
2285                 DRM_ERROR("No FB bound\n");
2286                 return 0;
2287         }
2288
2289         switch (intel_crtc->plane) {
2290         case 0:
2291         case 1:
2292                 break;
2293         case 2:
2294                 if (IS_IVYBRIDGE(dev))
2295                         break;
2296                 /* fall through otherwise */
2297         default:
2298                 DRM_ERROR("no plane for crtc\n");
2299                 return -EINVAL;
2300         }
2301
2302         mutex_lock(&dev->struct_mutex);
2303         ret = intel_pin_and_fence_fb_obj(dev,
2304                                          to_intel_framebuffer(crtc->fb)->obj,
2305                                          NULL);
2306         if (ret != 0) {
2307                 mutex_unlock(&dev->struct_mutex);
2308                 DRM_ERROR("pin & fence failed\n");
2309                 return ret;
2310         }
2311
2312         if (old_fb)
2313                 intel_finish_fb(old_fb);
2314
2315         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2316                                          LEAVE_ATOMIC_MODE_SET);
2317         if (ret) {
2318                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("failed to update base address\n");
2321                 return ret;
2322         }
2323
2324         if (old_fb) {
2325                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2326                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2327         }
2328
2329         mutex_unlock(&dev->struct_mutex);
2330
2331         if (!dev->primary->master)
2332                 return 0;
2333
2334         master_priv = dev->primary->master->driver_priv;
2335         if (!master_priv->sarea_priv)
2336                 return 0;
2337
2338         if (intel_crtc->pipe) {
2339                 master_priv->sarea_priv->pipeB_x = x;
2340                 master_priv->sarea_priv->pipeB_y = y;
2341         } else {
2342                 master_priv->sarea_priv->pipeA_x = x;
2343                 master_priv->sarea_priv->pipeA_y = y;
2344         }
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 /* The FDI link training functions for ILK/Ibexpeak. */
2440 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2441 {
2442         struct drm_device *dev = crtc->dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445         int pipe = intel_crtc->pipe;
2446         int plane = intel_crtc->plane;
2447         u32 reg, temp, tries;
2448
2449         /* FDI needs bits from pipe & plane first */
2450         assert_pipe_enabled(dev_priv, pipe);
2451         assert_plane_enabled(dev_priv, plane);
2452
2453         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2454            for train result */
2455         reg = FDI_RX_IMR(pipe);
2456         temp = I915_READ(reg);
2457         temp &= ~FDI_RX_SYMBOL_LOCK;
2458         temp &= ~FDI_RX_BIT_LOCK;
2459         I915_WRITE(reg, temp);
2460         I915_READ(reg);
2461         udelay(150);
2462
2463         /* enable CPU FDI TX and PCH FDI RX */
2464         reg = FDI_TX_CTL(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~(7 << 19);
2467         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2468         temp &= ~FDI_LINK_TRAIN_NONE;
2469         temp |= FDI_LINK_TRAIN_PATTERN_1;
2470         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2471
2472         reg = FDI_RX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~FDI_LINK_TRAIN_NONE;
2475         temp |= FDI_LINK_TRAIN_PATTERN_1;
2476         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2477
2478         POSTING_READ(reg);
2479         udelay(150);
2480
2481         /* Ironlake workaround, enable clock pointer after FDI enable*/
2482         if (HAS_PCH_IBX(dev)) {
2483                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2484                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2485                            FDI_RX_PHASE_SYNC_POINTER_EN);
2486         }
2487
2488         reg = FDI_RX_IIR(pipe);
2489         for (tries = 0; tries < 5; tries++) {
2490                 temp = I915_READ(reg);
2491                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2492
2493                 if ((temp & FDI_RX_BIT_LOCK)) {
2494                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2495                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2496                         break;
2497                 }
2498         }
2499         if (tries == 5)
2500                 DRM_ERROR("FDI train 1 fail!\n");
2501
2502         /* Train 2 */
2503         reg = FDI_TX_CTL(pipe);
2504         temp = I915_READ(reg);
2505         temp &= ~FDI_LINK_TRAIN_NONE;
2506         temp |= FDI_LINK_TRAIN_PATTERN_2;
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         temp &= ~FDI_LINK_TRAIN_NONE;
2512         temp |= FDI_LINK_TRAIN_PATTERN_2;
2513         I915_WRITE(reg, temp);
2514
2515         POSTING_READ(reg);
2516         udelay(150);
2517
2518         reg = FDI_RX_IIR(pipe);
2519         for (tries = 0; tries < 5; tries++) {
2520                 temp = I915_READ(reg);
2521                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523                 if (temp & FDI_RX_SYMBOL_LOCK) {
2524                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2525                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2526                         break;
2527                 }
2528         }
2529         if (tries == 5)
2530                 DRM_ERROR("FDI train 2 fail!\n");
2531
2532         DRM_DEBUG_KMS("FDI train done\n");
2533
2534 }
2535
2536 static const int snb_b_fdi_train_param[] = {
2537         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2538         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2539         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2540         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2541 };
2542
2543 /* The FDI link training functions for SNB/Cougarpoint. */
2544 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2545 {
2546         struct drm_device *dev = crtc->dev;
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549         int pipe = intel_crtc->pipe;
2550         u32 reg, temp, i, retry;
2551
2552         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553            for train result */
2554         reg = FDI_RX_IMR(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~FDI_RX_SYMBOL_LOCK;
2557         temp &= ~FDI_RX_BIT_LOCK;
2558         I915_WRITE(reg, temp);
2559
2560         POSTING_READ(reg);
2561         udelay(150);
2562
2563         /* enable CPU FDI TX and PCH FDI RX */
2564         reg = FDI_TX_CTL(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~(7 << 19);
2567         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2568         temp &= ~FDI_LINK_TRAIN_NONE;
2569         temp |= FDI_LINK_TRAIN_PATTERN_1;
2570         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571         /* SNB-B */
2572         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2574
2575         reg = FDI_RX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         if (HAS_PCH_CPT(dev)) {
2578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580         } else {
2581                 temp &= ~FDI_LINK_TRAIN_NONE;
2582                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583         }
2584         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2585
2586         POSTING_READ(reg);
2587         udelay(150);
2588
2589         if (HAS_PCH_CPT(dev))
2590                 cpt_phase_pointer_enable(dev, pipe);
2591
2592         for (i = 0; i < 4; i++) {
2593                 reg = FDI_TX_CTL(pipe);
2594                 temp = I915_READ(reg);
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 temp |= snb_b_fdi_train_param[i];
2597                 I915_WRITE(reg, temp);
2598
2599                 POSTING_READ(reg);
2600                 udelay(500);
2601
2602                 for (retry = 0; retry < 5; retry++) {
2603                         reg = FDI_RX_IIR(pipe);
2604                         temp = I915_READ(reg);
2605                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2606                         if (temp & FDI_RX_BIT_LOCK) {
2607                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2608                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2609                                 break;
2610                         }
2611                         udelay(50);
2612                 }
2613                 if (retry < 5)
2614                         break;
2615         }
2616         if (i == 4)
2617                 DRM_ERROR("FDI train 1 fail!\n");
2618
2619         /* Train 2 */
2620         reg = FDI_TX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_LINK_TRAIN_NONE;
2623         temp |= FDI_LINK_TRAIN_PATTERN_2;
2624         if (IS_GEN6(dev)) {
2625                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626                 /* SNB-B */
2627                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628         }
2629         I915_WRITE(reg, temp);
2630
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         if (HAS_PCH_CPT(dev)) {
2634                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636         } else {
2637                 temp &= ~FDI_LINK_TRAIN_NONE;
2638                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639         }
2640         I915_WRITE(reg, temp);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654
2655                 for (retry = 0; retry < 5; retry++) {
2656                         reg = FDI_RX_IIR(pipe);
2657                         temp = I915_READ(reg);
2658                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659                         if (temp & FDI_RX_SYMBOL_LOCK) {
2660                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2661                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2662                                 break;
2663                         }
2664                         udelay(50);
2665                 }
2666                 if (retry < 5)
2667                         break;
2668         }
2669         if (i == 4)
2670                 DRM_ERROR("FDI train 2 fail!\n");
2671
2672         DRM_DEBUG_KMS("FDI train done.\n");
2673 }
2674
2675 /* Manual link training for Ivy Bridge A0 parts */
2676 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2677 {
2678         struct drm_device *dev = crtc->dev;
2679         struct drm_i915_private *dev_priv = dev->dev_private;
2680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2681         int pipe = intel_crtc->pipe;
2682         u32 reg, temp, i;
2683
2684         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2685            for train result */
2686         reg = FDI_RX_IMR(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_RX_SYMBOL_LOCK;
2689         temp &= ~FDI_RX_BIT_LOCK;
2690         I915_WRITE(reg, temp);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         /* enable CPU FDI TX and PCH FDI RX */
2696         reg = FDI_TX_CTL(pipe);
2697         temp = I915_READ(reg);
2698         temp &= ~(7 << 19);
2699         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2700         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2701         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2702         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2703         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2704         temp |= FDI_COMPOSITE_SYNC;
2705         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2706
2707         reg = FDI_RX_CTL(pipe);
2708         temp = I915_READ(reg);
2709         temp &= ~FDI_LINK_TRAIN_AUTO;
2710         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2711         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2712         temp |= FDI_COMPOSITE_SYNC;
2713         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2714
2715         POSTING_READ(reg);
2716         udelay(150);
2717
2718         if (HAS_PCH_CPT(dev))
2719                 cpt_phase_pointer_enable(dev, pipe);
2720
2721         for (i = 0; i < 4; i++) {
2722                 reg = FDI_TX_CTL(pipe);
2723                 temp = I915_READ(reg);
2724                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725                 temp |= snb_b_fdi_train_param[i];
2726                 I915_WRITE(reg, temp);
2727
2728                 POSTING_READ(reg);
2729                 udelay(500);
2730
2731                 reg = FDI_RX_IIR(pipe);
2732                 temp = I915_READ(reg);
2733                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2734
2735                 if (temp & FDI_RX_BIT_LOCK ||
2736                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2737                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2738                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2739                         break;
2740                 }
2741         }
2742         if (i == 4)
2743                 DRM_ERROR("FDI train 1 fail!\n");
2744
2745         /* Train 2 */
2746         reg = FDI_TX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2749         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2750         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2751         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2752         I915_WRITE(reg, temp);
2753
2754         reg = FDI_RX_CTL(pipe);
2755         temp = I915_READ(reg);
2756         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2757         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2758         I915_WRITE(reg, temp);
2759
2760         POSTING_READ(reg);
2761         udelay(150);
2762
2763         for (i = 0; i < 4; i++) {
2764                 reg = FDI_TX_CTL(pipe);
2765                 temp = I915_READ(reg);
2766                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767                 temp |= snb_b_fdi_train_param[i];
2768                 I915_WRITE(reg, temp);
2769
2770                 POSTING_READ(reg);
2771                 udelay(500);
2772
2773                 reg = FDI_RX_IIR(pipe);
2774                 temp = I915_READ(reg);
2775                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2776
2777                 if (temp & FDI_RX_SYMBOL_LOCK) {
2778                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2779                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2780                         break;
2781                 }
2782         }
2783         if (i == 4)
2784                 DRM_ERROR("FDI train 2 fail!\n");
2785
2786         DRM_DEBUG_KMS("FDI train done.\n");
2787 }
2788
2789 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2790 {
2791         struct drm_device *dev = crtc->dev;
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2794         int pipe = intel_crtc->pipe;
2795         u32 reg, temp;
2796
2797         /* Write the TU size bits so error detection works */
2798         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2799                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2800
2801         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2802         reg = FDI_RX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         temp &= ~((0x7 << 19) | (0x7 << 16));
2805         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2806         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2807         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2808
2809         POSTING_READ(reg);
2810         udelay(200);
2811
2812         /* Switch from Rawclk to PCDclk */
2813         temp = I915_READ(reg);
2814         I915_WRITE(reg, temp | FDI_PCDCLK);
2815
2816         POSTING_READ(reg);
2817         udelay(200);
2818
2819         /* Enable CPU FDI TX PLL, always on for Ironlake */
2820         reg = FDI_TX_CTL(pipe);
2821         temp = I915_READ(reg);
2822         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2823                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2824
2825                 POSTING_READ(reg);
2826                 udelay(100);
2827         }
2828 }
2829
2830 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2831 {
2832         struct drm_i915_private *dev_priv = dev->dev_private;
2833         u32 flags = I915_READ(SOUTH_CHICKEN1);
2834
2835         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2836         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2837         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2838         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2839         POSTING_READ(SOUTH_CHICKEN1);
2840 }
2841 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2842 {
2843         struct drm_device *dev = crtc->dev;
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846         int pipe = intel_crtc->pipe;
2847         u32 reg, temp;
2848
2849         /* disable CPU FDI tx and PCH FDI rx */
2850         reg = FDI_TX_CTL(pipe);
2851         temp = I915_READ(reg);
2852         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2853         POSTING_READ(reg);
2854
2855         reg = FDI_RX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         temp &= ~(0x7 << 16);
2858         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2859         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2860
2861         POSTING_READ(reg);
2862         udelay(100);
2863
2864         /* Ironlake workaround, disable clock pointer after downing FDI */
2865         if (HAS_PCH_IBX(dev)) {
2866                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2867                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2868                            I915_READ(FDI_RX_CHICKEN(pipe) &
2869                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2870         } else if (HAS_PCH_CPT(dev)) {
2871                 cpt_phase_pointer_disable(dev, pipe);
2872         }
2873
2874         /* still set train pattern 1 */
2875         reg = FDI_TX_CTL(pipe);
2876         temp = I915_READ(reg);
2877         temp &= ~FDI_LINK_TRAIN_NONE;
2878         temp |= FDI_LINK_TRAIN_PATTERN_1;
2879         I915_WRITE(reg, temp);
2880
2881         reg = FDI_RX_CTL(pipe);
2882         temp = I915_READ(reg);
2883         if (HAS_PCH_CPT(dev)) {
2884                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2885                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2886         } else {
2887                 temp &= ~FDI_LINK_TRAIN_NONE;
2888                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2889         }
2890         /* BPC in FDI rx is consistent with that in PIPECONF */
2891         temp &= ~(0x07 << 16);
2892         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2893         I915_WRITE(reg, temp);
2894
2895         POSTING_READ(reg);
2896         udelay(100);
2897 }
2898
2899 /*
2900  * When we disable a pipe, we need to clear any pending scanline wait events
2901  * to avoid hanging the ring, which we assume we are waiting on.
2902  */
2903 static void intel_clear_scanline_wait(struct drm_device *dev)
2904 {
2905         struct drm_i915_private *dev_priv = dev->dev_private;
2906         struct intel_ring_buffer *ring;
2907         u32 tmp;
2908
2909         if (IS_GEN2(dev))
2910                 /* Can't break the hang on i8xx */
2911                 return;
2912
2913         ring = LP_RING(dev_priv);
2914         tmp = I915_READ_CTL(ring);
2915         if (tmp & RING_WAIT)
2916                 I915_WRITE_CTL(ring, tmp);
2917 }
2918
2919 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2920 {
2921         struct drm_i915_gem_object *obj;
2922         struct drm_i915_private *dev_priv;
2923
2924         if (crtc->fb == NULL)
2925                 return;
2926
2927         obj = to_intel_framebuffer(crtc->fb)->obj;
2928         dev_priv = crtc->dev->dev_private;
2929         wait_event(dev_priv->pending_flip_queue,
2930                    atomic_read(&obj->pending_flip) == 0);
2931 }
2932
2933 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2934 {
2935         struct drm_device *dev = crtc->dev;
2936         struct drm_mode_config *mode_config = &dev->mode_config;
2937         struct intel_encoder *encoder;
2938
2939         /*
2940          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2941          * must be driven by its own crtc; no sharing is possible.
2942          */
2943         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2944                 if (encoder->base.crtc != crtc)
2945                         continue;
2946
2947                 switch (encoder->type) {
2948                 case INTEL_OUTPUT_EDP:
2949                         if (!intel_encoder_is_pch_edp(&encoder->base))
2950                                 return false;
2951                         continue;
2952                 }
2953         }
2954
2955         return true;
2956 }
2957
2958 /*
2959  * Enable PCH resources required for PCH ports:
2960  *   - PCH PLLs
2961  *   - FDI training & RX/TX
2962  *   - update transcoder timings
2963  *   - DP transcoding bits
2964  *   - transcoder
2965  */
2966 static void ironlake_pch_enable(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971         int pipe = intel_crtc->pipe;
2972         u32 reg, temp, transc_sel;
2973
2974         /* For PCH output, training FDI link */
2975         dev_priv->display.fdi_link_train(crtc);
2976
2977         intel_enable_pch_pll(dev_priv, pipe);
2978
2979         if (HAS_PCH_CPT(dev)) {
2980                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2981                         TRANSC_DPLLB_SEL;
2982
2983                 /* Be sure PCH DPLL SEL is set */
2984                 temp = I915_READ(PCH_DPLL_SEL);
2985                 if (pipe == 0) {
2986                         temp &= ~(TRANSA_DPLLB_SEL);
2987                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2988                 } else if (pipe == 1) {
2989                         temp &= ~(TRANSB_DPLLB_SEL);
2990                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2991                 } else if (pipe == 2) {
2992                         temp &= ~(TRANSC_DPLLB_SEL);
2993                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2994                 }
2995                 I915_WRITE(PCH_DPLL_SEL, temp);
2996         }
2997
2998         /* set transcoder timing, panel must allow it */
2999         assert_panel_unlocked(dev_priv, pipe);
3000         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3001         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3002         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3003
3004         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3005         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3006         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3007         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3008
3009         intel_fdi_normal_train(crtc);
3010
3011         /* For PCH DP, enable TRANS_DP_CTL */
3012         if (HAS_PCH_CPT(dev) &&
3013             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3014              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3015                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3016                 reg = TRANS_DP_CTL(pipe);
3017                 temp = I915_READ(reg);
3018                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3019                           TRANS_DP_SYNC_MASK |
3020                           TRANS_DP_BPC_MASK);
3021                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3022                          TRANS_DP_ENH_FRAMING);
3023                 temp |= bpc << 9; /* same format but at 11:9 */
3024
3025                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3026                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3027                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3028                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3029
3030                 switch (intel_trans_dp_port_sel(crtc)) {
3031                 case PCH_DP_B:
3032                         temp |= TRANS_DP_PORT_SEL_B;
3033                         break;
3034                 case PCH_DP_C:
3035                         temp |= TRANS_DP_PORT_SEL_C;
3036                         break;
3037                 case PCH_DP_D:
3038                         temp |= TRANS_DP_PORT_SEL_D;
3039                         break;
3040                 default:
3041                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3042                         temp |= TRANS_DP_PORT_SEL_B;
3043                         break;
3044                 }
3045
3046                 I915_WRITE(reg, temp);
3047         }
3048
3049         intel_enable_transcoder(dev_priv, pipe);
3050 }
3051
3052 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3053 {
3054         struct drm_i915_private *dev_priv = dev->dev_private;
3055         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3056         u32 temp;
3057
3058         temp = I915_READ(dslreg);
3059         udelay(500);
3060         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3061                 /* Without this, mode sets may fail silently on FDI */
3062                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3063                 udelay(250);
3064                 I915_WRITE(tc2reg, 0);
3065                 if (wait_for(I915_READ(dslreg) != temp, 5))
3066                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3067         }
3068 }
3069
3070 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3071 {
3072         struct drm_device *dev = crtc->dev;
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075         int pipe = intel_crtc->pipe;
3076         int plane = intel_crtc->plane;
3077         u32 temp;
3078         bool is_pch_port;
3079
3080         if (intel_crtc->active)
3081                 return;
3082
3083         intel_crtc->active = true;
3084         intel_update_watermarks(dev);
3085
3086         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3087                 temp = I915_READ(PCH_LVDS);
3088                 if ((temp & LVDS_PORT_EN) == 0)
3089                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3090         }
3091
3092         is_pch_port = intel_crtc_driving_pch(crtc);
3093
3094         if (is_pch_port)
3095                 ironlake_fdi_pll_enable(crtc);
3096         else
3097                 ironlake_fdi_disable(crtc);
3098
3099         /* Enable panel fitting for LVDS */
3100         if (dev_priv->pch_pf_size &&
3101             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3102                 /* Force use of hard-coded filter coefficients
3103                  * as some pre-programmed values are broken,
3104                  * e.g. x201.
3105                  */
3106                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3107                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3108                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3109         }
3110
3111         /*
3112          * On ILK+ LUT must be loaded before the pipe is running but with
3113          * clocks enabled
3114          */
3115         intel_crtc_load_lut(crtc);
3116
3117         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3118         intel_enable_plane(dev_priv, plane, pipe);
3119
3120         if (is_pch_port)
3121                 ironlake_pch_enable(crtc);
3122
3123         mutex_lock(&dev->struct_mutex);
3124         intel_update_fbc(dev);
3125         mutex_unlock(&dev->struct_mutex);
3126
3127         intel_crtc_update_cursor(crtc, true);
3128 }
3129
3130 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3131 {
3132         struct drm_device *dev = crtc->dev;
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135         int pipe = intel_crtc->pipe;
3136         int plane = intel_crtc->plane;
3137         u32 reg, temp;
3138
3139         if (!intel_crtc->active)
3140                 return;
3141
3142         intel_crtc_wait_for_pending_flips(crtc);
3143         drm_vblank_off(dev, pipe);
3144         intel_crtc_update_cursor(crtc, false);
3145
3146         intel_disable_plane(dev_priv, plane, pipe);
3147
3148         if (dev_priv->cfb_plane == plane)
3149                 intel_disable_fbc(dev);
3150
3151         intel_disable_pipe(dev_priv, pipe);
3152
3153         /* Disable PF */
3154         I915_WRITE(PF_CTL(pipe), 0);
3155         I915_WRITE(PF_WIN_SZ(pipe), 0);
3156
3157         ironlake_fdi_disable(crtc);
3158
3159         /* This is a horrible layering violation; we should be doing this in
3160          * the connector/encoder ->prepare instead, but we don't always have
3161          * enough information there about the config to know whether it will
3162          * actually be necessary or just cause undesired flicker.
3163          */
3164         intel_disable_pch_ports(dev_priv, pipe);
3165
3166         intel_disable_transcoder(dev_priv, pipe);
3167
3168         if (HAS_PCH_CPT(dev)) {
3169                 /* disable TRANS_DP_CTL */
3170                 reg = TRANS_DP_CTL(pipe);
3171                 temp = I915_READ(reg);
3172                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3173                 temp |= TRANS_DP_PORT_SEL_NONE;
3174                 I915_WRITE(reg, temp);
3175
3176                 /* disable DPLL_SEL */
3177                 temp = I915_READ(PCH_DPLL_SEL);
3178                 switch (pipe) {
3179                 case 0:
3180                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3181                         break;
3182                 case 1:
3183                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3184                         break;
3185                 case 2:
3186                         /* C shares PLL A or B */
3187                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3188                         break;
3189                 default:
3190                         BUG(); /* wtf */
3191                 }
3192                 I915_WRITE(PCH_DPLL_SEL, temp);
3193         }
3194
3195         /* disable PCH DPLL */
3196         if (!intel_crtc->no_pll)
3197                 intel_disable_pch_pll(dev_priv, pipe);
3198
3199         /* Switch from PCDclk to Rawclk */
3200         reg = FDI_RX_CTL(pipe);
3201         temp = I915_READ(reg);
3202         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3203
3204         /* Disable CPU FDI TX PLL */
3205         reg = FDI_TX_CTL(pipe);
3206         temp = I915_READ(reg);
3207         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3208
3209         POSTING_READ(reg);
3210         udelay(100);
3211
3212         reg = FDI_RX_CTL(pipe);
3213         temp = I915_READ(reg);
3214         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3215
3216         /* Wait for the clocks to turn off. */
3217         POSTING_READ(reg);
3218         udelay(100);
3219
3220         intel_crtc->active = false;
3221         intel_update_watermarks(dev);
3222
3223         mutex_lock(&dev->struct_mutex);
3224         intel_update_fbc(dev);
3225         intel_clear_scanline_wait(dev);
3226         mutex_unlock(&dev->struct_mutex);
3227 }
3228
3229 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3230 {
3231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3232         int pipe = intel_crtc->pipe;
3233         int plane = intel_crtc->plane;
3234
3235         /* XXX: When our outputs are all unaware of DPMS modes other than off
3236          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3237          */
3238         switch (mode) {
3239         case DRM_MODE_DPMS_ON:
3240         case DRM_MODE_DPMS_STANDBY:
3241         case DRM_MODE_DPMS_SUSPEND:
3242                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3243                 ironlake_crtc_enable(crtc);
3244                 break;
3245
3246         case DRM_MODE_DPMS_OFF:
3247                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3248                 ironlake_crtc_disable(crtc);
3249                 break;
3250         }
3251 }
3252
3253 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3254 {
3255         if (!enable && intel_crtc->overlay) {
3256                 struct drm_device *dev = intel_crtc->base.dev;
3257                 struct drm_i915_private *dev_priv = dev->dev_private;
3258
3259                 mutex_lock(&dev->struct_mutex);
3260                 dev_priv->mm.interruptible = false;
3261                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3262                 dev_priv->mm.interruptible = true;
3263                 mutex_unlock(&dev->struct_mutex);
3264         }
3265
3266         /* Let userspace switch the overlay on again. In most cases userspace
3267          * has to recompute where to put it anyway.
3268          */
3269 }
3270
3271 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3272 {
3273         struct drm_device *dev = crtc->dev;
3274         struct drm_i915_private *dev_priv = dev->dev_private;
3275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3276         int pipe = intel_crtc->pipe;
3277         int plane = intel_crtc->plane;
3278
3279         if (intel_crtc->active)
3280                 return;
3281
3282         intel_crtc->active = true;
3283         intel_update_watermarks(dev);
3284
3285         intel_enable_pll(dev_priv, pipe);
3286         intel_enable_pipe(dev_priv, pipe, false);
3287         intel_enable_plane(dev_priv, plane, pipe);
3288
3289         intel_crtc_load_lut(crtc);
3290         intel_update_fbc(dev);
3291
3292         /* Give the overlay scaler a chance to enable if it's on this pipe */
3293         intel_crtc_dpms_overlay(intel_crtc, true);
3294         intel_crtc_update_cursor(crtc, true);
3295 }
3296
3297 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3298 {
3299         struct drm_device *dev = crtc->dev;
3300         struct drm_i915_private *dev_priv = dev->dev_private;
3301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302         int pipe = intel_crtc->pipe;
3303         int plane = intel_crtc->plane;
3304
3305         if (!intel_crtc->active)
3306                 return;
3307
3308         /* Give the overlay scaler a chance to disable if it's on this pipe */
3309         intel_crtc_wait_for_pending_flips(crtc);
3310         drm_vblank_off(dev, pipe);
3311         intel_crtc_dpms_overlay(intel_crtc, false);
3312         intel_crtc_update_cursor(crtc, false);
3313
3314         if (dev_priv->cfb_plane == plane)
3315                 intel_disable_fbc(dev);
3316
3317         intel_disable_plane(dev_priv, plane, pipe);
3318         intel_disable_pipe(dev_priv, pipe);
3319         intel_disable_pll(dev_priv, pipe);
3320
3321         intel_crtc->active = false;
3322         intel_update_fbc(dev);
3323         intel_update_watermarks(dev);
3324         intel_clear_scanline_wait(dev);
3325 }
3326
3327 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3328 {
3329         /* XXX: When our outputs are all unaware of DPMS modes other than off
3330          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3331          */
3332         switch (mode) {
3333         case DRM_MODE_DPMS_ON:
3334         case DRM_MODE_DPMS_STANDBY:
3335         case DRM_MODE_DPMS_SUSPEND:
3336                 i9xx_crtc_enable(crtc);
3337                 break;
3338         case DRM_MODE_DPMS_OFF:
3339                 i9xx_crtc_disable(crtc);
3340                 break;
3341         }
3342 }
3343
3344 /**
3345  * Sets the power management mode of the pipe and plane.
3346  */
3347 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3348 {
3349         struct drm_device *dev = crtc->dev;
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351         struct drm_i915_master_private *master_priv;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353         int pipe = intel_crtc->pipe;
3354         bool enabled;
3355
3356         if (intel_crtc->dpms_mode == mode)
3357                 return;
3358
3359         intel_crtc->dpms_mode = mode;
3360
3361         dev_priv->display.dpms(crtc, mode);
3362
3363         if (!dev->primary->master)
3364                 return;
3365
3366         master_priv = dev->primary->master->driver_priv;
3367         if (!master_priv->sarea_priv)
3368                 return;
3369
3370         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3371
3372         switch (pipe) {
3373         case 0:
3374                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3375                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3376                 break;
3377         case 1:
3378                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3379                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3380                 break;
3381         default:
3382                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3383                 break;
3384         }
3385 }
3386
3387 static void intel_crtc_disable(struct drm_crtc *crtc)
3388 {
3389         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3390         struct drm_device *dev = crtc->dev;
3391
3392         /* Flush any pending WAITs before we disable the pipe. Note that
3393          * we need to drop the struct_mutex in order to acquire it again
3394          * during the lowlevel dpms routines around a couple of the
3395          * operations. It does not look trivial nor desirable to move
3396          * that locking higher. So instead we leave a window for the
3397          * submission of further commands on the fb before we can actually
3398          * disable it. This race with userspace exists anyway, and we can
3399          * only rely on the pipe being disabled by userspace after it
3400          * receives the hotplug notification and has flushed any pending
3401          * batches.
3402          */
3403         if (crtc->fb) {
3404                 mutex_lock(&dev->struct_mutex);
3405                 intel_finish_fb(crtc->fb);
3406                 mutex_unlock(&dev->struct_mutex);
3407         }
3408
3409         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3410         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3411         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3412
3413         if (crtc->fb) {
3414                 mutex_lock(&dev->struct_mutex);
3415                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3416                 mutex_unlock(&dev->struct_mutex);
3417         }
3418 }
3419
3420 /* Prepare for a mode set.
3421  *
3422  * Note we could be a lot smarter here.  We need to figure out which outputs
3423  * will be enabled, which disabled (in short, how the config will changes)
3424  * and perform the minimum necessary steps to accomplish that, e.g. updating
3425  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3426  * panel fitting is in the proper state, etc.
3427  */
3428 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3429 {
3430         i9xx_crtc_disable(crtc);
3431 }
3432
3433 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3434 {
3435         i9xx_crtc_enable(crtc);
3436 }
3437
3438 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3439 {
3440         ironlake_crtc_disable(crtc);
3441 }
3442
3443 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3444 {
3445         ironlake_crtc_enable(crtc);
3446 }
3447
3448 void intel_encoder_prepare(struct drm_encoder *encoder)
3449 {
3450         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3451         /* lvds has its own version of prepare see intel_lvds_prepare */
3452         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3453 }
3454
3455 void intel_encoder_commit(struct drm_encoder *encoder)
3456 {
3457         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3458         struct drm_device *dev = encoder->dev;
3459         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3460         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3461
3462         /* lvds has its own version of commit see intel_lvds_commit */
3463         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3464
3465         if (HAS_PCH_CPT(dev))
3466                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3467 }
3468
3469 void intel_encoder_destroy(struct drm_encoder *encoder)
3470 {
3471         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3472
3473         drm_encoder_cleanup(encoder);
3474         kfree(intel_encoder);
3475 }
3476
3477 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3478                                   struct drm_display_mode *mode,
3479                                   struct drm_display_mode *adjusted_mode)
3480 {
3481         struct drm_device *dev = crtc->dev;
3482
3483         if (HAS_PCH_SPLIT(dev)) {
3484                 /* FDI link clock is fixed at 2.7G */
3485                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3486                         return false;
3487         }
3488
3489         /* All interlaced capable intel hw wants timings in frames. Note though
3490          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3491          * timings, so we need to be careful not to clobber these.*/
3492         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3493                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3494
3495         return true;
3496 }
3497
3498 static int i945_get_display_clock_speed(struct drm_device *dev)
3499 {
3500         return 400000;
3501 }
3502
3503 static int i915_get_display_clock_speed(struct drm_device *dev)
3504 {
3505         return 333000;
3506 }
3507
3508 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3509 {
3510         return 200000;
3511 }
3512
3513 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3514 {
3515         u16 gcfgc = 0;
3516
3517         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3518
3519         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3520                 return 133000;
3521         else {
3522                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3523                 case GC_DISPLAY_CLOCK_333_MHZ:
3524                         return 333000;
3525                 default:
3526                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3527                         return 190000;
3528                 }
3529         }
3530 }
3531
3532 static int i865_get_display_clock_speed(struct drm_device *dev)
3533 {
3534         return 266000;
3535 }
3536
3537 static int i855_get_display_clock_speed(struct drm_device *dev)
3538 {
3539         u16 hpllcc = 0;
3540         /* Assume that the hardware is in the high speed state.  This
3541          * should be the default.
3542          */
3543         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3544         case GC_CLOCK_133_200:
3545         case GC_CLOCK_100_200:
3546                 return 200000;
3547         case GC_CLOCK_166_250:
3548                 return 250000;
3549         case GC_CLOCK_100_133:
3550                 return 133000;
3551         }
3552
3553         /* Shouldn't happen */
3554         return 0;
3555 }
3556
3557 static int i830_get_display_clock_speed(struct drm_device *dev)
3558 {
3559         return 133000;
3560 }
3561
3562 struct fdi_m_n {
3563         u32        tu;
3564         u32        gmch_m;
3565         u32        gmch_n;
3566         u32        link_m;
3567         u32        link_n;
3568 };
3569
3570 static void
3571 fdi_reduce_ratio(u32 *num, u32 *den)
3572 {
3573         while (*num > 0xffffff || *den > 0xffffff) {
3574                 *num >>= 1;
3575                 *den >>= 1;
3576         }
3577 }
3578
3579 static void
3580 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3581                      int link_clock, struct fdi_m_n *m_n)
3582 {
3583         m_n->tu = 64; /* default size */
3584
3585         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3586         m_n->gmch_m = bits_per_pixel * pixel_clock;
3587         m_n->gmch_n = link_clock * nlanes * 8;
3588         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3589
3590         m_n->link_m = pixel_clock;
3591         m_n->link_n = link_clock;
3592         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3593 }
3594
3595
3596 struct intel_watermark_params {
3597         unsigned long fifo_size;
3598         unsigned long max_wm;
3599         unsigned long default_wm;
3600         unsigned long guard_size;
3601         unsigned long cacheline_size;
3602 };
3603
3604 /* Pineview has different values for various configs */
3605 static const struct intel_watermark_params pineview_display_wm = {
3606         PINEVIEW_DISPLAY_FIFO,
3607         PINEVIEW_MAX_WM,
3608         PINEVIEW_DFT_WM,
3609         PINEVIEW_GUARD_WM,
3610         PINEVIEW_FIFO_LINE_SIZE
3611 };
3612 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3613         PINEVIEW_DISPLAY_FIFO,
3614         PINEVIEW_MAX_WM,
3615         PINEVIEW_DFT_HPLLOFF_WM,
3616         PINEVIEW_GUARD_WM,
3617         PINEVIEW_FIFO_LINE_SIZE
3618 };
3619 static const struct intel_watermark_params pineview_cursor_wm = {
3620         PINEVIEW_CURSOR_FIFO,
3621         PINEVIEW_CURSOR_MAX_WM,
3622         PINEVIEW_CURSOR_DFT_WM,
3623         PINEVIEW_CURSOR_GUARD_WM,
3624         PINEVIEW_FIFO_LINE_SIZE,
3625 };
3626 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3627         PINEVIEW_CURSOR_FIFO,
3628         PINEVIEW_CURSOR_MAX_WM,
3629         PINEVIEW_CURSOR_DFT_WM,
3630         PINEVIEW_CURSOR_GUARD_WM,
3631         PINEVIEW_FIFO_LINE_SIZE
3632 };
3633 static const struct intel_watermark_params g4x_wm_info = {
3634         G4X_FIFO_SIZE,
3635         G4X_MAX_WM,
3636         G4X_MAX_WM,
3637         2,
3638         G4X_FIFO_LINE_SIZE,
3639 };
3640 static const struct intel_watermark_params g4x_cursor_wm_info = {
3641         I965_CURSOR_FIFO,
3642         I965_CURSOR_MAX_WM,
3643         I965_CURSOR_DFT_WM,
3644         2,
3645         G4X_FIFO_LINE_SIZE,
3646 };
3647 static const struct intel_watermark_params i965_cursor_wm_info = {
3648         I965_CURSOR_FIFO,
3649         I965_CURSOR_MAX_WM,
3650         I965_CURSOR_DFT_WM,
3651         2,
3652         I915_FIFO_LINE_SIZE,
3653 };
3654 static const struct intel_watermark_params i945_wm_info = {
3655         I945_FIFO_SIZE,
3656         I915_MAX_WM,
3657         1,
3658         2,
3659         I915_FIFO_LINE_SIZE
3660 };
3661 static const struct intel_watermark_params i915_wm_info = {
3662         I915_FIFO_SIZE,
3663         I915_MAX_WM,
3664         1,
3665         2,
3666         I915_FIFO_LINE_SIZE
3667 };
3668 static const struct intel_watermark_params i855_wm_info = {
3669         I855GM_FIFO_SIZE,
3670         I915_MAX_WM,
3671         1,
3672         2,
3673         I830_FIFO_LINE_SIZE
3674 };
3675 static const struct intel_watermark_params i830_wm_info = {
3676         I830_FIFO_SIZE,
3677         I915_MAX_WM,
3678         1,
3679         2,
3680         I830_FIFO_LINE_SIZE
3681 };
3682
3683 static const struct intel_watermark_params ironlake_display_wm_info = {
3684         ILK_DISPLAY_FIFO,
3685         ILK_DISPLAY_MAXWM,
3686         ILK_DISPLAY_DFTWM,
3687         2,
3688         ILK_FIFO_LINE_SIZE
3689 };
3690 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3691         ILK_CURSOR_FIFO,
3692         ILK_CURSOR_MAXWM,
3693         ILK_CURSOR_DFTWM,
3694         2,
3695         ILK_FIFO_LINE_SIZE
3696 };
3697 static const struct intel_watermark_params ironlake_display_srwm_info = {
3698         ILK_DISPLAY_SR_FIFO,
3699         ILK_DISPLAY_MAX_SRWM,
3700         ILK_DISPLAY_DFT_SRWM,
3701         2,
3702         ILK_FIFO_LINE_SIZE
3703 };
3704 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3705         ILK_CURSOR_SR_FIFO,
3706         ILK_CURSOR_MAX_SRWM,
3707         ILK_CURSOR_DFT_SRWM,
3708         2,
3709         ILK_FIFO_LINE_SIZE
3710 };
3711
3712 static const struct intel_watermark_params sandybridge_display_wm_info = {
3713         SNB_DISPLAY_FIFO,
3714         SNB_DISPLAY_MAXWM,
3715         SNB_DISPLAY_DFTWM,
3716         2,
3717         SNB_FIFO_LINE_SIZE
3718 };
3719 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3720         SNB_CURSOR_FIFO,
3721         SNB_CURSOR_MAXWM,
3722         SNB_CURSOR_DFTWM,
3723         2,
3724         SNB_FIFO_LINE_SIZE
3725 };
3726 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3727         SNB_DISPLAY_SR_FIFO,
3728         SNB_DISPLAY_MAX_SRWM,
3729         SNB_DISPLAY_DFT_SRWM,
3730         2,
3731         SNB_FIFO_LINE_SIZE
3732 };
3733 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3734         SNB_CURSOR_SR_FIFO,
3735         SNB_CURSOR_MAX_SRWM,
3736         SNB_CURSOR_DFT_SRWM,
3737         2,
3738         SNB_FIFO_LINE_SIZE
3739 };
3740
3741
3742 /**
3743  * intel_calculate_wm - calculate watermark level
3744  * @clock_in_khz: pixel clock
3745  * @wm: chip FIFO params
3746  * @pixel_size: display pixel size
3747  * @latency_ns: memory latency for the platform
3748  *
3749  * Calculate the watermark level (the level at which the display plane will
3750  * start fetching from memory again).  Each chip has a different display
3751  * FIFO size and allocation, so the caller needs to figure that out and pass
3752  * in the correct intel_watermark_params structure.
3753  *
3754  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3755  * on the pixel size.  When it reaches the watermark level, it'll start
3756  * fetching FIFO line sized based chunks from memory until the FIFO fills
3757  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3758  * will occur, and a display engine hang could result.
3759  */
3760 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3761                                         const struct intel_watermark_params *wm,
3762                                         int fifo_size,
3763                                         int pixel_size,
3764                                         unsigned long latency_ns)
3765 {
3766         long entries_required, wm_size;
3767
3768         /*
3769          * Note: we need to make sure we don't overflow for various clock &
3770          * latency values.
3771          * clocks go from a few thousand to several hundred thousand.
3772          * latency is usually a few thousand
3773          */
3774         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3775                 1000;
3776         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3777
3778         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3779
3780         wm_size = fifo_size - (entries_required + wm->guard_size);
3781
3782         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3783
3784         /* Don't promote wm_size to unsigned... */
3785         if (wm_size > (long)wm->max_wm)
3786                 wm_size = wm->max_wm;
3787         if (wm_size <= 0)
3788                 wm_size = wm->default_wm;
3789         return wm_size;
3790 }
3791
3792 struct cxsr_latency {
3793         int is_desktop;
3794         int is_ddr3;
3795         unsigned long fsb_freq;
3796         unsigned long mem_freq;
3797         unsigned long display_sr;
3798         unsigned long display_hpll_disable;
3799         unsigned long cursor_sr;
3800         unsigned long cursor_hpll_disable;
3801 };
3802
3803 static const struct cxsr_latency cxsr_latency_table[] = {
3804         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3805         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3806         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3807         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3808         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3809
3810         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3811         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3812         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3813         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3814         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3815
3816         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3817         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3818         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3819         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3820         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3821
3822         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3823         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3824         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3825         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3826         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3827
3828         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3829         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3830         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3831         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3832         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3833
3834         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3835         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3836         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3837         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3838         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3839 };
3840
3841 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3842                                                          int is_ddr3,
3843                                                          int fsb,
3844                                                          int mem)
3845 {
3846         const struct cxsr_latency *latency;
3847         int i;
3848
3849         if (fsb == 0 || mem == 0)
3850                 return NULL;
3851
3852         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3853                 latency = &cxsr_latency_table[i];
3854                 if (is_desktop == latency->is_desktop &&
3855                     is_ddr3 == latency->is_ddr3 &&
3856                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3857                         return latency;
3858         }
3859
3860         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3861
3862         return NULL;
3863 }
3864
3865 static void pineview_disable_cxsr(struct drm_device *dev)
3866 {
3867         struct drm_i915_private *dev_priv = dev->dev_private;
3868
3869         /* deactivate cxsr */
3870         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3871 }
3872
3873 /*
3874  * Latency for FIFO fetches is dependent on several factors:
3875  *   - memory configuration (speed, channels)
3876  *   - chipset
3877  *   - current MCH state
3878  * It can be fairly high in some situations, so here we assume a fairly
3879  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3880  * set this value too high, the FIFO will fetch frequently to stay full)
3881  * and power consumption (set it too low to save power and we might see
3882  * FIFO underruns and display "flicker").
3883  *
3884  * A value of 5us seems to be a good balance; safe for very low end
3885  * platforms but not overly aggressive on lower latency configs.
3886  */
3887 static const int latency_ns = 5000;
3888
3889 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3890 {
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         uint32_t dsparb = I915_READ(DSPARB);
3893         int size;
3894
3895         size = dsparb & 0x7f;
3896         if (plane)
3897                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3898
3899         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3900                       plane ? "B" : "A", size);
3901
3902         return size;
3903 }
3904
3905 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3906 {
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908         uint32_t dsparb = I915_READ(DSPARB);
3909         int size;
3910
3911         size = dsparb & 0x1ff;
3912         if (plane)
3913                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3914         size >>= 1; /* Convert to cachelines */
3915
3916         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3917                       plane ? "B" : "A", size);
3918
3919         return size;
3920 }
3921
3922 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3923 {
3924         struct drm_i915_private *dev_priv = dev->dev_private;
3925         uint32_t dsparb = I915_READ(DSPARB);
3926         int size;
3927
3928         size = dsparb & 0x7f;
3929         size >>= 2; /* Convert to cachelines */
3930
3931         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3932                       plane ? "B" : "A",
3933                       size);
3934
3935         return size;
3936 }
3937
3938 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3939 {
3940         struct drm_i915_private *dev_priv = dev->dev_private;
3941         uint32_t dsparb = I915_READ(DSPARB);
3942         int size;
3943
3944         size = dsparb & 0x7f;
3945         size >>= 1; /* Convert to cachelines */
3946
3947         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3948                       plane ? "B" : "A", size);
3949
3950         return size;
3951 }
3952
3953 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3954 {
3955         struct drm_crtc *crtc, *enabled = NULL;
3956
3957         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3958                 if (crtc->enabled && crtc->fb) {
3959                         if (enabled)
3960                                 return NULL;
3961                         enabled = crtc;
3962                 }
3963         }
3964
3965         return enabled;
3966 }
3967
3968 static void pineview_update_wm(struct drm_device *dev)
3969 {
3970         struct drm_i915_private *dev_priv = dev->dev_private;
3971         struct drm_crtc *crtc;
3972         const struct cxsr_latency *latency;
3973         u32 reg;
3974         unsigned long wm;
3975
3976         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3977                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3978         if (!latency) {
3979                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3980                 pineview_disable_cxsr(dev);
3981                 return;
3982         }
3983
3984         crtc = single_enabled_crtc(dev);
3985         if (crtc) {
3986                 int clock = crtc->mode.clock;
3987                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3988
3989                 /* Display SR */
3990                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3991                                         pineview_display_wm.fifo_size,
3992                                         pixel_size, latency->display_sr);
3993                 reg = I915_READ(DSPFW1);
3994                 reg &= ~DSPFW_SR_MASK;
3995                 reg |= wm << DSPFW_SR_SHIFT;
3996                 I915_WRITE(DSPFW1, reg);
3997                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3998
3999                 /* cursor SR */
4000                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4001                                         pineview_display_wm.fifo_size,
4002                                         pixel_size, latency->cursor_sr);
4003                 reg = I915_READ(DSPFW3);
4004                 reg &= ~DSPFW_CURSOR_SR_MASK;
4005                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4006                 I915_WRITE(DSPFW3, reg);
4007
4008                 /* Display HPLL off SR */
4009                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4010                                         pineview_display_hplloff_wm.fifo_size,
4011                                         pixel_size, latency->display_hpll_disable);
4012                 reg = I915_READ(DSPFW3);
4013                 reg &= ~DSPFW_HPLL_SR_MASK;
4014                 reg |= wm & DSPFW_HPLL_SR_MASK;
4015                 I915_WRITE(DSPFW3, reg);
4016
4017                 /* cursor HPLL off SR */
4018                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4019                                         pineview_display_hplloff_wm.fifo_size,
4020                                         pixel_size, latency->cursor_hpll_disable);
4021                 reg = I915_READ(DSPFW3);
4022                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4023                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4024                 I915_WRITE(DSPFW3, reg);
4025                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4026
4027                 /* activate cxsr */
4028                 I915_WRITE(DSPFW3,
4029                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4030                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4031         } else {
4032                 pineview_disable_cxsr(dev);
4033                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4034         }
4035 }
4036
4037 static bool g4x_compute_wm0(struct drm_device *dev,
4038                             int plane,
4039                             const struct intel_watermark_params *display,
4040                             int display_latency_ns,
4041                             const struct intel_watermark_params *cursor,
4042                             int cursor_latency_ns,
4043                             int *plane_wm,
4044                             int *cursor_wm)
4045 {
4046         struct drm_crtc *crtc;
4047         int htotal, hdisplay, clock, pixel_size;
4048         int line_time_us, line_count;
4049         int entries, tlb_miss;
4050
4051         crtc = intel_get_crtc_for_plane(dev, plane);
4052         if (crtc->fb == NULL || !crtc->enabled) {
4053                 *cursor_wm = cursor->guard_size;
4054                 *plane_wm = display->guard_size;
4055                 return false;
4056         }
4057
4058         htotal = crtc->mode.htotal;
4059         hdisplay = crtc->mode.hdisplay;
4060         clock = crtc->mode.clock;
4061         pixel_size = crtc->fb->bits_per_pixel / 8;
4062
4063         /* Use the small buffer method to calculate plane watermark */
4064         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4065         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4066         if (tlb_miss > 0)
4067                 entries += tlb_miss;
4068         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4069         *plane_wm = entries + display->guard_size;
4070         if (*plane_wm > (int)display->max_wm)
4071                 *plane_wm = display->max_wm;
4072
4073         /* Use the large buffer method to calculate cursor watermark */
4074         line_time_us = ((htotal * 1000) / clock);
4075         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4076         entries = line_count * 64 * pixel_size;
4077         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4078         if (tlb_miss > 0)
4079                 entries += tlb_miss;
4080         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4081         *cursor_wm = entries + cursor->guard_size;
4082         if (*cursor_wm > (int)cursor->max_wm)
4083                 *cursor_wm = (int)cursor->max_wm;
4084
4085         return true;
4086 }
4087
4088 /*
4089  * Check the wm result.
4090  *
4091  * If any calculated watermark values is larger than the maximum value that
4092  * can be programmed into the associated watermark register, that watermark
4093  * must be disabled.
4094  */
4095 static bool g4x_check_srwm(struct drm_device *dev,
4096                            int display_wm, int cursor_wm,
4097                            const struct intel_watermark_params *display,
4098                            const struct intel_watermark_params *cursor)
4099 {
4100         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4101                       display_wm, cursor_wm);
4102
4103         if (display_wm > display->max_wm) {
4104                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4105                               display_wm, display->max_wm);
4106                 return false;
4107         }
4108
4109         if (cursor_wm > cursor->max_wm) {
4110                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4111                               cursor_wm, cursor->max_wm);
4112                 return false;
4113         }
4114
4115         if (!(display_wm || cursor_wm)) {
4116                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4117                 return false;
4118         }
4119
4120         return true;
4121 }
4122
4123 static bool g4x_compute_srwm(struct drm_device *dev,
4124                              int plane,
4125                              int latency_ns,
4126                              const struct intel_watermark_params *display,
4127                              const struct intel_watermark_params *cursor,
4128                              int *display_wm, int *cursor_wm)
4129 {
4130         struct drm_crtc *crtc;
4131         int hdisplay, htotal, pixel_size, clock;
4132         unsigned long line_time_us;
4133         int line_count, line_size;
4134         int small, large;
4135         int entries;
4136
4137         if (!latency_ns) {
4138                 *display_wm = *cursor_wm = 0;
4139                 return false;
4140         }
4141
4142         crtc = intel_get_crtc_for_plane(dev, plane);
4143         hdisplay = crtc->mode.hdisplay;
4144         htotal = crtc->mode.htotal;
4145         clock = crtc->mode.clock;
4146         pixel_size = crtc->fb->bits_per_pixel / 8;
4147
4148         line_time_us = (htotal * 1000) / clock;
4149         line_count = (latency_ns / line_time_us + 1000) / 1000;
4150         line_size = hdisplay * pixel_size;
4151
4152         /* Use the minimum of the small and large buffer method for primary */
4153         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4154         large = line_count * line_size;
4155
4156         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4157         *display_wm = entries + display->guard_size;
4158
4159         /* calculate the self-refresh watermark for display cursor */
4160         entries = line_count * pixel_size * 64;
4161         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4162         *cursor_wm = entries + cursor->guard_size;
4163
4164         return g4x_check_srwm(dev,
4165                               *display_wm, *cursor_wm,
4166                               display, cursor);
4167 }
4168
4169 #define single_plane_enabled(mask) is_power_of_2(mask)
4170
4171 static void g4x_update_wm(struct drm_device *dev)
4172 {
4173         static const int sr_latency_ns = 12000;
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4176         int plane_sr, cursor_sr;
4177         unsigned int enabled = 0;
4178
4179         if (g4x_compute_wm0(dev, 0,
4180                             &g4x_wm_info, latency_ns,
4181                             &g4x_cursor_wm_info, latency_ns,
4182                             &planea_wm, &cursora_wm))
4183                 enabled |= 1;
4184
4185         if (g4x_compute_wm0(dev, 1,
4186                             &g4x_wm_info, latency_ns,
4187                             &g4x_cursor_wm_info, latency_ns,
4188                             &planeb_wm, &cursorb_wm))
4189                 enabled |= 2;
4190
4191         plane_sr = cursor_sr = 0;
4192         if (single_plane_enabled(enabled) &&
4193             g4x_compute_srwm(dev, ffs(enabled) - 1,
4194                              sr_latency_ns,
4195                              &g4x_wm_info,
4196                              &g4x_cursor_wm_info,
4197                              &plane_sr, &cursor_sr))
4198                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4199         else
4200                 I915_WRITE(FW_BLC_SELF,
4201                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4202
4203         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4204                       planea_wm, cursora_wm,
4205                       planeb_wm, cursorb_wm,
4206                       plane_sr, cursor_sr);
4207
4208         I915_WRITE(DSPFW1,
4209                    (plane_sr << DSPFW_SR_SHIFT) |
4210                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4211                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4212                    planea_wm);
4213         I915_WRITE(DSPFW2,
4214                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4215                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4216         /* HPLL off in SR has some issues on G4x... disable it */
4217         I915_WRITE(DSPFW3,
4218                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4219                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4220 }
4221
4222 static void i965_update_wm(struct drm_device *dev)
4223 {
4224         struct drm_i915_private *dev_priv = dev->dev_private;
4225         struct drm_crtc *crtc;
4226         int srwm = 1;
4227         int cursor_sr = 16;
4228
4229         /* Calc sr entries for one plane configs */
4230         crtc = single_enabled_crtc(dev);
4231         if (crtc) {
4232                 /* self-refresh has much higher latency */
4233                 static const int sr_latency_ns = 12000;
4234                 int clock = crtc->mode.clock;
4235                 int htotal = crtc->mode.htotal;
4236                 int hdisplay = crtc->mode.hdisplay;
4237                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4238                 unsigned long line_time_us;
4239                 int entries;
4240
4241                 line_time_us = ((htotal * 1000) / clock);
4242
4243                 /* Use ns/us then divide to preserve precision */
4244                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4245                         pixel_size * hdisplay;
4246                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4247                 srwm = I965_FIFO_SIZE - entries;
4248                 if (srwm < 0)
4249                         srwm = 1;
4250                 srwm &= 0x1ff;
4251                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4252                               entries, srwm);
4253
4254                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4255                         pixel_size * 64;
4256                 entries = DIV_ROUND_UP(entries,
4257                                           i965_cursor_wm_info.cacheline_size);
4258                 cursor_sr = i965_cursor_wm_info.fifo_size -
4259                         (entries + i965_cursor_wm_info.guard_size);
4260
4261                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4262                         cursor_sr = i965_cursor_wm_info.max_wm;
4263
4264                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4265                               "cursor %d\n", srwm, cursor_sr);
4266
4267                 if (IS_CRESTLINE(dev))
4268                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4269         } else {
4270                 /* Turn off self refresh if both pipes are enabled */
4271                 if (IS_CRESTLINE(dev))
4272                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4273                                    & ~FW_BLC_SELF_EN);
4274         }
4275
4276         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4277                       srwm);
4278
4279         /* 965 has limitations... */
4280         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4281                    (8 << 16) | (8 << 8) | (8 << 0));
4282         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4283         /* update cursor SR watermark */
4284         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4285 }
4286
4287 static void i9xx_update_wm(struct drm_device *dev)
4288 {
4289         struct drm_i915_private *dev_priv = dev->dev_private;
4290         const struct intel_watermark_params *wm_info;
4291         uint32_t fwater_lo;
4292         uint32_t fwater_hi;
4293         int cwm, srwm = 1;
4294         int fifo_size;
4295         int planea_wm, planeb_wm;
4296         struct drm_crtc *crtc, *enabled = NULL;
4297
4298         if (IS_I945GM(dev))
4299                 wm_info = &i945_wm_info;
4300         else if (!IS_GEN2(dev))
4301                 wm_info = &i915_wm_info;
4302         else
4303                 wm_info = &i855_wm_info;
4304
4305         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4306         crtc = intel_get_crtc_for_plane(dev, 0);
4307         if (crtc->enabled && crtc->fb) {
4308                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4309                                                wm_info, fifo_size,
4310                                                crtc->fb->bits_per_pixel / 8,
4311                                                latency_ns);
4312                 enabled = crtc;
4313         } else
4314                 planea_wm = fifo_size - wm_info->guard_size;
4315
4316         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4317         crtc = intel_get_crtc_for_plane(dev, 1);
4318         if (crtc->enabled && crtc->fb) {
4319                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4320                                                wm_info, fifo_size,
4321                                                crtc->fb->bits_per_pixel / 8,
4322                                                latency_ns);
4323                 if (enabled == NULL)
4324                         enabled = crtc;
4325                 else
4326                         enabled = NULL;
4327         } else
4328                 planeb_wm = fifo_size - wm_info->guard_size;
4329
4330         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4331
4332         /*
4333          * Overlay gets an aggressive default since video jitter is bad.
4334          */
4335         cwm = 2;
4336
4337         /* Play safe and disable self-refresh before adjusting watermarks. */
4338         if (IS_I945G(dev) || IS_I945GM(dev))
4339                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4340         else if (IS_I915GM(dev))
4341                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4342
4343         /* Calc sr entries for one plane configs */
4344         if (HAS_FW_BLC(dev) && enabled) {
4345                 /* self-refresh has much higher latency */
4346                 static const int sr_latency_ns = 6000;
4347                 int clock = enabled->mode.clock;
4348                 int htotal = enabled->mode.htotal;
4349                 int hdisplay = enabled->mode.hdisplay;
4350                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4351                 unsigned long line_time_us;
4352                 int entries;
4353
4354                 line_time_us = (htotal * 1000) / clock;
4355
4356                 /* Use ns/us then divide to preserve precision */
4357                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4358                         pixel_size * hdisplay;
4359                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4360                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4361                 srwm = wm_info->fifo_size - entries;
4362                 if (srwm < 0)
4363                         srwm = 1;
4364
4365                 if (IS_I945G(dev) || IS_I945GM(dev))
4366                         I915_WRITE(FW_BLC_SELF,
4367                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4368                 else if (IS_I915GM(dev))
4369                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4370         }
4371
4372         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4373                       planea_wm, planeb_wm, cwm, srwm);
4374
4375         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4376         fwater_hi = (cwm & 0x1f);
4377
4378         /* Set request length to 8 cachelines per fetch */
4379         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4380         fwater_hi = fwater_hi | (1 << 8);
4381
4382         I915_WRITE(FW_BLC, fwater_lo);
4383         I915_WRITE(FW_BLC2, fwater_hi);
4384
4385         if (HAS_FW_BLC(dev)) {
4386                 if (enabled) {
4387                         if (IS_I945G(dev) || IS_I945GM(dev))
4388                                 I915_WRITE(FW_BLC_SELF,
4389                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4390                         else if (IS_I915GM(dev))
4391                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4392                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4393                 } else
4394                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4395         }
4396 }
4397
4398 static void i830_update_wm(struct drm_device *dev)
4399 {
4400         struct drm_i915_private *dev_priv = dev->dev_private;
4401         struct drm_crtc *crtc;
4402         uint32_t fwater_lo;
4403         int planea_wm;
4404
4405         crtc = single_enabled_crtc(dev);
4406         if (crtc == NULL)
4407                 return;
4408
4409         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4410                                        dev_priv->display.get_fifo_size(dev, 0),
4411                                        crtc->fb->bits_per_pixel / 8,
4412                                        latency_ns);
4413         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4414         fwater_lo |= (3<<8) | planea_wm;
4415
4416         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4417
4418         I915_WRITE(FW_BLC, fwater_lo);
4419 }
4420
4421 #define ILK_LP0_PLANE_LATENCY           700
4422 #define ILK_LP0_CURSOR_LATENCY          1300
4423
4424 /*
4425  * Check the wm result.
4426  *
4427  * If any calculated watermark values is larger than the maximum value that
4428  * can be programmed into the associated watermark register, that watermark
4429  * must be disabled.
4430  */
4431 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4432                                 int fbc_wm, int display_wm, int cursor_wm,
4433                                 const struct intel_watermark_params *display,
4434                                 const struct intel_watermark_params *cursor)
4435 {
4436         struct drm_i915_private *dev_priv = dev->dev_private;
4437
4438         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4439                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4440
4441         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4442                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4443                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4444
4445                 /* fbc has it's own way to disable FBC WM */
4446                 I915_WRITE(DISP_ARB_CTL,
4447                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4448                 return false;
4449         }
4450
4451         if (display_wm > display->max_wm) {
4452                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4453                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4454                 return false;
4455         }
4456
4457         if (cursor_wm > cursor->max_wm) {
4458                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4459                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4460                 return false;
4461         }
4462
4463         if (!(fbc_wm || display_wm || cursor_wm)) {
4464                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4465                 return false;
4466         }
4467
4468         return true;
4469 }
4470
4471 /*
4472  * Compute watermark values of WM[1-3],
4473  */
4474 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4475                                   int latency_ns,
4476                                   const struct intel_watermark_params *display,
4477                                   const struct intel_watermark_params *cursor,
4478                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4479 {
4480         struct drm_crtc *crtc;
4481         unsigned long line_time_us;
4482         int hdisplay, htotal, pixel_size, clock;
4483         int line_count, line_size;
4484         int small, large;
4485         int entries;
4486
4487         if (!latency_ns) {
4488                 *fbc_wm = *display_wm = *cursor_wm = 0;
4489                 return false;
4490         }
4491
4492         crtc = intel_get_crtc_for_plane(dev, plane);
4493         hdisplay = crtc->mode.hdisplay;
4494         htotal = crtc->mode.htotal;
4495         clock = crtc->mode.clock;
4496         pixel_size = crtc->fb->bits_per_pixel / 8;
4497
4498         line_time_us = (htotal * 1000) / clock;
4499         line_count = (latency_ns / line_time_us + 1000) / 1000;
4500         line_size = hdisplay * pixel_size;
4501
4502         /* Use the minimum of the small and large buffer method for primary */
4503         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4504         large = line_count * line_size;
4505
4506         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4507         *display_wm = entries + display->guard_size;
4508
4509         /*
4510          * Spec says:
4511          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4512          */
4513         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4514
4515         /* calculate the self-refresh watermark for display cursor */
4516         entries = line_count * pixel_size * 64;
4517         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4518         *cursor_wm = entries + cursor->guard_size;
4519
4520         return ironlake_check_srwm(dev, level,
4521                                    *fbc_wm, *display_wm, *cursor_wm,
4522                                    display, cursor);
4523 }
4524
4525 static void ironlake_update_wm(struct drm_device *dev)
4526 {
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528         int fbc_wm, plane_wm, cursor_wm;
4529         unsigned int enabled;
4530
4531         enabled = 0;
4532         if (g4x_compute_wm0(dev, 0,
4533                             &ironlake_display_wm_info,
4534                             ILK_LP0_PLANE_LATENCY,
4535                             &ironlake_cursor_wm_info,
4536                             ILK_LP0_CURSOR_LATENCY,
4537                             &plane_wm, &cursor_wm)) {
4538                 I915_WRITE(WM0_PIPEA_ILK,
4539                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4540                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4541                               " plane %d, " "cursor: %d\n",
4542                               plane_wm, cursor_wm);
4543                 enabled |= 1;
4544         }
4545
4546         if (g4x_compute_wm0(dev, 1,
4547                             &ironlake_display_wm_info,
4548                             ILK_LP0_PLANE_LATENCY,
4549                             &ironlake_cursor_wm_info,
4550                             ILK_LP0_CURSOR_LATENCY,
4551                             &plane_wm, &cursor_wm)) {
4552                 I915_WRITE(WM0_PIPEB_ILK,
4553                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4554                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4555                               " plane %d, cursor: %d\n",
4556                               plane_wm, cursor_wm);
4557                 enabled |= 2;
4558         }
4559
4560         /*
4561          * Calculate and update the self-refresh watermark only when one
4562          * display plane is used.
4563          */
4564         I915_WRITE(WM3_LP_ILK, 0);
4565         I915_WRITE(WM2_LP_ILK, 0);
4566         I915_WRITE(WM1_LP_ILK, 0);
4567
4568         if (!single_plane_enabled(enabled))
4569                 return;
4570         enabled = ffs(enabled) - 1;
4571
4572         /* WM1 */
4573         if (!ironlake_compute_srwm(dev, 1, enabled,
4574                                    ILK_READ_WM1_LATENCY() * 500,
4575                                    &ironlake_display_srwm_info,
4576                                    &ironlake_cursor_srwm_info,
4577                                    &fbc_wm, &plane_wm, &cursor_wm))
4578                 return;
4579
4580         I915_WRITE(WM1_LP_ILK,
4581                    WM1_LP_SR_EN |
4582                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4583                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4584                    (plane_wm << WM1_LP_SR_SHIFT) |
4585                    cursor_wm);
4586
4587         /* WM2 */
4588         if (!ironlake_compute_srwm(dev, 2, enabled,
4589                                    ILK_READ_WM2_LATENCY() * 500,
4590                                    &ironlake_display_srwm_info,
4591                                    &ironlake_cursor_srwm_info,
4592                                    &fbc_wm, &plane_wm, &cursor_wm))
4593                 return;
4594
4595         I915_WRITE(WM2_LP_ILK,
4596                    WM2_LP_EN |
4597                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4598                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4599                    (plane_wm << WM1_LP_SR_SHIFT) |
4600                    cursor_wm);
4601
4602         /*
4603          * WM3 is unsupported on ILK, probably because we don't have latency
4604          * data for that power state
4605          */
4606 }
4607
4608 void sandybridge_update_wm(struct drm_device *dev)
4609 {
4610         struct drm_i915_private *dev_priv = dev->dev_private;
4611         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4612         u32 val;
4613         int fbc_wm, plane_wm, cursor_wm;
4614         unsigned int enabled;
4615
4616         enabled = 0;
4617         if (g4x_compute_wm0(dev, 0,
4618                             &sandybridge_display_wm_info, latency,
4619                             &sandybridge_cursor_wm_info, latency,
4620                             &plane_wm, &cursor_wm)) {
4621                 val = I915_READ(WM0_PIPEA_ILK);
4622                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4623                 I915_WRITE(WM0_PIPEA_ILK, val |
4624                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4625                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4626                               " plane %d, " "cursor: %d\n",
4627                               plane_wm, cursor_wm);
4628                 enabled |= 1;
4629         }
4630
4631         if (g4x_compute_wm0(dev, 1,
4632                             &sandybridge_display_wm_info, latency,
4633                             &sandybridge_cursor_wm_info, latency,
4634                             &plane_wm, &cursor_wm)) {
4635                 val = I915_READ(WM0_PIPEB_ILK);
4636                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4637                 I915_WRITE(WM0_PIPEB_ILK, val |
4638                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4639                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4640                               " plane %d, cursor: %d\n",
4641                               plane_wm, cursor_wm);
4642                 enabled |= 2;
4643         }
4644
4645         /* IVB has 3 pipes */
4646         if (IS_IVYBRIDGE(dev) &&
4647             g4x_compute_wm0(dev, 2,
4648                             &sandybridge_display_wm_info, latency,
4649                             &sandybridge_cursor_wm_info, latency,
4650                             &plane_wm, &cursor_wm)) {
4651                 val = I915_READ(WM0_PIPEC_IVB);
4652                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4653                 I915_WRITE(WM0_PIPEC_IVB, val |
4654                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4655                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4656                               " plane %d, cursor: %d\n",
4657                               plane_wm, cursor_wm);
4658                 enabled |= 3;
4659         }
4660
4661         /*
4662          * Calculate and update the self-refresh watermark only when one
4663          * display plane is used.
4664          *
4665          * SNB support 3 levels of watermark.
4666          *
4667          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4668          * and disabled in the descending order
4669          *
4670          */
4671         I915_WRITE(WM3_LP_ILK, 0);
4672         I915_WRITE(WM2_LP_ILK, 0);
4673         I915_WRITE(WM1_LP_ILK, 0);
4674
4675         if (!single_plane_enabled(enabled) ||
4676             dev_priv->sprite_scaling_enabled)
4677                 return;
4678         enabled = ffs(enabled) - 1;
4679
4680         /* WM1 */
4681         if (!ironlake_compute_srwm(dev, 1, enabled,
4682                                    SNB_READ_WM1_LATENCY() * 500,
4683                                    &sandybridge_display_srwm_info,
4684                                    &sandybridge_cursor_srwm_info,
4685                                    &fbc_wm, &plane_wm, &cursor_wm))
4686                 return;
4687
4688         I915_WRITE(WM1_LP_ILK,
4689                    WM1_LP_SR_EN |
4690                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4691                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4692                    (plane_wm << WM1_LP_SR_SHIFT) |
4693                    cursor_wm);
4694
4695         /* WM2 */
4696         if (!ironlake_compute_srwm(dev, 2, enabled,
4697                                    SNB_READ_WM2_LATENCY() * 500,
4698                                    &sandybridge_display_srwm_info,
4699                                    &sandybridge_cursor_srwm_info,
4700                                    &fbc_wm, &plane_wm, &cursor_wm))
4701                 return;
4702
4703         I915_WRITE(WM2_LP_ILK,
4704                    WM2_LP_EN |
4705                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4706                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4707                    (plane_wm << WM1_LP_SR_SHIFT) |
4708                    cursor_wm);
4709
4710         /* WM3 */
4711         if (!ironlake_compute_srwm(dev, 3, enabled,
4712                                    SNB_READ_WM3_LATENCY() * 500,
4713                                    &sandybridge_display_srwm_info,
4714                                    &sandybridge_cursor_srwm_info,
4715                                    &fbc_wm, &plane_wm, &cursor_wm))
4716                 return;
4717
4718         I915_WRITE(WM3_LP_ILK,
4719                    WM3_LP_EN |
4720                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4721                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4722                    (plane_wm << WM1_LP_SR_SHIFT) |
4723                    cursor_wm);
4724 }
4725
4726 static bool
4727 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4728                               uint32_t sprite_width, int pixel_size,
4729                               const struct intel_watermark_params *display,
4730                               int display_latency_ns, int *sprite_wm)
4731 {
4732         struct drm_crtc *crtc;
4733         int clock;
4734         int entries, tlb_miss;
4735
4736         crtc = intel_get_crtc_for_plane(dev, plane);
4737         if (crtc->fb == NULL || !crtc->enabled) {
4738                 *sprite_wm = display->guard_size;
4739                 return false;
4740         }
4741
4742         clock = crtc->mode.clock;
4743
4744         /* Use the small buffer method to calculate the sprite watermark */
4745         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4746         tlb_miss = display->fifo_size*display->cacheline_size -
4747                 sprite_width * 8;
4748         if (tlb_miss > 0)
4749                 entries += tlb_miss;
4750         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4751         *sprite_wm = entries + display->guard_size;
4752         if (*sprite_wm > (int)display->max_wm)
4753                 *sprite_wm = display->max_wm;
4754
4755         return true;
4756 }
4757
4758 static bool
4759 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4760                                 uint32_t sprite_width, int pixel_size,
4761                                 const struct intel_watermark_params *display,
4762                                 int latency_ns, int *sprite_wm)
4763 {
4764         struct drm_crtc *crtc;
4765         unsigned long line_time_us;
4766         int clock;
4767         int line_count, line_size;
4768         int small, large;
4769         int entries;
4770
4771         if (!latency_ns) {
4772                 *sprite_wm = 0;
4773                 return false;
4774         }
4775
4776         crtc = intel_get_crtc_for_plane(dev, plane);
4777         clock = crtc->mode.clock;
4778         if (!clock) {
4779                 *sprite_wm = 0;
4780                 return false;
4781         }
4782
4783         line_time_us = (sprite_width * 1000) / clock;
4784         if (!line_time_us) {
4785                 *sprite_wm = 0;
4786                 return false;
4787         }
4788
4789         line_count = (latency_ns / line_time_us + 1000) / 1000;
4790         line_size = sprite_width * pixel_size;
4791
4792         /* Use the minimum of the small and large buffer method for primary */
4793         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4794         large = line_count * line_size;
4795
4796         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4797         *sprite_wm = entries + display->guard_size;
4798
4799         return *sprite_wm > 0x3ff ? false : true;
4800 }
4801
4802 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4803                                          uint32_t sprite_width, int pixel_size)
4804 {
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4807         u32 val;
4808         int sprite_wm, reg;
4809         int ret;
4810
4811         switch (pipe) {
4812         case 0:
4813                 reg = WM0_PIPEA_ILK;
4814                 break;
4815         case 1:
4816                 reg = WM0_PIPEB_ILK;
4817                 break;
4818         case 2:
4819                 reg = WM0_PIPEC_IVB;
4820                 break;
4821         default:
4822                 return; /* bad pipe */
4823         }
4824
4825         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4826                                             &sandybridge_display_wm_info,
4827                                             latency, &sprite_wm);
4828         if (!ret) {
4829                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4830                               pipe);
4831                 return;
4832         }
4833
4834         val = I915_READ(reg);
4835         val &= ~WM0_PIPE_SPRITE_MASK;
4836         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4837         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4838
4839
4840         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4841                                               pixel_size,
4842                                               &sandybridge_display_srwm_info,
4843                                               SNB_READ_WM1_LATENCY() * 500,
4844                                               &sprite_wm);
4845         if (!ret) {
4846                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4847                               pipe);
4848                 return;
4849         }
4850         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4851
4852         /* Only IVB has two more LP watermarks for sprite */
4853         if (!IS_IVYBRIDGE(dev))
4854                 return;
4855
4856         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4857                                               pixel_size,
4858                                               &sandybridge_display_srwm_info,
4859                                               SNB_READ_WM2_LATENCY() * 500,
4860                                               &sprite_wm);
4861         if (!ret) {
4862                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4863                               pipe);
4864                 return;
4865         }
4866         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4867
4868         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4869                                               pixel_size,
4870                                               &sandybridge_display_srwm_info,
4871                                               SNB_READ_WM3_LATENCY() * 500,
4872                                               &sprite_wm);
4873         if (!ret) {
4874                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4875                               pipe);
4876                 return;
4877         }
4878         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4879 }
4880
4881 /**
4882  * intel_update_watermarks - update FIFO watermark values based on current modes
4883  *
4884  * Calculate watermark values for the various WM regs based on current mode
4885  * and plane configuration.
4886  *
4887  * There are several cases to deal with here:
4888  *   - normal (i.e. non-self-refresh)
4889  *   - self-refresh (SR) mode
4890  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4891  *   - lines are small relative to FIFO size (buffer can hold more than 2
4892  *     lines), so need to account for TLB latency
4893  *
4894  *   The normal calculation is:
4895  *     watermark = dotclock * bytes per pixel * latency
4896  *   where latency is platform & configuration dependent (we assume pessimal
4897  *   values here).
4898  *
4899  *   The SR calculation is:
4900  *     watermark = (trunc(latency/line time)+1) * surface width *
4901  *       bytes per pixel
4902  *   where
4903  *     line time = htotal / dotclock
4904  *     surface width = hdisplay for normal plane and 64 for cursor
4905  *   and latency is assumed to be high, as above.
4906  *
4907  * The final value programmed to the register should always be rounded up,
4908  * and include an extra 2 entries to account for clock crossings.
4909  *
4910  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4911  * to set the non-SR watermarks to 8.
4912  */
4913 static void intel_update_watermarks(struct drm_device *dev)
4914 {
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916
4917         if (dev_priv->display.update_wm)
4918                 dev_priv->display.update_wm(dev);
4919 }
4920
4921 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4922                                     uint32_t sprite_width, int pixel_size)
4923 {
4924         struct drm_i915_private *dev_priv = dev->dev_private;
4925
4926         if (dev_priv->display.update_sprite_wm)
4927                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4928                                                    pixel_size);
4929 }
4930
4931 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4932 {
4933         if (i915_panel_use_ssc >= 0)
4934                 return i915_panel_use_ssc != 0;
4935         return dev_priv->lvds_use_ssc
4936                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4937 }
4938
4939 /**
4940  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4941  * @crtc: CRTC structure
4942  * @mode: requested mode
4943  *
4944  * A pipe may be connected to one or more outputs.  Based on the depth of the
4945  * attached framebuffer, choose a good color depth to use on the pipe.
4946  *
4947  * If possible, match the pipe depth to the fb depth.  In some cases, this
4948  * isn't ideal, because the connected output supports a lesser or restricted
4949  * set of depths.  Resolve that here:
4950  *    LVDS typically supports only 6bpc, so clamp down in that case
4951  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4952  *    Displays may support a restricted set as well, check EDID and clamp as
4953  *      appropriate.
4954  *    DP may want to dither down to 6bpc to fit larger modes
4955  *
4956  * RETURNS:
4957  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4958  * true if they don't match).
4959  */
4960 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4961                                          unsigned int *pipe_bpp,
4962                                          struct drm_display_mode *mode)
4963 {
4964         struct drm_device *dev = crtc->dev;
4965         struct drm_i915_private *dev_priv = dev->dev_private;
4966         struct drm_encoder *encoder;
4967         struct drm_connector *connector;
4968         unsigned int display_bpc = UINT_MAX, bpc;
4969
4970         /* Walk the encoders & connectors on this crtc, get min bpc */
4971         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4972                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4973
4974                 if (encoder->crtc != crtc)
4975                         continue;
4976
4977                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4978                         unsigned int lvds_bpc;
4979
4980                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4981                             LVDS_A3_POWER_UP)
4982                                 lvds_bpc = 8;
4983                         else
4984                                 lvds_bpc = 6;
4985
4986                         if (lvds_bpc < display_bpc) {
4987                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4988                                 display_bpc = lvds_bpc;
4989                         }
4990                         continue;
4991                 }
4992
4993                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4994                         /* Use VBT settings if we have an eDP panel */
4995                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4996
4997                         if (edp_bpc < display_bpc) {
4998                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4999                                 display_bpc = edp_bpc;
5000                         }
5001                         continue;
5002                 }
5003
5004                 /* Not one of the known troublemakers, check the EDID */
5005                 list_for_each_entry(connector, &dev->mode_config.connector_list,
5006                                     head) {
5007                         if (connector->encoder != encoder)
5008                                 continue;
5009
5010                         /* Don't use an invalid EDID bpc value */
5011                         if (connector->display_info.bpc &&
5012                             connector->display_info.bpc < display_bpc) {
5013                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5014                                 display_bpc = connector->display_info.bpc;
5015                         }
5016                 }
5017
5018                 /*
5019                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5020                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5021                  */
5022                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5023                         if (display_bpc > 8 && display_bpc < 12) {
5024                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5025                                 display_bpc = 12;
5026                         } else {
5027                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5028                                 display_bpc = 8;
5029                         }
5030                 }
5031         }
5032
5033         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5034                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5035                 display_bpc = 6;
5036         }
5037
5038         /*
5039          * We could just drive the pipe at the highest bpc all the time and
5040          * enable dithering as needed, but that costs bandwidth.  So choose
5041          * the minimum value that expresses the full color range of the fb but
5042          * also stays within the max display bpc discovered above.
5043          */
5044
5045         switch (crtc->fb->depth) {
5046         case 8:
5047                 bpc = 8; /* since we go through a colormap */
5048                 break;
5049         case 15:
5050         case 16:
5051                 bpc = 6; /* min is 18bpp */
5052                 break;
5053         case 24:
5054                 bpc = 8;
5055                 break;
5056         case 30:
5057                 bpc = 10;
5058                 break;
5059         case 48:
5060                 bpc = 12;
5061                 break;
5062         default:
5063                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5064                 bpc = min((unsigned int)8, display_bpc);
5065                 break;
5066         }
5067
5068         display_bpc = min(display_bpc, bpc);
5069
5070         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5071                       bpc, display_bpc);
5072
5073         *pipe_bpp = display_bpc * 3;
5074
5075         return display_bpc != bpc;
5076 }
5077
5078 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5079 {
5080         struct drm_device *dev = crtc->dev;
5081         struct drm_i915_private *dev_priv = dev->dev_private;
5082         int refclk;
5083
5084         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5085             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5086                 refclk = dev_priv->lvds_ssc_freq * 1000;
5087                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5088                               refclk / 1000);
5089         } else if (!IS_GEN2(dev)) {
5090                 refclk = 96000;
5091         } else {
5092                 refclk = 48000;
5093         }
5094
5095         return refclk;
5096 }
5097
5098 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5099                                       intel_clock_t *clock)
5100 {
5101         /* SDVO TV has fixed PLL values depend on its clock range,
5102            this mirrors vbios setting. */
5103         if (adjusted_mode->clock >= 100000
5104             && adjusted_mode->clock < 140500) {
5105                 clock->p1 = 2;
5106                 clock->p2 = 10;
5107                 clock->n = 3;
5108                 clock->m1 = 16;
5109                 clock->m2 = 8;
5110         } else if (adjusted_mode->clock >= 140500
5111                    && adjusted_mode->clock <= 200000) {
5112                 clock->p1 = 1;
5113                 clock->p2 = 10;
5114                 clock->n = 6;
5115                 clock->m1 = 12;
5116                 clock->m2 = 8;
5117         }
5118 }
5119
5120 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5121                                      intel_clock_t *clock,
5122                                      intel_clock_t *reduced_clock)
5123 {
5124         struct drm_device *dev = crtc->dev;
5125         struct drm_i915_private *dev_priv = dev->dev_private;
5126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5127         int pipe = intel_crtc->pipe;
5128         u32 fp, fp2 = 0;
5129
5130         if (IS_PINEVIEW(dev)) {
5131                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5132                 if (reduced_clock)
5133                         fp2 = (1 << reduced_clock->n) << 16 |
5134                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5135         } else {
5136                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5137                 if (reduced_clock)
5138                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5139                                 reduced_clock->m2;
5140         }
5141
5142         I915_WRITE(FP0(pipe), fp);
5143
5144         intel_crtc->lowfreq_avail = false;
5145         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5146             reduced_clock && i915_powersave) {
5147                 I915_WRITE(FP1(pipe), fp2);
5148                 intel_crtc->lowfreq_avail = true;
5149         } else {
5150                 I915_WRITE(FP1(pipe), fp);
5151         }
5152 }
5153
5154 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5155                               struct drm_display_mode *mode,
5156                               struct drm_display_mode *adjusted_mode,
5157                               int x, int y,
5158                               struct drm_framebuffer *old_fb)
5159 {
5160         struct drm_device *dev = crtc->dev;
5161         struct drm_i915_private *dev_priv = dev->dev_private;
5162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163         int pipe = intel_crtc->pipe;
5164         int plane = intel_crtc->plane;
5165         int refclk, num_connectors = 0;
5166         intel_clock_t clock, reduced_clock;
5167         u32 dpll, dspcntr, pipeconf, vsyncshift;
5168         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5169         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5170         struct drm_mode_config *mode_config = &dev->mode_config;
5171         struct intel_encoder *encoder;
5172         const intel_limit_t *limit;
5173         int ret;
5174         u32 temp;
5175         u32 lvds_sync = 0;
5176
5177         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5178                 if (encoder->base.crtc != crtc)
5179                         continue;
5180
5181                 switch (encoder->type) {
5182                 case INTEL_OUTPUT_LVDS:
5183                         is_lvds = true;
5184                         break;
5185                 case INTEL_OUTPUT_SDVO:
5186                 case INTEL_OUTPUT_HDMI:
5187                         is_sdvo = true;
5188                         if (encoder->needs_tv_clock)
5189                                 is_tv = true;
5190                         break;
5191                 case INTEL_OUTPUT_DVO:
5192                         is_dvo = true;
5193                         break;
5194                 case INTEL_OUTPUT_TVOUT:
5195                         is_tv = true;
5196                         break;
5197                 case INTEL_OUTPUT_ANALOG:
5198                         is_crt = true;
5199                         break;
5200                 case INTEL_OUTPUT_DISPLAYPORT:
5201                         is_dp = true;
5202                         break;
5203                 }
5204
5205                 num_connectors++;
5206         }
5207
5208         refclk = i9xx_get_refclk(crtc, num_connectors);
5209
5210         /*
5211          * Returns a set of divisors for the desired target clock with the given
5212          * refclk, or FALSE.  The returned values represent the clock equation:
5213          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5214          */
5215         limit = intel_limit(crtc, refclk);
5216         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5217                              &clock);
5218         if (!ok) {
5219                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5220                 return -EINVAL;
5221         }
5222
5223         /* Ensure that the cursor is valid for the new mode before changing... */
5224         intel_crtc_update_cursor(crtc, true);
5225
5226         if (is_lvds && dev_priv->lvds_downclock_avail) {
5227                 /*
5228                  * Ensure we match the reduced clock's P to the target clock.
5229                  * If the clocks don't match, we can't switch the display clock
5230                  * by using the FP0/FP1. In such case we will disable the LVDS
5231                  * downclock feature.
5232                 */
5233                 has_reduced_clock = limit->find_pll(limit, crtc,
5234                                                     dev_priv->lvds_downclock,
5235                                                     refclk,
5236                                                     &clock,
5237                                                     &reduced_clock);
5238         }
5239
5240         if (is_sdvo && is_tv)
5241                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5242
5243         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5244                                  &reduced_clock : NULL);
5245
5246         dpll = DPLL_VGA_MODE_DIS;
5247
5248         if (!IS_GEN2(dev)) {
5249                 if (is_lvds)
5250                         dpll |= DPLLB_MODE_LVDS;
5251                 else
5252                         dpll |= DPLLB_MODE_DAC_SERIAL;
5253                 if (is_sdvo) {
5254                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5255                         if (pixel_multiplier > 1) {
5256                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5257                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5258                         }
5259                         dpll |= DPLL_DVO_HIGH_SPEED;
5260                 }
5261                 if (is_dp)
5262                         dpll |= DPLL_DVO_HIGH_SPEED;
5263
5264                 /* compute bitmask from p1 value */
5265                 if (IS_PINEVIEW(dev))
5266                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5267                 else {
5268                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5269                         if (IS_G4X(dev) && has_reduced_clock)
5270                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5271                 }
5272                 switch (clock.p2) {
5273                 case 5:
5274                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5275                         break;
5276                 case 7:
5277                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5278                         break;
5279                 case 10:
5280                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5281                         break;
5282                 case 14:
5283                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5284                         break;
5285                 }
5286                 if (INTEL_INFO(dev)->gen >= 4)
5287                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5288         } else {
5289                 if (is_lvds) {
5290                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5291                 } else {
5292                         if (clock.p1 == 2)
5293                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5294                         else
5295                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5296                         if (clock.p2 == 4)
5297                                 dpll |= PLL_P2_DIVIDE_BY_4;
5298                 }
5299         }
5300
5301         if (is_sdvo && is_tv)
5302                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5303         else if (is_tv)
5304                 /* XXX: just matching BIOS for now */
5305                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5306                 dpll |= 3;
5307         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5308                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5309         else
5310                 dpll |= PLL_REF_INPUT_DREFCLK;
5311
5312         /* setup pipeconf */
5313         pipeconf = I915_READ(PIPECONF(pipe));
5314
5315         /* Set up the display plane register */
5316         dspcntr = DISPPLANE_GAMMA_ENABLE;
5317
5318         if (pipe == 0)
5319                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5320         else
5321                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5322
5323         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5324                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5325                  * core speed.
5326                  *
5327                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5328                  * pipe == 0 check?
5329                  */
5330                 if (mode->clock >
5331                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5332                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5333                 else
5334                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5335         }
5336
5337         /* default to 8bpc */
5338         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5339         if (is_dp) {
5340                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5341                         pipeconf |= PIPECONF_BPP_6 |
5342                                     PIPECONF_DITHER_EN |
5343                                     PIPECONF_DITHER_TYPE_SP;
5344                 }
5345         }
5346
5347         dpll |= DPLL_VCO_ENABLE;
5348
5349         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5350         drm_mode_debug_printmodeline(mode);
5351
5352         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5353
5354         POSTING_READ(DPLL(pipe));
5355         udelay(150);
5356
5357         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5358          * This is an exception to the general rule that mode_set doesn't turn
5359          * things on.
5360          */
5361         if (is_lvds) {
5362                 temp = I915_READ(LVDS);
5363                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5364                 if (pipe == 1) {
5365                         temp |= LVDS_PIPEB_SELECT;
5366                 } else {
5367                         temp &= ~LVDS_PIPEB_SELECT;
5368                 }
5369                 /* set the corresponsding LVDS_BORDER bit */
5370                 temp |= dev_priv->lvds_border_bits;
5371                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5372                  * set the DPLLs for dual-channel mode or not.
5373                  */
5374                 if (clock.p2 == 7)
5375                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5376                 else
5377                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5378
5379                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5380                  * appropriately here, but we need to look more thoroughly into how
5381                  * panels behave in the two modes.
5382                  */
5383                 /* set the dithering flag on LVDS as needed */
5384                 if (INTEL_INFO(dev)->gen >= 4) {
5385                         if (dev_priv->lvds_dither)
5386                                 temp |= LVDS_ENABLE_DITHER;
5387                         else
5388                                 temp &= ~LVDS_ENABLE_DITHER;
5389                 }
5390                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5391                         lvds_sync |= LVDS_HSYNC_POLARITY;
5392                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5393                         lvds_sync |= LVDS_VSYNC_POLARITY;
5394                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5395                     != lvds_sync) {
5396                         char flags[2] = "-+";
5397                         DRM_INFO("Changing LVDS panel from "
5398                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5399                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5400                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5401                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5402                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5403                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5404                         temp |= lvds_sync;
5405                 }
5406                 I915_WRITE(LVDS, temp);
5407         }
5408
5409         if (is_dp) {
5410                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5411         }
5412
5413         I915_WRITE(DPLL(pipe), dpll);
5414
5415         /* Wait for the clocks to stabilize. */
5416         POSTING_READ(DPLL(pipe));
5417         udelay(150);
5418
5419         if (INTEL_INFO(dev)->gen >= 4) {
5420                 temp = 0;
5421                 if (is_sdvo) {
5422                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5423                         if (temp > 1)
5424                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5425                         else
5426                                 temp = 0;
5427                 }
5428                 I915_WRITE(DPLL_MD(pipe), temp);
5429         } else {
5430                 /* The pixel multiplier can only be updated once the
5431                  * DPLL is enabled and the clocks are stable.
5432                  *
5433                  * So write it again.
5434                  */
5435                 I915_WRITE(DPLL(pipe), dpll);
5436         }
5437
5438         if (HAS_PIPE_CXSR(dev)) {
5439                 if (intel_crtc->lowfreq_avail) {
5440                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5441                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5442                 } else {
5443                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5444                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5445                 }
5446         }
5447
5448         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5449         if (!IS_GEN2(dev) &&
5450             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5451                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5452                 /* the chip adds 2 halflines automatically */
5453                 adjusted_mode->crtc_vtotal -= 1;
5454                 adjusted_mode->crtc_vblank_end -= 1;
5455                 vsyncshift = adjusted_mode->crtc_hsync_start
5456                              - adjusted_mode->crtc_htotal/2;
5457         } else {
5458                 pipeconf |= PIPECONF_PROGRESSIVE;
5459                 vsyncshift = 0;
5460         }
5461
5462         if (!IS_GEN3(dev))
5463                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5464
5465         I915_WRITE(HTOTAL(pipe),
5466                    (adjusted_mode->crtc_hdisplay - 1) |
5467                    ((adjusted_mode->crtc_htotal - 1) << 16));
5468         I915_WRITE(HBLANK(pipe),
5469                    (adjusted_mode->crtc_hblank_start - 1) |
5470                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5471         I915_WRITE(HSYNC(pipe),
5472                    (adjusted_mode->crtc_hsync_start - 1) |
5473                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5474
5475         I915_WRITE(VTOTAL(pipe),
5476                    (adjusted_mode->crtc_vdisplay - 1) |
5477                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5478         I915_WRITE(VBLANK(pipe),
5479                    (adjusted_mode->crtc_vblank_start - 1) |
5480                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5481         I915_WRITE(VSYNC(pipe),
5482                    (adjusted_mode->crtc_vsync_start - 1) |
5483                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5484
5485         /* pipesrc and dspsize control the size that is scaled from,
5486          * which should always be the user's requested size.
5487          */
5488         I915_WRITE(DSPSIZE(plane),
5489                    ((mode->vdisplay - 1) << 16) |
5490                    (mode->hdisplay - 1));
5491         I915_WRITE(DSPPOS(plane), 0);
5492         I915_WRITE(PIPESRC(pipe),
5493                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5494
5495         I915_WRITE(PIPECONF(pipe), pipeconf);
5496         POSTING_READ(PIPECONF(pipe));
5497         intel_enable_pipe(dev_priv, pipe, false);
5498
5499         intel_wait_for_vblank(dev, pipe);
5500
5501         I915_WRITE(DSPCNTR(plane), dspcntr);
5502         POSTING_READ(DSPCNTR(plane));
5503         intel_enable_plane(dev_priv, plane, pipe);
5504
5505         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5506
5507         intel_update_watermarks(dev);
5508
5509         return ret;
5510 }
5511
5512 /*
5513  * Initialize reference clocks when the driver loads
5514  */
5515 void ironlake_init_pch_refclk(struct drm_device *dev)
5516 {
5517         struct drm_i915_private *dev_priv = dev->dev_private;
5518         struct drm_mode_config *mode_config = &dev->mode_config;
5519         struct intel_encoder *encoder;
5520         u32 temp;
5521         bool has_lvds = false;
5522         bool has_cpu_edp = false;
5523         bool has_pch_edp = false;
5524         bool has_panel = false;
5525         bool has_ck505 = false;
5526         bool can_ssc = false;
5527
5528         /* We need to take the global config into account */
5529         list_for_each_entry(encoder, &mode_config->encoder_list,
5530                             base.head) {
5531                 switch (encoder->type) {
5532                 case INTEL_OUTPUT_LVDS:
5533                         has_panel = true;
5534                         has_lvds = true;
5535                         break;
5536                 case INTEL_OUTPUT_EDP:
5537                         has_panel = true;
5538                         if (intel_encoder_is_pch_edp(&encoder->base))
5539                                 has_pch_edp = true;
5540                         else
5541                                 has_cpu_edp = true;
5542                         break;
5543                 }
5544         }
5545
5546         if (HAS_PCH_IBX(dev)) {
5547                 has_ck505 = dev_priv->display_clock_mode;
5548                 can_ssc = has_ck505;
5549         } else {
5550                 has_ck505 = false;
5551                 can_ssc = true;
5552         }
5553
5554         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5555                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5556                       has_ck505);
5557
5558         /* Ironlake: try to setup display ref clock before DPLL
5559          * enabling. This is only under driver's control after
5560          * PCH B stepping, previous chipset stepping should be
5561          * ignoring this setting.
5562          */
5563         temp = I915_READ(PCH_DREF_CONTROL);
5564         /* Always enable nonspread source */
5565         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5566
5567         if (has_ck505)
5568                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5569         else
5570                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5571
5572         if (has_panel) {
5573                 temp &= ~DREF_SSC_SOURCE_MASK;
5574                 temp |= DREF_SSC_SOURCE_ENABLE;
5575
5576                 /* SSC must be turned on before enabling the CPU output  */
5577                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5578                         DRM_DEBUG_KMS("Using SSC on panel\n");
5579                         temp |= DREF_SSC1_ENABLE;
5580                 } else
5581                         temp &= ~DREF_SSC1_ENABLE;
5582
5583                 /* Get SSC going before enabling the outputs */
5584                 I915_WRITE(PCH_DREF_CONTROL, temp);
5585                 POSTING_READ(PCH_DREF_CONTROL);
5586                 udelay(200);
5587
5588                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5589
5590                 /* Enable CPU source on CPU attached eDP */
5591                 if (has_cpu_edp) {
5592                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5593                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5594                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5595                         }
5596                         else
5597                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5598                 } else
5599                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5600
5601                 I915_WRITE(PCH_DREF_CONTROL, temp);
5602                 POSTING_READ(PCH_DREF_CONTROL);
5603                 udelay(200);
5604         } else {
5605                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5606
5607                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5608
5609                 /* Turn off CPU output */
5610                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5611
5612                 I915_WRITE(PCH_DREF_CONTROL, temp);
5613                 POSTING_READ(PCH_DREF_CONTROL);
5614                 udelay(200);
5615
5616                 /* Turn off the SSC source */
5617                 temp &= ~DREF_SSC_SOURCE_MASK;
5618                 temp |= DREF_SSC_SOURCE_DISABLE;
5619
5620                 /* Turn off SSC1 */
5621                 temp &= ~ DREF_SSC1_ENABLE;
5622
5623                 I915_WRITE(PCH_DREF_CONTROL, temp);
5624                 POSTING_READ(PCH_DREF_CONTROL);
5625                 udelay(200);
5626         }
5627 }
5628
5629 static int ironlake_get_refclk(struct drm_crtc *crtc)
5630 {
5631         struct drm_device *dev = crtc->dev;
5632         struct drm_i915_private *dev_priv = dev->dev_private;
5633         struct intel_encoder *encoder;
5634         struct drm_mode_config *mode_config = &dev->mode_config;
5635         struct intel_encoder *edp_encoder = NULL;
5636         int num_connectors = 0;
5637         bool is_lvds = false;
5638
5639         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5640                 if (encoder->base.crtc != crtc)
5641                         continue;
5642
5643                 switch (encoder->type) {
5644                 case INTEL_OUTPUT_LVDS:
5645                         is_lvds = true;
5646                         break;
5647                 case INTEL_OUTPUT_EDP:
5648                         edp_encoder = encoder;
5649                         break;
5650                 }
5651                 num_connectors++;
5652         }
5653
5654         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5655                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5656                               dev_priv->lvds_ssc_freq);
5657                 return dev_priv->lvds_ssc_freq * 1000;
5658         }
5659
5660         return 120000;
5661 }
5662
5663 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5664                                   struct drm_display_mode *mode,
5665                                   struct drm_display_mode *adjusted_mode,
5666                                   int x, int y,
5667                                   struct drm_framebuffer *old_fb)
5668 {
5669         struct drm_device *dev = crtc->dev;
5670         struct drm_i915_private *dev_priv = dev->dev_private;
5671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5672         int pipe = intel_crtc->pipe;
5673         int plane = intel_crtc->plane;
5674         int refclk, num_connectors = 0;
5675         intel_clock_t clock, reduced_clock;
5676         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5677         bool ok, has_reduced_clock = false, is_sdvo = false;
5678         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5679         struct intel_encoder *has_edp_encoder = NULL;
5680         struct drm_mode_config *mode_config = &dev->mode_config;
5681         struct intel_encoder *encoder;
5682         const intel_limit_t *limit;
5683         int ret;
5684         struct fdi_m_n m_n = {0};
5685         u32 temp;
5686         u32 lvds_sync = 0;
5687         int target_clock, pixel_multiplier, lane, link_bw, factor;
5688         unsigned int pipe_bpp;
5689         bool dither;
5690
5691         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5692                 if (encoder->base.crtc != crtc)
5693                         continue;
5694
5695                 switch (encoder->type) {
5696                 case INTEL_OUTPUT_LVDS:
5697                         is_lvds = true;
5698                         break;
5699                 case INTEL_OUTPUT_SDVO:
5700                 case INTEL_OUTPUT_HDMI:
5701                         is_sdvo = true;
5702                         if (encoder->needs_tv_clock)
5703                                 is_tv = true;
5704                         break;
5705                 case INTEL_OUTPUT_TVOUT:
5706                         is_tv = true;
5707                         break;
5708                 case INTEL_OUTPUT_ANALOG:
5709                         is_crt = true;
5710                         break;
5711                 case INTEL_OUTPUT_DISPLAYPORT:
5712                         is_dp = true;
5713                         break;
5714                 case INTEL_OUTPUT_EDP:
5715                         has_edp_encoder = encoder;
5716                         break;
5717                 }
5718
5719                 num_connectors++;
5720         }
5721
5722         refclk = ironlake_get_refclk(crtc);
5723
5724         /*
5725          * Returns a set of divisors for the desired target clock with the given
5726          * refclk, or FALSE.  The returned values represent the clock equation:
5727          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5728          */
5729         limit = intel_limit(crtc, refclk);
5730         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5731                              &clock);
5732         if (!ok) {
5733                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5734                 return -EINVAL;
5735         }
5736
5737         /* Ensure that the cursor is valid for the new mode before changing... */
5738         intel_crtc_update_cursor(crtc, true);
5739
5740         if (is_lvds && dev_priv->lvds_downclock_avail) {
5741                 /*
5742                  * Ensure we match the reduced clock's P to the target clock.
5743                  * If the clocks don't match, we can't switch the display clock
5744                  * by using the FP0/FP1. In such case we will disable the LVDS
5745                  * downclock feature.
5746                 */
5747                 has_reduced_clock = limit->find_pll(limit, crtc,
5748                                                     dev_priv->lvds_downclock,
5749                                                     refclk,
5750                                                     &clock,
5751                                                     &reduced_clock);
5752         }
5753         /* SDVO TV has fixed PLL values depend on its clock range,
5754            this mirrors vbios setting. */
5755         if (is_sdvo && is_tv) {
5756                 if (adjusted_mode->clock >= 100000
5757                     && adjusted_mode->clock < 140500) {
5758                         clock.p1 = 2;
5759                         clock.p2 = 10;
5760                         clock.n = 3;
5761                         clock.m1 = 16;
5762                         clock.m2 = 8;
5763                 } else if (adjusted_mode->clock >= 140500
5764                            && adjusted_mode->clock <= 200000) {
5765                         clock.p1 = 1;
5766                         clock.p2 = 10;
5767                         clock.n = 6;
5768                         clock.m1 = 12;
5769                         clock.m2 = 8;
5770                 }
5771         }
5772
5773         /* FDI link */
5774         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5775         lane = 0;
5776         /* CPU eDP doesn't require FDI link, so just set DP M/N
5777            according to current link config */
5778         if (has_edp_encoder &&
5779             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5780                 target_clock = mode->clock;
5781                 intel_edp_link_config(has_edp_encoder,
5782                                       &lane, &link_bw);
5783         } else {
5784                 /* [e]DP over FDI requires target mode clock
5785                    instead of link clock */
5786                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5787                         target_clock = mode->clock;
5788                 else
5789                         target_clock = adjusted_mode->clock;
5790
5791                 /* FDI is a binary signal running at ~2.7GHz, encoding
5792                  * each output octet as 10 bits. The actual frequency
5793                  * is stored as a divider into a 100MHz clock, and the
5794                  * mode pixel clock is stored in units of 1KHz.
5795                  * Hence the bw of each lane in terms of the mode signal
5796                  * is:
5797                  */
5798                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5799         }
5800
5801         /* determine panel color depth */
5802         temp = I915_READ(PIPECONF(pipe));
5803         temp &= ~PIPE_BPC_MASK;
5804         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5805         switch (pipe_bpp) {
5806         case 18:
5807                 temp |= PIPE_6BPC;
5808                 break;
5809         case 24:
5810                 temp |= PIPE_8BPC;
5811                 break;
5812         case 30:
5813                 temp |= PIPE_10BPC;
5814                 break;
5815         case 36:
5816                 temp |= PIPE_12BPC;
5817                 break;
5818         default:
5819                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5820                         pipe_bpp);
5821                 temp |= PIPE_8BPC;
5822                 pipe_bpp = 24;
5823                 break;
5824         }
5825
5826         intel_crtc->bpp = pipe_bpp;
5827         I915_WRITE(PIPECONF(pipe), temp);
5828
5829         if (!lane) {
5830                 /*
5831                  * Account for spread spectrum to avoid
5832                  * oversubscribing the link. Max center spread
5833                  * is 2.5%; use 5% for safety's sake.
5834                  */
5835                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5836                 lane = bps / (link_bw * 8) + 1;
5837         }
5838
5839         intel_crtc->fdi_lanes = lane;
5840
5841         if (pixel_multiplier > 1)
5842                 link_bw *= pixel_multiplier;
5843         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5844                              &m_n);
5845
5846         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5847         if (has_reduced_clock)
5848                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5849                         reduced_clock.m2;
5850
5851         /* Enable autotuning of the PLL clock (if permissible) */
5852         factor = 21;
5853         if (is_lvds) {
5854                 if ((intel_panel_use_ssc(dev_priv) &&
5855                      dev_priv->lvds_ssc_freq == 100) ||
5856                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5857                         factor = 25;
5858         } else if (is_sdvo && is_tv)
5859                 factor = 20;
5860
5861         if (clock.m < factor * clock.n)
5862                 fp |= FP_CB_TUNE;
5863
5864         dpll = 0;
5865
5866         if (is_lvds)
5867                 dpll |= DPLLB_MODE_LVDS;
5868         else
5869                 dpll |= DPLLB_MODE_DAC_SERIAL;
5870         if (is_sdvo) {
5871                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5872                 if (pixel_multiplier > 1) {
5873                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5874                 }
5875                 dpll |= DPLL_DVO_HIGH_SPEED;
5876         }
5877         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5878                 dpll |= DPLL_DVO_HIGH_SPEED;
5879
5880         /* compute bitmask from p1 value */
5881         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5882         /* also FPA1 */
5883         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5884
5885         switch (clock.p2) {
5886         case 5:
5887                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5888                 break;
5889         case 7:
5890                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5891                 break;
5892         case 10:
5893                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5894                 break;
5895         case 14:
5896                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5897                 break;
5898         }
5899
5900         if (is_sdvo && is_tv)
5901                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5902         else if (is_tv)
5903                 /* XXX: just matching BIOS for now */
5904                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5905                 dpll |= 3;
5906         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5907                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5908         else
5909                 dpll |= PLL_REF_INPUT_DREFCLK;
5910
5911         /* setup pipeconf */
5912         pipeconf = I915_READ(PIPECONF(pipe));
5913
5914         /* Set up the display plane register */
5915         dspcntr = DISPPLANE_GAMMA_ENABLE;
5916
5917         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5918         drm_mode_debug_printmodeline(mode);
5919
5920         /* PCH eDP needs FDI, but CPU eDP does not */
5921         if (!intel_crtc->no_pll) {
5922                 if (!has_edp_encoder ||
5923                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5924                         I915_WRITE(PCH_FP0(pipe), fp);
5925                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5926
5927                         POSTING_READ(PCH_DPLL(pipe));
5928                         udelay(150);
5929                 }
5930         } else {
5931                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5932                     fp == I915_READ(PCH_FP0(0))) {
5933                         intel_crtc->use_pll_a = true;
5934                         DRM_DEBUG_KMS("using pipe a dpll\n");
5935                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5936                            fp == I915_READ(PCH_FP0(1))) {
5937                         intel_crtc->use_pll_a = false;
5938                         DRM_DEBUG_KMS("using pipe b dpll\n");
5939                 } else {
5940                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5941                         return -EINVAL;
5942                 }
5943         }
5944
5945         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5946          * This is an exception to the general rule that mode_set doesn't turn
5947          * things on.
5948          */
5949         if (is_lvds) {
5950                 temp = I915_READ(PCH_LVDS);
5951                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5952                 if (HAS_PCH_CPT(dev)) {
5953                         temp &= ~PORT_TRANS_SEL_MASK;
5954                         temp |= PORT_TRANS_SEL_CPT(pipe);
5955                 } else {
5956                         if (pipe == 1)
5957                                 temp |= LVDS_PIPEB_SELECT;
5958                         else
5959                                 temp &= ~LVDS_PIPEB_SELECT;
5960                 }
5961
5962                 /* set the corresponsding LVDS_BORDER bit */
5963                 temp |= dev_priv->lvds_border_bits;
5964                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5965                  * set the DPLLs for dual-channel mode or not.
5966                  */
5967                 if (clock.p2 == 7)
5968                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5969                 else
5970                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5971
5972                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5973                  * appropriately here, but we need to look more thoroughly into how
5974                  * panels behave in the two modes.
5975                  */
5976                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5977                         lvds_sync |= LVDS_HSYNC_POLARITY;
5978                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5979                         lvds_sync |= LVDS_VSYNC_POLARITY;
5980                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5981                     != lvds_sync) {
5982                         char flags[2] = "-+";
5983                         DRM_INFO("Changing LVDS panel from "
5984                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5985                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5986                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5987                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5988                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5989                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5990                         temp |= lvds_sync;
5991                 }
5992                 I915_WRITE(PCH_LVDS, temp);
5993         }
5994
5995         pipeconf &= ~PIPECONF_DITHER_EN;
5996         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5997         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5998                 pipeconf |= PIPECONF_DITHER_EN;
5999                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6000         }
6001         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6002                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6003         } else {
6004                 /* For non-DP output, clear any trans DP clock recovery setting.*/
6005                 I915_WRITE(TRANSDATA_M1(pipe), 0);
6006                 I915_WRITE(TRANSDATA_N1(pipe), 0);
6007                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6008                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6009         }
6010
6011         if (!intel_crtc->no_pll &&
6012             (!has_edp_encoder ||
6013              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6014                 I915_WRITE(PCH_DPLL(pipe), dpll);
6015
6016                 /* Wait for the clocks to stabilize. */
6017                 POSTING_READ(PCH_DPLL(pipe));
6018                 udelay(150);
6019
6020                 /* The pixel multiplier can only be updated once the
6021                  * DPLL is enabled and the clocks are stable.
6022                  *
6023                  * So write it again.
6024                  */
6025                 I915_WRITE(PCH_DPLL(pipe), dpll);
6026         }
6027
6028         intel_crtc->lowfreq_avail = false;
6029         if (!intel_crtc->no_pll) {
6030                 if (is_lvds && has_reduced_clock && i915_powersave) {
6031                         I915_WRITE(PCH_FP1(pipe), fp2);
6032                         intel_crtc->lowfreq_avail = true;
6033                         if (HAS_PIPE_CXSR(dev)) {
6034                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6035                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6036                         }
6037                 } else {
6038                         I915_WRITE(PCH_FP1(pipe), fp);
6039                         if (HAS_PIPE_CXSR(dev)) {
6040                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6041                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6042                         }
6043                 }
6044         }
6045
6046         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6047         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6048                 pipeconf |= PIPECONF_INTERLACED_ILK;
6049                 /* the chip adds 2 halflines automatically */
6050                 adjusted_mode->crtc_vtotal -= 1;
6051                 adjusted_mode->crtc_vblank_end -= 1;
6052                 I915_WRITE(VSYNCSHIFT(pipe),
6053                            adjusted_mode->crtc_hsync_start
6054                            - adjusted_mode->crtc_htotal/2);
6055         } else {
6056                 pipeconf |= PIPECONF_PROGRESSIVE;
6057                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6058         }
6059
6060         I915_WRITE(HTOTAL(pipe),
6061                    (adjusted_mode->crtc_hdisplay - 1) |
6062                    ((adjusted_mode->crtc_htotal - 1) << 16));
6063         I915_WRITE(HBLANK(pipe),
6064                    (adjusted_mode->crtc_hblank_start - 1) |
6065                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6066         I915_WRITE(HSYNC(pipe),
6067                    (adjusted_mode->crtc_hsync_start - 1) |
6068                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6069
6070         I915_WRITE(VTOTAL(pipe),
6071                    (adjusted_mode->crtc_vdisplay - 1) |
6072                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6073         I915_WRITE(VBLANK(pipe),
6074                    (adjusted_mode->crtc_vblank_start - 1) |
6075                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6076         I915_WRITE(VSYNC(pipe),
6077                    (adjusted_mode->crtc_vsync_start - 1) |
6078                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6079
6080         /* pipesrc controls the size that is scaled from, which should
6081          * always be the user's requested size.
6082          */
6083         I915_WRITE(PIPESRC(pipe),
6084                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6085
6086         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6087         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6088         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6089         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6090
6091         if (has_edp_encoder &&
6092             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6093                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6094         }
6095
6096         I915_WRITE(PIPECONF(pipe), pipeconf);
6097         POSTING_READ(PIPECONF(pipe));
6098
6099         intel_wait_for_vblank(dev, pipe);
6100
6101         I915_WRITE(DSPCNTR(plane), dspcntr);
6102         POSTING_READ(DSPCNTR(plane));
6103
6104         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6105
6106         intel_update_watermarks(dev);
6107
6108         return ret;
6109 }
6110
6111 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6112                                struct drm_display_mode *mode,
6113                                struct drm_display_mode *adjusted_mode,
6114                                int x, int y,
6115                                struct drm_framebuffer *old_fb)
6116 {
6117         struct drm_device *dev = crtc->dev;
6118         struct drm_i915_private *dev_priv = dev->dev_private;
6119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120         int pipe = intel_crtc->pipe;
6121         int ret;
6122
6123         drm_vblank_pre_modeset(dev, pipe);
6124
6125         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6126                                               x, y, old_fb);
6127         drm_vblank_post_modeset(dev, pipe);
6128
6129         if (ret)
6130                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6131         else
6132                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6133
6134         return ret;
6135 }
6136
6137 static bool intel_eld_uptodate(struct drm_connector *connector,
6138                                int reg_eldv, uint32_t bits_eldv,
6139                                int reg_elda, uint32_t bits_elda,
6140                                int reg_edid)
6141 {
6142         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6143         uint8_t *eld = connector->eld;
6144         uint32_t i;
6145
6146         i = I915_READ(reg_eldv);
6147         i &= bits_eldv;
6148
6149         if (!eld[0])
6150                 return !i;
6151
6152         if (!i)
6153                 return false;
6154
6155         i = I915_READ(reg_elda);
6156         i &= ~bits_elda;
6157         I915_WRITE(reg_elda, i);
6158
6159         for (i = 0; i < eld[2]; i++)
6160                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6161                         return false;
6162
6163         return true;
6164 }
6165
6166 static void g4x_write_eld(struct drm_connector *connector,
6167                           struct drm_crtc *crtc)
6168 {
6169         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6170         uint8_t *eld = connector->eld;
6171         uint32_t eldv;
6172         uint32_t len;
6173         uint32_t i;
6174
6175         i = I915_READ(G4X_AUD_VID_DID);
6176
6177         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6178                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6179         else
6180                 eldv = G4X_ELDV_DEVCTG;
6181
6182         if (intel_eld_uptodate(connector,
6183                                G4X_AUD_CNTL_ST, eldv,
6184                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6185                                G4X_HDMIW_HDMIEDID))
6186                 return;
6187
6188         i = I915_READ(G4X_AUD_CNTL_ST);
6189         i &= ~(eldv | G4X_ELD_ADDR);
6190         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6191         I915_WRITE(G4X_AUD_CNTL_ST, i);
6192
6193         if (!eld[0])
6194                 return;
6195
6196         len = min_t(uint8_t, eld[2], len);
6197         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6198         for (i = 0; i < len; i++)
6199                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6200
6201         i = I915_READ(G4X_AUD_CNTL_ST);
6202         i |= eldv;
6203         I915_WRITE(G4X_AUD_CNTL_ST, i);
6204 }
6205
6206 static void ironlake_write_eld(struct drm_connector *connector,
6207                                      struct drm_crtc *crtc)
6208 {
6209         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6210         uint8_t *eld = connector->eld;
6211         uint32_t eldv;
6212         uint32_t i;
6213         int len;
6214         int hdmiw_hdmiedid;
6215         int aud_config;
6216         int aud_cntl_st;
6217         int aud_cntrl_st2;
6218
6219         if (HAS_PCH_IBX(connector->dev)) {
6220                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6221                 aud_config = IBX_AUD_CONFIG_A;
6222                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6223                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6224         } else {
6225                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6226                 aud_config = CPT_AUD_CONFIG_A;
6227                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6228                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6229         }
6230
6231         i = to_intel_crtc(crtc)->pipe;
6232         hdmiw_hdmiedid += i * 0x100;
6233         aud_cntl_st += i * 0x100;
6234         aud_config += i * 0x100;
6235
6236         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6237
6238         i = I915_READ(aud_cntl_st);
6239         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6240         if (!i) {
6241                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6242                 /* operate blindly on all ports */
6243                 eldv = IBX_ELD_VALIDB;
6244                 eldv |= IBX_ELD_VALIDB << 4;
6245                 eldv |= IBX_ELD_VALIDB << 8;
6246         } else {
6247                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6248                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6249         }
6250
6251         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6252                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6253                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6254                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6255         } else
6256                 I915_WRITE(aud_config, 0);
6257
6258         if (intel_eld_uptodate(connector,
6259                                aud_cntrl_st2, eldv,
6260                                aud_cntl_st, IBX_ELD_ADDRESS,
6261                                hdmiw_hdmiedid))
6262                 return;
6263
6264         i = I915_READ(aud_cntrl_st2);
6265         i &= ~eldv;
6266         I915_WRITE(aud_cntrl_st2, i);
6267
6268         if (!eld[0])
6269                 return;
6270
6271         i = I915_READ(aud_cntl_st);
6272         i &= ~IBX_ELD_ADDRESS;
6273         I915_WRITE(aud_cntl_st, i);
6274
6275         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6276         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6277         for (i = 0; i < len; i++)
6278                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6279
6280         i = I915_READ(aud_cntrl_st2);
6281         i |= eldv;
6282         I915_WRITE(aud_cntrl_st2, i);
6283 }
6284
6285 void intel_write_eld(struct drm_encoder *encoder,
6286                      struct drm_display_mode *mode)
6287 {
6288         struct drm_crtc *crtc = encoder->crtc;
6289         struct drm_connector *connector;
6290         struct drm_device *dev = encoder->dev;
6291         struct drm_i915_private *dev_priv = dev->dev_private;
6292
6293         connector = drm_select_eld(encoder, mode);
6294         if (!connector)
6295                 return;
6296
6297         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6298                          connector->base.id,
6299                          drm_get_connector_name(connector),
6300                          connector->encoder->base.id,
6301                          drm_get_encoder_name(connector->encoder));
6302
6303         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6304
6305         if (dev_priv->display.write_eld)
6306                 dev_priv->display.write_eld(connector, crtc);
6307 }
6308
6309 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6310 void intel_crtc_load_lut(struct drm_crtc *crtc)
6311 {
6312         struct drm_device *dev = crtc->dev;
6313         struct drm_i915_private *dev_priv = dev->dev_private;
6314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315         int palreg = PALETTE(intel_crtc->pipe);
6316         int i;
6317
6318         /* The clocks have to be on to load the palette. */
6319         if (!crtc->enabled || !intel_crtc->active)
6320                 return;
6321
6322         /* use legacy palette for Ironlake */
6323         if (HAS_PCH_SPLIT(dev))
6324                 palreg = LGC_PALETTE(intel_crtc->pipe);
6325
6326         for (i = 0; i < 256; i++) {
6327                 I915_WRITE(palreg + 4 * i,
6328                            (intel_crtc->lut_r[i] << 16) |
6329                            (intel_crtc->lut_g[i] << 8) |
6330                            intel_crtc->lut_b[i]);
6331         }
6332 }
6333
6334 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6335 {
6336         struct drm_device *dev = crtc->dev;
6337         struct drm_i915_private *dev_priv = dev->dev_private;
6338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6339         bool visible = base != 0;
6340         u32 cntl;
6341
6342         if (intel_crtc->cursor_visible == visible)
6343                 return;
6344
6345         cntl = I915_READ(_CURACNTR);
6346         if (visible) {
6347                 /* On these chipsets we can only modify the base whilst
6348                  * the cursor is disabled.
6349                  */
6350                 I915_WRITE(_CURABASE, base);
6351
6352                 cntl &= ~(CURSOR_FORMAT_MASK);
6353                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6354                 cntl |= CURSOR_ENABLE |
6355                         CURSOR_GAMMA_ENABLE |
6356                         CURSOR_FORMAT_ARGB;
6357         } else
6358                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6359         I915_WRITE(_CURACNTR, cntl);
6360
6361         intel_crtc->cursor_visible = visible;
6362 }
6363
6364 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6365 {
6366         struct drm_device *dev = crtc->dev;
6367         struct drm_i915_private *dev_priv = dev->dev_private;
6368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6369         int pipe = intel_crtc->pipe;
6370         bool visible = base != 0;
6371
6372         if (intel_crtc->cursor_visible != visible) {
6373                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6374                 if (base) {
6375                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6376                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6377                         cntl |= pipe << 28; /* Connect to correct pipe */
6378                 } else {
6379                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6380                         cntl |= CURSOR_MODE_DISABLE;
6381                 }
6382                 I915_WRITE(CURCNTR(pipe), cntl);
6383
6384                 intel_crtc->cursor_visible = visible;
6385         }
6386         /* and commit changes on next vblank */
6387         I915_WRITE(CURBASE(pipe), base);
6388 }
6389
6390 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6391 {
6392         struct drm_device *dev = crtc->dev;
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395         int pipe = intel_crtc->pipe;
6396         bool visible = base != 0;
6397
6398         if (intel_crtc->cursor_visible != visible) {
6399                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6400                 if (base) {
6401                         cntl &= ~CURSOR_MODE;
6402                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6403                 } else {
6404                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6405                         cntl |= CURSOR_MODE_DISABLE;
6406                 }
6407                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6408
6409                 intel_crtc->cursor_visible = visible;
6410         }
6411         /* and commit changes on next vblank */
6412         I915_WRITE(CURBASE_IVB(pipe), base);
6413 }
6414
6415 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6416 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6417                                      bool on)
6418 {
6419         struct drm_device *dev = crtc->dev;
6420         struct drm_i915_private *dev_priv = dev->dev_private;
6421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422         int pipe = intel_crtc->pipe;
6423         int x = intel_crtc->cursor_x;
6424         int y = intel_crtc->cursor_y;
6425         u32 base, pos;
6426         bool visible;
6427
6428         pos = 0;
6429
6430         if (on && crtc->enabled && crtc->fb) {
6431                 base = intel_crtc->cursor_addr;
6432                 if (x > (int) crtc->fb->width)
6433                         base = 0;
6434
6435                 if (y > (int) crtc->fb->height)
6436                         base = 0;
6437         } else
6438                 base = 0;
6439
6440         if (x < 0) {
6441                 if (x + intel_crtc->cursor_width < 0)
6442                         base = 0;
6443
6444                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6445                 x = -x;
6446         }
6447         pos |= x << CURSOR_X_SHIFT;
6448
6449         if (y < 0) {
6450                 if (y + intel_crtc->cursor_height < 0)
6451                         base = 0;
6452
6453                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6454                 y = -y;
6455         }
6456         pos |= y << CURSOR_Y_SHIFT;
6457
6458         visible = base != 0;
6459         if (!visible && !intel_crtc->cursor_visible)
6460                 return;
6461
6462         if (IS_IVYBRIDGE(dev)) {
6463                 I915_WRITE(CURPOS_IVB(pipe), pos);
6464                 ivb_update_cursor(crtc, base);
6465         } else {
6466                 I915_WRITE(CURPOS(pipe), pos);
6467                 if (IS_845G(dev) || IS_I865G(dev))
6468                         i845_update_cursor(crtc, base);
6469                 else
6470                         i9xx_update_cursor(crtc, base);
6471         }
6472
6473         if (visible)
6474                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6475 }
6476
6477 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6478                                  struct drm_file *file,
6479                                  uint32_t handle,
6480                                  uint32_t width, uint32_t height)
6481 {
6482         struct drm_device *dev = crtc->dev;
6483         struct drm_i915_private *dev_priv = dev->dev_private;
6484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6485         struct drm_i915_gem_object *obj;
6486         uint32_t addr;
6487         int ret;
6488
6489         DRM_DEBUG_KMS("\n");
6490
6491         /* if we want to turn off the cursor ignore width and height */
6492         if (!handle) {
6493                 DRM_DEBUG_KMS("cursor off\n");
6494                 addr = 0;
6495                 obj = NULL;
6496                 mutex_lock(&dev->struct_mutex);
6497                 goto finish;
6498         }
6499
6500         /* Currently we only support 64x64 cursors */
6501         if (width != 64 || height != 64) {
6502                 DRM_ERROR("we currently only support 64x64 cursors\n");
6503                 return -EINVAL;
6504         }
6505
6506         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6507         if (&obj->base == NULL)
6508                 return -ENOENT;
6509
6510         if (obj->base.size < width * height * 4) {
6511                 DRM_ERROR("buffer is to small\n");
6512                 ret = -ENOMEM;
6513                 goto fail;
6514         }
6515
6516         /* we only need to pin inside GTT if cursor is non-phy */
6517         mutex_lock(&dev->struct_mutex);
6518         if (!dev_priv->info->cursor_needs_physical) {
6519                 if (obj->tiling_mode) {
6520                         DRM_ERROR("cursor cannot be tiled\n");
6521                         ret = -EINVAL;
6522                         goto fail_locked;
6523                 }
6524
6525                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6526                 if (ret) {
6527                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6528                         goto fail_locked;
6529                 }
6530
6531                 ret = i915_gem_object_put_fence(obj);
6532                 if (ret) {
6533                         DRM_ERROR("failed to release fence for cursor");
6534                         goto fail_unpin;
6535                 }
6536
6537                 addr = obj->gtt_offset;
6538         } else {
6539                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6540                 ret = i915_gem_attach_phys_object(dev, obj,
6541                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6542                                                   align);
6543                 if (ret) {
6544                         DRM_ERROR("failed to attach phys object\n");
6545                         goto fail_locked;
6546                 }
6547                 addr = obj->phys_obj->handle->busaddr;
6548         }
6549
6550         if (IS_GEN2(dev))
6551                 I915_WRITE(CURSIZE, (height << 12) | width);
6552
6553  finish:
6554         if (intel_crtc->cursor_bo) {
6555                 if (dev_priv->info->cursor_needs_physical) {
6556                         if (intel_crtc->cursor_bo != obj)
6557                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6558                 } else
6559                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6560                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6561         }
6562
6563         mutex_unlock(&dev->struct_mutex);
6564
6565         intel_crtc->cursor_addr = addr;
6566         intel_crtc->cursor_bo = obj;
6567         intel_crtc->cursor_width = width;
6568         intel_crtc->cursor_height = height;
6569
6570         intel_crtc_update_cursor(crtc, true);
6571
6572         return 0;
6573 fail_unpin:
6574         i915_gem_object_unpin(obj);
6575 fail_locked:
6576         mutex_unlock(&dev->struct_mutex);
6577 fail:
6578         drm_gem_object_unreference_unlocked(&obj->base);
6579         return ret;
6580 }
6581
6582 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6583 {
6584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6585
6586         intel_crtc->cursor_x = x;
6587         intel_crtc->cursor_y = y;
6588
6589         intel_crtc_update_cursor(crtc, true);
6590
6591         return 0;
6592 }
6593
6594 /** Sets the color ramps on behalf of RandR */
6595 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6596                                  u16 blue, int regno)
6597 {
6598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6599
6600         intel_crtc->lut_r[regno] = red >> 8;
6601         intel_crtc->lut_g[regno] = green >> 8;
6602         intel_crtc->lut_b[regno] = blue >> 8;
6603 }
6604
6605 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6606                              u16 *blue, int regno)
6607 {
6608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6609
6610         *red = intel_crtc->lut_r[regno] << 8;
6611         *green = intel_crtc->lut_g[regno] << 8;
6612         *blue = intel_crtc->lut_b[regno] << 8;
6613 }
6614
6615 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6616                                  u16 *blue, uint32_t start, uint32_t size)
6617 {
6618         int end = (start + size > 256) ? 256 : start + size, i;
6619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6620
6621         for (i = start; i < end; i++) {
6622                 intel_crtc->lut_r[i] = red[i] >> 8;
6623                 intel_crtc->lut_g[i] = green[i] >> 8;
6624                 intel_crtc->lut_b[i] = blue[i] >> 8;
6625         }
6626
6627         intel_crtc_load_lut(crtc);
6628 }
6629
6630 /**
6631  * Get a pipe with a simple mode set on it for doing load-based monitor
6632  * detection.
6633  *
6634  * It will be up to the load-detect code to adjust the pipe as appropriate for
6635  * its requirements.  The pipe will be connected to no other encoders.
6636  *
6637  * Currently this code will only succeed if there is a pipe with no encoders
6638  * configured for it.  In the future, it could choose to temporarily disable
6639  * some outputs to free up a pipe for its use.
6640  *
6641  * \return crtc, or NULL if no pipes are available.
6642  */
6643
6644 /* VESA 640x480x72Hz mode to set on the pipe */
6645 static struct drm_display_mode load_detect_mode = {
6646         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6647                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6648 };
6649
6650 static struct drm_framebuffer *
6651 intel_framebuffer_create(struct drm_device *dev,
6652                          struct drm_mode_fb_cmd2 *mode_cmd,
6653                          struct drm_i915_gem_object *obj)
6654 {
6655         struct intel_framebuffer *intel_fb;
6656         int ret;
6657
6658         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6659         if (!intel_fb) {
6660                 drm_gem_object_unreference_unlocked(&obj->base);
6661                 return ERR_PTR(-ENOMEM);
6662         }
6663
6664         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6665         if (ret) {
6666                 drm_gem_object_unreference_unlocked(&obj->base);
6667                 kfree(intel_fb);
6668                 return ERR_PTR(ret);
6669         }
6670
6671         return &intel_fb->base;
6672 }
6673
6674 static u32
6675 intel_framebuffer_pitch_for_width(int width, int bpp)
6676 {
6677         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6678         return ALIGN(pitch, 64);
6679 }
6680
6681 static u32
6682 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6683 {
6684         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6685         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6686 }
6687
6688 static struct drm_framebuffer *
6689 intel_framebuffer_create_for_mode(struct drm_device *dev,
6690                                   struct drm_display_mode *mode,
6691                                   int depth, int bpp)
6692 {
6693         struct drm_i915_gem_object *obj;
6694         struct drm_mode_fb_cmd2 mode_cmd;
6695
6696         obj = i915_gem_alloc_object(dev,
6697                                     intel_framebuffer_size_for_mode(mode, bpp));
6698         if (obj == NULL)
6699                 return ERR_PTR(-ENOMEM);
6700
6701         mode_cmd.width = mode->hdisplay;
6702         mode_cmd.height = mode->vdisplay;
6703         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6704                                                                 bpp);
6705         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6706
6707         return intel_framebuffer_create(dev, &mode_cmd, obj);
6708 }
6709
6710 static struct drm_framebuffer *
6711 mode_fits_in_fbdev(struct drm_device *dev,
6712                    struct drm_display_mode *mode)
6713 {
6714         struct drm_i915_private *dev_priv = dev->dev_private;
6715         struct drm_i915_gem_object *obj;
6716         struct drm_framebuffer *fb;
6717
6718         if (dev_priv->fbdev == NULL)
6719                 return NULL;
6720
6721         obj = dev_priv->fbdev->ifb.obj;
6722         if (obj == NULL)
6723                 return NULL;
6724
6725         fb = &dev_priv->fbdev->ifb.base;
6726         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6727                                                                fb->bits_per_pixel))
6728                 return NULL;
6729
6730         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6731                 return NULL;
6732
6733         return fb;
6734 }
6735
6736 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6737                                 struct drm_connector *connector,
6738                                 struct drm_display_mode *mode,
6739                                 struct intel_load_detect_pipe *old)
6740 {
6741         struct intel_crtc *intel_crtc;
6742         struct drm_crtc *possible_crtc;
6743         struct drm_encoder *encoder = &intel_encoder->base;
6744         struct drm_crtc *crtc = NULL;
6745         struct drm_device *dev = encoder->dev;
6746         struct drm_framebuffer *old_fb;
6747         int i = -1;
6748
6749         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6750                       connector->base.id, drm_get_connector_name(connector),
6751                       encoder->base.id, drm_get_encoder_name(encoder));
6752
6753         /*
6754          * Algorithm gets a little messy:
6755          *
6756          *   - if the connector already has an assigned crtc, use it (but make
6757          *     sure it's on first)
6758          *
6759          *   - try to find the first unused crtc that can drive this connector,
6760          *     and use that if we find one
6761          */
6762
6763         /* See if we already have a CRTC for this connector */
6764         if (encoder->crtc) {
6765                 crtc = encoder->crtc;
6766
6767                 intel_crtc = to_intel_crtc(crtc);
6768                 old->dpms_mode = intel_crtc->dpms_mode;
6769                 old->load_detect_temp = false;
6770
6771                 /* Make sure the crtc and connector are running */
6772                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6773                         struct drm_encoder_helper_funcs *encoder_funcs;
6774                         struct drm_crtc_helper_funcs *crtc_funcs;
6775
6776                         crtc_funcs = crtc->helper_private;
6777                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6778
6779                         encoder_funcs = encoder->helper_private;
6780                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6781                 }
6782
6783                 return true;
6784         }
6785
6786         /* Find an unused one (if possible) */
6787         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6788                 i++;
6789                 if (!(encoder->possible_crtcs & (1 << i)))
6790                         continue;
6791                 if (!possible_crtc->enabled) {
6792                         crtc = possible_crtc;
6793                         break;
6794                 }
6795         }
6796
6797         /*
6798          * If we didn't find an unused CRTC, don't use any.
6799          */
6800         if (!crtc) {
6801                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6802                 return false;
6803         }
6804
6805         encoder->crtc = crtc;
6806         connector->encoder = encoder;
6807
6808         intel_crtc = to_intel_crtc(crtc);
6809         old->dpms_mode = intel_crtc->dpms_mode;
6810         old->load_detect_temp = true;
6811         old->release_fb = NULL;
6812
6813         if (!mode)
6814                 mode = &load_detect_mode;
6815
6816         old_fb = crtc->fb;
6817
6818         /* We need a framebuffer large enough to accommodate all accesses
6819          * that the plane may generate whilst we perform load detection.
6820          * We can not rely on the fbcon either being present (we get called
6821          * during its initialisation to detect all boot displays, or it may
6822          * not even exist) or that it is large enough to satisfy the
6823          * requested mode.
6824          */
6825         crtc->fb = mode_fits_in_fbdev(dev, mode);
6826         if (crtc->fb == NULL) {
6827                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6828                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6829                 old->release_fb = crtc->fb;
6830         } else
6831                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6832         if (IS_ERR(crtc->fb)) {
6833                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6834                 crtc->fb = old_fb;
6835                 return false;
6836         }
6837
6838         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6839                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6840                 if (old->release_fb)
6841                         old->release_fb->funcs->destroy(old->release_fb);
6842                 crtc->fb = old_fb;
6843                 return false;
6844         }
6845
6846         /* let the connector get through one full cycle before testing */
6847         intel_wait_for_vblank(dev, intel_crtc->pipe);
6848
6849         return true;
6850 }
6851
6852 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6853                                     struct drm_connector *connector,
6854                                     struct intel_load_detect_pipe *old)
6855 {
6856         struct drm_encoder *encoder = &intel_encoder->base;
6857         struct drm_device *dev = encoder->dev;
6858         struct drm_crtc *crtc = encoder->crtc;
6859         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6860         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6861
6862         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6863                       connector->base.id, drm_get_connector_name(connector),
6864                       encoder->base.id, drm_get_encoder_name(encoder));
6865
6866         if (old->load_detect_temp) {
6867                 connector->encoder = NULL;
6868                 drm_helper_disable_unused_functions(dev);
6869
6870                 if (old->release_fb)
6871                         old->release_fb->funcs->destroy(old->release_fb);
6872
6873                 return;
6874         }
6875
6876         /* Switch crtc and encoder back off if necessary */
6877         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6878                 encoder_funcs->dpms(encoder, old->dpms_mode);
6879                 crtc_funcs->dpms(crtc, old->dpms_mode);
6880         }
6881 }
6882
6883 /* Returns the clock of the currently programmed mode of the given pipe. */
6884 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6885 {
6886         struct drm_i915_private *dev_priv = dev->dev_private;
6887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6888         int pipe = intel_crtc->pipe;
6889         u32 dpll = I915_READ(DPLL(pipe));
6890         u32 fp;
6891         intel_clock_t clock;
6892
6893         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6894                 fp = I915_READ(FP0(pipe));
6895         else
6896                 fp = I915_READ(FP1(pipe));
6897
6898         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6899         if (IS_PINEVIEW(dev)) {
6900                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6901                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6902         } else {
6903                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6904                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6905         }
6906
6907         if (!IS_GEN2(dev)) {
6908                 if (IS_PINEVIEW(dev))
6909                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6910                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6911                 else
6912                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6913                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6914
6915                 switch (dpll & DPLL_MODE_MASK) {
6916                 case DPLLB_MODE_DAC_SERIAL:
6917                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6918                                 5 : 10;
6919                         break;
6920                 case DPLLB_MODE_LVDS:
6921                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6922                                 7 : 14;
6923                         break;
6924                 default:
6925                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6926                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6927                         return 0;
6928                 }
6929
6930                 /* XXX: Handle the 100Mhz refclk */
6931                 intel_clock(dev, 96000, &clock);
6932         } else {
6933                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6934
6935                 if (is_lvds) {
6936                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6937                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6938                         clock.p2 = 14;
6939
6940                         if ((dpll & PLL_REF_INPUT_MASK) ==
6941                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6942                                 /* XXX: might not be 66MHz */
6943                                 intel_clock(dev, 66000, &clock);
6944                         } else
6945                                 intel_clock(dev, 48000, &clock);
6946                 } else {
6947                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6948                                 clock.p1 = 2;
6949                         else {
6950                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6951                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6952                         }
6953                         if (dpll & PLL_P2_DIVIDE_BY_4)
6954                                 clock.p2 = 4;
6955                         else
6956                                 clock.p2 = 2;
6957
6958                         intel_clock(dev, 48000, &clock);
6959                 }
6960         }
6961
6962         /* XXX: It would be nice to validate the clocks, but we can't reuse
6963          * i830PllIsValid() because it relies on the xf86_config connector
6964          * configuration being accurate, which it isn't necessarily.
6965          */
6966
6967         return clock.dot;
6968 }
6969
6970 /** Returns the currently programmed mode of the given pipe. */
6971 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6972                                              struct drm_crtc *crtc)
6973 {
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6976         int pipe = intel_crtc->pipe;
6977         struct drm_display_mode *mode;
6978         int htot = I915_READ(HTOTAL(pipe));
6979         int hsync = I915_READ(HSYNC(pipe));
6980         int vtot = I915_READ(VTOTAL(pipe));
6981         int vsync = I915_READ(VSYNC(pipe));
6982
6983         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6984         if (!mode)
6985                 return NULL;
6986
6987         mode->clock = intel_crtc_clock_get(dev, crtc);
6988         mode->hdisplay = (htot & 0xffff) + 1;
6989         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6990         mode->hsync_start = (hsync & 0xffff) + 1;
6991         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6992         mode->vdisplay = (vtot & 0xffff) + 1;
6993         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6994         mode->vsync_start = (vsync & 0xffff) + 1;
6995         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6996
6997         drm_mode_set_name(mode);
6998         drm_mode_set_crtcinfo(mode, 0);
6999
7000         return mode;
7001 }
7002
7003 #define GPU_IDLE_TIMEOUT 400 /* ms */
7004
7005 /* When this timer fires, we've been idle for awhile */
7006 static void intel_gpu_idle_timer(unsigned long arg)
7007 {
7008         struct drm_device *dev = (struct drm_device *)arg;
7009         drm_i915_private_t *dev_priv = dev->dev_private;
7010
7011         if (!list_empty(&dev_priv->mm.active_list)) {
7012                 /* Still processing requests, so just re-arm the timer. */
7013                 mod_timer(&dev_priv->idle_timer, jiffies +
7014                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7015                 return;
7016         }
7017
7018         dev_priv->busy = false;
7019         queue_work(dev_priv->wq, &dev_priv->idle_work);
7020 }
7021
7022 #define CRTC_IDLE_TIMEOUT 700 /* ms */
7023
7024 static void intel_crtc_idle_timer(unsigned long arg)
7025 {
7026         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7027         struct drm_crtc *crtc = &intel_crtc->base;
7028         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7029         struct intel_framebuffer *intel_fb;
7030
7031         intel_fb = to_intel_framebuffer(crtc->fb);
7032         if (intel_fb && intel_fb->obj->active) {
7033                 /* The framebuffer is still being accessed by the GPU. */
7034                 mod_timer(&intel_crtc->idle_timer, jiffies +
7035                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7036                 return;
7037         }
7038
7039         intel_crtc->busy = false;
7040         queue_work(dev_priv->wq, &dev_priv->idle_work);
7041 }
7042
7043 static void intel_increase_pllclock(struct drm_crtc *crtc)
7044 {
7045         struct drm_device *dev = crtc->dev;
7046         drm_i915_private_t *dev_priv = dev->dev_private;
7047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048         int pipe = intel_crtc->pipe;
7049         int dpll_reg = DPLL(pipe);
7050         int dpll;
7051
7052         if (HAS_PCH_SPLIT(dev))
7053                 return;
7054
7055         if (!dev_priv->lvds_downclock_avail)
7056                 return;
7057
7058         dpll = I915_READ(dpll_reg);
7059         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7060                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7061
7062                 assert_panel_unlocked(dev_priv, pipe);
7063
7064                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7065                 I915_WRITE(dpll_reg, dpll);
7066                 intel_wait_for_vblank(dev, pipe);
7067
7068                 dpll = I915_READ(dpll_reg);
7069                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7070                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7071         }
7072
7073         /* Schedule downclock */
7074         mod_timer(&intel_crtc->idle_timer, jiffies +
7075                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7076 }
7077
7078 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7079 {
7080         struct drm_device *dev = crtc->dev;
7081         drm_i915_private_t *dev_priv = dev->dev_private;
7082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7083
7084         if (HAS_PCH_SPLIT(dev))
7085                 return;
7086
7087         if (!dev_priv->lvds_downclock_avail)
7088                 return;
7089
7090         /*
7091          * Since this is called by a timer, we should never get here in
7092          * the manual case.
7093          */
7094         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7095                 int pipe = intel_crtc->pipe;
7096                 int dpll_reg = DPLL(pipe);
7097                 u32 dpll;
7098
7099                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7100
7101                 assert_panel_unlocked(dev_priv, pipe);
7102
7103                 dpll = I915_READ(dpll_reg);
7104                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7105                 I915_WRITE(dpll_reg, dpll);
7106                 intel_wait_for_vblank(dev, pipe);
7107                 dpll = I915_READ(dpll_reg);
7108                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7109                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7110         }
7111 }
7112
7113 /**
7114  * intel_idle_update - adjust clocks for idleness
7115  * @work: work struct
7116  *
7117  * Either the GPU or display (or both) went idle.  Check the busy status
7118  * here and adjust the CRTC and GPU clocks as necessary.
7119  */
7120 static void intel_idle_update(struct work_struct *work)
7121 {
7122         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7123                                                     idle_work);
7124         struct drm_device *dev = dev_priv->dev;
7125         struct drm_crtc *crtc;
7126         struct intel_crtc *intel_crtc;
7127
7128         if (!i915_powersave)
7129                 return;
7130
7131         mutex_lock(&dev->struct_mutex);
7132
7133         i915_update_gfx_val(dev_priv);
7134
7135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7136                 /* Skip inactive CRTCs */
7137                 if (!crtc->fb)
7138                         continue;
7139
7140                 intel_crtc = to_intel_crtc(crtc);
7141                 if (!intel_crtc->busy)
7142                         intel_decrease_pllclock(crtc);
7143         }
7144
7145
7146         mutex_unlock(&dev->struct_mutex);
7147 }
7148
7149 /**
7150  * intel_mark_busy - mark the GPU and possibly the display busy
7151  * @dev: drm device
7152  * @obj: object we're operating on
7153  *
7154  * Callers can use this function to indicate that the GPU is busy processing
7155  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7156  * buffer), we'll also mark the display as busy, so we know to increase its
7157  * clock frequency.
7158  */
7159 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7160 {
7161         drm_i915_private_t *dev_priv = dev->dev_private;
7162         struct drm_crtc *crtc = NULL;
7163         struct intel_framebuffer *intel_fb;
7164         struct intel_crtc *intel_crtc;
7165
7166         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7167                 return;
7168
7169         if (!dev_priv->busy)
7170                 dev_priv->busy = true;
7171         else
7172                 mod_timer(&dev_priv->idle_timer, jiffies +
7173                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7174
7175         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7176                 if (!crtc->fb)
7177                         continue;
7178
7179                 intel_crtc = to_intel_crtc(crtc);
7180                 intel_fb = to_intel_framebuffer(crtc->fb);
7181                 if (intel_fb->obj == obj) {
7182                         if (!intel_crtc->busy) {
7183                                 /* Non-busy -> busy, upclock */
7184                                 intel_increase_pllclock(crtc);
7185                                 intel_crtc->busy = true;
7186                         } else {
7187                                 /* Busy -> busy, put off timer */
7188                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7189                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7190                         }
7191                 }
7192         }
7193 }
7194
7195 static void intel_crtc_destroy(struct drm_crtc *crtc)
7196 {
7197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7198         struct drm_device *dev = crtc->dev;
7199         struct intel_unpin_work *work;
7200         unsigned long flags;
7201
7202         spin_lock_irqsave(&dev->event_lock, flags);
7203         work = intel_crtc->unpin_work;
7204         intel_crtc->unpin_work = NULL;
7205         spin_unlock_irqrestore(&dev->event_lock, flags);
7206
7207         if (work) {
7208                 cancel_work_sync(&work->work);
7209                 kfree(work);
7210         }
7211
7212         drm_crtc_cleanup(crtc);
7213
7214         kfree(intel_crtc);
7215 }
7216
7217 static void intel_unpin_work_fn(struct work_struct *__work)
7218 {
7219         struct intel_unpin_work *work =
7220                 container_of(__work, struct intel_unpin_work, work);
7221
7222         mutex_lock(&work->dev->struct_mutex);
7223         intel_unpin_fb_obj(work->old_fb_obj);
7224         drm_gem_object_unreference(&work->pending_flip_obj->base);
7225         drm_gem_object_unreference(&work->old_fb_obj->base);
7226
7227         intel_update_fbc(work->dev);
7228         mutex_unlock(&work->dev->struct_mutex);
7229         kfree(work);
7230 }
7231
7232 static void do_intel_finish_page_flip(struct drm_device *dev,
7233                                       struct drm_crtc *crtc)
7234 {
7235         drm_i915_private_t *dev_priv = dev->dev_private;
7236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7237         struct intel_unpin_work *work;
7238         struct drm_i915_gem_object *obj;
7239         struct drm_pending_vblank_event *e;
7240         struct timeval tnow, tvbl;
7241         unsigned long flags;
7242
7243         /* Ignore early vblank irqs */
7244         if (intel_crtc == NULL)
7245                 return;
7246
7247         do_gettimeofday(&tnow);
7248
7249         spin_lock_irqsave(&dev->event_lock, flags);
7250         work = intel_crtc->unpin_work;
7251         if (work == NULL || !work->pending) {
7252                 spin_unlock_irqrestore(&dev->event_lock, flags);
7253                 return;
7254         }
7255
7256         intel_crtc->unpin_work = NULL;
7257
7258         if (work->event) {
7259                 e = work->event;
7260                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7261
7262                 /* Called before vblank count and timestamps have
7263                  * been updated for the vblank interval of flip
7264                  * completion? Need to increment vblank count and
7265                  * add one videorefresh duration to returned timestamp
7266                  * to account for this. We assume this happened if we
7267                  * get called over 0.9 frame durations after the last
7268                  * timestamped vblank.
7269                  *
7270                  * This calculation can not be used with vrefresh rates
7271                  * below 5Hz (10Hz to be on the safe side) without
7272                  * promoting to 64 integers.
7273                  */
7274                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7275                     9 * crtc->framedur_ns) {
7276                         e->event.sequence++;
7277                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7278                                              crtc->framedur_ns);
7279                 }
7280
7281                 e->event.tv_sec = tvbl.tv_sec;
7282                 e->event.tv_usec = tvbl.tv_usec;
7283
7284                 list_add_tail(&e->base.link,
7285                               &e->base.file_priv->event_list);
7286                 wake_up_interruptible(&e->base.file_priv->event_wait);
7287         }
7288
7289         drm_vblank_put(dev, intel_crtc->pipe);
7290
7291         spin_unlock_irqrestore(&dev->event_lock, flags);
7292
7293         obj = work->old_fb_obj;
7294
7295         atomic_clear_mask(1 << intel_crtc->plane,
7296                           &obj->pending_flip.counter);
7297         if (atomic_read(&obj->pending_flip) == 0)
7298                 wake_up(&dev_priv->pending_flip_queue);
7299
7300         schedule_work(&work->work);
7301
7302         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7303 }
7304
7305 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7306 {
7307         drm_i915_private_t *dev_priv = dev->dev_private;
7308         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7309
7310         do_intel_finish_page_flip(dev, crtc);
7311 }
7312
7313 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7314 {
7315         drm_i915_private_t *dev_priv = dev->dev_private;
7316         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7317
7318         do_intel_finish_page_flip(dev, crtc);
7319 }
7320
7321 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7322 {
7323         drm_i915_private_t *dev_priv = dev->dev_private;
7324         struct intel_crtc *intel_crtc =
7325                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7326         unsigned long flags;
7327
7328         spin_lock_irqsave(&dev->event_lock, flags);
7329         if (intel_crtc->unpin_work) {
7330                 if ((++intel_crtc->unpin_work->pending) > 1)
7331                         DRM_ERROR("Prepared flip multiple times\n");
7332         } else {
7333                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7334         }
7335         spin_unlock_irqrestore(&dev->event_lock, flags);
7336 }
7337
7338 static int intel_gen2_queue_flip(struct drm_device *dev,
7339                                  struct drm_crtc *crtc,
7340                                  struct drm_framebuffer *fb,
7341                                  struct drm_i915_gem_object *obj)
7342 {
7343         struct drm_i915_private *dev_priv = dev->dev_private;
7344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7345         unsigned long offset;
7346         u32 flip_mask;
7347         int ret;
7348
7349         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7350         if (ret)
7351                 goto out;
7352
7353         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7354         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7355
7356         ret = BEGIN_LP_RING(6);
7357         if (ret)
7358                 goto out;
7359
7360         /* Can't queue multiple flips, so wait for the previous
7361          * one to finish before executing the next.
7362          */
7363         if (intel_crtc->plane)
7364                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7365         else
7366                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7367         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7368         OUT_RING(MI_NOOP);
7369         OUT_RING(MI_DISPLAY_FLIP |
7370                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7371         OUT_RING(fb->pitches[0]);
7372         OUT_RING(obj->gtt_offset + offset);
7373         OUT_RING(0); /* aux display base address, unused */
7374         ADVANCE_LP_RING();
7375 out:
7376         return ret;
7377 }
7378
7379 static int intel_gen3_queue_flip(struct drm_device *dev,
7380                                  struct drm_crtc *crtc,
7381                                  struct drm_framebuffer *fb,
7382                                  struct drm_i915_gem_object *obj)
7383 {
7384         struct drm_i915_private *dev_priv = dev->dev_private;
7385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7386         unsigned long offset;
7387         u32 flip_mask;
7388         int ret;
7389
7390         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7391         if (ret)
7392                 goto out;
7393
7394         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7395         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7396
7397         ret = BEGIN_LP_RING(6);
7398         if (ret)
7399                 goto out;
7400
7401         if (intel_crtc->plane)
7402                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7403         else
7404                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7405         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7406         OUT_RING(MI_NOOP);
7407         OUT_RING(MI_DISPLAY_FLIP_I915 |
7408                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7409         OUT_RING(fb->pitches[0]);
7410         OUT_RING(obj->gtt_offset + offset);
7411         OUT_RING(MI_NOOP);
7412
7413         ADVANCE_LP_RING();
7414 out:
7415         return ret;
7416 }
7417
7418 static int intel_gen4_queue_flip(struct drm_device *dev,
7419                                  struct drm_crtc *crtc,
7420                                  struct drm_framebuffer *fb,
7421                                  struct drm_i915_gem_object *obj)
7422 {
7423         struct drm_i915_private *dev_priv = dev->dev_private;
7424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7425         uint32_t pf, pipesrc;
7426         int ret;
7427
7428         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7429         if (ret)
7430                 goto out;
7431
7432         ret = BEGIN_LP_RING(4);
7433         if (ret)
7434                 goto out;
7435
7436         /* i965+ uses the linear or tiled offsets from the
7437          * Display Registers (which do not change across a page-flip)
7438          * so we need only reprogram the base address.
7439          */
7440         OUT_RING(MI_DISPLAY_FLIP |
7441                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7442         OUT_RING(fb->pitches[0]);
7443         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7444
7445         /* XXX Enabling the panel-fitter across page-flip is so far
7446          * untested on non-native modes, so ignore it for now.
7447          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7448          */
7449         pf = 0;
7450         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7451         OUT_RING(pf | pipesrc);
7452         ADVANCE_LP_RING();
7453 out:
7454         return ret;
7455 }
7456
7457 static int intel_gen6_queue_flip(struct drm_device *dev,
7458                                  struct drm_crtc *crtc,
7459                                  struct drm_framebuffer *fb,
7460                                  struct drm_i915_gem_object *obj)
7461 {
7462         struct drm_i915_private *dev_priv = dev->dev_private;
7463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7464         uint32_t pf, pipesrc;
7465         int ret;
7466
7467         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7468         if (ret)
7469                 goto out;
7470
7471         ret = BEGIN_LP_RING(4);
7472         if (ret)
7473                 goto out;
7474
7475         OUT_RING(MI_DISPLAY_FLIP |
7476                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7477         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7478         OUT_RING(obj->gtt_offset);
7479
7480         /* Contrary to the suggestions in the documentation,
7481          * "Enable Panel Fitter" does not seem to be required when page
7482          * flipping with a non-native mode, and worse causes a normal
7483          * modeset to fail.
7484          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7485          */
7486         pf = 0;
7487         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7488         OUT_RING(pf | pipesrc);
7489         ADVANCE_LP_RING();
7490 out:
7491         return ret;
7492 }
7493
7494 /*
7495  * On gen7 we currently use the blit ring because (in early silicon at least)
7496  * the render ring doesn't give us interrpts for page flip completion, which
7497  * means clients will hang after the first flip is queued.  Fortunately the
7498  * blit ring generates interrupts properly, so use it instead.
7499  */
7500 static int intel_gen7_queue_flip(struct drm_device *dev,
7501                                  struct drm_crtc *crtc,
7502                                  struct drm_framebuffer *fb,
7503                                  struct drm_i915_gem_object *obj)
7504 {
7505         struct drm_i915_private *dev_priv = dev->dev_private;
7506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7507         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7508         int ret;
7509
7510         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7511         if (ret)
7512                 goto out;
7513
7514         ret = intel_ring_begin(ring, 4);
7515         if (ret)
7516                 goto out;
7517
7518         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7519         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7520         intel_ring_emit(ring, (obj->gtt_offset));
7521         intel_ring_emit(ring, (MI_NOOP));
7522         intel_ring_advance(ring);
7523 out:
7524         return ret;
7525 }
7526
7527 static int intel_default_queue_flip(struct drm_device *dev,
7528                                     struct drm_crtc *crtc,
7529                                     struct drm_framebuffer *fb,
7530                                     struct drm_i915_gem_object *obj)
7531 {
7532         return -ENODEV;
7533 }
7534
7535 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7536                                 struct drm_framebuffer *fb,
7537                                 struct drm_pending_vblank_event *event)
7538 {
7539         struct drm_device *dev = crtc->dev;
7540         struct drm_i915_private *dev_priv = dev->dev_private;
7541         struct intel_framebuffer *intel_fb;
7542         struct drm_i915_gem_object *obj;
7543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7544         struct intel_unpin_work *work;
7545         unsigned long flags;
7546         int ret;
7547
7548         work = kzalloc(sizeof *work, GFP_KERNEL);
7549         if (work == NULL)
7550                 return -ENOMEM;
7551
7552         work->event = event;
7553         work->dev = crtc->dev;
7554         intel_fb = to_intel_framebuffer(crtc->fb);
7555         work->old_fb_obj = intel_fb->obj;
7556         INIT_WORK(&work->work, intel_unpin_work_fn);
7557
7558         ret = drm_vblank_get(dev, intel_crtc->pipe);
7559         if (ret)
7560                 goto free_work;
7561
7562         /* We borrow the event spin lock for protecting unpin_work */
7563         spin_lock_irqsave(&dev->event_lock, flags);
7564         if (intel_crtc->unpin_work) {
7565                 spin_unlock_irqrestore(&dev->event_lock, flags);
7566                 kfree(work);
7567                 drm_vblank_put(dev, intel_crtc->pipe);
7568
7569                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7570                 return -EBUSY;
7571         }
7572         intel_crtc->unpin_work = work;
7573         spin_unlock_irqrestore(&dev->event_lock, flags);
7574
7575         intel_fb = to_intel_framebuffer(fb);
7576         obj = intel_fb->obj;
7577
7578         mutex_lock(&dev->struct_mutex);
7579
7580         /* Reference the objects for the scheduled work. */
7581         drm_gem_object_reference(&work->old_fb_obj->base);
7582         drm_gem_object_reference(&obj->base);
7583
7584         crtc->fb = fb;
7585
7586         work->pending_flip_obj = obj;
7587
7588         work->enable_stall_check = true;
7589
7590         /* Block clients from rendering to the new back buffer until
7591          * the flip occurs and the object is no longer visible.
7592          */
7593         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7594
7595         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7596         if (ret)
7597                 goto cleanup_pending;
7598
7599         intel_disable_fbc(dev);
7600         mutex_unlock(&dev->struct_mutex);
7601
7602         trace_i915_flip_request(intel_crtc->plane, obj);
7603
7604         return 0;
7605
7606 cleanup_pending:
7607         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7608         drm_gem_object_unreference(&work->old_fb_obj->base);
7609         drm_gem_object_unreference(&obj->base);
7610         mutex_unlock(&dev->struct_mutex);
7611
7612         spin_lock_irqsave(&dev->event_lock, flags);
7613         intel_crtc->unpin_work = NULL;
7614         spin_unlock_irqrestore(&dev->event_lock, flags);
7615
7616         drm_vblank_put(dev, intel_crtc->pipe);
7617 free_work:
7618         kfree(work);
7619
7620         return ret;
7621 }
7622
7623 static void intel_sanitize_modesetting(struct drm_device *dev,
7624                                        int pipe, int plane)
7625 {
7626         struct drm_i915_private *dev_priv = dev->dev_private;
7627         u32 reg, val;
7628
7629         /* Clear any frame start delays used for debugging left by the BIOS */
7630         for_each_pipe(pipe) {
7631                 reg = PIPECONF(pipe);
7632                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7633         }
7634
7635         if (HAS_PCH_SPLIT(dev))
7636                 return;
7637
7638         /* Who knows what state these registers were left in by the BIOS or
7639          * grub?
7640          *
7641          * If we leave the registers in a conflicting state (e.g. with the
7642          * display plane reading from the other pipe than the one we intend
7643          * to use) then when we attempt to teardown the active mode, we will
7644          * not disable the pipes and planes in the correct order -- leaving
7645          * a plane reading from a disabled pipe and possibly leading to
7646          * undefined behaviour.
7647          */
7648
7649         reg = DSPCNTR(plane);
7650         val = I915_READ(reg);
7651
7652         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7653                 return;
7654         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7655                 return;
7656
7657         /* This display plane is active and attached to the other CPU pipe. */
7658         pipe = !pipe;
7659
7660         /* Disable the plane and wait for it to stop reading from the pipe. */
7661         intel_disable_plane(dev_priv, plane, pipe);
7662         intel_disable_pipe(dev_priv, pipe);
7663 }
7664
7665 static void intel_crtc_reset(struct drm_crtc *crtc)
7666 {
7667         struct drm_device *dev = crtc->dev;
7668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7669
7670         /* Reset flags back to the 'unknown' status so that they
7671          * will be correctly set on the initial modeset.
7672          */
7673         intel_crtc->dpms_mode = -1;
7674
7675         /* We need to fix up any BIOS configuration that conflicts with
7676          * our expectations.
7677          */
7678         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7679 }
7680
7681 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7682         .dpms = intel_crtc_dpms,
7683         .mode_fixup = intel_crtc_mode_fixup,
7684         .mode_set = intel_crtc_mode_set,
7685         .mode_set_base = intel_pipe_set_base,
7686         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7687         .load_lut = intel_crtc_load_lut,
7688         .disable = intel_crtc_disable,
7689 };
7690
7691 static const struct drm_crtc_funcs intel_crtc_funcs = {
7692         .reset = intel_crtc_reset,
7693         .cursor_set = intel_crtc_cursor_set,
7694         .cursor_move = intel_crtc_cursor_move,
7695         .gamma_set = intel_crtc_gamma_set,
7696         .set_config = drm_crtc_helper_set_config,
7697         .destroy = intel_crtc_destroy,
7698         .page_flip = intel_crtc_page_flip,
7699 };
7700
7701 static void intel_crtc_init(struct drm_device *dev, int pipe)
7702 {
7703         drm_i915_private_t *dev_priv = dev->dev_private;
7704         struct intel_crtc *intel_crtc;
7705         int i;
7706
7707         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7708         if (intel_crtc == NULL)
7709                 return;
7710
7711         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7712
7713         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7714         for (i = 0; i < 256; i++) {
7715                 intel_crtc->lut_r[i] = i;
7716                 intel_crtc->lut_g[i] = i;
7717                 intel_crtc->lut_b[i] = i;
7718         }
7719
7720         /* Swap pipes & planes for FBC on pre-965 */
7721         intel_crtc->pipe = pipe;
7722         intel_crtc->plane = pipe;
7723         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7724                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7725                 intel_crtc->plane = !pipe;
7726         }
7727
7728         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7729                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7730         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7731         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7732
7733         intel_crtc_reset(&intel_crtc->base);
7734         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7735         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7736
7737         if (HAS_PCH_SPLIT(dev)) {
7738                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7739                         intel_crtc->no_pll = true;
7740                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7741                 intel_helper_funcs.commit = ironlake_crtc_commit;
7742         } else {
7743                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7744                 intel_helper_funcs.commit = i9xx_crtc_commit;
7745         }
7746
7747         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7748
7749         intel_crtc->busy = false;
7750
7751         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7752                     (unsigned long)intel_crtc);
7753 }
7754
7755 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7756                                 struct drm_file *file)
7757 {
7758         drm_i915_private_t *dev_priv = dev->dev_private;
7759         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7760         struct drm_mode_object *drmmode_obj;
7761         struct intel_crtc *crtc;
7762
7763         if (!dev_priv) {
7764                 DRM_ERROR("called with no initialization\n");
7765                 return -EINVAL;
7766         }
7767
7768         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7769                         DRM_MODE_OBJECT_CRTC);
7770
7771         if (!drmmode_obj) {
7772                 DRM_ERROR("no such CRTC id\n");
7773                 return -EINVAL;
7774         }
7775
7776         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7777         pipe_from_crtc_id->pipe = crtc->pipe;
7778
7779         return 0;
7780 }
7781
7782 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7783 {
7784         struct intel_encoder *encoder;
7785         int index_mask = 0;
7786         int entry = 0;
7787
7788         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7789                 if (type_mask & encoder->clone_mask)
7790                         index_mask |= (1 << entry);
7791                 entry++;
7792         }
7793
7794         return index_mask;
7795 }
7796
7797 static bool has_edp_a(struct drm_device *dev)
7798 {
7799         struct drm_i915_private *dev_priv = dev->dev_private;
7800
7801         if (!IS_MOBILE(dev))
7802                 return false;
7803
7804         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7805                 return false;
7806
7807         if (IS_GEN5(dev) &&
7808             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7809                 return false;
7810
7811         return true;
7812 }
7813
7814 static void intel_setup_outputs(struct drm_device *dev)
7815 {
7816         struct drm_i915_private *dev_priv = dev->dev_private;
7817         struct intel_encoder *encoder;
7818         bool dpd_is_edp = false;
7819         bool has_lvds;
7820
7821         has_lvds = intel_lvds_init(dev);
7822         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7823                 /* disable the panel fitter on everything but LVDS */
7824                 I915_WRITE(PFIT_CONTROL, 0);
7825         }
7826
7827         if (HAS_PCH_SPLIT(dev)) {
7828                 dpd_is_edp = intel_dpd_is_edp(dev);
7829
7830                 if (has_edp_a(dev))
7831                         intel_dp_init(dev, DP_A);
7832
7833                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7834                         intel_dp_init(dev, PCH_DP_D);
7835         }
7836
7837         intel_crt_init(dev);
7838
7839         if (HAS_PCH_SPLIT(dev)) {
7840                 int found;
7841
7842                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7843                         /* PCH SDVOB multiplex with HDMIB */
7844                         found = intel_sdvo_init(dev, PCH_SDVOB);
7845                         if (!found)
7846                                 intel_hdmi_init(dev, HDMIB);
7847                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7848                                 intel_dp_init(dev, PCH_DP_B);
7849                 }
7850
7851                 if (I915_READ(HDMIC) & PORT_DETECTED)
7852                         intel_hdmi_init(dev, HDMIC);
7853
7854                 if (I915_READ(HDMID) & PORT_DETECTED)
7855                         intel_hdmi_init(dev, HDMID);
7856
7857                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7858                         intel_dp_init(dev, PCH_DP_C);
7859
7860                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7861                         intel_dp_init(dev, PCH_DP_D);
7862
7863         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7864                 bool found = false;
7865
7866                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7867                         DRM_DEBUG_KMS("probing SDVOB\n");
7868                         found = intel_sdvo_init(dev, SDVOB);
7869                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7870                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7871                                 intel_hdmi_init(dev, SDVOB);
7872                         }
7873
7874                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7875                                 DRM_DEBUG_KMS("probing DP_B\n");
7876                                 intel_dp_init(dev, DP_B);
7877                         }
7878                 }
7879
7880                 /* Before G4X SDVOC doesn't have its own detect register */
7881
7882                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7883                         DRM_DEBUG_KMS("probing SDVOC\n");
7884                         found = intel_sdvo_init(dev, SDVOC);
7885                 }
7886
7887                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7888
7889                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7890                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7891                                 intel_hdmi_init(dev, SDVOC);
7892                         }
7893                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7894                                 DRM_DEBUG_KMS("probing DP_C\n");
7895                                 intel_dp_init(dev, DP_C);
7896                         }
7897                 }
7898
7899                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7900                     (I915_READ(DP_D) & DP_DETECTED)) {
7901                         DRM_DEBUG_KMS("probing DP_D\n");
7902                         intel_dp_init(dev, DP_D);
7903                 }
7904         } else if (IS_GEN2(dev))
7905                 intel_dvo_init(dev);
7906
7907         if (SUPPORTS_TV(dev))
7908                 intel_tv_init(dev);
7909
7910         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7911                 encoder->base.possible_crtcs = encoder->crtc_mask;
7912                 encoder->base.possible_clones =
7913                         intel_encoder_clones(dev, encoder->clone_mask);
7914         }
7915
7916         /* disable all the possible outputs/crtcs before entering KMS mode */
7917         drm_helper_disable_unused_functions(dev);
7918
7919         if (HAS_PCH_SPLIT(dev))
7920                 ironlake_init_pch_refclk(dev);
7921 }
7922
7923 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7924 {
7925         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7926
7927         drm_framebuffer_cleanup(fb);
7928         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7929
7930         kfree(intel_fb);
7931 }
7932
7933 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7934                                                 struct drm_file *file,
7935                                                 unsigned int *handle)
7936 {
7937         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7938         struct drm_i915_gem_object *obj = intel_fb->obj;
7939
7940         return drm_gem_handle_create(file, &obj->base, handle);
7941 }
7942
7943 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7944         .destroy = intel_user_framebuffer_destroy,
7945         .create_handle = intel_user_framebuffer_create_handle,
7946 };
7947
7948 int intel_framebuffer_init(struct drm_device *dev,
7949                            struct intel_framebuffer *intel_fb,
7950                            struct drm_mode_fb_cmd2 *mode_cmd,
7951                            struct drm_i915_gem_object *obj)
7952 {
7953         int ret;
7954
7955         if (obj->tiling_mode == I915_TILING_Y)
7956                 return -EINVAL;
7957
7958         if (mode_cmd->pitches[0] & 63)
7959                 return -EINVAL;
7960
7961         switch (mode_cmd->pixel_format) {
7962         case DRM_FORMAT_RGB332:
7963         case DRM_FORMAT_RGB565:
7964         case DRM_FORMAT_XRGB8888:
7965         case DRM_FORMAT_XBGR8888:
7966         case DRM_FORMAT_ARGB8888:
7967         case DRM_FORMAT_XRGB2101010:
7968         case DRM_FORMAT_ARGB2101010:
7969                 /* RGB formats are common across chipsets */
7970                 break;
7971         case DRM_FORMAT_YUYV:
7972         case DRM_FORMAT_UYVY:
7973         case DRM_FORMAT_YVYU:
7974         case DRM_FORMAT_VYUY:
7975                 break;
7976         default:
7977                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7978                                 mode_cmd->pixel_format);
7979                 return -EINVAL;
7980         }
7981
7982         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7983         if (ret) {
7984                 DRM_ERROR("framebuffer init failed %d\n", ret);
7985                 return ret;
7986         }
7987
7988         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7989         intel_fb->obj = obj;
7990         return 0;
7991 }
7992
7993 static struct drm_framebuffer *
7994 intel_user_framebuffer_create(struct drm_device *dev,
7995                               struct drm_file *filp,
7996                               struct drm_mode_fb_cmd2 *mode_cmd)
7997 {
7998         struct drm_i915_gem_object *obj;
7999
8000         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8001                                                 mode_cmd->handles[0]));
8002         if (&obj->base == NULL)
8003                 return ERR_PTR(-ENOENT);
8004
8005         return intel_framebuffer_create(dev, mode_cmd, obj);
8006 }
8007
8008 static const struct drm_mode_config_funcs intel_mode_funcs = {
8009         .fb_create = intel_user_framebuffer_create,
8010         .output_poll_changed = intel_fb_output_poll_changed,
8011 };
8012
8013 static struct drm_i915_gem_object *
8014 intel_alloc_context_page(struct drm_device *dev)
8015 {
8016         struct drm_i915_gem_object *ctx;
8017         int ret;
8018
8019         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8020
8021         ctx = i915_gem_alloc_object(dev, 4096);
8022         if (!ctx) {
8023                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8024                 return NULL;
8025         }
8026
8027         ret = i915_gem_object_pin(ctx, 4096, true);
8028         if (ret) {
8029                 DRM_ERROR("failed to pin power context: %d\n", ret);
8030                 goto err_unref;
8031         }
8032
8033         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8034         if (ret) {
8035                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8036                 goto err_unpin;
8037         }
8038
8039         return ctx;
8040
8041 err_unpin:
8042         i915_gem_object_unpin(ctx);
8043 err_unref:
8044         drm_gem_object_unreference(&ctx->base);
8045         mutex_unlock(&dev->struct_mutex);
8046         return NULL;
8047 }
8048
8049 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8050 {
8051         struct drm_i915_private *dev_priv = dev->dev_private;
8052         u16 rgvswctl;
8053
8054         rgvswctl = I915_READ16(MEMSWCTL);
8055         if (rgvswctl & MEMCTL_CMD_STS) {
8056                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8057                 return false; /* still busy with another command */
8058         }
8059
8060         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8061                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8062         I915_WRITE16(MEMSWCTL, rgvswctl);
8063         POSTING_READ16(MEMSWCTL);
8064
8065         rgvswctl |= MEMCTL_CMD_STS;
8066         I915_WRITE16(MEMSWCTL, rgvswctl);
8067
8068         return true;
8069 }
8070
8071 void ironlake_enable_drps(struct drm_device *dev)
8072 {
8073         struct drm_i915_private *dev_priv = dev->dev_private;
8074         u32 rgvmodectl = I915_READ(MEMMODECTL);
8075         u8 fmax, fmin, fstart, vstart;
8076
8077         /* Enable temp reporting */
8078         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8079         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8080
8081         /* 100ms RC evaluation intervals */
8082         I915_WRITE(RCUPEI, 100000);
8083         I915_WRITE(RCDNEI, 100000);
8084
8085         /* Set max/min thresholds to 90ms and 80ms respectively */
8086         I915_WRITE(RCBMAXAVG, 90000);
8087         I915_WRITE(RCBMINAVG, 80000);
8088
8089         I915_WRITE(MEMIHYST, 1);
8090
8091         /* Set up min, max, and cur for interrupt handling */
8092         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8093         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8094         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8095                 MEMMODE_FSTART_SHIFT;
8096
8097         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8098                 PXVFREQ_PX_SHIFT;
8099
8100         dev_priv->fmax = fmax; /* IPS callback will increase this */
8101         dev_priv->fstart = fstart;
8102
8103         dev_priv->max_delay = fstart;
8104         dev_priv->min_delay = fmin;
8105         dev_priv->cur_delay = fstart;
8106
8107         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8108                          fmax, fmin, fstart);
8109
8110         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8111
8112         /*
8113          * Interrupts will be enabled in ironlake_irq_postinstall
8114          */
8115
8116         I915_WRITE(VIDSTART, vstart);
8117         POSTING_READ(VIDSTART);
8118
8119         rgvmodectl |= MEMMODE_SWMODE_EN;
8120         I915_WRITE(MEMMODECTL, rgvmodectl);
8121
8122         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8123                 DRM_ERROR("stuck trying to change perf mode\n");
8124         msleep(1);
8125
8126         ironlake_set_drps(dev, fstart);
8127
8128         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8129                 I915_READ(0x112e0);
8130         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8131         dev_priv->last_count2 = I915_READ(0x112f4);
8132         getrawmonotonic(&dev_priv->last_time2);
8133 }
8134
8135 void ironlake_disable_drps(struct drm_device *dev)
8136 {
8137         struct drm_i915_private *dev_priv = dev->dev_private;
8138         u16 rgvswctl = I915_READ16(MEMSWCTL);
8139
8140         /* Ack interrupts, disable EFC interrupt */
8141         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8142         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8143         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8144         I915_WRITE(DEIIR, DE_PCU_EVENT);
8145         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8146
8147         /* Go back to the starting frequency */
8148         ironlake_set_drps(dev, dev_priv->fstart);
8149         msleep(1);
8150         rgvswctl |= MEMCTL_CMD_STS;
8151         I915_WRITE(MEMSWCTL, rgvswctl);
8152         msleep(1);
8153
8154 }
8155
8156 void gen6_set_rps(struct drm_device *dev, u8 val)
8157 {
8158         struct drm_i915_private *dev_priv = dev->dev_private;
8159         u32 swreq;
8160
8161         swreq = (val & 0x3ff) << 25;
8162         I915_WRITE(GEN6_RPNSWREQ, swreq);
8163 }
8164
8165 void gen6_disable_rps(struct drm_device *dev)
8166 {
8167         struct drm_i915_private *dev_priv = dev->dev_private;
8168
8169         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8170         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8171         I915_WRITE(GEN6_PMIER, 0);
8172         /* Complete PM interrupt masking here doesn't race with the rps work
8173          * item again unmasking PM interrupts because that is using a different
8174          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8175          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8176
8177         spin_lock_irq(&dev_priv->rps_lock);
8178         dev_priv->pm_iir = 0;
8179         spin_unlock_irq(&dev_priv->rps_lock);
8180
8181         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8182 }
8183
8184 static unsigned long intel_pxfreq(u32 vidfreq)
8185 {
8186         unsigned long freq;
8187         int div = (vidfreq & 0x3f0000) >> 16;
8188         int post = (vidfreq & 0x3000) >> 12;
8189         int pre = (vidfreq & 0x7);
8190
8191         if (!pre)
8192                 return 0;
8193
8194         freq = ((div * 133333) / ((1<<post) * pre));
8195
8196         return freq;
8197 }
8198
8199 void intel_init_emon(struct drm_device *dev)
8200 {
8201         struct drm_i915_private *dev_priv = dev->dev_private;
8202         u32 lcfuse;
8203         u8 pxw[16];
8204         int i;
8205
8206         /* Disable to program */
8207         I915_WRITE(ECR, 0);
8208         POSTING_READ(ECR);
8209
8210         /* Program energy weights for various events */
8211         I915_WRITE(SDEW, 0x15040d00);
8212         I915_WRITE(CSIEW0, 0x007f0000);
8213         I915_WRITE(CSIEW1, 0x1e220004);
8214         I915_WRITE(CSIEW2, 0x04000004);
8215
8216         for (i = 0; i < 5; i++)
8217                 I915_WRITE(PEW + (i * 4), 0);
8218         for (i = 0; i < 3; i++)
8219                 I915_WRITE(DEW + (i * 4), 0);
8220
8221         /* Program P-state weights to account for frequency power adjustment */
8222         for (i = 0; i < 16; i++) {
8223                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8224                 unsigned long freq = intel_pxfreq(pxvidfreq);
8225                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8226                         PXVFREQ_PX_SHIFT;
8227                 unsigned long val;
8228
8229                 val = vid * vid;
8230                 val *= (freq / 1000);
8231                 val *= 255;
8232                 val /= (127*127*900);
8233                 if (val > 0xff)
8234                         DRM_ERROR("bad pxval: %ld\n", val);
8235                 pxw[i] = val;
8236         }
8237         /* Render standby states get 0 weight */
8238         pxw[14] = 0;
8239         pxw[15] = 0;
8240
8241         for (i = 0; i < 4; i++) {
8242                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8243                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8244                 I915_WRITE(PXW + (i * 4), val);
8245         }
8246
8247         /* Adjust magic regs to magic values (more experimental results) */
8248         I915_WRITE(OGW0, 0);
8249         I915_WRITE(OGW1, 0);
8250         I915_WRITE(EG0, 0x00007f00);
8251         I915_WRITE(EG1, 0x0000000e);
8252         I915_WRITE(EG2, 0x000e0000);
8253         I915_WRITE(EG3, 0x68000300);
8254         I915_WRITE(EG4, 0x42000000);
8255         I915_WRITE(EG5, 0x00140031);
8256         I915_WRITE(EG6, 0);
8257         I915_WRITE(EG7, 0);
8258
8259         for (i = 0; i < 8; i++)
8260                 I915_WRITE(PXWL + (i * 4), 0);
8261
8262         /* Enable PMON + select events */
8263         I915_WRITE(ECR, 0x80000019);
8264
8265         lcfuse = I915_READ(LCFUSE02);
8266
8267         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8268 }
8269
8270 static int intel_enable_rc6(struct drm_device *dev)
8271 {
8272         /*
8273          * Respect the kernel parameter if it is set
8274          */
8275         if (i915_enable_rc6 >= 0)
8276                 return i915_enable_rc6;
8277
8278         /*
8279          * Disable RC6 on Ironlake
8280          */
8281         if (INTEL_INFO(dev)->gen == 5)
8282                 return 0;
8283
8284         /*
8285          * Disable rc6 on Sandybridge
8286          */
8287         if (INTEL_INFO(dev)->gen == 6) {
8288                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8289                 return INTEL_RC6_ENABLE;
8290         }
8291         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8292         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8293 }
8294
8295 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8296 {
8297         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8298         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8299         u32 pcu_mbox, rc6_mask = 0;
8300         u32 gtfifodbg;
8301         int cur_freq, min_freq, max_freq;
8302         int rc6_mode;
8303         int i;
8304
8305         /* Here begins a magic sequence of register writes to enable
8306          * auto-downclocking.
8307          *
8308          * Perhaps there might be some value in exposing these to
8309          * userspace...
8310          */
8311         I915_WRITE(GEN6_RC_STATE, 0);
8312         mutex_lock(&dev_priv->dev->struct_mutex);
8313
8314         /* Clear the DBG now so we don't confuse earlier errors */
8315         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8316                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8317                 I915_WRITE(GTFIFODBG, gtfifodbg);
8318         }
8319
8320         gen6_gt_force_wake_get(dev_priv);
8321
8322         /* disable the counters and set deterministic thresholds */
8323         I915_WRITE(GEN6_RC_CONTROL, 0);
8324
8325         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8326         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8327         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8328         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8329         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8330
8331         for (i = 0; i < I915_NUM_RINGS; i++)
8332                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8333
8334         I915_WRITE(GEN6_RC_SLEEP, 0);
8335         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8336         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8337         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8338         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8339
8340         rc6_mode = intel_enable_rc6(dev_priv->dev);
8341         if (rc6_mode & INTEL_RC6_ENABLE)
8342                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8343
8344         if (rc6_mode & INTEL_RC6p_ENABLE)
8345                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8346
8347         if (rc6_mode & INTEL_RC6pp_ENABLE)
8348                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8349
8350         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8351                         (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8352                         (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8353                         (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8354
8355         I915_WRITE(GEN6_RC_CONTROL,
8356                    rc6_mask |
8357                    GEN6_RC_CTL_EI_MODE(1) |
8358                    GEN6_RC_CTL_HW_ENABLE);
8359
8360         I915_WRITE(GEN6_RPNSWREQ,
8361                    GEN6_FREQUENCY(10) |
8362                    GEN6_OFFSET(0) |
8363                    GEN6_AGGRESSIVE_TURBO);
8364         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8365                    GEN6_FREQUENCY(12));
8366
8367         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8368         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8369                    18 << 24 |
8370                    6 << 16);
8371         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8372         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
8373         I915_WRITE(GEN6_RP_UP_EI, 100000);
8374         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8375         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8376         I915_WRITE(GEN6_RP_CONTROL,
8377                    GEN6_RP_MEDIA_TURBO |
8378                    GEN6_RP_MEDIA_HW_MODE |
8379                    GEN6_RP_MEDIA_IS_GFX |
8380                    GEN6_RP_ENABLE |
8381                    GEN6_RP_UP_BUSY_AVG |
8382                    GEN6_RP_DOWN_IDLE_CONT);
8383
8384         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8385                      500))
8386                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8387
8388         I915_WRITE(GEN6_PCODE_DATA, 0);
8389         I915_WRITE(GEN6_PCODE_MAILBOX,
8390                    GEN6_PCODE_READY |
8391                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8392         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8393                      500))
8394                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8395
8396         min_freq = (rp_state_cap & 0xff0000) >> 16;
8397         max_freq = rp_state_cap & 0xff;
8398         cur_freq = (gt_perf_status & 0xff00) >> 8;
8399
8400         /* Check for overclock support */
8401         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8402                      500))
8403                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8404         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8405         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8406         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8407                      500))
8408                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8409         if (pcu_mbox & (1<<31)) { /* OC supported */
8410                 max_freq = pcu_mbox & 0xff;
8411                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8412         }
8413
8414         /* In units of 100MHz */
8415         dev_priv->max_delay = max_freq;
8416         dev_priv->min_delay = min_freq;
8417         dev_priv->cur_delay = cur_freq;
8418
8419         /* requires MSI enabled */
8420         I915_WRITE(GEN6_PMIER,
8421                    GEN6_PM_MBOX_EVENT |
8422                    GEN6_PM_THERMAL_EVENT |
8423                    GEN6_PM_RP_DOWN_TIMEOUT |
8424                    GEN6_PM_RP_UP_THRESHOLD |
8425                    GEN6_PM_RP_DOWN_THRESHOLD |
8426                    GEN6_PM_RP_UP_EI_EXPIRED |
8427                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8428         spin_lock_irq(&dev_priv->rps_lock);
8429         WARN_ON(dev_priv->pm_iir != 0);
8430         I915_WRITE(GEN6_PMIMR, 0);
8431         spin_unlock_irq(&dev_priv->rps_lock);
8432         /* enable all PM interrupts */
8433         I915_WRITE(GEN6_PMINTRMSK, 0);
8434
8435         gen6_gt_force_wake_put(dev_priv);
8436         mutex_unlock(&dev_priv->dev->struct_mutex);
8437 }
8438
8439 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8440 {
8441         int min_freq = 15;
8442         int gpu_freq, ia_freq, max_ia_freq;
8443         int scaling_factor = 180;
8444
8445         max_ia_freq = cpufreq_quick_get_max(0);
8446         /*
8447          * Default to measured freq if none found, PCU will ensure we don't go
8448          * over
8449          */
8450         if (!max_ia_freq)
8451                 max_ia_freq = tsc_khz;
8452
8453         /* Convert from kHz to MHz */
8454         max_ia_freq /= 1000;
8455
8456         mutex_lock(&dev_priv->dev->struct_mutex);
8457
8458         /*
8459          * For each potential GPU frequency, load a ring frequency we'd like
8460          * to use for memory access.  We do this by specifying the IA frequency
8461          * the PCU should use as a reference to determine the ring frequency.
8462          */
8463         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8464              gpu_freq--) {
8465                 int diff = dev_priv->max_delay - gpu_freq;
8466
8467                 /*
8468                  * For GPU frequencies less than 750MHz, just use the lowest
8469                  * ring freq.
8470                  */
8471                 if (gpu_freq < min_freq)
8472                         ia_freq = 800;
8473                 else
8474                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8475                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8476
8477                 I915_WRITE(GEN6_PCODE_DATA,
8478                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8479                            gpu_freq);
8480                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8481                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8482                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8483                               GEN6_PCODE_READY) == 0, 10)) {
8484                         DRM_ERROR("pcode write of freq table timed out\n");
8485                         continue;
8486                 }
8487         }
8488
8489         mutex_unlock(&dev_priv->dev->struct_mutex);
8490 }
8491
8492 static void ironlake_init_clock_gating(struct drm_device *dev)
8493 {
8494         struct drm_i915_private *dev_priv = dev->dev_private;
8495         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8496
8497         /* Required for FBC */
8498         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8499                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8500                 DPFDUNIT_CLOCK_GATE_DISABLE;
8501         /* Required for CxSR */
8502         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8503
8504         I915_WRITE(PCH_3DCGDIS0,
8505                    MARIUNIT_CLOCK_GATE_DISABLE |
8506                    SVSMUNIT_CLOCK_GATE_DISABLE);
8507         I915_WRITE(PCH_3DCGDIS1,
8508                    VFMUNIT_CLOCK_GATE_DISABLE);
8509
8510         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8511
8512         /*
8513          * According to the spec the following bits should be set in
8514          * order to enable memory self-refresh
8515          * The bit 22/21 of 0x42004
8516          * The bit 5 of 0x42020
8517          * The bit 15 of 0x45000
8518          */
8519         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8520                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8521                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8522         I915_WRITE(ILK_DSPCLK_GATE,
8523                    (I915_READ(ILK_DSPCLK_GATE) |
8524                     ILK_DPARB_CLK_GATE));
8525         I915_WRITE(DISP_ARB_CTL,
8526                    (I915_READ(DISP_ARB_CTL) |
8527                     DISP_FBC_WM_DIS));
8528         I915_WRITE(WM3_LP_ILK, 0);
8529         I915_WRITE(WM2_LP_ILK, 0);
8530         I915_WRITE(WM1_LP_ILK, 0);
8531
8532         /*
8533          * Based on the document from hardware guys the following bits
8534          * should be set unconditionally in order to enable FBC.
8535          * The bit 22 of 0x42000
8536          * The bit 22 of 0x42004
8537          * The bit 7,8,9 of 0x42020.
8538          */
8539         if (IS_IRONLAKE_M(dev)) {
8540                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8541                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8542                            ILK_FBCQ_DIS);
8543                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8544                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8545                            ILK_DPARB_GATE);
8546                 I915_WRITE(ILK_DSPCLK_GATE,
8547                            I915_READ(ILK_DSPCLK_GATE) |
8548                            ILK_DPFC_DIS1 |
8549                            ILK_DPFC_DIS2 |
8550                            ILK_CLK_FBC);
8551         }
8552
8553         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8554                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8555                    ILK_ELPIN_409_SELECT);
8556         I915_WRITE(_3D_CHICKEN2,
8557                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8558                    _3D_CHICKEN2_WM_READ_PIPELINED);
8559 }
8560
8561 static void gen6_init_clock_gating(struct drm_device *dev)
8562 {
8563         struct drm_i915_private *dev_priv = dev->dev_private;
8564         int pipe;
8565         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8566
8567         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8568
8569         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8570                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8571                    ILK_ELPIN_409_SELECT);
8572
8573         I915_WRITE(WM3_LP_ILK, 0);
8574         I915_WRITE(WM2_LP_ILK, 0);
8575         I915_WRITE(WM1_LP_ILK, 0);
8576
8577         I915_WRITE(GEN6_UCGCTL1,
8578                    I915_READ(GEN6_UCGCTL1) |
8579                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
8580
8581         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8582          * gating disable must be set.  Failure to set it results in
8583          * flickering pixels due to Z write ordering failures after
8584          * some amount of runtime in the Mesa "fire" demo, and Unigine
8585          * Sanctuary and Tropics, and apparently anything else with
8586          * alpha test or pixel discard.
8587          *
8588          * According to the spec, bit 11 (RCCUNIT) must also be set,
8589          * but we didn't debug actual testcases to find it out.
8590          */
8591         I915_WRITE(GEN6_UCGCTL2,
8592                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8593                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8594
8595         /*
8596          * According to the spec the following bits should be
8597          * set in order to enable memory self-refresh and fbc:
8598          * The bit21 and bit22 of 0x42000
8599          * The bit21 and bit22 of 0x42004
8600          * The bit5 and bit7 of 0x42020
8601          * The bit14 of 0x70180
8602          * The bit14 of 0x71180
8603          */
8604         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8605                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8606                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8607         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8608                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8609                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8610         I915_WRITE(ILK_DSPCLK_GATE,
8611                    I915_READ(ILK_DSPCLK_GATE) |
8612                    ILK_DPARB_CLK_GATE  |
8613                    ILK_DPFD_CLK_GATE);
8614
8615         for_each_pipe(pipe) {
8616                 I915_WRITE(DSPCNTR(pipe),
8617                            I915_READ(DSPCNTR(pipe)) |
8618                            DISPPLANE_TRICKLE_FEED_DISABLE);
8619                 intel_flush_display_plane(dev_priv, pipe);
8620         }
8621 }
8622
8623 static void ivybridge_init_clock_gating(struct drm_device *dev)
8624 {
8625         struct drm_i915_private *dev_priv = dev->dev_private;
8626         int pipe;
8627         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8628
8629         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8630
8631         I915_WRITE(WM3_LP_ILK, 0);
8632         I915_WRITE(WM2_LP_ILK, 0);
8633         I915_WRITE(WM1_LP_ILK, 0);
8634
8635         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8636          * This implements the WaDisableRCZUnitClockGating workaround.
8637          */
8638         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8639
8640         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8641
8642         I915_WRITE(IVB_CHICKEN3,
8643                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8644                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8645
8646         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8647         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8648                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8649
8650         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8651         I915_WRITE(GEN7_L3CNTLREG1,
8652                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8653         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8654                         GEN7_WA_L3_CHICKEN_MODE);
8655
8656         /* This is required by WaCatErrorRejectionIssue */
8657         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8658                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8659                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8660
8661         for_each_pipe(pipe) {
8662                 I915_WRITE(DSPCNTR(pipe),
8663                            I915_READ(DSPCNTR(pipe)) |
8664                            DISPPLANE_TRICKLE_FEED_DISABLE);
8665                 intel_flush_display_plane(dev_priv, pipe);
8666         }
8667 }
8668
8669 static void g4x_init_clock_gating(struct drm_device *dev)
8670 {
8671         struct drm_i915_private *dev_priv = dev->dev_private;
8672         uint32_t dspclk_gate;
8673
8674         I915_WRITE(RENCLK_GATE_D1, 0);
8675         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8676                    GS_UNIT_CLOCK_GATE_DISABLE |
8677                    CL_UNIT_CLOCK_GATE_DISABLE);
8678         I915_WRITE(RAMCLK_GATE_D, 0);
8679         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8680                 OVRUNIT_CLOCK_GATE_DISABLE |
8681                 OVCUNIT_CLOCK_GATE_DISABLE;
8682         if (IS_GM45(dev))
8683                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8684         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8685 }
8686
8687 static void crestline_init_clock_gating(struct drm_device *dev)
8688 {
8689         struct drm_i915_private *dev_priv = dev->dev_private;
8690
8691         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8692         I915_WRITE(RENCLK_GATE_D2, 0);
8693         I915_WRITE(DSPCLK_GATE_D, 0);
8694         I915_WRITE(RAMCLK_GATE_D, 0);
8695         I915_WRITE16(DEUC, 0);
8696 }
8697
8698 static void broadwater_init_clock_gating(struct drm_device *dev)
8699 {
8700         struct drm_i915_private *dev_priv = dev->dev_private;
8701
8702         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8703                    I965_RCC_CLOCK_GATE_DISABLE |
8704                    I965_RCPB_CLOCK_GATE_DISABLE |
8705                    I965_ISC_CLOCK_GATE_DISABLE |
8706                    I965_FBC_CLOCK_GATE_DISABLE);
8707         I915_WRITE(RENCLK_GATE_D2, 0);
8708 }
8709
8710 static void gen3_init_clock_gating(struct drm_device *dev)
8711 {
8712         struct drm_i915_private *dev_priv = dev->dev_private;
8713         u32 dstate = I915_READ(D_STATE);
8714
8715         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8716                 DSTATE_DOT_CLOCK_GATING;
8717         I915_WRITE(D_STATE, dstate);
8718 }
8719
8720 static void i85x_init_clock_gating(struct drm_device *dev)
8721 {
8722         struct drm_i915_private *dev_priv = dev->dev_private;
8723
8724         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8725 }
8726
8727 static void i830_init_clock_gating(struct drm_device *dev)
8728 {
8729         struct drm_i915_private *dev_priv = dev->dev_private;
8730
8731         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8732 }
8733
8734 static void ibx_init_clock_gating(struct drm_device *dev)
8735 {
8736         struct drm_i915_private *dev_priv = dev->dev_private;
8737
8738         /*
8739          * On Ibex Peak and Cougar Point, we need to disable clock
8740          * gating for the panel power sequencer or it will fail to
8741          * start up when no ports are active.
8742          */
8743         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8744 }
8745
8746 static void cpt_init_clock_gating(struct drm_device *dev)
8747 {
8748         struct drm_i915_private *dev_priv = dev->dev_private;
8749         int pipe;
8750
8751         /*
8752          * On Ibex Peak and Cougar Point, we need to disable clock
8753          * gating for the panel power sequencer or it will fail to
8754          * start up when no ports are active.
8755          */
8756         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8757         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8758                    DPLS_EDP_PPS_FIX_DIS);
8759         /* Without this, mode sets may fail silently on FDI */
8760         for_each_pipe(pipe)
8761                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8762 }
8763
8764 static void ironlake_teardown_rc6(struct drm_device *dev)
8765 {
8766         struct drm_i915_private *dev_priv = dev->dev_private;
8767
8768         if (dev_priv->renderctx) {
8769                 i915_gem_object_unpin(dev_priv->renderctx);
8770                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8771                 dev_priv->renderctx = NULL;
8772         }
8773
8774         if (dev_priv->pwrctx) {
8775                 i915_gem_object_unpin(dev_priv->pwrctx);
8776                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8777                 dev_priv->pwrctx = NULL;
8778         }
8779 }
8780
8781 static void ironlake_disable_rc6(struct drm_device *dev)
8782 {
8783         struct drm_i915_private *dev_priv = dev->dev_private;
8784
8785         if (I915_READ(PWRCTXA)) {
8786                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8787                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8788                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8789                          50);
8790
8791                 I915_WRITE(PWRCTXA, 0);
8792                 POSTING_READ(PWRCTXA);
8793
8794                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8795                 POSTING_READ(RSTDBYCTL);
8796         }
8797
8798         ironlake_teardown_rc6(dev);
8799 }
8800
8801 static int ironlake_setup_rc6(struct drm_device *dev)
8802 {
8803         struct drm_i915_private *dev_priv = dev->dev_private;
8804
8805         if (dev_priv->renderctx == NULL)
8806                 dev_priv->renderctx = intel_alloc_context_page(dev);
8807         if (!dev_priv->renderctx)
8808                 return -ENOMEM;
8809
8810         if (dev_priv->pwrctx == NULL)
8811                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8812         if (!dev_priv->pwrctx) {
8813                 ironlake_teardown_rc6(dev);
8814                 return -ENOMEM;
8815         }
8816
8817         return 0;
8818 }
8819
8820 void ironlake_enable_rc6(struct drm_device *dev)
8821 {
8822         struct drm_i915_private *dev_priv = dev->dev_private;
8823         int ret;
8824
8825         /* rc6 disabled by default due to repeated reports of hanging during
8826          * boot and resume.
8827          */
8828         if (!intel_enable_rc6(dev))
8829                 return;
8830
8831         mutex_lock(&dev->struct_mutex);
8832         ret = ironlake_setup_rc6(dev);
8833         if (ret) {
8834                 mutex_unlock(&dev->struct_mutex);
8835                 return;
8836         }
8837
8838         /*
8839          * GPU can automatically power down the render unit if given a page
8840          * to save state.
8841          */
8842         ret = BEGIN_LP_RING(6);
8843         if (ret) {
8844                 ironlake_teardown_rc6(dev);
8845                 mutex_unlock(&dev->struct_mutex);
8846                 return;
8847         }
8848
8849         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8850         OUT_RING(MI_SET_CONTEXT);
8851         OUT_RING(dev_priv->renderctx->gtt_offset |
8852                  MI_MM_SPACE_GTT |
8853                  MI_SAVE_EXT_STATE_EN |
8854                  MI_RESTORE_EXT_STATE_EN |
8855                  MI_RESTORE_INHIBIT);
8856         OUT_RING(MI_SUSPEND_FLUSH);
8857         OUT_RING(MI_NOOP);
8858         OUT_RING(MI_FLUSH);
8859         ADVANCE_LP_RING();
8860
8861         /*
8862          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8863          * does an implicit flush, combined with MI_FLUSH above, it should be
8864          * safe to assume that renderctx is valid
8865          */
8866         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8867         if (ret) {
8868                 DRM_ERROR("failed to enable ironlake power power savings\n");
8869                 ironlake_teardown_rc6(dev);
8870                 mutex_unlock(&dev->struct_mutex);
8871                 return;
8872         }
8873
8874         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8875         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8876         mutex_unlock(&dev->struct_mutex);
8877 }
8878
8879 void intel_init_clock_gating(struct drm_device *dev)
8880 {
8881         struct drm_i915_private *dev_priv = dev->dev_private;
8882
8883         dev_priv->display.init_clock_gating(dev);
8884
8885         if (dev_priv->display.init_pch_clock_gating)
8886                 dev_priv->display.init_pch_clock_gating(dev);
8887 }
8888
8889 /* Set up chip specific display functions */
8890 static void intel_init_display(struct drm_device *dev)
8891 {
8892         struct drm_i915_private *dev_priv = dev->dev_private;
8893
8894         /* We always want a DPMS function */
8895         if (HAS_PCH_SPLIT(dev)) {
8896                 dev_priv->display.dpms = ironlake_crtc_dpms;
8897                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8898                 dev_priv->display.update_plane = ironlake_update_plane;
8899         } else {
8900                 dev_priv->display.dpms = i9xx_crtc_dpms;
8901                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8902                 dev_priv->display.update_plane = i9xx_update_plane;
8903         }
8904
8905         if (I915_HAS_FBC(dev)) {
8906                 if (HAS_PCH_SPLIT(dev)) {
8907                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8908                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8909                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8910                 } else if (IS_GM45(dev)) {
8911                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8912                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8913                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8914                 } else if (IS_CRESTLINE(dev)) {
8915                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8916                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8917                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8918                 }
8919                 /* 855GM needs testing */
8920         }
8921
8922         /* Returns the core display clock speed */
8923         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8924                 dev_priv->display.get_display_clock_speed =
8925                         i945_get_display_clock_speed;
8926         else if (IS_I915G(dev))
8927                 dev_priv->display.get_display_clock_speed =
8928                         i915_get_display_clock_speed;
8929         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8930                 dev_priv->display.get_display_clock_speed =
8931                         i9xx_misc_get_display_clock_speed;
8932         else if (IS_I915GM(dev))
8933                 dev_priv->display.get_display_clock_speed =
8934                         i915gm_get_display_clock_speed;
8935         else if (IS_I865G(dev))
8936                 dev_priv->display.get_display_clock_speed =
8937                         i865_get_display_clock_speed;
8938         else if (IS_I85X(dev))
8939                 dev_priv->display.get_display_clock_speed =
8940                         i855_get_display_clock_speed;
8941         else /* 852, 830 */
8942                 dev_priv->display.get_display_clock_speed =
8943                         i830_get_display_clock_speed;
8944
8945         /* For FIFO watermark updates */
8946         if (HAS_PCH_SPLIT(dev)) {
8947                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8948                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8949
8950                 /* IVB configs may use multi-threaded forcewake */
8951                 if (IS_IVYBRIDGE(dev)) {
8952                         u32     ecobus;
8953
8954                         /* A small trick here - if the bios hasn't configured MT forcewake,
8955                          * and if the device is in RC6, then force_wake_mt_get will not wake
8956                          * the device and the ECOBUS read will return zero. Which will be
8957                          * (correctly) interpreted by the test below as MT forcewake being
8958                          * disabled.
8959                          */
8960                         mutex_lock(&dev->struct_mutex);
8961                         __gen6_gt_force_wake_mt_get(dev_priv);
8962                         ecobus = I915_READ_NOTRACE(ECOBUS);
8963                         __gen6_gt_force_wake_mt_put(dev_priv);
8964                         mutex_unlock(&dev->struct_mutex);
8965
8966                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8967                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8968                                 dev_priv->display.force_wake_get =
8969                                         __gen6_gt_force_wake_mt_get;
8970                                 dev_priv->display.force_wake_put =
8971                                         __gen6_gt_force_wake_mt_put;
8972                         }
8973                 }
8974
8975                 if (HAS_PCH_IBX(dev))
8976                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8977                 else if (HAS_PCH_CPT(dev))
8978                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8979
8980                 if (IS_GEN5(dev)) {
8981                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8982                                 dev_priv->display.update_wm = ironlake_update_wm;
8983                         else {
8984                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8985                                               "Disable CxSR\n");
8986                                 dev_priv->display.update_wm = NULL;
8987                         }
8988                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8989                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8990                         dev_priv->display.write_eld = ironlake_write_eld;
8991                 } else if (IS_GEN6(dev)) {
8992                         if (SNB_READ_WM0_LATENCY()) {
8993                                 dev_priv->display.update_wm = sandybridge_update_wm;
8994                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8995                         } else {
8996                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8997                                               "Disable CxSR\n");
8998                                 dev_priv->display.update_wm = NULL;
8999                         }
9000                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9001                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9002                         dev_priv->display.write_eld = ironlake_write_eld;
9003                 } else if (IS_IVYBRIDGE(dev)) {
9004                         /* FIXME: detect B0+ stepping and use auto training */
9005                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9006                         if (SNB_READ_WM0_LATENCY()) {
9007                                 dev_priv->display.update_wm = sandybridge_update_wm;
9008                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9009                         } else {
9010                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9011                                               "Disable CxSR\n");
9012                                 dev_priv->display.update_wm = NULL;
9013                         }
9014                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9015                         dev_priv->display.write_eld = ironlake_write_eld;
9016                 } else
9017                         dev_priv->display.update_wm = NULL;
9018         } else if (IS_PINEVIEW(dev)) {
9019                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9020                                             dev_priv->is_ddr3,
9021                                             dev_priv->fsb_freq,
9022                                             dev_priv->mem_freq)) {
9023                         DRM_INFO("failed to find known CxSR latency "
9024                                  "(found ddr%s fsb freq %d, mem freq %d), "
9025                                  "disabling CxSR\n",
9026                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9027                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9028                         /* Disable CxSR and never update its watermark again */
9029                         pineview_disable_cxsr(dev);
9030                         dev_priv->display.update_wm = NULL;
9031                 } else
9032                         dev_priv->display.update_wm = pineview_update_wm;
9033                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9034         } else if (IS_G4X(dev)) {
9035                 dev_priv->display.write_eld = g4x_write_eld;
9036                 dev_priv->display.update_wm = g4x_update_wm;
9037                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9038         } else if (IS_GEN4(dev)) {
9039                 dev_priv->display.update_wm = i965_update_wm;
9040                 if (IS_CRESTLINE(dev))
9041                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9042                 else if (IS_BROADWATER(dev))
9043                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9044         } else if (IS_GEN3(dev)) {
9045                 dev_priv->display.update_wm = i9xx_update_wm;
9046                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9047                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9048         } else if (IS_I865G(dev)) {
9049                 dev_priv->display.update_wm = i830_update_wm;
9050                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9051                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9052         } else if (IS_I85X(dev)) {
9053                 dev_priv->display.update_wm = i9xx_update_wm;
9054                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9055                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9056         } else {
9057                 dev_priv->display.update_wm = i830_update_wm;
9058                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9059                 if (IS_845G(dev))
9060                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9061                 else
9062                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9063         }
9064
9065         /* Default just returns -ENODEV to indicate unsupported */
9066         dev_priv->display.queue_flip = intel_default_queue_flip;
9067
9068         switch (INTEL_INFO(dev)->gen) {
9069         case 2:
9070                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9071                 break;
9072
9073         case 3:
9074                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9075                 break;
9076
9077         case 4:
9078         case 5:
9079                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9080                 break;
9081
9082         case 6:
9083                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9084                 break;
9085         case 7:
9086                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9087                 break;
9088         }
9089 }
9090
9091 /*
9092  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9093  * resume, or other times.  This quirk makes sure that's the case for
9094  * affected systems.
9095  */
9096 static void quirk_pipea_force(struct drm_device *dev)
9097 {
9098         struct drm_i915_private *dev_priv = dev->dev_private;
9099
9100         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9101         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9102 }
9103
9104 /*
9105  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9106  */
9107 static void quirk_ssc_force_disable(struct drm_device *dev)
9108 {
9109         struct drm_i915_private *dev_priv = dev->dev_private;
9110         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9111 }
9112
9113 struct intel_quirk {
9114         int device;
9115         int subsystem_vendor;
9116         int subsystem_device;
9117         void (*hook)(struct drm_device *dev);
9118 };
9119
9120 struct intel_quirk intel_quirks[] = {
9121         /* HP Mini needs pipe A force quirk (LP: #322104) */
9122         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9123
9124         /* Thinkpad R31 needs pipe A force quirk */
9125         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9126         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9127         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9128
9129         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9130         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9131         /* ThinkPad X40 needs pipe A force quirk */
9132
9133         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9134         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9135
9136         /* 855 & before need to leave pipe A & dpll A up */
9137         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9138         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9139
9140         /* Lenovo U160 cannot use SSC on LVDS */
9141         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9142
9143         /* Sony Vaio Y cannot use SSC on LVDS */
9144         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9145 };
9146
9147 static void intel_init_quirks(struct drm_device *dev)
9148 {
9149         struct pci_dev *d = dev->pdev;
9150         int i;
9151
9152         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9153                 struct intel_quirk *q = &intel_quirks[i];
9154
9155                 if (d->device == q->device &&
9156                     (d->subsystem_vendor == q->subsystem_vendor ||
9157                      q->subsystem_vendor == PCI_ANY_ID) &&
9158                     (d->subsystem_device == q->subsystem_device ||
9159                      q->subsystem_device == PCI_ANY_ID))
9160                         q->hook(dev);
9161         }
9162 }
9163
9164 /* Disable the VGA plane that we never use */
9165 static void i915_disable_vga(struct drm_device *dev)
9166 {
9167         struct drm_i915_private *dev_priv = dev->dev_private;
9168         u8 sr1;
9169         u32 vga_reg;
9170
9171         if (HAS_PCH_SPLIT(dev))
9172                 vga_reg = CPU_VGACNTRL;
9173         else
9174                 vga_reg = VGACNTRL;
9175
9176         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9177         outb(1, VGA_SR_INDEX);
9178         sr1 = inb(VGA_SR_DATA);
9179         outb(sr1 | 1<<5, VGA_SR_DATA);
9180         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9181         udelay(300);
9182
9183         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9184         POSTING_READ(vga_reg);
9185 }
9186
9187 void intel_modeset_init(struct drm_device *dev)
9188 {
9189         struct drm_i915_private *dev_priv = dev->dev_private;
9190         int i, ret;
9191
9192         drm_mode_config_init(dev);
9193
9194         dev->mode_config.min_width = 0;
9195         dev->mode_config.min_height = 0;
9196
9197         dev->mode_config.preferred_depth = 24;
9198         dev->mode_config.prefer_shadow = 1;
9199
9200         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9201
9202         intel_init_quirks(dev);
9203
9204         intel_init_display(dev);
9205
9206         if (IS_GEN2(dev)) {
9207                 dev->mode_config.max_width = 2048;
9208                 dev->mode_config.max_height = 2048;
9209         } else if (IS_GEN3(dev)) {
9210                 dev->mode_config.max_width = 4096;
9211                 dev->mode_config.max_height = 4096;
9212         } else {
9213                 dev->mode_config.max_width = 8192;
9214                 dev->mode_config.max_height = 8192;
9215         }
9216         dev->mode_config.fb_base = dev->agp->base;
9217
9218         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9219                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9220
9221         for (i = 0; i < dev_priv->num_pipe; i++) {
9222                 intel_crtc_init(dev, i);
9223                 ret = intel_plane_init(dev, i);
9224                 if (ret)
9225                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9226         }
9227
9228         /* Just disable it once at startup */
9229         i915_disable_vga(dev);
9230         intel_setup_outputs(dev);
9231
9232         intel_init_clock_gating(dev);
9233
9234         if (IS_IRONLAKE_M(dev)) {
9235                 ironlake_enable_drps(dev);
9236                 intel_init_emon(dev);
9237         }
9238
9239         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9240                 gen6_enable_rps(dev_priv);
9241                 gen6_update_ring_freq(dev_priv);
9242         }
9243
9244         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9245         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9246                     (unsigned long)dev);
9247 }
9248
9249 void intel_modeset_gem_init(struct drm_device *dev)
9250 {
9251         if (IS_IRONLAKE_M(dev))
9252                 ironlake_enable_rc6(dev);
9253
9254         intel_setup_overlay(dev);
9255 }
9256
9257 void intel_modeset_cleanup(struct drm_device *dev)
9258 {
9259         struct drm_i915_private *dev_priv = dev->dev_private;
9260         struct drm_crtc *crtc;
9261         struct intel_crtc *intel_crtc;
9262
9263         drm_kms_helper_poll_fini(dev);
9264         mutex_lock(&dev->struct_mutex);
9265
9266         intel_unregister_dsm_handler();
9267
9268
9269         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9270                 /* Skip inactive CRTCs */
9271                 if (!crtc->fb)
9272                         continue;
9273
9274                 intel_crtc = to_intel_crtc(crtc);
9275                 intel_increase_pllclock(crtc);
9276         }
9277
9278         intel_disable_fbc(dev);
9279
9280         if (IS_IRONLAKE_M(dev))
9281                 ironlake_disable_drps(dev);
9282         if (IS_GEN6(dev) || IS_GEN7(dev))
9283                 gen6_disable_rps(dev);
9284
9285         if (IS_IRONLAKE_M(dev))
9286                 ironlake_disable_rc6(dev);
9287
9288         mutex_unlock(&dev->struct_mutex);
9289
9290         /* Disable the irq before mode object teardown, for the irq might
9291          * enqueue unpin/hotplug work. */
9292         drm_irq_uninstall(dev);
9293         cancel_work_sync(&dev_priv->hotplug_work);
9294         cancel_work_sync(&dev_priv->rps_work);
9295
9296         /* flush any delayed tasks or pending work */
9297         flush_scheduled_work();
9298
9299         /* Shut off idle work before the crtcs get freed. */
9300         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9301                 intel_crtc = to_intel_crtc(crtc);
9302                 del_timer_sync(&intel_crtc->idle_timer);
9303         }
9304         del_timer_sync(&dev_priv->idle_timer);
9305         cancel_work_sync(&dev_priv->idle_work);
9306
9307         drm_mode_config_cleanup(dev);
9308 }
9309
9310 /*
9311  * Return which encoder is currently attached for connector.
9312  */
9313 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9314 {
9315         return &intel_attached_encoder(connector)->base;
9316 }
9317
9318 void intel_connector_attach_encoder(struct intel_connector *connector,
9319                                     struct intel_encoder *encoder)
9320 {
9321         connector->encoder = encoder;
9322         drm_mode_connector_attach_encoder(&connector->base,
9323                                           &encoder->base);
9324 }
9325
9326 /*
9327  * set vga decode state - true == enable VGA decode
9328  */
9329 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9330 {
9331         struct drm_i915_private *dev_priv = dev->dev_private;
9332         u16 gmch_ctrl;
9333
9334         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9335         if (state)
9336                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9337         else
9338                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9339         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9340         return 0;
9341 }
9342
9343 #ifdef CONFIG_DEBUG_FS
9344 #include <linux/seq_file.h>
9345
9346 struct intel_display_error_state {
9347         struct intel_cursor_error_state {
9348                 u32 control;
9349                 u32 position;
9350                 u32 base;
9351                 u32 size;
9352         } cursor[2];
9353
9354         struct intel_pipe_error_state {
9355                 u32 conf;
9356                 u32 source;
9357
9358                 u32 htotal;
9359                 u32 hblank;
9360                 u32 hsync;
9361                 u32 vtotal;
9362                 u32 vblank;
9363                 u32 vsync;
9364         } pipe[2];
9365
9366         struct intel_plane_error_state {
9367                 u32 control;
9368                 u32 stride;
9369                 u32 size;
9370                 u32 pos;
9371                 u32 addr;
9372                 u32 surface;
9373                 u32 tile_offset;
9374         } plane[2];
9375 };
9376
9377 struct intel_display_error_state *
9378 intel_display_capture_error_state(struct drm_device *dev)
9379 {
9380         drm_i915_private_t *dev_priv = dev->dev_private;
9381         struct intel_display_error_state *error;
9382         int i;
9383
9384         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9385         if (error == NULL)
9386                 return NULL;
9387
9388         for (i = 0; i < 2; i++) {
9389                 error->cursor[i].control = I915_READ(CURCNTR(i));
9390                 error->cursor[i].position = I915_READ(CURPOS(i));
9391                 error->cursor[i].base = I915_READ(CURBASE(i));
9392
9393                 error->plane[i].control = I915_READ(DSPCNTR(i));
9394                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9395                 error->plane[i].size = I915_READ(DSPSIZE(i));
9396                 error->plane[i].pos = I915_READ(DSPPOS(i));
9397                 error->plane[i].addr = I915_READ(DSPADDR(i));
9398                 if (INTEL_INFO(dev)->gen >= 4) {
9399                         error->plane[i].surface = I915_READ(DSPSURF(i));
9400                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9401                 }
9402
9403                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9404                 error->pipe[i].source = I915_READ(PIPESRC(i));
9405                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9406                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9407                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9408                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9409                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9410                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9411         }
9412
9413         return error;
9414 }
9415
9416 void
9417 intel_display_print_error_state(struct seq_file *m,
9418                                 struct drm_device *dev,
9419                                 struct intel_display_error_state *error)
9420 {
9421         int i;
9422
9423         for (i = 0; i < 2; i++) {
9424                 seq_printf(m, "Pipe [%d]:\n", i);
9425                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9426                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9427                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9428                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9429                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9430                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9431                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9432                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9433
9434                 seq_printf(m, "Plane [%d]:\n", i);
9435                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9436                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9437                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9438                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9439                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9440                 if (INTEL_INFO(dev)->gen >= 4) {
9441                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9442                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9443                 }
9444
9445                 seq_printf(m, "Cursor [%d]:\n", i);
9446                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9447                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9448                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9449         }
9450 }
9451 #endif