drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  78
  79 static void intel_increase_pllclock(struct drm_device *dev,
  80                                     enum pipe pipe);
  81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  82
  83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  84                                 struct intel_crtc_config *pipe_config);
  85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  86                                    struct intel_crtc_config *pipe_config);
  87
  88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  89                           int x, int y, struct drm_framebuffer *old_fb);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  98                                          struct intel_link_m_n *m_n);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc);
 103
 104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 105 {
 106         if (!connector->mst_port)
 107                 return connector->encoder;
 108         else
 109                 return &connector->mst_port->mst_encoders[pipe]->base;
 110 }
 111
 112 typedef struct {
 113         int     min, max;
 114 } intel_range_t;
 115
 116 typedef struct {
 117         int     dot_limit;
 118         int     p2_slow, p2_fast;
 119 } intel_p2_t;
 120
 121 typedef struct intel_limit intel_limit_t;
 122 struct intel_limit {
 123         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 124         intel_p2_t          p2;
 125 };
 126
 127 int
 128 intel_pch_rawclk(struct drm_device *dev)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131
 132         WARN_ON(!HAS_PCH_SPLIT(dev));
 133
 134         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 135 }
 136
 137 static inline u32 /* units of 100MHz */
 138 intel_fdi_link_freq(struct drm_device *dev)
 139 {
 140         if (IS_GEN5(dev)) {
 141                 struct drm_i915_private *dev_priv = dev->dev_private;
 142                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 143         } else
 144                 return 27;
 145 }
 146
 147 static const intel_limit_t intel_limits_i8xx_dac = {
 148         .dot = { .min = 25000, .max = 350000 },
 149         .vco = { .min = 908000, .max = 1512000 },
 150         .n = { .min = 2, .max = 16 },
 151         .m = { .min = 96, .max = 140 },
 152         .m1 = { .min = 18, .max = 26 },
 153         .m2 = { .min = 6, .max = 16 },
 154         .p = { .min = 4, .max = 128 },
 155         .p1 = { .min = 2, .max = 33 },
 156         .p2 = { .dot_limit = 165000,
 157                 .p2_slow = 4, .p2_fast = 2 },
 158 };
 159
 160 static const intel_limit_t intel_limits_i8xx_dvo = {
 161         .dot = { .min = 25000, .max = 350000 },
 162         .vco = { .min = 908000, .max = 1512000 },
 163         .n = { .min = 2, .max = 16 },
 164         .m = { .min = 96, .max = 140 },
 165         .m1 = { .min = 18, .max = 26 },
 166         .m2 = { .min = 6, .max = 16 },
 167         .p = { .min = 4, .max = 128 },
 168         .p1 = { .min = 2, .max = 33 },
 169         .p2 = { .dot_limit = 165000,
 170                 .p2_slow = 4, .p2_fast = 4 },
 171 };
 172
 173 static const intel_limit_t intel_limits_i8xx_lvds = {
 174         .dot = { .min = 25000, .max = 350000 },
 175         .vco = { .min = 908000, .max = 1512000 },
 176         .n = { .min = 2, .max = 16 },
 177         .m = { .min = 96, .max = 140 },
 178         .m1 = { .min = 18, .max = 26 },
 179         .m2 = { .min = 6, .max = 16 },
 180         .p = { .min = 4, .max = 128 },
 181         .p1 = { .min = 1, .max = 6 },
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 14, .p2_fast = 7 },
 184 };
 185
 186 static const intel_limit_t intel_limits_i9xx_sdvo = {
 187         .dot = { .min = 20000, .max = 400000 },
 188         .vco = { .min = 1400000, .max = 2800000 },
 189         .n = { .min = 1, .max = 6 },
 190         .m = { .min = 70, .max = 120 },
 191         .m1 = { .min = 8, .max = 18 },
 192         .m2 = { .min = 3, .max = 7 },
 193         .p = { .min = 5, .max = 80 },
 194         .p1 = { .min = 1, .max = 8 },
 195         .p2 = { .dot_limit = 200000,
 196                 .p2_slow = 10, .p2_fast = 5 },
 197 };
 198
 199 static const intel_limit_t intel_limits_i9xx_lvds = {
 200         .dot = { .min = 20000, .max = 400000 },
 201         .vco = { .min = 1400000, .max = 2800000 },
 202         .n = { .min = 1, .max = 6 },
 203         .m = { .min = 70, .max = 120 },
 204         .m1 = { .min = 8, .max = 18 },
 205         .m2 = { .min = 3, .max = 7 },
 206         .p = { .min = 7, .max = 98 },
 207         .p1 = { .min = 1, .max = 8 },
 208         .p2 = { .dot_limit = 112000,
 209                 .p2_slow = 14, .p2_fast = 7 },
 210 };
 211
 212
 213 static const intel_limit_t intel_limits_g4x_sdvo = {
 214         .dot = { .min = 25000, .max = 270000 },
 215         .vco = { .min = 1750000, .max = 3500000},
 216         .n = { .min = 1, .max = 4 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 10, .max = 30 },
 221         .p1 = { .min = 1, .max = 3},
 222         .p2 = { .dot_limit = 270000,
 223                 .p2_slow = 10,
 224                 .p2_fast = 10
 225         },
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_hdmi = {
 229         .dot = { .min = 22000, .max = 400000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 4 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 16, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 5, .max = 80 },
 236         .p1 = { .min = 1, .max = 8},
 237         .p2 = { .dot_limit = 165000,
 238                 .p2_slow = 10, .p2_fast = 5 },
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 242         .dot = { .min = 20000, .max = 115000 },
 243         .vco = { .min = 1750000, .max = 3500000 },
 244         .n = { .min = 1, .max = 3 },
 245         .m = { .min = 104, .max = 138 },
 246         .m1 = { .min = 17, .max = 23 },
 247         .m2 = { .min = 5, .max = 11 },
 248         .p = { .min = 28, .max = 112 },
 249         .p1 = { .min = 2, .max = 8 },
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 14, .p2_fast = 14
 252         },
 253 };
 254
 255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 256         .dot = { .min = 80000, .max = 224000 },
 257         .vco = { .min = 1750000, .max = 3500000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 104, .max = 138 },
 260         .m1 = { .min = 17, .max = 23 },
 261         .m2 = { .min = 5, .max = 11 },
 262         .p = { .min = 14, .max = 42 },
 263         .p1 = { .min = 2, .max = 6 },
 264         .p2 = { .dot_limit = 0,
 265                 .p2_slow = 7, .p2_fast = 7
 266         },
 267 };
 268
 269 static const intel_limit_t intel_limits_pineview_sdvo = {
 270         .dot = { .min = 20000, .max = 400000},
 271         .vco = { .min = 1700000, .max = 3500000 },
 272         /* Pineview's Ncounter is a ring counter */
 273         .n = { .min = 3, .max = 6 },
 274         .m = { .min = 2, .max = 256 },
 275         /* Pineview only has one combined m divider, which we treat as m2. */
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 200000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282 };
 283
 284 static const intel_limit_t intel_limits_pineview_lvds = {
 285         .dot = { .min = 20000, .max = 400000 },
 286         .vco = { .min = 1700000, .max = 3500000 },
 287         .n = { .min = 3, .max = 6 },
 288         .m = { .min = 2, .max = 256 },
 289         .m1 = { .min = 0, .max = 0 },
 290         .m2 = { .min = 0, .max = 254 },
 291         .p = { .min = 7, .max = 112 },
 292         .p1 = { .min = 1, .max = 8 },
 293         .p2 = { .dot_limit = 112000,
 294                 .p2_slow = 14, .p2_fast = 14 },
 295 };
 296
 297 /* Ironlake / Sandybridge
 298  *
 299  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 300  * the range value for them is (actual_value - 2).
 301  */
 302 static const intel_limit_t intel_limits_ironlake_dac = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 5 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 316         .dot = { .min = 25000, .max = 350000 },
 317         .vco = { .min = 1760000, .max = 3510000 },
 318         .n = { .min = 1, .max = 3 },
 319         .m = { .min = 79, .max = 118 },
 320         .m1 = { .min = 12, .max = 22 },
 321         .m2 = { .min = 5, .max = 9 },
 322         .p = { .min = 28, .max = 112 },
 323         .p1 = { .min = 2, .max = 8 },
 324         .p2 = { .dot_limit = 225000,
 325                 .p2_slow = 14, .p2_fast = 14 },
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 127 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 56 },
 336         .p1 = { .min = 2, .max = 8 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339 };
 340
 341 /* LVDS 100mhz refclk limits. */
 342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 343         .dot = { .min = 25000, .max = 350000 },
 344         .vco = { .min = 1760000, .max = 3510000 },
 345         .n = { .min = 1, .max = 2 },
 346         .m = { .min = 79, .max = 126 },
 347         .m1 = { .min = 12, .max = 22 },
 348         .m2 = { .min = 5, .max = 9 },
 349         .p = { .min = 28, .max = 112 },
 350         .p1 = { .min = 2, .max = 8 },
 351         .p2 = { .dot_limit = 225000,
 352                 .p2_slow = 14, .p2_fast = 14 },
 353 };
 354
 355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 356         .dot = { .min = 25000, .max = 350000 },
 357         .vco = { .min = 1760000, .max = 3510000 },
 358         .n = { .min = 1, .max = 3 },
 359         .m = { .min = 79, .max = 126 },
 360         .m1 = { .min = 12, .max = 22 },
 361         .m2 = { .min = 5, .max = 9 },
 362         .p = { .min = 14, .max = 42 },
 363         .p1 = { .min = 2, .max = 6 },
 364         .p2 = { .dot_limit = 225000,
 365                 .p2_slow = 7, .p2_fast = 7 },
 366 };
 367
 368 static const intel_limit_t intel_limits_vlv = {
 369          /*
 370           * These are the data rate limits (measured in fast clocks)
 371           * since those are the strictest limits we have. The fast
 372           * clock and actual rate limits are more relaxed, so checking
 373           * them would make no difference.
 374           */
 375         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 376         .vco = { .min = 4000000, .max = 6000000 },
 377         .n = { .min = 1, .max = 7 },
 378         .m1 = { .min = 2, .max = 3 },
 379         .m2 = { .min = 11, .max = 156 },
 380         .p1 = { .min = 2, .max = 3 },
 381         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 382 };
 383
 384 static const intel_limit_t intel_limits_chv = {
 385         /*
 386          * These are the data rate limits (measured in fast clocks)
 387          * since those are the strictest limits we have.  The fast
 388          * clock and actual rate limits are more relaxed, so checking
 389          * them would make no difference.
 390          */
 391         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 392         .vco = { .min = 4860000, .max = 6700000 },
 393         .n = { .min = 1, .max = 1 },
 394         .m1 = { .min = 2, .max = 2 },
 395         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 396         .p1 = { .min = 2, .max = 4 },
 397         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 398 };
 399
 400 static void vlv_clock(int refclk, intel_clock_t *clock)
 401 {
 402         clock->m = clock->m1 * clock->m2;
 403         clock->p = clock->p1 * clock->p2;
 404         if (WARN_ON(clock->n == 0 || clock->p == 0))
 405                 return;
 406         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 407         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 408 }
 409
 410 /**
 411  * Returns whether any output on the specified pipe is of the specified type
 412  */
 413 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 414 {
 415         struct drm_device *dev = crtc->dev;
 416         struct intel_encoder *encoder;
 417
 418         for_each_encoder_on_crtc(dev, crtc, encoder)
 419                 if (encoder->type == type)
 420                         return true;
 421
 422         return false;
 423 }
 424
 425 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 426                                                 int refclk)
 427 {
 428         struct drm_device *dev = crtc->dev;
 429         const intel_limit_t *limit;
 430
 431         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 432                 if (intel_is_dual_link_lvds(dev)) {
 433                         if (refclk == 100000)
 434                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 435                         else
 436                                 limit = &intel_limits_ironlake_dual_lvds;
 437                 } else {
 438                         if (refclk == 100000)
 439                                 limit = &intel_limits_ironlake_single_lvds_100m;
 440                         else
 441                                 limit = &intel_limits_ironlake_single_lvds;
 442                 }
 443         } else
 444                 limit = &intel_limits_ironlake_dac;
 445
 446         return limit;
 447 }
 448
 449 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 450 {
 451         struct drm_device *dev = crtc->dev;
 452         const intel_limit_t *limit;
 453
 454         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 455                 if (intel_is_dual_link_lvds(dev))
 456                         limit = &intel_limits_g4x_dual_channel_lvds;
 457                 else
 458                         limit = &intel_limits_g4x_single_channel_lvds;
 459         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 460                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 461                 limit = &intel_limits_g4x_hdmi;
 462         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 463                 limit = &intel_limits_g4x_sdvo;
 464         } else /* The option is for other outputs */
 465                 limit = &intel_limits_i9xx_sdvo;
 466
 467         return limit;
 468 }
 469
 470 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 471 {
 472         struct drm_device *dev = crtc->dev;
 473         const intel_limit_t *limit;
 474
 475         if (HAS_PCH_SPLIT(dev))
 476                 limit = intel_ironlake_limit(crtc, refclk);
 477         else if (IS_G4X(dev)) {
 478                 limit = intel_g4x_limit(crtc);
 479         } else if (IS_PINEVIEW(dev)) {
 480                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 481                         limit = &intel_limits_pineview_lvds;
 482                 else
 483                         limit = &intel_limits_pineview_sdvo;
 484         } else if (IS_CHERRYVIEW(dev)) {
 485                 limit = &intel_limits_chv;
 486         } else if (IS_VALLEYVIEW(dev)) {
 487                 limit = &intel_limits_vlv;
 488         } else if (!IS_GEN2(dev)) {
 489                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 490                         limit = &intel_limits_i9xx_lvds;
 491                 else
 492                         limit = &intel_limits_i9xx_sdvo;
 493         } else {
 494                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 495                         limit = &intel_limits_i8xx_lvds;
 496                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 497                         limit = &intel_limits_i8xx_dvo;
 498                 else
 499                         limit = &intel_limits_i8xx_dac;
 500         }
 501         return limit;
 502 }
 503
 504 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 505 static void pineview_clock(int refclk, intel_clock_t *clock)
 506 {
 507         clock->m = clock->m2 + 2;
 508         clock->p = clock->p1 * clock->p2;
 509         if (WARN_ON(clock->n == 0 || clock->p == 0))
 510                 return;
 511         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 512         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 513 }
 514
 515 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 516 {
 517         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 518 }
 519
 520 static void i9xx_clock(int refclk, intel_clock_t *clock)
 521 {
 522         clock->m = i9xx_dpll_compute_m(clock);
 523         clock->p = clock->p1 * clock->p2;
 524         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 525                 return;
 526         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 527         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 528 }
 529
 530 static void chv_clock(int refclk, intel_clock_t *clock)
 531 {
 532         clock->m = clock->m1 * clock->m2;
 533         clock->p = clock->p1 * clock->p2;
 534         if (WARN_ON(clock->n == 0 || clock->p == 0))
 535                 return;
 536         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 537                         clock->n << 22);
 538         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 539 }
 540
 541 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 542 /**
 543  * Returns whether the given set of divisors are valid for a given refclk with
 544  * the given connectors.
 545  */
 546
 547 static bool intel_PLL_is_valid(struct drm_device *dev,
 548                                const intel_limit_t *limit,
 549                                const intel_clock_t *clock)
 550 {
 551         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 552                 INTELPllInvalid("n out of range\n");
 553         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 554                 INTELPllInvalid("p1 out of range\n");
 555         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 556                 INTELPllInvalid("m2 out of range\n");
 557         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 558                 INTELPllInvalid("m1 out of range\n");
 559
 560         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 561                 if (clock->m1 <= clock->m2)
 562                         INTELPllInvalid("m1 <= m2\n");
 563
 564         if (!IS_VALLEYVIEW(dev)) {
 565                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 566                         INTELPllInvalid("p out of range\n");
 567                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 568                         INTELPllInvalid("m out of range\n");
 569         }
 570
 571         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 572                 INTELPllInvalid("vco out of range\n");
 573         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 574          * connector, etc., rather than just a single range.
 575          */
 576         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 577                 INTELPllInvalid("dot out of range\n");
 578
 579         return true;
 580 }
 581
 582 static bool
 583 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 584                     int target, int refclk, intel_clock_t *match_clock,
 585                     intel_clock_t *best_clock)
 586 {
 587         struct drm_device *dev = crtc->dev;
 588         intel_clock_t clock;
 589         int err = target;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 /*
 593                  * For LVDS just rely on its current settings for dual-channel.
 594                  * We haven't figured out how to reliably set up different
 595                  * single/dual channel state, if we even can.
 596                  */
 597                 if (intel_is_dual_link_lvds(dev))
 598                         clock.p2 = limit->p2.p2_fast;
 599                 else
 600                         clock.p2 = limit->p2.p2_slow;
 601         } else {
 602                 if (target < limit->p2.dot_limit)
 603                         clock.p2 = limit->p2.p2_slow;
 604                 else
 605                         clock.p2 = limit->p2.p2_fast;
 606         }
 607
 608         memset(best_clock, 0, sizeof(*best_clock));
 609
 610         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 611              clock.m1++) {
 612                 for (clock.m2 = limit->m2.min;
 613                      clock.m2 <= limit->m2.max; clock.m2++) {
 614                         if (clock.m2 >= clock.m1)
 615                                 break;
 616                         for (clock.n = limit->n.min;
 617                              clock.n <= limit->n.max; clock.n++) {
 618                                 for (clock.p1 = limit->p1.min;
 619                                         clock.p1 <= limit->p1.max; clock.p1++) {
 620                                         int this_err;
 621
 622                                         i9xx_clock(refclk, &clock);
 623                                         if (!intel_PLL_is_valid(dev, limit,
 624                                                                 &clock))
 625                                                 continue;
 626                                         if (match_clock &&
 627                                             clock.p != match_clock->p)
 628                                                 continue;
 629
 630                                         this_err = abs(clock.dot - target);
 631                                         if (this_err < err) {
 632                                                 *best_clock = clock;
 633                                                 err = this_err;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639
 640         return (err != target);
 641 }
 642
 643 static bool
 644 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 645                    int target, int refclk, intel_clock_t *match_clock,
 646                    intel_clock_t *best_clock)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         intel_clock_t clock;
 650         int err = target;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 /*
 654                  * For LVDS just rely on its current settings for dual-channel.
 655                  * We haven't figured out how to reliably set up different
 656                  * single/dual channel state, if we even can.
 657                  */
 658                 if (intel_is_dual_link_lvds(dev))
 659                         clock.p2 = limit->p2.p2_fast;
 660                 else
 661                         clock.p2 = limit->p2.p2_slow;
 662         } else {
 663                 if (target < limit->p2.dot_limit)
 664                         clock.p2 = limit->p2.p2_slow;
 665                 else
 666                         clock.p2 = limit->p2.p2_fast;
 667         }
 668
 669         memset(best_clock, 0, sizeof(*best_clock));
 670
 671         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 672              clock.m1++) {
 673                 for (clock.m2 = limit->m2.min;
 674                      clock.m2 <= limit->m2.max; clock.m2++) {
 675                         for (clock.n = limit->n.min;
 676                              clock.n <= limit->n.max; clock.n++) {
 677                                 for (clock.p1 = limit->p1.min;
 678                                         clock.p1 <= limit->p1.max; clock.p1++) {
 679                                         int this_err;
 680
 681                                         pineview_clock(refclk, &clock);
 682                                         if (!intel_PLL_is_valid(dev, limit,
 683                                                                 &clock))
 684                                                 continue;
 685                                         if (match_clock &&
 686                                             clock.p != match_clock->p)
 687                                                 continue;
 688
 689                                         this_err = abs(clock.dot - target);
 690                                         if (this_err < err) {
 691                                                 *best_clock = clock;
 692                                                 err = this_err;
 693                                         }
 694                                 }
 695                         }
 696                 }
 697         }
 698
 699         return (err != target);
 700 }
 701
 702 static bool
 703 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 704                    int target, int refclk, intel_clock_t *match_clock,
 705                    intel_clock_t *best_clock)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         intel_clock_t clock;
 709         int max_n;
 710         bool found;
 711         /* approximately equals target * 0.00585 */
 712         int err_most = (target >> 8) + (target >> 9);
 713         found = false;
 714
 715         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 716                 if (intel_is_dual_link_lvds(dev))
 717                         clock.p2 = limit->p2.p2_fast;
 718                 else
 719                         clock.p2 = limit->p2.p2_slow;
 720         } else {
 721                 if (target < limit->p2.dot_limit)
 722                         clock.p2 = limit->p2.p2_slow;
 723                 else
 724                         clock.p2 = limit->p2.p2_fast;
 725         }
 726
 727         memset(best_clock, 0, sizeof(*best_clock));
 728         max_n = limit->n.max;
 729         /* based on hardware requirement, prefer smaller n to precision */
 730         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 731                 /* based on hardware requirement, prefere larger m1,m2 */
 732                 for (clock.m1 = limit->m1.max;
 733                      clock.m1 >= limit->m1.min; clock.m1--) {
 734                         for (clock.m2 = limit->m2.max;
 735                              clock.m2 >= limit->m2.min; clock.m2--) {
 736                                 for (clock.p1 = limit->p1.max;
 737                                      clock.p1 >= limit->p1.min; clock.p1--) {
 738                                         int this_err;
 739
 740                                         i9xx_clock(refclk, &clock);
 741                                         if (!intel_PLL_is_valid(dev, limit,
 742                                                                 &clock))
 743                                                 continue;
 744
 745                                         this_err = abs(clock.dot - target);
 746                                         if (this_err < err_most) {
 747                                                 *best_clock = clock;
 748                                                 err_most = this_err;
 749                                                 max_n = clock.n;
 750                                                 found = true;
 751                                         }
 752                                 }
 753                         }
 754                 }
 755         }
 756         return found;
 757 }
 758
 759 static bool
 760 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 761                    int target, int refclk, intel_clock_t *match_clock,
 762                    intel_clock_t *best_clock)
 763 {
 764         struct drm_device *dev = crtc->dev;
 765         intel_clock_t clock;
 766         unsigned int bestppm = 1000000;
 767         /* min update 19.2 MHz */
 768         int max_n = min(limit->n.max, refclk / 19200);
 769         bool found = false;
 770
 771         target *= 5; /* fast clock */
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 778                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 779                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 780                                 clock.p = clock.p1 * clock.p2;
 781                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 782                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 783                                         unsigned int ppm, diff;
 784
 785                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 786                                                                      refclk * clock.m1);
 787
 788                                         vlv_clock(refclk, &clock);
 789
 790                                         if (!intel_PLL_is_valid(dev, limit,
 791                                                                 &clock))
 792                                                 continue;
 793
 794                                         diff = abs(clock.dot - target);
 795                                         ppm = div_u64(1000000ULL * diff, target);
 796
 797                                         if (ppm < 100 && clock.p > best_clock->p) {
 798                                                 bestppm = 0;
 799                                                 *best_clock = clock;
 800                                                 found = true;
 801                                         }
 802
 803                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 804                                                 bestppm = ppm;
 805                                                 *best_clock = clock;
 806                                                 found = true;
 807                                         }
 808                                 }
 809                         }
 810                 }
 811         }
 812
 813         return found;
 814 }
 815
 816 static bool
 817 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 818                    int target, int refclk, intel_clock_t *match_clock,
 819                    intel_clock_t *best_clock)
 820 {
 821         struct drm_device *dev = crtc->dev;
 822         intel_clock_t clock;
 823         uint64_t m2;
 824         int found = false;
 825
 826         memset(best_clock, 0, sizeof(*best_clock));
 827
 828         /*
 829          * Based on hardware doc, the n always set to 1, and m1 always
 830          * set to 2.  If requires to support 200Mhz refclk, we need to
 831          * revisit this because n may not 1 anymore.
 832          */
 833         clock.n = 1, clock.m1 = 2;
 834         target *= 5;    /* fast clock */
 835
 836         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 837                 for (clock.p2 = limit->p2.p2_fast;
 838                                 clock.p2 >= limit->p2.p2_slow;
 839                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 840
 841                         clock.p = clock.p1 * clock.p2;
 842
 843                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 844                                         clock.n) << 22, refclk * clock.m1);
 845
 846                         if (m2 > INT_MAX/clock.m1)
 847                                 continue;
 848
 849                         clock.m2 = m2;
 850
 851                         chv_clock(refclk, &clock);
 852
 853                         if (!intel_PLL_is_valid(dev, limit, &clock))
 854                                 continue;
 855
 856                         /* based on hardware requirement, prefer bigger p
 857                          */
 858                         if (clock.p > best_clock->p) {
 859                                 *best_clock = clock;
 860                                 found = true;
 861                         }
 862                 }
 863         }
 864
 865         return found;
 866 }
 867
 868 bool intel_crtc_active(struct drm_crtc *crtc)
 869 {
 870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 871
 872         /* Be paranoid as we can arrive here with only partial
 873          * state retrieved from the hardware during setup.
 874          *
 875          * We can ditch the adjusted_mode.crtc_clock check as soon
 876          * as Haswell has gained clock readout/fastboot support.
 877          *
 878          * We can ditch the crtc->primary->fb check as soon as we can
 879          * properly reconstruct framebuffers.
 880          */
 881         return intel_crtc->active && crtc->primary->fb &&
 882                 intel_crtc->config.adjusted_mode.crtc_clock;
 883 }
 884
 885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 886                                              enum pipe pipe)
 887 {
 888         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         return intel_crtc->config.cpu_transcoder;
 892 }
 893
 894 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 895 {
 896         struct drm_i915_private *dev_priv = dev->dev_private;
 897         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 898
 899         frame = I915_READ(frame_reg);
 900
 901         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 902                 WARN(1, "vblank wait timed out\n");
 903 }
 904
 905 /**
 906  * intel_wait_for_vblank - wait for vblank on a given pipe
 907  * @dev: drm device
 908  * @pipe: pipe to wait for
 909  *
 910  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 911  * mode setting code.
 912  */
 913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int pipestat_reg = PIPESTAT(pipe);
 917
 918         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 919                 g4x_wait_for_vblank(dev, pipe);
 920                 return;
 921         }
 922
 923         /* Clear existing vblank status. Note this will clear any other
 924          * sticky status fields as well.
 925          *
 926          * This races with i915_driver_irq_handler() with the result
 927          * that either function could miss a vblank event.  Here it is not
 928          * fatal, as we will either wait upon the next vblank interrupt or
 929          * timeout.  Generally speaking intel_wait_for_vblank() is only
 930          * called during modeset at which time the GPU should be idle and
 931          * should *not* be performing page flips and thus not waiting on
 932          * vblanks...
 933          * Currently, the result of us stealing a vblank from the irq
 934          * handler is that a single frame will be skipped during swapbuffers.
 935          */
 936         I915_WRITE(pipestat_reg,
 937                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 938
 939         /* Wait for vblank interrupt bit to set */
 940         if (wait_for(I915_READ(pipestat_reg) &
 941                      PIPE_VBLANK_INTERRUPT_STATUS,
 942                      50))
 943                 DRM_DEBUG_KMS("vblank wait timed out\n");
 944 }
 945
 946 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 947 {
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         u32 reg = PIPEDSL(pipe);
 950         u32 line1, line2;
 951         u32 line_mask;
 952
 953         if (IS_GEN2(dev))
 954                 line_mask = DSL_LINEMASK_GEN2;
 955         else
 956                 line_mask = DSL_LINEMASK_GEN3;
 957
 958         line1 = I915_READ(reg) & line_mask;
 959         mdelay(5);
 960         line2 = I915_READ(reg) & line_mask;
 961
 962         return line1 == line2;
 963 }
 964
 965 /*
 966  * intel_wait_for_pipe_off - wait for pipe to turn off
 967  * @dev: drm device
 968  * @pipe: pipe to wait for
 969  *
 970  * After disabling a pipe, we can't wait for vblank in the usual way,
 971  * spinning on the vblank interrupt status bit, since we won't actually
 972  * see an interrupt when the pipe is disabled.
 973  *
 974  * On Gen4 and above:
 975  *   wait for the pipe register state bit to turn off
 976  *
 977  * Otherwise:
 978  *   wait for the display line value to settle (it usually
 979  *   ends up stopping at the start of the next frame).
 980  *
 981  */
 982 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 983 {
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 986                                                                       pipe);
 987
 988         if (INTEL_INFO(dev)->gen >= 4) {
 989                 int reg = PIPECONF(cpu_transcoder);
 990
 991                 /* Wait for the Pipe State to go off */
 992                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 993                              100))
 994                         WARN(1, "pipe_off wait timed out\n");
 995         } else {
 996                 /* Wait for the display line to settle */
 997                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 998                         WARN(1, "pipe_off wait timed out\n");
 999         }
1000 }
1001
1002 /*
1003  * ibx_digital_port_connected - is the specified port connected?
1004  * @dev_priv: i915 private structure
1005  * @port: the port to test
1006  *
1007  * Returns true if @port is connected, false otherwise.
1008  */
1009 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010                                 struct intel_digital_port *port)
1011 {
1012         u32 bit;
1013
1014         if (HAS_PCH_IBX(dev_priv->dev)) {
1015                 switch (port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         } else {
1029                 switch (port->port) {
1030                 case PORT_B:
1031                         bit = SDE_PORTB_HOTPLUG_CPT;
1032                         break;
1033                 case PORT_C:
1034                         bit = SDE_PORTC_HOTPLUG_CPT;
1035                         break;
1036                 case PORT_D:
1037                         bit = SDE_PORTD_HOTPLUG_CPT;
1038                         break;
1039                 default:
1040                         return true;
1041                 }
1042         }
1043
1044         return I915_READ(SDEISR) & bit;
1045 }
1046
1047 static const char *state_string(bool enabled)
1048 {
1049         return enabled ? "on" : "off";
1050 }
1051
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054                 enum pipe pipe, bool state)
1055 {
1056         int reg;
1057         u32 val;
1058         bool cur_state;
1059
1060         reg = DPLL(pipe);
1061         val = I915_READ(reg);
1062         cur_state = !!(val & DPLL_VCO_ENABLE);
1063         WARN(cur_state != state,
1064              "PLL state assertion failure (expected %s, current %s)\n",
1065              state_string(state), state_string(cur_state));
1066 }
1067
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1070 {
1071         u32 val;
1072         bool cur_state;
1073
1074         mutex_lock(&dev_priv->dpio_lock);
1075         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076         mutex_unlock(&dev_priv->dpio_lock);
1077
1078         cur_state = val & DSI_PLL_VCO_EN;
1079         WARN(cur_state != state,
1080              "DSI PLL state assertion failure (expected %s, current %s)\n",
1081              state_string(state), state_string(cur_state));
1082 }
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1085
1086 struct intel_shared_dpll *
1087 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1088 {
1089         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1090
1091         if (crtc->config.shared_dpll < 0)
1092                 return NULL;
1093
1094         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1095 }
1096
1097 /* For ILK+ */
1098 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099                         struct intel_shared_dpll *pll,
1100                         bool state)
1101 {
1102         bool cur_state;
1103         struct intel_dpll_hw_state hw_state;
1104
1105         if (WARN (!pll,
1106                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1107                 return;
1108
1109         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110         WARN(cur_state != state,
1111              "%s assertion failure (expected %s, current %s)\n",
1112              pll->name, state_string(state), state_string(cur_state));
1113 }
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116                           enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123
1124         if (HAS_DDI(dev_priv->dev)) {
1125                 /* DDI does not have a specific FDI_TX register */
1126                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129         } else {
1130                 reg = FDI_TX_CTL(pipe);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & FDI_TX_ENABLE);
1133         }
1134         WARN(cur_state != state,
1135              "FDI TX state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142                           enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX state assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159                                       enum pipe pipe)
1160 {
1161         int reg;
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv->dev))
1170                 return;
1171
1172         reg = FDI_TX_CTL(pipe);
1173         val = I915_READ(reg);
1174         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183
1184         reg = FDI_RX_CTL(pipe);
1185         val = I915_READ(reg);
1186         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187         WARN(cur_state != state,
1188              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189              state_string(state), state_string(cur_state));
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         int pp_reg, lvds_reg;
1196         u32 val;
1197         enum pipe panel_pipe = PIPE_A;
1198         bool locked = true;
1199
1200         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201                 pp_reg = PCH_PP_CONTROL;
1202                 lvds_reg = PCH_LVDS;
1203         } else {
1204                 pp_reg = PP_CONTROL;
1205                 lvds_reg = LVDS;
1206         }
1207
1208         val = I915_READ(pp_reg);
1209         if (!(val & PANEL_POWER_ON) ||
1210             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211                 locked = false;
1212
1213         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214                 panel_pipe = PIPE_B;
1215
1216         WARN(panel_pipe == pipe && locked,
1217              "panel assertion failure, pipe %c regs locked\n",
1218              pipe_name(pipe));
1219 }
1220
1221 static void assert_cursor(struct drm_i915_private *dev_priv,
1222                           enum pipe pipe, bool state)
1223 {
1224         struct drm_device *dev = dev_priv->dev;
1225         bool cur_state;
1226
1227         if (IS_845G(dev) || IS_I865G(dev))
1228                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1229         else
1230                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1231
1232         WARN(cur_state != state,
1233              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1234              pipe_name(pipe), state_string(state), state_string(cur_state));
1235 }
1236 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1237 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1238
1239 void assert_pipe(struct drm_i915_private *dev_priv,
1240                  enum pipe pipe, bool state)
1241 {
1242         int reg;
1243         u32 val;
1244         bool cur_state;
1245         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1246                                                                       pipe);
1247
1248         /* if we need the pipe A quirk it must be always on */
1249         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1250                 state = true;
1251
1252         if (!intel_display_power_enabled(dev_priv,
1253                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1254                 cur_state = false;
1255         } else {
1256                 reg = PIPECONF(cpu_transcoder);
1257                 val = I915_READ(reg);
1258                 cur_state = !!(val & PIPECONF_ENABLE);
1259         }
1260
1261         WARN(cur_state != state,
1262              "pipe %c assertion failure (expected %s, current %s)\n",
1263              pipe_name(pipe), state_string(state), state_string(cur_state));
1264 }
1265
1266 static void assert_plane(struct drm_i915_private *dev_priv,
1267                          enum plane plane, bool state)
1268 {
1269         int reg;
1270         u32 val;
1271         bool cur_state;
1272
1273         reg = DSPCNTR(plane);
1274         val = I915_READ(reg);
1275         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1276         WARN(cur_state != state,
1277              "plane %c assertion failure (expected %s, current %s)\n",
1278              plane_name(plane), state_string(state), state_string(cur_state));
1279 }
1280
1281 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1282 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1283
1284 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1285                                    enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int reg, i;
1289         u32 val;
1290         int cur_pipe;
1291
1292         /* Primary planes are fixed to pipes on gen4+ */
1293         if (INTEL_INFO(dev)->gen >= 4) {
1294                 reg = DSPCNTR(pipe);
1295                 val = I915_READ(reg);
1296                 WARN(val & DISPLAY_PLANE_ENABLE,
1297                      "plane %c assertion failure, should be disabled but not\n",
1298                      plane_name(pipe));
1299                 return;
1300         }
1301
1302         /* Need to check both planes against the pipe */
1303         for_each_pipe(i) {
1304                 reg = DSPCNTR(i);
1305                 val = I915_READ(reg);
1306                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1307                         DISPPLANE_SEL_PIPE_SHIFT;
1308                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1309                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1310                      plane_name(i), pipe_name(pipe));
1311         }
1312 }
1313
1314 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1315                                     enum pipe pipe)
1316 {
1317         struct drm_device *dev = dev_priv->dev;
1318         int reg, sprite;
1319         u32 val;
1320
1321         if (IS_VALLEYVIEW(dev)) {
1322                 for_each_sprite(pipe, sprite) {
1323                         reg = SPCNTR(pipe, sprite);
1324                         val = I915_READ(reg);
1325                         WARN(val & SP_ENABLE,
1326                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327                              sprite_name(pipe, sprite), pipe_name(pipe));
1328                 }
1329         } else if (INTEL_INFO(dev)->gen >= 7) {
1330                 reg = SPRCTL(pipe);
1331                 val = I915_READ(reg);
1332                 WARN(val & SPRITE_ENABLE,
1333                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334                      plane_name(pipe), pipe_name(pipe));
1335         } else if (INTEL_INFO(dev)->gen >= 5) {
1336                 reg = DVSCNTR(pipe);
1337                 val = I915_READ(reg);
1338                 WARN(val & DVS_ENABLE,
1339                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340                      plane_name(pipe), pipe_name(pipe));
1341         }
1342 }
1343
1344 static void assert_vblank_disabled(struct drm_crtc *crtc)
1345 {
1346         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1347                 drm_crtc_vblank_put(crtc);
1348 }
1349
1350 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1351 {
1352         u32 val;
1353         bool enabled;
1354
1355         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1356
1357         val = I915_READ(PCH_DREF_CONTROL);
1358         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1359                             DREF_SUPERSPREAD_SOURCE_MASK));
1360         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1361 }
1362
1363 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1364                                            enum pipe pipe)
1365 {
1366         int reg;
1367         u32 val;
1368         bool enabled;
1369
1370         reg = PCH_TRANSCONF(pipe);
1371         val = I915_READ(reg);
1372         enabled = !!(val & TRANS_ENABLE);
1373         WARN(enabled,
1374              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1375              pipe_name(pipe));
1376 }
1377
1378 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1379                             enum pipe pipe, u32 port_sel, u32 val)
1380 {
1381         if ((val & DP_PORT_EN) == 0)
1382                 return false;
1383
1384         if (HAS_PCH_CPT(dev_priv->dev)) {
1385                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1386                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1387                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1388                         return false;
1389         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1390                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1400                               enum pipe pipe, u32 val)
1401 {
1402         if ((val & SDVO_ENABLE) == 0)
1403                 return false;
1404
1405         if (HAS_PCH_CPT(dev_priv->dev)) {
1406                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1407                         return false;
1408         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1409                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1410                         return false;
1411         } else {
1412                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1413                         return false;
1414         }
1415         return true;
1416 }
1417
1418 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1419                               enum pipe pipe, u32 val)
1420 {
1421         if ((val & LVDS_PORT_EN) == 0)
1422                 return false;
1423
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1435                               enum pipe pipe, u32 val)
1436 {
1437         if ((val & ADPA_DAC_ENABLE) == 0)
1438                 return false;
1439         if (HAS_PCH_CPT(dev_priv->dev)) {
1440                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1441                         return false;
1442         } else {
1443                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1444                         return false;
1445         }
1446         return true;
1447 }
1448
1449 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1450                                    enum pipe pipe, int reg, u32 port_sel)
1451 {
1452         u32 val = I915_READ(reg);
1453         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1454              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1455              reg, pipe_name(pipe));
1456
1457         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1458              && (val & DP_PIPEB_SELECT),
1459              "IBX PCH dp port still using transcoder B\n");
1460 }
1461
1462 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1463                                      enum pipe pipe, int reg)
1464 {
1465         u32 val = I915_READ(reg);
1466         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1467              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1468              reg, pipe_name(pipe));
1469
1470         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1471              && (val & SDVO_PIPE_B_SELECT),
1472              "IBX PCH hdmi port still using transcoder B\n");
1473 }
1474
1475 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1476                                       enum pipe pipe)
1477 {
1478         int reg;
1479         u32 val;
1480
1481         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1482         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1483         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1484
1485         reg = PCH_ADPA;
1486         val = I915_READ(reg);
1487         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1488              "PCH VGA enabled on transcoder %c, should be disabled\n",
1489              pipe_name(pipe));
1490
1491         reg = PCH_LVDS;
1492         val = I915_READ(reg);
1493         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1494              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1495              pipe_name(pipe));
1496
1497         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1498         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1499         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1500 }
1501
1502 static void intel_init_dpio(struct drm_device *dev)
1503 {
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505
1506         if (!IS_VALLEYVIEW(dev))
1507                 return;
1508
1509         /*
1510          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1511          * CHV x1 PHY (DP/HDMI D)
1512          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1513          */
1514         if (IS_CHERRYVIEW(dev)) {
1515                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1516                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1517         } else {
1518                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1519         }
1520 }
1521
1522 static void intel_reset_dpio(struct drm_device *dev)
1523 {
1524         struct drm_i915_private *dev_priv = dev->dev_private;
1525
1526         if (IS_CHERRYVIEW(dev)) {
1527                 enum dpio_phy phy;
1528                 u32 val;
1529
1530                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1531                         /* Poll for phypwrgood signal */
1532                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1533                                                 PHY_POWERGOOD(phy), 1))
1534                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1535
1536                         /*
1537                          * Deassert common lane reset for PHY.
1538                          *
1539                          * This should only be done on init and resume from S3
1540                          * with both PLLs disabled, or we risk losing DPIO and
1541                          * PLL synchronization.
1542                          */
1543                         val = I915_READ(DISPLAY_PHY_CONTROL);
1544                         I915_WRITE(DISPLAY_PHY_CONTROL,
1545                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1546                 }
1547         }
1548 }
1549
1550 static void vlv_enable_pll(struct intel_crtc *crtc)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int reg = DPLL(crtc->pipe);
1555         u32 dpll = crtc->config.dpll_hw_state.dpll;
1556
1557         assert_pipe_disabled(dev_priv, crtc->pipe);
1558
1559         /* No really, not for ILK+ */
1560         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1561
1562         /* PLL is protected by panel, make sure we can write it */
1563         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1564                 assert_panel_unlocked(dev_priv, crtc->pipe);
1565
1566         I915_WRITE(reg, dpll);
1567         POSTING_READ(reg);
1568         udelay(150);
1569
1570         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1571                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1572
1573         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1574         POSTING_READ(DPLL_MD(crtc->pipe));
1575
1576         /* We do this three times for luck */
1577         I915_WRITE(reg, dpll);
1578         POSTING_READ(reg);
1579         udelay(150); /* wait for warmup */
1580         I915_WRITE(reg, dpll);
1581         POSTING_READ(reg);
1582         udelay(150); /* wait for warmup */
1583         I915_WRITE(reg, dpll);
1584         POSTING_READ(reg);
1585         udelay(150); /* wait for warmup */
1586 }
1587
1588 static void chv_enable_pll(struct intel_crtc *crtc)
1589 {
1590         struct drm_device *dev = crtc->base.dev;
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         int pipe = crtc->pipe;
1593         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1594         u32 tmp;
1595
1596         assert_pipe_disabled(dev_priv, crtc->pipe);
1597
1598         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1599
1600         mutex_lock(&dev_priv->dpio_lock);
1601
1602         /* Enable back the 10bit clock to display controller */
1603         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1604         tmp |= DPIO_DCLKP_EN;
1605         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1606
1607         /*
1608          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1609          */
1610         udelay(1);
1611
1612         /* Enable PLL */
1613         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1614
1615         /* Check PLL is locked */
1616         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1617                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1618
1619         /* not sure when this should be written */
1620         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1621         POSTING_READ(DPLL_MD(pipe));
1622
1623         mutex_unlock(&dev_priv->dpio_lock);
1624 }
1625
1626 static void i9xx_enable_pll(struct intel_crtc *crtc)
1627 {
1628         struct drm_device *dev = crtc->base.dev;
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         int reg = DPLL(crtc->pipe);
1631         u32 dpll = crtc->config.dpll_hw_state.dpll;
1632
1633         assert_pipe_disabled(dev_priv, crtc->pipe);
1634
1635         /* No really, not for ILK+ */
1636         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1637
1638         /* PLL is protected by panel, make sure we can write it */
1639         if (IS_MOBILE(dev) && !IS_I830(dev))
1640                 assert_panel_unlocked(dev_priv, crtc->pipe);
1641
1642         I915_WRITE(reg, dpll);
1643
1644         /* Wait for the clocks to stabilize. */
1645         POSTING_READ(reg);
1646         udelay(150);
1647
1648         if (INTEL_INFO(dev)->gen >= 4) {
1649                 I915_WRITE(DPLL_MD(crtc->pipe),
1650                            crtc->config.dpll_hw_state.dpll_md);
1651         } else {
1652                 /* The pixel multiplier can only be updated once the
1653                  * DPLL is enabled and the clocks are stable.
1654                  *
1655                  * So write it again.
1656                  */
1657                 I915_WRITE(reg, dpll);
1658         }
1659
1660         /* We do this three times for luck */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670 }
1671
1672 /**
1673  * i9xx_disable_pll - disable a PLL
1674  * @dev_priv: i915 private structure
1675  * @pipe: pipe PLL to disable
1676  *
1677  * Disable the PLL for @pipe, making sure the pipe is off first.
1678  *
1679  * Note!  This is for pre-ILK only.
1680  */
1681 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1682 {
1683         /* Don't disable pipe A or pipe A PLLs if needed */
1684         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1685                 return;
1686
1687         /* Make sure the pipe isn't still relying on us */
1688         assert_pipe_disabled(dev_priv, pipe);
1689
1690         I915_WRITE(DPLL(pipe), 0);
1691         POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696         u32 val = 0;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /*
1702          * Leave integrated clock source and reference clock enabled for pipe B.
1703          * The latter is needed for VGA hotplug / manual detection.
1704          */
1705         if (pipe == PIPE_B)
1706                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707         I915_WRITE(DPLL(pipe), val);
1708         POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715         u32 val;
1716
1717         /* Make sure the pipe isn't still relying on us */
1718         assert_pipe_disabled(dev_priv, pipe);
1719
1720         /* Set PLL en = 0 */
1721         val = DPLL_SSC_REF_CLOCK_CHV;
1722         if (pipe != PIPE_A)
1723                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726
1727         mutex_lock(&dev_priv->dpio_lock);
1728
1729         /* Disable 10bit clock to display controller */
1730         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731         val &= ~DPIO_DCLKP_EN;
1732         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734         /* disable left/right clock distribution */
1735         if (pipe != PIPE_B) {
1736                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739         } else {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743         }
1744
1745         mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                 struct intel_digital_port *dport)
1750 {
1751         u32 port_mask;
1752         int dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_D:
1764                 port_mask = DPLL_PORTD_READY_MASK;
1765                 dpll_reg = DPIO_PHY_STATUS;
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770
1771         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773                      port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782         if (WARN_ON(pll == NULL))
1783                 return;
1784
1785         WARN_ON(!pll->refcount);
1786         if (pll->active == 0) {
1787                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788                 WARN_ON(pll->on);
1789                 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791                 pll->mode_set(dev_priv, pll);
1792         }
1793 }
1794
1795 /**
1796  * intel_enable_shared_dpll - enable PCH PLL
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe PLL to enable
1799  *
1800  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801  * drives the transcoder clock.
1802  */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805         struct drm_device *dev = crtc->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809         if (WARN_ON(pll == NULL))
1810                 return;
1811
1812         if (WARN_ON(pll->refcount == 0))
1813                 return;
1814
1815         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1816                       pll->name, pll->active, pll->on,
1817                       crtc->base.base.id);
1818
1819         if (pll->active++) {
1820                 WARN_ON(!pll->on);
1821                 assert_shared_dpll_enabled(dev_priv, pll);
1822                 return;
1823         }
1824         WARN_ON(pll->on);
1825
1826         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829         pll->enable(dev_priv, pll);
1830         pll->on = true;
1831 }
1832
1833 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835         struct drm_device *dev = crtc->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841         if (WARN_ON(pll == NULL))
1842                return;
1843
1844         if (WARN_ON(pll->refcount == 0))
1845                 return;
1846
1847         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848                       pll->name, pll->active, pll->on,
1849                       crtc->base.base.id);
1850
1851         if (WARN_ON(pll->active == 0)) {
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853                 return;
1854         }
1855
1856         assert_shared_dpll_enabled(dev_priv, pll);
1857         WARN_ON(!pll->on);
1858         if (--pll->active)
1859                 return;
1860
1861         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862         pll->disable(dev_priv, pll);
1863         pll->on = false;
1864
1865         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869                                            enum pipe pipe)
1870 {
1871         struct drm_device *dev = dev_priv->dev;
1872         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874         uint32_t reg, val, pipeconf_val;
1875
1876         /* PCH only available on ILK+ */
1877         BUG_ON(INTEL_INFO(dev)->gen < 5);
1878
1879         /* Make sure PCH DPLL is enabled */
1880         assert_shared_dpll_enabled(dev_priv,
1881                                    intel_crtc_to_shared_dpll(intel_crtc));
1882
1883         /* FDI must be feeding us bits for PCH ports */
1884         assert_fdi_tx_enabled(dev_priv, pipe);
1885         assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887         if (HAS_PCH_CPT(dev)) {
1888                 /* Workaround: Set the timing override bit before enabling the
1889                  * pch transcoder. */
1890                 reg = TRANS_CHICKEN2(pipe);
1891                 val = I915_READ(reg);
1892                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893                 I915_WRITE(reg, val);
1894         }
1895
1896         reg = PCH_TRANSCONF(pipe);
1897         val = I915_READ(reg);
1898         pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900         if (HAS_PCH_IBX(dev_priv->dev)) {
1901                 /*
1902                  * make the BPC in transcoder be consistent with
1903                  * that in pipeconf reg.
1904                  */
1905                 val &= ~PIPECONF_BPC_MASK;
1906                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907         }
1908
1909         val &= ~TRANS_INTERLACE_MASK;
1910         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911                 if (HAS_PCH_IBX(dev_priv->dev) &&
1912                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1913                         val |= TRANS_LEGACY_INTERLACED_ILK;
1914                 else
1915                         val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(reg, val | TRANS_ENABLE);
1920         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                       enum transcoder cpu_transcoder)
1926 {
1927         u32 val, pipeconf_val;
1928
1929         /* PCH only available on ILK+ */
1930         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1931
1932         /* FDI must be feeding us bits for PCH ports */
1933         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936         /* Workaround: set timing override bit. */
1937         val = I915_READ(_TRANSA_CHICKEN2);
1938         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939         I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941         val = TRANS_ENABLE;
1942         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945             PIPECONF_INTERLACED_ILK)
1946                 val |= TRANS_INTERLACED;
1947         else
1948                 val |= TRANS_PROGRESSIVE;
1949
1950         I915_WRITE(LPT_TRANSCONF, val);
1951         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952                 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956                                             enum pipe pipe)
1957 {
1958         struct drm_device *dev = dev_priv->dev;
1959         uint32_t reg, val;
1960
1961         /* FDI relies on the transcoder */
1962         assert_fdi_tx_disabled(dev_priv, pipe);
1963         assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965         /* Ports must be off as well */
1966         assert_pch_ports_disabled(dev_priv, pipe);
1967
1968         reg = PCH_TRANSCONF(pipe);
1969         val = I915_READ(reg);
1970         val &= ~TRANS_ENABLE;
1971         I915_WRITE(reg, val);
1972         /* wait for PCH transcoder off, transcoder state */
1973         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976         if (!HAS_PCH_IBX(dev)) {
1977                 /* Workaround: Clear the timing override chicken bit again. */
1978                 reg = TRANS_CHICKEN2(pipe);
1979                 val = I915_READ(reg);
1980                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981                 I915_WRITE(reg, val);
1982         }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987         u32 val;
1988
1989         val = I915_READ(LPT_TRANSCONF);
1990         val &= ~TRANS_ENABLE;
1991         I915_WRITE(LPT_TRANSCONF, val);
1992         /* wait for PCH transcoder off, transcoder state */
1993         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994                 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996         /* Workaround: clear timing override bit. */
1997         val = I915_READ(_TRANSA_CHICKEN2);
1998         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999         I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003  * intel_enable_pipe - enable a pipe, asserting requirements
2004  * @crtc: crtc responsible for the pipe
2005  *
2006  * Enable @crtc's pipe, making sure that various hardware specific requirements
2007  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008  */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_device *dev = crtc->base.dev;
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         enum pipe pipe = crtc->pipe;
2014         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015                                                                       pipe);
2016         enum pipe pch_transcoder;
2017         int reg;
2018         u32 val;
2019
2020         assert_planes_disabled(dev_priv, pipe);
2021         assert_cursor_disabled(dev_priv, pipe);
2022         assert_sprites_disabled(dev_priv, pipe);
2023
2024         if (HAS_PCH_LPT(dev_priv->dev))
2025                 pch_transcoder = TRANSCODER_A;
2026         else
2027                 pch_transcoder = pipe;
2028
2029         /*
2030          * A pipe without a PLL won't actually be able to drive bits from
2031          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2032          * need the check.
2033          */
2034         if (!HAS_PCH_SPLIT(dev_priv->dev))
2035                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2036                         assert_dsi_pll_enabled(dev_priv);
2037                 else
2038                         assert_pll_enabled(dev_priv, pipe);
2039         else {
2040                 if (crtc->config.has_pch_encoder) {
2041                         /* if driving the PCH, we need FDI enabled */
2042                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043                         assert_fdi_tx_pll_enabled(dev_priv,
2044                                                   (enum pipe) cpu_transcoder);
2045                 }
2046                 /* FIXME: assert CPU port conditions for SNB+ */
2047         }
2048
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if (val & PIPECONF_ENABLE) {
2052                 WARN_ON(!(pipe == PIPE_A &&
2053                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2054                 return;
2055         }
2056
2057         I915_WRITE(reg, val | PIPECONF_ENABLE);
2058         POSTING_READ(reg);
2059 }
2060
2061 /**
2062  * intel_disable_pipe - disable a pipe, asserting requirements
2063  * @dev_priv: i915 private structure
2064  * @pipe: pipe to disable
2065  *
2066  * Disable @pipe, making sure that various hardware specific requirements
2067  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2068  *
2069  * @pipe should be %PIPE_A or %PIPE_B.
2070  *
2071  * Will wait until the pipe has shut down before returning.
2072  */
2073 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2074                                enum pipe pipe)
2075 {
2076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2077                                                                       pipe);
2078         int reg;
2079         u32 val;
2080
2081         /*
2082          * Make sure planes won't keep trying to pump pixels to us,
2083          * or we might hang the display.
2084          */
2085         assert_planes_disabled(dev_priv, pipe);
2086         assert_cursor_disabled(dev_priv, pipe);
2087         assert_sprites_disabled(dev_priv, pipe);
2088
2089         /* Don't disable pipe A or pipe A PLLs if needed */
2090         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2091                 return;
2092
2093         reg = PIPECONF(cpu_transcoder);
2094         val = I915_READ(reg);
2095         if ((val & PIPECONF_ENABLE) == 0)
2096                 return;
2097
2098         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2099         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2100 }
2101
2102 /*
2103  * Plane regs are double buffered, going from enabled->disabled needs a
2104  * trigger in order to latch.  The display address reg provides this.
2105  */
2106 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2107                                enum plane plane)
2108 {
2109         struct drm_device *dev = dev_priv->dev;
2110         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2111
2112         I915_WRITE(reg, I915_READ(reg));
2113         POSTING_READ(reg);
2114 }
2115
2116 /**
2117  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2118  * @dev_priv: i915 private structure
2119  * @plane: plane to enable
2120  * @pipe: pipe being fed
2121  *
2122  * Enable @plane on @pipe, making sure that @pipe is running first.
2123  */
2124 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2125                                           enum plane plane, enum pipe pipe)
2126 {
2127         struct drm_device *dev = dev_priv->dev;
2128         struct intel_crtc *intel_crtc =
2129                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2130         int reg;
2131         u32 val;
2132
2133         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2134         assert_pipe_enabled(dev_priv, pipe);
2135
2136         if (intel_crtc->primary_enabled)
2137                 return;
2138
2139         intel_crtc->primary_enabled = true;
2140
2141         reg = DSPCNTR(plane);
2142         val = I915_READ(reg);
2143         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2144
2145         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2146         intel_flush_primary_plane(dev_priv, plane);
2147
2148         /*
2149          * BDW signals flip done immediately if the plane
2150          * is disabled, even if the plane enable is already
2151          * armed to occur at the next vblank :(
2152          */
2153         if (IS_BROADWELL(dev))
2154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158  * intel_disable_primary_hw_plane - disable the primary hardware plane
2159  * @dev_priv: i915 private structure
2160  * @plane: plane to disable
2161  * @pipe: pipe consuming the data
2162  *
2163  * Disable @plane; should be an independent operation.
2164  */
2165 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2166                                            enum plane plane, enum pipe pipe)
2167 {
2168         struct intel_crtc *intel_crtc =
2169                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2170         int reg;
2171         u32 val;
2172
2173         if (!intel_crtc->primary_enabled)
2174                 return;
2175
2176         intel_crtc->primary_enabled = false;
2177
2178         reg = DSPCNTR(plane);
2179         val = I915_READ(reg);
2180         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2181
2182         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2183         intel_flush_primary_plane(dev_priv, plane);
2184 }
2185
2186 static bool need_vtd_wa(struct drm_device *dev)
2187 {
2188 #ifdef CONFIG_INTEL_IOMMU
2189         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2190                 return true;
2191 #endif
2192         return false;
2193 }
2194
2195 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2196 {
2197         int tile_height;
2198
2199         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2200         return ALIGN(height, tile_height);
2201 }
2202
2203 int
2204 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2205                            struct drm_i915_gem_object *obj,
2206                            struct intel_engine_cs *pipelined)
2207 {
2208         struct drm_i915_private *dev_priv = dev->dev_private;
2209         u32 alignment;
2210         int ret;
2211
2212         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2213
2214         switch (obj->tiling_mode) {
2215         case I915_TILING_NONE:
2216                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2217                         alignment = 128 * 1024;
2218                 else if (INTEL_INFO(dev)->gen >= 4)
2219                         alignment = 4 * 1024;
2220                 else
2221                         alignment = 64 * 1024;
2222                 break;
2223         case I915_TILING_X:
2224                 /* pin() will align the object as required by fence */
2225                 alignment = 0;
2226                 break;
2227         case I915_TILING_Y:
2228                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2229                 return -EINVAL;
2230         default:
2231                 BUG();
2232         }
2233
2234         /* Note that the w/a also requires 64 PTE of padding following the
2235          * bo. We currently fill all unused PTE with the shadow page and so
2236          * we should always have valid PTE following the scanout preventing
2237          * the VT-d warning.
2238          */
2239         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2240                 alignment = 256 * 1024;
2241
2242         dev_priv->mm.interruptible = false;
2243         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2244         if (ret)
2245                 goto err_interruptible;
2246
2247         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2248          * fence, whereas 965+ only requires a fence if using
2249          * framebuffer compression.  For simplicity, we always install
2250          * a fence as the cost is not that onerous.
2251          */
2252         ret = i915_gem_object_get_fence(obj);
2253         if (ret)
2254                 goto err_unpin;
2255
2256         i915_gem_object_pin_fence(obj);
2257
2258         dev_priv->mm.interruptible = true;
2259         return 0;
2260
2261 err_unpin:
2262         i915_gem_object_unpin_from_display_plane(obj);
2263 err_interruptible:
2264         dev_priv->mm.interruptible = true;
2265         return ret;
2266 }
2267
2268 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2269 {
2270         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2271
2272         i915_gem_object_unpin_fence(obj);
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 }
2275
2276 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2277  * is assumed to be a power-of-two. */
2278 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2279                                              unsigned int tiling_mode,
2280                                              unsigned int cpp,
2281                                              unsigned int pitch)
2282 {
2283         if (tiling_mode != I915_TILING_NONE) {
2284                 unsigned int tile_rows, tiles;
2285
2286                 tile_rows = *y / 8;
2287                 *y %= 8;
2288
2289                 tiles = *x / (512/cpp);
2290                 *x %= 512/cpp;
2291
2292                 return tile_rows * pitch * 8 + tiles * 4096;
2293         } else {
2294                 unsigned int offset;
2295
2296                 offset = *y * pitch + *x * cpp;
2297                 *y = 0;
2298                 *x = (offset & 4095) / cpp;
2299                 return offset & -4096;
2300         }
2301 }
2302
2303 int intel_format_to_fourcc(int format)
2304 {
2305         switch (format) {
2306         case DISPPLANE_8BPP:
2307                 return DRM_FORMAT_C8;
2308         case DISPPLANE_BGRX555:
2309                 return DRM_FORMAT_XRGB1555;
2310         case DISPPLANE_BGRX565:
2311                 return DRM_FORMAT_RGB565;
2312         default:
2313         case DISPPLANE_BGRX888:
2314                 return DRM_FORMAT_XRGB8888;
2315         case DISPPLANE_RGBX888:
2316                 return DRM_FORMAT_XBGR8888;
2317         case DISPPLANE_BGRX101010:
2318                 return DRM_FORMAT_XRGB2101010;
2319         case DISPPLANE_RGBX101010:
2320                 return DRM_FORMAT_XBGR2101010;
2321         }
2322 }
2323
2324 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2325                                   struct intel_plane_config *plane_config)
2326 {
2327         struct drm_device *dev = crtc->base.dev;
2328         struct drm_i915_gem_object *obj = NULL;
2329         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2330         u32 base = plane_config->base;
2331
2332         if (plane_config->size == 0)
2333                 return false;
2334
2335         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2336                                                              plane_config->size);
2337         if (!obj)
2338                 return false;
2339
2340         if (plane_config->tiled) {
2341                 obj->tiling_mode = I915_TILING_X;
2342                 obj->stride = crtc->base.primary->fb->pitches[0];
2343         }
2344
2345         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2346         mode_cmd.width = crtc->base.primary->fb->width;
2347         mode_cmd.height = crtc->base.primary->fb->height;
2348         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2349
2350         mutex_lock(&dev->struct_mutex);
2351
2352         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2353                                    &mode_cmd, obj)) {
2354                 DRM_DEBUG_KMS("intel fb init failed\n");
2355                 goto out_unref_obj;
2356         }
2357
2358         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2359         mutex_unlock(&dev->struct_mutex);
2360
2361         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2362         return true;
2363
2364 out_unref_obj:
2365         drm_gem_object_unreference(&obj->base);
2366         mutex_unlock(&dev->struct_mutex);
2367         return false;
2368 }
2369
2370 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2371                                  struct intel_plane_config *plane_config)
2372 {
2373         struct drm_device *dev = intel_crtc->base.dev;
2374         struct drm_crtc *c;
2375         struct intel_crtc *i;
2376         struct drm_i915_gem_object *obj;
2377
2378         if (!intel_crtc->base.primary->fb)
2379                 return;
2380
2381         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2382                 return;
2383
2384         kfree(intel_crtc->base.primary->fb);
2385         intel_crtc->base.primary->fb = NULL;
2386
2387         /*
2388          * Failed to alloc the obj, check to see if we should share
2389          * an fb with another CRTC instead
2390          */
2391         for_each_crtc(dev, c) {
2392                 i = to_intel_crtc(c);
2393
2394                 if (c == &intel_crtc->base)
2395                         continue;
2396
2397                 if (!i->active)
2398                         continue;
2399
2400                 obj = intel_fb_obj(c->primary->fb);
2401                 if (obj == NULL)
2402                         continue;
2403
2404                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2405                         drm_framebuffer_reference(c->primary->fb);
2406                         intel_crtc->base.primary->fb = c->primary->fb;
2407                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2408                         break;
2409                 }
2410         }
2411 }
2412
2413 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2414                                       struct drm_framebuffer *fb,
2415                                       int x, int y)
2416 {
2417         struct drm_device *dev = crtc->dev;
2418         struct drm_i915_private *dev_priv = dev->dev_private;
2419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2421         int plane = intel_crtc->plane;
2422         unsigned long linear_offset;
2423         u32 dspcntr;
2424         u32 reg;
2425
2426         reg = DSPCNTR(plane);
2427         dspcntr = I915_READ(reg);
2428         /* Mask out pixel format bits in case we change it */
2429         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2430         switch (fb->pixel_format) {
2431         case DRM_FORMAT_C8:
2432                 dspcntr |= DISPPLANE_8BPP;
2433                 break;
2434         case DRM_FORMAT_XRGB1555:
2435         case DRM_FORMAT_ARGB1555:
2436                 dspcntr |= DISPPLANE_BGRX555;
2437                 break;
2438         case DRM_FORMAT_RGB565:
2439                 dspcntr |= DISPPLANE_BGRX565;
2440                 break;
2441         case DRM_FORMAT_XRGB8888:
2442         case DRM_FORMAT_ARGB8888:
2443                 dspcntr |= DISPPLANE_BGRX888;
2444                 break;
2445         case DRM_FORMAT_XBGR8888:
2446         case DRM_FORMAT_ABGR8888:
2447                 dspcntr |= DISPPLANE_RGBX888;
2448                 break;
2449         case DRM_FORMAT_XRGB2101010:
2450         case DRM_FORMAT_ARGB2101010:
2451                 dspcntr |= DISPPLANE_BGRX101010;
2452                 break;
2453         case DRM_FORMAT_XBGR2101010:
2454         case DRM_FORMAT_ABGR2101010:
2455                 dspcntr |= DISPPLANE_RGBX101010;
2456                 break;
2457         default:
2458                 BUG();
2459         }
2460
2461         if (INTEL_INFO(dev)->gen >= 4) {
2462                 if (obj->tiling_mode != I915_TILING_NONE)
2463                         dspcntr |= DISPPLANE_TILED;
2464                 else
2465                         dspcntr &= ~DISPPLANE_TILED;
2466         }
2467
2468         if (IS_G4X(dev))
2469                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2470
2471         I915_WRITE(reg, dspcntr);
2472
2473         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2474
2475         if (INTEL_INFO(dev)->gen >= 4) {
2476                 intel_crtc->dspaddr_offset =
2477                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2478                                                        fb->bits_per_pixel / 8,
2479                                                        fb->pitches[0]);
2480                 linear_offset -= intel_crtc->dspaddr_offset;
2481         } else {
2482                 intel_crtc->dspaddr_offset = linear_offset;
2483         }
2484
2485         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2486                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2487                       fb->pitches[0]);
2488         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2489         if (INTEL_INFO(dev)->gen >= 4) {
2490                 I915_WRITE(DSPSURF(plane),
2491                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2492                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2493                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2494         } else
2495                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2496         POSTING_READ(reg);
2497 }
2498
2499 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2500                                           struct drm_framebuffer *fb,
2501                                           int x, int y)
2502 {
2503         struct drm_device *dev = crtc->dev;
2504         struct drm_i915_private *dev_priv = dev->dev_private;
2505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2507         int plane = intel_crtc->plane;
2508         unsigned long linear_offset;
2509         u32 dspcntr;
2510         u32 reg;
2511
2512         reg = DSPCNTR(plane);
2513         dspcntr = I915_READ(reg);
2514         /* Mask out pixel format bits in case we change it */
2515         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2516         switch (fb->pixel_format) {
2517         case DRM_FORMAT_C8:
2518                 dspcntr |= DISPPLANE_8BPP;
2519                 break;
2520         case DRM_FORMAT_RGB565:
2521                 dspcntr |= DISPPLANE_BGRX565;
2522                 break;
2523         case DRM_FORMAT_XRGB8888:
2524         case DRM_FORMAT_ARGB8888:
2525                 dspcntr |= DISPPLANE_BGRX888;
2526                 break;
2527         case DRM_FORMAT_XBGR8888:
2528         case DRM_FORMAT_ABGR8888:
2529                 dspcntr |= DISPPLANE_RGBX888;
2530                 break;
2531         case DRM_FORMAT_XRGB2101010:
2532         case DRM_FORMAT_ARGB2101010:
2533                 dspcntr |= DISPPLANE_BGRX101010;
2534                 break;
2535         case DRM_FORMAT_XBGR2101010:
2536         case DRM_FORMAT_ABGR2101010:
2537                 dspcntr |= DISPPLANE_RGBX101010;
2538                 break;
2539         default:
2540                 BUG();
2541         }
2542
2543         if (obj->tiling_mode != I915_TILING_NONE)
2544                 dspcntr |= DISPPLANE_TILED;
2545         else
2546                 dspcntr &= ~DISPPLANE_TILED;
2547
2548         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2549                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2550         else
2551                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2552
2553         I915_WRITE(reg, dspcntr);
2554
2555         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2556         intel_crtc->dspaddr_offset =
2557                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2558                                                fb->bits_per_pixel / 8,
2559                                                fb->pitches[0]);
2560         linear_offset -= intel_crtc->dspaddr_offset;
2561
2562         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2563                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2564                       fb->pitches[0]);
2565         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2566         I915_WRITE(DSPSURF(plane),
2567                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2568         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2569                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2570         } else {
2571                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2572                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2573         }
2574         POSTING_READ(reg);
2575 }
2576
2577 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2578 static int
2579 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2580                            int x, int y, enum mode_set_atomic state)
2581 {
2582         struct drm_device *dev = crtc->dev;
2583         struct drm_i915_private *dev_priv = dev->dev_private;
2584
2585         if (dev_priv->display.disable_fbc)
2586                 dev_priv->display.disable_fbc(dev);
2587         intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2588
2589         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2590
2591         return 0;
2592 }
2593
2594 void intel_display_handle_reset(struct drm_device *dev)
2595 {
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct drm_crtc *crtc;
2598
2599         /*
2600          * Flips in the rings have been nuked by the reset,
2601          * so complete all pending flips so that user space
2602          * will get its events and not get stuck.
2603          *
2604          * Also update the base address of all primary
2605          * planes to the the last fb to make sure we're
2606          * showing the correct fb after a reset.
2607          *
2608          * Need to make two loops over the crtcs so that we
2609          * don't try to grab a crtc mutex before the
2610          * pending_flip_queue really got woken up.
2611          */
2612
2613         for_each_crtc(dev, crtc) {
2614                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615                 enum plane plane = intel_crtc->plane;
2616
2617                 intel_prepare_page_flip(dev, plane);
2618                 intel_finish_page_flip_plane(dev, plane);
2619         }
2620
2621         for_each_crtc(dev, crtc) {
2622                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2623
2624                 drm_modeset_lock(&crtc->mutex, NULL);
2625                 /*
2626                  * FIXME: Once we have proper support for primary planes (and
2627                  * disabling them without disabling the entire crtc) allow again
2628                  * a NULL crtc->primary->fb.
2629                  */
2630                 if (intel_crtc->active && crtc->primary->fb)
2631                         dev_priv->display.update_primary_plane(crtc,
2632                                                                crtc->primary->fb,
2633                                                                crtc->x,
2634                                                                crtc->y);
2635                 drm_modeset_unlock(&crtc->mutex);
2636         }
2637 }
2638
2639 static int
2640 intel_finish_fb(struct drm_framebuffer *old_fb)
2641 {
2642         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2643         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2644         bool was_interruptible = dev_priv->mm.interruptible;
2645         int ret;
2646
2647         /* Big Hammer, we also need to ensure that any pending
2648          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2649          * current scanout is retired before unpinning the old
2650          * framebuffer.
2651          *
2652          * This should only fail upon a hung GPU, in which case we
2653          * can safely continue.
2654          */
2655         dev_priv->mm.interruptible = false;
2656         ret = i915_gem_object_finish_gpu(obj);
2657         dev_priv->mm.interruptible = was_interruptible;
2658
2659         return ret;
2660 }
2661
2662 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2663 {
2664         struct drm_device *dev = crtc->dev;
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667         unsigned long flags;
2668         bool pending;
2669
2670         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2671             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2672                 return false;
2673
2674         spin_lock_irqsave(&dev->event_lock, flags);
2675         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2676         spin_unlock_irqrestore(&dev->event_lock, flags);
2677
2678         return pending;
2679 }
2680
2681 static int
2682 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2683                     struct drm_framebuffer *fb)
2684 {
2685         struct drm_device *dev = crtc->dev;
2686         struct drm_i915_private *dev_priv = dev->dev_private;
2687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2688         enum pipe pipe = intel_crtc->pipe;
2689         struct drm_framebuffer *old_fb = crtc->primary->fb;
2690         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2691         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2692         int ret;
2693
2694         if (intel_crtc_has_pending_flip(crtc)) {
2695                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2696                 return -EBUSY;
2697         }
2698
2699         /* no fb bound */
2700         if (!fb) {
2701                 DRM_ERROR("No FB bound\n");
2702                 return 0;
2703         }
2704
2705         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2706                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2707                           plane_name(intel_crtc->plane),
2708                           INTEL_INFO(dev)->num_pipes);
2709                 return -EINVAL;
2710         }
2711
2712         mutex_lock(&dev->struct_mutex);
2713         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2714         if (ret == 0)
2715                 i915_gem_track_fb(old_obj, obj,
2716                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2717         mutex_unlock(&dev->struct_mutex);
2718         if (ret != 0) {
2719                 DRM_ERROR("pin & fence failed\n");
2720                 return ret;
2721         }
2722
2723         /*
2724          * Update pipe size and adjust fitter if needed: the reason for this is
2725          * that in compute_mode_changes we check the native mode (not the pfit
2726          * mode) to see if we can flip rather than do a full mode set. In the
2727          * fastboot case, we'll flip, but if we don't update the pipesrc and
2728          * pfit state, we'll end up with a big fb scanned out into the wrong
2729          * sized surface.
2730          *
2731          * To fix this properly, we need to hoist the checks up into
2732          * compute_mode_changes (or above), check the actual pfit state and
2733          * whether the platform allows pfit disable with pipe active, and only
2734          * then update the pipesrc and pfit state, even on the flip path.
2735          */
2736         if (i915.fastboot) {
2737                 const struct drm_display_mode *adjusted_mode =
2738                         &intel_crtc->config.adjusted_mode;
2739
2740                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2741                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2742                            (adjusted_mode->crtc_vdisplay - 1));
2743                 if (!intel_crtc->config.pch_pfit.enabled &&
2744                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2745                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2746                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2747                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2748                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2749                 }
2750                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2751                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2752         }
2753
2754         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2755
2756         if (intel_crtc->active)
2757                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2758
2759         crtc->primary->fb = fb;
2760         crtc->x = x;
2761         crtc->y = y;
2762
2763         if (old_fb) {
2764                 if (intel_crtc->active && old_fb != fb)
2765                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2766                 mutex_lock(&dev->struct_mutex);
2767                 intel_unpin_fb_obj(old_obj);
2768                 mutex_unlock(&dev->struct_mutex);
2769         }
2770
2771         mutex_lock(&dev->struct_mutex);
2772         intel_update_fbc(dev);
2773         mutex_unlock(&dev->struct_mutex);
2774
2775         return 0;
2776 }
2777
2778 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2779 {
2780         struct drm_device *dev = crtc->dev;
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783         int pipe = intel_crtc->pipe;
2784         u32 reg, temp;
2785
2786         /* enable normal train */
2787         reg = FDI_TX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         if (IS_IVYBRIDGE(dev)) {
2790                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2791                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2792         } else {
2793                 temp &= ~FDI_LINK_TRAIN_NONE;
2794                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2795         }
2796         I915_WRITE(reg, temp);
2797
2798         reg = FDI_RX_CTL(pipe);
2799         temp = I915_READ(reg);
2800         if (HAS_PCH_CPT(dev)) {
2801                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2802                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2803         } else {
2804                 temp &= ~FDI_LINK_TRAIN_NONE;
2805                 temp |= FDI_LINK_TRAIN_NONE;
2806         }
2807         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2808
2809         /* wait one idle pattern time */
2810         POSTING_READ(reg);
2811         udelay(1000);
2812
2813         /* IVB wants error correction enabled */
2814         if (IS_IVYBRIDGE(dev))
2815                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2816                            FDI_FE_ERRC_ENABLE);
2817 }
2818
2819 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2820 {
2821         return crtc->base.enabled && crtc->active &&
2822                 crtc->config.has_pch_encoder;
2823 }
2824
2825 static void ivb_modeset_global_resources(struct drm_device *dev)
2826 {
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         struct intel_crtc *pipe_B_crtc =
2829                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2830         struct intel_crtc *pipe_C_crtc =
2831                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2832         uint32_t temp;
2833
2834         /*
2835          * When everything is off disable fdi C so that we could enable fdi B
2836          * with all lanes. Note that we don't care about enabled pipes without
2837          * an enabled pch encoder.
2838          */
2839         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2840             !pipe_has_enabled_pch(pipe_C_crtc)) {
2841                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2842                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2843
2844                 temp = I915_READ(SOUTH_CHICKEN1);
2845                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2846                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2847                 I915_WRITE(SOUTH_CHICKEN1, temp);
2848         }
2849 }
2850
2851 /* The FDI link training functions for ILK/Ibexpeak. */
2852 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2857         int pipe = intel_crtc->pipe;
2858         u32 reg, temp, tries;
2859
2860         /* FDI needs bits from pipe first */
2861         assert_pipe_enabled(dev_priv, pipe);
2862
2863         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2864            for train result */
2865         reg = FDI_RX_IMR(pipe);
2866         temp = I915_READ(reg);
2867         temp &= ~FDI_RX_SYMBOL_LOCK;
2868         temp &= ~FDI_RX_BIT_LOCK;
2869         I915_WRITE(reg, temp);
2870         I915_READ(reg);
2871         udelay(150);
2872
2873         /* enable CPU FDI TX and PCH FDI RX */
2874         reg = FDI_TX_CTL(pipe);
2875         temp = I915_READ(reg);
2876         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2877         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2878         temp &= ~FDI_LINK_TRAIN_NONE;
2879         temp |= FDI_LINK_TRAIN_PATTERN_1;
2880         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2881
2882         reg = FDI_RX_CTL(pipe);
2883         temp = I915_READ(reg);
2884         temp &= ~FDI_LINK_TRAIN_NONE;
2885         temp |= FDI_LINK_TRAIN_PATTERN_1;
2886         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2887
2888         POSTING_READ(reg);
2889         udelay(150);
2890
2891         /* Ironlake workaround, enable clock pointer after FDI enable*/
2892         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2893         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2894                    FDI_RX_PHASE_SYNC_POINTER_EN);
2895
2896         reg = FDI_RX_IIR(pipe);
2897         for (tries = 0; tries < 5; tries++) {
2898                 temp = I915_READ(reg);
2899                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2900
2901                 if ((temp & FDI_RX_BIT_LOCK)) {
2902                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2903                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2904                         break;
2905                 }
2906         }
2907         if (tries == 5)
2908                 DRM_ERROR("FDI train 1 fail!\n");
2909
2910         /* Train 2 */
2911         reg = FDI_TX_CTL(pipe);
2912         temp = I915_READ(reg);
2913         temp &= ~FDI_LINK_TRAIN_NONE;
2914         temp |= FDI_LINK_TRAIN_PATTERN_2;
2915         I915_WRITE(reg, temp);
2916
2917         reg = FDI_RX_CTL(pipe);
2918         temp = I915_READ(reg);
2919         temp &= ~FDI_LINK_TRAIN_NONE;
2920         temp |= FDI_LINK_TRAIN_PATTERN_2;
2921         I915_WRITE(reg, temp);
2922
2923         POSTING_READ(reg);
2924         udelay(150);
2925
2926         reg = FDI_RX_IIR(pipe);
2927         for (tries = 0; tries < 5; tries++) {
2928                 temp = I915_READ(reg);
2929                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2930
2931                 if (temp & FDI_RX_SYMBOL_LOCK) {
2932                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2933                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2934                         break;
2935                 }
2936         }
2937         if (tries == 5)
2938                 DRM_ERROR("FDI train 2 fail!\n");
2939
2940         DRM_DEBUG_KMS("FDI train done\n");
2941
2942 }
2943
2944 static const int snb_b_fdi_train_param[] = {
2945         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2946         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2947         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2948         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2949 };
2950
2951 /* The FDI link training functions for SNB/Cougarpoint. */
2952 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2953 {
2954         struct drm_device *dev = crtc->dev;
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2957         int pipe = intel_crtc->pipe;
2958         u32 reg, temp, i, retry;
2959
2960         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2961            for train result */
2962         reg = FDI_RX_IMR(pipe);
2963         temp = I915_READ(reg);
2964         temp &= ~FDI_RX_SYMBOL_LOCK;
2965         temp &= ~FDI_RX_BIT_LOCK;
2966         I915_WRITE(reg, temp);
2967
2968         POSTING_READ(reg);
2969         udelay(150);
2970
2971         /* enable CPU FDI TX and PCH FDI RX */
2972         reg = FDI_TX_CTL(pipe);
2973         temp = I915_READ(reg);
2974         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2975         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2976         temp &= ~FDI_LINK_TRAIN_NONE;
2977         temp |= FDI_LINK_TRAIN_PATTERN_1;
2978         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2979         /* SNB-B */
2980         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2981         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2982
2983         I915_WRITE(FDI_RX_MISC(pipe),
2984                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2985
2986         reg = FDI_RX_CTL(pipe);
2987         temp = I915_READ(reg);
2988         if (HAS_PCH_CPT(dev)) {
2989                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2990                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2991         } else {
2992                 temp &= ~FDI_LINK_TRAIN_NONE;
2993                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2994         }
2995         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2996
2997         POSTING_READ(reg);
2998         udelay(150);
2999
3000         for (i = 0; i < 4; i++) {
3001                 reg = FDI_TX_CTL(pipe);
3002                 temp = I915_READ(reg);
3003                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3004                 temp |= snb_b_fdi_train_param[i];
3005                 I915_WRITE(reg, temp);
3006
3007                 POSTING_READ(reg);
3008                 udelay(500);
3009
3010                 for (retry = 0; retry < 5; retry++) {
3011                         reg = FDI_RX_IIR(pipe);
3012                         temp = I915_READ(reg);
3013                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3014                         if (temp & FDI_RX_BIT_LOCK) {
3015                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3016                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3017                                 break;
3018                         }
3019                         udelay(50);
3020                 }
3021                 if (retry < 5)
3022                         break;
3023         }
3024         if (i == 4)
3025                 DRM_ERROR("FDI train 1 fail!\n");
3026
3027         /* Train 2 */
3028         reg = FDI_TX_CTL(pipe);
3029         temp = I915_READ(reg);
3030         temp &= ~FDI_LINK_TRAIN_NONE;
3031         temp |= FDI_LINK_TRAIN_PATTERN_2;
3032         if (IS_GEN6(dev)) {
3033                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3034                 /* SNB-B */
3035                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3036         }
3037         I915_WRITE(reg, temp);
3038
3039         reg = FDI_RX_CTL(pipe);
3040         temp = I915_READ(reg);
3041         if (HAS_PCH_CPT(dev)) {
3042                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3043                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3044         } else {
3045                 temp &= ~FDI_LINK_TRAIN_NONE;
3046                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3047         }
3048         I915_WRITE(reg, temp);
3049
3050         POSTING_READ(reg);
3051         udelay(150);
3052
3053         for (i = 0; i < 4; i++) {
3054                 reg = FDI_TX_CTL(pipe);
3055                 temp = I915_READ(reg);
3056                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3057                 temp |= snb_b_fdi_train_param[i];
3058                 I915_WRITE(reg, temp);
3059
3060                 POSTING_READ(reg);
3061                 udelay(500);
3062
3063                 for (retry = 0; retry < 5; retry++) {
3064                         reg = FDI_RX_IIR(pipe);
3065                         temp = I915_READ(reg);
3066                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3067                         if (temp & FDI_RX_SYMBOL_LOCK) {
3068                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3069                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3070                                 break;
3071                         }
3072                         udelay(50);
3073                 }
3074                 if (retry < 5)
3075                         break;
3076         }
3077         if (i == 4)
3078                 DRM_ERROR("FDI train 2 fail!\n");
3079
3080         DRM_DEBUG_KMS("FDI train done.\n");
3081 }
3082
3083 /* Manual link training for Ivy Bridge A0 parts */
3084 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3085 {
3086         struct drm_device *dev = crtc->dev;
3087         struct drm_i915_private *dev_priv = dev->dev_private;
3088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3089         int pipe = intel_crtc->pipe;
3090         u32 reg, temp, i, j;
3091
3092         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3093            for train result */
3094         reg = FDI_RX_IMR(pipe);
3095         temp = I915_READ(reg);
3096         temp &= ~FDI_RX_SYMBOL_LOCK;
3097         temp &= ~FDI_RX_BIT_LOCK;
3098         I915_WRITE(reg, temp);
3099
3100         POSTING_READ(reg);
3101         udelay(150);
3102
3103         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3104                       I915_READ(FDI_RX_IIR(pipe)));
3105
3106         /* Try each vswing and preemphasis setting twice before moving on */
3107         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3108                 /* disable first in case we need to retry */
3109                 reg = FDI_TX_CTL(pipe);
3110                 temp = I915_READ(reg);
3111                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3112                 temp &= ~FDI_TX_ENABLE;
3113                 I915_WRITE(reg, temp);
3114
3115                 reg = FDI_RX_CTL(pipe);
3116                 temp = I915_READ(reg);
3117                 temp &= ~FDI_LINK_TRAIN_AUTO;
3118                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3119                 temp &= ~FDI_RX_ENABLE;
3120                 I915_WRITE(reg, temp);
3121
3122                 /* enable CPU FDI TX and PCH FDI RX */
3123                 reg = FDI_TX_CTL(pipe);
3124                 temp = I915_READ(reg);
3125                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3126                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3127                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3128                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3129                 temp |= snb_b_fdi_train_param[j/2];
3130                 temp |= FDI_COMPOSITE_SYNC;
3131                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3132
3133                 I915_WRITE(FDI_RX_MISC(pipe),
3134                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3135
3136                 reg = FDI_RX_CTL(pipe);
3137                 temp = I915_READ(reg);
3138                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3139                 temp |= FDI_COMPOSITE_SYNC;
3140                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3141
3142                 POSTING_READ(reg);
3143                 udelay(1); /* should be 0.5us */
3144
3145                 for (i = 0; i < 4; i++) {
3146                         reg = FDI_RX_IIR(pipe);
3147                         temp = I915_READ(reg);
3148                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3149
3150                         if (temp & FDI_RX_BIT_LOCK ||
3151                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3152                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3153                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3154                                               i);
3155                                 break;
3156                         }
3157                         udelay(1); /* should be 0.5us */
3158                 }
3159                 if (i == 4) {
3160                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3161                         continue;
3162                 }
3163
3164                 /* Train 2 */
3165                 reg = FDI_TX_CTL(pipe);
3166                 temp = I915_READ(reg);
3167                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3168                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3169                 I915_WRITE(reg, temp);
3170
3171                 reg = FDI_RX_CTL(pipe);
3172                 temp = I915_READ(reg);
3173                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3174                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3175                 I915_WRITE(reg, temp);
3176
3177                 POSTING_READ(reg);
3178                 udelay(2); /* should be 1.5us */
3179
3180                 for (i = 0; i < 4; i++) {
3181                         reg = FDI_RX_IIR(pipe);
3182                         temp = I915_READ(reg);
3183                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3184
3185                         if (temp & FDI_RX_SYMBOL_LOCK ||
3186                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3187                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3188                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3189                                               i);
3190                                 goto train_done;
3191                         }
3192                         udelay(2); /* should be 1.5us */
3193                 }
3194                 if (i == 4)
3195                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3196         }
3197
3198 train_done:
3199         DRM_DEBUG_KMS("FDI train done.\n");
3200 }
3201
3202 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3203 {
3204         struct drm_device *dev = intel_crtc->base.dev;
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         int pipe = intel_crtc->pipe;
3207         u32 reg, temp;
3208
3209
3210         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3211         reg = FDI_RX_CTL(pipe);
3212         temp = I915_READ(reg);
3213         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3214         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3215         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3216         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3217
3218         POSTING_READ(reg);
3219         udelay(200);
3220
3221         /* Switch from Rawclk to PCDclk */
3222         temp = I915_READ(reg);
3223         I915_WRITE(reg, temp | FDI_PCDCLK);
3224
3225         POSTING_READ(reg);
3226         udelay(200);
3227
3228         /* Enable CPU FDI TX PLL, always on for Ironlake */
3229         reg = FDI_TX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3232                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3233
3234                 POSTING_READ(reg);
3235                 udelay(100);
3236         }
3237 }
3238
3239 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3240 {
3241         struct drm_device *dev = intel_crtc->base.dev;
3242         struct drm_i915_private *dev_priv = dev->dev_private;
3243         int pipe = intel_crtc->pipe;
3244         u32 reg, temp;
3245
3246         /* Switch from PCDclk to Rawclk */
3247         reg = FDI_RX_CTL(pipe);
3248         temp = I915_READ(reg);
3249         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3250
3251         /* Disable CPU FDI TX PLL */
3252         reg = FDI_TX_CTL(pipe);
3253         temp = I915_READ(reg);
3254         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3255
3256         POSTING_READ(reg);
3257         udelay(100);
3258
3259         reg = FDI_RX_CTL(pipe);
3260         temp = I915_READ(reg);
3261         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3262
3263         /* Wait for the clocks to turn off. */
3264         POSTING_READ(reg);
3265         udelay(100);
3266 }
3267
3268 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273         int pipe = intel_crtc->pipe;
3274         u32 reg, temp;
3275
3276         /* disable CPU FDI tx and PCH FDI rx */
3277         reg = FDI_TX_CTL(pipe);
3278         temp = I915_READ(reg);
3279         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3280         POSTING_READ(reg);
3281
3282         reg = FDI_RX_CTL(pipe);
3283         temp = I915_READ(reg);
3284         temp &= ~(0x7 << 16);
3285         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3286         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3287
3288         POSTING_READ(reg);
3289         udelay(100);
3290
3291         /* Ironlake workaround, disable clock pointer after downing FDI */
3292         if (HAS_PCH_IBX(dev))
3293                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3294
3295         /* still set train pattern 1 */
3296         reg = FDI_TX_CTL(pipe);
3297         temp = I915_READ(reg);
3298         temp &= ~FDI_LINK_TRAIN_NONE;
3299         temp |= FDI_LINK_TRAIN_PATTERN_1;
3300         I915_WRITE(reg, temp);
3301
3302         reg = FDI_RX_CTL(pipe);
3303         temp = I915_READ(reg);
3304         if (HAS_PCH_CPT(dev)) {
3305                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3306                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3307         } else {
3308                 temp &= ~FDI_LINK_TRAIN_NONE;
3309                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310         }
3311         /* BPC in FDI rx is consistent with that in PIPECONF */
3312         temp &= ~(0x07 << 16);
3313         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3314         I915_WRITE(reg, temp);
3315
3316         POSTING_READ(reg);
3317         udelay(100);
3318 }
3319
3320 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3321 {
3322         struct intel_crtc *crtc;
3323
3324         /* Note that we don't need to be called with mode_config.lock here
3325          * as our list of CRTC objects is static for the lifetime of the
3326          * device and so cannot disappear as we iterate. Similarly, we can
3327          * happily treat the predicates as racy, atomic checks as userspace
3328          * cannot claim and pin a new fb without at least acquring the
3329          * struct_mutex and so serialising with us.
3330          */
3331         for_each_intel_crtc(dev, crtc) {
3332                 if (atomic_read(&crtc->unpin_work_count) == 0)
3333                         continue;
3334
3335                 if (crtc->unpin_work)
3336                         intel_wait_for_vblank(dev, crtc->pipe);
3337
3338                 return true;
3339         }
3340
3341         return false;
3342 }
3343
3344 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3345 {
3346         struct drm_device *dev = crtc->dev;
3347         struct drm_i915_private *dev_priv = dev->dev_private;
3348
3349         if (crtc->primary->fb == NULL)
3350                 return;
3351
3352         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3353
3354         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3355                                    !intel_crtc_has_pending_flip(crtc),
3356                                    60*HZ) == 0);
3357
3358         mutex_lock(&dev->struct_mutex);
3359         intel_finish_fb(crtc->primary->fb);
3360         mutex_unlock(&dev->struct_mutex);
3361 }
3362
3363 /* Program iCLKIP clock to the desired frequency */
3364 static void lpt_program_iclkip(struct drm_crtc *crtc)
3365 {
3366         struct drm_device *dev = crtc->dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3369         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3370         u32 temp;
3371
3372         mutex_lock(&dev_priv->dpio_lock);
3373
3374         /* It is necessary to ungate the pixclk gate prior to programming
3375          * the divisors, and gate it back when it is done.
3376          */
3377         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3378
3379         /* Disable SSCCTL */
3380         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3381                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3382                                 SBI_SSCCTL_DISABLE,
3383                         SBI_ICLK);
3384
3385         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3386         if (clock == 20000) {
3387                 auxdiv = 1;
3388                 divsel = 0x41;
3389                 phaseinc = 0x20;
3390         } else {
3391                 /* The iCLK virtual clock root frequency is in MHz,
3392                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3393                  * divisors, it is necessary to divide one by another, so we
3394                  * convert the virtual clock precision to KHz here for higher
3395                  * precision.
3396                  */
3397                 u32 iclk_virtual_root_freq = 172800 * 1000;
3398                 u32 iclk_pi_range = 64;
3399                 u32 desired_divisor, msb_divisor_value, pi_value;
3400
3401                 desired_divisor = (iclk_virtual_root_freq / clock);
3402                 msb_divisor_value = desired_divisor / iclk_pi_range;
3403                 pi_value = desired_divisor % iclk_pi_range;
3404
3405                 auxdiv = 0;
3406                 divsel = msb_divisor_value - 2;
3407                 phaseinc = pi_value;
3408         }
3409
3410         /* This should not happen with any sane values */
3411         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3412                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3413         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3414                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3415
3416         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3417                         clock,
3418                         auxdiv,
3419                         divsel,
3420                         phasedir,
3421                         phaseinc);
3422
3423         /* Program SSCDIVINTPHASE6 */
3424         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3425         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3426         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3427         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3428         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3429         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3430         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3431         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3432
3433         /* Program SSCAUXDIV */
3434         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3435         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3436         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3437         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3438
3439         /* Enable modulator and associated divider */
3440         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3441         temp &= ~SBI_SSCCTL_DISABLE;
3442         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3443
3444         /* Wait for initialization time */
3445         udelay(24);
3446
3447         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3448
3449         mutex_unlock(&dev_priv->dpio_lock);
3450 }
3451
3452 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3453                                                 enum pipe pch_transcoder)
3454 {
3455         struct drm_device *dev = crtc->base.dev;
3456         struct drm_i915_private *dev_priv = dev->dev_private;
3457         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3458
3459         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3460                    I915_READ(HTOTAL(cpu_transcoder)));
3461         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3462                    I915_READ(HBLANK(cpu_transcoder)));
3463         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3464                    I915_READ(HSYNC(cpu_transcoder)));
3465
3466         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3467                    I915_READ(VTOTAL(cpu_transcoder)));
3468         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3469                    I915_READ(VBLANK(cpu_transcoder)));
3470         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3471                    I915_READ(VSYNC(cpu_transcoder)));
3472         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3473                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3474 }
3475
3476 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3477 {
3478         struct drm_i915_private *dev_priv = dev->dev_private;
3479         uint32_t temp;
3480
3481         temp = I915_READ(SOUTH_CHICKEN1);
3482         if (temp & FDI_BC_BIFURCATION_SELECT)
3483                 return;
3484
3485         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3486         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3487
3488         temp |= FDI_BC_BIFURCATION_SELECT;
3489         DRM_DEBUG_KMS("enabling fdi C rx\n");
3490         I915_WRITE(SOUTH_CHICKEN1, temp);
3491         POSTING_READ(SOUTH_CHICKEN1);
3492 }
3493
3494 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3495 {
3496         struct drm_device *dev = intel_crtc->base.dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498
3499         switch (intel_crtc->pipe) {
3500         case PIPE_A:
3501                 break;
3502         case PIPE_B:
3503                 if (intel_crtc->config.fdi_lanes > 2)
3504                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3505                 else
3506                         cpt_enable_fdi_bc_bifurcation(dev);
3507
3508                 break;
3509         case PIPE_C:
3510                 cpt_enable_fdi_bc_bifurcation(dev);
3511
3512                 break;
3513         default:
3514                 BUG();
3515         }
3516 }
3517
3518 /*
3519  * Enable PCH resources required for PCH ports:
3520  *   - PCH PLLs
3521  *   - FDI training & RX/TX
3522  *   - update transcoder timings
3523  *   - DP transcoding bits
3524  *   - transcoder
3525  */
3526 static void ironlake_pch_enable(struct drm_crtc *crtc)
3527 {
3528         struct drm_device *dev = crtc->dev;
3529         struct drm_i915_private *dev_priv = dev->dev_private;
3530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531         int pipe = intel_crtc->pipe;
3532         u32 reg, temp;
3533
3534         assert_pch_transcoder_disabled(dev_priv, pipe);
3535
3536         if (IS_IVYBRIDGE(dev))
3537                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3538
3539         /* Write the TU size bits before fdi link training, so that error
3540          * detection works. */
3541         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3542                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3543
3544         /* For PCH output, training FDI link */
3545         dev_priv->display.fdi_link_train(crtc);
3546
3547         /* We need to program the right clock selection before writing the pixel
3548          * mutliplier into the DPLL. */
3549         if (HAS_PCH_CPT(dev)) {
3550                 u32 sel;
3551
3552                 temp = I915_READ(PCH_DPLL_SEL);
3553                 temp |= TRANS_DPLL_ENABLE(pipe);
3554                 sel = TRANS_DPLLB_SEL(pipe);
3555                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3556                         temp |= sel;
3557                 else
3558                         temp &= ~sel;
3559                 I915_WRITE(PCH_DPLL_SEL, temp);
3560         }
3561
3562         /* XXX: pch pll's can be enabled any time before we enable the PCH
3563          * transcoder, and we actually should do this to not upset any PCH
3564          * transcoder that already use the clock when we share it.
3565          *
3566          * Note that enable_shared_dpll tries to do the right thing, but
3567          * get_shared_dpll unconditionally resets the pll - we need that to have
3568          * the right LVDS enable sequence. */
3569         intel_enable_shared_dpll(intel_crtc);
3570
3571         /* set transcoder timing, panel must allow it */
3572         assert_panel_unlocked(dev_priv, pipe);
3573         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3574
3575         intel_fdi_normal_train(crtc);
3576
3577         /* For PCH DP, enable TRANS_DP_CTL */
3578         if (HAS_PCH_CPT(dev) &&
3579             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3580              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3581                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3582                 reg = TRANS_DP_CTL(pipe);
3583                 temp = I915_READ(reg);
3584                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3585                           TRANS_DP_SYNC_MASK |
3586                           TRANS_DP_BPC_MASK);
3587                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3588                          TRANS_DP_ENH_FRAMING);
3589                 temp |= bpc << 9; /* same format but at 11:9 */
3590
3591                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3592                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3593                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3594                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3595
3596                 switch (intel_trans_dp_port_sel(crtc)) {
3597                 case PCH_DP_B:
3598                         temp |= TRANS_DP_PORT_SEL_B;
3599                         break;
3600                 case PCH_DP_C:
3601                         temp |= TRANS_DP_PORT_SEL_C;
3602                         break;
3603                 case PCH_DP_D:
3604                         temp |= TRANS_DP_PORT_SEL_D;
3605                         break;
3606                 default:
3607                         BUG();
3608                 }
3609
3610                 I915_WRITE(reg, temp);
3611         }
3612
3613         ironlake_enable_pch_transcoder(dev_priv, pipe);
3614 }
3615
3616 static void lpt_pch_enable(struct drm_crtc *crtc)
3617 {
3618         struct drm_device *dev = crtc->dev;
3619         struct drm_i915_private *dev_priv = dev->dev_private;
3620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3622
3623         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3624
3625         lpt_program_iclkip(crtc);
3626
3627         /* Set transcoder timing. */
3628         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3629
3630         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3631 }
3632
3633 void intel_put_shared_dpll(struct intel_crtc *crtc)
3634 {
3635         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3636
3637         if (pll == NULL)
3638                 return;
3639
3640         if (pll->refcount == 0) {
3641                 WARN(1, "bad %s refcount\n", pll->name);
3642                 return;
3643         }
3644
3645         if (--pll->refcount == 0) {
3646                 WARN_ON(pll->on);
3647                 WARN_ON(pll->active);
3648         }
3649
3650         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3651 }
3652
3653 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3654 {
3655         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3656         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3657         enum intel_dpll_id i;
3658
3659         if (pll) {
3660                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3661                               crtc->base.base.id, pll->name);
3662                 intel_put_shared_dpll(crtc);
3663         }
3664
3665         if (HAS_PCH_IBX(dev_priv->dev)) {
3666                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3667                 i = (enum intel_dpll_id) crtc->pipe;
3668                 pll = &dev_priv->shared_dplls[i];
3669
3670                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3671                               crtc->base.base.id, pll->name);
3672
3673                 WARN_ON(pll->refcount);
3674
3675                 goto found;
3676         }
3677
3678         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3679                 pll = &dev_priv->shared_dplls[i];
3680
3681                 /* Only want to check enabled timings first */
3682                 if (pll->refcount == 0)
3683                         continue;
3684
3685                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3686                            sizeof(pll->hw_state)) == 0) {
3687                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3688                                       crtc->base.base.id,
3689                                       pll->name, pll->refcount, pll->active);
3690
3691                         goto found;
3692                 }
3693         }
3694
3695         /* Ok no matching timings, maybe there's a free one? */
3696         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3697                 pll = &dev_priv->shared_dplls[i];
3698                 if (pll->refcount == 0) {
3699                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3700                                       crtc->base.base.id, pll->name);
3701                         goto found;
3702                 }
3703         }
3704
3705         return NULL;
3706
3707 found:
3708         if (pll->refcount == 0)
3709                 pll->hw_state = crtc->config.dpll_hw_state;
3710
3711         crtc->config.shared_dpll = i;
3712         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3713                          pipe_name(crtc->pipe));
3714
3715         pll->refcount++;
3716
3717         return pll;
3718 }
3719
3720 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3721 {
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         int dslreg = PIPEDSL(pipe);
3724         u32 temp;
3725
3726         temp = I915_READ(dslreg);
3727         udelay(500);
3728         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3729                 if (wait_for(I915_READ(dslreg) != temp, 5))
3730                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3731         }
3732 }
3733
3734 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3735 {
3736         struct drm_device *dev = crtc->base.dev;
3737         struct drm_i915_private *dev_priv = dev->dev_private;
3738         int pipe = crtc->pipe;
3739
3740         if (crtc->config.pch_pfit.enabled) {
3741                 /* Force use of hard-coded filter coefficients
3742                  * as some pre-programmed values are broken,
3743                  * e.g. x201.
3744                  */
3745                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3746                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3747                                                  PF_PIPE_SEL_IVB(pipe));
3748                 else
3749                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3750                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3751                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3752         }
3753 }
3754
3755 static void intel_enable_planes(struct drm_crtc *crtc)
3756 {
3757         struct drm_device *dev = crtc->dev;
3758         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3759         struct drm_plane *plane;
3760         struct intel_plane *intel_plane;
3761
3762         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3763                 intel_plane = to_intel_plane(plane);
3764                 if (intel_plane->pipe == pipe)
3765                         intel_plane_restore(&intel_plane->base);
3766         }
3767 }
3768
3769 static void intel_disable_planes(struct drm_crtc *crtc)
3770 {
3771         struct drm_device *dev = crtc->dev;
3772         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3773         struct drm_plane *plane;
3774         struct intel_plane *intel_plane;
3775
3776         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3777                 intel_plane = to_intel_plane(plane);
3778                 if (intel_plane->pipe == pipe)
3779                         intel_plane_disable(&intel_plane->base);
3780         }
3781 }
3782
3783 void hsw_enable_ips(struct intel_crtc *crtc)
3784 {
3785         struct drm_device *dev = crtc->base.dev;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787
3788         if (!crtc->config.ips_enabled)
3789                 return;
3790
3791         /* We can only enable IPS after we enable a plane and wait for a vblank */
3792         intel_wait_for_vblank(dev, crtc->pipe);
3793
3794         assert_plane_enabled(dev_priv, crtc->plane);
3795         if (IS_BROADWELL(dev)) {
3796                 mutex_lock(&dev_priv->rps.hw_lock);
3797                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3798                 mutex_unlock(&dev_priv->rps.hw_lock);
3799                 /* Quoting Art Runyan: "its not safe to expect any particular
3800                  * value in IPS_CTL bit 31 after enabling IPS through the
3801                  * mailbox." Moreover, the mailbox may return a bogus state,
3802                  * so we need to just enable it and continue on.
3803                  */
3804         } else {
3805                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3806                 /* The bit only becomes 1 in the next vblank, so this wait here
3807                  * is essentially intel_wait_for_vblank. If we don't have this
3808                  * and don't wait for vblanks until the end of crtc_enable, then
3809                  * the HW state readout code will complain that the expected
3810                  * IPS_CTL value is not the one we read. */
3811                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3812                         DRM_ERROR("Timed out waiting for IPS enable\n");
3813         }
3814 }
3815
3816 void hsw_disable_ips(struct intel_crtc *crtc)
3817 {
3818         struct drm_device *dev = crtc->base.dev;
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820
3821         if (!crtc->config.ips_enabled)
3822                 return;
3823
3824         assert_plane_enabled(dev_priv, crtc->plane);
3825         if (IS_BROADWELL(dev)) {
3826                 mutex_lock(&dev_priv->rps.hw_lock);
3827                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3828                 mutex_unlock(&dev_priv->rps.hw_lock);
3829                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3830                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3831                         DRM_ERROR("Timed out waiting for IPS disable\n");
3832         } else {
3833                 I915_WRITE(IPS_CTL, 0);
3834                 POSTING_READ(IPS_CTL);
3835         }
3836
3837         /* We need to wait for a vblank before we can disable the plane. */
3838         intel_wait_for_vblank(dev, crtc->pipe);
3839 }
3840
3841 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3842 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847         enum pipe pipe = intel_crtc->pipe;
3848         int palreg = PALETTE(pipe);
3849         int i;
3850         bool reenable_ips = false;
3851
3852         /* The clocks have to be on to load the palette. */
3853         if (!crtc->enabled || !intel_crtc->active)
3854                 return;
3855
3856         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3857                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3858                         assert_dsi_pll_enabled(dev_priv);
3859                 else
3860                         assert_pll_enabled(dev_priv, pipe);
3861         }
3862
3863         /* use legacy palette for Ironlake */
3864         if (!HAS_GMCH_DISPLAY(dev))
3865                 palreg = LGC_PALETTE(pipe);
3866
3867         /* Workaround : Do not read or write the pipe palette/gamma data while
3868          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3869          */
3870         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3871             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3872              GAMMA_MODE_MODE_SPLIT)) {
3873                 hsw_disable_ips(intel_crtc);
3874                 reenable_ips = true;
3875         }
3876
3877         for (i = 0; i < 256; i++) {
3878                 I915_WRITE(palreg + 4 * i,
3879                            (intel_crtc->lut_r[i] << 16) |
3880                            (intel_crtc->lut_g[i] << 8) |
3881                            intel_crtc->lut_b[i]);
3882         }
3883
3884         if (reenable_ips)
3885                 hsw_enable_ips(intel_crtc);
3886 }
3887
3888 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3889 {
3890         if (!enable && intel_crtc->overlay) {
3891                 struct drm_device *dev = intel_crtc->base.dev;
3892                 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894                 mutex_lock(&dev->struct_mutex);
3895                 dev_priv->mm.interruptible = false;
3896                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3897                 dev_priv->mm.interruptible = true;
3898                 mutex_unlock(&dev->struct_mutex);
3899         }
3900
3901         /* Let userspace switch the overlay on again. In most cases userspace
3902          * has to recompute where to put it anyway.
3903          */
3904 }
3905
3906 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3907 {
3908         struct drm_device *dev = crtc->dev;
3909         struct drm_i915_private *dev_priv = dev->dev_private;
3910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3911         int pipe = intel_crtc->pipe;
3912         int plane = intel_crtc->plane;
3913
3914         assert_vblank_disabled(crtc);
3915
3916         drm_vblank_on(dev, pipe);
3917
3918         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3919         intel_enable_planes(crtc);
3920         intel_crtc_update_cursor(crtc, true);
3921         intel_crtc_dpms_overlay(intel_crtc, true);
3922
3923         hsw_enable_ips(intel_crtc);
3924
3925         mutex_lock(&dev->struct_mutex);
3926         intel_update_fbc(dev);
3927         mutex_unlock(&dev->struct_mutex);
3928
3929         /*
3930          * FIXME: Once we grow proper nuclear flip support out of this we need
3931          * to compute the mask of flip planes precisely. For the time being
3932          * consider this a flip from a NULL plane.
3933          */
3934         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3935 }
3936
3937 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3938 {
3939         struct drm_device *dev = crtc->dev;
3940         struct drm_i915_private *dev_priv = dev->dev_private;
3941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942         int pipe = intel_crtc->pipe;
3943         int plane = intel_crtc->plane;
3944
3945         intel_crtc_wait_for_pending_flips(crtc);
3946
3947         if (dev_priv->fbc.plane == plane)
3948                 intel_disable_fbc(dev);
3949
3950         hsw_disable_ips(intel_crtc);
3951
3952         intel_crtc_dpms_overlay(intel_crtc, false);
3953         intel_crtc_update_cursor(crtc, false);
3954         intel_disable_planes(crtc);
3955         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3956
3957         /*
3958          * FIXME: Once we grow proper nuclear flip support out of this we need
3959          * to compute the mask of flip planes precisely. For the time being
3960          * consider this a flip to a NULL plane.
3961          */
3962         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3963
3964         drm_vblank_off(dev, pipe);
3965
3966         assert_vblank_disabled(crtc);
3967 }
3968
3969 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3970 {
3971         struct drm_device *dev = crtc->dev;
3972         struct drm_i915_private *dev_priv = dev->dev_private;
3973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974         struct intel_encoder *encoder;
3975         int pipe = intel_crtc->pipe;
3976         enum plane plane = intel_crtc->plane;
3977
3978         WARN_ON(!crtc->enabled);
3979
3980         if (intel_crtc->active)
3981                 return;
3982
3983         if (intel_crtc->config.has_pch_encoder)
3984                 intel_prepare_shared_dpll(intel_crtc);
3985
3986         if (intel_crtc->config.has_dp_encoder)
3987                 intel_dp_set_m_n(intel_crtc);
3988
3989         intel_set_pipe_timings(intel_crtc);
3990
3991         if (intel_crtc->config.has_pch_encoder) {
3992                 intel_cpu_transcoder_set_m_n(intel_crtc,
3993                                              &intel_crtc->config.fdi_m_n);
3994         }
3995
3996         ironlake_set_pipeconf(crtc);
3997
3998         /* Set up the display plane register */
3999         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4000         POSTING_READ(DSPCNTR(plane));
4001
4002         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4003                                                crtc->x, crtc->y);
4004
4005         intel_crtc->active = true;
4006
4007         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4008         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4009
4010         for_each_encoder_on_crtc(dev, crtc, encoder)
4011                 if (encoder->pre_enable)
4012                         encoder->pre_enable(encoder);
4013
4014         if (intel_crtc->config.has_pch_encoder) {
4015                 /* Note: FDI PLL enabling _must_ be done before we enable the
4016                  * cpu pipes, hence this is separate from all the other fdi/pch
4017                  * enabling. */
4018                 ironlake_fdi_pll_enable(intel_crtc);
4019         } else {
4020                 assert_fdi_tx_disabled(dev_priv, pipe);
4021                 assert_fdi_rx_disabled(dev_priv, pipe);
4022         }
4023
4024         ironlake_pfit_enable(intel_crtc);
4025
4026         /*
4027          * On ILK+ LUT must be loaded before the pipe is running but with
4028          * clocks enabled
4029          */
4030         intel_crtc_load_lut(crtc);
4031
4032         intel_update_watermarks(crtc);
4033         intel_enable_pipe(intel_crtc);
4034
4035         if (intel_crtc->config.has_pch_encoder)
4036                 ironlake_pch_enable(crtc);
4037
4038         for_each_encoder_on_crtc(dev, crtc, encoder)
4039                 encoder->enable(encoder);
4040
4041         if (HAS_PCH_CPT(dev))
4042                 cpt_verify_modeset(dev, intel_crtc->pipe);
4043
4044         intel_crtc_enable_planes(crtc);
4045 }
4046
4047 /* IPS only exists on ULT machines and is tied to pipe A. */
4048 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4049 {
4050         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4051 }
4052
4053 /*
4054  * This implements the workaround described in the "notes" section of the mode
4055  * set sequence documentation. When going from no pipes or single pipe to
4056  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4057  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4058  */
4059 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4060 {
4061         struct drm_device *dev = crtc->base.dev;
4062         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4063
4064         /* We want to get the other_active_crtc only if there's only 1 other
4065          * active crtc. */
4066         for_each_intel_crtc(dev, crtc_it) {
4067                 if (!crtc_it->active || crtc_it == crtc)
4068                         continue;
4069
4070                 if (other_active_crtc)
4071                         return;
4072
4073                 other_active_crtc = crtc_it;
4074         }
4075         if (!other_active_crtc)
4076                 return;
4077
4078         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4079         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4080 }
4081
4082 static void haswell_crtc_enable(struct drm_crtc *crtc)
4083 {
4084         struct drm_device *dev = crtc->dev;
4085         struct drm_i915_private *dev_priv = dev->dev_private;
4086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4087         struct intel_encoder *encoder;
4088         int pipe = intel_crtc->pipe;
4089         enum plane plane = intel_crtc->plane;
4090
4091         WARN_ON(!crtc->enabled);
4092
4093         if (intel_crtc->active)
4094                 return;
4095
4096         if (intel_crtc_to_shared_dpll(intel_crtc))
4097                 intel_enable_shared_dpll(intel_crtc);
4098
4099         if (intel_crtc->config.has_dp_encoder)
4100                 intel_dp_set_m_n(intel_crtc);
4101
4102         intel_set_pipe_timings(intel_crtc);
4103
4104         if (intel_crtc->config.has_pch_encoder) {
4105                 intel_cpu_transcoder_set_m_n(intel_crtc,
4106                                              &intel_crtc->config.fdi_m_n);
4107         }
4108
4109         haswell_set_pipeconf(crtc);
4110
4111         intel_set_pipe_csc(crtc);
4112
4113         /* Set up the display plane register */
4114         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4115         POSTING_READ(DSPCNTR(plane));
4116
4117         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4118                                                crtc->x, crtc->y);
4119
4120         intel_crtc->active = true;
4121
4122         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4123         for_each_encoder_on_crtc(dev, crtc, encoder)
4124                 if (encoder->pre_enable)
4125                         encoder->pre_enable(encoder);
4126
4127         if (intel_crtc->config.has_pch_encoder) {
4128                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4129                 dev_priv->display.fdi_link_train(crtc);
4130         }
4131
4132         intel_ddi_enable_pipe_clock(intel_crtc);
4133
4134         ironlake_pfit_enable(intel_crtc);
4135
4136         /*
4137          * On ILK+ LUT must be loaded before the pipe is running but with
4138          * clocks enabled
4139          */
4140         intel_crtc_load_lut(crtc);
4141
4142         intel_ddi_set_pipe_settings(crtc);
4143         intel_ddi_enable_transcoder_func(crtc);
4144
4145         intel_update_watermarks(crtc);
4146         intel_enable_pipe(intel_crtc);
4147
4148         if (intel_crtc->config.has_pch_encoder)
4149                 lpt_pch_enable(crtc);
4150
4151         if (intel_crtc->config.dp_encoder_is_mst)
4152                 intel_ddi_set_vc_payload_alloc(crtc, true);
4153
4154         for_each_encoder_on_crtc(dev, crtc, encoder) {
4155                 encoder->enable(encoder);
4156                 intel_opregion_notify_encoder(encoder, true);
4157         }
4158
4159         /* If we change the relative order between pipe/planes enabling, we need
4160          * to change the workaround. */
4161         haswell_mode_set_planes_workaround(intel_crtc);
4162         intel_crtc_enable_planes(crtc);
4163 }
4164
4165 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4166 {
4167         struct drm_device *dev = crtc->base.dev;
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         int pipe = crtc->pipe;
4170
4171         /* To avoid upsetting the power well on haswell only disable the pfit if
4172          * it's in use. The hw state code will make sure we get this right. */
4173         if (crtc->config.pch_pfit.enabled) {
4174                 I915_WRITE(PF_CTL(pipe), 0);
4175                 I915_WRITE(PF_WIN_POS(pipe), 0);
4176                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4177         }
4178 }
4179
4180 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4181 {
4182         struct drm_device *dev = crtc->dev;
4183         struct drm_i915_private *dev_priv = dev->dev_private;
4184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185         struct intel_encoder *encoder;
4186         int pipe = intel_crtc->pipe;
4187         u32 reg, temp;
4188
4189         if (!intel_crtc->active)
4190                 return;
4191
4192         intel_crtc_disable_planes(crtc);
4193
4194         for_each_encoder_on_crtc(dev, crtc, encoder)
4195                 encoder->disable(encoder);
4196
4197         if (intel_crtc->config.has_pch_encoder)
4198                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4199
4200         intel_disable_pipe(dev_priv, pipe);
4201
4202         if (intel_crtc->config.dp_encoder_is_mst)
4203                 intel_ddi_set_vc_payload_alloc(crtc, false);
4204
4205         ironlake_pfit_disable(intel_crtc);
4206
4207         for_each_encoder_on_crtc(dev, crtc, encoder)
4208                 if (encoder->post_disable)
4209                         encoder->post_disable(encoder);
4210
4211         if (intel_crtc->config.has_pch_encoder) {
4212                 ironlake_fdi_disable(crtc);
4213
4214                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4215                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4216
4217                 if (HAS_PCH_CPT(dev)) {
4218                         /* disable TRANS_DP_CTL */
4219                         reg = TRANS_DP_CTL(pipe);
4220                         temp = I915_READ(reg);
4221                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4222                                   TRANS_DP_PORT_SEL_MASK);
4223                         temp |= TRANS_DP_PORT_SEL_NONE;
4224                         I915_WRITE(reg, temp);
4225
4226                         /* disable DPLL_SEL */
4227                         temp = I915_READ(PCH_DPLL_SEL);
4228                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4229                         I915_WRITE(PCH_DPLL_SEL, temp);
4230                 }
4231
4232                 /* disable PCH DPLL */
4233                 intel_disable_shared_dpll(intel_crtc);
4234
4235                 ironlake_fdi_pll_disable(intel_crtc);
4236         }
4237
4238         intel_crtc->active = false;
4239         intel_update_watermarks(crtc);
4240
4241         mutex_lock(&dev->struct_mutex);
4242         intel_update_fbc(dev);
4243         mutex_unlock(&dev->struct_mutex);
4244 }
4245
4246 static void haswell_crtc_disable(struct drm_crtc *crtc)
4247 {
4248         struct drm_device *dev = crtc->dev;
4249         struct drm_i915_private *dev_priv = dev->dev_private;
4250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251         struct intel_encoder *encoder;
4252         int pipe = intel_crtc->pipe;
4253         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4254
4255         if (!intel_crtc->active)
4256                 return;
4257
4258         intel_crtc_disable_planes(crtc);
4259
4260         for_each_encoder_on_crtc(dev, crtc, encoder) {
4261                 intel_opregion_notify_encoder(encoder, false);
4262                 encoder->disable(encoder);
4263         }
4264
4265         if (intel_crtc->config.has_pch_encoder)
4266                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4267         intel_disable_pipe(dev_priv, pipe);
4268
4269         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4270
4271         ironlake_pfit_disable(intel_crtc);
4272
4273         intel_ddi_disable_pipe_clock(intel_crtc);
4274
4275         if (intel_crtc->config.has_pch_encoder) {
4276                 lpt_disable_pch_transcoder(dev_priv);
4277                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4278                 intel_ddi_fdi_disable(crtc);
4279         }
4280
4281         for_each_encoder_on_crtc(dev, crtc, encoder)
4282                 if (encoder->post_disable)
4283                         encoder->post_disable(encoder);
4284
4285         intel_crtc->active = false;
4286         intel_update_watermarks(crtc);
4287
4288         mutex_lock(&dev->struct_mutex);
4289         intel_update_fbc(dev);
4290         mutex_unlock(&dev->struct_mutex);
4291
4292         if (intel_crtc_to_shared_dpll(intel_crtc))
4293                 intel_disable_shared_dpll(intel_crtc);
4294 }
4295
4296 static void ironlake_crtc_off(struct drm_crtc *crtc)
4297 {
4298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299         intel_put_shared_dpll(intel_crtc);
4300 }
4301
4302
4303 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4304 {
4305         struct drm_device *dev = crtc->base.dev;
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307         struct intel_crtc_config *pipe_config = &crtc->config;
4308
4309         if (!crtc->config.gmch_pfit.control)
4310                 return;
4311
4312         /*
4313          * The panel fitter should only be adjusted whilst the pipe is disabled,
4314          * according to register description and PRM.
4315          */
4316         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4317         assert_pipe_disabled(dev_priv, crtc->pipe);
4318
4319         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4320         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4321
4322         /* Border color in case we don't scale up to the full screen. Black by
4323          * default, change to something else for debugging. */
4324         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4325 }
4326
4327 static enum intel_display_power_domain port_to_power_domain(enum port port)
4328 {
4329         switch (port) {
4330         case PORT_A:
4331                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4332         case PORT_B:
4333                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4334         case PORT_C:
4335                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4336         case PORT_D:
4337                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4338         default:
4339                 WARN_ON_ONCE(1);
4340                 return POWER_DOMAIN_PORT_OTHER;
4341         }
4342 }
4343
4344 #define for_each_power_domain(domain, mask)                             \
4345         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4346                 if ((1 << (domain)) & (mask))
4347
4348 enum intel_display_power_domain
4349 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4350 {
4351         struct drm_device *dev = intel_encoder->base.dev;
4352         struct intel_digital_port *intel_dig_port;
4353
4354         switch (intel_encoder->type) {
4355         case INTEL_OUTPUT_UNKNOWN:
4356                 /* Only DDI platforms should ever use this output type */
4357                 WARN_ON_ONCE(!HAS_DDI(dev));
4358         case INTEL_OUTPUT_DISPLAYPORT:
4359         case INTEL_OUTPUT_HDMI:
4360         case INTEL_OUTPUT_EDP:
4361                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4362                 return port_to_power_domain(intel_dig_port->port);
4363         case INTEL_OUTPUT_DP_MST:
4364                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4365                 return port_to_power_domain(intel_dig_port->port);
4366         case INTEL_OUTPUT_ANALOG:
4367                 return POWER_DOMAIN_PORT_CRT;
4368         case INTEL_OUTPUT_DSI:
4369                 return POWER_DOMAIN_PORT_DSI;
4370         default:
4371                 return POWER_DOMAIN_PORT_OTHER;
4372         }
4373 }
4374
4375 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4376 {
4377         struct drm_device *dev = crtc->dev;
4378         struct intel_encoder *intel_encoder;
4379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4380         enum pipe pipe = intel_crtc->pipe;
4381         unsigned long mask;
4382         enum transcoder transcoder;
4383
4384         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4385
4386         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4387         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4388         if (intel_crtc->config.pch_pfit.enabled ||
4389             intel_crtc->config.pch_pfit.force_thru)
4390                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4391
4392         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4393                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4394
4395         return mask;
4396 }
4397
4398 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4399                                   bool enable)
4400 {
4401         if (dev_priv->power_domains.init_power_on == enable)
4402                 return;
4403
4404         if (enable)
4405                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4406         else
4407                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4408
4409         dev_priv->power_domains.init_power_on = enable;
4410 }
4411
4412 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4413 {
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4416         struct intel_crtc *crtc;
4417
4418         /*
4419          * First get all needed power domains, then put all unneeded, to avoid
4420          * any unnecessary toggling of the power wells.
4421          */
4422         for_each_intel_crtc(dev, crtc) {
4423                 enum intel_display_power_domain domain;
4424
4425                 if (!crtc->base.enabled)
4426                         continue;
4427
4428                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4429
4430                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4431                         intel_display_power_get(dev_priv, domain);
4432         }
4433
4434         for_each_intel_crtc(dev, crtc) {
4435                 enum intel_display_power_domain domain;
4436
4437                 for_each_power_domain(domain, crtc->enabled_power_domains)
4438                         intel_display_power_put(dev_priv, domain);
4439
4440                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4441         }
4442
4443         intel_display_set_init_power(dev_priv, false);
4444 }
4445
4446 /* returns HPLL frequency in kHz */
4447 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4448 {
4449         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4450
4451         /* Obtain SKU information */
4452         mutex_lock(&dev_priv->dpio_lock);
4453         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4454                 CCK_FUSE_HPLL_FREQ_MASK;
4455         mutex_unlock(&dev_priv->dpio_lock);
4456
4457         return vco_freq[hpll_freq] * 1000;
4458 }
4459
4460 static void vlv_update_cdclk(struct drm_device *dev)
4461 {
4462         struct drm_i915_private *dev_priv = dev->dev_private;
4463
4464         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4465         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4466                          dev_priv->vlv_cdclk_freq);
4467
4468         /*
4469          * Program the gmbus_freq based on the cdclk frequency.
4470          * BSpec erroneously claims we should aim for 4MHz, but
4471          * in fact 1MHz is the correct frequency.
4472          */
4473         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4474 }
4475
4476 /* Adjust CDclk dividers to allow high res or save power if possible */
4477 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4478 {
4479         struct drm_i915_private *dev_priv = dev->dev_private;
4480         u32 val, cmd;
4481
4482         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4483
4484         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4485                 cmd = 2;
4486         else if (cdclk == 266667)
4487                 cmd = 1;
4488         else
4489                 cmd = 0;
4490
4491         mutex_lock(&dev_priv->rps.hw_lock);
4492         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4493         val &= ~DSPFREQGUAR_MASK;
4494         val |= (cmd << DSPFREQGUAR_SHIFT);
4495         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4496         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4497                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4498                      50)) {
4499                 DRM_ERROR("timed out waiting for CDclk change\n");
4500         }
4501         mutex_unlock(&dev_priv->rps.hw_lock);
4502
4503         if (cdclk == 400000) {
4504                 u32 divider, vco;
4505
4506                 vco = valleyview_get_vco(dev_priv);
4507                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4508
4509                 mutex_lock(&dev_priv->dpio_lock);
4510                 /* adjust cdclk divider */
4511                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4512                 val &= ~DISPLAY_FREQUENCY_VALUES;
4513                 val |= divider;
4514                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4515
4516                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4517                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4518                              50))
4519                         DRM_ERROR("timed out waiting for CDclk change\n");
4520                 mutex_unlock(&dev_priv->dpio_lock);
4521         }
4522
4523         mutex_lock(&dev_priv->dpio_lock);
4524         /* adjust self-refresh exit latency value */
4525         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4526         val &= ~0x7f;
4527
4528         /*
4529          * For high bandwidth configs, we set a higher latency in the bunit
4530          * so that the core display fetch happens in time to avoid underruns.
4531          */
4532         if (cdclk == 400000)
4533                 val |= 4500 / 250; /* 4.5 usec */
4534         else
4535                 val |= 3000 / 250; /* 3.0 usec */
4536         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4537         mutex_unlock(&dev_priv->dpio_lock);
4538
4539         vlv_update_cdclk(dev);
4540 }
4541
4542 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4543                                  int max_pixclk)
4544 {
4545         int vco = valleyview_get_vco(dev_priv);
4546         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4547
4548         /*
4549          * Really only a few cases to deal with, as only 4 CDclks are supported:
4550          *   200MHz
4551          *   267MHz
4552          *   320/333MHz (depends on HPLL freq)
4553          *   400MHz
4554          * So we check to see whether we're above 90% of the lower bin and
4555          * adjust if needed.
4556          *
4557          * We seem to get an unstable or solid color picture at 200MHz.
4558          * Not sure what's wrong. For now use 200MHz only when all pipes
4559          * are off.
4560          */
4561         if (max_pixclk > freq_320*9/10)
4562                 return 400000;
4563         else if (max_pixclk > 266667*9/10)
4564                 return freq_320;
4565         else if (max_pixclk > 0)
4566                 return 266667;
4567         else
4568                 return 200000;
4569 }
4570
4571 /* compute the max pixel clock for new configuration */
4572 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4573 {
4574         struct drm_device *dev = dev_priv->dev;
4575         struct intel_crtc *intel_crtc;
4576         int max_pixclk = 0;
4577
4578         for_each_intel_crtc(dev, intel_crtc) {
4579                 if (intel_crtc->new_enabled)
4580                         max_pixclk = max(max_pixclk,
4581                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4582         }
4583
4584         return max_pixclk;
4585 }
4586
4587 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4588                                             unsigned *prepare_pipes)
4589 {
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         struct intel_crtc *intel_crtc;
4592         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4593
4594         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4595             dev_priv->vlv_cdclk_freq)
4596                 return;
4597
4598         /* disable/enable all currently active pipes while we change cdclk */
4599         for_each_intel_crtc(dev, intel_crtc)
4600                 if (intel_crtc->base.enabled)
4601                         *prepare_pipes |= (1 << intel_crtc->pipe);
4602 }
4603
4604 static void valleyview_modeset_global_resources(struct drm_device *dev)
4605 {
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4608         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4609
4610         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4611                 valleyview_set_cdclk(dev, req_cdclk);
4612         modeset_update_crtc_power_domains(dev);
4613 }
4614
4615 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4616 {
4617         struct drm_device *dev = crtc->dev;
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4620         struct intel_encoder *encoder;
4621         int pipe = intel_crtc->pipe;
4622         int plane = intel_crtc->plane;
4623         bool is_dsi;
4624         u32 dspcntr;
4625
4626         WARN_ON(!crtc->enabled);
4627
4628         if (intel_crtc->active)
4629                 return;
4630
4631         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4632
4633         if (!is_dsi && !IS_CHERRYVIEW(dev))
4634                 vlv_prepare_pll(intel_crtc);
4635
4636         /* Set up the display plane register */
4637         dspcntr = DISPPLANE_GAMMA_ENABLE;
4638
4639         if (intel_crtc->config.has_dp_encoder)
4640                 intel_dp_set_m_n(intel_crtc);
4641
4642         intel_set_pipe_timings(intel_crtc);
4643
4644         /* pipesrc and dspsize control the size that is scaled from,
4645          * which should always be the user's requested size.
4646          */
4647         I915_WRITE(DSPSIZE(plane),
4648                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4649                    (intel_crtc->config.pipe_src_w - 1));
4650         I915_WRITE(DSPPOS(plane), 0);
4651
4652         i9xx_set_pipeconf(intel_crtc);
4653
4654         I915_WRITE(DSPCNTR(plane), dspcntr);
4655         POSTING_READ(DSPCNTR(plane));
4656
4657         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4658                                                crtc->x, crtc->y);
4659
4660         intel_crtc->active = true;
4661
4662         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4663
4664         for_each_encoder_on_crtc(dev, crtc, encoder)
4665                 if (encoder->pre_pll_enable)
4666                         encoder->pre_pll_enable(encoder);
4667
4668         if (!is_dsi) {
4669                 if (IS_CHERRYVIEW(dev))
4670                         chv_enable_pll(intel_crtc);
4671                 else
4672                         vlv_enable_pll(intel_crtc);
4673         }
4674
4675         for_each_encoder_on_crtc(dev, crtc, encoder)
4676                 if (encoder->pre_enable)
4677                         encoder->pre_enable(encoder);
4678
4679         i9xx_pfit_enable(intel_crtc);
4680
4681         intel_crtc_load_lut(crtc);
4682
4683         intel_update_watermarks(crtc);
4684         intel_enable_pipe(intel_crtc);
4685
4686         for_each_encoder_on_crtc(dev, crtc, encoder)
4687                 encoder->enable(encoder);
4688
4689         intel_crtc_enable_planes(crtc);
4690
4691         /* Underruns don't raise interrupts, so check manually. */
4692         i9xx_check_fifo_underruns(dev);
4693 }
4694
4695 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4696 {
4697         struct drm_device *dev = crtc->base.dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699
4700         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4701         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4702 }
4703
4704 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         struct intel_encoder *encoder;
4710         int pipe = intel_crtc->pipe;
4711         int plane = intel_crtc->plane;
4712         u32 dspcntr;
4713
4714         WARN_ON(!crtc->enabled);
4715
4716         if (intel_crtc->active)
4717                 return;
4718
4719         i9xx_set_pll_dividers(intel_crtc);
4720
4721         /* Set up the display plane register */
4722         dspcntr = DISPPLANE_GAMMA_ENABLE;
4723
4724         if (pipe == 0)
4725                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4726         else
4727                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4728
4729         if (intel_crtc->config.has_dp_encoder)
4730                 intel_dp_set_m_n(intel_crtc);
4731
4732         intel_set_pipe_timings(intel_crtc);
4733
4734         /* pipesrc and dspsize control the size that is scaled from,
4735          * which should always be the user's requested size.
4736          */
4737         I915_WRITE(DSPSIZE(plane),
4738                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4739                    (intel_crtc->config.pipe_src_w - 1));
4740         I915_WRITE(DSPPOS(plane), 0);
4741
4742         i9xx_set_pipeconf(intel_crtc);
4743
4744         I915_WRITE(DSPCNTR(plane), dspcntr);
4745         POSTING_READ(DSPCNTR(plane));
4746
4747         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4748                                                crtc->x, crtc->y);
4749
4750         intel_crtc->active = true;
4751
4752         if (!IS_GEN2(dev))
4753                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4754
4755         for_each_encoder_on_crtc(dev, crtc, encoder)
4756                 if (encoder->pre_enable)
4757                         encoder->pre_enable(encoder);
4758
4759         i9xx_enable_pll(intel_crtc);
4760
4761         i9xx_pfit_enable(intel_crtc);
4762
4763         intel_crtc_load_lut(crtc);
4764
4765         intel_update_watermarks(crtc);
4766         intel_enable_pipe(intel_crtc);
4767
4768         for_each_encoder_on_crtc(dev, crtc, encoder)
4769                 encoder->enable(encoder);
4770
4771         intel_crtc_enable_planes(crtc);
4772
4773         /*
4774          * Gen2 reports pipe underruns whenever all planes are disabled.
4775          * So don't enable underrun reporting before at least some planes
4776          * are enabled.
4777          * FIXME: Need to fix the logic to work when we turn off all planes
4778          * but leave the pipe running.
4779          */
4780         if (IS_GEN2(dev))
4781                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4782
4783         /* Underruns don't raise interrupts, so check manually. */
4784         i9xx_check_fifo_underruns(dev);
4785 }
4786
4787 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4788 {
4789         struct drm_device *dev = crtc->base.dev;
4790         struct drm_i915_private *dev_priv = dev->dev_private;
4791
4792         if (!crtc->config.gmch_pfit.control)
4793                 return;
4794
4795         assert_pipe_disabled(dev_priv, crtc->pipe);
4796
4797         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4798                          I915_READ(PFIT_CONTROL));
4799         I915_WRITE(PFIT_CONTROL, 0);
4800 }
4801
4802 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4803 {
4804         struct drm_device *dev = crtc->dev;
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4807         struct intel_encoder *encoder;
4808         int pipe = intel_crtc->pipe;
4809
4810         if (!intel_crtc->active)
4811                 return;
4812
4813         /*
4814          * Gen2 reports pipe underruns whenever all planes are disabled.
4815          * So diasble underrun reporting before all the planes get disabled.
4816          * FIXME: Need to fix the logic to work when we turn off all planes
4817          * but leave the pipe running.
4818          */
4819         if (IS_GEN2(dev))
4820                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4821
4822         /*
4823          * Vblank time updates from the shadow to live plane control register
4824          * are blocked if the memory self-refresh mode is active at that
4825          * moment. So to make sure the plane gets truly disabled, disable
4826          * first the self-refresh mode. The self-refresh enable bit in turn
4827          * will be checked/applied by the HW only at the next frame start
4828          * event which is after the vblank start event, so we need to have a
4829          * wait-for-vblank between disabling the plane and the pipe.
4830          */
4831         intel_set_memory_cxsr(dev_priv, false);
4832         intel_crtc_disable_planes(crtc);
4833
4834         for_each_encoder_on_crtc(dev, crtc, encoder)
4835                 encoder->disable(encoder);
4836
4837         /*
4838          * On gen2 planes are double buffered but the pipe isn't, so we must
4839          * wait for planes to fully turn off before disabling the pipe.
4840          * We also need to wait on all gmch platforms because of the
4841          * self-refresh mode constraint explained above.
4842          */
4843         intel_wait_for_vblank(dev, pipe);
4844
4845         intel_disable_pipe(dev_priv, pipe);
4846
4847         i9xx_pfit_disable(intel_crtc);
4848
4849         for_each_encoder_on_crtc(dev, crtc, encoder)
4850                 if (encoder->post_disable)
4851                         encoder->post_disable(encoder);
4852
4853         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4854                 if (IS_CHERRYVIEW(dev))
4855                         chv_disable_pll(dev_priv, pipe);
4856                 else if (IS_VALLEYVIEW(dev))
4857                         vlv_disable_pll(dev_priv, pipe);
4858                 else
4859                         i9xx_disable_pll(dev_priv, pipe);
4860         }
4861
4862         if (!IS_GEN2(dev))
4863                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4864
4865         intel_crtc->active = false;
4866         intel_update_watermarks(crtc);
4867
4868         mutex_lock(&dev->struct_mutex);
4869         intel_update_fbc(dev);
4870         mutex_unlock(&dev->struct_mutex);
4871 }
4872
4873 static void i9xx_crtc_off(struct drm_crtc *crtc)
4874 {
4875 }
4876
4877 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4878                                     bool enabled)
4879 {
4880         struct drm_device *dev = crtc->dev;
4881         struct drm_i915_master_private *master_priv;
4882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883         int pipe = intel_crtc->pipe;
4884
4885         if (!dev->primary->master)
4886                 return;
4887
4888         master_priv = dev->primary->master->driver_priv;
4889         if (!master_priv->sarea_priv)
4890                 return;
4891
4892         switch (pipe) {
4893         case 0:
4894                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4895                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4896                 break;
4897         case 1:
4898                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4899                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4900                 break;
4901         default:
4902                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4903                 break;
4904         }
4905 }
4906
4907 /* Master function to enable/disable CRTC and corresponding power wells */
4908 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4909 {
4910         struct drm_device *dev = crtc->dev;
4911         struct drm_i915_private *dev_priv = dev->dev_private;
4912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4913         enum intel_display_power_domain domain;
4914         unsigned long domains;
4915
4916         if (enable) {
4917                 if (!intel_crtc->active) {
4918                         domains = get_crtc_power_domains(crtc);
4919                         for_each_power_domain(domain, domains)
4920                                 intel_display_power_get(dev_priv, domain);
4921                         intel_crtc->enabled_power_domains = domains;
4922
4923                         dev_priv->display.crtc_enable(crtc);
4924                 }
4925         } else {
4926                 if (intel_crtc->active) {
4927                         dev_priv->display.crtc_disable(crtc);
4928
4929                         domains = intel_crtc->enabled_power_domains;
4930                         for_each_power_domain(domain, domains)
4931                                 intel_display_power_put(dev_priv, domain);
4932                         intel_crtc->enabled_power_domains = 0;
4933                 }
4934         }
4935 }
4936
4937 /**
4938  * Sets the power management mode of the pipe and plane.
4939  */
4940 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4941 {
4942         struct drm_device *dev = crtc->dev;
4943         struct intel_encoder *intel_encoder;
4944         bool enable = false;
4945
4946         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4947                 enable |= intel_encoder->connectors_active;
4948
4949         intel_crtc_control(crtc, enable);
4950
4951         intel_crtc_update_sarea(crtc, enable);
4952 }
4953
4954 static void intel_crtc_disable(struct drm_crtc *crtc)
4955 {
4956         struct drm_device *dev = crtc->dev;
4957         struct drm_connector *connector;
4958         struct drm_i915_private *dev_priv = dev->dev_private;
4959         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4960         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4961
4962         /* crtc should still be enabled when we disable it. */
4963         WARN_ON(!crtc->enabled);
4964
4965         dev_priv->display.crtc_disable(crtc);
4966         intel_crtc_update_sarea(crtc, false);
4967         dev_priv->display.off(crtc);
4968
4969         if (crtc->primary->fb) {
4970                 mutex_lock(&dev->struct_mutex);
4971                 intel_unpin_fb_obj(old_obj);
4972                 i915_gem_track_fb(old_obj, NULL,
4973                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
4974                 mutex_unlock(&dev->struct_mutex);
4975                 crtc->primary->fb = NULL;
4976         }
4977
4978         /* Update computed state. */
4979         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4980                 if (!connector->encoder || !connector->encoder->crtc)
4981                         continue;
4982
4983                 if (connector->encoder->crtc != crtc)
4984                         continue;
4985
4986                 connector->dpms = DRM_MODE_DPMS_OFF;
4987                 to_intel_encoder(connector->encoder)->connectors_active = false;
4988         }
4989 }
4990
4991 void intel_encoder_destroy(struct drm_encoder *encoder)
4992 {
4993         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4994
4995         drm_encoder_cleanup(encoder);
4996         kfree(intel_encoder);
4997 }
4998
4999 /* Simple dpms helper for encoders with just one connector, no cloning and only
5000  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5001  * state of the entire output pipe. */
5002 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5003 {
5004         if (mode == DRM_MODE_DPMS_ON) {
5005                 encoder->connectors_active = true;
5006
5007                 intel_crtc_update_dpms(encoder->base.crtc);
5008         } else {
5009                 encoder->connectors_active = false;
5010
5011                 intel_crtc_update_dpms(encoder->base.crtc);
5012         }
5013 }
5014
5015 /* Cross check the actual hw state with our own modeset state tracking (and it's
5016  * internal consistency). */
5017 static void intel_connector_check_state(struct intel_connector *connector)
5018 {
5019         if (connector->get_hw_state(connector)) {
5020                 struct intel_encoder *encoder = connector->encoder;
5021                 struct drm_crtc *crtc;
5022                 bool encoder_enabled;
5023                 enum pipe pipe;
5024
5025                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5026                               connector->base.base.id,
5027                               connector->base.name);
5028
5029                 /* there is no real hw state for MST connectors */
5030                 if (connector->mst_port)
5031                         return;
5032
5033                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5034                      "wrong connector dpms state\n");
5035                 WARN(connector->base.encoder != &encoder->base,
5036                      "active connector not linked to encoder\n");
5037
5038                 if (encoder) {
5039                         WARN(!encoder->connectors_active,
5040                              "encoder->connectors_active not set\n");
5041
5042                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5043                         WARN(!encoder_enabled, "encoder not enabled\n");
5044                         if (WARN_ON(!encoder->base.crtc))
5045                                 return;
5046
5047                         crtc = encoder->base.crtc;
5048
5049                         WARN(!crtc->enabled, "crtc not enabled\n");
5050                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5051                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5052                              "encoder active on the wrong pipe\n");
5053                 }
5054         }
5055 }
5056
5057 /* Even simpler default implementation, if there's really no special case to
5058  * consider. */
5059 void intel_connector_dpms(struct drm_connector *connector, int mode)
5060 {
5061         /* All the simple cases only support two dpms states. */
5062         if (mode != DRM_MODE_DPMS_ON)
5063                 mode = DRM_MODE_DPMS_OFF;
5064
5065         if (mode == connector->dpms)
5066                 return;
5067
5068         connector->dpms = mode;
5069
5070         /* Only need to change hw state when actually enabled */
5071         if (connector->encoder)
5072                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5073
5074         intel_modeset_check_state(connector->dev);
5075 }
5076
5077 /* Simple connector->get_hw_state implementation for encoders that support only
5078  * one connector and no cloning and hence the encoder state determines the state
5079  * of the connector. */
5080 bool intel_connector_get_hw_state(struct intel_connector *connector)
5081 {
5082         enum pipe pipe = 0;
5083         struct intel_encoder *encoder = connector->encoder;
5084
5085         return encoder->get_hw_state(encoder, &pipe);
5086 }
5087
5088 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5089                                      struct intel_crtc_config *pipe_config)
5090 {
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092         struct intel_crtc *pipe_B_crtc =
5093                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5094
5095         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5096                       pipe_name(pipe), pipe_config->fdi_lanes);
5097         if (pipe_config->fdi_lanes > 4) {
5098                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5099                               pipe_name(pipe), pipe_config->fdi_lanes);
5100                 return false;
5101         }
5102
5103         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5104                 if (pipe_config->fdi_lanes > 2) {
5105                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5106                                       pipe_config->fdi_lanes);
5107                         return false;
5108                 } else {
5109                         return true;
5110                 }
5111         }
5112
5113         if (INTEL_INFO(dev)->num_pipes == 2)
5114                 return true;
5115
5116         /* Ivybridge 3 pipe is really complicated */
5117         switch (pipe) {
5118         case PIPE_A:
5119                 return true;
5120         case PIPE_B:
5121                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5122                     pipe_config->fdi_lanes > 2) {
5123                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5124                                       pipe_name(pipe), pipe_config->fdi_lanes);
5125                         return false;
5126                 }
5127                 return true;
5128         case PIPE_C:
5129                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5130                     pipe_B_crtc->config.fdi_lanes <= 2) {
5131                         if (pipe_config->fdi_lanes > 2) {
5132                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5133                                               pipe_name(pipe), pipe_config->fdi_lanes);
5134                                 return false;
5135                         }
5136                 } else {
5137                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5138                         return false;
5139                 }
5140                 return true;
5141         default:
5142                 BUG();
5143         }
5144 }
5145
5146 #define RETRY 1
5147 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5148                                        struct intel_crtc_config *pipe_config)
5149 {
5150         struct drm_device *dev = intel_crtc->base.dev;
5151         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5152         int lane, link_bw, fdi_dotclock;
5153         bool setup_ok, needs_recompute = false;
5154
5155 retry:
5156         /* FDI is a binary signal running at ~2.7GHz, encoding
5157          * each output octet as 10 bits. The actual frequency
5158          * is stored as a divider into a 100MHz clock, and the
5159          * mode pixel clock is stored in units of 1KHz.
5160          * Hence the bw of each lane in terms of the mode signal
5161          * is:
5162          */
5163         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5164
5165         fdi_dotclock = adjusted_mode->crtc_clock;
5166
5167         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5168                                            pipe_config->pipe_bpp);
5169
5170         pipe_config->fdi_lanes = lane;
5171
5172         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5173                                link_bw, &pipe_config->fdi_m_n);
5174
5175         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5176                                             intel_crtc->pipe, pipe_config);
5177         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5178                 pipe_config->pipe_bpp -= 2*3;
5179                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5180                               pipe_config->pipe_bpp);
5181                 needs_recompute = true;
5182                 pipe_config->bw_constrained = true;
5183
5184                 goto retry;
5185         }
5186
5187         if (needs_recompute)
5188                 return RETRY;
5189
5190         return setup_ok ? 0 : -EINVAL;
5191 }
5192
5193 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5194                                    struct intel_crtc_config *pipe_config)
5195 {
5196         pipe_config->ips_enabled = i915.enable_ips &&
5197                                    hsw_crtc_supports_ips(crtc) &&
5198                                    pipe_config->pipe_bpp <= 24;
5199 }
5200
5201 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5202                                      struct intel_crtc_config *pipe_config)
5203 {
5204         struct drm_device *dev = crtc->base.dev;
5205         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5206
5207         /* FIXME should check pixel clock limits on all platforms */
5208         if (INTEL_INFO(dev)->gen < 4) {
5209                 struct drm_i915_private *dev_priv = dev->dev_private;
5210                 int clock_limit =
5211                         dev_priv->display.get_display_clock_speed(dev);
5212
5213                 /*
5214                  * Enable pixel doubling when the dot clock
5215                  * is > 90% of the (display) core speed.
5216                  *
5217                  * GDG double wide on either pipe,
5218                  * otherwise pipe A only.
5219                  */
5220                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5221                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5222                         clock_limit *= 2;
5223                         pipe_config->double_wide = true;
5224                 }
5225
5226                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5227                         return -EINVAL;
5228         }
5229
5230         /*
5231          * Pipe horizontal size must be even in:
5232          * - DVO ganged mode
5233          * - LVDS dual channel mode
5234          * - Double wide pipe
5235          */
5236         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5237              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5238                 pipe_config->pipe_src_w &= ~1;
5239
5240         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5241          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5242          */
5243         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5244                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5245                 return -EINVAL;
5246
5247         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5248                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5249         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5250                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5251                  * for lvds. */
5252                 pipe_config->pipe_bpp = 8*3;
5253         }
5254
5255         if (HAS_IPS(dev))
5256                 hsw_compute_ips_config(crtc, pipe_config);
5257
5258         /*
5259          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5260          * old clock survives for now.
5261          */
5262         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5263                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5264
5265         if (pipe_config->has_pch_encoder)
5266                 return ironlake_fdi_compute_config(crtc, pipe_config);
5267
5268         return 0;
5269 }
5270
5271 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274         int vco = valleyview_get_vco(dev_priv);
5275         u32 val;
5276         int divider;
5277
5278         mutex_lock(&dev_priv->dpio_lock);
5279         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5280         mutex_unlock(&dev_priv->dpio_lock);
5281
5282         divider = val & DISPLAY_FREQUENCY_VALUES;
5283
5284         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5285              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5286              "cdclk change in progress\n");
5287
5288         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5289 }
5290
5291 static int i945_get_display_clock_speed(struct drm_device *dev)
5292 {
5293         return 400000;
5294 }
5295
5296 static int i915_get_display_clock_speed(struct drm_device *dev)
5297 {
5298         return 333000;
5299 }
5300
5301 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5302 {
5303         return 200000;
5304 }
5305
5306 static int pnv_get_display_clock_speed(struct drm_device *dev)
5307 {
5308         u16 gcfgc = 0;
5309
5310         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5311
5312         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5313         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5314                 return 267000;
5315         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5316                 return 333000;
5317         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5318                 return 444000;
5319         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5320                 return 200000;
5321         default:
5322                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5323         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5324                 return 133000;
5325         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5326                 return 167000;
5327         }
5328 }
5329
5330 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5331 {
5332         u16 gcfgc = 0;
5333
5334         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5335
5336         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5337                 return 133000;
5338         else {
5339                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5340                 case GC_DISPLAY_CLOCK_333_MHZ:
5341                         return 333000;
5342                 default:
5343                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5344                         return 190000;
5345                 }
5346         }
5347 }
5348
5349 static int i865_get_display_clock_speed(struct drm_device *dev)
5350 {
5351         return 266000;
5352 }
5353
5354 static int i855_get_display_clock_speed(struct drm_device *dev)
5355 {
5356         u16 hpllcc = 0;
5357         /* Assume that the hardware is in the high speed state.  This
5358          * should be the default.
5359          */
5360         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5361         case GC_CLOCK_133_200:
5362         case GC_CLOCK_100_200:
5363                 return 200000;
5364         case GC_CLOCK_166_250:
5365                 return 250000;
5366         case GC_CLOCK_100_133:
5367                 return 133000;
5368         }
5369
5370         /* Shouldn't happen */
5371         return 0;
5372 }
5373
5374 static int i830_get_display_clock_speed(struct drm_device *dev)
5375 {
5376         return 133000;
5377 }
5378
5379 static void
5380 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5381 {
5382         while (*num > DATA_LINK_M_N_MASK ||
5383                *den > DATA_LINK_M_N_MASK) {
5384                 *num >>= 1;
5385                 *den >>= 1;
5386         }
5387 }
5388
5389 static void compute_m_n(unsigned int m, unsigned int n,
5390                         uint32_t *ret_m, uint32_t *ret_n)
5391 {
5392         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5393         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5394         intel_reduce_m_n_ratio(ret_m, ret_n);
5395 }
5396
5397 void
5398 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5399                        int pixel_clock, int link_clock,
5400                        struct intel_link_m_n *m_n)
5401 {
5402         m_n->tu = 64;
5403
5404         compute_m_n(bits_per_pixel * pixel_clock,
5405                     link_clock * nlanes * 8,
5406                     &m_n->gmch_m, &m_n->gmch_n);
5407
5408         compute_m_n(pixel_clock, link_clock,
5409                     &m_n->link_m, &m_n->link_n);
5410 }
5411
5412 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5413 {
5414         if (i915.panel_use_ssc >= 0)
5415                 return i915.panel_use_ssc != 0;
5416         return dev_priv->vbt.lvds_use_ssc
5417                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5418 }
5419
5420 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5421 {
5422         struct drm_device *dev = crtc->dev;
5423         struct drm_i915_private *dev_priv = dev->dev_private;
5424         int refclk;
5425
5426         if (IS_VALLEYVIEW(dev)) {
5427                 refclk = 100000;
5428         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5429             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5430                 refclk = dev_priv->vbt.lvds_ssc_freq;
5431                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5432         } else if (!IS_GEN2(dev)) {
5433                 refclk = 96000;
5434         } else {
5435                 refclk = 48000;
5436         }
5437
5438         return refclk;
5439 }
5440
5441 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5442 {
5443         return (1 << dpll->n) << 16 | dpll->m2;
5444 }
5445
5446 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5447 {
5448         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5449 }
5450
5451 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5452                                      intel_clock_t *reduced_clock)
5453 {
5454         struct drm_device *dev = crtc->base.dev;
5455         u32 fp, fp2 = 0;
5456
5457         if (IS_PINEVIEW(dev)) {
5458                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5459                 if (reduced_clock)
5460                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5461         } else {
5462                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5463                 if (reduced_clock)
5464                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5465         }
5466
5467         crtc->config.dpll_hw_state.fp0 = fp;
5468
5469         crtc->lowfreq_avail = false;
5470         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5471             reduced_clock && i915.powersave) {
5472                 crtc->config.dpll_hw_state.fp1 = fp2;
5473                 crtc->lowfreq_avail = true;
5474         } else {
5475                 crtc->config.dpll_hw_state.fp1 = fp;
5476         }
5477 }
5478
5479 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5480                 pipe)
5481 {
5482         u32 reg_val;
5483
5484         /*
5485          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5486          * and set it to a reasonable value instead.
5487          */
5488         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5489         reg_val &= 0xffffff00;
5490         reg_val |= 0x00000030;
5491         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5492
5493         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5494         reg_val &= 0x8cffffff;
5495         reg_val = 0x8c000000;
5496         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5497
5498         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5499         reg_val &= 0xffffff00;
5500         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5501
5502         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5503         reg_val &= 0x00ffffff;
5504         reg_val |= 0xb0000000;
5505         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5506 }
5507
5508 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5509                                          struct intel_link_m_n *m_n)
5510 {
5511         struct drm_device *dev = crtc->base.dev;
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513         int pipe = crtc->pipe;
5514
5515         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5516         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5517         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5518         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5519 }
5520
5521 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5522                                          struct intel_link_m_n *m_n)
5523 {
5524         struct drm_device *dev = crtc->base.dev;
5525         struct drm_i915_private *dev_priv = dev->dev_private;
5526         int pipe = crtc->pipe;
5527         enum transcoder transcoder = crtc->config.cpu_transcoder;
5528
5529         if (INTEL_INFO(dev)->gen >= 5) {
5530                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5531                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5532                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5533                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5534         } else {
5535                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5536                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5537                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5538                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5539         }
5540 }
5541
5542 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5543 {
5544         if (crtc->config.has_pch_encoder)
5545                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5546         else
5547                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5548 }
5549
5550 static void vlv_update_pll(struct intel_crtc *crtc)
5551 {
5552         u32 dpll, dpll_md;
5553
5554         /*
5555          * Enable DPIO clock input. We should never disable the reference
5556          * clock for pipe B, since VGA hotplug / manual detection depends
5557          * on it.
5558          */
5559         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5560                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5561         /* We should never disable this, set it here for state tracking */
5562         if (crtc->pipe == PIPE_B)
5563                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5564         dpll |= DPLL_VCO_ENABLE;
5565         crtc->config.dpll_hw_state.dpll = dpll;
5566
5567         dpll_md = (crtc->config.pixel_multiplier - 1)
5568                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5569         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5570 }
5571
5572 static void vlv_prepare_pll(struct intel_crtc *crtc)
5573 {
5574         struct drm_device *dev = crtc->base.dev;
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576         int pipe = crtc->pipe;
5577         u32 mdiv;
5578         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5579         u32 coreclk, reg_val;
5580
5581         mutex_lock(&dev_priv->dpio_lock);
5582
5583         bestn = crtc->config.dpll.n;
5584         bestm1 = crtc->config.dpll.m1;
5585         bestm2 = crtc->config.dpll.m2;
5586         bestp1 = crtc->config.dpll.p1;
5587         bestp2 = crtc->config.dpll.p2;
5588
5589         /* See eDP HDMI DPIO driver vbios notes doc */
5590
5591         /* PLL B needs special handling */
5592         if (pipe == PIPE_B)
5593                 vlv_pllb_recal_opamp(dev_priv, pipe);
5594
5595         /* Set up Tx target for periodic Rcomp update */
5596         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5597
5598         /* Disable target IRef on PLL */
5599         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5600         reg_val &= 0x00ffffff;
5601         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5602
5603         /* Disable fast lock */
5604         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5605
5606         /* Set idtafcrecal before PLL is enabled */
5607         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5608         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5609         mdiv |= ((bestn << DPIO_N_SHIFT));
5610         mdiv |= (1 << DPIO_K_SHIFT);
5611
5612         /*
5613          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5614          * but we don't support that).
5615          * Note: don't use the DAC post divider as it seems unstable.
5616          */
5617         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5618         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5619
5620         mdiv |= DPIO_ENABLE_CALIBRATION;
5621         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5622
5623         /* Set HBR and RBR LPF coefficients */
5624         if (crtc->config.port_clock == 162000 ||
5625             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5626             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5627                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5628                                  0x009f0003);
5629         else
5630                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5631                                  0x00d0000f);
5632
5633         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5634             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5635                 /* Use SSC source */
5636                 if (pipe == PIPE_A)
5637                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5638                                          0x0df40000);
5639                 else
5640                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5641                                          0x0df70000);
5642         } else { /* HDMI or VGA */
5643                 /* Use bend source */
5644                 if (pipe == PIPE_A)
5645                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5646                                          0x0df70000);
5647                 else
5648                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5649                                          0x0df40000);
5650         }
5651
5652         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5653         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5654         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5655             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5656                 coreclk |= 0x01000000;
5657         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5658
5659         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5660         mutex_unlock(&dev_priv->dpio_lock);
5661 }
5662
5663 static void chv_update_pll(struct intel_crtc *crtc)
5664 {
5665         struct drm_device *dev = crtc->base.dev;
5666         struct drm_i915_private *dev_priv = dev->dev_private;
5667         int pipe = crtc->pipe;
5668         int dpll_reg = DPLL(crtc->pipe);
5669         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5670         u32 loopfilter, intcoeff;
5671         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5672         int refclk;
5673
5674         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5675                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5676                 DPLL_VCO_ENABLE;
5677         if (pipe != PIPE_A)
5678                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5679
5680         crtc->config.dpll_hw_state.dpll_md =
5681                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5682
5683         bestn = crtc->config.dpll.n;
5684         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5685         bestm1 = crtc->config.dpll.m1;
5686         bestm2 = crtc->config.dpll.m2 >> 22;
5687         bestp1 = crtc->config.dpll.p1;
5688         bestp2 = crtc->config.dpll.p2;
5689
5690         /*
5691          * Enable Refclk and SSC
5692          */
5693         I915_WRITE(dpll_reg,
5694                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5695
5696         mutex_lock(&dev_priv->dpio_lock);
5697
5698         /* p1 and p2 divider */
5699         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5700                         5 << DPIO_CHV_S1_DIV_SHIFT |
5701                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5702                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5703                         1 << DPIO_CHV_K_DIV_SHIFT);
5704
5705         /* Feedback post-divider - m2 */
5706         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5707
5708         /* Feedback refclk divider - n and m1 */
5709         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5710                         DPIO_CHV_M1_DIV_BY_2 |
5711                         1 << DPIO_CHV_N_DIV_SHIFT);
5712
5713         /* M2 fraction division */
5714         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5715
5716         /* M2 fraction division enable */
5717         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5718                        DPIO_CHV_FRAC_DIV_EN |
5719                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5720
5721         /* Loop filter */
5722         refclk = i9xx_get_refclk(&crtc->base, 0);
5723         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5724                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5725         if (refclk == 100000)
5726                 intcoeff = 11;
5727         else if (refclk == 38400)
5728                 intcoeff = 10;
5729         else
5730                 intcoeff = 9;
5731         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5732         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5733
5734         /* AFC Recal */
5735         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5736                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5737                         DPIO_AFC_RECAL);
5738
5739         mutex_unlock(&dev_priv->dpio_lock);
5740 }
5741
5742 static void i9xx_update_pll(struct intel_crtc *crtc,
5743                             intel_clock_t *reduced_clock,
5744                             int num_connectors)
5745 {
5746         struct drm_device *dev = crtc->base.dev;
5747         struct drm_i915_private *dev_priv = dev->dev_private;
5748         u32 dpll;
5749         bool is_sdvo;
5750         struct dpll *clock = &crtc->config.dpll;
5751
5752         i9xx_update_pll_dividers(crtc, reduced_clock);
5753
5754         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5755                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5756
5757         dpll = DPLL_VGA_MODE_DIS;
5758
5759         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5760                 dpll |= DPLLB_MODE_LVDS;
5761         else
5762                 dpll |= DPLLB_MODE_DAC_SERIAL;
5763
5764         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5765                 dpll |= (crtc->config.pixel_multiplier - 1)
5766                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5767         }
5768
5769         if (is_sdvo)
5770                 dpll |= DPLL_SDVO_HIGH_SPEED;
5771
5772         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5773                 dpll |= DPLL_SDVO_HIGH_SPEED;
5774
5775         /* compute bitmask from p1 value */
5776         if (IS_PINEVIEW(dev))
5777                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5778         else {
5779                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5780                 if (IS_G4X(dev) && reduced_clock)
5781                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5782         }
5783         switch (clock->p2) {
5784         case 5:
5785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5786                 break;
5787         case 7:
5788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5789                 break;
5790         case 10:
5791                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5792                 break;
5793         case 14:
5794                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5795                 break;
5796         }
5797         if (INTEL_INFO(dev)->gen >= 4)
5798                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5799
5800         if (crtc->config.sdvo_tv_clock)
5801                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5802         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5803                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5804                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5805         else
5806                 dpll |= PLL_REF_INPUT_DREFCLK;
5807
5808         dpll |= DPLL_VCO_ENABLE;
5809         crtc->config.dpll_hw_state.dpll = dpll;
5810
5811         if (INTEL_INFO(dev)->gen >= 4) {
5812                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5813                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5814                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5815         }
5816 }
5817
5818 static void i8xx_update_pll(struct intel_crtc *crtc,
5819                             intel_clock_t *reduced_clock,
5820                             int num_connectors)
5821 {
5822         struct drm_device *dev = crtc->base.dev;
5823         struct drm_i915_private *dev_priv = dev->dev_private;
5824         u32 dpll;
5825         struct dpll *clock = &crtc->config.dpll;
5826
5827         i9xx_update_pll_dividers(crtc, reduced_clock);
5828
5829         dpll = DPLL_VGA_MODE_DIS;
5830
5831         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5832                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5833         } else {
5834                 if (clock->p1 == 2)
5835                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5836                 else
5837                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5838                 if (clock->p2 == 4)
5839                         dpll |= PLL_P2_DIVIDE_BY_4;
5840         }
5841
5842         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5843                 dpll |= DPLL_DVO_2X_MODE;
5844
5845         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5846                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5847                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5848         else
5849                 dpll |= PLL_REF_INPUT_DREFCLK;
5850
5851         dpll |= DPLL_VCO_ENABLE;
5852         crtc->config.dpll_hw_state.dpll = dpll;
5853 }
5854
5855 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5856 {
5857         struct drm_device *dev = intel_crtc->base.dev;
5858         struct drm_i915_private *dev_priv = dev->dev_private;
5859         enum pipe pipe = intel_crtc->pipe;
5860         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5861         struct drm_display_mode *adjusted_mode =
5862                 &intel_crtc->config.adjusted_mode;
5863         uint32_t crtc_vtotal, crtc_vblank_end;
5864         int vsyncshift = 0;
5865
5866         /* We need to be careful not to changed the adjusted mode, for otherwise
5867          * the hw state checker will get angry at the mismatch. */
5868         crtc_vtotal = adjusted_mode->crtc_vtotal;
5869         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5870
5871         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5872                 /* the chip adds 2 halflines automatically */
5873                 crtc_vtotal -= 1;
5874                 crtc_vblank_end -= 1;
5875
5876                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5877                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5878                 else
5879                         vsyncshift = adjusted_mode->crtc_hsync_start -
5880                                 adjusted_mode->crtc_htotal / 2;
5881                 if (vsyncshift < 0)
5882                         vsyncshift += adjusted_mode->crtc_htotal;
5883         }
5884
5885         if (INTEL_INFO(dev)->gen > 3)
5886                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5887
5888         I915_WRITE(HTOTAL(cpu_transcoder),
5889                    (adjusted_mode->crtc_hdisplay - 1) |
5890                    ((adjusted_mode->crtc_htotal - 1) << 16));
5891         I915_WRITE(HBLANK(cpu_transcoder),
5892                    (adjusted_mode->crtc_hblank_start - 1) |
5893                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5894         I915_WRITE(HSYNC(cpu_transcoder),
5895                    (adjusted_mode->crtc_hsync_start - 1) |
5896                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5897
5898         I915_WRITE(VTOTAL(cpu_transcoder),
5899                    (adjusted_mode->crtc_vdisplay - 1) |
5900                    ((crtc_vtotal - 1) << 16));
5901         I915_WRITE(VBLANK(cpu_transcoder),
5902                    (adjusted_mode->crtc_vblank_start - 1) |
5903                    ((crtc_vblank_end - 1) << 16));
5904         I915_WRITE(VSYNC(cpu_transcoder),
5905                    (adjusted_mode->crtc_vsync_start - 1) |
5906                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5907
5908         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5909          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5910          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5911          * bits. */
5912         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5913             (pipe == PIPE_B || pipe == PIPE_C))
5914                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5915
5916         /* pipesrc controls the size that is scaled from, which should
5917          * always be the user's requested size.
5918          */
5919         I915_WRITE(PIPESRC(pipe),
5920                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5921                    (intel_crtc->config.pipe_src_h - 1));
5922 }
5923
5924 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5925                                    struct intel_crtc_config *pipe_config)
5926 {
5927         struct drm_device *dev = crtc->base.dev;
5928         struct drm_i915_private *dev_priv = dev->dev_private;
5929         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5930         uint32_t tmp;
5931
5932         tmp = I915_READ(HTOTAL(cpu_transcoder));
5933         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5934         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5935         tmp = I915_READ(HBLANK(cpu_transcoder));
5936         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5937         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5938         tmp = I915_READ(HSYNC(cpu_transcoder));
5939         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5940         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5941
5942         tmp = I915_READ(VTOTAL(cpu_transcoder));
5943         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5944         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5945         tmp = I915_READ(VBLANK(cpu_transcoder));
5946         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5947         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5948         tmp = I915_READ(VSYNC(cpu_transcoder));
5949         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5950         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5951
5952         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5953                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5954                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5955                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5956         }
5957
5958         tmp = I915_READ(PIPESRC(crtc->pipe));
5959         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5960         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5961
5962         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5963         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5964 }
5965
5966 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5967                                  struct intel_crtc_config *pipe_config)
5968 {
5969         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5970         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5971         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5972         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5973
5974         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5975         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5976         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5977         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5978
5979         mode->flags = pipe_config->adjusted_mode.flags;
5980
5981         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5982         mode->flags |= pipe_config->adjusted_mode.flags;
5983 }
5984
5985 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5986 {
5987         struct drm_device *dev = intel_crtc->base.dev;
5988         struct drm_i915_private *dev_priv = dev->dev_private;
5989         uint32_t pipeconf;
5990
5991         pipeconf = 0;
5992
5993         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5994             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5995                 pipeconf |= PIPECONF_ENABLE;
5996
5997         if (intel_crtc->config.double_wide)
5998                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5999
6000         /* only g4x and later have fancy bpc/dither controls */
6001         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6002                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6003                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6004                         pipeconf |= PIPECONF_DITHER_EN |
6005                                     PIPECONF_DITHER_TYPE_SP;
6006
6007                 switch (intel_crtc->config.pipe_bpp) {
6008                 case 18:
6009                         pipeconf |= PIPECONF_6BPC;
6010                         break;
6011                 case 24:
6012                         pipeconf |= PIPECONF_8BPC;
6013                         break;
6014                 case 30:
6015                         pipeconf |= PIPECONF_10BPC;
6016                         break;
6017                 default:
6018                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6019                         BUG();
6020                 }
6021         }
6022
6023         if (HAS_PIPE_CXSR(dev)) {
6024                 if (intel_crtc->lowfreq_avail) {
6025                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6026                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6027                 } else {
6028                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6029                 }
6030         }
6031
6032         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6033                 if (INTEL_INFO(dev)->gen < 4 ||
6034                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6035                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6036                 else
6037                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6038         } else
6039                 pipeconf |= PIPECONF_PROGRESSIVE;
6040
6041         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6042                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6043
6044         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6045         POSTING_READ(PIPECONF(intel_crtc->pipe));
6046 }
6047
6048 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6049                               int x, int y,
6050                               struct drm_framebuffer *fb)
6051 {
6052         struct drm_device *dev = crtc->dev;
6053         struct drm_i915_private *dev_priv = dev->dev_private;
6054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055         int refclk, num_connectors = 0;
6056         intel_clock_t clock, reduced_clock;
6057         bool ok, has_reduced_clock = false;
6058         bool is_lvds = false, is_dsi = false;
6059         struct intel_encoder *encoder;
6060         const intel_limit_t *limit;
6061
6062         for_each_encoder_on_crtc(dev, crtc, encoder) {
6063                 switch (encoder->type) {
6064                 case INTEL_OUTPUT_LVDS:
6065                         is_lvds = true;
6066                         break;
6067                 case INTEL_OUTPUT_DSI:
6068                         is_dsi = true;
6069                         break;
6070                 }
6071
6072                 num_connectors++;
6073         }
6074
6075         if (is_dsi)
6076                 return 0;
6077
6078         if (!intel_crtc->config.clock_set) {
6079                 refclk = i9xx_get_refclk(crtc, num_connectors);
6080
6081                 /*
6082                  * Returns a set of divisors for the desired target clock with
6083                  * the given refclk, or FALSE.  The returned values represent
6084                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6085                  * 2) / p1 / p2.
6086                  */
6087                 limit = intel_limit(crtc, refclk);
6088                 ok = dev_priv->display.find_dpll(limit, crtc,
6089                                                  intel_crtc->config.port_clock,
6090                                                  refclk, NULL, &clock);
6091                 if (!ok) {
6092                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6093                         return -EINVAL;
6094                 }
6095
6096                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6097                         /*
6098                          * Ensure we match the reduced clock's P to the target
6099                          * clock.  If the clocks don't match, we can't switch
6100                          * the display clock by using the FP0/FP1. In such case
6101                          * we will disable the LVDS downclock feature.
6102                          */
6103                         has_reduced_clock =
6104                                 dev_priv->display.find_dpll(limit, crtc,
6105                                                             dev_priv->lvds_downclock,
6106                                                             refclk, &clock,
6107                                                             &reduced_clock);
6108                 }
6109                 /* Compat-code for transition, will disappear. */
6110                 intel_crtc->config.dpll.n = clock.n;
6111                 intel_crtc->config.dpll.m1 = clock.m1;
6112                 intel_crtc->config.dpll.m2 = clock.m2;
6113                 intel_crtc->config.dpll.p1 = clock.p1;
6114                 intel_crtc->config.dpll.p2 = clock.p2;
6115         }
6116
6117         if (IS_GEN2(dev)) {
6118                 i8xx_update_pll(intel_crtc,
6119                                 has_reduced_clock ? &reduced_clock : NULL,
6120                                 num_connectors);
6121         } else if (IS_CHERRYVIEW(dev)) {
6122                 chv_update_pll(intel_crtc);
6123         } else if (IS_VALLEYVIEW(dev)) {
6124                 vlv_update_pll(intel_crtc);
6125         } else {
6126                 i9xx_update_pll(intel_crtc,
6127                                 has_reduced_clock ? &reduced_clock : NULL,
6128                                 num_connectors);
6129         }
6130
6131         return 0;
6132 }
6133
6134 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6135                                  struct intel_crtc_config *pipe_config)
6136 {
6137         struct drm_device *dev = crtc->base.dev;
6138         struct drm_i915_private *dev_priv = dev->dev_private;
6139         uint32_t tmp;
6140
6141         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6142                 return;
6143
6144         tmp = I915_READ(PFIT_CONTROL);
6145         if (!(tmp & PFIT_ENABLE))
6146                 return;
6147
6148         /* Check whether the pfit is attached to our pipe. */
6149         if (INTEL_INFO(dev)->gen < 4) {
6150                 if (crtc->pipe != PIPE_B)
6151                         return;
6152         } else {
6153                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6154                         return;
6155         }
6156
6157         pipe_config->gmch_pfit.control = tmp;
6158         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6159         if (INTEL_INFO(dev)->gen < 5)
6160                 pipe_config->gmch_pfit.lvds_border_bits =
6161                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6162 }
6163
6164 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6165                                struct intel_crtc_config *pipe_config)
6166 {
6167         struct drm_device *dev = crtc->base.dev;
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169         int pipe = pipe_config->cpu_transcoder;
6170         intel_clock_t clock;
6171         u32 mdiv;
6172         int refclk = 100000;
6173
6174         mutex_lock(&dev_priv->dpio_lock);
6175         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6176         mutex_unlock(&dev_priv->dpio_lock);
6177
6178         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6179         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6180         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6181         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6182         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6183
6184         vlv_clock(refclk, &clock);
6185
6186         /* clock.dot is the fast clock */
6187         pipe_config->port_clock = clock.dot / 5;
6188 }
6189
6190 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6191                                   struct intel_plane_config *plane_config)
6192 {
6193         struct drm_device *dev = crtc->base.dev;
6194         struct drm_i915_private *dev_priv = dev->dev_private;
6195         u32 val, base, offset;
6196         int pipe = crtc->pipe, plane = crtc->plane;
6197         int fourcc, pixel_format;
6198         int aligned_height;
6199
6200         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6201         if (!crtc->base.primary->fb) {
6202                 DRM_DEBUG_KMS("failed to alloc fb\n");
6203                 return;
6204         }
6205
6206         val = I915_READ(DSPCNTR(plane));
6207
6208         if (INTEL_INFO(dev)->gen >= 4)
6209                 if (val & DISPPLANE_TILED)
6210                         plane_config->tiled = true;
6211
6212         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6213         fourcc = intel_format_to_fourcc(pixel_format);
6214         crtc->base.primary->fb->pixel_format = fourcc;
6215         crtc->base.primary->fb->bits_per_pixel =
6216                 drm_format_plane_cpp(fourcc, 0) * 8;
6217
6218         if (INTEL_INFO(dev)->gen >= 4) {
6219                 if (plane_config->tiled)
6220                         offset = I915_READ(DSPTILEOFF(plane));
6221                 else
6222                         offset = I915_READ(DSPLINOFF(plane));
6223                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6224         } else {
6225                 base = I915_READ(DSPADDR(plane));
6226         }
6227         plane_config->base = base;
6228
6229         val = I915_READ(PIPESRC(pipe));
6230         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6231         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6232
6233         val = I915_READ(DSPSTRIDE(pipe));
6234         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6235
6236         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6237                                             plane_config->tiled);
6238
6239         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6240                                         aligned_height);
6241
6242         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6243                       pipe, plane, crtc->base.primary->fb->width,
6244                       crtc->base.primary->fb->height,
6245                       crtc->base.primary->fb->bits_per_pixel, base,
6246                       crtc->base.primary->fb->pitches[0],
6247                       plane_config->size);
6248
6249 }
6250
6251 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6252                                struct intel_crtc_config *pipe_config)
6253 {
6254         struct drm_device *dev = crtc->base.dev;
6255         struct drm_i915_private *dev_priv = dev->dev_private;
6256         int pipe = pipe_config->cpu_transcoder;
6257         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6258         intel_clock_t clock;
6259         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6260         int refclk = 100000;
6261
6262         mutex_lock(&dev_priv->dpio_lock);
6263         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6264         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6265         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6266         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6267         mutex_unlock(&dev_priv->dpio_lock);
6268
6269         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6270         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6271         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6272         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6273         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6274
6275         chv_clock(refclk, &clock);
6276
6277         /* clock.dot is the fast clock */
6278         pipe_config->port_clock = clock.dot / 5;
6279 }
6280
6281 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6282                                  struct intel_crtc_config *pipe_config)
6283 {
6284         struct drm_device *dev = crtc->base.dev;
6285         struct drm_i915_private *dev_priv = dev->dev_private;
6286         uint32_t tmp;
6287
6288         if (!intel_display_power_enabled(dev_priv,
6289                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6290                 return false;
6291
6292         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6293         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6294
6295         tmp = I915_READ(PIPECONF(crtc->pipe));
6296         if (!(tmp & PIPECONF_ENABLE))
6297                 return false;
6298
6299         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6300                 switch (tmp & PIPECONF_BPC_MASK) {
6301                 case PIPECONF_6BPC:
6302                         pipe_config->pipe_bpp = 18;
6303                         break;
6304                 case PIPECONF_8BPC:
6305                         pipe_config->pipe_bpp = 24;
6306                         break;
6307                 case PIPECONF_10BPC:
6308                         pipe_config->pipe_bpp = 30;
6309                         break;
6310                 default:
6311                         break;
6312                 }
6313         }
6314
6315         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6316                 pipe_config->limited_color_range = true;
6317
6318         if (INTEL_INFO(dev)->gen < 4)
6319                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6320
6321         intel_get_pipe_timings(crtc, pipe_config);
6322
6323         i9xx_get_pfit_config(crtc, pipe_config);
6324
6325         if (INTEL_INFO(dev)->gen >= 4) {
6326                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6327                 pipe_config->pixel_multiplier =
6328                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6329                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6330                 pipe_config->dpll_hw_state.dpll_md = tmp;
6331         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6332                 tmp = I915_READ(DPLL(crtc->pipe));
6333                 pipe_config->pixel_multiplier =
6334                         ((tmp & SDVO_MULTIPLIER_MASK)
6335                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6336         } else {
6337                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6338                  * port and will be fixed up in the encoder->get_config
6339                  * function. */
6340                 pipe_config->pixel_multiplier = 1;
6341         }
6342         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6343         if (!IS_VALLEYVIEW(dev)) {
6344                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6345                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6346         } else {
6347                 /* Mask out read-only status bits. */
6348                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6349                                                      DPLL_PORTC_READY_MASK |
6350                                                      DPLL_PORTB_READY_MASK);
6351         }
6352
6353         if (IS_CHERRYVIEW(dev))
6354                 chv_crtc_clock_get(crtc, pipe_config);
6355         else if (IS_VALLEYVIEW(dev))
6356                 vlv_crtc_clock_get(crtc, pipe_config);
6357         else
6358                 i9xx_crtc_clock_get(crtc, pipe_config);
6359
6360         return true;
6361 }
6362
6363 static void ironlake_init_pch_refclk(struct drm_device *dev)
6364 {
6365         struct drm_i915_private *dev_priv = dev->dev_private;
6366         struct drm_mode_config *mode_config = &dev->mode_config;
6367         struct intel_encoder *encoder;
6368         u32 val, final;
6369         bool has_lvds = false;
6370         bool has_cpu_edp = false;
6371         bool has_panel = false;
6372         bool has_ck505 = false;
6373         bool can_ssc = false;
6374
6375         /* We need to take the global config into account */
6376         list_for_each_entry(encoder, &mode_config->encoder_list,
6377                             base.head) {
6378                 switch (encoder->type) {
6379                 case INTEL_OUTPUT_LVDS:
6380                         has_panel = true;
6381                         has_lvds = true;
6382                         break;
6383                 case INTEL_OUTPUT_EDP:
6384                         has_panel = true;
6385                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6386                                 has_cpu_edp = true;
6387                         break;
6388                 }
6389         }
6390
6391         if (HAS_PCH_IBX(dev)) {
6392                 has_ck505 = dev_priv->vbt.display_clock_mode;
6393                 can_ssc = has_ck505;
6394         } else {
6395                 has_ck505 = false;
6396                 can_ssc = true;
6397         }
6398
6399         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6400                       has_panel, has_lvds, has_ck505);
6401
6402         /* Ironlake: try to setup display ref clock before DPLL
6403          * enabling. This is only under driver's control after
6404          * PCH B stepping, previous chipset stepping should be
6405          * ignoring this setting.
6406          */
6407         val = I915_READ(PCH_DREF_CONTROL);
6408
6409         /* As we must carefully and slowly disable/enable each source in turn,
6410          * compute the final state we want first and check if we need to
6411          * make any changes at all.
6412          */
6413         final = val;
6414         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6415         if (has_ck505)
6416                 final |= DREF_NONSPREAD_CK505_ENABLE;
6417         else
6418                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6419
6420         final &= ~DREF_SSC_SOURCE_MASK;
6421         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6422         final &= ~DREF_SSC1_ENABLE;
6423
6424         if (has_panel) {
6425                 final |= DREF_SSC_SOURCE_ENABLE;
6426
6427                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6428                         final |= DREF_SSC1_ENABLE;
6429
6430                 if (has_cpu_edp) {
6431                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6432                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6433                         else
6434                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6435                 } else
6436                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6437         } else {
6438                 final |= DREF_SSC_SOURCE_DISABLE;
6439                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6440         }
6441
6442         if (final == val)
6443                 return;
6444
6445         /* Always enable nonspread source */
6446         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6447
6448         if (has_ck505)
6449                 val |= DREF_NONSPREAD_CK505_ENABLE;
6450         else
6451                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6452
6453         if (has_panel) {
6454                 val &= ~DREF_SSC_SOURCE_MASK;
6455                 val |= DREF_SSC_SOURCE_ENABLE;
6456
6457                 /* SSC must be turned on before enabling the CPU output  */
6458                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6459                         DRM_DEBUG_KMS("Using SSC on panel\n");
6460                         val |= DREF_SSC1_ENABLE;
6461                 } else
6462                         val &= ~DREF_SSC1_ENABLE;
6463
6464                 /* Get SSC going before enabling the outputs */
6465                 I915_WRITE(PCH_DREF_CONTROL, val);
6466                 POSTING_READ(PCH_DREF_CONTROL);
6467                 udelay(200);
6468
6469                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6470
6471                 /* Enable CPU source on CPU attached eDP */
6472                 if (has_cpu_edp) {
6473                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6474                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6475                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6476                         } else
6477                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6478                 } else
6479                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6480
6481                 I915_WRITE(PCH_DREF_CONTROL, val);
6482                 POSTING_READ(PCH_DREF_CONTROL);
6483                 udelay(200);
6484         } else {
6485                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6486
6487                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6488
6489                 /* Turn off CPU output */
6490                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6491
6492                 I915_WRITE(PCH_DREF_CONTROL, val);
6493                 POSTING_READ(PCH_DREF_CONTROL);
6494                 udelay(200);
6495
6496                 /* Turn off the SSC source */
6497                 val &= ~DREF_SSC_SOURCE_MASK;
6498                 val |= DREF_SSC_SOURCE_DISABLE;
6499
6500                 /* Turn off SSC1 */
6501                 val &= ~DREF_SSC1_ENABLE;
6502
6503                 I915_WRITE(PCH_DREF_CONTROL, val);
6504                 POSTING_READ(PCH_DREF_CONTROL);
6505                 udelay(200);
6506         }
6507
6508         BUG_ON(val != final);
6509 }
6510
6511 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6512 {
6513         uint32_t tmp;
6514
6515         tmp = I915_READ(SOUTH_CHICKEN2);
6516         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6517         I915_WRITE(SOUTH_CHICKEN2, tmp);
6518
6519         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6520                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6521                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6522
6523         tmp = I915_READ(SOUTH_CHICKEN2);
6524         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6525         I915_WRITE(SOUTH_CHICKEN2, tmp);
6526
6527         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6528                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6529                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6530 }
6531
6532 /* WaMPhyProgramming:hsw */
6533 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6534 {
6535         uint32_t tmp;
6536
6537         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6538         tmp &= ~(0xFF << 24);
6539         tmp |= (0x12 << 24);
6540         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6541
6542         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6543         tmp |= (1 << 11);
6544         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6545
6546         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6547         tmp |= (1 << 11);
6548         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6549
6550         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6551         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6552         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6553
6554         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6555         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6556         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6557
6558         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6559         tmp &= ~(7 << 13);
6560         tmp |= (5 << 13);
6561         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6562
6563         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6564         tmp &= ~(7 << 13);
6565         tmp |= (5 << 13);
6566         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6567
6568         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6569         tmp &= ~0xFF;
6570         tmp |= 0x1C;
6571         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6572
6573         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6574         tmp &= ~0xFF;
6575         tmp |= 0x1C;
6576         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6577
6578         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6579         tmp &= ~(0xFF << 16);
6580         tmp |= (0x1C << 16);
6581         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6582
6583         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6584         tmp &= ~(0xFF << 16);
6585         tmp |= (0x1C << 16);
6586         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6587
6588         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6589         tmp |= (1 << 27);
6590         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6591
6592         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6593         tmp |= (1 << 27);
6594         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6595
6596         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6597         tmp &= ~(0xF << 28);
6598         tmp |= (4 << 28);
6599         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6600
6601         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6602         tmp &= ~(0xF << 28);
6603         tmp |= (4 << 28);
6604         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6605 }
6606
6607 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6608  * Programming" based on the parameters passed:
6609  * - Sequence to enable CLKOUT_DP
6610  * - Sequence to enable CLKOUT_DP without spread
6611  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6612  */
6613 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6614                                  bool with_fdi)
6615 {
6616         struct drm_i915_private *dev_priv = dev->dev_private;
6617         uint32_t reg, tmp;
6618
6619         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6620                 with_spread = true;
6621         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6622                  with_fdi, "LP PCH doesn't have FDI\n"))
6623                 with_fdi = false;
6624
6625         mutex_lock(&dev_priv->dpio_lock);
6626
6627         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6628         tmp &= ~SBI_SSCCTL_DISABLE;
6629         tmp |= SBI_SSCCTL_PATHALT;
6630         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6631
6632         udelay(24);
6633
6634         if (with_spread) {
6635                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6636                 tmp &= ~SBI_SSCCTL_PATHALT;
6637                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6638
6639                 if (with_fdi) {
6640                         lpt_reset_fdi_mphy(dev_priv);
6641                         lpt_program_fdi_mphy(dev_priv);
6642                 }
6643         }
6644
6645         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6646                SBI_GEN0 : SBI_DBUFF0;
6647         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6648         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6649         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6650
6651         mutex_unlock(&dev_priv->dpio_lock);
6652 }
6653
6654 /* Sequence to disable CLKOUT_DP */
6655 static void lpt_disable_clkout_dp(struct drm_device *dev)
6656 {
6657         struct drm_i915_private *dev_priv = dev->dev_private;
6658         uint32_t reg, tmp;
6659
6660         mutex_lock(&dev_priv->dpio_lock);
6661
6662         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6663                SBI_GEN0 : SBI_DBUFF0;
6664         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6665         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6666         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6667
6668         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6669         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6670                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6671                         tmp |= SBI_SSCCTL_PATHALT;
6672                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6673                         udelay(32);
6674                 }
6675                 tmp |= SBI_SSCCTL_DISABLE;
6676                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6677         }
6678
6679         mutex_unlock(&dev_priv->dpio_lock);
6680 }
6681
6682 static void lpt_init_pch_refclk(struct drm_device *dev)
6683 {
6684         struct drm_mode_config *mode_config = &dev->mode_config;
6685         struct intel_encoder *encoder;
6686         bool has_vga = false;
6687
6688         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6689                 switch (encoder->type) {
6690                 case INTEL_OUTPUT_ANALOG:
6691                         has_vga = true;
6692                         break;
6693                 }
6694         }
6695
6696         if (has_vga)
6697                 lpt_enable_clkout_dp(dev, true, true);
6698         else
6699                 lpt_disable_clkout_dp(dev);
6700 }
6701
6702 /*
6703  * Initialize reference clocks when the driver loads
6704  */
6705 void intel_init_pch_refclk(struct drm_device *dev)
6706 {
6707         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6708                 ironlake_init_pch_refclk(dev);
6709         else if (HAS_PCH_LPT(dev))
6710                 lpt_init_pch_refclk(dev);
6711 }
6712
6713 static int ironlake_get_refclk(struct drm_crtc *crtc)
6714 {
6715         struct drm_device *dev = crtc->dev;
6716         struct drm_i915_private *dev_priv = dev->dev_private;
6717         struct intel_encoder *encoder;
6718         int num_connectors = 0;
6719         bool is_lvds = false;
6720
6721         for_each_encoder_on_crtc(dev, crtc, encoder) {
6722                 switch (encoder->type) {
6723                 case INTEL_OUTPUT_LVDS:
6724                         is_lvds = true;
6725                         break;
6726                 }
6727                 num_connectors++;
6728         }
6729
6730         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6731                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6732                               dev_priv->vbt.lvds_ssc_freq);
6733                 return dev_priv->vbt.lvds_ssc_freq;
6734         }
6735
6736         return 120000;
6737 }
6738
6739 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6740 {
6741         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6743         int pipe = intel_crtc->pipe;
6744         uint32_t val;
6745
6746         val = 0;
6747
6748         switch (intel_crtc->config.pipe_bpp) {
6749         case 18:
6750                 val |= PIPECONF_6BPC;
6751                 break;
6752         case 24:
6753                 val |= PIPECONF_8BPC;
6754                 break;
6755         case 30:
6756                 val |= PIPECONF_10BPC;
6757                 break;
6758         case 36:
6759                 val |= PIPECONF_12BPC;
6760                 break;
6761         default:
6762                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6763                 BUG();
6764         }
6765
6766         if (intel_crtc->config.dither)
6767                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6768
6769         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6770                 val |= PIPECONF_INTERLACED_ILK;
6771         else
6772                 val |= PIPECONF_PROGRESSIVE;
6773
6774         if (intel_crtc->config.limited_color_range)
6775                 val |= PIPECONF_COLOR_RANGE_SELECT;
6776
6777         I915_WRITE(PIPECONF(pipe), val);
6778         POSTING_READ(PIPECONF(pipe));
6779 }
6780
6781 /*
6782  * Set up the pipe CSC unit.
6783  *
6784  * Currently only full range RGB to limited range RGB conversion
6785  * is supported, but eventually this should handle various
6786  * RGB<->YCbCr scenarios as well.
6787  */
6788 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6789 {
6790         struct drm_device *dev = crtc->dev;
6791         struct drm_i915_private *dev_priv = dev->dev_private;
6792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6793         int pipe = intel_crtc->pipe;
6794         uint16_t coeff = 0x7800; /* 1.0 */
6795
6796         /*
6797          * TODO: Check what kind of values actually come out of the pipe
6798          * with these coeff/postoff values and adjust to get the best
6799          * accuracy. Perhaps we even need to take the bpc value into
6800          * consideration.
6801          */
6802
6803         if (intel_crtc->config.limited_color_range)
6804                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6805
6806         /*
6807          * GY/GU and RY/RU should be the other way around according
6808          * to BSpec, but reality doesn't agree. Just set them up in
6809          * a way that results in the correct picture.
6810          */
6811         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6812         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6813
6814         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6815         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6816
6817         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6818         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6819
6820         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6821         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6822         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6823
6824         if (INTEL_INFO(dev)->gen > 6) {
6825                 uint16_t postoff = 0;
6826
6827                 if (intel_crtc->config.limited_color_range)
6828                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6829
6830                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6831                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6832                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6833
6834                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6835         } else {
6836                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6837
6838                 if (intel_crtc->config.limited_color_range)
6839                         mode |= CSC_BLACK_SCREEN_OFFSET;
6840
6841                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6842         }
6843 }
6844
6845 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6846 {
6847         struct drm_device *dev = crtc->dev;
6848         struct drm_i915_private *dev_priv = dev->dev_private;
6849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6850         enum pipe pipe = intel_crtc->pipe;
6851         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6852         uint32_t val;
6853
6854         val = 0;
6855
6856         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6857                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6858
6859         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6860                 val |= PIPECONF_INTERLACED_ILK;
6861         else
6862                 val |= PIPECONF_PROGRESSIVE;
6863
6864         I915_WRITE(PIPECONF(cpu_transcoder), val);
6865         POSTING_READ(PIPECONF(cpu_transcoder));
6866
6867         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6868         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6869
6870         if (IS_BROADWELL(dev)) {
6871                 val = 0;
6872
6873                 switch (intel_crtc->config.pipe_bpp) {
6874                 case 18:
6875                         val |= PIPEMISC_DITHER_6_BPC;
6876                         break;
6877                 case 24:
6878                         val |= PIPEMISC_DITHER_8_BPC;
6879                         break;
6880                 case 30:
6881                         val |= PIPEMISC_DITHER_10_BPC;
6882                         break;
6883                 case 36:
6884                         val |= PIPEMISC_DITHER_12_BPC;
6885                         break;
6886                 default:
6887                         /* Case prevented by pipe_config_set_bpp. */
6888                         BUG();
6889                 }
6890
6891                 if (intel_crtc->config.dither)
6892                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6893
6894                 I915_WRITE(PIPEMISC(pipe), val);
6895         }
6896 }
6897
6898 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6899                                     intel_clock_t *clock,
6900                                     bool *has_reduced_clock,
6901                                     intel_clock_t *reduced_clock)
6902 {
6903         struct drm_device *dev = crtc->dev;
6904         struct drm_i915_private *dev_priv = dev->dev_private;
6905         struct intel_encoder *intel_encoder;
6906         int refclk;
6907         const intel_limit_t *limit;
6908         bool ret, is_lvds = false;
6909
6910         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6911                 switch (intel_encoder->type) {
6912                 case INTEL_OUTPUT_LVDS:
6913                         is_lvds = true;
6914                         break;
6915                 }
6916         }
6917
6918         refclk = ironlake_get_refclk(crtc);
6919
6920         /*
6921          * Returns a set of divisors for the desired target clock with the given
6922          * refclk, or FALSE.  The returned values represent the clock equation:
6923          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6924          */
6925         limit = intel_limit(crtc, refclk);
6926         ret = dev_priv->display.find_dpll(limit, crtc,
6927                                           to_intel_crtc(crtc)->config.port_clock,
6928                                           refclk, NULL, clock);
6929         if (!ret)
6930                 return false;
6931
6932         if (is_lvds && dev_priv->lvds_downclock_avail) {
6933                 /*
6934                  * Ensure we match the reduced clock's P to the target clock.
6935                  * If the clocks don't match, we can't switch the display clock
6936                  * by using the FP0/FP1. In such case we will disable the LVDS
6937                  * downclock feature.
6938                 */
6939                 *has_reduced_clock =
6940                         dev_priv->display.find_dpll(limit, crtc,
6941                                                     dev_priv->lvds_downclock,
6942                                                     refclk, clock,
6943                                                     reduced_clock);
6944         }
6945
6946         return true;
6947 }
6948
6949 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6950 {
6951         /*
6952          * Account for spread spectrum to avoid
6953          * oversubscribing the link. Max center spread
6954          * is 2.5%; use 5% for safety's sake.
6955          */
6956         u32 bps = target_clock * bpp * 21 / 20;
6957         return DIV_ROUND_UP(bps, link_bw * 8);
6958 }
6959
6960 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6961 {
6962         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6963 }
6964
6965 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6966                                       u32 *fp,
6967                                       intel_clock_t *reduced_clock, u32 *fp2)
6968 {
6969         struct drm_crtc *crtc = &intel_crtc->base;
6970         struct drm_device *dev = crtc->dev;
6971         struct drm_i915_private *dev_priv = dev->dev_private;
6972         struct intel_encoder *intel_encoder;
6973         uint32_t dpll;
6974         int factor, num_connectors = 0;
6975         bool is_lvds = false, is_sdvo = false;
6976
6977         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6978                 switch (intel_encoder->type) {
6979                 case INTEL_OUTPUT_LVDS:
6980                         is_lvds = true;
6981                         break;
6982                 case INTEL_OUTPUT_SDVO:
6983                 case INTEL_OUTPUT_HDMI:
6984                         is_sdvo = true;
6985                         break;
6986                 }
6987
6988                 num_connectors++;
6989         }
6990
6991         /* Enable autotuning of the PLL clock (if permissible) */
6992         factor = 21;
6993         if (is_lvds) {
6994                 if ((intel_panel_use_ssc(dev_priv) &&
6995                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6996                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6997                         factor = 25;
6998         } else if (intel_crtc->config.sdvo_tv_clock)
6999                 factor = 20;
7000
7001         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7002                 *fp |= FP_CB_TUNE;
7003
7004         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7005                 *fp2 |= FP_CB_TUNE;
7006
7007         dpll = 0;
7008
7009         if (is_lvds)
7010                 dpll |= DPLLB_MODE_LVDS;
7011         else
7012                 dpll |= DPLLB_MODE_DAC_SERIAL;
7013
7014         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7015                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7016
7017         if (is_sdvo)
7018                 dpll |= DPLL_SDVO_HIGH_SPEED;
7019         if (intel_crtc->config.has_dp_encoder)
7020                 dpll |= DPLL_SDVO_HIGH_SPEED;
7021
7022         /* compute bitmask from p1 value */
7023         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7024         /* also FPA1 */
7025         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7026
7027         switch (intel_crtc->config.dpll.p2) {
7028         case 5:
7029                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7030                 break;
7031         case 7:
7032                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7033                 break;
7034         case 10:
7035                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7036                 break;
7037         case 14:
7038                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7039                 break;
7040         }
7041
7042         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7043                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7044         else
7045                 dpll |= PLL_REF_INPUT_DREFCLK;
7046
7047         return dpll | DPLL_VCO_ENABLE;
7048 }
7049
7050 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7051                                   int x, int y,
7052                                   struct drm_framebuffer *fb)
7053 {
7054         struct drm_device *dev = crtc->dev;
7055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7056         int num_connectors = 0;
7057         intel_clock_t clock, reduced_clock;
7058         u32 dpll = 0, fp = 0, fp2 = 0;
7059         bool ok, has_reduced_clock = false;
7060         bool is_lvds = false;
7061         struct intel_encoder *encoder;
7062         struct intel_shared_dpll *pll;
7063
7064         for_each_encoder_on_crtc(dev, crtc, encoder) {
7065                 switch (encoder->type) {
7066                 case INTEL_OUTPUT_LVDS:
7067                         is_lvds = true;
7068                         break;
7069                 }
7070
7071                 num_connectors++;
7072         }
7073
7074         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7075              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7076
7077         ok = ironlake_compute_clocks(crtc, &clock,
7078                                      &has_reduced_clock, &reduced_clock);
7079         if (!ok && !intel_crtc->config.clock_set) {
7080                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7081                 return -EINVAL;
7082         }
7083         /* Compat-code for transition, will disappear. */
7084         if (!intel_crtc->config.clock_set) {
7085                 intel_crtc->config.dpll.n = clock.n;
7086                 intel_crtc->config.dpll.m1 = clock.m1;
7087                 intel_crtc->config.dpll.m2 = clock.m2;
7088                 intel_crtc->config.dpll.p1 = clock.p1;
7089                 intel_crtc->config.dpll.p2 = clock.p2;
7090         }
7091
7092         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7093         if (intel_crtc->config.has_pch_encoder) {
7094                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7095                 if (has_reduced_clock)
7096                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7097
7098                 dpll = ironlake_compute_dpll(intel_crtc,
7099                                              &fp, &reduced_clock,
7100                                              has_reduced_clock ? &fp2 : NULL);
7101
7102                 intel_crtc->config.dpll_hw_state.dpll = dpll;
7103                 intel_crtc->config.dpll_hw_state.fp0 = fp;
7104                 if (has_reduced_clock)
7105                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
7106                 else
7107                         intel_crtc->config.dpll_hw_state.fp1 = fp;
7108
7109                 pll = intel_get_shared_dpll(intel_crtc);
7110                 if (pll == NULL) {
7111                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7112                                          pipe_name(intel_crtc->pipe));
7113                         return -EINVAL;
7114                 }
7115         } else
7116                 intel_put_shared_dpll(intel_crtc);
7117
7118         if (is_lvds && has_reduced_clock && i915.powersave)
7119                 intel_crtc->lowfreq_avail = true;
7120         else
7121                 intel_crtc->lowfreq_avail = false;
7122
7123         return 0;
7124 }
7125
7126 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7127                                          struct intel_link_m_n *m_n)
7128 {
7129         struct drm_device *dev = crtc->base.dev;
7130         struct drm_i915_private *dev_priv = dev->dev_private;
7131         enum pipe pipe = crtc->pipe;
7132
7133         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7134         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7135         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7136                 & ~TU_SIZE_MASK;
7137         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7138         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7139                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7140 }
7141
7142 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7143                                          enum transcoder transcoder,
7144                                          struct intel_link_m_n *m_n)
7145 {
7146         struct drm_device *dev = crtc->base.dev;
7147         struct drm_i915_private *dev_priv = dev->dev_private;
7148         enum pipe pipe = crtc->pipe;
7149
7150         if (INTEL_INFO(dev)->gen >= 5) {
7151                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7152                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7153                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7154                         & ~TU_SIZE_MASK;
7155                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7156                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7157                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7158         } else {
7159                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7160                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7161                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7162                         & ~TU_SIZE_MASK;
7163                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7164                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7165                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7166         }
7167 }
7168
7169 void intel_dp_get_m_n(struct intel_crtc *crtc,
7170                       struct intel_crtc_config *pipe_config)
7171 {
7172         if (crtc->config.has_pch_encoder)
7173                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7174         else
7175                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7176                                              &pipe_config->dp_m_n);
7177 }
7178
7179 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7180                                         struct intel_crtc_config *pipe_config)
7181 {
7182         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7183                                      &pipe_config->fdi_m_n);
7184 }
7185
7186 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7187                                      struct intel_crtc_config *pipe_config)
7188 {
7189         struct drm_device *dev = crtc->base.dev;
7190         struct drm_i915_private *dev_priv = dev->dev_private;
7191         uint32_t tmp;
7192
7193         tmp = I915_READ(PF_CTL(crtc->pipe));
7194
7195         if (tmp & PF_ENABLE) {
7196                 pipe_config->pch_pfit.enabled = true;
7197                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7198                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7199
7200                 /* We currently do not free assignements of panel fitters on
7201                  * ivb/hsw (since we don't use the higher upscaling modes which
7202                  * differentiates them) so just WARN about this case for now. */
7203                 if (IS_GEN7(dev)) {
7204                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7205                                 PF_PIPE_SEL_IVB(crtc->pipe));
7206                 }
7207         }
7208 }
7209
7210 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7211                                       struct intel_plane_config *plane_config)
7212 {
7213         struct drm_device *dev = crtc->base.dev;
7214         struct drm_i915_private *dev_priv = dev->dev_private;
7215         u32 val, base, offset;
7216         int pipe = crtc->pipe, plane = crtc->plane;
7217         int fourcc, pixel_format;
7218         int aligned_height;
7219
7220         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7221         if (!crtc->base.primary->fb) {
7222                 DRM_DEBUG_KMS("failed to alloc fb\n");
7223                 return;
7224         }
7225
7226         val = I915_READ(DSPCNTR(plane));
7227
7228         if (INTEL_INFO(dev)->gen >= 4)
7229                 if (val & DISPPLANE_TILED)
7230                         plane_config->tiled = true;
7231
7232         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7233         fourcc = intel_format_to_fourcc(pixel_format);
7234         crtc->base.primary->fb->pixel_format = fourcc;
7235         crtc->base.primary->fb->bits_per_pixel =
7236                 drm_format_plane_cpp(fourcc, 0) * 8;
7237
7238         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7239         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7240                 offset = I915_READ(DSPOFFSET(plane));
7241         } else {
7242                 if (plane_config->tiled)
7243                         offset = I915_READ(DSPTILEOFF(plane));
7244                 else
7245                         offset = I915_READ(DSPLINOFF(plane));
7246         }
7247         plane_config->base = base;
7248
7249         val = I915_READ(PIPESRC(pipe));
7250         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7251         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7252
7253         val = I915_READ(DSPSTRIDE(pipe));
7254         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7255
7256         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7257                                             plane_config->tiled);
7258
7259         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7260                                         aligned_height);
7261
7262         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7263                       pipe, plane, crtc->base.primary->fb->width,
7264                       crtc->base.primary->fb->height,
7265                       crtc->base.primary->fb->bits_per_pixel, base,
7266                       crtc->base.primary->fb->pitches[0],
7267                       plane_config->size);
7268 }
7269
7270 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7271                                      struct intel_crtc_config *pipe_config)
7272 {
7273         struct drm_device *dev = crtc->base.dev;
7274         struct drm_i915_private *dev_priv = dev->dev_private;
7275         uint32_t tmp;
7276
7277         if (!intel_display_power_enabled(dev_priv,
7278                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7279                 return false;
7280
7281         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7282         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7283
7284         tmp = I915_READ(PIPECONF(crtc->pipe));
7285         if (!(tmp & PIPECONF_ENABLE))
7286                 return false;
7287
7288         switch (tmp & PIPECONF_BPC_MASK) {
7289         case PIPECONF_6BPC:
7290                 pipe_config->pipe_bpp = 18;
7291                 break;
7292         case PIPECONF_8BPC:
7293                 pipe_config->pipe_bpp = 24;
7294                 break;
7295         case PIPECONF_10BPC:
7296                 pipe_config->pipe_bpp = 30;
7297                 break;
7298         case PIPECONF_12BPC:
7299                 pipe_config->pipe_bpp = 36;
7300                 break;
7301         default:
7302                 break;
7303         }
7304
7305         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7306                 pipe_config->limited_color_range = true;
7307
7308         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7309                 struct intel_shared_dpll *pll;
7310
7311                 pipe_config->has_pch_encoder = true;
7312
7313                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7314                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7315                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7316
7317                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7318
7319                 if (HAS_PCH_IBX(dev_priv->dev)) {
7320                         pipe_config->shared_dpll =
7321                                 (enum intel_dpll_id) crtc->pipe;
7322                 } else {
7323                         tmp = I915_READ(PCH_DPLL_SEL);
7324                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7325                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7326                         else
7327                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7328                 }
7329
7330                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7331
7332                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7333                                            &pipe_config->dpll_hw_state));
7334
7335                 tmp = pipe_config->dpll_hw_state.dpll;
7336                 pipe_config->pixel_multiplier =
7337                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7338                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7339
7340                 ironlake_pch_clock_get(crtc, pipe_config);
7341         } else {
7342                 pipe_config->pixel_multiplier = 1;
7343         }
7344
7345         intel_get_pipe_timings(crtc, pipe_config);
7346
7347         ironlake_get_pfit_config(crtc, pipe_config);
7348
7349         return true;
7350 }
7351
7352 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7353 {
7354         struct drm_device *dev = dev_priv->dev;
7355         struct intel_crtc *crtc;
7356
7357         for_each_intel_crtc(dev, crtc)
7358                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7359                      pipe_name(crtc->pipe));
7360
7361         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7362         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7363         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7364         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7365         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7366         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7367              "CPU PWM1 enabled\n");
7368         if (IS_HASWELL(dev))
7369                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7370                      "CPU PWM2 enabled\n");
7371         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7372              "PCH PWM1 enabled\n");
7373         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7374              "Utility pin enabled\n");
7375         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7376
7377         /*
7378          * In theory we can still leave IRQs enabled, as long as only the HPD
7379          * interrupts remain enabled. We used to check for that, but since it's
7380          * gen-specific and since we only disable LCPLL after we fully disable
7381          * the interrupts, the check below should be enough.
7382          */
7383         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7384 }
7385
7386 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7387 {
7388         struct drm_device *dev = dev_priv->dev;
7389
7390         if (IS_HASWELL(dev))
7391                 return I915_READ(D_COMP_HSW);
7392         else
7393                 return I915_READ(D_COMP_BDW);
7394 }
7395
7396 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7397 {
7398         struct drm_device *dev = dev_priv->dev;
7399
7400         if (IS_HASWELL(dev)) {
7401                 mutex_lock(&dev_priv->rps.hw_lock);
7402                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7403                                             val))
7404                         DRM_ERROR("Failed to write to D_COMP\n");
7405                 mutex_unlock(&dev_priv->rps.hw_lock);
7406         } else {
7407                 I915_WRITE(D_COMP_BDW, val);
7408                 POSTING_READ(D_COMP_BDW);
7409         }
7410 }
7411
7412 /*
7413  * This function implements pieces of two sequences from BSpec:
7414  * - Sequence for display software to disable LCPLL
7415  * - Sequence for display software to allow package C8+
7416  * The steps implemented here are just the steps that actually touch the LCPLL
7417  * register. Callers should take care of disabling all the display engine
7418  * functions, doing the mode unset, fixing interrupts, etc.
7419  */
7420 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7421                               bool switch_to_fclk, bool allow_power_down)
7422 {
7423         uint32_t val;
7424
7425         assert_can_disable_lcpll(dev_priv);
7426
7427         val = I915_READ(LCPLL_CTL);
7428
7429         if (switch_to_fclk) {
7430                 val |= LCPLL_CD_SOURCE_FCLK;
7431                 I915_WRITE(LCPLL_CTL, val);
7432
7433                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7434                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7435                         DRM_ERROR("Switching to FCLK failed\n");
7436
7437                 val = I915_READ(LCPLL_CTL);
7438         }
7439
7440         val |= LCPLL_PLL_DISABLE;
7441         I915_WRITE(LCPLL_CTL, val);
7442         POSTING_READ(LCPLL_CTL);
7443
7444         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7445                 DRM_ERROR("LCPLL still locked\n");
7446
7447         val = hsw_read_dcomp(dev_priv);
7448         val |= D_COMP_COMP_DISABLE;
7449         hsw_write_dcomp(dev_priv, val);
7450         ndelay(100);
7451
7452         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7453                      1))
7454                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7455
7456         if (allow_power_down) {
7457                 val = I915_READ(LCPLL_CTL);
7458                 val |= LCPLL_POWER_DOWN_ALLOW;
7459                 I915_WRITE(LCPLL_CTL, val);
7460                 POSTING_READ(LCPLL_CTL);
7461         }
7462 }
7463
7464 /*
7465  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7466  * source.
7467  */
7468 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7469 {
7470         uint32_t val;
7471         unsigned long irqflags;
7472
7473         val = I915_READ(LCPLL_CTL);
7474
7475         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7476                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7477                 return;
7478
7479         /*
7480          * Make sure we're not on PC8 state before disabling PC8, otherwise
7481          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7482          *
7483          * The other problem is that hsw_restore_lcpll() is called as part of
7484          * the runtime PM resume sequence, so we can't just call
7485          * gen6_gt_force_wake_get() because that function calls
7486          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7487          * while we are on the resume sequence. So to solve this problem we have
7488          * to call special forcewake code that doesn't touch runtime PM and
7489          * doesn't enable the forcewake delayed work.
7490          */
7491         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7492         if (dev_priv->uncore.forcewake_count++ == 0)
7493                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7494         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7495
7496         if (val & LCPLL_POWER_DOWN_ALLOW) {
7497                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7498                 I915_WRITE(LCPLL_CTL, val);
7499                 POSTING_READ(LCPLL_CTL);
7500         }
7501
7502         val = hsw_read_dcomp(dev_priv);
7503         val |= D_COMP_COMP_FORCE;
7504         val &= ~D_COMP_COMP_DISABLE;
7505         hsw_write_dcomp(dev_priv, val);
7506
7507         val = I915_READ(LCPLL_CTL);
7508         val &= ~LCPLL_PLL_DISABLE;
7509         I915_WRITE(LCPLL_CTL, val);
7510
7511         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7512                 DRM_ERROR("LCPLL not locked yet\n");
7513
7514         if (val & LCPLL_CD_SOURCE_FCLK) {
7515                 val = I915_READ(LCPLL_CTL);
7516                 val &= ~LCPLL_CD_SOURCE_FCLK;
7517                 I915_WRITE(LCPLL_CTL, val);
7518
7519                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7520                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7521                         DRM_ERROR("Switching back to LCPLL failed\n");
7522         }
7523
7524         /* See the big comment above. */
7525         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7526         if (--dev_priv->uncore.forcewake_count == 0)
7527                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7528         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7529 }
7530
7531 /*
7532  * Package states C8 and deeper are really deep PC states that can only be
7533  * reached when all the devices on the system allow it, so even if the graphics
7534  * device allows PC8+, it doesn't mean the system will actually get to these
7535  * states. Our driver only allows PC8+ when going into runtime PM.
7536  *
7537  * The requirements for PC8+ are that all the outputs are disabled, the power
7538  * well is disabled and most interrupts are disabled, and these are also
7539  * requirements for runtime PM. When these conditions are met, we manually do
7540  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7541  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7542  * hang the machine.
7543  *
7544  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7545  * the state of some registers, so when we come back from PC8+ we need to
7546  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7547  * need to take care of the registers kept by RC6. Notice that this happens even
7548  * if we don't put the device in PCI D3 state (which is what currently happens
7549  * because of the runtime PM support).
7550  *
7551  * For more, read "Display Sequences for Package C8" on the hardware
7552  * documentation.
7553  */
7554 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7555 {
7556         struct drm_device *dev = dev_priv->dev;
7557         uint32_t val;
7558
7559         DRM_DEBUG_KMS("Enabling package C8+\n");
7560
7561         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7562                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7563                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7564                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7565         }
7566
7567         lpt_disable_clkout_dp(dev);
7568         hsw_disable_lcpll(dev_priv, true, true);
7569 }
7570
7571 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7572 {
7573         struct drm_device *dev = dev_priv->dev;
7574         uint32_t val;
7575
7576         DRM_DEBUG_KMS("Disabling package C8+\n");
7577
7578         hsw_restore_lcpll(dev_priv);
7579         lpt_init_pch_refclk(dev);
7580
7581         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7582                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7583                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7584                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7585         }
7586
7587         intel_prepare_ddi(dev);
7588 }
7589
7590 static void snb_modeset_global_resources(struct drm_device *dev)
7591 {
7592         modeset_update_crtc_power_domains(dev);
7593 }
7594
7595 static void haswell_modeset_global_resources(struct drm_device *dev)
7596 {
7597         modeset_update_crtc_power_domains(dev);
7598 }
7599
7600 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7601                                  int x, int y,
7602                                  struct drm_framebuffer *fb)
7603 {
7604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7605
7606         if (!intel_ddi_pll_select(intel_crtc))
7607                 return -EINVAL;
7608
7609         intel_crtc->lowfreq_avail = false;
7610
7611         return 0;
7612 }
7613
7614 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7615                                        struct intel_crtc_config *pipe_config)
7616 {
7617         struct drm_device *dev = crtc->base.dev;
7618         struct drm_i915_private *dev_priv = dev->dev_private;
7619         struct intel_shared_dpll *pll;
7620         enum port port;
7621         uint32_t tmp;
7622
7623         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7624
7625         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7626
7627         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7628
7629         switch (pipe_config->ddi_pll_sel) {
7630         case PORT_CLK_SEL_WRPLL1:
7631                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7632                 break;
7633         case PORT_CLK_SEL_WRPLL2:
7634                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7635                 break;
7636         }
7637
7638         if (pipe_config->shared_dpll >= 0) {
7639                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7640
7641                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7642                                            &pipe_config->dpll_hw_state));
7643         }
7644
7645         /*
7646          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7647          * DDI E. So just check whether this pipe is wired to DDI E and whether
7648          * the PCH transcoder is on.
7649          */
7650         if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7651                 pipe_config->has_pch_encoder = true;
7652
7653                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7654                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7655                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7656
7657                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7658         }
7659 }
7660
7661 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7662                                     struct intel_crtc_config *pipe_config)
7663 {
7664         struct drm_device *dev = crtc->base.dev;
7665         struct drm_i915_private *dev_priv = dev->dev_private;
7666         enum intel_display_power_domain pfit_domain;
7667         uint32_t tmp;
7668
7669         if (!intel_display_power_enabled(dev_priv,
7670                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7671                 return false;
7672
7673         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7674         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7675
7676         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7677         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7678                 enum pipe trans_edp_pipe;
7679                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7680                 default:
7681                         WARN(1, "unknown pipe linked to edp transcoder\n");
7682                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7683                 case TRANS_DDI_EDP_INPUT_A_ON:
7684                         trans_edp_pipe = PIPE_A;
7685                         break;
7686                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7687                         trans_edp_pipe = PIPE_B;
7688                         break;
7689                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7690                         trans_edp_pipe = PIPE_C;
7691                         break;
7692                 }
7693
7694                 if (trans_edp_pipe == crtc->pipe)
7695                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7696         }
7697
7698         if (!intel_display_power_enabled(dev_priv,
7699                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7700                 return false;
7701
7702         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7703         if (!(tmp & PIPECONF_ENABLE))
7704                 return false;
7705
7706         haswell_get_ddi_port_state(crtc, pipe_config);
7707
7708         intel_get_pipe_timings(crtc, pipe_config);
7709
7710         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7711         if (intel_display_power_enabled(dev_priv, pfit_domain))
7712                 ironlake_get_pfit_config(crtc, pipe_config);
7713
7714         if (IS_HASWELL(dev))
7715                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7716                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7717
7718         pipe_config->pixel_multiplier = 1;
7719
7720         return true;
7721 }
7722
7723 static struct {
7724         int clock;
7725         u32 config;
7726 } hdmi_audio_clock[] = {
7727         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7728         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7729         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7730         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7731         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7732         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7733         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7734         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7735         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7736         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7737 };
7738
7739 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7740 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7741 {
7742         int i;
7743
7744         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7745                 if (mode->clock == hdmi_audio_clock[i].clock)
7746                         break;
7747         }
7748
7749         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7750                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7751                 i = 1;
7752         }
7753
7754         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7755                       hdmi_audio_clock[i].clock,
7756                       hdmi_audio_clock[i].config);
7757
7758         return hdmi_audio_clock[i].config;
7759 }
7760
7761 static bool intel_eld_uptodate(struct drm_connector *connector,
7762                                int reg_eldv, uint32_t bits_eldv,
7763                                int reg_elda, uint32_t bits_elda,
7764                                int reg_edid)
7765 {
7766         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7767         uint8_t *eld = connector->eld;
7768         uint32_t i;
7769
7770         i = I915_READ(reg_eldv);
7771         i &= bits_eldv;
7772
7773         if (!eld[0])
7774                 return !i;
7775
7776         if (!i)
7777                 return false;
7778
7779         i = I915_READ(reg_elda);
7780         i &= ~bits_elda;
7781         I915_WRITE(reg_elda, i);
7782
7783         for (i = 0; i < eld[2]; i++)
7784                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7785                         return false;
7786
7787         return true;
7788 }
7789
7790 static void g4x_write_eld(struct drm_connector *connector,
7791                           struct drm_crtc *crtc,
7792                           struct drm_display_mode *mode)
7793 {
7794         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7795         uint8_t *eld = connector->eld;
7796         uint32_t eldv;
7797         uint32_t len;
7798         uint32_t i;
7799
7800         i = I915_READ(G4X_AUD_VID_DID);
7801
7802         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7803                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7804         else
7805                 eldv = G4X_ELDV_DEVCTG;
7806
7807         if (intel_eld_uptodate(connector,
7808                                G4X_AUD_CNTL_ST, eldv,
7809                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7810                                G4X_HDMIW_HDMIEDID))
7811                 return;
7812
7813         i = I915_READ(G4X_AUD_CNTL_ST);
7814         i &= ~(eldv | G4X_ELD_ADDR);
7815         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7816         I915_WRITE(G4X_AUD_CNTL_ST, i);
7817
7818         if (!eld[0])
7819                 return;
7820
7821         len = min_t(uint8_t, eld[2], len);
7822         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7823         for (i = 0; i < len; i++)
7824                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7825
7826         i = I915_READ(G4X_AUD_CNTL_ST);
7827         i |= eldv;
7828         I915_WRITE(G4X_AUD_CNTL_ST, i);
7829 }
7830
7831 static void haswell_write_eld(struct drm_connector *connector,
7832                               struct drm_crtc *crtc,
7833                               struct drm_display_mode *mode)
7834 {
7835         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7836         uint8_t *eld = connector->eld;
7837         uint32_t eldv;
7838         uint32_t i;
7839         int len;
7840         int pipe = to_intel_crtc(crtc)->pipe;
7841         int tmp;
7842
7843         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7844         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7845         int aud_config = HSW_AUD_CFG(pipe);
7846         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7847
7848         /* Audio output enable */
7849         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7850         tmp = I915_READ(aud_cntrl_st2);
7851         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7852         I915_WRITE(aud_cntrl_st2, tmp);
7853         POSTING_READ(aud_cntrl_st2);
7854
7855         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7856
7857         /* Set ELD valid state */
7858         tmp = I915_READ(aud_cntrl_st2);
7859         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7860         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7861         I915_WRITE(aud_cntrl_st2, tmp);
7862         tmp = I915_READ(aud_cntrl_st2);
7863         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7864
7865         /* Enable HDMI mode */
7866         tmp = I915_READ(aud_config);
7867         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7868         /* clear N_programing_enable and N_value_index */
7869         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7870         I915_WRITE(aud_config, tmp);
7871
7872         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7873
7874         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7875
7876         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7877                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7878                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7879                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7880         } else {
7881                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7882         }
7883
7884         if (intel_eld_uptodate(connector,
7885                                aud_cntrl_st2, eldv,
7886                                aud_cntl_st, IBX_ELD_ADDRESS,
7887                                hdmiw_hdmiedid))
7888                 return;
7889
7890         i = I915_READ(aud_cntrl_st2);
7891         i &= ~eldv;
7892         I915_WRITE(aud_cntrl_st2, i);
7893
7894         if (!eld[0])
7895                 return;
7896
7897         i = I915_READ(aud_cntl_st);
7898         i &= ~IBX_ELD_ADDRESS;
7899         I915_WRITE(aud_cntl_st, i);
7900         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7901         DRM_DEBUG_DRIVER("port num:%d\n", i);
7902
7903         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7904         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7905         for (i = 0; i < len; i++)
7906                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7907
7908         i = I915_READ(aud_cntrl_st2);
7909         i |= eldv;
7910         I915_WRITE(aud_cntrl_st2, i);
7911
7912 }
7913
7914 static void ironlake_write_eld(struct drm_connector *connector,
7915                                struct drm_crtc *crtc,
7916                                struct drm_display_mode *mode)
7917 {
7918         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7919         uint8_t *eld = connector->eld;
7920         uint32_t eldv;
7921         uint32_t i;
7922         int len;
7923         int hdmiw_hdmiedid;
7924         int aud_config;
7925         int aud_cntl_st;
7926         int aud_cntrl_st2;
7927         int pipe = to_intel_crtc(crtc)->pipe;
7928
7929         if (HAS_PCH_IBX(connector->dev)) {
7930                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7931                 aud_config = IBX_AUD_CFG(pipe);
7932                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7933                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7934         } else if (IS_VALLEYVIEW(connector->dev)) {
7935                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7936                 aud_config = VLV_AUD_CFG(pipe);
7937                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7938                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7939         } else {
7940                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7941                 aud_config = CPT_AUD_CFG(pipe);
7942                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7943                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7944         }
7945
7946         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7947
7948         if (IS_VALLEYVIEW(connector->dev))  {
7949                 struct intel_encoder *intel_encoder;
7950                 struct intel_digital_port *intel_dig_port;
7951
7952                 intel_encoder = intel_attached_encoder(connector);
7953                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7954                 i = intel_dig_port->port;
7955         } else {
7956                 i = I915_READ(aud_cntl_st);
7957                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7958                 /* DIP_Port_Select, 0x1 = PortB */
7959         }
7960
7961         if (!i) {
7962                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7963                 /* operate blindly on all ports */
7964                 eldv = IBX_ELD_VALIDB;
7965                 eldv |= IBX_ELD_VALIDB << 4;
7966                 eldv |= IBX_ELD_VALIDB << 8;
7967         } else {
7968                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7969                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7970         }
7971
7972         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7973                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7974                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7975                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7976         } else {
7977                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7978         }
7979
7980         if (intel_eld_uptodate(connector,
7981                                aud_cntrl_st2, eldv,
7982                                aud_cntl_st, IBX_ELD_ADDRESS,
7983                                hdmiw_hdmiedid))
7984                 return;
7985
7986         i = I915_READ(aud_cntrl_st2);
7987         i &= ~eldv;
7988         I915_WRITE(aud_cntrl_st2, i);
7989
7990         if (!eld[0])
7991                 return;
7992
7993         i = I915_READ(aud_cntl_st);
7994         i &= ~IBX_ELD_ADDRESS;
7995         I915_WRITE(aud_cntl_st, i);
7996
7997         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7998         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7999         for (i = 0; i < len; i++)
8000                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8001
8002         i = I915_READ(aud_cntrl_st2);
8003         i |= eldv;
8004         I915_WRITE(aud_cntrl_st2, i);
8005 }
8006
8007 void intel_write_eld(struct drm_encoder *encoder,
8008                      struct drm_display_mode *mode)
8009 {
8010         struct drm_crtc *crtc = encoder->crtc;
8011         struct drm_connector *connector;
8012         struct drm_device *dev = encoder->dev;
8013         struct drm_i915_private *dev_priv = dev->dev_private;
8014
8015         connector = drm_select_eld(encoder, mode);
8016         if (!connector)
8017                 return;
8018
8019         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8020                          connector->base.id,
8021                          connector->name,
8022                          connector->encoder->base.id,
8023                          connector->encoder->name);
8024
8025         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8026
8027         if (dev_priv->display.write_eld)
8028                 dev_priv->display.write_eld(connector, crtc, mode);
8029 }
8030
8031 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8032 {
8033         struct drm_device *dev = crtc->dev;
8034         struct drm_i915_private *dev_priv = dev->dev_private;
8035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8036         uint32_t cntl;
8037
8038         if (base != intel_crtc->cursor_base) {
8039                 /* On these chipsets we can only modify the base whilst
8040                  * the cursor is disabled.
8041                  */
8042                 if (intel_crtc->cursor_cntl) {
8043                         I915_WRITE(_CURACNTR, 0);
8044                         POSTING_READ(_CURACNTR);
8045                         intel_crtc->cursor_cntl = 0;
8046                 }
8047
8048                 I915_WRITE(_CURABASE, base);
8049                 POSTING_READ(_CURABASE);
8050         }
8051
8052         /* XXX width must be 64, stride 256 => 0x00 << 28 */
8053         cntl = 0;
8054         if (base)
8055                 cntl = (CURSOR_ENABLE |
8056                         CURSOR_GAMMA_ENABLE |
8057                         CURSOR_FORMAT_ARGB);
8058         if (intel_crtc->cursor_cntl != cntl) {
8059                 I915_WRITE(_CURACNTR, cntl);
8060                 POSTING_READ(_CURACNTR);
8061                 intel_crtc->cursor_cntl = cntl;
8062         }
8063 }
8064
8065 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8066 {
8067         struct drm_device *dev = crtc->dev;
8068         struct drm_i915_private *dev_priv = dev->dev_private;
8069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8070         int pipe = intel_crtc->pipe;
8071         uint32_t cntl;
8072
8073         cntl = 0;
8074         if (base) {
8075                 cntl = MCURSOR_GAMMA_ENABLE;
8076                 switch (intel_crtc->cursor_width) {
8077                         case 64:
8078                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8079                                 break;
8080                         case 128:
8081                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8082                                 break;
8083                         case 256:
8084                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8085                                 break;
8086                         default:
8087                                 WARN_ON(1);
8088                                 return;
8089                 }
8090                 cntl |= pipe << 28; /* Connect to correct pipe */
8091         }
8092         if (intel_crtc->cursor_cntl != cntl) {
8093                 I915_WRITE(CURCNTR(pipe), cntl);
8094                 POSTING_READ(CURCNTR(pipe));
8095                 intel_crtc->cursor_cntl = cntl;
8096         }
8097
8098         /* and commit changes on next vblank */
8099         I915_WRITE(CURBASE(pipe), base);
8100         POSTING_READ(CURBASE(pipe));
8101 }
8102
8103 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8104 {
8105         struct drm_device *dev = crtc->dev;
8106         struct drm_i915_private *dev_priv = dev->dev_private;
8107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8108         int pipe = intel_crtc->pipe;
8109         uint32_t cntl;
8110
8111         cntl = 0;
8112         if (base) {
8113                 cntl = MCURSOR_GAMMA_ENABLE;
8114                 switch (intel_crtc->cursor_width) {
8115                         case 64:
8116                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8117                                 break;
8118                         case 128:
8119                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8120                                 break;
8121                         case 256:
8122                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8123                                 break;
8124                         default:
8125                                 WARN_ON(1);
8126                                 return;
8127                 }
8128         }
8129         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8130                 cntl |= CURSOR_PIPE_CSC_ENABLE;
8131
8132         if (intel_crtc->cursor_cntl != cntl) {
8133                 I915_WRITE(CURCNTR(pipe), cntl);
8134                 POSTING_READ(CURCNTR(pipe));
8135                 intel_crtc->cursor_cntl = cntl;
8136         }
8137
8138         /* and commit changes on next vblank */
8139         I915_WRITE(CURBASE(pipe), base);
8140         POSTING_READ(CURBASE(pipe));
8141 }
8142
8143 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8144 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8145                                      bool on)
8146 {
8147         struct drm_device *dev = crtc->dev;
8148         struct drm_i915_private *dev_priv = dev->dev_private;
8149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8150         int pipe = intel_crtc->pipe;
8151         int x = crtc->cursor_x;
8152         int y = crtc->cursor_y;
8153         u32 base = 0, pos = 0;
8154
8155         if (on)
8156                 base = intel_crtc->cursor_addr;
8157
8158         if (x >= intel_crtc->config.pipe_src_w)
8159                 base = 0;
8160
8161         if (y >= intel_crtc->config.pipe_src_h)
8162                 base = 0;
8163
8164         if (x < 0) {
8165                 if (x + intel_crtc->cursor_width <= 0)
8166                         base = 0;
8167
8168                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8169                 x = -x;
8170         }
8171         pos |= x << CURSOR_X_SHIFT;
8172
8173         if (y < 0) {
8174                 if (y + intel_crtc->cursor_height <= 0)
8175                         base = 0;
8176
8177                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8178                 y = -y;
8179         }
8180         pos |= y << CURSOR_Y_SHIFT;
8181
8182         if (base == 0 && intel_crtc->cursor_base == 0)
8183                 return;
8184
8185         I915_WRITE(CURPOS(pipe), pos);
8186
8187         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8188                 ivb_update_cursor(crtc, base);
8189         else if (IS_845G(dev) || IS_I865G(dev))
8190                 i845_update_cursor(crtc, base);
8191         else
8192                 i9xx_update_cursor(crtc, base);
8193         intel_crtc->cursor_base = base;
8194 }
8195
8196 /*
8197  * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8198  *
8199  * Note that the object's reference will be consumed if the update fails.  If
8200  * the update succeeds, the reference of the old object (if any) will be
8201  * consumed.
8202  */
8203 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8204                                      struct drm_i915_gem_object *obj,
8205                                      uint32_t width, uint32_t height)
8206 {
8207         struct drm_device *dev = crtc->dev;
8208         struct drm_i915_private *dev_priv = dev->dev_private;
8209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8210         enum pipe pipe = intel_crtc->pipe;
8211         unsigned old_width;
8212         uint32_t addr;
8213         int ret;
8214
8215         /* if we want to turn off the cursor ignore width and height */
8216         if (!obj) {
8217                 DRM_DEBUG_KMS("cursor off\n");
8218                 addr = 0;
8219                 obj = NULL;
8220                 mutex_lock(&dev->struct_mutex);
8221                 goto finish;
8222         }
8223
8224         /* Check for which cursor types we support */
8225         if (!((width == 64 && height == 64) ||
8226                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8227                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8228                 DRM_DEBUG("Cursor dimension not supported\n");
8229                 return -EINVAL;
8230         }
8231
8232         if (obj->base.size < width * height * 4) {
8233                 DRM_DEBUG_KMS("buffer is too small\n");
8234                 ret = -ENOMEM;
8235                 goto fail;
8236         }
8237
8238         /* we only need to pin inside GTT if cursor is non-phy */
8239         mutex_lock(&dev->struct_mutex);
8240         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8241                 unsigned alignment;
8242
8243                 if (obj->tiling_mode) {
8244                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8245                         ret = -EINVAL;
8246                         goto fail_locked;
8247                 }
8248
8249                 /* Note that the w/a also requires 2 PTE of padding following
8250                  * the bo. We currently fill all unused PTE with the shadow
8251                  * page and so we should always have valid PTE following the
8252                  * cursor preventing the VT-d warning.
8253                  */
8254                 alignment = 0;
8255                 if (need_vtd_wa(dev))
8256                         alignment = 64*1024;
8257
8258                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8259                 if (ret) {
8260                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8261                         goto fail_locked;
8262                 }
8263
8264                 ret = i915_gem_object_put_fence(obj);
8265                 if (ret) {
8266                         DRM_DEBUG_KMS("failed to release fence for cursor");
8267                         goto fail_unpin;
8268                 }
8269
8270                 addr = i915_gem_obj_ggtt_offset(obj);
8271         } else {
8272                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8273                 ret = i915_gem_object_attach_phys(obj, align);
8274                 if (ret) {
8275                         DRM_DEBUG_KMS("failed to attach phys object\n");
8276                         goto fail_locked;
8277                 }
8278                 addr = obj->phys_handle->busaddr;
8279         }
8280
8281         if (IS_GEN2(dev))
8282                 I915_WRITE(CURSIZE, (height << 12) | width);
8283
8284  finish:
8285         if (intel_crtc->cursor_bo) {
8286                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8287                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8288         }
8289
8290         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8291                           INTEL_FRONTBUFFER_CURSOR(pipe));
8292         mutex_unlock(&dev->struct_mutex);
8293
8294         old_width = intel_crtc->cursor_width;
8295
8296         intel_crtc->cursor_addr = addr;
8297         intel_crtc->cursor_bo = obj;
8298         intel_crtc->cursor_width = width;
8299         intel_crtc->cursor_height = height;
8300
8301         if (intel_crtc->active) {
8302                 if (old_width != width)
8303                         intel_update_watermarks(crtc);
8304                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8305         }
8306
8307         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8308
8309         return 0;
8310 fail_unpin:
8311         i915_gem_object_unpin_from_display_plane(obj);
8312 fail_locked:
8313         mutex_unlock(&dev->struct_mutex);
8314 fail:
8315         drm_gem_object_unreference_unlocked(&obj->base);
8316         return ret;
8317 }
8318
8319 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8320                                  u16 *blue, uint32_t start, uint32_t size)
8321 {
8322         int end = (start + size > 256) ? 256 : start + size, i;
8323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8324
8325         for (i = start; i < end; i++) {
8326                 intel_crtc->lut_r[i] = red[i] >> 8;
8327                 intel_crtc->lut_g[i] = green[i] >> 8;
8328                 intel_crtc->lut_b[i] = blue[i] >> 8;
8329         }
8330
8331         intel_crtc_load_lut(crtc);
8332 }
8333
8334 /* VESA 640x480x72Hz mode to set on the pipe */
8335 static struct drm_display_mode load_detect_mode = {
8336         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8337                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8338 };
8339
8340 struct drm_framebuffer *
8341 __intel_framebuffer_create(struct drm_device *dev,
8342                            struct drm_mode_fb_cmd2 *mode_cmd,
8343                            struct drm_i915_gem_object *obj)
8344 {
8345         struct intel_framebuffer *intel_fb;
8346         int ret;
8347
8348         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8349         if (!intel_fb) {
8350                 drm_gem_object_unreference_unlocked(&obj->base);
8351                 return ERR_PTR(-ENOMEM);
8352         }
8353
8354         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8355         if (ret)
8356                 goto err;
8357
8358         return &intel_fb->base;
8359 err:
8360         drm_gem_object_unreference_unlocked(&obj->base);
8361         kfree(intel_fb);
8362
8363         return ERR_PTR(ret);
8364 }
8365
8366 static struct drm_framebuffer *
8367 intel_framebuffer_create(struct drm_device *dev,
8368                          struct drm_mode_fb_cmd2 *mode_cmd,
8369                          struct drm_i915_gem_object *obj)
8370 {
8371         struct drm_framebuffer *fb;
8372         int ret;
8373
8374         ret = i915_mutex_lock_interruptible(dev);
8375         if (ret)
8376                 return ERR_PTR(ret);
8377         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8378         mutex_unlock(&dev->struct_mutex);
8379
8380         return fb;
8381 }
8382
8383 static u32
8384 intel_framebuffer_pitch_for_width(int width, int bpp)
8385 {
8386         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8387         return ALIGN(pitch, 64);
8388 }
8389
8390 static u32
8391 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8392 {
8393         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8394         return PAGE_ALIGN(pitch * mode->vdisplay);
8395 }
8396
8397 static struct drm_framebuffer *
8398 intel_framebuffer_create_for_mode(struct drm_device *dev,
8399                                   struct drm_display_mode *mode,
8400                                   int depth, int bpp)
8401 {
8402         struct drm_i915_gem_object *obj;
8403         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8404
8405         obj = i915_gem_alloc_object(dev,
8406                                     intel_framebuffer_size_for_mode(mode, bpp));
8407         if (obj == NULL)
8408                 return ERR_PTR(-ENOMEM);
8409
8410         mode_cmd.width = mode->hdisplay;
8411         mode_cmd.height = mode->vdisplay;
8412         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8413                                                                 bpp);
8414         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8415
8416         return intel_framebuffer_create(dev, &mode_cmd, obj);
8417 }
8418
8419 static struct drm_framebuffer *
8420 mode_fits_in_fbdev(struct drm_device *dev,
8421                    struct drm_display_mode *mode)
8422 {
8423 #ifdef CONFIG_DRM_I915_FBDEV
8424         struct drm_i915_private *dev_priv = dev->dev_private;
8425         struct drm_i915_gem_object *obj;
8426         struct drm_framebuffer *fb;
8427
8428         if (!dev_priv->fbdev)
8429                 return NULL;
8430
8431         if (!dev_priv->fbdev->fb)
8432                 return NULL;
8433
8434         obj = dev_priv->fbdev->fb->obj;
8435         BUG_ON(!obj);
8436
8437         fb = &dev_priv->fbdev->fb->base;
8438         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8439                                                                fb->bits_per_pixel))
8440                 return NULL;
8441
8442         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8443                 return NULL;
8444
8445         return fb;
8446 #else
8447         return NULL;
8448 #endif
8449 }
8450
8451 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8452                                 struct drm_display_mode *mode,
8453                                 struct intel_load_detect_pipe *old,
8454                                 struct drm_modeset_acquire_ctx *ctx)
8455 {
8456         struct intel_crtc *intel_crtc;
8457         struct intel_encoder *intel_encoder =
8458                 intel_attached_encoder(connector);
8459         struct drm_crtc *possible_crtc;
8460         struct drm_encoder *encoder = &intel_encoder->base;
8461         struct drm_crtc *crtc = NULL;
8462         struct drm_device *dev = encoder->dev;
8463         struct drm_framebuffer *fb;
8464         struct drm_mode_config *config = &dev->mode_config;
8465         int ret, i = -1;
8466
8467         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8468                       connector->base.id, connector->name,
8469                       encoder->base.id, encoder->name);
8470
8471         drm_modeset_acquire_init(ctx, 0);
8472
8473 retry:
8474         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8475         if (ret)
8476                 goto fail_unlock;
8477
8478         /*
8479          * Algorithm gets a little messy:
8480          *
8481          *   - if the connector already has an assigned crtc, use it (but make
8482          *     sure it's on first)
8483          *
8484          *   - try to find the first unused crtc that can drive this connector,
8485          *     and use that if we find one
8486          */
8487
8488         /* See if we already have a CRTC for this connector */
8489         if (encoder->crtc) {
8490                 crtc = encoder->crtc;
8491
8492                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8493                 if (ret)
8494                         goto fail_unlock;
8495
8496                 old->dpms_mode = connector->dpms;
8497                 old->load_detect_temp = false;
8498
8499                 /* Make sure the crtc and connector are running */
8500                 if (connector->dpms != DRM_MODE_DPMS_ON)
8501                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8502
8503                 return true;
8504         }
8505
8506         /* Find an unused one (if possible) */
8507         for_each_crtc(dev, possible_crtc) {
8508                 i++;
8509                 if (!(encoder->possible_crtcs & (1 << i)))
8510                         continue;
8511                 if (!possible_crtc->enabled) {
8512                         crtc = possible_crtc;
8513                         break;
8514                 }
8515         }
8516
8517         /*
8518          * If we didn't find an unused CRTC, don't use any.
8519          */
8520         if (!crtc) {
8521                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8522                 goto fail_unlock;
8523         }
8524
8525         ret = drm_modeset_lock(&crtc->mutex, ctx);
8526         if (ret)
8527                 goto fail_unlock;
8528         intel_encoder->new_crtc = to_intel_crtc(crtc);
8529         to_intel_connector(connector)->new_encoder = intel_encoder;
8530
8531         intel_crtc = to_intel_crtc(crtc);
8532         intel_crtc->new_enabled = true;
8533         intel_crtc->new_config = &intel_crtc->config;
8534         old->dpms_mode = connector->dpms;
8535         old->load_detect_temp = true;
8536         old->release_fb = NULL;
8537
8538         if (!mode)
8539                 mode = &load_detect_mode;
8540
8541         /* We need a framebuffer large enough to accommodate all accesses
8542          * that the plane may generate whilst we perform load detection.
8543          * We can not rely on the fbcon either being present (we get called
8544          * during its initialisation to detect all boot displays, or it may
8545          * not even exist) or that it is large enough to satisfy the
8546          * requested mode.
8547          */
8548         fb = mode_fits_in_fbdev(dev, mode);
8549         if (fb == NULL) {
8550                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8551                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8552                 old->release_fb = fb;
8553         } else
8554                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8555         if (IS_ERR(fb)) {
8556                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8557                 goto fail;
8558         }
8559
8560         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8561                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8562                 if (old->release_fb)
8563                         old->release_fb->funcs->destroy(old->release_fb);
8564                 goto fail;
8565         }
8566
8567         /* let the connector get through one full cycle before testing */
8568         intel_wait_for_vblank(dev, intel_crtc->pipe);
8569         return true;
8570
8571  fail:
8572         intel_crtc->new_enabled = crtc->enabled;
8573         if (intel_crtc->new_enabled)
8574                 intel_crtc->new_config = &intel_crtc->config;
8575         else
8576                 intel_crtc->new_config = NULL;
8577 fail_unlock:
8578         if (ret == -EDEADLK) {
8579                 drm_modeset_backoff(ctx);
8580                 goto retry;
8581         }
8582
8583         drm_modeset_drop_locks(ctx);
8584         drm_modeset_acquire_fini(ctx);
8585
8586         return false;
8587 }
8588
8589 void intel_release_load_detect_pipe(struct drm_connector *connector,
8590                                     struct intel_load_detect_pipe *old,
8591                                     struct drm_modeset_acquire_ctx *ctx)
8592 {
8593         struct intel_encoder *intel_encoder =
8594                 intel_attached_encoder(connector);
8595         struct drm_encoder *encoder = &intel_encoder->base;
8596         struct drm_crtc *crtc = encoder->crtc;
8597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8598
8599         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8600                       connector->base.id, connector->name,
8601                       encoder->base.id, encoder->name);
8602
8603         if (old->load_detect_temp) {
8604                 to_intel_connector(connector)->new_encoder = NULL;
8605                 intel_encoder->new_crtc = NULL;
8606                 intel_crtc->new_enabled = false;
8607                 intel_crtc->new_config = NULL;
8608                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8609
8610                 if (old->release_fb) {
8611                         drm_framebuffer_unregister_private(old->release_fb);
8612                         drm_framebuffer_unreference(old->release_fb);
8613                 }
8614
8615                 goto unlock;
8616                 return;
8617         }
8618
8619         /* Switch crtc and encoder back off if necessary */
8620         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8621                 connector->funcs->dpms(connector, old->dpms_mode);
8622
8623 unlock:
8624         drm_modeset_drop_locks(ctx);
8625         drm_modeset_acquire_fini(ctx);
8626 }
8627
8628 static int i9xx_pll_refclk(struct drm_device *dev,
8629                            const struct intel_crtc_config *pipe_config)
8630 {
8631         struct drm_i915_private *dev_priv = dev->dev_private;
8632         u32 dpll = pipe_config->dpll_hw_state.dpll;
8633
8634         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8635                 return dev_priv->vbt.lvds_ssc_freq;
8636         else if (HAS_PCH_SPLIT(dev))
8637                 return 120000;
8638         else if (!IS_GEN2(dev))
8639                 return 96000;
8640         else
8641                 return 48000;
8642 }
8643
8644 /* Returns the clock of the currently programmed mode of the given pipe. */
8645 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8646                                 struct intel_crtc_config *pipe_config)
8647 {
8648         struct drm_device *dev = crtc->base.dev;
8649         struct drm_i915_private *dev_priv = dev->dev_private;
8650         int pipe = pipe_config->cpu_transcoder;
8651         u32 dpll = pipe_config->dpll_hw_state.dpll;
8652         u32 fp;
8653         intel_clock_t clock;
8654         int refclk = i9xx_pll_refclk(dev, pipe_config);
8655
8656         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8657                 fp = pipe_config->dpll_hw_state.fp0;
8658         else
8659                 fp = pipe_config->dpll_hw_state.fp1;
8660
8661         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8662         if (IS_PINEVIEW(dev)) {
8663                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8664                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8665         } else {
8666                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8667                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8668         }
8669
8670         if (!IS_GEN2(dev)) {
8671                 if (IS_PINEVIEW(dev))
8672                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8673                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8674                 else
8675                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8676                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8677
8678                 switch (dpll & DPLL_MODE_MASK) {
8679                 case DPLLB_MODE_DAC_SERIAL:
8680                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8681                                 5 : 10;
8682                         break;
8683                 case DPLLB_MODE_LVDS:
8684                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8685                                 7 : 14;
8686                         break;
8687                 default:
8688                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8689                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8690                         return;
8691                 }
8692
8693                 if (IS_PINEVIEW(dev))
8694                         pineview_clock(refclk, &clock);
8695                 else
8696                         i9xx_clock(refclk, &clock);
8697         } else {
8698                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8699                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8700
8701                 if (is_lvds) {
8702                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8703                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8704
8705                         if (lvds & LVDS_CLKB_POWER_UP)
8706                                 clock.p2 = 7;
8707                         else
8708                                 clock.p2 = 14;
8709                 } else {
8710                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8711                                 clock.p1 = 2;
8712                         else {
8713                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8714                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8715                         }
8716                         if (dpll & PLL_P2_DIVIDE_BY_4)
8717                                 clock.p2 = 4;
8718                         else
8719                                 clock.p2 = 2;
8720                 }
8721
8722                 i9xx_clock(refclk, &clock);
8723         }
8724
8725         /*
8726          * This value includes pixel_multiplier. We will use
8727          * port_clock to compute adjusted_mode.crtc_clock in the
8728          * encoder's get_config() function.
8729          */
8730         pipe_config->port_clock = clock.dot;
8731 }
8732
8733 int intel_dotclock_calculate(int link_freq,
8734                              const struct intel_link_m_n *m_n)
8735 {
8736         /*
8737          * The calculation for the data clock is:
8738          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8739          * But we want to avoid losing precison if possible, so:
8740          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8741          *
8742          * and the link clock is simpler:
8743          * link_clock = (m * link_clock) / n
8744          */
8745
8746         if (!m_n->link_n)
8747                 return 0;
8748
8749         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8750 }
8751
8752 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8753                                    struct intel_crtc_config *pipe_config)
8754 {
8755         struct drm_device *dev = crtc->base.dev;
8756
8757         /* read out port_clock from the DPLL */
8758         i9xx_crtc_clock_get(crtc, pipe_config);
8759
8760         /*
8761          * This value does not include pixel_multiplier.
8762          * We will check that port_clock and adjusted_mode.crtc_clock
8763          * agree once we know their relationship in the encoder's
8764          * get_config() function.
8765          */
8766         pipe_config->adjusted_mode.crtc_clock =
8767                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8768                                          &pipe_config->fdi_m_n);
8769 }
8770
8771 /** Returns the currently programmed mode of the given pipe. */
8772 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8773                                              struct drm_crtc *crtc)
8774 {
8775         struct drm_i915_private *dev_priv = dev->dev_private;
8776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8777         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8778         struct drm_display_mode *mode;
8779         struct intel_crtc_config pipe_config;
8780         int htot = I915_READ(HTOTAL(cpu_transcoder));
8781         int hsync = I915_READ(HSYNC(cpu_transcoder));
8782         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8783         int vsync = I915_READ(VSYNC(cpu_transcoder));
8784         enum pipe pipe = intel_crtc->pipe;
8785
8786         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8787         if (!mode)
8788                 return NULL;
8789
8790         /*
8791          * Construct a pipe_config sufficient for getting the clock info
8792          * back out of crtc_clock_get.
8793          *
8794          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8795          * to use a real value here instead.
8796          */
8797         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8798         pipe_config.pixel_multiplier = 1;
8799         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8800         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8801         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8802         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8803
8804         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8805         mode->hdisplay = (htot & 0xffff) + 1;
8806         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8807         mode->hsync_start = (hsync & 0xffff) + 1;
8808         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8809         mode->vdisplay = (vtot & 0xffff) + 1;
8810         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8811         mode->vsync_start = (vsync & 0xffff) + 1;
8812         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8813
8814         drm_mode_set_name(mode);
8815
8816         return mode;
8817 }
8818
8819 static void intel_increase_pllclock(struct drm_device *dev,
8820                                     enum pipe pipe)
8821 {
8822         struct drm_i915_private *dev_priv = dev->dev_private;
8823         int dpll_reg = DPLL(pipe);
8824         int dpll;
8825
8826         if (!HAS_GMCH_DISPLAY(dev))
8827                 return;
8828
8829         if (!dev_priv->lvds_downclock_avail)
8830                 return;
8831
8832         dpll = I915_READ(dpll_reg);
8833         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8834                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8835
8836                 assert_panel_unlocked(dev_priv, pipe);
8837
8838                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8839                 I915_WRITE(dpll_reg, dpll);
8840                 intel_wait_for_vblank(dev, pipe);
8841
8842                 dpll = I915_READ(dpll_reg);
8843                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8844                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8845         }
8846 }
8847
8848 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8849 {
8850         struct drm_device *dev = crtc->dev;
8851         struct drm_i915_private *dev_priv = dev->dev_private;
8852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8853
8854         if (!HAS_GMCH_DISPLAY(dev))
8855                 return;
8856
8857         if (!dev_priv->lvds_downclock_avail)
8858                 return;
8859
8860         /*
8861          * Since this is called by a timer, we should never get here in
8862          * the manual case.
8863          */
8864         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8865                 int pipe = intel_crtc->pipe;
8866                 int dpll_reg = DPLL(pipe);
8867                 int dpll;
8868
8869                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8870
8871                 assert_panel_unlocked(dev_priv, pipe);
8872
8873                 dpll = I915_READ(dpll_reg);
8874                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8875                 I915_WRITE(dpll_reg, dpll);
8876                 intel_wait_for_vblank(dev, pipe);
8877                 dpll = I915_READ(dpll_reg);
8878                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8879                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8880         }
8881
8882 }
8883
8884 void intel_mark_busy(struct drm_device *dev)
8885 {
8886         struct drm_i915_private *dev_priv = dev->dev_private;
8887
8888         if (dev_priv->mm.busy)
8889                 return;
8890
8891         intel_runtime_pm_get(dev_priv);
8892         i915_update_gfx_val(dev_priv);
8893         dev_priv->mm.busy = true;
8894 }
8895
8896 void intel_mark_idle(struct drm_device *dev)
8897 {
8898         struct drm_i915_private *dev_priv = dev->dev_private;
8899         struct drm_crtc *crtc;
8900
8901         if (!dev_priv->mm.busy)
8902                 return;
8903
8904         dev_priv->mm.busy = false;
8905
8906         if (!i915.powersave)
8907                 goto out;
8908
8909         for_each_crtc(dev, crtc) {
8910                 if (!crtc->primary->fb)
8911                         continue;
8912
8913                 intel_decrease_pllclock(crtc);
8914         }
8915
8916         if (INTEL_INFO(dev)->gen >= 6)
8917                 gen6_rps_idle(dev->dev_private);
8918
8919 out:
8920         intel_runtime_pm_put(dev_priv);
8921 }
8922
8923
8924 /**
8925  * intel_mark_fb_busy - mark given planes as busy
8926  * @dev: DRM device
8927  * @frontbuffer_bits: bits for the affected planes
8928  * @ring: optional ring for asynchronous commands
8929  *
8930  * This function gets called every time the screen contents change. It can be
8931  * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8932  */
8933 static void intel_mark_fb_busy(struct drm_device *dev,
8934                                unsigned frontbuffer_bits,
8935                                struct intel_engine_cs *ring)
8936 {
8937         enum pipe pipe;
8938
8939         if (!i915.powersave)
8940                 return;
8941
8942         for_each_pipe(pipe) {
8943                 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8944                         continue;
8945
8946                 intel_increase_pllclock(dev, pipe);
8947                 if (ring && intel_fbc_enabled(dev))
8948                         ring->fbc_dirty = true;
8949         }
8950 }
8951
8952 /**
8953  * intel_fb_obj_invalidate - invalidate frontbuffer object
8954  * @obj: GEM object to invalidate
8955  * @ring: set for asynchronous rendering
8956  *
8957  * This function gets called every time rendering on the given object starts and
8958  * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8959  * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8960  * until the rendering completes or a flip on this frontbuffer plane is
8961  * scheduled.
8962  */
8963 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8964                              struct intel_engine_cs *ring)
8965 {
8966         struct drm_device *dev = obj->base.dev;
8967         struct drm_i915_private *dev_priv = dev->dev_private;
8968
8969         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8970
8971         if (!obj->frontbuffer_bits)
8972                 return;
8973
8974         if (ring) {
8975                 mutex_lock(&dev_priv->fb_tracking.lock);
8976                 dev_priv->fb_tracking.busy_bits
8977                         |= obj->frontbuffer_bits;
8978                 dev_priv->fb_tracking.flip_bits
8979                         &= ~obj->frontbuffer_bits;
8980                 mutex_unlock(&dev_priv->fb_tracking.lock);
8981         }
8982
8983         intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8984
8985         intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
8986 }
8987
8988 /**
8989  * intel_frontbuffer_flush - flush frontbuffer
8990  * @dev: DRM device
8991  * @frontbuffer_bits: frontbuffer plane tracking bits
8992  *
8993  * This function gets called every time rendering on the given planes has
8994  * completed and frontbuffer caching can be started again. Flushes will get
8995  * delayed if they're blocked by some oustanding asynchronous rendering.
8996  *
8997  * Can be called without any locks held.
8998  */
8999 void intel_frontbuffer_flush(struct drm_device *dev,
9000                              unsigned frontbuffer_bits)
9001 {
9002         struct drm_i915_private *dev_priv = dev->dev_private;
9003
9004         /* Delay flushing when rings are still busy.*/
9005         mutex_lock(&dev_priv->fb_tracking.lock);
9006         frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9007         mutex_unlock(&dev_priv->fb_tracking.lock);
9008
9009         intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9010
9011         intel_edp_psr_flush(dev, frontbuffer_bits);
9012 }
9013
9014 /**
9015  * intel_fb_obj_flush - flush frontbuffer object
9016  * @obj: GEM object to flush
9017  * @retire: set when retiring asynchronous rendering
9018  *
9019  * This function gets called every time rendering on the given object has
9020  * completed and frontbuffer caching can be started again. If @retire is true
9021  * then any delayed flushes will be unblocked.
9022  */
9023 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9024                         bool retire)
9025 {
9026         struct drm_device *dev = obj->base.dev;
9027         struct drm_i915_private *dev_priv = dev->dev_private;
9028         unsigned frontbuffer_bits;
9029
9030         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9031
9032         if (!obj->frontbuffer_bits)
9033                 return;
9034
9035         frontbuffer_bits = obj->frontbuffer_bits;
9036
9037         if (retire) {
9038                 mutex_lock(&dev_priv->fb_tracking.lock);
9039                 /* Filter out new bits since rendering started. */
9040                 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9041
9042                 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9043                 mutex_unlock(&dev_priv->fb_tracking.lock);
9044         }
9045
9046         intel_frontbuffer_flush(dev, frontbuffer_bits);
9047 }
9048
9049 /**
9050  * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9051  * @dev: DRM device
9052  * @frontbuffer_bits: frontbuffer plane tracking bits
9053  *
9054  * This function gets called after scheduling a flip on @obj. The actual
9055  * frontbuffer flushing will be delayed until completion is signalled with
9056  * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9057  * flush will be cancelled.
9058  *
9059  * Can be called without any locks held.
9060  */
9061 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9062                                     unsigned frontbuffer_bits)
9063 {
9064         struct drm_i915_private *dev_priv = dev->dev_private;
9065
9066         mutex_lock(&dev_priv->fb_tracking.lock);
9067         dev_priv->fb_tracking.flip_bits
9068                 |= frontbuffer_bits;
9069         mutex_unlock(&dev_priv->fb_tracking.lock);
9070 }
9071
9072 /**
9073  * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9074  * @dev: DRM device
9075  * @frontbuffer_bits: frontbuffer plane tracking bits
9076  *
9077  * This function gets called after the flip has been latched and will complete
9078  * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9079  *
9080  * Can be called without any locks held.
9081  */
9082 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9083                                      unsigned frontbuffer_bits)
9084 {
9085         struct drm_i915_private *dev_priv = dev->dev_private;
9086
9087         mutex_lock(&dev_priv->fb_tracking.lock);
9088         /* Mask any cancelled flips. */
9089         frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9090         dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9091         mutex_unlock(&dev_priv->fb_tracking.lock);
9092
9093         intel_frontbuffer_flush(dev, frontbuffer_bits);
9094 }
9095
9096 static void intel_crtc_destroy(struct drm_crtc *crtc)
9097 {
9098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9099         struct drm_device *dev = crtc->dev;
9100         struct intel_unpin_work *work;
9101         unsigned long flags;
9102
9103         spin_lock_irqsave(&dev->event_lock, flags);
9104         work = intel_crtc->unpin_work;
9105         intel_crtc->unpin_work = NULL;
9106         spin_unlock_irqrestore(&dev->event_lock, flags);
9107
9108         if (work) {
9109                 cancel_work_sync(&work->work);
9110                 kfree(work);
9111         }
9112
9113         drm_crtc_cleanup(crtc);
9114
9115         kfree(intel_crtc);
9116 }
9117
9118 static void intel_unpin_work_fn(struct work_struct *__work)
9119 {
9120         struct intel_unpin_work *work =
9121                 container_of(__work, struct intel_unpin_work, work);
9122         struct drm_device *dev = work->crtc->dev;
9123         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9124
9125         mutex_lock(&dev->struct_mutex);
9126         intel_unpin_fb_obj(work->old_fb_obj);
9127         drm_gem_object_unreference(&work->pending_flip_obj->base);
9128         drm_gem_object_unreference(&work->old_fb_obj->base);
9129
9130         intel_update_fbc(dev);
9131         mutex_unlock(&dev->struct_mutex);
9132
9133         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9134
9135         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9136         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9137
9138         kfree(work);
9139 }
9140
9141 static void do_intel_finish_page_flip(struct drm_device *dev,
9142                                       struct drm_crtc *crtc)
9143 {
9144         struct drm_i915_private *dev_priv = dev->dev_private;
9145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9146         struct intel_unpin_work *work;
9147         unsigned long flags;
9148
9149         /* Ignore early vblank irqs */
9150         if (intel_crtc == NULL)
9151                 return;
9152
9153         spin_lock_irqsave(&dev->event_lock, flags);
9154         work = intel_crtc->unpin_work;
9155
9156         /* Ensure we don't miss a work->pending update ... */
9157         smp_rmb();
9158
9159         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9160                 spin_unlock_irqrestore(&dev->event_lock, flags);
9161                 return;
9162         }
9163
9164         /* and that the unpin work is consistent wrt ->pending. */
9165         smp_rmb();
9166
9167         intel_crtc->unpin_work = NULL;
9168
9169         if (work->event)
9170                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9171
9172         drm_crtc_vblank_put(crtc);
9173
9174         spin_unlock_irqrestore(&dev->event_lock, flags);
9175
9176         wake_up_all(&dev_priv->pending_flip_queue);
9177
9178         queue_work(dev_priv->wq, &work->work);
9179
9180         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9181 }
9182
9183 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9184 {
9185         struct drm_i915_private *dev_priv = dev->dev_private;
9186         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9187
9188         do_intel_finish_page_flip(dev, crtc);
9189 }
9190
9191 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9192 {
9193         struct drm_i915_private *dev_priv = dev->dev_private;
9194         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9195
9196         do_intel_finish_page_flip(dev, crtc);
9197 }
9198
9199 /* Is 'a' after or equal to 'b'? */
9200 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9201 {
9202         return !((a - b) & 0x80000000);
9203 }
9204
9205 static bool page_flip_finished(struct intel_crtc *crtc)
9206 {
9207         struct drm_device *dev = crtc->base.dev;
9208         struct drm_i915_private *dev_priv = dev->dev_private;
9209
9210         /*
9211          * The relevant registers doen't exist on pre-ctg.
9212          * As the flip done interrupt doesn't trigger for mmio
9213          * flips on gmch platforms, a flip count check isn't
9214          * really needed there. But since ctg has the registers,
9215          * include it in the check anyway.
9216          */
9217         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9218                 return true;
9219
9220         /*
9221          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9222          * used the same base address. In that case the mmio flip might
9223          * have completed, but the CS hasn't even executed the flip yet.
9224          *
9225          * A flip count check isn't enough as the CS might have updated
9226          * the base address just after start of vblank, but before we
9227          * managed to process the interrupt. This means we'd complete the
9228          * CS flip too soon.
9229          *
9230          * Combining both checks should get us a good enough result. It may
9231          * still happen that the CS flip has been executed, but has not
9232          * yet actually completed. But in case the base address is the same
9233          * anyway, we don't really care.
9234          */
9235         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9236                 crtc->unpin_work->gtt_offset &&
9237                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9238                                     crtc->unpin_work->flip_count);
9239 }
9240
9241 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9242 {
9243         struct drm_i915_private *dev_priv = dev->dev_private;
9244         struct intel_crtc *intel_crtc =
9245                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9246         unsigned long flags;
9247
9248         /* NB: An MMIO update of the plane base pointer will also
9249          * generate a page-flip completion irq, i.e. every modeset
9250          * is also accompanied by a spurious intel_prepare_page_flip().
9251          */
9252         spin_lock_irqsave(&dev->event_lock, flags);
9253         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9254                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9255         spin_unlock_irqrestore(&dev->event_lock, flags);
9256 }
9257
9258 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9259 {
9260         /* Ensure that the work item is consistent when activating it ... */
9261         smp_wmb();
9262         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9263         /* and that it is marked active as soon as the irq could fire. */
9264         smp_wmb();
9265 }
9266
9267 static int intel_gen2_queue_flip(struct drm_device *dev,
9268                                  struct drm_crtc *crtc,
9269                                  struct drm_framebuffer *fb,
9270                                  struct drm_i915_gem_object *obj,
9271                                  struct intel_engine_cs *ring,
9272                                  uint32_t flags)
9273 {
9274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9275         u32 flip_mask;
9276         int ret;
9277
9278         ret = intel_ring_begin(ring, 6);
9279         if (ret)
9280                 return ret;
9281
9282         /* Can't queue multiple flips, so wait for the previous
9283          * one to finish before executing the next.
9284          */
9285         if (intel_crtc->plane)
9286                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9287         else
9288                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9289         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9290         intel_ring_emit(ring, MI_NOOP);
9291         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9292                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9293         intel_ring_emit(ring, fb->pitches[0]);
9294         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9295         intel_ring_emit(ring, 0); /* aux display base address, unused */
9296
9297         intel_mark_page_flip_active(intel_crtc);
9298         __intel_ring_advance(ring);
9299         return 0;
9300 }
9301
9302 static int intel_gen3_queue_flip(struct drm_device *dev,
9303                                  struct drm_crtc *crtc,
9304                                  struct drm_framebuffer *fb,
9305                                  struct drm_i915_gem_object *obj,
9306                                  struct intel_engine_cs *ring,
9307                                  uint32_t flags)
9308 {
9309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9310         u32 flip_mask;
9311         int ret;
9312
9313         ret = intel_ring_begin(ring, 6);
9314         if (ret)
9315                 return ret;
9316
9317         if (intel_crtc->plane)
9318                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9319         else
9320                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9321         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9322         intel_ring_emit(ring, MI_NOOP);
9323         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9324                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9325         intel_ring_emit(ring, fb->pitches[0]);
9326         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9327         intel_ring_emit(ring, MI_NOOP);
9328
9329         intel_mark_page_flip_active(intel_crtc);
9330         __intel_ring_advance(ring);
9331         return 0;
9332 }
9333
9334 static int intel_gen4_queue_flip(struct drm_device *dev,
9335                                  struct drm_crtc *crtc,
9336                                  struct drm_framebuffer *fb,
9337                                  struct drm_i915_gem_object *obj,
9338                                  struct intel_engine_cs *ring,
9339                                  uint32_t flags)
9340 {
9341         struct drm_i915_private *dev_priv = dev->dev_private;
9342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9343         uint32_t pf, pipesrc;
9344         int ret;
9345
9346         ret = intel_ring_begin(ring, 4);
9347         if (ret)
9348                 return ret;
9349
9350         /* i965+ uses the linear or tiled offsets from the
9351          * Display Registers (which do not change across a page-flip)
9352          * so we need only reprogram the base address.
9353          */
9354         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9355                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9356         intel_ring_emit(ring, fb->pitches[0]);
9357         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9358                         obj->tiling_mode);
9359
9360         /* XXX Enabling the panel-fitter across page-flip is so far
9361          * untested on non-native modes, so ignore it for now.
9362          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9363          */
9364         pf = 0;
9365         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9366         intel_ring_emit(ring, pf | pipesrc);
9367
9368         intel_mark_page_flip_active(intel_crtc);
9369         __intel_ring_advance(ring);
9370         return 0;
9371 }
9372
9373 static int intel_gen6_queue_flip(struct drm_device *dev,
9374                                  struct drm_crtc *crtc,
9375                                  struct drm_framebuffer *fb,
9376                                  struct drm_i915_gem_object *obj,
9377                                  struct intel_engine_cs *ring,
9378                                  uint32_t flags)
9379 {
9380         struct drm_i915_private *dev_priv = dev->dev_private;
9381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9382         uint32_t pf, pipesrc;
9383         int ret;
9384
9385         ret = intel_ring_begin(ring, 4);
9386         if (ret)
9387                 return ret;
9388
9389         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9390                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9391         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9392         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9393
9394         /* Contrary to the suggestions in the documentation,
9395          * "Enable Panel Fitter" does not seem to be required when page
9396          * flipping with a non-native mode, and worse causes a normal
9397          * modeset to fail.
9398          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9399          */
9400         pf = 0;
9401         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9402         intel_ring_emit(ring, pf | pipesrc);
9403
9404         intel_mark_page_flip_active(intel_crtc);
9405         __intel_ring_advance(ring);
9406         return 0;
9407 }
9408
9409 static int intel_gen7_queue_flip(struct drm_device *dev,
9410                                  struct drm_crtc *crtc,
9411                                  struct drm_framebuffer *fb,
9412                                  struct drm_i915_gem_object *obj,
9413                                  struct intel_engine_cs *ring,
9414                                  uint32_t flags)
9415 {
9416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9417         uint32_t plane_bit = 0;
9418         int len, ret;
9419
9420         switch (intel_crtc->plane) {
9421         case PLANE_A:
9422                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9423                 break;
9424         case PLANE_B:
9425                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9426                 break;
9427         case PLANE_C:
9428                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9429                 break;
9430         default:
9431                 WARN_ONCE(1, "unknown plane in flip command\n");
9432                 return -ENODEV;
9433         }
9434
9435         len = 4;
9436         if (ring->id == RCS) {
9437                 len += 6;
9438                 /*
9439                  * On Gen 8, SRM is now taking an extra dword to accommodate
9440                  * 48bits addresses, and we need a NOOP for the batch size to
9441                  * stay even.
9442                  */
9443                 if (IS_GEN8(dev))
9444                         len += 2;
9445         }
9446
9447         /*
9448          * BSpec MI_DISPLAY_FLIP for IVB:
9449          * "The full packet must be contained within the same cache line."
9450          *
9451          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9452          * cacheline, if we ever start emitting more commands before
9453          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9454          * then do the cacheline alignment, and finally emit the
9455          * MI_DISPLAY_FLIP.
9456          */
9457         ret = intel_ring_cacheline_align(ring);
9458         if (ret)
9459                 return ret;
9460
9461         ret = intel_ring_begin(ring, len);
9462         if (ret)
9463                 return ret;
9464
9465         /* Unmask the flip-done completion message. Note that the bspec says that
9466          * we should do this for both the BCS and RCS, and that we must not unmask
9467          * more than one flip event at any time (or ensure that one flip message
9468          * can be sent by waiting for flip-done prior to queueing new flips).
9469          * Experimentation says that BCS works despite DERRMR masking all
9470          * flip-done completion events and that unmasking all planes at once
9471          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9472          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9473          */
9474         if (ring->id == RCS) {
9475                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9476                 intel_ring_emit(ring, DERRMR);
9477                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9478                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9479                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9480                 if (IS_GEN8(dev))
9481                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9482                                               MI_SRM_LRM_GLOBAL_GTT);
9483                 else
9484                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9485                                               MI_SRM_LRM_GLOBAL_GTT);
9486                 intel_ring_emit(ring, DERRMR);
9487                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9488                 if (IS_GEN8(dev)) {
9489                         intel_ring_emit(ring, 0);
9490                         intel_ring_emit(ring, MI_NOOP);
9491                 }
9492         }
9493
9494         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9495         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9496         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9497         intel_ring_emit(ring, (MI_NOOP));
9498
9499         intel_mark_page_flip_active(intel_crtc);
9500         __intel_ring_advance(ring);
9501         return 0;
9502 }
9503
9504 static bool use_mmio_flip(struct intel_engine_cs *ring,
9505                           struct drm_i915_gem_object *obj)
9506 {
9507         /*
9508          * This is not being used for older platforms, because
9509          * non-availability of flip done interrupt forces us to use
9510          * CS flips. Older platforms derive flip done using some clever
9511          * tricks involving the flip_pending status bits and vblank irqs.
9512          * So using MMIO flips there would disrupt this mechanism.
9513          */
9514
9515         if (ring == NULL)
9516                 return true;
9517
9518         if (INTEL_INFO(ring->dev)->gen < 5)
9519                 return false;
9520
9521         if (i915.use_mmio_flip < 0)
9522                 return false;
9523         else if (i915.use_mmio_flip > 0)
9524                 return true;
9525         else
9526                 return ring != obj->ring;
9527 }
9528
9529 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9530 {
9531         struct drm_device *dev = intel_crtc->base.dev;
9532         struct drm_i915_private *dev_priv = dev->dev_private;
9533         struct intel_framebuffer *intel_fb =
9534                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9535         struct drm_i915_gem_object *obj = intel_fb->obj;
9536         u32 dspcntr;
9537         u32 reg;
9538
9539         intel_mark_page_flip_active(intel_crtc);
9540
9541         reg = DSPCNTR(intel_crtc->plane);
9542         dspcntr = I915_READ(reg);
9543
9544         if (INTEL_INFO(dev)->gen >= 4) {
9545                 if (obj->tiling_mode != I915_TILING_NONE)
9546                         dspcntr |= DISPPLANE_TILED;
9547                 else
9548                         dspcntr &= ~DISPPLANE_TILED;
9549         }
9550         I915_WRITE(reg, dspcntr);
9551
9552         I915_WRITE(DSPSURF(intel_crtc->plane),
9553                    intel_crtc->unpin_work->gtt_offset);
9554         POSTING_READ(DSPSURF(intel_crtc->plane));
9555 }
9556
9557 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9558 {
9559         struct intel_engine_cs *ring;
9560         int ret;
9561
9562         lockdep_assert_held(&obj->base.dev->struct_mutex);
9563
9564         if (!obj->last_write_seqno)
9565                 return 0;
9566
9567         ring = obj->ring;
9568
9569         if (i915_seqno_passed(ring->get_seqno(ring, true),
9570                               obj->last_write_seqno))
9571                 return 0;
9572
9573         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9574         if (ret)
9575                 return ret;
9576
9577         if (WARN_ON(!ring->irq_get(ring)))
9578                 return 0;
9579
9580         return 1;
9581 }
9582
9583 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9584 {
9585         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9586         struct intel_crtc *intel_crtc;
9587         unsigned long irq_flags;
9588         u32 seqno;
9589
9590         seqno = ring->get_seqno(ring, false);
9591
9592         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9593         for_each_intel_crtc(ring->dev, intel_crtc) {
9594                 struct intel_mmio_flip *mmio_flip;
9595
9596                 mmio_flip = &intel_crtc->mmio_flip;
9597                 if (mmio_flip->seqno == 0)
9598                         continue;
9599
9600                 if (ring->id != mmio_flip->ring_id)
9601                         continue;
9602
9603                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9604                         intel_do_mmio_flip(intel_crtc);
9605                         mmio_flip->seqno = 0;
9606                         ring->irq_put(ring);
9607                 }
9608         }
9609         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9610 }
9611
9612 static int intel_queue_mmio_flip(struct drm_device *dev,
9613                                  struct drm_crtc *crtc,
9614                                  struct drm_framebuffer *fb,
9615                                  struct drm_i915_gem_object *obj,
9616                                  struct intel_engine_cs *ring,
9617                                  uint32_t flags)
9618 {
9619         struct drm_i915_private *dev_priv = dev->dev_private;
9620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9621         unsigned long irq_flags;
9622         int ret;
9623
9624         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9625                 return -EBUSY;
9626
9627         ret = intel_postpone_flip(obj);
9628         if (ret < 0)
9629                 return ret;
9630         if (ret == 0) {
9631                 intel_do_mmio_flip(intel_crtc);
9632                 return 0;
9633         }
9634
9635         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9636         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9637         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9638         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9639
9640         /*
9641          * Double check to catch cases where irq fired before
9642          * mmio flip data was ready
9643          */
9644         intel_notify_mmio_flip(obj->ring);
9645         return 0;
9646 }
9647
9648 static int intel_default_queue_flip(struct drm_device *dev,
9649                                     struct drm_crtc *crtc,
9650                                     struct drm_framebuffer *fb,
9651                                     struct drm_i915_gem_object *obj,
9652                                     struct intel_engine_cs *ring,
9653                                     uint32_t flags)
9654 {
9655         return -ENODEV;
9656 }
9657
9658 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9659                                 struct drm_framebuffer *fb,
9660                                 struct drm_pending_vblank_event *event,
9661                                 uint32_t page_flip_flags)
9662 {
9663         struct drm_device *dev = crtc->dev;
9664         struct drm_i915_private *dev_priv = dev->dev_private;
9665         struct drm_framebuffer *old_fb = crtc->primary->fb;
9666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9668         enum pipe pipe = intel_crtc->pipe;
9669         struct intel_unpin_work *work;
9670         struct intel_engine_cs *ring;
9671         unsigned long flags;
9672         int ret;
9673
9674         /*
9675          * drm_mode_page_flip_ioctl() should already catch this, but double
9676          * check to be safe.  In the future we may enable pageflipping from
9677          * a disabled primary plane.
9678          */
9679         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9680                 return -EBUSY;
9681
9682         /* Can't change pixel format via MI display flips. */
9683         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9684                 return -EINVAL;
9685
9686         /*
9687          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9688          * Note that pitch changes could also affect these register.
9689          */
9690         if (INTEL_INFO(dev)->gen > 3 &&
9691             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9692              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9693                 return -EINVAL;
9694
9695         if (i915_terminally_wedged(&dev_priv->gpu_error))
9696                 goto out_hang;
9697
9698         work = kzalloc(sizeof(*work), GFP_KERNEL);
9699         if (work == NULL)
9700                 return -ENOMEM;
9701
9702         work->event = event;
9703         work->crtc = crtc;
9704         work->old_fb_obj = intel_fb_obj(old_fb);
9705         INIT_WORK(&work->work, intel_unpin_work_fn);
9706
9707         ret = drm_crtc_vblank_get(crtc);
9708         if (ret)
9709                 goto free_work;
9710
9711         /* We borrow the event spin lock for protecting unpin_work */
9712         spin_lock_irqsave(&dev->event_lock, flags);
9713         if (intel_crtc->unpin_work) {
9714                 spin_unlock_irqrestore(&dev->event_lock, flags);
9715                 kfree(work);
9716                 drm_crtc_vblank_put(crtc);
9717
9718                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9719                 return -EBUSY;
9720         }
9721         intel_crtc->unpin_work = work;
9722         spin_unlock_irqrestore(&dev->event_lock, flags);
9723
9724         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9725                 flush_workqueue(dev_priv->wq);
9726
9727         ret = i915_mutex_lock_interruptible(dev);
9728         if (ret)
9729                 goto cleanup;
9730
9731         /* Reference the objects for the scheduled work. */
9732         drm_gem_object_reference(&work->old_fb_obj->base);
9733         drm_gem_object_reference(&obj->base);
9734
9735         crtc->primary->fb = fb;
9736
9737         work->pending_flip_obj = obj;
9738
9739         work->enable_stall_check = true;
9740
9741         atomic_inc(&intel_crtc->unpin_work_count);
9742         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9743
9744         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9745                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9746
9747         if (IS_VALLEYVIEW(dev)) {
9748                 ring = &dev_priv->ring[BCS];
9749                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9750                         /* vlv: DISPLAY_FLIP fails to change tiling */
9751                         ring = NULL;
9752         } else if (IS_IVYBRIDGE(dev)) {
9753                 ring = &dev_priv->ring[BCS];
9754         } else if (INTEL_INFO(dev)->gen >= 7) {
9755                 ring = obj->ring;
9756                 if (ring == NULL || ring->id != RCS)
9757                         ring = &dev_priv->ring[BCS];
9758         } else {
9759                 ring = &dev_priv->ring[RCS];
9760         }
9761
9762         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9763         if (ret)
9764                 goto cleanup_pending;
9765
9766         work->gtt_offset =
9767                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9768
9769         if (use_mmio_flip(ring, obj))
9770                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9771                                             page_flip_flags);
9772         else
9773                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9774                                 page_flip_flags);
9775         if (ret)
9776                 goto cleanup_unpin;
9777
9778         i915_gem_track_fb(work->old_fb_obj, obj,
9779                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9780
9781         intel_disable_fbc(dev);
9782         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9783         mutex_unlock(&dev->struct_mutex);
9784
9785         trace_i915_flip_request(intel_crtc->plane, obj);
9786
9787         return 0;
9788
9789 cleanup_unpin:
9790         intel_unpin_fb_obj(obj);
9791 cleanup_pending:
9792         atomic_dec(&intel_crtc->unpin_work_count);
9793         crtc->primary->fb = old_fb;
9794         drm_gem_object_unreference(&work->old_fb_obj->base);
9795         drm_gem_object_unreference(&obj->base);
9796         mutex_unlock(&dev->struct_mutex);
9797
9798 cleanup:
9799         spin_lock_irqsave(&dev->event_lock, flags);
9800         intel_crtc->unpin_work = NULL;
9801         spin_unlock_irqrestore(&dev->event_lock, flags);
9802
9803         drm_crtc_vblank_put(crtc);
9804 free_work:
9805         kfree(work);
9806
9807         if (ret == -EIO) {
9808 out_hang:
9809                 intel_crtc_wait_for_pending_flips(crtc);
9810                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9811                 if (ret == 0 && event)
9812                         drm_send_vblank_event(dev, pipe, event);
9813         }
9814         return ret;
9815 }
9816
9817 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9818         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9819         .load_lut = intel_crtc_load_lut,
9820 };
9821
9822 /**
9823  * intel_modeset_update_staged_output_state
9824  *
9825  * Updates the staged output configuration state, e.g. after we've read out the
9826  * current hw state.
9827  */
9828 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9829 {
9830         struct intel_crtc *crtc;
9831         struct intel_encoder *encoder;
9832         struct intel_connector *connector;
9833
9834         list_for_each_entry(connector, &dev->mode_config.connector_list,
9835                             base.head) {
9836                 connector->new_encoder =
9837                         to_intel_encoder(connector->base.encoder);
9838         }
9839
9840         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9841                             base.head) {
9842                 encoder->new_crtc =
9843                         to_intel_crtc(encoder->base.crtc);
9844         }
9845
9846         for_each_intel_crtc(dev, crtc) {
9847                 crtc->new_enabled = crtc->base.enabled;
9848
9849                 if (crtc->new_enabled)
9850                         crtc->new_config = &crtc->config;
9851                 else
9852                         crtc->new_config = NULL;
9853         }
9854 }
9855
9856 /**
9857  * intel_modeset_commit_output_state
9858  *
9859  * This function copies the stage display pipe configuration to the real one.
9860  */
9861 static void intel_modeset_commit_output_state(struct drm_device *dev)
9862 {
9863         struct intel_crtc *crtc;
9864         struct intel_encoder *encoder;
9865         struct intel_connector *connector;
9866
9867         list_for_each_entry(connector, &dev->mode_config.connector_list,
9868                             base.head) {
9869                 connector->base.encoder = &connector->new_encoder->base;
9870         }
9871
9872         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9873                             base.head) {
9874                 encoder->base.crtc = &encoder->new_crtc->base;
9875         }
9876
9877         for_each_intel_crtc(dev, crtc) {
9878                 crtc->base.enabled = crtc->new_enabled;
9879         }
9880 }
9881
9882 static void
9883 connected_sink_compute_bpp(struct intel_connector *connector,
9884                            struct intel_crtc_config *pipe_config)
9885 {
9886         int bpp = pipe_config->pipe_bpp;
9887
9888         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9889                 connector->base.base.id,
9890                 connector->base.name);
9891
9892         /* Don't use an invalid EDID bpc value */
9893         if (connector->base.display_info.bpc &&
9894             connector->base.display_info.bpc * 3 < bpp) {
9895                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9896                               bpp, connector->base.display_info.bpc*3);
9897                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9898         }
9899
9900         /* Clamp bpp to 8 on screens without EDID 1.4 */
9901         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9902                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9903                               bpp);
9904                 pipe_config->pipe_bpp = 24;
9905         }
9906 }
9907
9908 static int
9909 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9910                           struct drm_framebuffer *fb,
9911                           struct intel_crtc_config *pipe_config)
9912 {
9913         struct drm_device *dev = crtc->base.dev;
9914         struct intel_connector *connector;
9915         int bpp;
9916
9917         switch (fb->pixel_format) {
9918         case DRM_FORMAT_C8:
9919                 bpp = 8*3; /* since we go through a colormap */
9920                 break;
9921         case DRM_FORMAT_XRGB1555:
9922         case DRM_FORMAT_ARGB1555:
9923                 /* checked in intel_framebuffer_init already */
9924                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9925                         return -EINVAL;
9926         case DRM_FORMAT_RGB565:
9927                 bpp = 6*3; /* min is 18bpp */
9928                 break;
9929         case DRM_FORMAT_XBGR8888:
9930         case DRM_FORMAT_ABGR8888:
9931                 /* checked in intel_framebuffer_init already */
9932                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9933                         return -EINVAL;
9934         case DRM_FORMAT_XRGB8888:
9935         case DRM_FORMAT_ARGB8888:
9936                 bpp = 8*3;
9937                 break;
9938         case DRM_FORMAT_XRGB2101010:
9939         case DRM_FORMAT_ARGB2101010:
9940         case DRM_FORMAT_XBGR2101010:
9941         case DRM_FORMAT_ABGR2101010:
9942                 /* checked in intel_framebuffer_init already */
9943                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9944                         return -EINVAL;
9945                 bpp = 10*3;
9946                 break;
9947         /* TODO: gen4+ supports 16 bpc floating point, too. */
9948         default:
9949                 DRM_DEBUG_KMS("unsupported depth\n");
9950                 return -EINVAL;
9951         }
9952
9953         pipe_config->pipe_bpp = bpp;
9954
9955         /* Clamp display bpp to EDID value */
9956         list_for_each_entry(connector, &dev->mode_config.connector_list,
9957                             base.head) {
9958                 if (!connector->new_encoder ||
9959                     connector->new_encoder->new_crtc != crtc)
9960                         continue;
9961
9962                 connected_sink_compute_bpp(connector, pipe_config);
9963         }
9964
9965         return bpp;
9966 }
9967
9968 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9969 {
9970         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9971                         "type: 0x%x flags: 0x%x\n",
9972                 mode->crtc_clock,
9973                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9974                 mode->crtc_hsync_end, mode->crtc_htotal,
9975                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9976                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9977 }
9978
9979 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9980                                    struct intel_crtc_config *pipe_config,
9981                                    const char *context)
9982 {
9983         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9984                       context, pipe_name(crtc->pipe));
9985
9986         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9987         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9988                       pipe_config->pipe_bpp, pipe_config->dither);
9989         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9990                       pipe_config->has_pch_encoder,
9991                       pipe_config->fdi_lanes,
9992                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9993                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9994                       pipe_config->fdi_m_n.tu);
9995         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9996                       pipe_config->has_dp_encoder,
9997                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9998                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9999                       pipe_config->dp_m_n.tu);
10000         DRM_DEBUG_KMS("requested mode:\n");
10001         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10002         DRM_DEBUG_KMS("adjusted mode:\n");
10003         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10004         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10005         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10006         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10007                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10008         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10009                       pipe_config->gmch_pfit.control,
10010                       pipe_config->gmch_pfit.pgm_ratios,
10011                       pipe_config->gmch_pfit.lvds_border_bits);
10012         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10013                       pipe_config->pch_pfit.pos,
10014                       pipe_config->pch_pfit.size,
10015                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10016         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10017         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10018 }
10019
10020 static bool encoders_cloneable(const struct intel_encoder *a,
10021                                const struct intel_encoder *b)
10022 {
10023         /* masks could be asymmetric, so check both ways */
10024         return a == b || (a->cloneable & (1 << b->type) &&
10025                           b->cloneable & (1 << a->type));
10026 }
10027
10028 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10029                                          struct intel_encoder *encoder)
10030 {
10031         struct drm_device *dev = crtc->base.dev;
10032         struct intel_encoder *source_encoder;
10033
10034         list_for_each_entry(source_encoder,
10035                             &dev->mode_config.encoder_list, base.head) {
10036                 if (source_encoder->new_crtc != crtc)
10037                         continue;
10038
10039                 if (!encoders_cloneable(encoder, source_encoder))
10040                         return false;
10041         }
10042
10043         return true;
10044 }
10045
10046 static bool check_encoder_cloning(struct intel_crtc *crtc)
10047 {
10048         struct drm_device *dev = crtc->base.dev;
10049         struct intel_encoder *encoder;
10050
10051         list_for_each_entry(encoder,
10052                             &dev->mode_config.encoder_list, base.head) {
10053                 if (encoder->new_crtc != crtc)
10054                         continue;
10055
10056                 if (!check_single_encoder_cloning(crtc, encoder))
10057                         return false;
10058         }
10059
10060         return true;
10061 }
10062
10063 static struct intel_crtc_config *
10064 intel_modeset_pipe_config(struct drm_crtc *crtc,
10065                           struct drm_framebuffer *fb,
10066                           struct drm_display_mode *mode)
10067 {
10068         struct drm_device *dev = crtc->dev;
10069         struct intel_encoder *encoder;
10070         struct intel_crtc_config *pipe_config;
10071         int plane_bpp, ret = -EINVAL;
10072         bool retry = true;
10073
10074         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10075                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10076                 return ERR_PTR(-EINVAL);
10077         }
10078
10079         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10080         if (!pipe_config)
10081                 return ERR_PTR(-ENOMEM);
10082
10083         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10084         drm_mode_copy(&pipe_config->requested_mode, mode);
10085
10086         pipe_config->cpu_transcoder =
10087                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10088         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10089
10090         /*
10091          * Sanitize sync polarity flags based on requested ones. If neither
10092          * positive or negative polarity is requested, treat this as meaning
10093          * negative polarity.
10094          */
10095         if (!(pipe_config->adjusted_mode.flags &
10096               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10097                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10098
10099         if (!(pipe_config->adjusted_mode.flags &
10100               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10101                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10102
10103         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10104          * plane pixel format and any sink constraints into account. Returns the
10105          * source plane bpp so that dithering can be selected on mismatches
10106          * after encoders and crtc also have had their say. */
10107         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10108                                               fb, pipe_config);
10109         if (plane_bpp < 0)
10110                 goto fail;
10111
10112         /*
10113          * Determine the real pipe dimensions. Note that stereo modes can
10114          * increase the actual pipe size due to the frame doubling and
10115          * insertion of additional space for blanks between the frame. This
10116          * is stored in the crtc timings. We use the requested mode to do this
10117          * computation to clearly distinguish it from the adjusted mode, which
10118          * can be changed by the connectors in the below retry loop.
10119          */
10120         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10121         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10122         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10123
10124 encoder_retry:
10125         /* Ensure the port clock defaults are reset when retrying. */
10126         pipe_config->port_clock = 0;
10127         pipe_config->pixel_multiplier = 1;
10128
10129         /* Fill in default crtc timings, allow encoders to overwrite them. */
10130         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10131
10132         /* Pass our mode to the connectors and the CRTC to give them a chance to
10133          * adjust it according to limitations or connector properties, and also
10134          * a chance to reject the mode entirely.
10135          */
10136         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10137                             base.head) {
10138
10139                 if (&encoder->new_crtc->base != crtc)
10140                         continue;
10141
10142                 if (!(encoder->compute_config(encoder, pipe_config))) {
10143                         DRM_DEBUG_KMS("Encoder config failure\n");
10144                         goto fail;
10145                 }
10146         }
10147
10148         /* Set default port clock if not overwritten by the encoder. Needs to be
10149          * done afterwards in case the encoder adjusts the mode. */
10150         if (!pipe_config->port_clock)
10151                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10152                         * pipe_config->pixel_multiplier;
10153
10154         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10155         if (ret < 0) {
10156                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10157                 goto fail;
10158         }
10159
10160         if (ret == RETRY) {
10161                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10162                         ret = -EINVAL;
10163                         goto fail;
10164                 }
10165
10166                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10167                 retry = false;
10168                 goto encoder_retry;
10169         }
10170
10171         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10172         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10173                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10174
10175         return pipe_config;
10176 fail:
10177         kfree(pipe_config);
10178         return ERR_PTR(ret);
10179 }
10180
10181 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10182  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10183 static void
10184 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10185                              unsigned *prepare_pipes, unsigned *disable_pipes)
10186 {
10187         struct intel_crtc *intel_crtc;
10188         struct drm_device *dev = crtc->dev;
10189         struct intel_encoder *encoder;
10190         struct intel_connector *connector;
10191         struct drm_crtc *tmp_crtc;
10192
10193         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10194
10195         /* Check which crtcs have changed outputs connected to them, these need
10196          * to be part of the prepare_pipes mask. We don't (yet) support global
10197          * modeset across multiple crtcs, so modeset_pipes will only have one
10198          * bit set at most. */
10199         list_for_each_entry(connector, &dev->mode_config.connector_list,
10200                             base.head) {
10201                 if (connector->base.encoder == &connector->new_encoder->base)
10202                         continue;
10203
10204                 if (connector->base.encoder) {
10205                         tmp_crtc = connector->base.encoder->crtc;
10206
10207                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10208                 }
10209
10210                 if (connector->new_encoder)
10211                         *prepare_pipes |=
10212                                 1 << connector->new_encoder->new_crtc->pipe;
10213         }
10214
10215         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10216                             base.head) {
10217                 if (encoder->base.crtc == &encoder->new_crtc->base)
10218                         continue;
10219
10220                 if (encoder->base.crtc) {
10221                         tmp_crtc = encoder->base.crtc;
10222
10223                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10224                 }
10225
10226                 if (encoder->new_crtc)
10227                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10228         }
10229
10230         /* Check for pipes that will be enabled/disabled ... */
10231         for_each_intel_crtc(dev, intel_crtc) {
10232                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10233                         continue;
10234
10235                 if (!intel_crtc->new_enabled)
10236                         *disable_pipes |= 1 << intel_crtc->pipe;
10237                 else
10238                         *prepare_pipes |= 1 << intel_crtc->pipe;
10239         }
10240
10241
10242         /* set_mode is also used to update properties on life display pipes. */
10243         intel_crtc = to_intel_crtc(crtc);
10244         if (intel_crtc->new_enabled)
10245                 *prepare_pipes |= 1 << intel_crtc->pipe;
10246
10247         /*
10248          * For simplicity do a full modeset on any pipe where the output routing
10249          * changed. We could be more clever, but that would require us to be
10250          * more careful with calling the relevant encoder->mode_set functions.
10251          */
10252         if (*prepare_pipes)
10253                 *modeset_pipes = *prepare_pipes;
10254
10255         /* ... and mask these out. */
10256         *modeset_pipes &= ~(*disable_pipes);
10257         *prepare_pipes &= ~(*disable_pipes);
10258
10259         /*
10260          * HACK: We don't (yet) fully support global modesets. intel_set_config
10261          * obies this rule, but the modeset restore mode of
10262          * intel_modeset_setup_hw_state does not.
10263          */
10264         *modeset_pipes &= 1 << intel_crtc->pipe;
10265         *prepare_pipes &= 1 << intel_crtc->pipe;
10266
10267         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10268                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10269 }
10270
10271 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10272 {
10273         struct drm_encoder *encoder;
10274         struct drm_device *dev = crtc->dev;
10275
10276         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10277                 if (encoder->crtc == crtc)
10278                         return true;
10279
10280         return false;
10281 }
10282
10283 static void
10284 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10285 {
10286         struct intel_encoder *intel_encoder;
10287         struct intel_crtc *intel_crtc;
10288         struct drm_connector *connector;
10289
10290         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10291                             base.head) {
10292                 if (!intel_encoder->base.crtc)
10293                         continue;
10294
10295                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10296
10297                 if (prepare_pipes & (1 << intel_crtc->pipe))
10298                         intel_encoder->connectors_active = false;
10299         }
10300
10301         intel_modeset_commit_output_state(dev);
10302
10303         /* Double check state. */
10304         for_each_intel_crtc(dev, intel_crtc) {
10305                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10306                 WARN_ON(intel_crtc->new_config &&
10307                         intel_crtc->new_config != &intel_crtc->config);
10308                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10309         }
10310
10311         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10312                 if (!connector->encoder || !connector->encoder->crtc)
10313                         continue;
10314
10315                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10316
10317                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10318                         struct drm_property *dpms_property =
10319                                 dev->mode_config.dpms_property;
10320
10321                         connector->dpms = DRM_MODE_DPMS_ON;
10322                         drm_object_property_set_value(&connector->base,
10323                                                          dpms_property,
10324                                                          DRM_MODE_DPMS_ON);
10325
10326                         intel_encoder = to_intel_encoder(connector->encoder);
10327                         intel_encoder->connectors_active = true;
10328                 }
10329         }
10330
10331 }
10332
10333 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10334 {
10335         int diff;
10336
10337         if (clock1 == clock2)
10338                 return true;
10339
10340         if (!clock1 || !clock2)
10341                 return false;
10342
10343         diff = abs(clock1 - clock2);
10344
10345         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10346                 return true;
10347
10348         return false;
10349 }
10350
10351 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10352         list_for_each_entry((intel_crtc), \
10353                             &(dev)->mode_config.crtc_list, \
10354                             base.head) \
10355                 if (mask & (1 <<(intel_crtc)->pipe))
10356
10357 static bool
10358 intel_pipe_config_compare(struct drm_device *dev,
10359                           struct intel_crtc_config *current_config,
10360                           struct intel_crtc_config *pipe_config)
10361 {
10362 #define PIPE_CONF_CHECK_X(name) \
10363         if (current_config->name != pipe_config->name) { \
10364                 DRM_ERROR("mismatch in " #name " " \
10365                           "(expected 0x%08x, found 0x%08x)\n", \
10366                           current_config->name, \
10367                           pipe_config->name); \
10368                 return false; \
10369         }
10370
10371 #define PIPE_CONF_CHECK_I(name) \
10372         if (current_config->name != pipe_config->name) { \
10373                 DRM_ERROR("mismatch in " #name " " \
10374                           "(expected %i, found %i)\n", \
10375                           current_config->name, \
10376                           pipe_config->name); \
10377                 return false; \
10378         }
10379
10380 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10381         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10382                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10383                           "(expected %i, found %i)\n", \
10384                           current_config->name & (mask), \
10385                           pipe_config->name & (mask)); \
10386                 return false; \
10387         }
10388
10389 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10390         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10391                 DRM_ERROR("mismatch in " #name " " \
10392                           "(expected %i, found %i)\n", \
10393                           current_config->name, \
10394                           pipe_config->name); \
10395                 return false; \
10396         }
10397
10398 #define PIPE_CONF_QUIRK(quirk)  \
10399         ((current_config->quirks | pipe_config->quirks) & (quirk))
10400
10401         PIPE_CONF_CHECK_I(cpu_transcoder);
10402
10403         PIPE_CONF_CHECK_I(has_pch_encoder);
10404         PIPE_CONF_CHECK_I(fdi_lanes);
10405         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10406         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10407         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10408         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10409         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10410
10411         PIPE_CONF_CHECK_I(has_dp_encoder);
10412         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10413         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10414         PIPE_CONF_CHECK_I(dp_m_n.link_m);
10415         PIPE_CONF_CHECK_I(dp_m_n.link_n);
10416         PIPE_CONF_CHECK_I(dp_m_n.tu);
10417
10418         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10419         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10420         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10421         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10422         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10423         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10424
10425         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10426         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10427         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10428         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10429         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10430         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10431
10432         PIPE_CONF_CHECK_I(pixel_multiplier);
10433         PIPE_CONF_CHECK_I(has_hdmi_sink);
10434         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10435             IS_VALLEYVIEW(dev))
10436                 PIPE_CONF_CHECK_I(limited_color_range);
10437
10438         PIPE_CONF_CHECK_I(has_audio);
10439
10440         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10441                               DRM_MODE_FLAG_INTERLACE);
10442
10443         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10444                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10445                                       DRM_MODE_FLAG_PHSYNC);
10446                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10447                                       DRM_MODE_FLAG_NHSYNC);
10448                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10449                                       DRM_MODE_FLAG_PVSYNC);
10450                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10451                                       DRM_MODE_FLAG_NVSYNC);
10452         }
10453
10454         PIPE_CONF_CHECK_I(pipe_src_w);
10455         PIPE_CONF_CHECK_I(pipe_src_h);
10456
10457         /*
10458          * FIXME: BIOS likes to set up a cloned config with lvds+external
10459          * screen. Since we don't yet re-compute the pipe config when moving
10460          * just the lvds port away to another pipe the sw tracking won't match.
10461          *
10462          * Proper atomic modesets with recomputed global state will fix this.
10463          * Until then just don't check gmch state for inherited modes.
10464          */
10465         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10466                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10467                 /* pfit ratios are autocomputed by the hw on gen4+ */
10468                 if (INTEL_INFO(dev)->gen < 4)
10469                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10470                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10471         }
10472
10473         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10474         if (current_config->pch_pfit.enabled) {
10475                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10476                 PIPE_CONF_CHECK_I(pch_pfit.size);
10477         }
10478
10479         /* BDW+ don't expose a synchronous way to read the state */
10480         if (IS_HASWELL(dev))
10481                 PIPE_CONF_CHECK_I(ips_enabled);
10482
10483         PIPE_CONF_CHECK_I(double_wide);
10484
10485         PIPE_CONF_CHECK_X(ddi_pll_sel);
10486
10487         PIPE_CONF_CHECK_I(shared_dpll);
10488         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10489         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10490         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10491         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10492         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10493
10494         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10495                 PIPE_CONF_CHECK_I(pipe_bpp);
10496
10497         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10498         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10499
10500 #undef PIPE_CONF_CHECK_X
10501 #undef PIPE_CONF_CHECK_I
10502 #undef PIPE_CONF_CHECK_FLAGS
10503 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10504 #undef PIPE_CONF_QUIRK
10505
10506         return true;
10507 }
10508
10509 static void
10510 check_connector_state(struct drm_device *dev)
10511 {
10512         struct intel_connector *connector;
10513
10514         list_for_each_entry(connector, &dev->mode_config.connector_list,
10515                             base.head) {
10516                 /* This also checks the encoder/connector hw state with the
10517                  * ->get_hw_state callbacks. */
10518                 intel_connector_check_state(connector);
10519
10520                 WARN(&connector->new_encoder->base != connector->base.encoder,
10521                      "connector's staged encoder doesn't match current encoder\n");
10522         }
10523 }
10524
10525 static void
10526 check_encoder_state(struct drm_device *dev)
10527 {
10528         struct intel_encoder *encoder;
10529         struct intel_connector *connector;
10530
10531         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10532                             base.head) {
10533                 bool enabled = false;
10534                 bool active = false;
10535                 enum pipe pipe, tracked_pipe;
10536
10537                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10538                               encoder->base.base.id,
10539                               encoder->base.name);
10540
10541                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10542                      "encoder's stage crtc doesn't match current crtc\n");
10543                 WARN(encoder->connectors_active && !encoder->base.crtc,
10544                      "encoder's active_connectors set, but no crtc\n");
10545
10546                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10547                                     base.head) {
10548                         if (connector->base.encoder != &encoder->base)
10549                                 continue;
10550                         enabled = true;
10551                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10552                                 active = true;
10553                 }
10554                 /*
10555                  * for MST connectors if we unplug the connector is gone
10556                  * away but the encoder is still connected to a crtc
10557                  * until a modeset happens in response to the hotplug.
10558                  */
10559                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10560                         continue;
10561
10562                 WARN(!!encoder->base.crtc != enabled,
10563                      "encoder's enabled state mismatch "
10564                      "(expected %i, found %i)\n",
10565                      !!encoder->base.crtc, enabled);
10566                 WARN(active && !encoder->base.crtc,
10567                      "active encoder with no crtc\n");
10568
10569                 WARN(encoder->connectors_active != active,
10570                      "encoder's computed active state doesn't match tracked active state "
10571                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10572
10573                 active = encoder->get_hw_state(encoder, &pipe);
10574                 WARN(active != encoder->connectors_active,
10575                      "encoder's hw state doesn't match sw tracking "
10576                      "(expected %i, found %i)\n",
10577                      encoder->connectors_active, active);
10578
10579                 if (!encoder->base.crtc)
10580                         continue;
10581
10582                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10583                 WARN(active && pipe != tracked_pipe,
10584                      "active encoder's pipe doesn't match"
10585                      "(expected %i, found %i)\n",
10586                      tracked_pipe, pipe);
10587
10588         }
10589 }
10590
10591 static void
10592 check_crtc_state(struct drm_device *dev)
10593 {
10594         struct drm_i915_private *dev_priv = dev->dev_private;
10595         struct intel_crtc *crtc;
10596         struct intel_encoder *encoder;
10597         struct intel_crtc_config pipe_config;
10598
10599         for_each_intel_crtc(dev, crtc) {
10600                 bool enabled = false;
10601                 bool active = false;
10602
10603                 memset(&pipe_config, 0, sizeof(pipe_config));
10604
10605                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10606                               crtc->base.base.id);
10607
10608                 WARN(crtc->active && !crtc->base.enabled,
10609                      "active crtc, but not enabled in sw tracking\n");
10610
10611                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10612                                     base.head) {
10613                         if (encoder->base.crtc != &crtc->base)
10614                                 continue;
10615                         enabled = true;
10616                         if (encoder->connectors_active)
10617                                 active = true;
10618                 }
10619
10620                 WARN(active != crtc->active,
10621                      "crtc's computed active state doesn't match tracked active state "
10622                      "(expected %i, found %i)\n", active, crtc->active);
10623                 WARN(enabled != crtc->base.enabled,
10624                      "crtc's computed enabled state doesn't match tracked enabled state "
10625                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10626
10627                 active = dev_priv->display.get_pipe_config(crtc,
10628                                                            &pipe_config);
10629
10630                 /* hw state is inconsistent with the pipe A quirk */
10631                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10632                         active = crtc->active;
10633
10634                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10635                                     base.head) {
10636                         enum pipe pipe;
10637                         if (encoder->base.crtc != &crtc->base)
10638                                 continue;
10639                         if (encoder->get_hw_state(encoder, &pipe))
10640                                 encoder->get_config(encoder, &pipe_config);
10641                 }
10642
10643                 WARN(crtc->active != active,
10644                      "crtc active state doesn't match with hw state "
10645                      "(expected %i, found %i)\n", crtc->active, active);
10646
10647                 if (active &&
10648                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10649                         WARN(1, "pipe state doesn't match!\n");
10650                         intel_dump_pipe_config(crtc, &pipe_config,
10651                                                "[hw state]");
10652                         intel_dump_pipe_config(crtc, &crtc->config,
10653                                                "[sw state]");
10654                 }
10655         }
10656 }
10657
10658 static void
10659 check_shared_dpll_state(struct drm_device *dev)
10660 {
10661         struct drm_i915_private *dev_priv = dev->dev_private;
10662         struct intel_crtc *crtc;
10663         struct intel_dpll_hw_state dpll_hw_state;
10664         int i;
10665
10666         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10667                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10668                 int enabled_crtcs = 0, active_crtcs = 0;
10669                 bool active;
10670
10671                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10672
10673                 DRM_DEBUG_KMS("%s\n", pll->name);
10674
10675                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10676
10677                 WARN(pll->active > pll->refcount,
10678                      "more active pll users than references: %i vs %i\n",
10679                      pll->active, pll->refcount);
10680                 WARN(pll->active && !pll->on,
10681                      "pll in active use but not on in sw tracking\n");
10682                 WARN(pll->on && !pll->active,
10683                      "pll in on but not on in use in sw tracking\n");
10684                 WARN(pll->on != active,
10685                      "pll on state mismatch (expected %i, found %i)\n",
10686                      pll->on, active);
10687
10688                 for_each_intel_crtc(dev, crtc) {
10689                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10690                                 enabled_crtcs++;
10691                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10692                                 active_crtcs++;
10693                 }
10694                 WARN(pll->active != active_crtcs,
10695                      "pll active crtcs mismatch (expected %i, found %i)\n",
10696                      pll->active, active_crtcs);
10697                 WARN(pll->refcount != enabled_crtcs,
10698                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10699                      pll->refcount, enabled_crtcs);
10700
10701                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10702                                        sizeof(dpll_hw_state)),
10703                      "pll hw state mismatch\n");
10704         }
10705 }
10706
10707 void
10708 intel_modeset_check_state(struct drm_device *dev)
10709 {
10710         check_connector_state(dev);
10711         check_encoder_state(dev);
10712         check_crtc_state(dev);
10713         check_shared_dpll_state(dev);
10714 }
10715
10716 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10717                                      int dotclock)
10718 {
10719         /*
10720          * FDI already provided one idea for the dotclock.
10721          * Yell if the encoder disagrees.
10722          */
10723         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10724              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10725              pipe_config->adjusted_mode.crtc_clock, dotclock);
10726 }
10727
10728 static void update_scanline_offset(struct intel_crtc *crtc)
10729 {
10730         struct drm_device *dev = crtc->base.dev;
10731
10732         /*
10733          * The scanline counter increments at the leading edge of hsync.
10734          *
10735          * On most platforms it starts counting from vtotal-1 on the
10736          * first active line. That means the scanline counter value is
10737          * always one less than what we would expect. Ie. just after
10738          * start of vblank, which also occurs at start of hsync (on the
10739          * last active line), the scanline counter will read vblank_start-1.
10740          *
10741          * On gen2 the scanline counter starts counting from 1 instead
10742          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10743          * to keep the value positive), instead of adding one.
10744          *
10745          * On HSW+ the behaviour of the scanline counter depends on the output
10746          * type. For DP ports it behaves like most other platforms, but on HDMI
10747          * there's an extra 1 line difference. So we need to add two instead of
10748          * one to the value.
10749          */
10750         if (IS_GEN2(dev)) {
10751                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10752                 int vtotal;
10753
10754                 vtotal = mode->crtc_vtotal;
10755                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10756                         vtotal /= 2;
10757
10758                 crtc->scanline_offset = vtotal - 1;
10759         } else if (HAS_DDI(dev) &&
10760                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10761                 crtc->scanline_offset = 2;
10762         } else
10763                 crtc->scanline_offset = 1;
10764 }
10765
10766 static int __intel_set_mode(struct drm_crtc *crtc,
10767                             struct drm_display_mode *mode,
10768                             int x, int y, struct drm_framebuffer *fb)
10769 {
10770         struct drm_device *dev = crtc->dev;
10771         struct drm_i915_private *dev_priv = dev->dev_private;
10772         struct drm_display_mode *saved_mode;
10773         struct intel_crtc_config *pipe_config = NULL;
10774         struct intel_crtc *intel_crtc;
10775         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10776         int ret = 0;
10777
10778         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10779         if (!saved_mode)
10780                 return -ENOMEM;
10781
10782         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10783                                      &prepare_pipes, &disable_pipes);
10784
10785         *saved_mode = crtc->mode;
10786
10787         /* Hack: Because we don't (yet) support global modeset on multiple
10788          * crtcs, we don't keep track of the new mode for more than one crtc.
10789          * Hence simply check whether any bit is set in modeset_pipes in all the
10790          * pieces of code that are not yet converted to deal with mutliple crtcs
10791          * changing their mode at the same time. */
10792         if (modeset_pipes) {
10793                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10794                 if (IS_ERR(pipe_config)) {
10795                         ret = PTR_ERR(pipe_config);
10796                         pipe_config = NULL;
10797
10798                         goto out;
10799                 }
10800                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10801                                        "[modeset]");
10802                 to_intel_crtc(crtc)->new_config = pipe_config;
10803         }
10804
10805         /*
10806          * See if the config requires any additional preparation, e.g.
10807          * to adjust global state with pipes off.  We need to do this
10808          * here so we can get the modeset_pipe updated config for the new
10809          * mode set on this crtc.  For other crtcs we need to use the
10810          * adjusted_mode bits in the crtc directly.
10811          */
10812         if (IS_VALLEYVIEW(dev)) {
10813                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10814
10815                 /* may have added more to prepare_pipes than we should */
10816                 prepare_pipes &= ~disable_pipes;
10817         }
10818
10819         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10820                 intel_crtc_disable(&intel_crtc->base);
10821
10822         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10823                 if (intel_crtc->base.enabled)
10824                         dev_priv->display.crtc_disable(&intel_crtc->base);
10825         }
10826
10827         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10828          * to set it here already despite that we pass it down the callchain.
10829          */
10830         if (modeset_pipes) {
10831                 crtc->mode = *mode;
10832                 /* mode_set/enable/disable functions rely on a correct pipe
10833                  * config. */
10834                 to_intel_crtc(crtc)->config = *pipe_config;
10835                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10836
10837                 /*
10838                  * Calculate and store various constants which
10839                  * are later needed by vblank and swap-completion
10840                  * timestamping. They are derived from true hwmode.
10841                  */
10842                 drm_calc_timestamping_constants(crtc,
10843                                                 &pipe_config->adjusted_mode);
10844         }
10845
10846         /* Only after disabling all output pipelines that will be changed can we
10847          * update the the output configuration. */
10848         intel_modeset_update_state(dev, prepare_pipes);
10849
10850         if (dev_priv->display.modeset_global_resources)
10851                 dev_priv->display.modeset_global_resources(dev);
10852
10853         /* Set up the DPLL and any encoders state that needs to adjust or depend
10854          * on the DPLL.
10855          */
10856         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10857                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10858                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10859                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10860
10861                 mutex_lock(&dev->struct_mutex);
10862                 ret = intel_pin_and_fence_fb_obj(dev,
10863                                                  obj,
10864                                                  NULL);
10865                 if (ret != 0) {
10866                         DRM_ERROR("pin & fence failed\n");
10867                         mutex_unlock(&dev->struct_mutex);
10868                         goto done;
10869                 }
10870                 if (old_fb)
10871                         intel_unpin_fb_obj(old_obj);
10872                 i915_gem_track_fb(old_obj, obj,
10873                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10874                 mutex_unlock(&dev->struct_mutex);
10875
10876                 crtc->primary->fb = fb;
10877                 crtc->x = x;
10878                 crtc->y = y;
10879
10880                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10881                                                       x, y, fb);
10882                 if (ret)
10883                         goto done;
10884         }
10885
10886         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10887         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10888                 update_scanline_offset(intel_crtc);
10889
10890                 dev_priv->display.crtc_enable(&intel_crtc->base);
10891         }
10892
10893         /* FIXME: add subpixel order */
10894 done:
10895         if (ret && crtc->enabled)
10896                 crtc->mode = *saved_mode;
10897
10898 out:
10899         kfree(pipe_config);
10900         kfree(saved_mode);
10901         return ret;
10902 }
10903
10904 static int intel_set_mode(struct drm_crtc *crtc,
10905                           struct drm_display_mode *mode,
10906                           int x, int y, struct drm_framebuffer *fb)
10907 {
10908         int ret;
10909
10910         ret = __intel_set_mode(crtc, mode, x, y, fb);
10911
10912         if (ret == 0)
10913                 intel_modeset_check_state(crtc->dev);
10914
10915         return ret;
10916 }
10917
10918 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10919 {
10920         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10921 }
10922
10923 #undef for_each_intel_crtc_masked
10924
10925 static void intel_set_config_free(struct intel_set_config *config)
10926 {
10927         if (!config)
10928                 return;
10929
10930         kfree(config->save_connector_encoders);
10931         kfree(config->save_encoder_crtcs);
10932         kfree(config->save_crtc_enabled);
10933         kfree(config);
10934 }
10935
10936 static int intel_set_config_save_state(struct drm_device *dev,
10937                                        struct intel_set_config *config)
10938 {
10939         struct drm_crtc *crtc;
10940         struct drm_encoder *encoder;
10941         struct drm_connector *connector;
10942         int count;
10943
10944         config->save_crtc_enabled =
10945                 kcalloc(dev->mode_config.num_crtc,
10946                         sizeof(bool), GFP_KERNEL);
10947         if (!config->save_crtc_enabled)
10948                 return -ENOMEM;
10949
10950         config->save_encoder_crtcs =
10951                 kcalloc(dev->mode_config.num_encoder,
10952                         sizeof(struct drm_crtc *), GFP_KERNEL);
10953         if (!config->save_encoder_crtcs)
10954                 return -ENOMEM;
10955
10956         config->save_connector_encoders =
10957                 kcalloc(dev->mode_config.num_connector,
10958                         sizeof(struct drm_encoder *), GFP_KERNEL);
10959         if (!config->save_connector_encoders)
10960                 return -ENOMEM;
10961
10962         /* Copy data. Note that driver private data is not affected.
10963          * Should anything bad happen only the expected state is
10964          * restored, not the drivers personal bookkeeping.
10965          */
10966         count = 0;
10967         for_each_crtc(dev, crtc) {
10968                 config->save_crtc_enabled[count++] = crtc->enabled;
10969         }
10970
10971         count = 0;
10972         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10973                 config->save_encoder_crtcs[count++] = encoder->crtc;
10974         }
10975
10976         count = 0;
10977         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10978                 config->save_connector_encoders[count++] = connector->encoder;
10979         }
10980
10981         return 0;
10982 }
10983
10984 static void intel_set_config_restore_state(struct drm_device *dev,
10985                                            struct intel_set_config *config)
10986 {
10987         struct intel_crtc *crtc;
10988         struct intel_encoder *encoder;
10989         struct intel_connector *connector;
10990         int count;
10991
10992         count = 0;
10993         for_each_intel_crtc(dev, crtc) {
10994                 crtc->new_enabled = config->save_crtc_enabled[count++];
10995
10996                 if (crtc->new_enabled)
10997                         crtc->new_config = &crtc->config;
10998                 else
10999                         crtc->new_config = NULL;
11000         }
11001
11002         count = 0;
11003         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11004                 encoder->new_crtc =
11005                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11006         }
11007
11008         count = 0;
11009         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11010                 connector->new_encoder =
11011                         to_intel_encoder(config->save_connector_encoders[count++]);
11012         }
11013 }
11014
11015 static bool
11016 is_crtc_connector_off(struct drm_mode_set *set)
11017 {
11018         int i;
11019
11020         if (set->num_connectors == 0)
11021                 return false;
11022
11023         if (WARN_ON(set->connectors == NULL))
11024                 return false;
11025
11026         for (i = 0; i < set->num_connectors; i++)
11027                 if (set->connectors[i]->encoder &&
11028                     set->connectors[i]->encoder->crtc == set->crtc &&
11029                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11030                         return true;
11031
11032         return false;
11033 }
11034
11035 static void
11036 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11037                                       struct intel_set_config *config)
11038 {
11039
11040         /* We should be able to check here if the fb has the same properties
11041          * and then just flip_or_move it */
11042         if (is_crtc_connector_off(set)) {
11043                 config->mode_changed = true;
11044         } else if (set->crtc->primary->fb != set->fb) {
11045                 /*
11046                  * If we have no fb, we can only flip as long as the crtc is
11047                  * active, otherwise we need a full mode set.  The crtc may
11048                  * be active if we've only disabled the primary plane, or
11049                  * in fastboot situations.
11050                  */
11051                 if (set->crtc->primary->fb == NULL) {
11052                         struct intel_crtc *intel_crtc =
11053                                 to_intel_crtc(set->crtc);
11054
11055                         if (intel_crtc->active) {
11056                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11057                                 config->fb_changed = true;
11058                         } else {
11059                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11060                                 config->mode_changed = true;
11061                         }
11062                 } else if (set->fb == NULL) {
11063                         config->mode_changed = true;
11064                 } else if (set->fb->pixel_format !=
11065                            set->crtc->primary->fb->pixel_format) {
11066                         config->mode_changed = true;
11067                 } else {
11068                         config->fb_changed = true;
11069                 }
11070         }
11071
11072         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11073                 config->fb_changed = true;
11074
11075         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11076                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11077                 drm_mode_debug_printmodeline(&set->crtc->mode);
11078                 drm_mode_debug_printmodeline(set->mode);
11079                 config->mode_changed = true;
11080         }
11081
11082         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11083                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11084 }
11085
11086 static int
11087 intel_modeset_stage_output_state(struct drm_device *dev,
11088                                  struct drm_mode_set *set,
11089                                  struct intel_set_config *config)
11090 {
11091         struct intel_connector *connector;
11092         struct intel_encoder *encoder;
11093         struct intel_crtc *crtc;
11094         int ro;
11095
11096         /* The upper layers ensure that we either disable a crtc or have a list
11097          * of connectors. For paranoia, double-check this. */
11098         WARN_ON(!set->fb && (set->num_connectors != 0));
11099         WARN_ON(set->fb && (set->num_connectors == 0));
11100
11101         list_for_each_entry(connector, &dev->mode_config.connector_list,
11102                             base.head) {
11103                 /* Otherwise traverse passed in connector list and get encoders
11104                  * for them. */
11105                 for (ro = 0; ro < set->num_connectors; ro++) {
11106                         if (set->connectors[ro] == &connector->base) {
11107                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11108                                 break;
11109                         }
11110                 }
11111
11112                 /* If we disable the crtc, disable all its connectors. Also, if
11113                  * the connector is on the changing crtc but not on the new
11114                  * connector list, disable it. */
11115                 if ((!set->fb || ro == set->num_connectors) &&
11116                     connector->base.encoder &&
11117                     connector->base.encoder->crtc == set->crtc) {
11118                         connector->new_encoder = NULL;
11119
11120                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11121                                 connector->base.base.id,
11122                                 connector->base.name);
11123                 }
11124
11125
11126                 if (&connector->new_encoder->base != connector->base.encoder) {
11127                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11128                         config->mode_changed = true;
11129                 }
11130         }
11131         /* connector->new_encoder is now updated for all connectors. */
11132
11133         /* Update crtc of enabled connectors. */
11134         list_for_each_entry(connector, &dev->mode_config.connector_list,
11135                             base.head) {
11136                 struct drm_crtc *new_crtc;
11137
11138                 if (!connector->new_encoder)
11139                         continue;
11140
11141                 new_crtc = connector->new_encoder->base.crtc;
11142
11143                 for (ro = 0; ro < set->num_connectors; ro++) {
11144                         if (set->connectors[ro] == &connector->base)
11145                                 new_crtc = set->crtc;
11146                 }
11147
11148                 /* Make sure the new CRTC will work with the encoder */
11149                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11150                                          new_crtc)) {
11151                         return -EINVAL;
11152                 }
11153                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11154
11155                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11156                         connector->base.base.id,
11157                         connector->base.name,
11158                         new_crtc->base.id);
11159         }
11160
11161         /* Check for any encoders that needs to be disabled. */
11162         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11163                             base.head) {
11164                 int num_connectors = 0;
11165                 list_for_each_entry(connector,
11166                                     &dev->mode_config.connector_list,
11167                                     base.head) {
11168                         if (connector->new_encoder == encoder) {
11169                                 WARN_ON(!connector->new_encoder->new_crtc);
11170                                 num_connectors++;
11171                         }
11172                 }
11173
11174                 if (num_connectors == 0)
11175                         encoder->new_crtc = NULL;
11176                 else if (num_connectors > 1)
11177                         return -EINVAL;
11178
11179                 /* Only now check for crtc changes so we don't miss encoders
11180                  * that will be disabled. */
11181                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11182                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11183                         config->mode_changed = true;
11184                 }
11185         }
11186         /* Now we've also updated encoder->new_crtc for all encoders. */
11187         list_for_each_entry(connector, &dev->mode_config.connector_list,
11188                             base.head) {
11189                 if (connector->new_encoder)
11190                         if (connector->new_encoder != connector->encoder)
11191                                 connector->encoder = connector->new_encoder;
11192         }
11193         for_each_intel_crtc(dev, crtc) {
11194                 crtc->new_enabled = false;
11195
11196                 list_for_each_entry(encoder,
11197                                     &dev->mode_config.encoder_list,
11198                                     base.head) {
11199                         if (encoder->new_crtc == crtc) {
11200                                 crtc->new_enabled = true;
11201                                 break;
11202                         }
11203                 }
11204
11205                 if (crtc->new_enabled != crtc->base.enabled) {
11206                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11207                                       crtc->new_enabled ? "en" : "dis");
11208                         config->mode_changed = true;
11209                 }
11210
11211                 if (crtc->new_enabled)
11212                         crtc->new_config = &crtc->config;
11213                 else
11214                         crtc->new_config = NULL;
11215         }
11216
11217         return 0;
11218 }
11219
11220 static void disable_crtc_nofb(struct intel_crtc *crtc)
11221 {
11222         struct drm_device *dev = crtc->base.dev;
11223         struct intel_encoder *encoder;
11224         struct intel_connector *connector;
11225
11226         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11227                       pipe_name(crtc->pipe));
11228
11229         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11230                 if (connector->new_encoder &&
11231                     connector->new_encoder->new_crtc == crtc)
11232                         connector->new_encoder = NULL;
11233         }
11234
11235         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11236                 if (encoder->new_crtc == crtc)
11237                         encoder->new_crtc = NULL;
11238         }
11239
11240         crtc->new_enabled = false;
11241         crtc->new_config = NULL;
11242 }
11243
11244 static int intel_crtc_set_config(struct drm_mode_set *set)
11245 {
11246         struct drm_device *dev;
11247         struct drm_mode_set save_set;
11248         struct intel_set_config *config;
11249         int ret;
11250
11251         BUG_ON(!set);
11252         BUG_ON(!set->crtc);
11253         BUG_ON(!set->crtc->helper_private);
11254
11255         /* Enforce sane interface api - has been abused by the fb helper. */
11256         BUG_ON(!set->mode && set->fb);
11257         BUG_ON(set->fb && set->num_connectors == 0);
11258
11259         if (set->fb) {
11260                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11261                                 set->crtc->base.id, set->fb->base.id,
11262                                 (int)set->num_connectors, set->x, set->y);
11263         } else {
11264                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11265         }
11266
11267         dev = set->crtc->dev;
11268
11269         ret = -ENOMEM;
11270         config = kzalloc(sizeof(*config), GFP_KERNEL);
11271         if (!config)
11272                 goto out_config;
11273
11274         ret = intel_set_config_save_state(dev, config);
11275         if (ret)
11276                 goto out_config;
11277
11278         save_set.crtc = set->crtc;
11279         save_set.mode = &set->crtc->mode;
11280         save_set.x = set->crtc->x;
11281         save_set.y = set->crtc->y;
11282         save_set.fb = set->crtc->primary->fb;
11283
11284         /* Compute whether we need a full modeset, only an fb base update or no
11285          * change at all. In the future we might also check whether only the
11286          * mode changed, e.g. for LVDS where we only change the panel fitter in
11287          * such cases. */
11288         intel_set_config_compute_mode_changes(set, config);
11289
11290         ret = intel_modeset_stage_output_state(dev, set, config);
11291         if (ret)
11292                 goto fail;
11293
11294         if (config->mode_changed) {
11295                 ret = intel_set_mode(set->crtc, set->mode,
11296                                      set->x, set->y, set->fb);
11297         } else if (config->fb_changed) {
11298                 struct drm_i915_private *dev_priv = dev->dev_private;
11299                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11300
11301                 intel_crtc_wait_for_pending_flips(set->crtc);
11302
11303                 ret = intel_pipe_set_base(set->crtc,
11304                                           set->x, set->y, set->fb);
11305
11306                 /*
11307                  * We need to make sure the primary plane is re-enabled if it
11308                  * has previously been turned off.
11309                  */
11310                 if (!intel_crtc->primary_enabled && ret == 0) {
11311                         WARN_ON(!intel_crtc->active);
11312                         intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11313                                                       intel_crtc->pipe);
11314                 }
11315
11316                 /*
11317                  * In the fastboot case this may be our only check of the
11318                  * state after boot.  It would be better to only do it on
11319                  * the first update, but we don't have a nice way of doing that
11320                  * (and really, set_config isn't used much for high freq page
11321                  * flipping, so increasing its cost here shouldn't be a big
11322                  * deal).
11323                  */
11324                 if (i915.fastboot && ret == 0)
11325                         intel_modeset_check_state(set->crtc->dev);
11326         }
11327
11328         if (ret) {
11329                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11330                               set->crtc->base.id, ret);
11331 fail:
11332                 intel_set_config_restore_state(dev, config);
11333
11334                 /*
11335                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11336                  * force the pipe off to avoid oopsing in the modeset code
11337                  * due to fb==NULL. This should only happen during boot since
11338                  * we don't yet reconstruct the FB from the hardware state.
11339                  */
11340                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11341                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11342
11343                 /* Try to restore the config */
11344                 if (config->mode_changed &&
11345                     intel_set_mode(save_set.crtc, save_set.mode,
11346                                    save_set.x, save_set.y, save_set.fb))
11347                         DRM_ERROR("failed to restore config after modeset failure\n");
11348         }
11349
11350 out_config:
11351         intel_set_config_free(config);
11352         return ret;
11353 }
11354
11355 static const struct drm_crtc_funcs intel_crtc_funcs = {
11356         .gamma_set = intel_crtc_gamma_set,
11357         .set_config = intel_crtc_set_config,
11358         .destroy = intel_crtc_destroy,
11359         .page_flip = intel_crtc_page_flip,
11360 };
11361
11362 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11363                                       struct intel_shared_dpll *pll,
11364                                       struct intel_dpll_hw_state *hw_state)
11365 {
11366         uint32_t val;
11367
11368         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11369                 return false;
11370
11371         val = I915_READ(PCH_DPLL(pll->id));
11372         hw_state->dpll = val;
11373         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11374         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11375
11376         return val & DPLL_VCO_ENABLE;
11377 }
11378
11379 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11380                                   struct intel_shared_dpll *pll)
11381 {
11382         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11383         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11384 }
11385
11386 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11387                                 struct intel_shared_dpll *pll)
11388 {
11389         /* PCH refclock must be enabled first */
11390         ibx_assert_pch_refclk_enabled(dev_priv);
11391
11392         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11393
11394         /* Wait for the clocks to stabilize. */
11395         POSTING_READ(PCH_DPLL(pll->id));
11396         udelay(150);
11397
11398         /* The pixel multiplier can only be updated once the
11399          * DPLL is enabled and the clocks are stable.
11400          *
11401          * So write it again.
11402          */
11403         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11404         POSTING_READ(PCH_DPLL(pll->id));
11405         udelay(200);
11406 }
11407
11408 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11409                                  struct intel_shared_dpll *pll)
11410 {
11411         struct drm_device *dev = dev_priv->dev;
11412         struct intel_crtc *crtc;
11413
11414         /* Make sure no transcoder isn't still depending on us. */
11415         for_each_intel_crtc(dev, crtc) {
11416                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11417                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11418         }
11419
11420         I915_WRITE(PCH_DPLL(pll->id), 0);
11421         POSTING_READ(PCH_DPLL(pll->id));
11422         udelay(200);
11423 }
11424
11425 static char *ibx_pch_dpll_names[] = {
11426         "PCH DPLL A",
11427         "PCH DPLL B",
11428 };
11429
11430 static void ibx_pch_dpll_init(struct drm_device *dev)
11431 {
11432         struct drm_i915_private *dev_priv = dev->dev_private;
11433         int i;
11434
11435         dev_priv->num_shared_dpll = 2;
11436
11437         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11438                 dev_priv->shared_dplls[i].id = i;
11439                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11440                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11441                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11442                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11443                 dev_priv->shared_dplls[i].get_hw_state =
11444                         ibx_pch_dpll_get_hw_state;
11445         }
11446 }
11447
11448 static void intel_shared_dpll_init(struct drm_device *dev)
11449 {
11450         struct drm_i915_private *dev_priv = dev->dev_private;
11451
11452         if (HAS_DDI(dev))
11453                 intel_ddi_pll_init(dev);
11454         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11455                 ibx_pch_dpll_init(dev);
11456         else
11457                 dev_priv->num_shared_dpll = 0;
11458
11459         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11460 }
11461
11462 static int
11463 intel_primary_plane_disable(struct drm_plane *plane)
11464 {
11465         struct drm_device *dev = plane->dev;
11466         struct drm_i915_private *dev_priv = dev->dev_private;
11467         struct intel_plane *intel_plane = to_intel_plane(plane);
11468         struct intel_crtc *intel_crtc;
11469
11470         if (!plane->fb)
11471                 return 0;
11472
11473         BUG_ON(!plane->crtc);
11474
11475         intel_crtc = to_intel_crtc(plane->crtc);
11476
11477         /*
11478          * Even though we checked plane->fb above, it's still possible that
11479          * the primary plane has been implicitly disabled because the crtc
11480          * coordinates given weren't visible, or because we detected
11481          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11482          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11483          * In either case, we need to unpin the FB and let the fb pointer get
11484          * updated, but otherwise we don't need to touch the hardware.
11485          */
11486         if (!intel_crtc->primary_enabled)
11487                 goto disable_unpin;
11488
11489         intel_crtc_wait_for_pending_flips(plane->crtc);
11490         intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11491                                        intel_plane->pipe);
11492 disable_unpin:
11493         mutex_lock(&dev->struct_mutex);
11494         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11495                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11496         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11497         mutex_unlock(&dev->struct_mutex);
11498         plane->fb = NULL;
11499
11500         return 0;
11501 }
11502
11503 static int
11504 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11505                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11506                              unsigned int crtc_w, unsigned int crtc_h,
11507                              uint32_t src_x, uint32_t src_y,
11508                              uint32_t src_w, uint32_t src_h)
11509 {
11510         struct drm_device *dev = crtc->dev;
11511         struct drm_i915_private *dev_priv = dev->dev_private;
11512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11513         struct intel_plane *intel_plane = to_intel_plane(plane);
11514         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11515         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11516         struct drm_rect dest = {
11517                 /* integer pixels */
11518                 .x1 = crtc_x,
11519                 .y1 = crtc_y,
11520                 .x2 = crtc_x + crtc_w,
11521                 .y2 = crtc_y + crtc_h,
11522         };
11523         struct drm_rect src = {
11524                 /* 16.16 fixed point */
11525                 .x1 = src_x,
11526                 .y1 = src_y,
11527                 .x2 = src_x + src_w,
11528                 .y2 = src_y + src_h,
11529         };
11530         const struct drm_rect clip = {
11531                 /* integer pixels */
11532                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11533                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11534         };
11535         bool visible;
11536         int ret;
11537
11538         ret = drm_plane_helper_check_update(plane, crtc, fb,
11539                                             &src, &dest, &clip,
11540                                             DRM_PLANE_HELPER_NO_SCALING,
11541                                             DRM_PLANE_HELPER_NO_SCALING,
11542                                             false, true, &visible);
11543
11544         if (ret)
11545                 return ret;
11546
11547         /*
11548          * If the CRTC isn't enabled, we're just pinning the framebuffer,
11549          * updating the fb pointer, and returning without touching the
11550          * hardware.  This allows us to later do a drmModeSetCrtc with fb=-1 to
11551          * turn on the display with all planes setup as desired.
11552          */
11553         if (!crtc->enabled) {
11554                 mutex_lock(&dev->struct_mutex);
11555
11556                 /*
11557                  * If we already called setplane while the crtc was disabled,
11558                  * we may have an fb pinned; unpin it.
11559                  */
11560                 if (plane->fb)
11561                         intel_unpin_fb_obj(old_obj);
11562
11563                 i915_gem_track_fb(old_obj, obj,
11564                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11565
11566                 /* Pin and return without programming hardware */
11567                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11568                 mutex_unlock(&dev->struct_mutex);
11569
11570                 return ret;
11571         }
11572
11573         intel_crtc_wait_for_pending_flips(crtc);
11574
11575         /*
11576          * If clipping results in a non-visible primary plane, we'll disable
11577          * the primary plane.  Note that this is a bit different than what
11578          * happens if userspace explicitly disables the plane by passing fb=0
11579          * because plane->fb still gets set and pinned.
11580          */
11581         if (!visible) {
11582                 mutex_lock(&dev->struct_mutex);
11583
11584                 /*
11585                  * Try to pin the new fb first so that we can bail out if we
11586                  * fail.
11587                  */
11588                 if (plane->fb != fb) {
11589                         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11590                         if (ret) {
11591                                 mutex_unlock(&dev->struct_mutex);
11592                                 return ret;
11593                         }
11594                 }
11595
11596                 i915_gem_track_fb(old_obj, obj,
11597                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11598
11599                 if (intel_crtc->primary_enabled)
11600                         intel_disable_primary_hw_plane(dev_priv,
11601                                                        intel_plane->plane,
11602                                                        intel_plane->pipe);
11603
11604
11605                 if (plane->fb != fb)
11606                         if (plane->fb)
11607                                 intel_unpin_fb_obj(old_obj);
11608
11609                 mutex_unlock(&dev->struct_mutex);
11610
11611                 return 0;
11612         }
11613
11614         ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11615         if (ret)
11616                 return ret;
11617
11618         if (!intel_crtc->primary_enabled)
11619                 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11620                                               intel_crtc->pipe);
11621
11622         return 0;
11623 }
11624
11625 /* Common destruction function for both primary and cursor planes */
11626 static void intel_plane_destroy(struct drm_plane *plane)
11627 {
11628         struct intel_plane *intel_plane = to_intel_plane(plane);
11629         drm_plane_cleanup(plane);
11630         kfree(intel_plane);
11631 }
11632
11633 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11634         .update_plane = intel_primary_plane_setplane,
11635         .disable_plane = intel_primary_plane_disable,
11636         .destroy = intel_plane_destroy,
11637 };
11638
11639 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11640                                                     int pipe)
11641 {
11642         struct intel_plane *primary;
11643         const uint32_t *intel_primary_formats;
11644         int num_formats;
11645
11646         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11647         if (primary == NULL)
11648                 return NULL;
11649
11650         primary->can_scale = false;
11651         primary->max_downscale = 1;
11652         primary->pipe = pipe;
11653         primary->plane = pipe;
11654         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11655                 primary->plane = !pipe;
11656
11657         if (INTEL_INFO(dev)->gen <= 3) {
11658                 intel_primary_formats = intel_primary_formats_gen2;
11659                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11660         } else {
11661                 intel_primary_formats = intel_primary_formats_gen4;
11662                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11663         }
11664
11665         drm_universal_plane_init(dev, &primary->base, 0,
11666                                  &intel_primary_plane_funcs,
11667                                  intel_primary_formats, num_formats,
11668                                  DRM_PLANE_TYPE_PRIMARY);
11669         return &primary->base;
11670 }
11671
11672 static int
11673 intel_cursor_plane_disable(struct drm_plane *plane)
11674 {
11675         if (!plane->fb)
11676                 return 0;
11677
11678         BUG_ON(!plane->crtc);
11679
11680         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11681 }
11682
11683 static int
11684 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11685                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11686                           unsigned int crtc_w, unsigned int crtc_h,
11687                           uint32_t src_x, uint32_t src_y,
11688                           uint32_t src_w, uint32_t src_h)
11689 {
11690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11691         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11692         struct drm_i915_gem_object *obj = intel_fb->obj;
11693         struct drm_rect dest = {
11694                 /* integer pixels */
11695                 .x1 = crtc_x,
11696                 .y1 = crtc_y,
11697                 .x2 = crtc_x + crtc_w,
11698                 .y2 = crtc_y + crtc_h,
11699         };
11700         struct drm_rect src = {
11701                 /* 16.16 fixed point */
11702                 .x1 = src_x,
11703                 .y1 = src_y,
11704                 .x2 = src_x + src_w,
11705                 .y2 = src_y + src_h,
11706         };
11707         const struct drm_rect clip = {
11708                 /* integer pixels */
11709                 .x2 = intel_crtc->config.pipe_src_w,
11710                 .y2 = intel_crtc->config.pipe_src_h,
11711         };
11712         bool visible;
11713         int ret;
11714
11715         ret = drm_plane_helper_check_update(plane, crtc, fb,
11716                                             &src, &dest, &clip,
11717                                             DRM_PLANE_HELPER_NO_SCALING,
11718                                             DRM_PLANE_HELPER_NO_SCALING,
11719                                             true, true, &visible);
11720         if (ret)
11721                 return ret;
11722
11723         crtc->cursor_x = crtc_x;
11724         crtc->cursor_y = crtc_y;
11725         if (fb != crtc->cursor->fb) {
11726                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11727         } else {
11728                 intel_crtc_update_cursor(crtc, visible);
11729                 return 0;
11730         }
11731 }
11732 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11733         .update_plane = intel_cursor_plane_update,
11734         .disable_plane = intel_cursor_plane_disable,
11735         .destroy = intel_plane_destroy,
11736 };
11737
11738 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11739                                                    int pipe)
11740 {
11741         struct intel_plane *cursor;
11742
11743         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11744         if (cursor == NULL)
11745                 return NULL;
11746
11747         cursor->can_scale = false;
11748         cursor->max_downscale = 1;
11749         cursor->pipe = pipe;
11750         cursor->plane = pipe;
11751
11752         drm_universal_plane_init(dev, &cursor->base, 0,
11753                                  &intel_cursor_plane_funcs,
11754                                  intel_cursor_formats,
11755                                  ARRAY_SIZE(intel_cursor_formats),
11756                                  DRM_PLANE_TYPE_CURSOR);
11757         return &cursor->base;
11758 }
11759
11760 static void intel_crtc_init(struct drm_device *dev, int pipe)
11761 {
11762         struct drm_i915_private *dev_priv = dev->dev_private;
11763         struct intel_crtc *intel_crtc;
11764         struct drm_plane *primary = NULL;
11765         struct drm_plane *cursor = NULL;
11766         int i, ret;
11767
11768         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11769         if (intel_crtc == NULL)
11770                 return;
11771
11772         primary = intel_primary_plane_create(dev, pipe);
11773         if (!primary)
11774                 goto fail;
11775
11776         cursor = intel_cursor_plane_create(dev, pipe);
11777         if (!cursor)
11778                 goto fail;
11779
11780         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11781                                         cursor, &intel_crtc_funcs);
11782         if (ret)
11783                 goto fail;
11784
11785         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11786         for (i = 0; i < 256; i++) {
11787                 intel_crtc->lut_r[i] = i;
11788                 intel_crtc->lut_g[i] = i;
11789                 intel_crtc->lut_b[i] = i;
11790         }
11791
11792         /*
11793          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11794          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11795          */
11796         intel_crtc->pipe = pipe;
11797         intel_crtc->plane = pipe;
11798         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11799                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11800                 intel_crtc->plane = !pipe;
11801         }
11802
11803         intel_crtc->cursor_base = ~0;
11804         intel_crtc->cursor_cntl = ~0;
11805
11806         init_waitqueue_head(&intel_crtc->vbl_wait);
11807
11808         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11809                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11810         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11811         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11812
11813         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11814
11815         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11816         return;
11817
11818 fail:
11819         if (primary)
11820                 drm_plane_cleanup(primary);
11821         if (cursor)
11822                 drm_plane_cleanup(cursor);
11823         kfree(intel_crtc);
11824 }
11825
11826 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11827 {
11828         struct drm_encoder *encoder = connector->base.encoder;
11829         struct drm_device *dev = connector->base.dev;
11830
11831         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11832
11833         if (!encoder)
11834                 return INVALID_PIPE;
11835
11836         return to_intel_crtc(encoder->crtc)->pipe;
11837 }
11838
11839 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11840                                 struct drm_file *file)
11841 {
11842         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11843         struct drm_crtc *drmmode_crtc;
11844         struct intel_crtc *crtc;
11845
11846         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11847                 return -ENODEV;
11848
11849         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11850
11851         if (!drmmode_crtc) {
11852                 DRM_ERROR("no such CRTC id\n");
11853                 return -ENOENT;
11854         }
11855
11856         crtc = to_intel_crtc(drmmode_crtc);
11857         pipe_from_crtc_id->pipe = crtc->pipe;
11858
11859         return 0;
11860 }
11861
11862 static int intel_encoder_clones(struct intel_encoder *encoder)
11863 {
11864         struct drm_device *dev = encoder->base.dev;
11865         struct intel_encoder *source_encoder;
11866         int index_mask = 0;
11867         int entry = 0;
11868
11869         list_for_each_entry(source_encoder,
11870                             &dev->mode_config.encoder_list, base.head) {
11871                 if (encoders_cloneable(encoder, source_encoder))
11872                         index_mask |= (1 << entry);
11873
11874                 entry++;
11875         }
11876
11877         return index_mask;
11878 }
11879
11880 static bool has_edp_a(struct drm_device *dev)
11881 {
11882         struct drm_i915_private *dev_priv = dev->dev_private;
11883
11884         if (!IS_MOBILE(dev))
11885                 return false;
11886
11887         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11888                 return false;
11889
11890         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11891                 return false;
11892
11893         return true;
11894 }
11895
11896 const char *intel_output_name(int output)
11897 {
11898         static const char *names[] = {
11899                 [INTEL_OUTPUT_UNUSED] = "Unused",
11900                 [INTEL_OUTPUT_ANALOG] = "Analog",
11901                 [INTEL_OUTPUT_DVO] = "DVO",
11902                 [INTEL_OUTPUT_SDVO] = "SDVO",
11903                 [INTEL_OUTPUT_LVDS] = "LVDS",
11904                 [INTEL_OUTPUT_TVOUT] = "TV",
11905                 [INTEL_OUTPUT_HDMI] = "HDMI",
11906                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11907                 [INTEL_OUTPUT_EDP] = "eDP",
11908                 [INTEL_OUTPUT_DSI] = "DSI",
11909                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11910         };
11911
11912         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11913                 return "Invalid";
11914
11915         return names[output];
11916 }
11917
11918 static bool intel_crt_present(struct drm_device *dev)
11919 {
11920         struct drm_i915_private *dev_priv = dev->dev_private;
11921
11922         if (IS_ULT(dev))
11923                 return false;
11924
11925         if (IS_CHERRYVIEW(dev))
11926                 return false;
11927
11928         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11929                 return false;
11930
11931         return true;
11932 }
11933
11934 static void intel_setup_outputs(struct drm_device *dev)
11935 {
11936         struct drm_i915_private *dev_priv = dev->dev_private;
11937         struct intel_encoder *encoder;
11938         bool dpd_is_edp = false;
11939
11940         intel_lvds_init(dev);
11941
11942         if (intel_crt_present(dev))
11943                 intel_crt_init(dev);
11944
11945         if (HAS_DDI(dev)) {
11946                 int found;
11947
11948                 /* Haswell uses DDI functions to detect digital outputs */
11949                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11950                 /* DDI A only supports eDP */
11951                 if (found)
11952                         intel_ddi_init(dev, PORT_A);
11953
11954                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11955                  * register */
11956                 found = I915_READ(SFUSE_STRAP);
11957
11958                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11959                         intel_ddi_init(dev, PORT_B);
11960                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11961                         intel_ddi_init(dev, PORT_C);
11962                 if (found & SFUSE_STRAP_DDID_DETECTED)
11963                         intel_ddi_init(dev, PORT_D);
11964         } else if (HAS_PCH_SPLIT(dev)) {
11965                 int found;
11966                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11967
11968                 if (has_edp_a(dev))
11969                         intel_dp_init(dev, DP_A, PORT_A);
11970
11971                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11972                         /* PCH SDVOB multiplex with HDMIB */
11973                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11974                         if (!found)
11975                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11976                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11977                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11978                 }
11979
11980                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11981                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11982
11983                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11984                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11985
11986                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11987                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11988
11989                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11990                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11991         } else if (IS_VALLEYVIEW(dev)) {
11992                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11993                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11994                                         PORT_B);
11995                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11996                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11997                 }
11998
11999                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12000                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12001                                         PORT_C);
12002                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12003                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12004                 }
12005
12006                 if (IS_CHERRYVIEW(dev)) {
12007                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12008                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12009                                                 PORT_D);
12010                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12011                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12012                         }
12013                 }
12014
12015                 intel_dsi_init(dev);
12016         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12017                 bool found = false;
12018
12019                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12020                         DRM_DEBUG_KMS("probing SDVOB\n");
12021                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12022                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12023                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12024                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12025                         }
12026
12027                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12028                                 intel_dp_init(dev, DP_B, PORT_B);
12029                 }
12030
12031                 /* Before G4X SDVOC doesn't have its own detect register */
12032
12033                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12034                         DRM_DEBUG_KMS("probing SDVOC\n");
12035                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12036                 }
12037
12038                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12039
12040                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12041                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12042                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12043                         }
12044                         if (SUPPORTS_INTEGRATED_DP(dev))
12045                                 intel_dp_init(dev, DP_C, PORT_C);
12046                 }
12047
12048                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12049                     (I915_READ(DP_D) & DP_DETECTED))
12050                         intel_dp_init(dev, DP_D, PORT_D);
12051         } else if (IS_GEN2(dev))
12052                 intel_dvo_init(dev);
12053
12054         if (SUPPORTS_TV(dev))
12055                 intel_tv_init(dev);
12056
12057         intel_edp_psr_init(dev);
12058
12059         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12060                 encoder->base.possible_crtcs = encoder->crtc_mask;
12061                 encoder->base.possible_clones =
12062                         intel_encoder_clones(encoder);
12063         }
12064
12065         intel_init_pch_refclk(dev);
12066
12067         drm_helper_move_panel_connectors_to_head(dev);
12068 }
12069
12070 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12071 {
12072         struct drm_device *dev = fb->dev;
12073         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12074
12075         drm_framebuffer_cleanup(fb);
12076         mutex_lock(&dev->struct_mutex);
12077         WARN_ON(!intel_fb->obj->framebuffer_references--);
12078         drm_gem_object_unreference(&intel_fb->obj->base);
12079         mutex_unlock(&dev->struct_mutex);
12080         kfree(intel_fb);
12081 }
12082
12083 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12084                                                 struct drm_file *file,
12085                                                 unsigned int *handle)
12086 {
12087         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12088         struct drm_i915_gem_object *obj = intel_fb->obj;
12089
12090         return drm_gem_handle_create(file, &obj->base, handle);
12091 }
12092
12093 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12094         .destroy = intel_user_framebuffer_destroy,
12095         .create_handle = intel_user_framebuffer_create_handle,
12096 };
12097
12098 static int intel_framebuffer_init(struct drm_device *dev,
12099                                   struct intel_framebuffer *intel_fb,
12100                                   struct drm_mode_fb_cmd2 *mode_cmd,
12101                                   struct drm_i915_gem_object *obj)
12102 {
12103         int aligned_height;
12104         int pitch_limit;
12105         int ret;
12106
12107         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12108
12109         if (obj->tiling_mode == I915_TILING_Y) {
12110                 DRM_DEBUG("hardware does not support tiling Y\n");
12111                 return -EINVAL;
12112         }
12113
12114         if (mode_cmd->pitches[0] & 63) {
12115                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12116                           mode_cmd->pitches[0]);
12117                 return -EINVAL;
12118         }
12119
12120         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12121                 pitch_limit = 32*1024;
12122         } else if (INTEL_INFO(dev)->gen >= 4) {
12123                 if (obj->tiling_mode)
12124                         pitch_limit = 16*1024;
12125                 else
12126                         pitch_limit = 32*1024;
12127         } else if (INTEL_INFO(dev)->gen >= 3) {
12128                 if (obj->tiling_mode)
12129                         pitch_limit = 8*1024;
12130                 else
12131                         pitch_limit = 16*1024;
12132         } else
12133                 /* XXX DSPC is limited to 4k tiled */
12134                 pitch_limit = 8*1024;
12135
12136         if (mode_cmd->pitches[0] > pitch_limit) {
12137                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12138                           obj->tiling_mode ? "tiled" : "linear",
12139                           mode_cmd->pitches[0], pitch_limit);
12140                 return -EINVAL;
12141         }
12142
12143         if (obj->tiling_mode != I915_TILING_NONE &&
12144             mode_cmd->pitches[0] != obj->stride) {
12145                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12146                           mode_cmd->pitches[0], obj->stride);
12147                 return -EINVAL;
12148         }
12149
12150         /* Reject formats not supported by any plane early. */
12151         switch (mode_cmd->pixel_format) {
12152         case DRM_FORMAT_C8:
12153         case DRM_FORMAT_RGB565:
12154         case DRM_FORMAT_XRGB8888:
12155         case DRM_FORMAT_ARGB8888:
12156                 break;
12157         case DRM_FORMAT_XRGB1555:
12158         case DRM_FORMAT_ARGB1555:
12159                 if (INTEL_INFO(dev)->gen > 3) {
12160                         DRM_DEBUG("unsupported pixel format: %s\n",
12161                                   drm_get_format_name(mode_cmd->pixel_format));
12162                         return -EINVAL;
12163                 }
12164                 break;
12165         case DRM_FORMAT_XBGR8888:
12166         case DRM_FORMAT_ABGR8888:
12167         case DRM_FORMAT_XRGB2101010:
12168         case DRM_FORMAT_ARGB2101010:
12169         case DRM_FORMAT_XBGR2101010:
12170         case DRM_FORMAT_ABGR2101010:
12171                 if (INTEL_INFO(dev)->gen < 4) {
12172                         DRM_DEBUG("unsupported pixel format: %s\n",
12173                                   drm_get_format_name(mode_cmd->pixel_format));
12174                         return -EINVAL;
12175                 }
12176                 break;
12177         case DRM_FORMAT_YUYV:
12178         case DRM_FORMAT_UYVY:
12179         case DRM_FORMAT_YVYU:
12180         case DRM_FORMAT_VYUY:
12181                 if (INTEL_INFO(dev)->gen < 5) {
12182                         DRM_DEBUG("unsupported pixel format: %s\n",
12183                                   drm_get_format_name(mode_cmd->pixel_format));
12184                         return -EINVAL;
12185                 }
12186                 break;
12187         default:
12188                 DRM_DEBUG("unsupported pixel format: %s\n",
12189                           drm_get_format_name(mode_cmd->pixel_format));
12190                 return -EINVAL;
12191         }
12192
12193         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12194         if (mode_cmd->offsets[0] != 0)
12195                 return -EINVAL;
12196
12197         aligned_height = intel_align_height(dev, mode_cmd->height,
12198                                             obj->tiling_mode);
12199         /* FIXME drm helper for size checks (especially planar formats)? */
12200         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12201                 return -EINVAL;
12202
12203         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12204         intel_fb->obj = obj;
12205         intel_fb->obj->framebuffer_references++;
12206
12207         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12208         if (ret) {
12209                 DRM_ERROR("framebuffer init failed %d\n", ret);
12210                 return ret;
12211         }
12212
12213         return 0;
12214 }
12215
12216 static struct drm_framebuffer *
12217 intel_user_framebuffer_create(struct drm_device *dev,
12218                               struct drm_file *filp,
12219                               struct drm_mode_fb_cmd2 *mode_cmd)
12220 {
12221         struct drm_i915_gem_object *obj;
12222
12223         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12224                                                 mode_cmd->handles[0]));
12225         if (&obj->base == NULL)
12226                 return ERR_PTR(-ENOENT);
12227
12228         return intel_framebuffer_create(dev, mode_cmd, obj);
12229 }
12230
12231 #ifndef CONFIG_DRM_I915_FBDEV
12232 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12233 {
12234 }
12235 #endif
12236
12237 static const struct drm_mode_config_funcs intel_mode_funcs = {
12238         .fb_create = intel_user_framebuffer_create,
12239         .output_poll_changed = intel_fbdev_output_poll_changed,
12240 };
12241
12242 /* Set up chip specific display functions */
12243 static void intel_init_display(struct drm_device *dev)
12244 {
12245         struct drm_i915_private *dev_priv = dev->dev_private;
12246
12247         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12248                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12249         else if (IS_CHERRYVIEW(dev))
12250                 dev_priv->display.find_dpll = chv_find_best_dpll;
12251         else if (IS_VALLEYVIEW(dev))
12252                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12253         else if (IS_PINEVIEW(dev))
12254                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12255         else
12256                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12257
12258         if (HAS_DDI(dev)) {
12259                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12260                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12261                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12262                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12263                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12264                 dev_priv->display.off = ironlake_crtc_off;
12265                 dev_priv->display.update_primary_plane =
12266                         ironlake_update_primary_plane;
12267         } else if (HAS_PCH_SPLIT(dev)) {
12268                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12269                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12270                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12271                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12272                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12273                 dev_priv->display.off = ironlake_crtc_off;
12274                 dev_priv->display.update_primary_plane =
12275                         ironlake_update_primary_plane;
12276         } else if (IS_VALLEYVIEW(dev)) {
12277                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12278                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12279                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12280                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12281                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12282                 dev_priv->display.off = i9xx_crtc_off;
12283                 dev_priv->display.update_primary_plane =
12284                         i9xx_update_primary_plane;
12285         } else {
12286                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12287                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12288                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12289                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12290                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12291                 dev_priv->display.off = i9xx_crtc_off;
12292                 dev_priv->display.update_primary_plane =
12293                         i9xx_update_primary_plane;
12294         }
12295
12296         /* Returns the core display clock speed */
12297         if (IS_VALLEYVIEW(dev))
12298                 dev_priv->display.get_display_clock_speed =
12299                         valleyview_get_display_clock_speed;
12300         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12301                 dev_priv->display.get_display_clock_speed =
12302                         i945_get_display_clock_speed;
12303         else if (IS_I915G(dev))
12304                 dev_priv->display.get_display_clock_speed =
12305                         i915_get_display_clock_speed;
12306         else if (IS_I945GM(dev) || IS_845G(dev))
12307                 dev_priv->display.get_display_clock_speed =
12308                         i9xx_misc_get_display_clock_speed;
12309         else if (IS_PINEVIEW(dev))
12310                 dev_priv->display.get_display_clock_speed =
12311                         pnv_get_display_clock_speed;
12312         else if (IS_I915GM(dev))
12313                 dev_priv->display.get_display_clock_speed =
12314                         i915gm_get_display_clock_speed;
12315         else if (IS_I865G(dev))
12316                 dev_priv->display.get_display_clock_speed =
12317                         i865_get_display_clock_speed;
12318         else if (IS_I85X(dev))
12319                 dev_priv->display.get_display_clock_speed =
12320                         i855_get_display_clock_speed;
12321         else /* 852, 830 */
12322                 dev_priv->display.get_display_clock_speed =
12323                         i830_get_display_clock_speed;
12324
12325         if (HAS_PCH_SPLIT(dev)) {
12326                 if (IS_GEN5(dev)) {
12327                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12328                         dev_priv->display.write_eld = ironlake_write_eld;
12329                 } else if (IS_GEN6(dev)) {
12330                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12331                         dev_priv->display.write_eld = ironlake_write_eld;
12332                         dev_priv->display.modeset_global_resources =
12333                                 snb_modeset_global_resources;
12334                 } else if (IS_IVYBRIDGE(dev)) {
12335                         /* FIXME: detect B0+ stepping and use auto training */
12336                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12337                         dev_priv->display.write_eld = ironlake_write_eld;
12338                         dev_priv->display.modeset_global_resources =
12339                                 ivb_modeset_global_resources;
12340                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12341                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12342                         dev_priv->display.write_eld = haswell_write_eld;
12343                         dev_priv->display.modeset_global_resources =
12344                                 haswell_modeset_global_resources;
12345                 }
12346         } else if (IS_G4X(dev)) {
12347                 dev_priv->display.write_eld = g4x_write_eld;
12348         } else if (IS_VALLEYVIEW(dev)) {
12349                 dev_priv->display.modeset_global_resources =
12350                         valleyview_modeset_global_resources;
12351                 dev_priv->display.write_eld = ironlake_write_eld;
12352         }
12353
12354         /* Default just returns -ENODEV to indicate unsupported */
12355         dev_priv->display.queue_flip = intel_default_queue_flip;
12356
12357         switch (INTEL_INFO(dev)->gen) {
12358         case 2:
12359                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12360                 break;
12361
12362         case 3:
12363                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12364                 break;
12365
12366         case 4:
12367         case 5:
12368                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12369                 break;
12370
12371         case 6:
12372                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12373                 break;
12374         case 7:
12375         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12376                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12377                 break;
12378         }
12379
12380         intel_panel_init_backlight_funcs(dev);
12381 }
12382
12383 /*
12384  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12385  * resume, or other times.  This quirk makes sure that's the case for
12386  * affected systems.
12387  */
12388 static void quirk_pipea_force(struct drm_device *dev)
12389 {
12390         struct drm_i915_private *dev_priv = dev->dev_private;
12391
12392         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12393         DRM_INFO("applying pipe a force quirk\n");
12394 }
12395
12396 /*
12397  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12398  */
12399 static void quirk_ssc_force_disable(struct drm_device *dev)
12400 {
12401         struct drm_i915_private *dev_priv = dev->dev_private;
12402         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12403         DRM_INFO("applying lvds SSC disable quirk\n");
12404 }
12405
12406 /*
12407  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12408  * brightness value
12409  */
12410 static void quirk_invert_brightness(struct drm_device *dev)
12411 {
12412         struct drm_i915_private *dev_priv = dev->dev_private;
12413         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12414         DRM_INFO("applying inverted panel brightness quirk\n");
12415 }
12416
12417 /* Some VBT's incorrectly indicate no backlight is present */
12418 static void quirk_backlight_present(struct drm_device *dev)
12419 {
12420         struct drm_i915_private *dev_priv = dev->dev_private;
12421         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12422         DRM_INFO("applying backlight present quirk\n");
12423 }
12424
12425 struct intel_quirk {
12426         int device;
12427         int subsystem_vendor;
12428         int subsystem_device;
12429         void (*hook)(struct drm_device *dev);
12430 };
12431
12432 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12433 struct intel_dmi_quirk {
12434         void (*hook)(struct drm_device *dev);
12435         const struct dmi_system_id (*dmi_id_list)[];
12436 };
12437
12438 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12439 {
12440         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12441         return 1;
12442 }
12443
12444 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12445         {
12446                 .dmi_id_list = &(const struct dmi_system_id[]) {
12447                         {
12448                                 .callback = intel_dmi_reverse_brightness,
12449                                 .ident = "NCR Corporation",
12450                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12451                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12452                                 },
12453                         },
12454                         { }  /* terminating entry */
12455                 },
12456                 .hook = quirk_invert_brightness,
12457         },
12458 };
12459
12460 static struct intel_quirk intel_quirks[] = {
12461         /* HP Mini needs pipe A force quirk (LP: #322104) */
12462         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12463
12464         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12465         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12466
12467         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12468         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12469
12470         /* Lenovo U160 cannot use SSC on LVDS */
12471         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12472
12473         /* Sony Vaio Y cannot use SSC on LVDS */
12474         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12475
12476         /* Acer Aspire 5734Z must invert backlight brightness */
12477         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12478
12479         /* Acer/eMachines G725 */
12480         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12481
12482         /* Acer/eMachines e725 */
12483         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12484
12485         /* Acer/Packard Bell NCL20 */
12486         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12487
12488         /* Acer Aspire 4736Z */
12489         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12490
12491         /* Acer Aspire 5336 */
12492         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12493
12494         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12495         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12496
12497         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12498         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12499
12500         /* HP Chromebook 14 (Celeron 2955U) */
12501         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12502 };
12503
12504 static void intel_init_quirks(struct drm_device *dev)
12505 {
12506         struct pci_dev *d = dev->pdev;
12507         int i;
12508
12509         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12510                 struct intel_quirk *q = &intel_quirks[i];
12511
12512                 if (d->device == q->device &&
12513                     (d->subsystem_vendor == q->subsystem_vendor ||
12514                      q->subsystem_vendor == PCI_ANY_ID) &&
12515                     (d->subsystem_device == q->subsystem_device ||
12516                      q->subsystem_device == PCI_ANY_ID))
12517                         q->hook(dev);
12518         }
12519         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12520                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12521                         intel_dmi_quirks[i].hook(dev);
12522         }
12523 }
12524
12525 /* Disable the VGA plane that we never use */
12526 static void i915_disable_vga(struct drm_device *dev)
12527 {
12528         struct drm_i915_private *dev_priv = dev->dev_private;
12529         u8 sr1;
12530         u32 vga_reg = i915_vgacntrl_reg(dev);
12531
12532         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12533         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12534         outb(SR01, VGA_SR_INDEX);
12535         sr1 = inb(VGA_SR_DATA);
12536         outb(sr1 | 1<<5, VGA_SR_DATA);
12537         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12538         udelay(300);
12539
12540         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12541         POSTING_READ(vga_reg);
12542 }
12543
12544 void intel_modeset_init_hw(struct drm_device *dev)
12545 {
12546         intel_prepare_ddi(dev);
12547
12548         if (IS_VALLEYVIEW(dev))
12549                 vlv_update_cdclk(dev);
12550
12551         intel_init_clock_gating(dev);
12552
12553         intel_reset_dpio(dev);
12554
12555         intel_enable_gt_powersave(dev);
12556 }
12557
12558 void intel_modeset_suspend_hw(struct drm_device *dev)
12559 {
12560         intel_suspend_hw(dev);
12561 }
12562
12563 void intel_modeset_init(struct drm_device *dev)
12564 {
12565         struct drm_i915_private *dev_priv = dev->dev_private;
12566         int sprite, ret;
12567         enum pipe pipe;
12568         struct intel_crtc *crtc;
12569
12570         drm_mode_config_init(dev);
12571
12572         dev->mode_config.min_width = 0;
12573         dev->mode_config.min_height = 0;
12574
12575         dev->mode_config.preferred_depth = 24;
12576         dev->mode_config.prefer_shadow = 1;
12577
12578         dev->mode_config.funcs = &intel_mode_funcs;
12579
12580         intel_init_quirks(dev);
12581
12582         intel_init_pm(dev);
12583
12584         if (INTEL_INFO(dev)->num_pipes == 0)
12585                 return;
12586
12587         intel_init_display(dev);
12588
12589         if (IS_GEN2(dev)) {
12590                 dev->mode_config.max_width = 2048;
12591                 dev->mode_config.max_height = 2048;
12592         } else if (IS_GEN3(dev)) {
12593                 dev->mode_config.max_width = 4096;
12594                 dev->mode_config.max_height = 4096;
12595         } else {
12596                 dev->mode_config.max_width = 8192;
12597                 dev->mode_config.max_height = 8192;
12598         }
12599
12600         if (IS_GEN2(dev)) {
12601                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12602                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12603         } else {
12604                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12605                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12606         }
12607
12608         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12609
12610         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12611                       INTEL_INFO(dev)->num_pipes,
12612                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12613
12614         for_each_pipe(pipe) {
12615                 intel_crtc_init(dev, pipe);
12616                 for_each_sprite(pipe, sprite) {
12617                         ret = intel_plane_init(dev, pipe, sprite);
12618                         if (ret)
12619                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12620                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12621                 }
12622         }
12623
12624         intel_init_dpio(dev);
12625         intel_reset_dpio(dev);
12626
12627         intel_shared_dpll_init(dev);
12628
12629         /* Just disable it once at startup */
12630         i915_disable_vga(dev);
12631         intel_setup_outputs(dev);
12632
12633         /* Just in case the BIOS is doing something questionable. */
12634         intel_disable_fbc(dev);
12635
12636         drm_modeset_lock_all(dev);
12637         intel_modeset_setup_hw_state(dev, false);
12638         drm_modeset_unlock_all(dev);
12639
12640         for_each_intel_crtc(dev, crtc) {
12641                 if (!crtc->active)
12642                         continue;
12643
12644                 /*
12645                  * Note that reserving the BIOS fb up front prevents us
12646                  * from stuffing other stolen allocations like the ring
12647                  * on top.  This prevents some ugliness at boot time, and
12648                  * can even allow for smooth boot transitions if the BIOS
12649                  * fb is large enough for the active pipe configuration.
12650                  */
12651                 if (dev_priv->display.get_plane_config) {
12652                         dev_priv->display.get_plane_config(crtc,
12653                                                            &crtc->plane_config);
12654                         /*
12655                          * If the fb is shared between multiple heads, we'll
12656                          * just get the first one.
12657                          */
12658                         intel_find_plane_obj(crtc, &crtc->plane_config);
12659                 }
12660         }
12661 }
12662
12663 static void intel_enable_pipe_a(struct drm_device *dev)
12664 {
12665         struct intel_connector *connector;
12666         struct drm_connector *crt = NULL;
12667         struct intel_load_detect_pipe load_detect_temp;
12668         struct drm_modeset_acquire_ctx ctx;
12669
12670         /* We can't just switch on the pipe A, we need to set things up with a
12671          * proper mode and output configuration. As a gross hack, enable pipe A
12672          * by enabling the load detect pipe once. */
12673         list_for_each_entry(connector,
12674                             &dev->mode_config.connector_list,
12675                             base.head) {
12676                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12677                         crt = &connector->base;
12678                         break;
12679                 }
12680         }
12681
12682         if (!crt)
12683                 return;
12684
12685         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12686                 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12687
12688
12689 }
12690
12691 static bool
12692 intel_check_plane_mapping(struct intel_crtc *crtc)
12693 {
12694         struct drm_device *dev = crtc->base.dev;
12695         struct drm_i915_private *dev_priv = dev->dev_private;
12696         u32 reg, val;
12697
12698         if (INTEL_INFO(dev)->num_pipes == 1)
12699                 return true;
12700
12701         reg = DSPCNTR(!crtc->plane);
12702         val = I915_READ(reg);
12703
12704         if ((val & DISPLAY_PLANE_ENABLE) &&
12705             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12706                 return false;
12707
12708         return true;
12709 }
12710
12711 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12712 {
12713         struct drm_device *dev = crtc->base.dev;
12714         struct drm_i915_private *dev_priv = dev->dev_private;
12715         u32 reg;
12716
12717         /* Clear any frame start delays used for debugging left by the BIOS */
12718         reg = PIPECONF(crtc->config.cpu_transcoder);
12719         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12720
12721         /* restore vblank interrupts to correct state */
12722         if (crtc->active) {
12723                 update_scanline_offset(crtc);
12724                 drm_vblank_on(dev, crtc->pipe);
12725         } else
12726                 drm_vblank_off(dev, crtc->pipe);
12727
12728         /* We need to sanitize the plane -> pipe mapping first because this will
12729          * disable the crtc (and hence change the state) if it is wrong. Note
12730          * that gen4+ has a fixed plane -> pipe mapping.  */
12731         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12732                 struct intel_connector *connector;
12733                 bool plane;
12734
12735                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12736                               crtc->base.base.id);
12737
12738                 /* Pipe has the wrong plane attached and the plane is active.
12739                  * Temporarily change the plane mapping and disable everything
12740                  * ...  */
12741                 plane = crtc->plane;
12742                 crtc->plane = !plane;
12743                 crtc->primary_enabled = true;
12744                 dev_priv->display.crtc_disable(&crtc->base);
12745                 crtc->plane = plane;
12746
12747                 /* ... and break all links. */
12748                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12749                                     base.head) {
12750                         if (connector->encoder->base.crtc != &crtc->base)
12751                                 continue;
12752
12753                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12754                         connector->base.encoder = NULL;
12755                 }
12756                 /* multiple connectors may have the same encoder:
12757                  *  handle them and break crtc link separately */
12758                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12759                                     base.head)
12760                         if (connector->encoder->base.crtc == &crtc->base) {
12761                                 connector->encoder->base.crtc = NULL;
12762                                 connector->encoder->connectors_active = false;
12763                         }
12764
12765                 WARN_ON(crtc->active);
12766                 crtc->base.enabled = false;
12767         }
12768
12769         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12770             crtc->pipe == PIPE_A && !crtc->active) {
12771                 /* BIOS forgot to enable pipe A, this mostly happens after
12772                  * resume. Force-enable the pipe to fix this, the update_dpms
12773                  * call below we restore the pipe to the right state, but leave
12774                  * the required bits on. */
12775                 intel_enable_pipe_a(dev);
12776         }
12777
12778         /* Adjust the state of the output pipe according to whether we
12779          * have active connectors/encoders. */
12780         intel_crtc_update_dpms(&crtc->base);
12781
12782         if (crtc->active != crtc->base.enabled) {
12783                 struct intel_encoder *encoder;
12784
12785                 /* This can happen either due to bugs in the get_hw_state
12786                  * functions or because the pipe is force-enabled due to the
12787                  * pipe A quirk. */
12788                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12789                               crtc->base.base.id,
12790                               crtc->base.enabled ? "enabled" : "disabled",
12791                               crtc->active ? "enabled" : "disabled");
12792
12793                 crtc->base.enabled = crtc->active;
12794
12795                 /* Because we only establish the connector -> encoder ->
12796                  * crtc links if something is active, this means the
12797                  * crtc is now deactivated. Break the links. connector
12798                  * -> encoder links are only establish when things are
12799                  *  actually up, hence no need to break them. */
12800                 WARN_ON(crtc->active);
12801
12802                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12803                         WARN_ON(encoder->connectors_active);
12804                         encoder->base.crtc = NULL;
12805                 }
12806         }
12807
12808         if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12809                 /*
12810                  * We start out with underrun reporting disabled to avoid races.
12811                  * For correct bookkeeping mark this on active crtcs.
12812                  *
12813                  * Also on gmch platforms we dont have any hardware bits to
12814                  * disable the underrun reporting. Which means we need to start
12815                  * out with underrun reporting disabled also on inactive pipes,
12816                  * since otherwise we'll complain about the garbage we read when
12817                  * e.g. coming up after runtime pm.
12818                  *
12819                  * No protection against concurrent access is required - at
12820                  * worst a fifo underrun happens which also sets this to false.
12821                  */
12822                 crtc->cpu_fifo_underrun_disabled = true;
12823                 crtc->pch_fifo_underrun_disabled = true;
12824         }
12825 }
12826
12827 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12828 {
12829         struct intel_connector *connector;
12830         struct drm_device *dev = encoder->base.dev;
12831
12832         /* We need to check both for a crtc link (meaning that the
12833          * encoder is active and trying to read from a pipe) and the
12834          * pipe itself being active. */
12835         bool has_active_crtc = encoder->base.crtc &&
12836                 to_intel_crtc(encoder->base.crtc)->active;
12837
12838         if (encoder->connectors_active && !has_active_crtc) {
12839                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12840                               encoder->base.base.id,
12841                               encoder->base.name);
12842
12843                 /* Connector is active, but has no active pipe. This is
12844                  * fallout from our resume register restoring. Disable
12845                  * the encoder manually again. */
12846                 if (encoder->base.crtc) {
12847                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12848                                       encoder->base.base.id,
12849                                       encoder->base.name);
12850                         encoder->disable(encoder);
12851                         if (encoder->post_disable)
12852                                 encoder->post_disable(encoder);
12853                 }
12854                 encoder->base.crtc = NULL;
12855                 encoder->connectors_active = false;
12856
12857                 /* Inconsistent output/port/pipe state happens presumably due to
12858                  * a bug in one of the get_hw_state functions. Or someplace else
12859                  * in our code, like the register restore mess on resume. Clamp
12860                  * things to off as a safer default. */
12861                 list_for_each_entry(connector,
12862                                     &dev->mode_config.connector_list,
12863                                     base.head) {
12864                         if (connector->encoder != encoder)
12865                                 continue;
12866                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12867                         connector->base.encoder = NULL;
12868                 }
12869         }
12870         /* Enabled encoders without active connectors will be fixed in
12871          * the crtc fixup. */
12872 }
12873
12874 void i915_redisable_vga_power_on(struct drm_device *dev)
12875 {
12876         struct drm_i915_private *dev_priv = dev->dev_private;
12877         u32 vga_reg = i915_vgacntrl_reg(dev);
12878
12879         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12880                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12881                 i915_disable_vga(dev);
12882         }
12883 }
12884
12885 void i915_redisable_vga(struct drm_device *dev)
12886 {
12887         struct drm_i915_private *dev_priv = dev->dev_private;
12888
12889         /* This function can be called both from intel_modeset_setup_hw_state or
12890          * at a very early point in our resume sequence, where the power well
12891          * structures are not yet restored. Since this function is at a very
12892          * paranoid "someone might have enabled VGA while we were not looking"
12893          * level, just check if the power well is enabled instead of trying to
12894          * follow the "don't touch the power well if we don't need it" policy
12895          * the rest of the driver uses. */
12896         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12897                 return;
12898
12899         i915_redisable_vga_power_on(dev);
12900 }
12901
12902 static bool primary_get_hw_state(struct intel_crtc *crtc)
12903 {
12904         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12905
12906         if (!crtc->active)
12907                 return false;
12908
12909         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12910 }
12911
12912 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12913 {
12914         struct drm_i915_private *dev_priv = dev->dev_private;
12915         enum pipe pipe;
12916         struct intel_crtc *crtc;
12917         struct intel_encoder *encoder;
12918         struct intel_connector *connector;
12919         int i;
12920
12921         for_each_intel_crtc(dev, crtc) {
12922                 memset(&crtc->config, 0, sizeof(crtc->config));
12923
12924                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12925
12926                 crtc->active = dev_priv->display.get_pipe_config(crtc,
12927                                                                  &crtc->config);
12928
12929                 crtc->base.enabled = crtc->active;
12930                 crtc->primary_enabled = primary_get_hw_state(crtc);
12931
12932                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12933                               crtc->base.base.id,
12934                               crtc->active ? "enabled" : "disabled");
12935         }
12936
12937         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12938                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12939
12940                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12941                 pll->active = 0;
12942                 for_each_intel_crtc(dev, crtc) {
12943                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12944                                 pll->active++;
12945                 }
12946                 pll->refcount = pll->active;
12947
12948                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12949                               pll->name, pll->refcount, pll->on);
12950
12951                 if (pll->refcount)
12952                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12953         }
12954
12955         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12956                             base.head) {
12957                 pipe = 0;
12958
12959                 if (encoder->get_hw_state(encoder, &pipe)) {
12960                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12961                         encoder->base.crtc = &crtc->base;
12962                         encoder->get_config(encoder, &crtc->config);
12963                 } else {
12964                         encoder->base.crtc = NULL;
12965                 }
12966
12967                 encoder->connectors_active = false;
12968                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12969                               encoder->base.base.id,
12970                               encoder->base.name,
12971                               encoder->base.crtc ? "enabled" : "disabled",
12972                               pipe_name(pipe));
12973         }
12974
12975         list_for_each_entry(connector, &dev->mode_config.connector_list,
12976                             base.head) {
12977                 if (connector->get_hw_state(connector)) {
12978                         connector->base.dpms = DRM_MODE_DPMS_ON;
12979                         connector->encoder->connectors_active = true;
12980                         connector->base.encoder = &connector->encoder->base;
12981                 } else {
12982                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12983                         connector->base.encoder = NULL;
12984                 }
12985                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12986                               connector->base.base.id,
12987                               connector->base.name,
12988                               connector->base.encoder ? "enabled" : "disabled");
12989         }
12990 }
12991
12992 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12993  * and i915 state tracking structures. */
12994 void intel_modeset_setup_hw_state(struct drm_device *dev,
12995                                   bool force_restore)
12996 {
12997         struct drm_i915_private *dev_priv = dev->dev_private;
12998         enum pipe pipe;
12999         struct intel_crtc *crtc;
13000         struct intel_encoder *encoder;
13001         int i;
13002
13003         intel_modeset_readout_hw_state(dev);
13004
13005         /*
13006          * Now that we have the config, copy it to each CRTC struct
13007          * Note that this could go away if we move to using crtc_config
13008          * checking everywhere.
13009          */
13010         for_each_intel_crtc(dev, crtc) {
13011                 if (crtc->active && i915.fastboot) {
13012                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13013                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13014                                       crtc->base.base.id);
13015                         drm_mode_debug_printmodeline(&crtc->base.mode);
13016                 }
13017         }
13018
13019         /* HW state is read out, now we need to sanitize this mess. */
13020         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
13021                             base.head) {
13022                 intel_sanitize_encoder(encoder);
13023         }
13024
13025         for_each_pipe(pipe) {
13026                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13027                 intel_sanitize_crtc(crtc);
13028                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13029         }
13030
13031         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13032                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13033
13034                 if (!pll->on || pll->active)
13035                         continue;
13036
13037                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13038
13039                 pll->disable(dev_priv, pll);
13040                 pll->on = false;
13041         }
13042
13043         if (HAS_PCH_SPLIT(dev))
13044                 ilk_wm_get_hw_state(dev);
13045
13046         if (force_restore) {
13047                 i915_redisable_vga(dev);
13048
13049                 /*
13050                  * We need to use raw interfaces for restoring state to avoid
13051                  * checking (bogus) intermediate states.
13052                  */
13053                 for_each_pipe(pipe) {
13054                         struct drm_crtc *crtc =
13055                                 dev_priv->pipe_to_crtc_mapping[pipe];
13056
13057                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13058                                          crtc->primary->fb);
13059                 }
13060         } else {
13061                 intel_modeset_update_staged_output_state(dev);
13062         }
13063
13064         intel_modeset_check_state(dev);
13065 }
13066
13067 void intel_modeset_gem_init(struct drm_device *dev)
13068 {
13069         struct drm_crtc *c;
13070         struct drm_i915_gem_object *obj;
13071
13072         mutex_lock(&dev->struct_mutex);
13073         intel_init_gt_powersave(dev);
13074         mutex_unlock(&dev->struct_mutex);
13075
13076         intel_modeset_init_hw(dev);
13077
13078         intel_setup_overlay(dev);
13079
13080         /*
13081          * Make sure any fbs we allocated at startup are properly
13082          * pinned & fenced.  When we do the allocation it's too early
13083          * for this.
13084          */
13085         mutex_lock(&dev->struct_mutex);
13086         for_each_crtc(dev, c) {
13087                 obj = intel_fb_obj(c->primary->fb);
13088                 if (obj == NULL)
13089                         continue;
13090
13091                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13092                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13093                                   to_intel_crtc(c)->pipe);
13094                         drm_framebuffer_unreference(c->primary->fb);
13095                         c->primary->fb = NULL;
13096                 }
13097         }
13098         mutex_unlock(&dev->struct_mutex);
13099 }
13100
13101 void intel_connector_unregister(struct intel_connector *intel_connector)
13102 {
13103         struct drm_connector *connector = &intel_connector->base;
13104
13105         intel_panel_destroy_backlight(connector);
13106         drm_connector_unregister(connector);
13107 }
13108
13109 void intel_modeset_cleanup(struct drm_device *dev)
13110 {
13111         struct drm_i915_private *dev_priv = dev->dev_private;
13112         struct drm_connector *connector;
13113
13114         /*
13115          * Interrupts and polling as the first thing to avoid creating havoc.
13116          * Too much stuff here (turning of rps, connectors, ...) would
13117          * experience fancy races otherwise.
13118          */
13119         drm_irq_uninstall(dev);
13120         cancel_work_sync(&dev_priv->hotplug_work);
13121         dev_priv->pm._irqs_disabled = true;
13122
13123         /*
13124          * Due to the hpd irq storm handling the hotplug work can re-arm the
13125          * poll handlers. Hence disable polling after hpd handling is shut down.
13126          */
13127         drm_kms_helper_poll_fini(dev);
13128
13129         mutex_lock(&dev->struct_mutex);
13130
13131         intel_unregister_dsm_handler();
13132
13133         intel_disable_fbc(dev);
13134
13135         intel_disable_gt_powersave(dev);
13136
13137         ironlake_teardown_rc6(dev);
13138
13139         mutex_unlock(&dev->struct_mutex);
13140
13141         /* flush any delayed tasks or pending work */
13142         flush_scheduled_work();
13143
13144         /* destroy the backlight and sysfs files before encoders/connectors */
13145         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13146                 struct intel_connector *intel_connector;
13147
13148                 intel_connector = to_intel_connector(connector);
13149                 intel_connector->unregister(intel_connector);
13150         }
13151
13152         drm_mode_config_cleanup(dev);
13153
13154         intel_cleanup_overlay(dev);
13155
13156         mutex_lock(&dev->struct_mutex);
13157         intel_cleanup_gt_powersave(dev);
13158         mutex_unlock(&dev->struct_mutex);
13159 }
13160
13161 /*
13162  * Return which encoder is currently attached for connector.
13163  */
13164 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13165 {
13166         return &intel_attached_encoder(connector)->base;
13167 }
13168
13169 void intel_connector_attach_encoder(struct intel_connector *connector,
13170                                     struct intel_encoder *encoder)
13171 {
13172         connector->encoder = encoder;
13173         drm_mode_connector_attach_encoder(&connector->base,
13174                                           &encoder->base);
13175 }
13176
13177 /*
13178  * set vga decode state - true == enable VGA decode
13179  */
13180 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13181 {
13182         struct drm_i915_private *dev_priv = dev->dev_private;
13183         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13184         u16 gmch_ctrl;
13185
13186         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13187                 DRM_ERROR("failed to read control word\n");
13188                 return -EIO;
13189         }
13190
13191         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13192                 return 0;
13193
13194         if (state)
13195                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13196         else
13197                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13198
13199         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13200                 DRM_ERROR("failed to write control word\n");
13201                 return -EIO;
13202         }
13203
13204         return 0;
13205 }
13206
13207 struct intel_display_error_state {
13208
13209         u32 power_well_driver;
13210
13211         int num_transcoders;
13212
13213         struct intel_cursor_error_state {
13214                 u32 control;
13215                 u32 position;
13216                 u32 base;
13217                 u32 size;
13218         } cursor[I915_MAX_PIPES];
13219
13220         struct intel_pipe_error_state {
13221                 bool power_domain_on;
13222                 u32 source;
13223                 u32 stat;
13224         } pipe[I915_MAX_PIPES];
13225
13226         struct intel_plane_error_state {
13227                 u32 control;
13228                 u32 stride;
13229                 u32 size;
13230                 u32 pos;
13231                 u32 addr;
13232                 u32 surface;
13233                 u32 tile_offset;
13234         } plane[I915_MAX_PIPES];
13235
13236         struct intel_transcoder_error_state {
13237                 bool power_domain_on;
13238                 enum transcoder cpu_transcoder;
13239
13240                 u32 conf;
13241
13242                 u32 htotal;
13243                 u32 hblank;
13244                 u32 hsync;
13245                 u32 vtotal;
13246                 u32 vblank;
13247                 u32 vsync;
13248         } transcoder[4];
13249 };
13250
13251 struct intel_display_error_state *
13252 intel_display_capture_error_state(struct drm_device *dev)
13253 {
13254         struct drm_i915_private *dev_priv = dev->dev_private;
13255         struct intel_display_error_state *error;
13256         int transcoders[] = {
13257                 TRANSCODER_A,
13258                 TRANSCODER_B,
13259                 TRANSCODER_C,
13260                 TRANSCODER_EDP,
13261         };
13262         int i;
13263
13264         if (INTEL_INFO(dev)->num_pipes == 0)
13265                 return NULL;
13266
13267         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13268         if (error == NULL)
13269                 return NULL;
13270
13271         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13272                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13273
13274         for_each_pipe(i) {
13275                 error->pipe[i].power_domain_on =
13276                         intel_display_power_enabled_unlocked(dev_priv,
13277                                                            POWER_DOMAIN_PIPE(i));
13278                 if (!error->pipe[i].power_domain_on)
13279                         continue;
13280
13281                 error->cursor[i].control = I915_READ(CURCNTR(i));
13282                 error->cursor[i].position = I915_READ(CURPOS(i));
13283                 error->cursor[i].base = I915_READ(CURBASE(i));
13284
13285                 error->plane[i].control = I915_READ(DSPCNTR(i));
13286                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13287                 if (INTEL_INFO(dev)->gen <= 3) {
13288                         error->plane[i].size = I915_READ(DSPSIZE(i));
13289                         error->plane[i].pos = I915_READ(DSPPOS(i));
13290                 }
13291                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13292                         error->plane[i].addr = I915_READ(DSPADDR(i));
13293                 if (INTEL_INFO(dev)->gen >= 4) {
13294                         error->plane[i].surface = I915_READ(DSPSURF(i));
13295                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13296                 }
13297
13298                 error->pipe[i].source = I915_READ(PIPESRC(i));
13299
13300                 if (HAS_GMCH_DISPLAY(dev))
13301                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13302         }
13303
13304         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13305         if (HAS_DDI(dev_priv->dev))
13306                 error->num_transcoders++; /* Account for eDP. */
13307
13308         for (i = 0; i < error->num_transcoders; i++) {
13309                 enum transcoder cpu_transcoder = transcoders[i];
13310
13311                 error->transcoder[i].power_domain_on =
13312                         intel_display_power_enabled_unlocked(dev_priv,
13313                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13314                 if (!error->transcoder[i].power_domain_on)
13315                         continue;
13316
13317                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13318
13319                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13320                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13321                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13322                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13323                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13324                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13325                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13326         }
13327
13328         return error;
13329 }
13330
13331 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13332
13333 void
13334 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13335                                 struct drm_device *dev,
13336                                 struct intel_display_error_state *error)
13337 {
13338         int i;
13339
13340         if (!error)
13341                 return;
13342
13343         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13344         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13345                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13346                            error->power_well_driver);
13347         for_each_pipe(i) {
13348                 err_printf(m, "Pipe [%d]:\n", i);
13349                 err_printf(m, "  Power: %s\n",
13350                            error->pipe[i].power_domain_on ? "on" : "off");
13351                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13352                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13353
13354                 err_printf(m, "Plane [%d]:\n", i);
13355                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13356                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13357                 if (INTEL_INFO(dev)->gen <= 3) {
13358                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13359                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13360                 }
13361                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13362                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13363                 if (INTEL_INFO(dev)->gen >= 4) {
13364                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13365                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13366                 }
13367
13368                 err_printf(m, "Cursor [%d]:\n", i);
13369                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13370                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13371                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13372         }
13373
13374         for (i = 0; i < error->num_transcoders; i++) {
13375                 err_printf(m, "CPU transcoder: %c\n",
13376                            transcoder_name(error->transcoder[i].cpu_transcoder));
13377                 err_printf(m, "  Power: %s\n",
13378                            error->transcoder[i].power_domain_on ? "on" : "off");
13379                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13380                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13381                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13382                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13383                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13384                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13385                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13386         }
13387 }