2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
68 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
84 static const uint32_t intel_cursor_formats[] = {
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
100 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
101 struct intel_link_m_n *m_n,
102 struct intel_link_m_n *m2_n2);
103 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
104 static void haswell_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipemisc(struct drm_crtc *crtc);
106 static void vlv_prepare_pll(struct intel_crtc *crtc,
107 const struct intel_crtc_state *pipe_config);
108 static void chv_prepare_pll(struct intel_crtc *crtc,
109 const struct intel_crtc_state *pipe_config);
110 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
113 struct intel_crtc_state *crtc_state);
114 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
116 static void skylake_pfit_enable(struct intel_crtc *crtc);
117 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
118 static void ironlake_pfit_enable(struct intel_crtc *crtc);
119 static void intel_modeset_setup_hw_state(struct drm_device *dev);
120 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
128 int p2_slow, p2_fast;
131 typedef struct intel_limit intel_limit_t;
133 intel_range_t dot, vco, n, m, m1, m2, p, p1;
137 /* returns HPLL frequency in kHz */
138 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
148 return vco_freq[hpll_freq] * 1000;
151 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg)
157 if (dev_priv->hpll_freq == 0)
158 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
164 divider = val & CCK_FREQUENCY_VALUES;
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
170 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
174 intel_pch_rawclk(struct drm_i915_private *dev_priv)
176 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
180 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
182 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
183 CCK_DISPLAY_REF_CLOCK_CONTROL);
187 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
191 /* hrawclock is 1/4 the FSB frequency */
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
202 case CLKCFG_FSB_1067:
204 case CLKCFG_FSB_1333:
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
215 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
217 if (HAS_PCH_SPLIT(dev_priv))
218 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
219 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
220 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
221 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
222 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
224 return; /* no rawclk on other platforms, or no need to know it */
226 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
229 static void intel_update_czclk(struct drm_i915_private *dev_priv)
231 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
234 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
235 CCK_CZ_CLOCK_CONTROL);
237 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
240 static inline u32 /* units of 100MHz */
241 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
242 const struct intel_crtc_state *pipe_config)
244 if (HAS_DDI(dev_priv))
245 return pipe_config->port_clock; /* SPLL */
246 else if (IS_GEN5(dev_priv))
247 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
252 static const intel_limit_t intel_limits_i8xx_dac = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 908000, .max = 1512000 },
255 .n = { .min = 2, .max = 16 },
256 .m = { .min = 96, .max = 140 },
257 .m1 = { .min = 18, .max = 26 },
258 .m2 = { .min = 6, .max = 16 },
259 .p = { .min = 4, .max = 128 },
260 .p1 = { .min = 2, .max = 33 },
261 .p2 = { .dot_limit = 165000,
262 .p2_slow = 4, .p2_fast = 2 },
265 static const intel_limit_t intel_limits_i8xx_dvo = {
266 .dot = { .min = 25000, .max = 350000 },
267 .vco = { .min = 908000, .max = 1512000 },
268 .n = { .min = 2, .max = 16 },
269 .m = { .min = 96, .max = 140 },
270 .m1 = { .min = 18, .max = 26 },
271 .m2 = { .min = 6, .max = 16 },
272 .p = { .min = 4, .max = 128 },
273 .p1 = { .min = 2, .max = 33 },
274 .p2 = { .dot_limit = 165000,
275 .p2_slow = 4, .p2_fast = 4 },
278 static const intel_limit_t intel_limits_i8xx_lvds = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 908000, .max = 1512000 },
281 .n = { .min = 2, .max = 16 },
282 .m = { .min = 96, .max = 140 },
283 .m1 = { .min = 18, .max = 26 },
284 .m2 = { .min = 6, .max = 16 },
285 .p = { .min = 4, .max = 128 },
286 .p1 = { .min = 1, .max = 6 },
287 .p2 = { .dot_limit = 165000,
288 .p2_slow = 14, .p2_fast = 7 },
291 static const intel_limit_t intel_limits_i9xx_sdvo = {
292 .dot = { .min = 20000, .max = 400000 },
293 .vco = { .min = 1400000, .max = 2800000 },
294 .n = { .min = 1, .max = 6 },
295 .m = { .min = 70, .max = 120 },
296 .m1 = { .min = 8, .max = 18 },
297 .m2 = { .min = 3, .max = 7 },
298 .p = { .min = 5, .max = 80 },
299 .p1 = { .min = 1, .max = 8 },
300 .p2 = { .dot_limit = 200000,
301 .p2_slow = 10, .p2_fast = 5 },
304 static const intel_limit_t intel_limits_i9xx_lvds = {
305 .dot = { .min = 20000, .max = 400000 },
306 .vco = { .min = 1400000, .max = 2800000 },
307 .n = { .min = 1, .max = 6 },
308 .m = { .min = 70, .max = 120 },
309 .m1 = { .min = 8, .max = 18 },
310 .m2 = { .min = 3, .max = 7 },
311 .p = { .min = 7, .max = 98 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 112000,
314 .p2_slow = 14, .p2_fast = 7 },
318 static const intel_limit_t intel_limits_g4x_sdvo = {
319 .dot = { .min = 25000, .max = 270000 },
320 .vco = { .min = 1750000, .max = 3500000},
321 .n = { .min = 1, .max = 4 },
322 .m = { .min = 104, .max = 138 },
323 .m1 = { .min = 17, .max = 23 },
324 .m2 = { .min = 5, .max = 11 },
325 .p = { .min = 10, .max = 30 },
326 .p1 = { .min = 1, .max = 3},
327 .p2 = { .dot_limit = 270000,
333 static const intel_limit_t intel_limits_g4x_hdmi = {
334 .dot = { .min = 22000, .max = 400000 },
335 .vco = { .min = 1750000, .max = 3500000},
336 .n = { .min = 1, .max = 4 },
337 .m = { .min = 104, .max = 138 },
338 .m1 = { .min = 16, .max = 23 },
339 .m2 = { .min = 5, .max = 11 },
340 .p = { .min = 5, .max = 80 },
341 .p1 = { .min = 1, .max = 8},
342 .p2 = { .dot_limit = 165000,
343 .p2_slow = 10, .p2_fast = 5 },
346 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
347 .dot = { .min = 20000, .max = 115000 },
348 .vco = { .min = 1750000, .max = 3500000 },
349 .n = { .min = 1, .max = 3 },
350 .m = { .min = 104, .max = 138 },
351 .m1 = { .min = 17, .max = 23 },
352 .m2 = { .min = 5, .max = 11 },
353 .p = { .min = 28, .max = 112 },
354 .p1 = { .min = 2, .max = 8 },
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 14, .p2_fast = 14
360 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
361 .dot = { .min = 80000, .max = 224000 },
362 .vco = { .min = 1750000, .max = 3500000 },
363 .n = { .min = 1, .max = 3 },
364 .m = { .min = 104, .max = 138 },
365 .m1 = { .min = 17, .max = 23 },
366 .m2 = { .min = 5, .max = 11 },
367 .p = { .min = 14, .max = 42 },
368 .p1 = { .min = 2, .max = 6 },
369 .p2 = { .dot_limit = 0,
370 .p2_slow = 7, .p2_fast = 7
374 static const intel_limit_t intel_limits_pineview_sdvo = {
375 .dot = { .min = 20000, .max = 400000},
376 .vco = { .min = 1700000, .max = 3500000 },
377 /* Pineview's Ncounter is a ring counter */
378 .n = { .min = 3, .max = 6 },
379 .m = { .min = 2, .max = 256 },
380 /* Pineview only has one combined m divider, which we treat as m2. */
381 .m1 = { .min = 0, .max = 0 },
382 .m2 = { .min = 0, .max = 254 },
383 .p = { .min = 5, .max = 80 },
384 .p1 = { .min = 1, .max = 8 },
385 .p2 = { .dot_limit = 200000,
386 .p2_slow = 10, .p2_fast = 5 },
389 static const intel_limit_t intel_limits_pineview_lvds = {
390 .dot = { .min = 20000, .max = 400000 },
391 .vco = { .min = 1700000, .max = 3500000 },
392 .n = { .min = 3, .max = 6 },
393 .m = { .min = 2, .max = 256 },
394 .m1 = { .min = 0, .max = 0 },
395 .m2 = { .min = 0, .max = 254 },
396 .p = { .min = 7, .max = 112 },
397 .p1 = { .min = 1, .max = 8 },
398 .p2 = { .dot_limit = 112000,
399 .p2_slow = 14, .p2_fast = 14 },
402 /* Ironlake / Sandybridge
404 * We calculate clock using (register_value + 2) for N/M1/M2, so here
405 * the range value for them is (actual_value - 2).
407 static const intel_limit_t intel_limits_ironlake_dac = {
408 .dot = { .min = 25000, .max = 350000 },
409 .vco = { .min = 1760000, .max = 3510000 },
410 .n = { .min = 1, .max = 5 },
411 .m = { .min = 79, .max = 127 },
412 .m1 = { .min = 12, .max = 22 },
413 .m2 = { .min = 5, .max = 9 },
414 .p = { .min = 5, .max = 80 },
415 .p1 = { .min = 1, .max = 8 },
416 .p2 = { .dot_limit = 225000,
417 .p2_slow = 10, .p2_fast = 5 },
420 static const intel_limit_t intel_limits_ironlake_single_lvds = {
421 .dot = { .min = 25000, .max = 350000 },
422 .vco = { .min = 1760000, .max = 3510000 },
423 .n = { .min = 1, .max = 3 },
424 .m = { .min = 79, .max = 118 },
425 .m1 = { .min = 12, .max = 22 },
426 .m2 = { .min = 5, .max = 9 },
427 .p = { .min = 28, .max = 112 },
428 .p1 = { .min = 2, .max = 8 },
429 .p2 = { .dot_limit = 225000,
430 .p2_slow = 14, .p2_fast = 14 },
433 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
434 .dot = { .min = 25000, .max = 350000 },
435 .vco = { .min = 1760000, .max = 3510000 },
436 .n = { .min = 1, .max = 3 },
437 .m = { .min = 79, .max = 127 },
438 .m1 = { .min = 12, .max = 22 },
439 .m2 = { .min = 5, .max = 9 },
440 .p = { .min = 14, .max = 56 },
441 .p1 = { .min = 2, .max = 8 },
442 .p2 = { .dot_limit = 225000,
443 .p2_slow = 7, .p2_fast = 7 },
446 /* LVDS 100mhz refclk limits. */
447 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
448 .dot = { .min = 25000, .max = 350000 },
449 .vco = { .min = 1760000, .max = 3510000 },
450 .n = { .min = 1, .max = 2 },
451 .m = { .min = 79, .max = 126 },
452 .m1 = { .min = 12, .max = 22 },
453 .m2 = { .min = 5, .max = 9 },
454 .p = { .min = 28, .max = 112 },
455 .p1 = { .min = 2, .max = 8 },
456 .p2 = { .dot_limit = 225000,
457 .p2_slow = 14, .p2_fast = 14 },
460 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
461 .dot = { .min = 25000, .max = 350000 },
462 .vco = { .min = 1760000, .max = 3510000 },
463 .n = { .min = 1, .max = 3 },
464 .m = { .min = 79, .max = 126 },
465 .m1 = { .min = 12, .max = 22 },
466 .m2 = { .min = 5, .max = 9 },
467 .p = { .min = 14, .max = 42 },
468 .p1 = { .min = 2, .max = 6 },
469 .p2 = { .dot_limit = 225000,
470 .p2_slow = 7, .p2_fast = 7 },
473 static const intel_limit_t intel_limits_vlv = {
475 * These are the data rate limits (measured in fast clocks)
476 * since those are the strictest limits we have. The fast
477 * clock and actual rate limits are more relaxed, so checking
478 * them would make no difference.
480 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
481 .vco = { .min = 4000000, .max = 6000000 },
482 .n = { .min = 1, .max = 7 },
483 .m1 = { .min = 2, .max = 3 },
484 .m2 = { .min = 11, .max = 156 },
485 .p1 = { .min = 2, .max = 3 },
486 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
489 static const intel_limit_t intel_limits_chv = {
491 * These are the data rate limits (measured in fast clocks)
492 * since those are the strictest limits we have. The fast
493 * clock and actual rate limits are more relaxed, so checking
494 * them would make no difference.
496 .dot = { .min = 25000 * 5, .max = 540000 * 5},
497 .vco = { .min = 4800000, .max = 6480000 },
498 .n = { .min = 1, .max = 1 },
499 .m1 = { .min = 2, .max = 2 },
500 .m2 = { .min = 24 << 22, .max = 175 << 22 },
501 .p1 = { .min = 2, .max = 4 },
502 .p2 = { .p2_slow = 1, .p2_fast = 14 },
505 static const intel_limit_t intel_limits_bxt = {
506 /* FIXME: find real dot limits */
507 .dot = { .min = 0, .max = INT_MAX },
508 .vco = { .min = 4800000, .max = 6700000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 /* FIXME: find real m2 limits */
512 .m2 = { .min = 2 << 22, .max = 255 << 22 },
513 .p1 = { .min = 2, .max = 4 },
514 .p2 = { .p2_slow = 1, .p2_fast = 20 },
518 needs_modeset(struct drm_crtc_state *state)
520 return drm_atomic_crtc_needs_modeset(state);
524 * Returns whether any output on the specified pipe is of the specified type
526 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
528 struct drm_device *dev = crtc->base.dev;
529 struct intel_encoder *encoder;
531 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
532 if (encoder->type == type)
539 * Returns whether any output on the specified pipe will have the specified
540 * type after a staged modeset is complete, i.e., the same as
541 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
544 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
547 struct drm_atomic_state *state = crtc_state->base.state;
548 struct drm_connector *connector;
549 struct drm_connector_state *connector_state;
550 struct intel_encoder *encoder;
551 int i, num_connectors = 0;
553 for_each_connector_in_state(state, connector, connector_state, i) {
554 if (connector_state->crtc != crtc_state->base.crtc)
559 encoder = to_intel_encoder(connector_state->best_encoder);
560 if (encoder->type == type)
564 WARN_ON(num_connectors == 0);
569 static const intel_limit_t *
570 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
572 struct drm_device *dev = crtc_state->base.crtc->dev;
573 const intel_limit_t *limit;
575 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
576 if (intel_is_dual_link_lvds(dev)) {
577 if (refclk == 100000)
578 limit = &intel_limits_ironlake_dual_lvds_100m;
580 limit = &intel_limits_ironlake_dual_lvds;
582 if (refclk == 100000)
583 limit = &intel_limits_ironlake_single_lvds_100m;
585 limit = &intel_limits_ironlake_single_lvds;
588 limit = &intel_limits_ironlake_dac;
593 static const intel_limit_t *
594 intel_g4x_limit(struct intel_crtc_state *crtc_state)
596 struct drm_device *dev = crtc_state->base.crtc->dev;
597 const intel_limit_t *limit;
599 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
600 if (intel_is_dual_link_lvds(dev))
601 limit = &intel_limits_g4x_dual_channel_lvds;
603 limit = &intel_limits_g4x_single_channel_lvds;
604 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
605 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
606 limit = &intel_limits_g4x_hdmi;
607 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
608 limit = &intel_limits_g4x_sdvo;
609 } else /* The option is for other outputs */
610 limit = &intel_limits_i9xx_sdvo;
615 static const intel_limit_t *
616 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
618 struct drm_device *dev = crtc_state->base.crtc->dev;
619 const intel_limit_t *limit;
622 limit = &intel_limits_bxt;
623 else if (HAS_PCH_SPLIT(dev))
624 limit = intel_ironlake_limit(crtc_state, refclk);
625 else if (IS_G4X(dev)) {
626 limit = intel_g4x_limit(crtc_state);
627 } else if (IS_PINEVIEW(dev)) {
628 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
629 limit = &intel_limits_pineview_lvds;
631 limit = &intel_limits_pineview_sdvo;
632 } else if (IS_CHERRYVIEW(dev)) {
633 limit = &intel_limits_chv;
634 } else if (IS_VALLEYVIEW(dev)) {
635 limit = &intel_limits_vlv;
636 } else if (!IS_GEN2(dev)) {
637 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
638 limit = &intel_limits_i9xx_lvds;
640 limit = &intel_limits_i9xx_sdvo;
642 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
643 limit = &intel_limits_i8xx_lvds;
644 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
645 limit = &intel_limits_i8xx_dvo;
647 limit = &intel_limits_i8xx_dac;
653 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
654 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
655 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
656 * The helpers' return value is the rate of the clock that is fed to the
657 * display engine's pipe which can be the above fast dot clock rate or a
658 * divided-down version of it.
660 /* m1 is reserved as 0 in Pineview, n is a ring counter */
661 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
663 clock->m = clock->m2 + 2;
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n == 0 || clock->p == 0))
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
673 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
675 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
678 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
680 clock->m = i9xx_dpll_compute_m(clock);
681 clock->p = clock->p1 * clock->p2;
682 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
684 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
685 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
690 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
692 clock->m = clock->m1 * clock->m2;
693 clock->p = clock->p1 * clock->p2;
694 if (WARN_ON(clock->n == 0 || clock->p == 0))
696 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
697 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
699 return clock->dot / 5;
702 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
704 clock->m = clock->m1 * clock->m2;
705 clock->p = clock->p1 * clock->p2;
706 if (WARN_ON(clock->n == 0 || clock->p == 0))
708 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
710 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
712 return clock->dot / 5;
715 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
717 * Returns whether the given set of divisors are valid for a given refclk with
718 * the given connectors.
721 static bool intel_PLL_is_valid(struct drm_device *dev,
722 const intel_limit_t *limit,
723 const intel_clock_t *clock)
725 if (clock->n < limit->n.min || limit->n.max < clock->n)
726 INTELPllInvalid("n out of range\n");
727 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
728 INTELPllInvalid("p1 out of range\n");
729 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
730 INTELPllInvalid("m2 out of range\n");
731 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
732 INTELPllInvalid("m1 out of range\n");
734 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
735 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
736 if (clock->m1 <= clock->m2)
737 INTELPllInvalid("m1 <= m2\n");
739 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
740 if (clock->p < limit->p.min || limit->p.max < clock->p)
741 INTELPllInvalid("p out of range\n");
742 if (clock->m < limit->m.min || limit->m.max < clock->m)
743 INTELPllInvalid("m out of range\n");
746 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
747 INTELPllInvalid("vco out of range\n");
748 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
749 * connector, etc., rather than just a single range.
751 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
752 INTELPllInvalid("dot out of range\n");
758 i9xx_select_p2_div(const intel_limit_t *limit,
759 const struct intel_crtc_state *crtc_state,
762 struct drm_device *dev = crtc_state->base.crtc->dev;
764 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
766 * For LVDS just rely on its current settings for dual-channel.
767 * We haven't figured out how to reliably set up different
768 * single/dual channel state, if we even can.
770 if (intel_is_dual_link_lvds(dev))
771 return limit->p2.p2_fast;
773 return limit->p2.p2_slow;
775 if (target < limit->p2.dot_limit)
776 return limit->p2.p2_slow;
778 return limit->p2.p2_fast;
783 i9xx_find_best_dpll(const intel_limit_t *limit,
784 struct intel_crtc_state *crtc_state,
785 int target, int refclk, intel_clock_t *match_clock,
786 intel_clock_t *best_clock)
788 struct drm_device *dev = crtc_state->base.crtc->dev;
792 memset(best_clock, 0, sizeof(*best_clock));
794 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
796 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
798 for (clock.m2 = limit->m2.min;
799 clock.m2 <= limit->m2.max; clock.m2++) {
800 if (clock.m2 >= clock.m1)
802 for (clock.n = limit->n.min;
803 clock.n <= limit->n.max; clock.n++) {
804 for (clock.p1 = limit->p1.min;
805 clock.p1 <= limit->p1.max; clock.p1++) {
808 i9xx_calc_dpll_params(refclk, &clock);
809 if (!intel_PLL_is_valid(dev, limit,
813 clock.p != match_clock->p)
816 this_err = abs(clock.dot - target);
817 if (this_err < err) {
826 return (err != target);
830 pnv_find_best_dpll(const intel_limit_t *limit,
831 struct intel_crtc_state *crtc_state,
832 int target, int refclk, intel_clock_t *match_clock,
833 intel_clock_t *best_clock)
835 struct drm_device *dev = crtc_state->base.crtc->dev;
839 memset(best_clock, 0, sizeof(*best_clock));
841 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
843 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
845 for (clock.m2 = limit->m2.min;
846 clock.m2 <= limit->m2.max; clock.m2++) {
847 for (clock.n = limit->n.min;
848 clock.n <= limit->n.max; clock.n++) {
849 for (clock.p1 = limit->p1.min;
850 clock.p1 <= limit->p1.max; clock.p1++) {
853 pnv_calc_dpll_params(refclk, &clock);
854 if (!intel_PLL_is_valid(dev, limit,
858 clock.p != match_clock->p)
861 this_err = abs(clock.dot - target);
862 if (this_err < err) {
871 return (err != target);
875 g4x_find_best_dpll(const intel_limit_t *limit,
876 struct intel_crtc_state *crtc_state,
877 int target, int refclk, intel_clock_t *match_clock,
878 intel_clock_t *best_clock)
880 struct drm_device *dev = crtc_state->base.crtc->dev;
884 /* approximately equals target * 0.00585 */
885 int err_most = (target >> 8) + (target >> 9);
887 memset(best_clock, 0, sizeof(*best_clock));
889 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
891 max_n = limit->n.max;
892 /* based on hardware requirement, prefer smaller n to precision */
893 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
894 /* based on hardware requirement, prefere larger m1,m2 */
895 for (clock.m1 = limit->m1.max;
896 clock.m1 >= limit->m1.min; clock.m1--) {
897 for (clock.m2 = limit->m2.max;
898 clock.m2 >= limit->m2.min; clock.m2--) {
899 for (clock.p1 = limit->p1.max;
900 clock.p1 >= limit->p1.min; clock.p1--) {
903 i9xx_calc_dpll_params(refclk, &clock);
904 if (!intel_PLL_is_valid(dev, limit,
908 this_err = abs(clock.dot - target);
909 if (this_err < err_most) {
923 * Check if the calculated PLL configuration is more optimal compared to the
924 * best configuration and error found so far. Return the calculated error.
926 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
927 const intel_clock_t *calculated_clock,
928 const intel_clock_t *best_clock,
929 unsigned int best_error_ppm,
930 unsigned int *error_ppm)
933 * For CHV ignore the error and consider only the P value.
934 * Prefer a bigger P value based on HW requirements.
936 if (IS_CHERRYVIEW(dev)) {
939 return calculated_clock->p > best_clock->p;
942 if (WARN_ON_ONCE(!target_freq))
945 *error_ppm = div_u64(1000000ULL *
946 abs(target_freq - calculated_clock->dot),
949 * Prefer a better P value over a better (smaller) error if the error
950 * is small. Ensure this preference for future configurations too by
951 * setting the error to 0.
953 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
959 return *error_ppm + 10 < best_error_ppm;
963 vlv_find_best_dpll(const intel_limit_t *limit,
964 struct intel_crtc_state *crtc_state,
965 int target, int refclk, intel_clock_t *match_clock,
966 intel_clock_t *best_clock)
968 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
969 struct drm_device *dev = crtc->base.dev;
971 unsigned int bestppm = 1000000;
972 /* min update 19.2 MHz */
973 int max_n = min(limit->n.max, refclk / 19200);
976 target *= 5; /* fast clock */
978 memset(best_clock, 0, sizeof(*best_clock));
980 /* based on hardware requirement, prefer smaller n to precision */
981 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
982 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
983 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
984 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
985 clock.p = clock.p1 * clock.p2;
986 /* based on hardware requirement, prefer bigger m1,m2 values */
987 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
990 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
993 vlv_calc_dpll_params(refclk, &clock);
995 if (!intel_PLL_is_valid(dev, limit,
999 if (!vlv_PLL_is_optimal(dev, target,
1005 *best_clock = clock;
1017 chv_find_best_dpll(const intel_limit_t *limit,
1018 struct intel_crtc_state *crtc_state,
1019 int target, int refclk, intel_clock_t *match_clock,
1020 intel_clock_t *best_clock)
1022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1023 struct drm_device *dev = crtc->base.dev;
1024 unsigned int best_error_ppm;
1025 intel_clock_t clock;
1029 memset(best_clock, 0, sizeof(*best_clock));
1030 best_error_ppm = 1000000;
1033 * Based on hardware doc, the n always set to 1, and m1 always
1034 * set to 2. If requires to support 200Mhz refclk, we need to
1035 * revisit this because n may not 1 anymore.
1037 clock.n = 1, clock.m1 = 2;
1038 target *= 5; /* fast clock */
1040 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1041 for (clock.p2 = limit->p2.p2_fast;
1042 clock.p2 >= limit->p2.p2_slow;
1043 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1044 unsigned int error_ppm;
1046 clock.p = clock.p1 * clock.p2;
1048 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1049 clock.n) << 22, refclk * clock.m1);
1051 if (m2 > INT_MAX/clock.m1)
1056 chv_calc_dpll_params(refclk, &clock);
1058 if (!intel_PLL_is_valid(dev, limit, &clock))
1061 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1062 best_error_ppm, &error_ppm))
1065 *best_clock = clock;
1066 best_error_ppm = error_ppm;
1074 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1075 intel_clock_t *best_clock)
1077 int refclk = i9xx_get_refclk(crtc_state, 0);
1079 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1080 target_clock, refclk, NULL, best_clock);
1083 bool intel_crtc_active(struct drm_crtc *crtc)
1085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1087 /* Be paranoid as we can arrive here with only partial
1088 * state retrieved from the hardware during setup.
1090 * We can ditch the adjusted_mode.crtc_clock check as soon
1091 * as Haswell has gained clock readout/fastboot support.
1093 * We can ditch the crtc->primary->fb check as soon as we can
1094 * properly reconstruct framebuffers.
1096 * FIXME: The intel_crtc->active here should be switched to
1097 * crtc->state->active once we have proper CRTC states wired up
1100 return intel_crtc->active && crtc->primary->state->fb &&
1101 intel_crtc->config->base.adjusted_mode.crtc_clock;
1104 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1107 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1110 return intel_crtc->config->cpu_transcoder;
1113 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 i915_reg_t reg = PIPEDSL(pipe);
1121 line_mask = DSL_LINEMASK_GEN2;
1123 line_mask = DSL_LINEMASK_GEN3;
1125 line1 = I915_READ(reg) & line_mask;
1127 line2 = I915_READ(reg) & line_mask;
1129 return line1 == line2;
1133 * intel_wait_for_pipe_off - wait for pipe to turn off
1134 * @crtc: crtc whose pipe to wait for
1136 * After disabling a pipe, we can't wait for vblank in the usual way,
1137 * spinning on the vblank interrupt status bit, since we won't actually
1138 * see an interrupt when the pipe is disabled.
1140 * On Gen4 and above:
1141 * wait for the pipe register state bit to turn off
1144 * wait for the display line value to settle (it usually
1145 * ends up stopping at the start of the next frame).
1148 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1150 struct drm_device *dev = crtc->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1153 enum pipe pipe = crtc->pipe;
1155 if (INTEL_INFO(dev)->gen >= 4) {
1156 i915_reg_t reg = PIPECONF(cpu_transcoder);
1158 /* Wait for the Pipe State to go off */
1159 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1161 WARN(1, "pipe_off wait timed out\n");
1163 /* Wait for the display line to settle */
1164 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1165 WARN(1, "pipe_off wait timed out\n");
1169 /* Only for pre-ILK configs */
1170 void assert_pll(struct drm_i915_private *dev_priv,
1171 enum pipe pipe, bool state)
1176 val = I915_READ(DPLL(pipe));
1177 cur_state = !!(val & DPLL_VCO_ENABLE);
1178 I915_STATE_WARN(cur_state != state,
1179 "PLL state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1183 /* XXX: the dsi pll is shared between MIPI DSI ports */
1184 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1189 mutex_lock(&dev_priv->sb_lock);
1190 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1191 mutex_unlock(&dev_priv->sb_lock);
1193 cur_state = val & DSI_PLL_VCO_EN;
1194 I915_STATE_WARN(cur_state != state,
1195 "DSI PLL state assertion failure (expected %s, current %s)\n",
1196 onoff(state), onoff(cur_state));
1199 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, bool state)
1203 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1206 if (HAS_DDI(dev_priv->dev)) {
1207 /* DDI does not have a specific FDI_TX register */
1208 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1209 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1211 u32 val = I915_READ(FDI_TX_CTL(pipe));
1212 cur_state = !!(val & FDI_TX_ENABLE);
1214 I915_STATE_WARN(cur_state != state,
1215 "FDI TX state assertion failure (expected %s, current %s)\n",
1216 onoff(state), onoff(cur_state));
1218 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1219 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1221 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1227 val = I915_READ(FDI_RX_CTL(pipe));
1228 cur_state = !!(val & FDI_RX_ENABLE);
1229 I915_STATE_WARN(cur_state != state,
1230 "FDI RX state assertion failure (expected %s, current %s)\n",
1231 onoff(state), onoff(cur_state));
1233 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1234 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1236 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1241 /* ILK FDI PLL is always enabled */
1242 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1245 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1246 if (HAS_DDI(dev_priv->dev))
1249 val = I915_READ(FDI_TX_CTL(pipe));
1250 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1253 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1254 enum pipe pipe, bool state)
1259 val = I915_READ(FDI_RX_CTL(pipe));
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 onoff(state), onoff(cur_state));
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1269 struct drm_device *dev = dev_priv->dev;
1272 enum pipe panel_pipe = PIPE_A;
1275 if (WARN_ON(HAS_DDI(dev)))
1278 if (HAS_PCH_SPLIT(dev)) {
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1311 struct drm_device *dev = dev_priv->dev;
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), onoff(state), onoff(cur_state));
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1330 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1332 enum intel_display_power_domain power_domain;
1334 /* if we need the pipe quirk it must be always on */
1335 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1336 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1339 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1340 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1341 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1342 cur_state = !!(val & PIPECONF_ENABLE);
1344 intel_display_power_put(dev_priv, power_domain);
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), onoff(state), onoff(cur_state));
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1360 val = I915_READ(DSPCNTR(plane));
1361 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1362 I915_STATE_WARN(cur_state != state,
1363 "plane %c assertion failure (expected %s, current %s)\n",
1364 plane_name(plane), onoff(state), onoff(cur_state));
1367 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1368 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1370 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 struct drm_device *dev = dev_priv->dev;
1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
1378 u32 val = I915_READ(DSPCNTR(pipe));
1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380 "plane %c assertion failure, should be disabled but not\n",
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv, i) {
1387 u32 val = I915_READ(DSPCNTR(i));
1388 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1389 DISPPLANE_SEL_PIPE_SHIFT;
1390 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1391 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1392 plane_name(i), pipe_name(pipe));
1396 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 struct drm_device *dev = dev_priv->dev;
1402 if (INTEL_INFO(dev)->gen >= 9) {
1403 for_each_sprite(dev_priv, pipe, sprite) {
1404 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1405 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1406 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1407 sprite, pipe_name(pipe));
1409 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 u32 val = I915_READ(SPCNTR(pipe, sprite));
1412 I915_STATE_WARN(val & SP_ENABLE,
1413 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1414 sprite_name(pipe, sprite), pipe_name(pipe));
1416 } else if (INTEL_INFO(dev)->gen >= 7) {
1417 u32 val = I915_READ(SPRCTL(pipe));
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 u32 val = I915_READ(DVSCNTR(pipe));
1423 I915_STATE_WARN(val & DVS_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 plane_name(pipe), pipe_name(pipe));
1429 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1432 drm_crtc_vblank_put(crtc);
1435 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1441 val = I915_READ(PCH_TRANSCONF(pipe));
1442 enabled = !!(val & TRANS_ENABLE);
1443 I915_STATE_WARN(enabled,
1444 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1448 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe, u32 port_sel, u32 val)
1451 if ((val & DP_PORT_EN) == 0)
1454 if (HAS_PCH_CPT(dev_priv->dev)) {
1455 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1456 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1458 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1459 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1462 if ((val & DP_PIPE_MASK) != (pipe << 30))
1468 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 val)
1471 if ((val & SDVO_ENABLE) == 0)
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1477 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1478 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1481 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1487 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1488 enum pipe pipe, u32 val)
1490 if ((val & LVDS_PORT_EN) == 0)
1493 if (HAS_PCH_CPT(dev_priv->dev)) {
1494 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1497 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1503 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1504 enum pipe pipe, u32 val)
1506 if ((val & ADPA_DAC_ENABLE) == 0)
1508 if (HAS_PCH_CPT(dev_priv->dev)) {
1509 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1518 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1519 enum pipe pipe, i915_reg_t reg,
1522 u32 val = I915_READ(reg);
1523 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1524 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1525 i915_mmio_reg_offset(reg), pipe_name(pipe));
1527 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1528 && (val & DP_PIPEB_SELECT),
1529 "IBX PCH dp port still using transcoder B\n");
1532 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, i915_reg_t reg)
1535 u32 val = I915_READ(reg);
1536 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1537 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1538 i915_mmio_reg_offset(reg), pipe_name(pipe));
1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1541 && (val & SDVO_PIPE_B_SELECT),
1542 "IBX PCH hdmi port still using transcoder B\n");
1545 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1550 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1551 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1552 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1554 val = I915_READ(PCH_ADPA);
1555 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1556 "PCH VGA enabled on transcoder %c, should be disabled\n",
1559 val = I915_READ(PCH_LVDS);
1560 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1561 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1564 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1565 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1566 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1569 static void vlv_enable_pll(struct intel_crtc *crtc,
1570 const struct intel_crtc_state *pipe_config)
1572 struct drm_device *dev = crtc->base.dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 i915_reg_t reg = DPLL(crtc->pipe);
1575 u32 dpll = pipe_config->dpll_hw_state.dpll;
1577 assert_pipe_disabled(dev_priv, crtc->pipe);
1579 /* PLL is protected by panel, make sure we can write it */
1580 if (IS_MOBILE(dev_priv->dev))
1581 assert_panel_unlocked(dev_priv, crtc->pipe);
1583 I915_WRITE(reg, dpll);
1587 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1588 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1590 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1591 POSTING_READ(DPLL_MD(crtc->pipe));
1593 /* We do this three times for luck */
1594 I915_WRITE(reg, dpll);
1596 udelay(150); /* wait for warmup */
1597 I915_WRITE(reg, dpll);
1599 udelay(150); /* wait for warmup */
1600 I915_WRITE(reg, dpll);
1602 udelay(150); /* wait for warmup */
1605 static void chv_enable_pll(struct intel_crtc *crtc,
1606 const struct intel_crtc_state *pipe_config)
1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int pipe = crtc->pipe;
1611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1614 assert_pipe_disabled(dev_priv, crtc->pipe);
1616 mutex_lock(&dev_priv->sb_lock);
1618 /* Enable back the 10bit clock to display controller */
1619 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1620 tmp |= DPIO_DCLKP_EN;
1621 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1623 mutex_unlock(&dev_priv->sb_lock);
1626 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1631 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1633 /* Check PLL is locked */
1634 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("PLL %d failed to lock\n", pipe);
1637 /* not sure when this should be written */
1638 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1639 POSTING_READ(DPLL_MD(pipe));
1642 static int intel_num_dvo_pipes(struct drm_device *dev)
1644 struct intel_crtc *crtc;
1647 for_each_intel_crtc(dev, crtc)
1648 count += crtc->base.state->active &&
1649 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1654 static void i9xx_enable_pll(struct intel_crtc *crtc)
1656 struct drm_device *dev = crtc->base.dev;
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 i915_reg_t reg = DPLL(crtc->pipe);
1659 u32 dpll = crtc->config->dpll_hw_state.dpll;
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1663 /* No really, not for ILK+ */
1664 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1666 /* PLL is protected by panel, make sure we can write it */
1667 if (IS_MOBILE(dev) && !IS_I830(dev))
1668 assert_panel_unlocked(dev_priv, crtc->pipe);
1670 /* Enable DVO 2x clock on both PLLs if necessary */
1671 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1673 * It appears to be important that we don't enable this
1674 * for the current pipe before otherwise configuring the
1675 * PLL. No idea how this should be handled if multiple
1676 * DVO outputs are enabled simultaneosly.
1678 dpll |= DPLL_DVO_2X_MODE;
1679 I915_WRITE(DPLL(!crtc->pipe),
1680 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1684 * Apparently we need to have VGA mode enabled prior to changing
1685 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1686 * dividers, even though the register value does change.
1690 I915_WRITE(reg, dpll);
1692 /* Wait for the clocks to stabilize. */
1696 if (INTEL_INFO(dev)->gen >= 4) {
1697 I915_WRITE(DPLL_MD(crtc->pipe),
1698 crtc->config->dpll_hw_state.dpll_md);
1700 /* The pixel multiplier can only be updated once the
1701 * DPLL is enabled and the clocks are stable.
1703 * So write it again.
1705 I915_WRITE(reg, dpll);
1708 /* We do this three times for luck */
1709 I915_WRITE(reg, dpll);
1711 udelay(150); /* wait for warmup */
1712 I915_WRITE(reg, dpll);
1714 udelay(150); /* wait for warmup */
1715 I915_WRITE(reg, dpll);
1717 udelay(150); /* wait for warmup */
1721 * i9xx_disable_pll - disable a PLL
1722 * @dev_priv: i915 private structure
1723 * @pipe: pipe PLL to disable
1725 * Disable the PLL for @pipe, making sure the pipe is off first.
1727 * Note! This is for pre-ILK only.
1729 static void i9xx_disable_pll(struct intel_crtc *crtc)
1731 struct drm_device *dev = crtc->base.dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 enum pipe pipe = crtc->pipe;
1735 /* Disable DVO 2x clock on both PLLs if necessary */
1737 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1738 !intel_num_dvo_pipes(dev)) {
1739 I915_WRITE(DPLL(PIPE_B),
1740 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1741 I915_WRITE(DPLL(PIPE_A),
1742 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1745 /* Don't disable pipe or pipe PLLs if needed */
1746 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1747 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1750 /* Make sure the pipe isn't still relying on us */
1751 assert_pipe_disabled(dev_priv, pipe);
1753 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1754 POSTING_READ(DPLL(pipe));
1757 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
1765 * Leave integrated clock source and reference clock enabled for pipe B.
1766 * The latter is needed for VGA hotplug / manual detection.
1768 val = DPLL_VGA_MODE_DIS;
1770 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1771 I915_WRITE(DPLL(pipe), val);
1772 POSTING_READ(DPLL(pipe));
1776 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1778 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1781 /* Make sure the pipe isn't still relying on us */
1782 assert_pipe_disabled(dev_priv, pipe);
1784 /* Set PLL en = 0 */
1785 val = DPLL_SSC_REF_CLK_CHV |
1786 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1788 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1789 I915_WRITE(DPLL(pipe), val);
1790 POSTING_READ(DPLL(pipe));
1792 mutex_lock(&dev_priv->sb_lock);
1794 /* Disable 10bit clock to display controller */
1795 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1796 val &= ~DPIO_DCLKP_EN;
1797 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1799 mutex_unlock(&dev_priv->sb_lock);
1802 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1803 struct intel_digital_port *dport,
1804 unsigned int expected_mask)
1807 i915_reg_t dpll_reg;
1809 switch (dport->port) {
1811 port_mask = DPLL_PORTB_READY_MASK;
1815 port_mask = DPLL_PORTC_READY_MASK;
1817 expected_mask <<= 4;
1820 port_mask = DPLL_PORTD_READY_MASK;
1821 dpll_reg = DPIO_PHY_STATUS;
1827 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1828 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1829 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1832 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1835 struct drm_device *dev = dev_priv->dev;
1836 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839 uint32_t val, pipeconf_val;
1841 /* PCH only available on ILK+ */
1842 BUG_ON(!HAS_PCH_SPLIT(dev));
1844 /* Make sure PCH DPLL is enabled */
1845 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1847 /* FDI must be feeding us bits for PCH ports */
1848 assert_fdi_tx_enabled(dev_priv, pipe);
1849 assert_fdi_rx_enabled(dev_priv, pipe);
1851 if (HAS_PCH_CPT(dev)) {
1852 /* Workaround: Set the timing override bit before enabling the
1853 * pch transcoder. */
1854 reg = TRANS_CHICKEN2(pipe);
1855 val = I915_READ(reg);
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(reg, val);
1860 reg = PCH_TRANSCONF(pipe);
1861 val = I915_READ(reg);
1862 pipeconf_val = I915_READ(PIPECONF(pipe));
1864 if (HAS_PCH_IBX(dev_priv->dev)) {
1866 * Make the BPC in transcoder be consistent with
1867 * that in pipeconf reg. For HDMI we must use 8bpc
1868 * here for both 8bpc and 12bpc.
1870 val &= ~PIPECONF_BPC_MASK;
1871 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1872 val |= PIPECONF_8BPC;
1874 val |= pipeconf_val & PIPECONF_BPC_MASK;
1877 val &= ~TRANS_INTERLACE_MASK;
1878 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1879 if (HAS_PCH_IBX(dev_priv->dev) &&
1880 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1881 val |= TRANS_LEGACY_INTERLACED_ILK;
1883 val |= TRANS_INTERLACED;
1885 val |= TRANS_PROGRESSIVE;
1887 I915_WRITE(reg, val | TRANS_ENABLE);
1888 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1889 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1892 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1893 enum transcoder cpu_transcoder)
1895 u32 val, pipeconf_val;
1897 /* PCH only available on ILK+ */
1898 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1900 /* FDI must be feeding us bits for PCH ports */
1901 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1902 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1904 /* Workaround: set timing override bit. */
1905 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1906 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1907 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1910 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1912 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1913 PIPECONF_INTERLACED_ILK)
1914 val |= TRANS_INTERLACED;
1916 val |= TRANS_PROGRESSIVE;
1918 I915_WRITE(LPT_TRANSCONF, val);
1919 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1920 DRM_ERROR("Failed to enable PCH transcoder\n");
1923 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1926 struct drm_device *dev = dev_priv->dev;
1930 /* FDI relies on the transcoder */
1931 assert_fdi_tx_disabled(dev_priv, pipe);
1932 assert_fdi_rx_disabled(dev_priv, pipe);
1934 /* Ports must be off as well */
1935 assert_pch_ports_disabled(dev_priv, pipe);
1937 reg = PCH_TRANSCONF(pipe);
1938 val = I915_READ(reg);
1939 val &= ~TRANS_ENABLE;
1940 I915_WRITE(reg, val);
1941 /* wait for PCH transcoder off, transcoder state */
1942 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1943 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1945 if (HAS_PCH_CPT(dev)) {
1946 /* Workaround: Clear the timing override chicken bit again. */
1947 reg = TRANS_CHICKEN2(pipe);
1948 val = I915_READ(reg);
1949 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950 I915_WRITE(reg, val);
1954 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1958 val = I915_READ(LPT_TRANSCONF);
1959 val &= ~TRANS_ENABLE;
1960 I915_WRITE(LPT_TRANSCONF, val);
1961 /* wait for PCH transcoder off, transcoder state */
1962 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1963 DRM_ERROR("Failed to disable PCH transcoder\n");
1965 /* Workaround: clear timing override bit. */
1966 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1967 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1972 * intel_enable_pipe - enable a pipe, asserting requirements
1973 * @crtc: crtc responsible for the pipe
1975 * Enable @crtc's pipe, making sure that various hardware specific requirements
1976 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1978 static void intel_enable_pipe(struct intel_crtc *crtc)
1980 struct drm_device *dev = crtc->base.dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 enum pipe pipe = crtc->pipe;
1983 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1984 enum pipe pch_transcoder;
1988 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1990 assert_planes_disabled(dev_priv, pipe);
1991 assert_cursor_disabled(dev_priv, pipe);
1992 assert_sprites_disabled(dev_priv, pipe);
1994 if (HAS_PCH_LPT(dev_priv->dev))
1995 pch_transcoder = TRANSCODER_A;
1997 pch_transcoder = pipe;
2000 * A pipe without a PLL won't actually be able to drive bits from
2001 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2004 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2005 if (crtc->config->has_dsi_encoder)
2006 assert_dsi_pll_enabled(dev_priv);
2008 assert_pll_enabled(dev_priv, pipe);
2010 if (crtc->config->has_pch_encoder) {
2011 /* if driving the PCH, we need FDI enabled */
2012 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2013 assert_fdi_tx_pll_enabled(dev_priv,
2014 (enum pipe) cpu_transcoder);
2016 /* FIXME: assert CPU port conditions for SNB+ */
2019 reg = PIPECONF(cpu_transcoder);
2020 val = I915_READ(reg);
2021 if (val & PIPECONF_ENABLE) {
2022 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2023 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2027 I915_WRITE(reg, val | PIPECONF_ENABLE);
2031 * Until the pipe starts DSL will read as 0, which would cause
2032 * an apparent vblank timestamp jump, which messes up also the
2033 * frame count when it's derived from the timestamps. So let's
2034 * wait for the pipe to start properly before we call
2035 * drm_crtc_vblank_on()
2037 if (dev->max_vblank_count == 0 &&
2038 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2039 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2043 * intel_disable_pipe - disable a pipe, asserting requirements
2044 * @crtc: crtc whose pipes is to be disabled
2046 * Disable the pipe of @crtc, making sure that various hardware
2047 * specific requirements are met, if applicable, e.g. plane
2048 * disabled, panel fitter off, etc.
2050 * Will wait until the pipe has shut down before returning.
2052 static void intel_disable_pipe(struct intel_crtc *crtc)
2054 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2056 enum pipe pipe = crtc->pipe;
2060 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2063 * Make sure planes won't keep trying to pump pixels to us,
2064 * or we might hang the display.
2066 assert_planes_disabled(dev_priv, pipe);
2067 assert_cursor_disabled(dev_priv, pipe);
2068 assert_sprites_disabled(dev_priv, pipe);
2070 reg = PIPECONF(cpu_transcoder);
2071 val = I915_READ(reg);
2072 if ((val & PIPECONF_ENABLE) == 0)
2076 * Double wide has implications for planes
2077 * so best keep it disabled when not needed.
2079 if (crtc->config->double_wide)
2080 val &= ~PIPECONF_DOUBLE_WIDE;
2082 /* Don't disable pipe or pipe PLLs if needed */
2083 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2084 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2085 val &= ~PIPECONF_ENABLE;
2087 I915_WRITE(reg, val);
2088 if ((val & PIPECONF_ENABLE) == 0)
2089 intel_wait_for_pipe_off(crtc);
2092 static bool need_vtd_wa(struct drm_device *dev)
2094 #ifdef CONFIG_INTEL_IOMMU
2095 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2101 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2103 return IS_GEN2(dev_priv) ? 2048 : 4096;
2106 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2107 uint64_t fb_modifier, unsigned int cpp)
2109 switch (fb_modifier) {
2110 case DRM_FORMAT_MOD_NONE:
2112 case I915_FORMAT_MOD_X_TILED:
2113 if (IS_GEN2(dev_priv))
2117 case I915_FORMAT_MOD_Y_TILED:
2118 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2122 case I915_FORMAT_MOD_Yf_TILED:
2138 MISSING_CASE(fb_modifier);
2143 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2144 uint64_t fb_modifier, unsigned int cpp)
2146 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2149 return intel_tile_size(dev_priv) /
2150 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2153 /* Return the tile dimensions in pixel units */
2154 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2155 unsigned int *tile_width,
2156 unsigned int *tile_height,
2157 uint64_t fb_modifier,
2160 unsigned int tile_width_bytes =
2161 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2163 *tile_width = tile_width_bytes / cpp;
2164 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2168 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2169 uint32_t pixel_format, uint64_t fb_modifier)
2171 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2172 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2174 return ALIGN(height, tile_height);
2177 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2179 unsigned int size = 0;
2182 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2183 size += rot_info->plane[i].width * rot_info->plane[i].height;
2189 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2190 const struct drm_framebuffer *fb,
2191 unsigned int rotation)
2193 if (intel_rotation_90_or_270(rotation)) {
2194 *view = i915_ggtt_view_rotated;
2195 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2197 *view = i915_ggtt_view_normal;
2202 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2203 struct drm_framebuffer *fb)
2205 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2206 unsigned int tile_size, tile_width, tile_height, cpp;
2208 tile_size = intel_tile_size(dev_priv);
2210 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2211 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2212 fb->modifier[0], cpp);
2214 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2215 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2217 if (info->pixel_format == DRM_FORMAT_NV12) {
2218 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2219 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2220 fb->modifier[1], cpp);
2222 info->uv_offset = fb->offsets[1];
2223 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2224 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2228 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2230 if (INTEL_INFO(dev_priv)->gen >= 9)
2232 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2233 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2235 else if (INTEL_INFO(dev_priv)->gen >= 4)
2241 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2242 uint64_t fb_modifier)
2244 switch (fb_modifier) {
2245 case DRM_FORMAT_MOD_NONE:
2246 return intel_linear_alignment(dev_priv);
2247 case I915_FORMAT_MOD_X_TILED:
2248 if (INTEL_INFO(dev_priv)->gen >= 9)
2251 case I915_FORMAT_MOD_Y_TILED:
2252 case I915_FORMAT_MOD_Yf_TILED:
2253 return 1 * 1024 * 1024;
2255 MISSING_CASE(fb_modifier);
2261 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2262 unsigned int rotation)
2264 struct drm_device *dev = fb->dev;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2267 struct i915_ggtt_view view;
2271 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2273 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2275 intel_fill_fb_ggtt_view(&view, fb, rotation);
2277 /* Note that the w/a also requires 64 PTE of padding following the
2278 * bo. We currently fill all unused PTE with the shadow page and so
2279 * we should always have valid PTE following the scanout preventing
2282 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2283 alignment = 256 * 1024;
2286 * Global gtt pte registers are special registers which actually forward
2287 * writes to a chunk of system memory. Which means that there is no risk
2288 * that the register values disappear as soon as we call
2289 * intel_runtime_pm_put(), so it is correct to wrap only the
2290 * pin/unpin/fence and not more.
2292 intel_runtime_pm_get(dev_priv);
2294 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2299 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2300 * fence, whereas 965+ only requires a fence if using
2301 * framebuffer compression. For simplicity, we always install
2302 * a fence as the cost is not that onerous.
2304 if (view.type == I915_GGTT_VIEW_NORMAL) {
2305 ret = i915_gem_object_get_fence(obj);
2306 if (ret == -EDEADLK) {
2308 * -EDEADLK means there are no free fences
2311 * This is propagated to atomic, but it uses
2312 * -EDEADLK to force a locking recovery, so
2313 * change the returned error to -EBUSY.
2320 i915_gem_object_pin_fence(obj);
2323 intel_runtime_pm_put(dev_priv);
2327 i915_gem_object_unpin_from_display_plane(obj, &view);
2329 intel_runtime_pm_put(dev_priv);
2333 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2335 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336 struct i915_ggtt_view view;
2338 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2340 intel_fill_fb_ggtt_view(&view, fb, rotation);
2342 if (view.type == I915_GGTT_VIEW_NORMAL)
2343 i915_gem_object_unpin_fence(obj);
2345 i915_gem_object_unpin_from_display_plane(obj, &view);
2349 * Adjust the tile offset by moving the difference into
2352 * Input tile dimensions and pitch must already be
2353 * rotated to match x and y, and in pixel units.
2355 static u32 intel_adjust_tile_offset(int *x, int *y,
2356 unsigned int tile_width,
2357 unsigned int tile_height,
2358 unsigned int tile_size,
2359 unsigned int pitch_tiles,
2365 WARN_ON(old_offset & (tile_size - 1));
2366 WARN_ON(new_offset & (tile_size - 1));
2367 WARN_ON(new_offset > old_offset);
2369 tiles = (old_offset - new_offset) / tile_size;
2371 *y += tiles / pitch_tiles * tile_height;
2372 *x += tiles % pitch_tiles * tile_width;
2378 * Computes the linear offset to the base tile and adjusts
2379 * x, y. bytes per pixel is assumed to be a power-of-two.
2381 * In the 90/270 rotated case, x and y are assumed
2382 * to be already rotated to match the rotated GTT view, and
2383 * pitch is the tile_height aligned framebuffer height.
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386 const struct drm_framebuffer *fb, int plane,
2388 unsigned int rotation)
2390 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2391 uint64_t fb_modifier = fb->modifier[plane];
2392 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2393 u32 offset, offset_aligned, alignment;
2395 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2399 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2400 unsigned int tile_size, tile_width, tile_height;
2401 unsigned int tile_rows, tiles, pitch_tiles;
2403 tile_size = intel_tile_size(dev_priv);
2404 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2407 if (intel_rotation_90_or_270(rotation)) {
2408 pitch_tiles = pitch / tile_height;
2409 swap(tile_width, tile_height);
2411 pitch_tiles = pitch / (tile_width * cpp);
2414 tile_rows = *y / tile_height;
2417 tiles = *x / tile_width;
2420 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2421 offset_aligned = offset & ~alignment;
2423 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2424 tile_size, pitch_tiles,
2425 offset, offset_aligned);
2427 offset = *y * pitch + *x * cpp;
2428 offset_aligned = offset & ~alignment;
2430 *y = (offset & alignment) / pitch;
2431 *x = ((offset & alignment) - *y * pitch) / cpp;
2434 return offset_aligned;
2437 static int i9xx_format_to_fourcc(int format)
2440 case DISPPLANE_8BPP:
2441 return DRM_FORMAT_C8;
2442 case DISPPLANE_BGRX555:
2443 return DRM_FORMAT_XRGB1555;
2444 case DISPPLANE_BGRX565:
2445 return DRM_FORMAT_RGB565;
2447 case DISPPLANE_BGRX888:
2448 return DRM_FORMAT_XRGB8888;
2449 case DISPPLANE_RGBX888:
2450 return DRM_FORMAT_XBGR8888;
2451 case DISPPLANE_BGRX101010:
2452 return DRM_FORMAT_XRGB2101010;
2453 case DISPPLANE_RGBX101010:
2454 return DRM_FORMAT_XBGR2101010;
2458 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2461 case PLANE_CTL_FORMAT_RGB_565:
2462 return DRM_FORMAT_RGB565;
2464 case PLANE_CTL_FORMAT_XRGB_8888:
2467 return DRM_FORMAT_ABGR8888;
2469 return DRM_FORMAT_XBGR8888;
2472 return DRM_FORMAT_ARGB8888;
2474 return DRM_FORMAT_XRGB8888;
2476 case PLANE_CTL_FORMAT_XRGB_2101010:
2478 return DRM_FORMAT_XBGR2101010;
2480 return DRM_FORMAT_XRGB2101010;
2485 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2486 struct intel_initial_plane_config *plane_config)
2488 struct drm_device *dev = crtc->base.dev;
2489 struct drm_i915_private *dev_priv = to_i915(dev);
2490 struct drm_i915_gem_object *obj = NULL;
2491 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2492 struct drm_framebuffer *fb = &plane_config->fb->base;
2493 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2494 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2497 size_aligned -= base_aligned;
2499 if (plane_config->size == 0)
2502 /* If the FB is too big, just don't use it since fbdev is not very
2503 * important and we should probably use that space with FBC or other
2505 if (size_aligned * 2 > dev_priv->ggtt.stolen_usable_size)
2508 mutex_lock(&dev->struct_mutex);
2510 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2515 mutex_unlock(&dev->struct_mutex);
2519 obj->tiling_mode = plane_config->tiling;
2520 if (obj->tiling_mode == I915_TILING_X)
2521 obj->stride = fb->pitches[0];
2523 mode_cmd.pixel_format = fb->pixel_format;
2524 mode_cmd.width = fb->width;
2525 mode_cmd.height = fb->height;
2526 mode_cmd.pitches[0] = fb->pitches[0];
2527 mode_cmd.modifier[0] = fb->modifier[0];
2528 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2532 DRM_DEBUG_KMS("intel fb init failed\n");
2536 mutex_unlock(&dev->struct_mutex);
2538 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2542 drm_gem_object_unreference(&obj->base);
2543 mutex_unlock(&dev->struct_mutex);
2547 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 update_state_fb(struct drm_plane *plane)
2551 if (plane->fb == plane->state->fb)
2554 if (plane->state->fb)
2555 drm_framebuffer_unreference(plane->state->fb);
2556 plane->state->fb = plane->fb;
2557 if (plane->state->fb)
2558 drm_framebuffer_reference(plane->state->fb);
2562 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2563 struct intel_initial_plane_config *plane_config)
2565 struct drm_device *dev = intel_crtc->base.dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2568 struct intel_crtc *i;
2569 struct drm_i915_gem_object *obj;
2570 struct drm_plane *primary = intel_crtc->base.primary;
2571 struct drm_plane_state *plane_state = primary->state;
2572 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2573 struct intel_plane *intel_plane = to_intel_plane(primary);
2574 struct intel_plane_state *intel_state =
2575 to_intel_plane_state(plane_state);
2576 struct drm_framebuffer *fb;
2578 if (!plane_config->fb)
2581 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2582 fb = &plane_config->fb->base;
2586 kfree(plane_config->fb);
2589 * Failed to alloc the obj, check to see if we should share
2590 * an fb with another CRTC instead
2592 for_each_crtc(dev, c) {
2593 i = to_intel_crtc(c);
2595 if (c == &intel_crtc->base)
2601 fb = c->primary->fb;
2605 obj = intel_fb_obj(fb);
2606 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2607 drm_framebuffer_reference(fb);
2613 * We've failed to reconstruct the BIOS FB. Current display state
2614 * indicates that the primary plane is visible, but has a NULL FB,
2615 * which will lead to problems later if we don't fix it up. The
2616 * simplest solution is to just disable the primary plane now and
2617 * pretend the BIOS never had it enabled.
2619 to_intel_plane_state(plane_state)->visible = false;
2620 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2621 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2622 intel_plane->disable_plane(primary, &intel_crtc->base);
2627 plane_state->src_x = 0;
2628 plane_state->src_y = 0;
2629 plane_state->src_w = fb->width << 16;
2630 plane_state->src_h = fb->height << 16;
2632 plane_state->crtc_x = 0;
2633 plane_state->crtc_y = 0;
2634 plane_state->crtc_w = fb->width;
2635 plane_state->crtc_h = fb->height;
2637 intel_state->src.x1 = plane_state->src_x;
2638 intel_state->src.y1 = plane_state->src_y;
2639 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2640 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2641 intel_state->dst.x1 = plane_state->crtc_x;
2642 intel_state->dst.y1 = plane_state->crtc_y;
2643 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2644 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2646 obj = intel_fb_obj(fb);
2647 if (obj->tiling_mode != I915_TILING_NONE)
2648 dev_priv->preserve_bios_swizzle = true;
2650 drm_framebuffer_reference(fb);
2651 primary->fb = primary->state->fb = fb;
2652 primary->crtc = primary->state->crtc = &intel_crtc->base;
2653 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2654 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2657 static void i9xx_update_primary_plane(struct drm_plane *primary,
2658 const struct intel_crtc_state *crtc_state,
2659 const struct intel_plane_state *plane_state)
2661 struct drm_device *dev = primary->dev;
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2664 struct drm_framebuffer *fb = plane_state->base.fb;
2665 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2666 int plane = intel_crtc->plane;
2669 i915_reg_t reg = DSPCNTR(plane);
2670 unsigned int rotation = plane_state->base.rotation;
2671 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2672 int x = plane_state->src.x1 >> 16;
2673 int y = plane_state->src.y1 >> 16;
2675 dspcntr = DISPPLANE_GAMMA_ENABLE;
2677 dspcntr |= DISPLAY_PLANE_ENABLE;
2679 if (INTEL_INFO(dev)->gen < 4) {
2680 if (intel_crtc->pipe == PIPE_B)
2681 dspcntr |= DISPPLANE_SEL_PIPE_B;
2683 /* pipesrc and dspsize control the size that is scaled from,
2684 * which should always be the user's requested size.
2686 I915_WRITE(DSPSIZE(plane),
2687 ((crtc_state->pipe_src_h - 1) << 16) |
2688 (crtc_state->pipe_src_w - 1));
2689 I915_WRITE(DSPPOS(plane), 0);
2690 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2691 I915_WRITE(PRIMSIZE(plane),
2692 ((crtc_state->pipe_src_h - 1) << 16) |
2693 (crtc_state->pipe_src_w - 1));
2694 I915_WRITE(PRIMPOS(plane), 0);
2695 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2698 switch (fb->pixel_format) {
2700 dspcntr |= DISPPLANE_8BPP;
2702 case DRM_FORMAT_XRGB1555:
2703 dspcntr |= DISPPLANE_BGRX555;
2705 case DRM_FORMAT_RGB565:
2706 dspcntr |= DISPPLANE_BGRX565;
2708 case DRM_FORMAT_XRGB8888:
2709 dspcntr |= DISPPLANE_BGRX888;
2711 case DRM_FORMAT_XBGR8888:
2712 dspcntr |= DISPPLANE_RGBX888;
2714 case DRM_FORMAT_XRGB2101010:
2715 dspcntr |= DISPPLANE_BGRX101010;
2717 case DRM_FORMAT_XBGR2101010:
2718 dspcntr |= DISPPLANE_RGBX101010;
2724 if (INTEL_INFO(dev)->gen >= 4 &&
2725 obj->tiling_mode != I915_TILING_NONE)
2726 dspcntr |= DISPPLANE_TILED;
2729 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731 linear_offset = y * fb->pitches[0] + x * cpp;
2733 if (INTEL_INFO(dev)->gen >= 4) {
2734 intel_crtc->dspaddr_offset =
2735 intel_compute_tile_offset(&x, &y, fb, 0,
2736 fb->pitches[0], rotation);
2737 linear_offset -= intel_crtc->dspaddr_offset;
2739 intel_crtc->dspaddr_offset = linear_offset;
2742 if (rotation == BIT(DRM_ROTATE_180)) {
2743 dspcntr |= DISPPLANE_ROTATE_180;
2745 x += (crtc_state->pipe_src_w - 1);
2746 y += (crtc_state->pipe_src_h - 1);
2748 /* Finding the last pixel of the last line of the display
2749 data and adding to linear_offset*/
2751 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2752 (crtc_state->pipe_src_w - 1) * cpp;
2755 intel_crtc->adjusted_x = x;
2756 intel_crtc->adjusted_y = y;
2758 I915_WRITE(reg, dspcntr);
2760 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2761 if (INTEL_INFO(dev)->gen >= 4) {
2762 I915_WRITE(DSPSURF(plane),
2763 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2764 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2765 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2771 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2772 struct drm_crtc *crtc)
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 int plane = intel_crtc->plane;
2779 I915_WRITE(DSPCNTR(plane), 0);
2780 if (INTEL_INFO(dev_priv)->gen >= 4)
2781 I915_WRITE(DSPSURF(plane), 0);
2783 I915_WRITE(DSPADDR(plane), 0);
2784 POSTING_READ(DSPCNTR(plane));
2787 static void ironlake_update_primary_plane(struct drm_plane *primary,
2788 const struct intel_crtc_state *crtc_state,
2789 const struct intel_plane_state *plane_state)
2791 struct drm_device *dev = primary->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2794 struct drm_framebuffer *fb = plane_state->base.fb;
2795 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2796 int plane = intel_crtc->plane;
2799 i915_reg_t reg = DSPCNTR(plane);
2800 unsigned int rotation = plane_state->base.rotation;
2801 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2802 int x = plane_state->src.x1 >> 16;
2803 int y = plane_state->src.y1 >> 16;
2805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806 dspcntr |= DISPLAY_PLANE_ENABLE;
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811 switch (fb->pixel_format) {
2813 dspcntr |= DISPPLANE_8BPP;
2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
2818 case DRM_FORMAT_XRGB8888:
2819 dspcntr |= DISPPLANE_BGRX888;
2821 case DRM_FORMAT_XBGR8888:
2822 dspcntr |= DISPPLANE_RGBX888;
2824 case DRM_FORMAT_XRGB2101010:
2825 dspcntr |= DISPPLANE_BGRX101010;
2827 case DRM_FORMAT_XBGR2101010:
2828 dspcntr |= DISPPLANE_RGBX101010;
2834 if (obj->tiling_mode != I915_TILING_NONE)
2835 dspcntr |= DISPPLANE_TILED;
2837 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2838 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2840 linear_offset = y * fb->pitches[0] + x * cpp;
2841 intel_crtc->dspaddr_offset =
2842 intel_compute_tile_offset(&x, &y, fb, 0,
2843 fb->pitches[0], rotation);
2844 linear_offset -= intel_crtc->dspaddr_offset;
2845 if (rotation == BIT(DRM_ROTATE_180)) {
2846 dspcntr |= DISPPLANE_ROTATE_180;
2848 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2849 x += (crtc_state->pipe_src_w - 1);
2850 y += (crtc_state->pipe_src_h - 1);
2852 /* Finding the last pixel of the last line of the display
2853 data and adding to linear_offset*/
2855 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2856 (crtc_state->pipe_src_w - 1) * cpp;
2860 intel_crtc->adjusted_x = x;
2861 intel_crtc->adjusted_y = y;
2863 I915_WRITE(reg, dspcntr);
2865 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2866 I915_WRITE(DSPSURF(plane),
2867 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2868 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2869 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2872 I915_WRITE(DSPLINOFF(plane), linear_offset);
2877 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2878 uint64_t fb_modifier, uint32_t pixel_format)
2880 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2883 int cpp = drm_format_plane_cpp(pixel_format, 0);
2885 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2889 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2890 struct drm_i915_gem_object *obj,
2893 struct i915_ggtt_view view;
2894 struct i915_vma *vma;
2897 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2898 intel_plane->base.state->rotation);
2900 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2901 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2905 offset = vma->node.start;
2908 offset += vma->ggtt_view.params.rotated.uv_start_page *
2912 WARN_ON(upper_32_bits(offset));
2914 return lower_32_bits(offset);
2917 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 struct drm_device *dev = intel_crtc->base.dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2922 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2923 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2924 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2928 * This function detaches (aka. unbinds) unused scalers in hardware
2930 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 struct intel_crtc_scaler_state *scaler_state;
2935 scaler_state = &intel_crtc->config->scaler_state;
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use)
2940 skl_detach_scaler(intel_crtc, i);
2944 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 switch (pixel_format) {
2948 return PLANE_CTL_FORMAT_INDEXED;
2949 case DRM_FORMAT_RGB565:
2950 return PLANE_CTL_FORMAT_RGB_565;
2951 case DRM_FORMAT_XBGR8888:
2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2953 case DRM_FORMAT_XRGB8888:
2954 return PLANE_CTL_FORMAT_XRGB_8888;
2956 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2957 * to be already pre-multiplied. We need to add a knob (or a different
2958 * DRM_FORMAT) for user-space to configure that.
2960 case DRM_FORMAT_ABGR8888:
2961 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2962 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2963 case DRM_FORMAT_ARGB8888:
2964 return PLANE_CTL_FORMAT_XRGB_8888 |
2965 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966 case DRM_FORMAT_XRGB2101010:
2967 return PLANE_CTL_FORMAT_XRGB_2101010;
2968 case DRM_FORMAT_XBGR2101010:
2969 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2970 case DRM_FORMAT_YUYV:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2972 case DRM_FORMAT_YVYU:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2974 case DRM_FORMAT_UYVY:
2975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2976 case DRM_FORMAT_VYUY:
2977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979 MISSING_CASE(pixel_format);
2985 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 switch (fb_modifier) {
2988 case DRM_FORMAT_MOD_NONE:
2990 case I915_FORMAT_MOD_X_TILED:
2991 return PLANE_CTL_TILED_X;
2992 case I915_FORMAT_MOD_Y_TILED:
2993 return PLANE_CTL_TILED_Y;
2994 case I915_FORMAT_MOD_Yf_TILED:
2995 return PLANE_CTL_TILED_YF;
2997 MISSING_CASE(fb_modifier);
3003 u32 skl_plane_ctl_rotation(unsigned int rotation)
3006 case BIT(DRM_ROTATE_0):
3009 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3010 * while i915 HW rotation is clockwise, thats why this swapping.
3012 case BIT(DRM_ROTATE_90):
3013 return PLANE_CTL_ROTATE_270;
3014 case BIT(DRM_ROTATE_180):
3015 return PLANE_CTL_ROTATE_180;
3016 case BIT(DRM_ROTATE_270):
3017 return PLANE_CTL_ROTATE_90;
3019 MISSING_CASE(rotation);
3025 static void skylake_update_primary_plane(struct drm_plane *plane,
3026 const struct intel_crtc_state *crtc_state,
3027 const struct intel_plane_state *plane_state)
3029 struct drm_device *dev = plane->dev;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3032 struct drm_framebuffer *fb = plane_state->base.fb;
3033 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3034 int pipe = intel_crtc->pipe;
3035 u32 plane_ctl, stride_div, stride;
3036 u32 tile_height, plane_offset, plane_size;
3037 unsigned int rotation = plane_state->base.rotation;
3038 int x_offset, y_offset;
3040 int scaler_id = plane_state->scaler_id;
3041 int src_x = plane_state->src.x1 >> 16;
3042 int src_y = plane_state->src.y1 >> 16;
3043 int src_w = drm_rect_width(&plane_state->src) >> 16;
3044 int src_h = drm_rect_height(&plane_state->src) >> 16;
3045 int dst_x = plane_state->dst.x1;
3046 int dst_y = plane_state->dst.y1;
3047 int dst_w = drm_rect_width(&plane_state->dst);
3048 int dst_h = drm_rect_height(&plane_state->dst);
3050 plane_ctl = PLANE_CTL_ENABLE |
3051 PLANE_CTL_PIPE_GAMMA_ENABLE |
3052 PLANE_CTL_PIPE_CSC_ENABLE;
3054 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3055 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3056 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3057 plane_ctl |= skl_plane_ctl_rotation(rotation);
3059 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3063 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3065 if (intel_rotation_90_or_270(rotation)) {
3066 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3068 /* stride = Surface height in tiles */
3069 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3070 stride = DIV_ROUND_UP(fb->height, tile_height);
3071 x_offset = stride * tile_height - src_y - src_h;
3073 plane_size = (src_w - 1) << 16 | (src_h - 1);
3075 stride = fb->pitches[0] / stride_div;
3078 plane_size = (src_h - 1) << 16 | (src_w - 1);
3080 plane_offset = y_offset << 16 | x_offset;
3082 intel_crtc->adjusted_x = x_offset;
3083 intel_crtc->adjusted_y = y_offset;
3085 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3086 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3087 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3088 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3090 if (scaler_id >= 0) {
3091 uint32_t ps_ctrl = 0;
3093 WARN_ON(!dst_w || !dst_h);
3094 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3095 crtc_state->scaler_state.scalers[scaler_id].mode;
3096 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3097 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3098 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3099 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3100 I915_WRITE(PLANE_POS(pipe, 0), 0);
3102 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3105 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3107 POSTING_READ(PLANE_SURF(pipe, 0));
3110 static void skylake_disable_primary_plane(struct drm_plane *primary,
3111 struct drm_crtc *crtc)
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 int pipe = to_intel_crtc(crtc)->pipe;
3117 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3118 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3119 POSTING_READ(PLANE_SURF(pipe, 0));
3122 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3124 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3125 int x, int y, enum mode_set_atomic state)
3127 /* Support for kgdboc is disabled, this needs a major rework. */
3128 DRM_ERROR("legacy panic handler not supported any more.\n");
3133 static void intel_complete_page_flips(struct drm_device *dev)
3135 struct drm_crtc *crtc;
3137 for_each_crtc(dev, crtc) {
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 enum plane plane = intel_crtc->plane;
3141 intel_prepare_page_flip(dev, plane);
3142 intel_finish_page_flip_plane(dev, plane);
3146 static void intel_update_primary_planes(struct drm_device *dev)
3148 struct drm_crtc *crtc;
3150 for_each_crtc(dev, crtc) {
3151 struct intel_plane *plane = to_intel_plane(crtc->primary);
3152 struct intel_plane_state *plane_state;
3154 drm_modeset_lock_crtc(crtc, &plane->base);
3155 plane_state = to_intel_plane_state(plane->base.state);
3157 if (plane_state->visible)
3158 plane->update_plane(&plane->base,
3159 to_intel_crtc_state(crtc->state),
3162 drm_modeset_unlock_crtc(crtc);
3166 void intel_prepare_reset(struct drm_device *dev)
3168 /* no reset support for gen2 */
3172 /* reset doesn't touch the display */
3173 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3176 drm_modeset_lock_all(dev);
3178 * Disabling the crtcs gracefully seems nicer. Also the
3179 * g33 docs say we should at least disable all the planes.
3181 intel_display_suspend(dev);
3184 void intel_finish_reset(struct drm_device *dev)
3186 struct drm_i915_private *dev_priv = to_i915(dev);
3189 * Flips in the rings will be nuked by the reset,
3190 * so complete all pending flips so that user space
3191 * will get its events and not get stuck.
3193 intel_complete_page_flips(dev);
3195 /* no reset support for gen2 */
3199 /* reset doesn't touch the display */
3200 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3202 * Flips in the rings have been nuked by the reset,
3203 * so update the base address of all primary
3204 * planes to the the last fb to make sure we're
3205 * showing the correct fb after a reset.
3207 * FIXME: Atomic will make this obsolete since we won't schedule
3208 * CS-based flips (which might get lost in gpu resets) any more.
3210 intel_update_primary_planes(dev);
3215 * The display has been reset as well,
3216 * so need a full re-initialization.
3218 intel_runtime_pm_disable_interrupts(dev_priv);
3219 intel_runtime_pm_enable_interrupts(dev_priv);
3221 intel_modeset_init_hw(dev);
3223 spin_lock_irq(&dev_priv->irq_lock);
3224 if (dev_priv->display.hpd_irq_setup)
3225 dev_priv->display.hpd_irq_setup(dev);
3226 spin_unlock_irq(&dev_priv->irq_lock);
3228 intel_display_resume(dev);
3230 intel_hpd_init(dev_priv);
3232 drm_modeset_unlock_all(dev);
3235 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3243 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3246 spin_lock_irq(&dev->event_lock);
3247 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3248 spin_unlock_irq(&dev->event_lock);
3253 static void intel_update_pipe_config(struct intel_crtc *crtc,
3254 struct intel_crtc_state *old_crtc_state)
3256 struct drm_device *dev = crtc->base.dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_crtc_state *pipe_config =
3259 to_intel_crtc_state(crtc->base.state);
3261 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3262 crtc->base.mode = crtc->base.state->mode;
3264 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3265 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3266 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3269 intel_color_set_csc(&crtc->base);
3272 * Update pipe size and adjust fitter if needed: the reason for this is
3273 * that in compute_mode_changes we check the native mode (not the pfit
3274 * mode) to see if we can flip rather than do a full mode set. In the
3275 * fastboot case, we'll flip, but if we don't update the pipesrc and
3276 * pfit state, we'll end up with a big fb scanned out into the wrong
3280 I915_WRITE(PIPESRC(crtc->pipe),
3281 ((pipe_config->pipe_src_w - 1) << 16) |
3282 (pipe_config->pipe_src_h - 1));
3284 /* on skylake this is done by detaching scalers */
3285 if (INTEL_INFO(dev)->gen >= 9) {
3286 skl_detach_scalers(crtc);
3288 if (pipe_config->pch_pfit.enabled)
3289 skylake_pfit_enable(crtc);
3290 } else if (HAS_PCH_SPLIT(dev)) {
3291 if (pipe_config->pch_pfit.enabled)
3292 ironlake_pfit_enable(crtc);
3293 else if (old_crtc_state->pch_pfit.enabled)
3294 ironlake_pfit_disable(crtc, true);
3298 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3300 struct drm_device *dev = crtc->dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3303 int pipe = intel_crtc->pipe;
3307 /* enable normal train */
3308 reg = FDI_TX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 if (IS_IVYBRIDGE(dev)) {
3311 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3312 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3314 temp &= ~FDI_LINK_TRAIN_NONE;
3315 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3317 I915_WRITE(reg, temp);
3319 reg = FDI_RX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 if (HAS_PCH_CPT(dev)) {
3322 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3323 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3325 temp &= ~FDI_LINK_TRAIN_NONE;
3326 temp |= FDI_LINK_TRAIN_NONE;
3328 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3330 /* wait one idle pattern time */
3334 /* IVB wants error correction enabled */
3335 if (IS_IVYBRIDGE(dev))
3336 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3337 FDI_FE_ERRC_ENABLE);
3340 /* The FDI link training functions for ILK/Ibexpeak. */
3341 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3343 struct drm_device *dev = crtc->dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346 int pipe = intel_crtc->pipe;
3350 /* FDI needs bits from pipe first */
3351 assert_pipe_enabled(dev_priv, pipe);
3353 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3355 reg = FDI_RX_IMR(pipe);
3356 temp = I915_READ(reg);
3357 temp &= ~FDI_RX_SYMBOL_LOCK;
3358 temp &= ~FDI_RX_BIT_LOCK;
3359 I915_WRITE(reg, temp);
3363 /* enable CPU FDI TX and PCH FDI RX */
3364 reg = FDI_TX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3367 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3368 temp &= ~FDI_LINK_TRAIN_NONE;
3369 temp |= FDI_LINK_TRAIN_PATTERN_1;
3370 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3372 reg = FDI_RX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 temp &= ~FDI_LINK_TRAIN_NONE;
3375 temp |= FDI_LINK_TRAIN_PATTERN_1;
3376 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3381 /* Ironlake workaround, enable clock pointer after FDI enable*/
3382 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3383 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3384 FDI_RX_PHASE_SYNC_POINTER_EN);
3386 reg = FDI_RX_IIR(pipe);
3387 for (tries = 0; tries < 5; tries++) {
3388 temp = I915_READ(reg);
3389 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391 if ((temp & FDI_RX_BIT_LOCK)) {
3392 DRM_DEBUG_KMS("FDI train 1 done.\n");
3393 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3398 DRM_ERROR("FDI train 1 fail!\n");
3401 reg = FDI_TX_CTL(pipe);
3402 temp = I915_READ(reg);
3403 temp &= ~FDI_LINK_TRAIN_NONE;
3404 temp |= FDI_LINK_TRAIN_PATTERN_2;
3405 I915_WRITE(reg, temp);
3407 reg = FDI_RX_CTL(pipe);
3408 temp = I915_READ(reg);
3409 temp &= ~FDI_LINK_TRAIN_NONE;
3410 temp |= FDI_LINK_TRAIN_PATTERN_2;
3411 I915_WRITE(reg, temp);
3416 reg = FDI_RX_IIR(pipe);
3417 for (tries = 0; tries < 5; tries++) {
3418 temp = I915_READ(reg);
3419 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421 if (temp & FDI_RX_SYMBOL_LOCK) {
3422 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3423 DRM_DEBUG_KMS("FDI train 2 done.\n");
3428 DRM_ERROR("FDI train 2 fail!\n");
3430 DRM_DEBUG_KMS("FDI train done\n");
3434 static const int snb_b_fdi_train_param[] = {
3435 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3436 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3437 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3438 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3441 /* The FDI link training functions for SNB/Cougarpoint. */
3442 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3444 struct drm_device *dev = crtc->dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447 int pipe = intel_crtc->pipe;
3451 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453 reg = FDI_RX_IMR(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_RX_SYMBOL_LOCK;
3456 temp &= ~FDI_RX_BIT_LOCK;
3457 I915_WRITE(reg, temp);
3462 /* enable CPU FDI TX and PCH FDI RX */
3463 reg = FDI_TX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_1;
3469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3472 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3474 I915_WRITE(FDI_RX_MISC(pipe),
3475 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3477 reg = FDI_RX_CTL(pipe);
3478 temp = I915_READ(reg);
3479 if (HAS_PCH_CPT(dev)) {
3480 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483 temp &= ~FDI_LINK_TRAIN_NONE;
3484 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3491 for (i = 0; i < 4; i++) {
3492 reg = FDI_TX_CTL(pipe);
3493 temp = I915_READ(reg);
3494 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3495 temp |= snb_b_fdi_train_param[i];
3496 I915_WRITE(reg, temp);
3501 for (retry = 0; retry < 5; retry++) {
3502 reg = FDI_RX_IIR(pipe);
3503 temp = I915_READ(reg);
3504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3505 if (temp & FDI_RX_BIT_LOCK) {
3506 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3507 DRM_DEBUG_KMS("FDI train 1 done.\n");
3516 DRM_ERROR("FDI train 1 fail!\n");
3519 reg = FDI_TX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_LINK_TRAIN_NONE;
3522 temp |= FDI_LINK_TRAIN_PATTERN_2;
3524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3528 I915_WRITE(reg, temp);
3530 reg = FDI_RX_CTL(pipe);
3531 temp = I915_READ(reg);
3532 if (HAS_PCH_CPT(dev)) {
3533 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3534 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3536 temp &= ~FDI_LINK_TRAIN_NONE;
3537 temp |= FDI_LINK_TRAIN_PATTERN_2;
3539 I915_WRITE(reg, temp);
3544 for (i = 0; i < 4; i++) {
3545 reg = FDI_TX_CTL(pipe);
3546 temp = I915_READ(reg);
3547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548 temp |= snb_b_fdi_train_param[i];
3549 I915_WRITE(reg, temp);
3554 for (retry = 0; retry < 5; retry++) {
3555 reg = FDI_RX_IIR(pipe);
3556 temp = I915_READ(reg);
3557 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3558 if (temp & FDI_RX_SYMBOL_LOCK) {
3559 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3560 DRM_DEBUG_KMS("FDI train 2 done.\n");
3569 DRM_ERROR("FDI train 2 fail!\n");
3571 DRM_DEBUG_KMS("FDI train done.\n");
3574 /* Manual link training for Ivy Bridge A0 parts */
3575 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3577 struct drm_device *dev = crtc->dev;
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580 int pipe = intel_crtc->pipe;
3584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3586 reg = FDI_RX_IMR(pipe);
3587 temp = I915_READ(reg);
3588 temp &= ~FDI_RX_SYMBOL_LOCK;
3589 temp &= ~FDI_RX_BIT_LOCK;
3590 I915_WRITE(reg, temp);
3595 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3596 I915_READ(FDI_RX_IIR(pipe)));
3598 /* Try each vswing and preemphasis setting twice before moving on */
3599 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3600 /* disable first in case we need to retry */
3601 reg = FDI_TX_CTL(pipe);
3602 temp = I915_READ(reg);
3603 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3604 temp &= ~FDI_TX_ENABLE;
3605 I915_WRITE(reg, temp);
3607 reg = FDI_RX_CTL(pipe);
3608 temp = I915_READ(reg);
3609 temp &= ~FDI_LINK_TRAIN_AUTO;
3610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3611 temp &= ~FDI_RX_ENABLE;
3612 I915_WRITE(reg, temp);
3614 /* enable CPU FDI TX and PCH FDI RX */
3615 reg = FDI_TX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3618 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3619 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3621 temp |= snb_b_fdi_train_param[j/2];
3622 temp |= FDI_COMPOSITE_SYNC;
3623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3625 I915_WRITE(FDI_RX_MISC(pipe),
3626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3628 reg = FDI_RX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3631 temp |= FDI_COMPOSITE_SYNC;
3632 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3635 udelay(1); /* should be 0.5us */
3637 for (i = 0; i < 4; i++) {
3638 reg = FDI_RX_IIR(pipe);
3639 temp = I915_READ(reg);
3640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3642 if (temp & FDI_RX_BIT_LOCK ||
3643 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3644 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3645 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3649 udelay(1); /* should be 0.5us */
3652 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3657 reg = FDI_TX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3660 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3661 I915_WRITE(reg, temp);
3663 reg = FDI_RX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3666 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3667 I915_WRITE(reg, temp);
3670 udelay(2); /* should be 1.5us */
3672 for (i = 0; i < 4; i++) {
3673 reg = FDI_RX_IIR(pipe);
3674 temp = I915_READ(reg);
3675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677 if (temp & FDI_RX_SYMBOL_LOCK ||
3678 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3679 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3680 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3684 udelay(2); /* should be 1.5us */
3687 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3691 DRM_DEBUG_KMS("FDI train done.\n");
3694 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3696 struct drm_device *dev = intel_crtc->base.dev;
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698 int pipe = intel_crtc->pipe;
3702 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3703 reg = FDI_RX_CTL(pipe);
3704 temp = I915_READ(reg);
3705 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3706 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3707 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3708 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3713 /* Switch from Rawclk to PCDclk */
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp | FDI_PCDCLK);
3720 /* Enable CPU FDI TX PLL, always on for Ironlake */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3724 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3731 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3733 struct drm_device *dev = intel_crtc->base.dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 int pipe = intel_crtc->pipe;
3739 /* Switch from PCDclk to Rawclk */
3740 reg = FDI_RX_CTL(pipe);
3741 temp = I915_READ(reg);
3742 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3744 /* Disable CPU FDI TX PLL */
3745 reg = FDI_TX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3752 reg = FDI_RX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3756 /* Wait for the clocks to turn off. */
3761 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3763 struct drm_device *dev = crtc->dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766 int pipe = intel_crtc->pipe;
3770 /* disable CPU FDI tx and PCH FDI rx */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3776 reg = FDI_RX_CTL(pipe);
3777 temp = I915_READ(reg);
3778 temp &= ~(0x7 << 16);
3779 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3780 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3785 /* Ironlake workaround, disable clock pointer after downing FDI */
3786 if (HAS_PCH_IBX(dev))
3787 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3789 /* still set train pattern 1 */
3790 reg = FDI_TX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~FDI_LINK_TRAIN_NONE;
3793 temp |= FDI_LINK_TRAIN_PATTERN_1;
3794 I915_WRITE(reg, temp);
3796 reg = FDI_RX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 if (HAS_PCH_CPT(dev)) {
3799 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3800 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3802 temp &= ~FDI_LINK_TRAIN_NONE;
3803 temp |= FDI_LINK_TRAIN_PATTERN_1;
3805 /* BPC in FDI rx is consistent with that in PIPECONF */
3806 temp &= ~(0x07 << 16);
3807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3808 I915_WRITE(reg, temp);
3814 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3816 struct intel_crtc *crtc;
3818 /* Note that we don't need to be called with mode_config.lock here
3819 * as our list of CRTC objects is static for the lifetime of the
3820 * device and so cannot disappear as we iterate. Similarly, we can
3821 * happily treat the predicates as racy, atomic checks as userspace
3822 * cannot claim and pin a new fb without at least acquring the
3823 * struct_mutex and so serialising with us.
3825 for_each_intel_crtc(dev, crtc) {
3826 if (atomic_read(&crtc->unpin_work_count) == 0)
3829 if (crtc->unpin_work)
3830 intel_wait_for_vblank(dev, crtc->pipe);
3838 static void page_flip_completed(struct intel_crtc *intel_crtc)
3840 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3841 struct intel_unpin_work *work = intel_crtc->unpin_work;
3843 /* ensure that the unpin work is consistent wrt ->pending. */
3845 intel_crtc->unpin_work = NULL;
3848 drm_send_vblank_event(intel_crtc->base.dev,
3852 drm_crtc_vblank_put(&intel_crtc->base);
3854 wake_up_all(&dev_priv->pending_flip_queue);
3855 queue_work(dev_priv->wq, &work->work);
3857 trace_i915_flip_complete(intel_crtc->plane,
3858 work->pending_flip_obj);
3861 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3863 struct drm_device *dev = crtc->dev;
3864 struct drm_i915_private *dev_priv = dev->dev_private;
3867 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3869 ret = wait_event_interruptible_timeout(
3870 dev_priv->pending_flip_queue,
3871 !intel_crtc_has_pending_flip(crtc),
3878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880 spin_lock_irq(&dev->event_lock);
3881 if (intel_crtc->unpin_work) {
3882 WARN_ONCE(1, "Removing stuck page flip\n");
3883 page_flip_completed(intel_crtc);
3885 spin_unlock_irq(&dev->event_lock);
3891 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3895 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3897 mutex_lock(&dev_priv->sb_lock);
3899 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3900 temp |= SBI_SSCCTL_DISABLE;
3901 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3903 mutex_unlock(&dev_priv->sb_lock);
3906 /* Program iCLKIP clock to the desired frequency */
3907 static void lpt_program_iclkip(struct drm_crtc *crtc)
3909 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3910 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3911 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3914 lpt_disable_iclkip(dev_priv);
3916 /* The iCLK virtual clock root frequency is in MHz,
3917 * but the adjusted_mode->crtc_clock in in KHz. To get the
3918 * divisors, it is necessary to divide one by another, so we
3919 * convert the virtual clock precision to KHz here for higher
3922 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3923 u32 iclk_virtual_root_freq = 172800 * 1000;
3924 u32 iclk_pi_range = 64;
3925 u32 desired_divisor;
3927 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3929 divsel = (desired_divisor / iclk_pi_range) - 2;
3930 phaseinc = desired_divisor % iclk_pi_range;
3933 * Near 20MHz is a corner case which is
3934 * out of range for the 7-bit divisor
3940 /* This should not happen with any sane values */
3941 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3942 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3943 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3944 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3946 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3953 mutex_lock(&dev_priv->sb_lock);
3955 /* Program SSCDIVINTPHASE6 */
3956 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3957 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3958 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3959 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3960 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3961 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3962 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3963 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3965 /* Program SSCAUXDIV */
3966 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3967 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3968 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3969 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3971 /* Enable modulator and associated divider */
3972 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3973 temp &= ~SBI_SSCCTL_DISABLE;
3974 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3976 mutex_unlock(&dev_priv->sb_lock);
3978 /* Wait for initialization time */
3981 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3984 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3986 u32 divsel, phaseinc, auxdiv;
3987 u32 iclk_virtual_root_freq = 172800 * 1000;
3988 u32 iclk_pi_range = 64;
3989 u32 desired_divisor;
3992 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3995 mutex_lock(&dev_priv->sb_lock);
3997 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3998 if (temp & SBI_SSCCTL_DISABLE) {
3999 mutex_unlock(&dev_priv->sb_lock);
4003 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4004 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4005 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4006 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4007 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4009 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4010 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4011 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4013 mutex_unlock(&dev_priv->sb_lock);
4015 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4017 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4018 desired_divisor << auxdiv);
4021 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4022 enum pipe pch_transcoder)
4024 struct drm_device *dev = crtc->base.dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4029 I915_READ(HTOTAL(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4031 I915_READ(HBLANK(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4033 I915_READ(HSYNC(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4036 I915_READ(VTOTAL(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4038 I915_READ(VBLANK(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4040 I915_READ(VSYNC(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4042 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4045 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 struct drm_i915_private *dev_priv = dev->dev_private;
4050 temp = I915_READ(SOUTH_CHICKEN1);
4051 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4054 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 temp |= FDI_BC_BIFURCATION_SELECT;
4061 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4062 I915_WRITE(SOUTH_CHICKEN1, temp);
4063 POSTING_READ(SOUTH_CHICKEN1);
4066 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 struct drm_device *dev = intel_crtc->base.dev;
4070 switch (intel_crtc->pipe) {
4074 if (intel_crtc->config->fdi_lanes > 2)
4075 cpt_set_fdi_bc_bifurcation(dev, false);
4077 cpt_set_fdi_bc_bifurcation(dev, true);
4081 cpt_set_fdi_bc_bifurcation(dev, true);
4089 /* Return which DP Port should be selected for Transcoder DP control */
4091 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4093 struct drm_device *dev = crtc->dev;
4094 struct intel_encoder *encoder;
4096 for_each_encoder_on_crtc(dev, crtc, encoder) {
4097 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4098 encoder->type == INTEL_OUTPUT_EDP)
4099 return enc_to_dig_port(&encoder->base)->port;
4106 * Enable PCH resources required for PCH ports:
4108 * - FDI training & RX/TX
4109 * - update transcoder timings
4110 * - DP transcoding bits
4113 static void ironlake_pch_enable(struct drm_crtc *crtc)
4115 struct drm_device *dev = crtc->dev;
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4118 int pipe = intel_crtc->pipe;
4121 assert_pch_transcoder_disabled(dev_priv, pipe);
4123 if (IS_IVYBRIDGE(dev))
4124 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4126 /* Write the TU size bits before fdi link training, so that error
4127 * detection works. */
4128 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4129 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4132 * Sometimes spurious CPU pipe underruns happen during FDI
4133 * training, at least with VGA+HDMI cloning. Suppress them.
4135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4137 /* For PCH output, training FDI link */
4138 dev_priv->display.fdi_link_train(crtc);
4140 /* We need to program the right clock selection before writing the pixel
4141 * mutliplier into the DPLL. */
4142 if (HAS_PCH_CPT(dev)) {
4145 temp = I915_READ(PCH_DPLL_SEL);
4146 temp |= TRANS_DPLL_ENABLE(pipe);
4147 sel = TRANS_DPLLB_SEL(pipe);
4148 if (intel_crtc->config->shared_dpll ==
4149 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4153 I915_WRITE(PCH_DPLL_SEL, temp);
4156 /* XXX: pch pll's can be enabled any time before we enable the PCH
4157 * transcoder, and we actually should do this to not upset any PCH
4158 * transcoder that already use the clock when we share it.
4160 * Note that enable_shared_dpll tries to do the right thing, but
4161 * get_shared_dpll unconditionally resets the pll - we need that to have
4162 * the right LVDS enable sequence. */
4163 intel_enable_shared_dpll(intel_crtc);
4165 /* set transcoder timing, panel must allow it */
4166 assert_panel_unlocked(dev_priv, pipe);
4167 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4169 intel_fdi_normal_train(crtc);
4171 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173 /* For PCH DP, enable TRANS_DP_CTL */
4174 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4175 const struct drm_display_mode *adjusted_mode =
4176 &intel_crtc->config->base.adjusted_mode;
4177 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4178 i915_reg_t reg = TRANS_DP_CTL(pipe);
4179 temp = I915_READ(reg);
4180 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4181 TRANS_DP_SYNC_MASK |
4183 temp |= TRANS_DP_OUTPUT_ENABLE;
4184 temp |= bpc << 9; /* same format but at 11:9 */
4186 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4187 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4188 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4189 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191 switch (intel_trans_dp_port_sel(crtc)) {
4193 temp |= TRANS_DP_PORT_SEL_B;
4196 temp |= TRANS_DP_PORT_SEL_C;
4199 temp |= TRANS_DP_PORT_SEL_D;
4205 I915_WRITE(reg, temp);
4208 ironlake_enable_pch_transcoder(dev_priv, pipe);
4211 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220 lpt_program_iclkip(crtc);
4222 /* Set transcoder timing. */
4223 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4228 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4230 struct drm_i915_private *dev_priv = dev->dev_private;
4231 i915_reg_t dslreg = PIPEDSL(pipe);
4234 temp = I915_READ(dslreg);
4236 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4237 if (wait_for(I915_READ(dslreg) != temp, 5))
4238 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4243 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4244 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4245 int src_w, int src_h, int dst_w, int dst_h)
4247 struct intel_crtc_scaler_state *scaler_state =
4248 &crtc_state->scaler_state;
4249 struct intel_crtc *intel_crtc =
4250 to_intel_crtc(crtc_state->base.crtc);
4253 need_scaling = intel_rotation_90_or_270(rotation) ?
4254 (src_h != dst_w || src_w != dst_h):
4255 (src_w != dst_w || src_h != dst_h);
4258 * if plane is being disabled or scaler is no more required or force detach
4259 * - free scaler binded to this plane/crtc
4260 * - in order to do this, update crtc->scaler_usage
4262 * Here scaler state in crtc_state is set free so that
4263 * scaler can be assigned to other user. Actual register
4264 * update to free the scaler is done in plane/panel-fit programming.
4265 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4267 if (force_detach || !need_scaling) {
4268 if (*scaler_id >= 0) {
4269 scaler_state->scaler_users &= ~(1 << scaler_user);
4270 scaler_state->scalers[*scaler_id].in_use = 0;
4272 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4273 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4274 intel_crtc->pipe, scaler_user, *scaler_id,
4275 scaler_state->scaler_users);
4282 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4283 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4285 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4286 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4287 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4288 "size is out of scaler range\n",
4289 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4293 /* mark this plane as a scaler user in crtc_state */
4294 scaler_state->scaler_users |= (1 << scaler_user);
4295 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4296 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4297 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4298 scaler_state->scaler_users);
4304 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4306 * @state: crtc's scaler state
4309 * 0 - scaler_usage updated successfully
4310 * error - requested scaling cannot be supported or other error condition
4312 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4314 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4315 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4317 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4318 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4320 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4321 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4322 state->pipe_src_w, state->pipe_src_h,
4323 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4327 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4329 * @state: crtc's scaler state
4330 * @plane_state: atomic plane state to update
4333 * 0 - scaler_usage updated successfully
4334 * error - requested scaling cannot be supported or other error condition
4336 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4337 struct intel_plane_state *plane_state)
4340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4341 struct intel_plane *intel_plane =
4342 to_intel_plane(plane_state->base.plane);
4343 struct drm_framebuffer *fb = plane_state->base.fb;
4346 bool force_detach = !fb || !plane_state->visible;
4348 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4349 intel_plane->base.base.id, intel_crtc->pipe,
4350 drm_plane_index(&intel_plane->base));
4352 ret = skl_update_scaler(crtc_state, force_detach,
4353 drm_plane_index(&intel_plane->base),
4354 &plane_state->scaler_id,
4355 plane_state->base.rotation,
4356 drm_rect_width(&plane_state->src) >> 16,
4357 drm_rect_height(&plane_state->src) >> 16,
4358 drm_rect_width(&plane_state->dst),
4359 drm_rect_height(&plane_state->dst));
4361 if (ret || plane_state->scaler_id < 0)
4364 /* check colorkey */
4365 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4366 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4367 intel_plane->base.base.id);
4371 /* Check src format */
4372 switch (fb->pixel_format) {
4373 case DRM_FORMAT_RGB565:
4374 case DRM_FORMAT_XBGR8888:
4375 case DRM_FORMAT_XRGB8888:
4376 case DRM_FORMAT_ABGR8888:
4377 case DRM_FORMAT_ARGB8888:
4378 case DRM_FORMAT_XRGB2101010:
4379 case DRM_FORMAT_XBGR2101010:
4380 case DRM_FORMAT_YUYV:
4381 case DRM_FORMAT_YVYU:
4382 case DRM_FORMAT_UYVY:
4383 case DRM_FORMAT_VYUY:
4386 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4387 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4394 static void skylake_scaler_disable(struct intel_crtc *crtc)
4398 for (i = 0; i < crtc->num_scalers; i++)
4399 skl_detach_scaler(crtc, i);
4402 static void skylake_pfit_enable(struct intel_crtc *crtc)
4404 struct drm_device *dev = crtc->base.dev;
4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406 int pipe = crtc->pipe;
4407 struct intel_crtc_scaler_state *scaler_state =
4408 &crtc->config->scaler_state;
4410 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4412 if (crtc->config->pch_pfit.enabled) {
4415 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4416 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4420 id = scaler_state->scaler_id;
4421 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4422 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4423 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4424 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4426 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4430 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4432 struct drm_device *dev = crtc->base.dev;
4433 struct drm_i915_private *dev_priv = dev->dev_private;
4434 int pipe = crtc->pipe;
4436 if (crtc->config->pch_pfit.enabled) {
4437 /* Force use of hard-coded filter coefficients
4438 * as some pre-programmed values are broken,
4441 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4442 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4443 PF_PIPE_SEL_IVB(pipe));
4445 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4446 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4447 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4451 void hsw_enable_ips(struct intel_crtc *crtc)
4453 struct drm_device *dev = crtc->base.dev;
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4456 if (!crtc->config->ips_enabled)
4459 /* We can only enable IPS after we enable a plane and wait for a vblank */
4460 intel_wait_for_vblank(dev, crtc->pipe);
4462 assert_plane_enabled(dev_priv, crtc->plane);
4463 if (IS_BROADWELL(dev)) {
4464 mutex_lock(&dev_priv->rps.hw_lock);
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4466 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* Quoting Art Runyan: "its not safe to expect any particular
4468 * value in IPS_CTL bit 31 after enabling IPS through the
4469 * mailbox." Moreover, the mailbox may return a bogus state,
4470 * so we need to just enable it and continue on.
4473 I915_WRITE(IPS_CTL, IPS_ENABLE);
4474 /* The bit only becomes 1 in the next vblank, so this wait here
4475 * is essentially intel_wait_for_vblank. If we don't have this
4476 * and don't wait for vblanks until the end of crtc_enable, then
4477 * the HW state readout code will complain that the expected
4478 * IPS_CTL value is not the one we read. */
4479 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4480 DRM_ERROR("Timed out waiting for IPS enable\n");
4484 void hsw_disable_ips(struct intel_crtc *crtc)
4486 struct drm_device *dev = crtc->base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4489 if (!crtc->config->ips_enabled)
4492 assert_plane_enabled(dev_priv, crtc->plane);
4493 if (IS_BROADWELL(dev)) {
4494 mutex_lock(&dev_priv->rps.hw_lock);
4495 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4496 mutex_unlock(&dev_priv->rps.hw_lock);
4497 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4498 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4499 DRM_ERROR("Timed out waiting for IPS disable\n");
4501 I915_WRITE(IPS_CTL, 0);
4502 POSTING_READ(IPS_CTL);
4505 /* We need to wait for a vblank before we can disable the plane. */
4506 intel_wait_for_vblank(dev, crtc->pipe);
4509 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4511 if (intel_crtc->overlay) {
4512 struct drm_device *dev = intel_crtc->base.dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4515 mutex_lock(&dev->struct_mutex);
4516 dev_priv->mm.interruptible = false;
4517 (void) intel_overlay_switch_off(intel_crtc->overlay);
4518 dev_priv->mm.interruptible = true;
4519 mutex_unlock(&dev->struct_mutex);
4522 /* Let userspace switch the overlay on again. In most cases userspace
4523 * has to recompute where to put it anyway.
4528 * intel_post_enable_primary - Perform operations after enabling primary plane
4529 * @crtc: the CRTC whose primary plane was just enabled
4531 * Performs potentially sleeping operations that must be done after the primary
4532 * plane is enabled, such as updating FBC and IPS. Note that this may be
4533 * called due to an explicit primary plane update, or due to an implicit
4534 * re-enable that is caused when a sprite plane is updated to no longer
4535 * completely hide the primary plane.
4538 intel_post_enable_primary(struct drm_crtc *crtc)
4540 struct drm_device *dev = crtc->dev;
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4543 int pipe = intel_crtc->pipe;
4546 * FIXME IPS should be fine as long as one plane is
4547 * enabled, but in practice it seems to have problems
4548 * when going from primary only to sprite only and vice
4551 hsw_enable_ips(intel_crtc);
4554 * Gen2 reports pipe underruns whenever all planes are disabled.
4555 * So don't enable underrun reporting before at least some planes
4557 * FIXME: Need to fix the logic to work when we turn off all planes
4558 * but leave the pipe running.
4561 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4563 /* Underruns don't always raise interrupts, so check manually. */
4564 intel_check_cpu_fifo_underruns(dev_priv);
4565 intel_check_pch_fifo_underruns(dev_priv);
4568 /* FIXME move all this to pre_plane_update() with proper state tracking */
4570 intel_pre_disable_primary(struct drm_crtc *crtc)
4572 struct drm_device *dev = crtc->dev;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4575 int pipe = intel_crtc->pipe;
4578 * Gen2 reports pipe underruns whenever all planes are disabled.
4579 * So diasble underrun reporting before all the planes get disabled.
4580 * FIXME: Need to fix the logic to work when we turn off all planes
4581 * but leave the pipe running.
4584 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4587 * FIXME IPS should be fine as long as one plane is
4588 * enabled, but in practice it seems to have problems
4589 * when going from primary only to sprite only and vice
4592 hsw_disable_ips(intel_crtc);
4595 /* FIXME get rid of this and use pre_plane_update */
4597 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4599 struct drm_device *dev = crtc->dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4602 int pipe = intel_crtc->pipe;
4604 intel_pre_disable_primary(crtc);
4607 * Vblank time updates from the shadow to live plane control register
4608 * are blocked if the memory self-refresh mode is active at that
4609 * moment. So to make sure the plane gets truly disabled, disable
4610 * first the self-refresh mode. The self-refresh enable bit in turn
4611 * will be checked/applied by the HW only at the next frame start
4612 * event which is after the vblank start event, so we need to have a
4613 * wait-for-vblank between disabling the plane and the pipe.
4615 if (HAS_GMCH_DISPLAY(dev)) {
4616 intel_set_memory_cxsr(dev_priv, false);
4617 dev_priv->wm.vlv.cxsr = false;
4618 intel_wait_for_vblank(dev, pipe);
4622 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4624 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4625 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4626 struct intel_crtc_state *pipe_config =
4627 to_intel_crtc_state(crtc->base.state);
4628 struct drm_device *dev = crtc->base.dev;
4629 struct drm_plane *primary = crtc->base.primary;
4630 struct drm_plane_state *old_pri_state =
4631 drm_atomic_get_existing_plane_state(old_state, primary);
4633 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4635 crtc->wm.cxsr_allowed = true;
4637 if (pipe_config->update_wm_post && pipe_config->base.active)
4638 intel_update_watermarks(&crtc->base);
4640 if (old_pri_state) {
4641 struct intel_plane_state *primary_state =
4642 to_intel_plane_state(primary->state);
4643 struct intel_plane_state *old_primary_state =
4644 to_intel_plane_state(old_pri_state);
4646 intel_fbc_post_update(crtc);
4648 if (primary_state->visible &&
4649 (needs_modeset(&pipe_config->base) ||
4650 !old_primary_state->visible))
4651 intel_post_enable_primary(&crtc->base);
4655 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4657 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4658 struct drm_device *dev = crtc->base.dev;
4659 struct drm_i915_private *dev_priv = dev->dev_private;
4660 struct intel_crtc_state *pipe_config =
4661 to_intel_crtc_state(crtc->base.state);
4662 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4663 struct drm_plane *primary = crtc->base.primary;
4664 struct drm_plane_state *old_pri_state =
4665 drm_atomic_get_existing_plane_state(old_state, primary);
4666 bool modeset = needs_modeset(&pipe_config->base);
4668 if (old_pri_state) {
4669 struct intel_plane_state *primary_state =
4670 to_intel_plane_state(primary->state);
4671 struct intel_plane_state *old_primary_state =
4672 to_intel_plane_state(old_pri_state);
4674 intel_fbc_pre_update(crtc);
4676 if (old_primary_state->visible &&
4677 (modeset || !primary_state->visible))
4678 intel_pre_disable_primary(&crtc->base);
4681 if (pipe_config->disable_cxsr) {
4682 crtc->wm.cxsr_allowed = false;
4685 * Vblank time updates from the shadow to live plane control register
4686 * are blocked if the memory self-refresh mode is active at that
4687 * moment. So to make sure the plane gets truly disabled, disable
4688 * first the self-refresh mode. The self-refresh enable bit in turn
4689 * will be checked/applied by the HW only at the next frame start
4690 * event which is after the vblank start event, so we need to have a
4691 * wait-for-vblank between disabling the plane and the pipe.
4693 if (old_crtc_state->base.active) {
4694 intel_set_memory_cxsr(dev_priv, false);
4695 dev_priv->wm.vlv.cxsr = false;
4696 intel_wait_for_vblank(dev, crtc->pipe);
4701 * IVB workaround: must disable low power watermarks for at least
4702 * one frame before enabling scaling. LP watermarks can be re-enabled
4703 * when scaling is disabled.
4705 * WaCxSRDisabledForSpriteScaling:ivb
4707 if (pipe_config->disable_lp_wm) {
4708 ilk_disable_lp_wm(dev);
4709 intel_wait_for_vblank(dev, crtc->pipe);
4713 * If we're doing a modeset, we're done. No need to do any pre-vblank
4714 * watermark programming here.
4716 if (needs_modeset(&pipe_config->base))
4720 * For platforms that support atomic watermarks, program the
4721 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4722 * will be the intermediate values that are safe for both pre- and
4723 * post- vblank; when vblank happens, the 'active' values will be set
4724 * to the final 'target' values and we'll do this again to get the
4725 * optimal watermarks. For gen9+ platforms, the values we program here
4726 * will be the final target values which will get automatically latched
4727 * at vblank time; no further programming will be necessary.
4729 * If a platform hasn't been transitioned to atomic watermarks yet,
4730 * we'll continue to update watermarks the old way, if flags tell
4733 if (dev_priv->display.initial_watermarks != NULL)
4734 dev_priv->display.initial_watermarks(pipe_config);
4735 else if (pipe_config->update_wm_pre)
4736 intel_update_watermarks(&crtc->base);
4739 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4741 struct drm_device *dev = crtc->dev;
4742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743 struct drm_plane *p;
4744 int pipe = intel_crtc->pipe;
4746 intel_crtc_dpms_overlay_disable(intel_crtc);
4748 drm_for_each_plane_mask(p, dev, plane_mask)
4749 to_intel_plane(p)->disable_plane(p, crtc);
4752 * FIXME: Once we grow proper nuclear flip support out of this we need
4753 * to compute the mask of flip planes precisely. For the time being
4754 * consider this a flip to a NULL plane.
4756 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4759 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4761 struct drm_device *dev = crtc->dev;
4762 struct drm_i915_private *dev_priv = dev->dev_private;
4763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4764 struct intel_encoder *encoder;
4765 int pipe = intel_crtc->pipe;
4767 if (WARN_ON(intel_crtc->active))
4770 if (intel_crtc->config->has_pch_encoder)
4771 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4773 if (intel_crtc->config->has_pch_encoder)
4774 intel_prepare_shared_dpll(intel_crtc);
4776 if (intel_crtc->config->has_dp_encoder)
4777 intel_dp_set_m_n(intel_crtc, M1_N1);
4779 intel_set_pipe_timings(intel_crtc);
4780 intel_set_pipe_src_size(intel_crtc);
4782 if (intel_crtc->config->has_pch_encoder) {
4783 intel_cpu_transcoder_set_m_n(intel_crtc,
4784 &intel_crtc->config->fdi_m_n, NULL);
4787 ironlake_set_pipeconf(crtc);
4789 intel_crtc->active = true;
4791 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4793 for_each_encoder_on_crtc(dev, crtc, encoder)
4794 if (encoder->pre_enable)
4795 encoder->pre_enable(encoder);
4797 if (intel_crtc->config->has_pch_encoder) {
4798 /* Note: FDI PLL enabling _must_ be done before we enable the
4799 * cpu pipes, hence this is separate from all the other fdi/pch
4801 ironlake_fdi_pll_enable(intel_crtc);
4803 assert_fdi_tx_disabled(dev_priv, pipe);
4804 assert_fdi_rx_disabled(dev_priv, pipe);
4807 ironlake_pfit_enable(intel_crtc);
4810 * On ILK+ LUT must be loaded before the pipe is running but with
4813 intel_color_load_luts(crtc);
4815 if (dev_priv->display.initial_watermarks != NULL)
4816 dev_priv->display.initial_watermarks(intel_crtc->config);
4817 intel_enable_pipe(intel_crtc);
4819 if (intel_crtc->config->has_pch_encoder)
4820 ironlake_pch_enable(crtc);
4822 assert_vblank_disabled(crtc);
4823 drm_crtc_vblank_on(crtc);
4825 for_each_encoder_on_crtc(dev, crtc, encoder)
4826 encoder->enable(encoder);
4828 if (HAS_PCH_CPT(dev))
4829 cpt_verify_modeset(dev, intel_crtc->pipe);
4831 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4832 if (intel_crtc->config->has_pch_encoder)
4833 intel_wait_for_vblank(dev, pipe);
4834 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4837 /* IPS only exists on ULT machines and is tied to pipe A. */
4838 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4840 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4843 static void haswell_crtc_enable(struct drm_crtc *crtc)
4845 struct drm_device *dev = crtc->dev;
4846 struct drm_i915_private *dev_priv = dev->dev_private;
4847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848 struct intel_encoder *encoder;
4849 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4850 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4851 struct intel_crtc_state *pipe_config =
4852 to_intel_crtc_state(crtc->state);
4854 if (WARN_ON(intel_crtc->active))
4857 if (intel_crtc->config->has_pch_encoder)
4858 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4861 if (intel_crtc->config->shared_dpll)
4862 intel_enable_shared_dpll(intel_crtc);
4864 if (intel_crtc->config->has_dp_encoder)
4865 intel_dp_set_m_n(intel_crtc, M1_N1);
4867 if (!intel_crtc->config->has_dsi_encoder)
4868 intel_set_pipe_timings(intel_crtc);
4870 intel_set_pipe_src_size(intel_crtc);
4872 if (cpu_transcoder != TRANSCODER_EDP &&
4873 !transcoder_is_dsi(cpu_transcoder)) {
4874 I915_WRITE(PIPE_MULT(cpu_transcoder),
4875 intel_crtc->config->pixel_multiplier - 1);
4878 if (intel_crtc->config->has_pch_encoder) {
4879 intel_cpu_transcoder_set_m_n(intel_crtc,
4880 &intel_crtc->config->fdi_m_n, NULL);
4883 if (!intel_crtc->config->has_dsi_encoder)
4884 haswell_set_pipeconf(crtc);
4886 haswell_set_pipemisc(crtc);
4888 intel_color_set_csc(crtc);
4890 intel_crtc->active = true;
4892 if (intel_crtc->config->has_pch_encoder)
4893 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4895 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4897 for_each_encoder_on_crtc(dev, crtc, encoder) {
4898 if (encoder->pre_enable)
4899 encoder->pre_enable(encoder);
4902 if (intel_crtc->config->has_pch_encoder)
4903 dev_priv->display.fdi_link_train(crtc);
4905 if (!intel_crtc->config->has_dsi_encoder)
4906 intel_ddi_enable_pipe_clock(intel_crtc);
4908 if (INTEL_INFO(dev)->gen >= 9)
4909 skylake_pfit_enable(intel_crtc);
4911 ironlake_pfit_enable(intel_crtc);
4914 * On ILK+ LUT must be loaded before the pipe is running but with
4917 intel_color_load_luts(crtc);
4919 intel_ddi_set_pipe_settings(crtc);
4920 if (!intel_crtc->config->has_dsi_encoder)
4921 intel_ddi_enable_transcoder_func(crtc);
4923 if (dev_priv->display.initial_watermarks != NULL)
4924 dev_priv->display.initial_watermarks(pipe_config);
4926 intel_update_watermarks(crtc);
4928 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4929 if (!intel_crtc->config->has_dsi_encoder)
4930 intel_enable_pipe(intel_crtc);
4932 if (intel_crtc->config->has_pch_encoder)
4933 lpt_pch_enable(crtc);
4935 if (intel_crtc->config->dp_encoder_is_mst)
4936 intel_ddi_set_vc_payload_alloc(crtc, true);
4938 assert_vblank_disabled(crtc);
4939 drm_crtc_vblank_on(crtc);
4941 for_each_encoder_on_crtc(dev, crtc, encoder) {
4942 encoder->enable(encoder);
4943 intel_opregion_notify_encoder(encoder, true);
4946 if (intel_crtc->config->has_pch_encoder) {
4947 intel_wait_for_vblank(dev, pipe);
4948 intel_wait_for_vblank(dev, pipe);
4949 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4950 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4954 /* If we change the relative order between pipe/planes enabling, we need
4955 * to change the workaround. */
4956 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4957 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4958 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4959 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4963 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4965 struct drm_device *dev = crtc->base.dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 int pipe = crtc->pipe;
4969 /* To avoid upsetting the power well on haswell only disable the pfit if
4970 * it's in use. The hw state code will make sure we get this right. */
4971 if (force || crtc->config->pch_pfit.enabled) {
4972 I915_WRITE(PF_CTL(pipe), 0);
4973 I915_WRITE(PF_WIN_POS(pipe), 0);
4974 I915_WRITE(PF_WIN_SZ(pipe), 0);
4978 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4980 struct drm_device *dev = crtc->dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983 struct intel_encoder *encoder;
4984 int pipe = intel_crtc->pipe;
4986 if (intel_crtc->config->has_pch_encoder)
4987 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4989 for_each_encoder_on_crtc(dev, crtc, encoder)
4990 encoder->disable(encoder);
4992 drm_crtc_vblank_off(crtc);
4993 assert_vblank_disabled(crtc);
4996 * Sometimes spurious CPU pipe underruns happen when the
4997 * pipe is already disabled, but FDI RX/TX is still enabled.
4998 * Happens at least with VGA+HDMI cloning. Suppress them.
5000 if (intel_crtc->config->has_pch_encoder)
5001 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5003 intel_disable_pipe(intel_crtc);
5005 ironlake_pfit_disable(intel_crtc, false);
5007 if (intel_crtc->config->has_pch_encoder) {
5008 ironlake_fdi_disable(crtc);
5009 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5012 for_each_encoder_on_crtc(dev, crtc, encoder)
5013 if (encoder->post_disable)
5014 encoder->post_disable(encoder);
5016 if (intel_crtc->config->has_pch_encoder) {
5017 ironlake_disable_pch_transcoder(dev_priv, pipe);
5019 if (HAS_PCH_CPT(dev)) {
5023 /* disable TRANS_DP_CTL */
5024 reg = TRANS_DP_CTL(pipe);
5025 temp = I915_READ(reg);
5026 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5027 TRANS_DP_PORT_SEL_MASK);
5028 temp |= TRANS_DP_PORT_SEL_NONE;
5029 I915_WRITE(reg, temp);
5031 /* disable DPLL_SEL */
5032 temp = I915_READ(PCH_DPLL_SEL);
5033 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5034 I915_WRITE(PCH_DPLL_SEL, temp);
5037 ironlake_fdi_pll_disable(intel_crtc);
5040 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5043 static void haswell_crtc_disable(struct drm_crtc *crtc)
5045 struct drm_device *dev = crtc->dev;
5046 struct drm_i915_private *dev_priv = dev->dev_private;
5047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048 struct intel_encoder *encoder;
5049 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5051 if (intel_crtc->config->has_pch_encoder)
5052 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5055 for_each_encoder_on_crtc(dev, crtc, encoder) {
5056 intel_opregion_notify_encoder(encoder, false);
5057 encoder->disable(encoder);
5060 drm_crtc_vblank_off(crtc);
5061 assert_vblank_disabled(crtc);
5063 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5064 if (!intel_crtc->config->has_dsi_encoder)
5065 intel_disable_pipe(intel_crtc);
5067 if (intel_crtc->config->dp_encoder_is_mst)
5068 intel_ddi_set_vc_payload_alloc(crtc, false);
5070 if (!intel_crtc->config->has_dsi_encoder)
5071 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5073 if (INTEL_INFO(dev)->gen >= 9)
5074 skylake_scaler_disable(intel_crtc);
5076 ironlake_pfit_disable(intel_crtc, false);
5078 if (!intel_crtc->config->has_dsi_encoder)
5079 intel_ddi_disable_pipe_clock(intel_crtc);
5081 for_each_encoder_on_crtc(dev, crtc, encoder)
5082 if (encoder->post_disable)
5083 encoder->post_disable(encoder);
5085 if (intel_crtc->config->has_pch_encoder) {
5086 lpt_disable_pch_transcoder(dev_priv);
5087 lpt_disable_iclkip(dev_priv);
5088 intel_ddi_fdi_disable(crtc);
5090 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5095 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5097 struct drm_device *dev = crtc->base.dev;
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct intel_crtc_state *pipe_config = crtc->config;
5101 if (!pipe_config->gmch_pfit.control)
5105 * The panel fitter should only be adjusted whilst the pipe is disabled,
5106 * according to register description and PRM.
5108 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5109 assert_pipe_disabled(dev_priv, crtc->pipe);
5111 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5112 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5114 /* Border color in case we don't scale up to the full screen. Black by
5115 * default, change to something else for debugging. */
5116 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5119 static enum intel_display_power_domain port_to_power_domain(enum port port)
5123 return POWER_DOMAIN_PORT_DDI_A_LANES;
5125 return POWER_DOMAIN_PORT_DDI_B_LANES;
5127 return POWER_DOMAIN_PORT_DDI_C_LANES;
5129 return POWER_DOMAIN_PORT_DDI_D_LANES;
5131 return POWER_DOMAIN_PORT_DDI_E_LANES;
5134 return POWER_DOMAIN_PORT_OTHER;
5138 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5142 return POWER_DOMAIN_AUX_A;
5144 return POWER_DOMAIN_AUX_B;
5146 return POWER_DOMAIN_AUX_C;
5148 return POWER_DOMAIN_AUX_D;
5150 /* FIXME: Check VBT for actual wiring of PORT E */
5151 return POWER_DOMAIN_AUX_D;
5154 return POWER_DOMAIN_AUX_A;
5158 enum intel_display_power_domain
5159 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5161 struct drm_device *dev = intel_encoder->base.dev;
5162 struct intel_digital_port *intel_dig_port;
5164 switch (intel_encoder->type) {
5165 case INTEL_OUTPUT_UNKNOWN:
5166 /* Only DDI platforms should ever use this output type */
5167 WARN_ON_ONCE(!HAS_DDI(dev));
5168 case INTEL_OUTPUT_DISPLAYPORT:
5169 case INTEL_OUTPUT_HDMI:
5170 case INTEL_OUTPUT_EDP:
5171 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5172 return port_to_power_domain(intel_dig_port->port);
5173 case INTEL_OUTPUT_DP_MST:
5174 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5175 return port_to_power_domain(intel_dig_port->port);
5176 case INTEL_OUTPUT_ANALOG:
5177 return POWER_DOMAIN_PORT_CRT;
5178 case INTEL_OUTPUT_DSI:
5179 return POWER_DOMAIN_PORT_DSI;
5181 return POWER_DOMAIN_PORT_OTHER;
5185 enum intel_display_power_domain
5186 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5188 struct drm_device *dev = intel_encoder->base.dev;
5189 struct intel_digital_port *intel_dig_port;
5191 switch (intel_encoder->type) {
5192 case INTEL_OUTPUT_UNKNOWN:
5193 case INTEL_OUTPUT_HDMI:
5195 * Only DDI platforms should ever use these output types.
5196 * We can get here after the HDMI detect code has already set
5197 * the type of the shared encoder. Since we can't be sure
5198 * what's the status of the given connectors, play safe and
5199 * run the DP detection too.
5201 WARN_ON_ONCE(!HAS_DDI(dev));
5202 case INTEL_OUTPUT_DISPLAYPORT:
5203 case INTEL_OUTPUT_EDP:
5204 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5205 return port_to_aux_power_domain(intel_dig_port->port);
5206 case INTEL_OUTPUT_DP_MST:
5207 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5208 return port_to_aux_power_domain(intel_dig_port->port);
5210 MISSING_CASE(intel_encoder->type);
5211 return POWER_DOMAIN_AUX_A;
5215 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5216 struct intel_crtc_state *crtc_state)
5218 struct drm_device *dev = crtc->dev;
5219 struct drm_encoder *encoder;
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221 enum pipe pipe = intel_crtc->pipe;
5223 enum transcoder transcoder = crtc_state->cpu_transcoder;
5225 if (!crtc_state->base.active)
5228 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5229 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5230 if (crtc_state->pch_pfit.enabled ||
5231 crtc_state->pch_pfit.force_thru)
5232 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5234 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5235 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5237 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5240 if (crtc_state->shared_dpll)
5241 mask |= BIT(POWER_DOMAIN_PLLS);
5246 static unsigned long
5247 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5248 struct intel_crtc_state *crtc_state)
5250 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5252 enum intel_display_power_domain domain;
5253 unsigned long domains, new_domains, old_domains;
5255 old_domains = intel_crtc->enabled_power_domains;
5256 intel_crtc->enabled_power_domains = new_domains =
5257 get_crtc_power_domains(crtc, crtc_state);
5259 domains = new_domains & ~old_domains;
5261 for_each_power_domain(domain, domains)
5262 intel_display_power_get(dev_priv, domain);
5264 return old_domains & ~new_domains;
5267 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5268 unsigned long domains)
5270 enum intel_display_power_domain domain;
5272 for_each_power_domain(domain, domains)
5273 intel_display_power_put(dev_priv, domain);
5276 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5278 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5280 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5281 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5282 return max_cdclk_freq;
5283 else if (IS_CHERRYVIEW(dev_priv))
5284 return max_cdclk_freq*95/100;
5285 else if (INTEL_INFO(dev_priv)->gen < 4)
5286 return 2*max_cdclk_freq*90/100;
5288 return max_cdclk_freq*90/100;
5291 static void intel_update_max_cdclk(struct drm_device *dev)
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5295 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5296 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5298 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5299 dev_priv->max_cdclk_freq = 675000;
5300 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5301 dev_priv->max_cdclk_freq = 540000;
5302 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5303 dev_priv->max_cdclk_freq = 450000;
5305 dev_priv->max_cdclk_freq = 337500;
5306 } else if (IS_BROADWELL(dev)) {
5308 * FIXME with extra cooling we can allow
5309 * 540 MHz for ULX and 675 Mhz for ULT.
5310 * How can we know if extra cooling is
5311 * available? PCI ID, VTB, something else?
5313 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5314 dev_priv->max_cdclk_freq = 450000;
5315 else if (IS_BDW_ULX(dev))
5316 dev_priv->max_cdclk_freq = 450000;
5317 else if (IS_BDW_ULT(dev))
5318 dev_priv->max_cdclk_freq = 540000;
5320 dev_priv->max_cdclk_freq = 675000;
5321 } else if (IS_CHERRYVIEW(dev)) {
5322 dev_priv->max_cdclk_freq = 320000;
5323 } else if (IS_VALLEYVIEW(dev)) {
5324 dev_priv->max_cdclk_freq = 400000;
5326 /* otherwise assume cdclk is fixed */
5327 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5330 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5332 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5333 dev_priv->max_cdclk_freq);
5335 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5336 dev_priv->max_dotclk_freq);
5339 static void intel_update_cdclk(struct drm_device *dev)
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5343 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5345 dev_priv->cdclk_freq);
5348 * Program the gmbus_freq based on the cdclk frequency.
5349 * BSpec erroneously claims we should aim for 4MHz, but
5350 * in fact 1MHz is the correct frequency.
5352 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5354 * Program the gmbus_freq based on the cdclk frequency.
5355 * BSpec erroneously claims we should aim for 4MHz, but
5356 * in fact 1MHz is the correct frequency.
5358 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5361 if (dev_priv->max_cdclk_freq == 0)
5362 intel_update_max_cdclk(dev);
5365 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t current_freq;
5373 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5374 switch (frequency) {
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5377 ratio = BXT_DE_PLL_RATIO(60);
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5381 ratio = BXT_DE_PLL_RATIO(60);
5384 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5385 ratio = BXT_DE_PLL_RATIO(60);
5388 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5389 ratio = BXT_DE_PLL_RATIO(60);
5392 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393 ratio = BXT_DE_PLL_RATIO(65);
5397 * Bypass frequency with DE PLL disabled. Init ratio, divider
5398 * to suppress GCC warning.
5404 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5409 mutex_lock(&dev_priv->rps.hw_lock);
5410 /* Inform power controller of upcoming frequency change */
5411 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5413 mutex_unlock(&dev_priv->rps.hw_lock);
5416 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5421 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5422 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5423 current_freq = current_freq * 500 + 1000;
5426 * DE PLL has to be disabled when
5427 * - setting to 19.2MHz (bypass, PLL isn't used)
5428 * - before setting to 624MHz (PLL needs toggling)
5429 * - before setting to any frequency from 624MHz (PLL needs toggling)
5431 if (frequency == 19200 || frequency == 624000 ||
5432 current_freq == 624000) {
5433 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5435 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5437 DRM_ERROR("timout waiting for DE PLL unlock\n");
5440 if (frequency != 19200) {
5443 val = I915_READ(BXT_DE_PLL_CTL);
5444 val &= ~BXT_DE_PLL_RATIO_MASK;
5446 I915_WRITE(BXT_DE_PLL_CTL, val);
5448 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5450 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5451 DRM_ERROR("timeout waiting for DE PLL lock\n");
5453 val = I915_READ(CDCLK_CTL);
5454 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5457 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5460 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461 if (frequency >= 500000)
5462 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5464 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5465 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5466 val |= (frequency - 1000) / 500;
5467 I915_WRITE(CDCLK_CTL, val);
5470 mutex_lock(&dev_priv->rps.hw_lock);
5471 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5472 DIV_ROUND_UP(frequency, 25000));
5473 mutex_unlock(&dev_priv->rps.hw_lock);
5476 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5481 intel_update_cdclk(dev);
5484 void broxton_init_cdclk(struct drm_device *dev)
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5490 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5491 * or else the reset will hang because there is no PCH to respond.
5492 * Move the handshake programming to initialization sequence.
5493 * Previously was left up to BIOS.
5495 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5496 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5497 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5499 /* Enable PG1 for cdclk */
5500 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5502 /* check if cd clock is enabled */
5503 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5504 DRM_DEBUG_KMS("Display already initialized\n");
5510 * - The initial CDCLK needs to be read from VBT.
5511 * Need to make this change after VBT has changes for BXT.
5512 * - check if setting the max (or any) cdclk freq is really necessary
5513 * here, it belongs to modeset time
5515 broxton_set_cdclk(dev, 624000);
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5518 POSTING_READ(DBUF_CTL);
5522 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5523 DRM_ERROR("DBuf power enable timeout!\n");
5526 void broxton_uninit_cdclk(struct drm_device *dev)
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5530 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5531 POSTING_READ(DBUF_CTL);
5535 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5536 DRM_ERROR("DBuf power disable timeout!\n");
5538 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5539 broxton_set_cdclk(dev, 19200);
5541 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5544 static const struct skl_cdclk_entry {
5547 } skl_cdclk_frequencies[] = {
5548 { .freq = 308570, .vco = 8640 },
5549 { .freq = 337500, .vco = 8100 },
5550 { .freq = 432000, .vco = 8640 },
5551 { .freq = 450000, .vco = 8100 },
5552 { .freq = 540000, .vco = 8100 },
5553 { .freq = 617140, .vco = 8640 },
5554 { .freq = 675000, .vco = 8100 },
5557 static unsigned int skl_cdclk_decimal(unsigned int freq)
5559 return (freq - 1000) / 500;
5562 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5566 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5567 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5569 if (e->freq == freq)
5577 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5579 unsigned int min_freq;
5582 /* select the minimum CDCLK before enabling DPLL 0 */
5583 val = I915_READ(CDCLK_CTL);
5584 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5585 val |= CDCLK_FREQ_337_308;
5587 if (required_vco == 8640)
5592 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5594 I915_WRITE(CDCLK_CTL, val);
5595 POSTING_READ(CDCLK_CTL);
5598 * We always enable DPLL0 with the lowest link rate possible, but still
5599 * taking into account the VCO required to operate the eDP panel at the
5600 * desired frequency. The usual DP link rates operate with a VCO of
5601 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5602 * The modeset code is responsible for the selection of the exact link
5603 * rate later on, with the constraint of choosing a frequency that
5604 * works with required_vco.
5606 val = I915_READ(DPLL_CTRL1);
5608 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5609 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5610 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5611 if (required_vco == 8640)
5612 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5615 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5618 I915_WRITE(DPLL_CTRL1, val);
5619 POSTING_READ(DPLL_CTRL1);
5621 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5623 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5624 DRM_ERROR("DPLL0 not locked\n");
5627 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5632 /* inform PCU we want to change CDCLK */
5633 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5634 mutex_lock(&dev_priv->rps.hw_lock);
5635 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5636 mutex_unlock(&dev_priv->rps.hw_lock);
5638 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5641 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5645 for (i = 0; i < 15; i++) {
5646 if (skl_cdclk_pcu_ready(dev_priv))
5654 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5656 struct drm_device *dev = dev_priv->dev;
5657 u32 freq_select, pcu_ack;
5659 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5661 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5662 DRM_ERROR("failed to inform PCU about cdclk change\n");
5670 freq_select = CDCLK_FREQ_450_432;
5674 freq_select = CDCLK_FREQ_540;
5680 freq_select = CDCLK_FREQ_337_308;
5685 freq_select = CDCLK_FREQ_675_617;
5690 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5691 POSTING_READ(CDCLK_CTL);
5693 /* inform PCU of the change */
5694 mutex_lock(&dev_priv->rps.hw_lock);
5695 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5696 mutex_unlock(&dev_priv->rps.hw_lock);
5698 intel_update_cdclk(dev);
5701 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5703 /* disable DBUF power */
5704 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5705 POSTING_READ(DBUF_CTL);
5709 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5710 DRM_ERROR("DBuf power disable timeout\n");
5713 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5714 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5715 DRM_ERROR("Couldn't disable DPLL0\n");
5718 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5720 unsigned int required_vco;
5722 /* DPLL0 not enabled (happens on early BIOS versions) */
5723 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5725 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5726 skl_dpll0_enable(dev_priv, required_vco);
5729 /* set CDCLK to the frequency the BIOS chose */
5730 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5732 /* enable DBUF power */
5733 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5734 POSTING_READ(DBUF_CTL);
5738 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5739 DRM_ERROR("DBuf power enable timeout\n");
5742 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5744 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5745 uint32_t cdctl = I915_READ(CDCLK_CTL);
5746 int freq = dev_priv->skl_boot_cdclk;
5749 * check if the pre-os intialized the display
5750 * There is SWF18 scratchpad register defined which is set by the
5751 * pre-os which can be used by the OS drivers to check the status
5753 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5756 /* Is PLL enabled and locked ? */
5757 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5760 /* DPLL okay; verify the cdclock
5762 * Noticed in some instances that the freq selection is correct but
5763 * decimal part is programmed wrong from BIOS where pre-os does not
5764 * enable display. Verify the same as well.
5766 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5767 /* All well; nothing to sanitize */
5771 * As of now initialize with max cdclk till
5772 * we get dynamic cdclk support
5774 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5775 skl_init_cdclk(dev_priv);
5777 /* we did have to sanitize */
5781 /* Adjust CDclk dividers to allow high res or save power if possible */
5782 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5787 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5788 != dev_priv->cdclk_freq);
5790 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5792 else if (cdclk == 266667)
5797 mutex_lock(&dev_priv->rps.hw_lock);
5798 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5799 val &= ~DSPFREQGUAR_MASK;
5800 val |= (cmd << DSPFREQGUAR_SHIFT);
5801 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5802 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5803 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5805 DRM_ERROR("timed out waiting for CDclk change\n");
5807 mutex_unlock(&dev_priv->rps.hw_lock);
5809 mutex_lock(&dev_priv->sb_lock);
5811 if (cdclk == 400000) {
5814 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5816 /* adjust cdclk divider */
5817 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5818 val &= ~CCK_FREQUENCY_VALUES;
5820 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5822 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5823 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5825 DRM_ERROR("timed out waiting for CDclk change\n");
5828 /* adjust self-refresh exit latency value */
5829 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5833 * For high bandwidth configs, we set a higher latency in the bunit
5834 * so that the core display fetch happens in time to avoid underruns.
5836 if (cdclk == 400000)
5837 val |= 4500 / 250; /* 4.5 usec */
5839 val |= 3000 / 250; /* 3.0 usec */
5840 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5842 mutex_unlock(&dev_priv->sb_lock);
5844 intel_update_cdclk(dev);
5847 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5852 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5853 != dev_priv->cdclk_freq);
5862 MISSING_CASE(cdclk);
5867 * Specs are full of misinformation, but testing on actual
5868 * hardware has shown that we just need to write the desired
5869 * CCK divider into the Punit register.
5871 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5873 mutex_lock(&dev_priv->rps.hw_lock);
5874 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5875 val &= ~DSPFREQGUAR_MASK_CHV;
5876 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5877 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5878 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5879 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5881 DRM_ERROR("timed out waiting for CDclk change\n");
5883 mutex_unlock(&dev_priv->rps.hw_lock);
5885 intel_update_cdclk(dev);
5888 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5891 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5892 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5895 * Really only a few cases to deal with, as only 4 CDclks are supported:
5898 * 320/333MHz (depends on HPLL freq)
5900 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5901 * of the lower bin and adjust if needed.
5903 * We seem to get an unstable or solid color picture at 200MHz.
5904 * Not sure what's wrong. For now use 200MHz only when all pipes
5907 if (!IS_CHERRYVIEW(dev_priv) &&
5908 max_pixclk > freq_320*limit/100)
5910 else if (max_pixclk > 266667*limit/100)
5912 else if (max_pixclk > 0)
5918 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5923 * - remove the guardband, it's not needed on BXT
5924 * - set 19.2MHz bypass frequency if there are no active pipes
5926 if (max_pixclk > 576000*9/10)
5928 else if (max_pixclk > 384000*9/10)
5930 else if (max_pixclk > 288000*9/10)
5932 else if (max_pixclk > 144000*9/10)
5938 /* Compute the max pixel clock for new configuration. */
5939 static int intel_mode_max_pixclk(struct drm_device *dev,
5940 struct drm_atomic_state *state)
5942 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5943 struct drm_i915_private *dev_priv = dev->dev_private;
5944 struct drm_crtc *crtc;
5945 struct drm_crtc_state *crtc_state;
5946 unsigned max_pixclk = 0, i;
5949 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5950 sizeof(intel_state->min_pixclk));
5952 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5955 if (crtc_state->enable)
5956 pixclk = crtc_state->adjusted_mode.crtc_clock;
5958 intel_state->min_pixclk[i] = pixclk;
5961 for_each_pipe(dev_priv, pipe)
5962 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5967 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5969 struct drm_device *dev = state->dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971 int max_pixclk = intel_mode_max_pixclk(dev, state);
5972 struct intel_atomic_state *intel_state =
5973 to_intel_atomic_state(state);
5978 intel_state->cdclk = intel_state->dev_cdclk =
5979 valleyview_calc_cdclk(dev_priv, max_pixclk);
5981 if (!intel_state->active_crtcs)
5982 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5987 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5989 struct drm_device *dev = state->dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 int max_pixclk = intel_mode_max_pixclk(dev, state);
5992 struct intel_atomic_state *intel_state =
5993 to_intel_atomic_state(state);
5998 intel_state->cdclk = intel_state->dev_cdclk =
5999 broxton_calc_cdclk(dev_priv, max_pixclk);
6001 if (!intel_state->active_crtcs)
6002 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6007 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6009 unsigned int credits, default_credits;
6011 if (IS_CHERRYVIEW(dev_priv))
6012 default_credits = PFI_CREDIT(12);
6014 default_credits = PFI_CREDIT(8);
6016 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6017 /* CHV suggested value is 31 or 63 */
6018 if (IS_CHERRYVIEW(dev_priv))
6019 credits = PFI_CREDIT_63;
6021 credits = PFI_CREDIT(15);
6023 credits = default_credits;
6027 * WA - write default credits before re-programming
6028 * FIXME: should we also set the resend bit here?
6030 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6033 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6034 credits | PFI_CREDIT_RESEND);
6037 * FIXME is this guaranteed to clear
6038 * immediately or should we poll for it?
6040 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6043 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6045 struct drm_device *dev = old_state->dev;
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6047 struct intel_atomic_state *old_intel_state =
6048 to_intel_atomic_state(old_state);
6049 unsigned req_cdclk = old_intel_state->dev_cdclk;
6052 * FIXME: We can end up here with all power domains off, yet
6053 * with a CDCLK frequency other than the minimum. To account
6054 * for this take the PIPE-A power domain, which covers the HW
6055 * blocks needed for the following programming. This can be
6056 * removed once it's guaranteed that we get here either with
6057 * the minimum CDCLK set, or the required power domains
6060 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6062 if (IS_CHERRYVIEW(dev))
6063 cherryview_set_cdclk(dev, req_cdclk);
6065 valleyview_set_cdclk(dev, req_cdclk);
6067 vlv_program_pfi_credits(dev_priv);
6069 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6072 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6074 struct drm_device *dev = crtc->dev;
6075 struct drm_i915_private *dev_priv = to_i915(dev);
6076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6077 struct intel_encoder *encoder;
6078 int pipe = intel_crtc->pipe;
6080 if (WARN_ON(intel_crtc->active))
6083 if (intel_crtc->config->has_dp_encoder)
6084 intel_dp_set_m_n(intel_crtc, M1_N1);
6086 intel_set_pipe_timings(intel_crtc);
6087 intel_set_pipe_src_size(intel_crtc);
6089 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6090 struct drm_i915_private *dev_priv = dev->dev_private;
6092 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6093 I915_WRITE(CHV_CANVAS(pipe), 0);
6096 i9xx_set_pipeconf(intel_crtc);
6098 intel_crtc->active = true;
6100 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6102 for_each_encoder_on_crtc(dev, crtc, encoder)
6103 if (encoder->pre_pll_enable)
6104 encoder->pre_pll_enable(encoder);
6106 if (!intel_crtc->config->has_dsi_encoder) {
6107 if (IS_CHERRYVIEW(dev)) {
6108 chv_prepare_pll(intel_crtc, intel_crtc->config);
6109 chv_enable_pll(intel_crtc, intel_crtc->config);
6111 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6112 vlv_enable_pll(intel_crtc, intel_crtc->config);
6116 for_each_encoder_on_crtc(dev, crtc, encoder)
6117 if (encoder->pre_enable)
6118 encoder->pre_enable(encoder);
6120 i9xx_pfit_enable(intel_crtc);
6122 intel_color_load_luts(crtc);
6124 intel_update_watermarks(crtc);
6125 intel_enable_pipe(intel_crtc);
6127 assert_vblank_disabled(crtc);
6128 drm_crtc_vblank_on(crtc);
6130 for_each_encoder_on_crtc(dev, crtc, encoder)
6131 encoder->enable(encoder);
6134 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6136 struct drm_device *dev = crtc->base.dev;
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6139 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6140 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6143 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6145 struct drm_device *dev = crtc->dev;
6146 struct drm_i915_private *dev_priv = to_i915(dev);
6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148 struct intel_encoder *encoder;
6149 int pipe = intel_crtc->pipe;
6151 if (WARN_ON(intel_crtc->active))
6154 i9xx_set_pll_dividers(intel_crtc);
6156 if (intel_crtc->config->has_dp_encoder)
6157 intel_dp_set_m_n(intel_crtc, M1_N1);
6159 intel_set_pipe_timings(intel_crtc);
6160 intel_set_pipe_src_size(intel_crtc);
6162 i9xx_set_pipeconf(intel_crtc);
6164 intel_crtc->active = true;
6167 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6169 for_each_encoder_on_crtc(dev, crtc, encoder)
6170 if (encoder->pre_enable)
6171 encoder->pre_enable(encoder);
6173 i9xx_enable_pll(intel_crtc);
6175 i9xx_pfit_enable(intel_crtc);
6177 intel_color_load_luts(crtc);
6179 intel_update_watermarks(crtc);
6180 intel_enable_pipe(intel_crtc);
6182 assert_vblank_disabled(crtc);
6183 drm_crtc_vblank_on(crtc);
6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 encoder->enable(encoder);
6189 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6191 struct drm_device *dev = crtc->base.dev;
6192 struct drm_i915_private *dev_priv = dev->dev_private;
6194 if (!crtc->config->gmch_pfit.control)
6197 assert_pipe_disabled(dev_priv, crtc->pipe);
6199 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6200 I915_READ(PFIT_CONTROL));
6201 I915_WRITE(PFIT_CONTROL, 0);
6204 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6206 struct drm_device *dev = crtc->dev;
6207 struct drm_i915_private *dev_priv = dev->dev_private;
6208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209 struct intel_encoder *encoder;
6210 int pipe = intel_crtc->pipe;
6213 * On gen2 planes are double buffered but the pipe isn't, so we must
6214 * wait for planes to fully turn off before disabling the pipe.
6215 * We also need to wait on all gmch platforms because of the
6216 * self-refresh mode constraint explained above.
6218 intel_wait_for_vblank(dev, pipe);
6220 for_each_encoder_on_crtc(dev, crtc, encoder)
6221 encoder->disable(encoder);
6223 drm_crtc_vblank_off(crtc);
6224 assert_vblank_disabled(crtc);
6226 intel_disable_pipe(intel_crtc);
6228 i9xx_pfit_disable(intel_crtc);
6230 for_each_encoder_on_crtc(dev, crtc, encoder)
6231 if (encoder->post_disable)
6232 encoder->post_disable(encoder);
6234 if (!intel_crtc->config->has_dsi_encoder) {
6235 if (IS_CHERRYVIEW(dev))
6236 chv_disable_pll(dev_priv, pipe);
6237 else if (IS_VALLEYVIEW(dev))
6238 vlv_disable_pll(dev_priv, pipe);
6240 i9xx_disable_pll(intel_crtc);
6243 for_each_encoder_on_crtc(dev, crtc, encoder)
6244 if (encoder->post_pll_disable)
6245 encoder->post_pll_disable(encoder);
6248 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6251 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6253 struct intel_encoder *encoder;
6254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6256 enum intel_display_power_domain domain;
6257 unsigned long domains;
6259 if (!intel_crtc->active)
6262 if (to_intel_plane_state(crtc->primary->state)->visible) {
6263 WARN_ON(intel_crtc->unpin_work);
6265 intel_pre_disable_primary_noatomic(crtc);
6267 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6268 to_intel_plane_state(crtc->primary->state)->visible = false;
6271 dev_priv->display.crtc_disable(crtc);
6273 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6276 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6277 crtc->state->active = false;
6278 intel_crtc->active = false;
6279 crtc->enabled = false;
6280 crtc->state->connector_mask = 0;
6281 crtc->state->encoder_mask = 0;
6283 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6284 encoder->base.crtc = NULL;
6286 intel_fbc_disable(intel_crtc);
6287 intel_update_watermarks(crtc);
6288 intel_disable_shared_dpll(intel_crtc);
6290 domains = intel_crtc->enabled_power_domains;
6291 for_each_power_domain(domain, domains)
6292 intel_display_power_put(dev_priv, domain);
6293 intel_crtc->enabled_power_domains = 0;
6295 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6296 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6300 * turn all crtc's off, but do not adjust state
6301 * This has to be paired with a call to intel_modeset_setup_hw_state.
6303 int intel_display_suspend(struct drm_device *dev)
6305 struct drm_i915_private *dev_priv = to_i915(dev);
6306 struct drm_atomic_state *state;
6309 state = drm_atomic_helper_suspend(dev);
6310 ret = PTR_ERR_OR_ZERO(state);
6312 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6314 dev_priv->modeset_restore_state = state;
6318 void intel_encoder_destroy(struct drm_encoder *encoder)
6320 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6322 drm_encoder_cleanup(encoder);
6323 kfree(intel_encoder);
6326 /* Cross check the actual hw state with our own modeset state tracking (and it's
6327 * internal consistency). */
6328 static void intel_connector_check_state(struct intel_connector *connector)
6330 struct drm_crtc *crtc = connector->base.state->crtc;
6332 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6333 connector->base.base.id,
6334 connector->base.name);
6336 if (connector->get_hw_state(connector)) {
6337 struct intel_encoder *encoder = connector->encoder;
6338 struct drm_connector_state *conn_state = connector->base.state;
6340 I915_STATE_WARN(!crtc,
6341 "connector enabled without attached crtc\n");
6346 I915_STATE_WARN(!crtc->state->active,
6347 "connector is active, but attached crtc isn't\n");
6349 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6352 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6353 "atomic encoder doesn't match attached encoder\n");
6355 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6356 "attached encoder crtc differs from connector crtc\n");
6358 I915_STATE_WARN(crtc && crtc->state->active,
6359 "attached crtc is active, but connector isn't\n");
6360 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6361 "best encoder set without crtc!\n");
6365 int intel_connector_init(struct intel_connector *connector)
6367 drm_atomic_helper_connector_reset(&connector->base);
6369 if (!connector->base.state)
6375 struct intel_connector *intel_connector_alloc(void)
6377 struct intel_connector *connector;
6379 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6383 if (intel_connector_init(connector) < 0) {
6391 /* Simple connector->get_hw_state implementation for encoders that support only
6392 * one connector and no cloning and hence the encoder state determines the state
6393 * of the connector. */
6394 bool intel_connector_get_hw_state(struct intel_connector *connector)
6397 struct intel_encoder *encoder = connector->encoder;
6399 return encoder->get_hw_state(encoder, &pipe);
6402 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6404 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6405 return crtc_state->fdi_lanes;
6410 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6411 struct intel_crtc_state *pipe_config)
6413 struct drm_atomic_state *state = pipe_config->base.state;
6414 struct intel_crtc *other_crtc;
6415 struct intel_crtc_state *other_crtc_state;
6417 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6418 pipe_name(pipe), pipe_config->fdi_lanes);
6419 if (pipe_config->fdi_lanes > 4) {
6420 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6421 pipe_name(pipe), pipe_config->fdi_lanes);
6425 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6426 if (pipe_config->fdi_lanes > 2) {
6427 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6428 pipe_config->fdi_lanes);
6435 if (INTEL_INFO(dev)->num_pipes == 2)
6438 /* Ivybridge 3 pipe is really complicated */
6443 if (pipe_config->fdi_lanes <= 2)
6446 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6448 intel_atomic_get_crtc_state(state, other_crtc);
6449 if (IS_ERR(other_crtc_state))
6450 return PTR_ERR(other_crtc_state);
6452 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6453 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6454 pipe_name(pipe), pipe_config->fdi_lanes);
6459 if (pipe_config->fdi_lanes > 2) {
6460 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6461 pipe_name(pipe), pipe_config->fdi_lanes);
6465 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6467 intel_atomic_get_crtc_state(state, other_crtc);
6468 if (IS_ERR(other_crtc_state))
6469 return PTR_ERR(other_crtc_state);
6471 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6472 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6482 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6483 struct intel_crtc_state *pipe_config)
6485 struct drm_device *dev = intel_crtc->base.dev;
6486 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6487 int lane, link_bw, fdi_dotclock, ret;
6488 bool needs_recompute = false;
6491 /* FDI is a binary signal running at ~2.7GHz, encoding
6492 * each output octet as 10 bits. The actual frequency
6493 * is stored as a divider into a 100MHz clock, and the
6494 * mode pixel clock is stored in units of 1KHz.
6495 * Hence the bw of each lane in terms of the mode signal
6498 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6500 fdi_dotclock = adjusted_mode->crtc_clock;
6502 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6503 pipe_config->pipe_bpp);
6505 pipe_config->fdi_lanes = lane;
6507 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6508 link_bw, &pipe_config->fdi_m_n);
6510 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6511 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6512 pipe_config->pipe_bpp -= 2*3;
6513 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6514 pipe_config->pipe_bpp);
6515 needs_recompute = true;
6516 pipe_config->bw_constrained = true;
6521 if (needs_recompute)
6527 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6528 struct intel_crtc_state *pipe_config)
6530 if (pipe_config->pipe_bpp > 24)
6533 /* HSW can handle pixel rate up to cdclk? */
6534 if (IS_HASWELL(dev_priv->dev))
6538 * We compare against max which means we must take
6539 * the increased cdclk requirement into account when
6540 * calculating the new cdclk.
6542 * Should measure whether using a lower cdclk w/o IPS
6544 return ilk_pipe_pixel_rate(pipe_config) <=
6545 dev_priv->max_cdclk_freq * 95 / 100;
6548 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6549 struct intel_crtc_state *pipe_config)
6551 struct drm_device *dev = crtc->base.dev;
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6554 pipe_config->ips_enabled = i915.enable_ips &&
6555 hsw_crtc_supports_ips(crtc) &&
6556 pipe_config_supports_ips(dev_priv, pipe_config);
6559 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6561 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6563 /* GDG double wide on either pipe, otherwise pipe A only */
6564 return INTEL_INFO(dev_priv)->gen < 4 &&
6565 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6568 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6569 struct intel_crtc_state *pipe_config)
6571 struct drm_device *dev = crtc->base.dev;
6572 struct drm_i915_private *dev_priv = dev->dev_private;
6573 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6575 /* FIXME should check pixel clock limits on all platforms */
6576 if (INTEL_INFO(dev)->gen < 4) {
6577 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6580 * Enable double wide mode when the dot clock
6581 * is > 90% of the (display) core speed.
6583 if (intel_crtc_supports_double_wide(crtc) &&
6584 adjusted_mode->crtc_clock > clock_limit) {
6586 pipe_config->double_wide = true;
6589 if (adjusted_mode->crtc_clock > clock_limit) {
6590 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6591 adjusted_mode->crtc_clock, clock_limit,
6592 yesno(pipe_config->double_wide));
6598 * Pipe horizontal size must be even in:
6600 * - LVDS dual channel mode
6601 * - Double wide pipe
6603 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6604 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6605 pipe_config->pipe_src_w &= ~1;
6607 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6608 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6610 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6611 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6615 hsw_compute_ips_config(crtc, pipe_config);
6617 if (pipe_config->has_pch_encoder)
6618 return ironlake_fdi_compute_config(crtc, pipe_config);
6623 static int skylake_get_display_clock_speed(struct drm_device *dev)
6625 struct drm_i915_private *dev_priv = to_i915(dev);
6626 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6627 uint32_t cdctl = I915_READ(CDCLK_CTL);
6630 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6631 return 24000; /* 24MHz is the cd freq with NSSC ref */
6633 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6636 linkrate = (I915_READ(DPLL_CTRL1) &
6637 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6639 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6640 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6642 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6643 case CDCLK_FREQ_450_432:
6645 case CDCLK_FREQ_337_308:
6647 case CDCLK_FREQ_675_617:
6650 WARN(1, "Unknown cd freq selection\n");
6654 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6655 case CDCLK_FREQ_450_432:
6657 case CDCLK_FREQ_337_308:
6659 case CDCLK_FREQ_675_617:
6662 WARN(1, "Unknown cd freq selection\n");
6666 /* error case, do as if DPLL0 isn't enabled */
6670 static int broxton_get_display_clock_speed(struct drm_device *dev)
6672 struct drm_i915_private *dev_priv = to_i915(dev);
6673 uint32_t cdctl = I915_READ(CDCLK_CTL);
6674 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6675 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6678 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6681 cdclk = 19200 * pll_ratio / 2;
6683 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6684 case BXT_CDCLK_CD2X_DIV_SEL_1:
6685 return cdclk; /* 576MHz or 624MHz */
6686 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6687 return cdclk * 2 / 3; /* 384MHz */
6688 case BXT_CDCLK_CD2X_DIV_SEL_2:
6689 return cdclk / 2; /* 288MHz */
6690 case BXT_CDCLK_CD2X_DIV_SEL_4:
6691 return cdclk / 4; /* 144MHz */
6694 /* error case, do as if DE PLL isn't enabled */
6698 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 uint32_t lcpll = I915_READ(LCPLL_CTL);
6702 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6704 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6706 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6708 else if (freq == LCPLL_CLK_FREQ_450)
6710 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6712 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6718 static int haswell_get_display_clock_speed(struct drm_device *dev)
6720 struct drm_i915_private *dev_priv = dev->dev_private;
6721 uint32_t lcpll = I915_READ(LCPLL_CTL);
6722 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6724 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6726 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6728 else if (freq == LCPLL_CLK_FREQ_450)
6730 else if (IS_HSW_ULT(dev))
6736 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6738 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6739 CCK_DISPLAY_CLOCK_CONTROL);
6742 static int ilk_get_display_clock_speed(struct drm_device *dev)
6747 static int i945_get_display_clock_speed(struct drm_device *dev)
6752 static int i915_get_display_clock_speed(struct drm_device *dev)
6757 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6762 static int pnv_get_display_clock_speed(struct drm_device *dev)
6766 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6768 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6769 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6771 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6773 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6775 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6778 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6779 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6781 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6786 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6790 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6792 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6795 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796 case GC_DISPLAY_CLOCK_333_MHZ:
6799 case GC_DISPLAY_CLOCK_190_200_MHZ:
6805 static int i865_get_display_clock_speed(struct drm_device *dev)
6810 static int i85x_get_display_clock_speed(struct drm_device *dev)
6815 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6816 * encoding is different :(
6817 * FIXME is this the right way to detect 852GM/852GMV?
6819 if (dev->pdev->revision == 0x1)
6822 pci_bus_read_config_word(dev->pdev->bus,
6823 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6825 /* Assume that the hardware is in the high speed state. This
6826 * should be the default.
6828 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6829 case GC_CLOCK_133_200:
6830 case GC_CLOCK_133_200_2:
6831 case GC_CLOCK_100_200:
6833 case GC_CLOCK_166_250:
6835 case GC_CLOCK_100_133:
6837 case GC_CLOCK_133_266:
6838 case GC_CLOCK_133_266_2:
6839 case GC_CLOCK_166_266:
6843 /* Shouldn't happen */
6847 static int i830_get_display_clock_speed(struct drm_device *dev)
6852 static unsigned int intel_hpll_vco(struct drm_device *dev)
6854 struct drm_i915_private *dev_priv = dev->dev_private;
6855 static const unsigned int blb_vco[8] = {
6862 static const unsigned int pnv_vco[8] = {
6869 static const unsigned int cl_vco[8] = {
6878 static const unsigned int elk_vco[8] = {
6884 static const unsigned int ctg_vco[8] = {
6892 const unsigned int *vco_table;
6896 /* FIXME other chipsets? */
6898 vco_table = ctg_vco;
6899 else if (IS_G4X(dev))
6900 vco_table = elk_vco;
6901 else if (IS_CRESTLINE(dev))
6903 else if (IS_PINEVIEW(dev))
6904 vco_table = pnv_vco;
6905 else if (IS_G33(dev))
6906 vco_table = blb_vco;
6910 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6912 vco = vco_table[tmp & 0x7];
6914 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6916 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6921 static int gm45_get_display_clock_speed(struct drm_device *dev)
6923 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6926 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6928 cdclk_sel = (tmp >> 12) & 0x1;
6934 return cdclk_sel ? 333333 : 222222;
6936 return cdclk_sel ? 320000 : 228571;
6938 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6943 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6945 static const uint8_t div_3200[] = { 16, 10, 8 };
6946 static const uint8_t div_4000[] = { 20, 12, 10 };
6947 static const uint8_t div_5333[] = { 24, 16, 14 };
6948 const uint8_t *div_table;
6949 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6952 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6954 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6956 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6961 div_table = div_3200;
6964 div_table = div_4000;
6967 div_table = div_5333;
6973 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6976 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6980 static int g33_get_display_clock_speed(struct drm_device *dev)
6982 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6983 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6984 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6985 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6986 const uint8_t *div_table;
6987 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6990 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6992 cdclk_sel = (tmp >> 4) & 0x7;
6994 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6999 div_table = div_3200;
7002 div_table = div_4000;
7005 div_table = div_4800;
7008 div_table = div_5333;
7014 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7017 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7022 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7024 while (*num > DATA_LINK_M_N_MASK ||
7025 *den > DATA_LINK_M_N_MASK) {
7031 static void compute_m_n(unsigned int m, unsigned int n,
7032 uint32_t *ret_m, uint32_t *ret_n)
7034 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7035 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7036 intel_reduce_m_n_ratio(ret_m, ret_n);
7040 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7041 int pixel_clock, int link_clock,
7042 struct intel_link_m_n *m_n)
7046 compute_m_n(bits_per_pixel * pixel_clock,
7047 link_clock * nlanes * 8,
7048 &m_n->gmch_m, &m_n->gmch_n);
7050 compute_m_n(pixel_clock, link_clock,
7051 &m_n->link_m, &m_n->link_n);
7054 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7056 if (i915.panel_use_ssc >= 0)
7057 return i915.panel_use_ssc != 0;
7058 return dev_priv->vbt.lvds_use_ssc
7059 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7062 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7065 struct drm_device *dev = crtc_state->base.crtc->dev;
7066 struct drm_i915_private *dev_priv = dev->dev_private;
7069 WARN_ON(!crtc_state->base.state);
7071 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7073 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7074 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7075 refclk = dev_priv->vbt.lvds_ssc_freq;
7076 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7077 } else if (!IS_GEN2(dev)) {
7086 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7088 return (1 << dpll->n) << 16 | dpll->m2;
7091 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7093 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7096 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7097 struct intel_crtc_state *crtc_state,
7098 intel_clock_t *reduced_clock)
7100 struct drm_device *dev = crtc->base.dev;
7103 if (IS_PINEVIEW(dev)) {
7104 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7106 fp2 = pnv_dpll_compute_fp(reduced_clock);
7108 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7110 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7113 crtc_state->dpll_hw_state.fp0 = fp;
7115 crtc->lowfreq_avail = false;
7116 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7118 crtc_state->dpll_hw_state.fp1 = fp2;
7119 crtc->lowfreq_avail = true;
7121 crtc_state->dpll_hw_state.fp1 = fp;
7125 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7131 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7132 * and set it to a reasonable value instead.
7134 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7135 reg_val &= 0xffffff00;
7136 reg_val |= 0x00000030;
7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7139 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7140 reg_val &= 0x8cffffff;
7141 reg_val = 0x8c000000;
7142 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7144 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7145 reg_val &= 0xffffff00;
7146 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7148 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7149 reg_val &= 0x00ffffff;
7150 reg_val |= 0xb0000000;
7151 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7154 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7155 struct intel_link_m_n *m_n)
7157 struct drm_device *dev = crtc->base.dev;
7158 struct drm_i915_private *dev_priv = dev->dev_private;
7159 int pipe = crtc->pipe;
7161 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7162 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7163 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7164 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7167 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7168 struct intel_link_m_n *m_n,
7169 struct intel_link_m_n *m2_n2)
7171 struct drm_device *dev = crtc->base.dev;
7172 struct drm_i915_private *dev_priv = dev->dev_private;
7173 int pipe = crtc->pipe;
7174 enum transcoder transcoder = crtc->config->cpu_transcoder;
7176 if (INTEL_INFO(dev)->gen >= 5) {
7177 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7178 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7179 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7180 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7181 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7182 * for gen < 8) and if DRRS is supported (to make sure the
7183 * registers are not unnecessarily accessed).
7185 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7186 crtc->config->has_drrs) {
7187 I915_WRITE(PIPE_DATA_M2(transcoder),
7188 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7189 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7190 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7191 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7194 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7195 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7196 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7197 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7201 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7203 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7206 dp_m_n = &crtc->config->dp_m_n;
7207 dp_m2_n2 = &crtc->config->dp_m2_n2;
7208 } else if (m_n == M2_N2) {
7211 * M2_N2 registers are not supported. Hence m2_n2 divider value
7212 * needs to be programmed into M1_N1.
7214 dp_m_n = &crtc->config->dp_m2_n2;
7216 DRM_ERROR("Unsupported divider value\n");
7220 if (crtc->config->has_pch_encoder)
7221 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7223 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7226 static void vlv_compute_dpll(struct intel_crtc *crtc,
7227 struct intel_crtc_state *pipe_config)
7232 * Enable DPIO clock input. We should never disable the reference
7233 * clock for pipe B, since VGA hotplug / manual detection depends
7236 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7237 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7238 /* We should never disable this, set it here for state tracking */
7239 if (crtc->pipe == PIPE_B)
7240 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7241 dpll |= DPLL_VCO_ENABLE;
7242 pipe_config->dpll_hw_state.dpll = dpll;
7244 dpll_md = (pipe_config->pixel_multiplier - 1)
7245 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7246 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7249 static void vlv_prepare_pll(struct intel_crtc *crtc,
7250 const struct intel_crtc_state *pipe_config)
7252 struct drm_device *dev = crtc->base.dev;
7253 struct drm_i915_private *dev_priv = dev->dev_private;
7254 int pipe = crtc->pipe;
7256 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7257 u32 coreclk, reg_val;
7259 mutex_lock(&dev_priv->sb_lock);
7261 bestn = pipe_config->dpll.n;
7262 bestm1 = pipe_config->dpll.m1;
7263 bestm2 = pipe_config->dpll.m2;
7264 bestp1 = pipe_config->dpll.p1;
7265 bestp2 = pipe_config->dpll.p2;
7267 /* See eDP HDMI DPIO driver vbios notes doc */
7269 /* PLL B needs special handling */
7271 vlv_pllb_recal_opamp(dev_priv, pipe);
7273 /* Set up Tx target for periodic Rcomp update */
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7276 /* Disable target IRef on PLL */
7277 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7278 reg_val &= 0x00ffffff;
7279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7281 /* Disable fast lock */
7282 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7284 /* Set idtafcrecal before PLL is enabled */
7285 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7286 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7287 mdiv |= ((bestn << DPIO_N_SHIFT));
7288 mdiv |= (1 << DPIO_K_SHIFT);
7291 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7292 * but we don't support that).
7293 * Note: don't use the DAC post divider as it seems unstable.
7295 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7298 mdiv |= DPIO_ENABLE_CALIBRATION;
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7301 /* Set HBR and RBR LPF coefficients */
7302 if (pipe_config->port_clock == 162000 ||
7303 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7304 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7311 if (pipe_config->has_dp_encoder) {
7312 /* Use SSC source */
7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319 } else { /* HDMI or VGA */
7320 /* Use bend source */
7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7329 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7330 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7331 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7332 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7333 coreclk |= 0x01000000;
7334 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7336 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7337 mutex_unlock(&dev_priv->sb_lock);
7340 static void chv_compute_dpll(struct intel_crtc *crtc,
7341 struct intel_crtc_state *pipe_config)
7343 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7344 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7346 if (crtc->pipe != PIPE_A)
7347 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7349 pipe_config->dpll_hw_state.dpll_md =
7350 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7353 static void chv_prepare_pll(struct intel_crtc *crtc,
7354 const struct intel_crtc_state *pipe_config)
7356 struct drm_device *dev = crtc->base.dev;
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358 int pipe = crtc->pipe;
7359 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7360 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7361 u32 loopfilter, tribuf_calcntr;
7362 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7366 bestn = pipe_config->dpll.n;
7367 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7368 bestm1 = pipe_config->dpll.m1;
7369 bestm2 = pipe_config->dpll.m2 >> 22;
7370 bestp1 = pipe_config->dpll.p1;
7371 bestp2 = pipe_config->dpll.p2;
7372 vco = pipe_config->dpll.vco;
7377 * Enable Refclk and SSC
7379 I915_WRITE(dpll_reg,
7380 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7382 mutex_lock(&dev_priv->sb_lock);
7384 /* p1 and p2 divider */
7385 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7386 5 << DPIO_CHV_S1_DIV_SHIFT |
7387 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7388 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7389 1 << DPIO_CHV_K_DIV_SHIFT);
7391 /* Feedback post-divider - m2 */
7392 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7394 /* Feedback refclk divider - n and m1 */
7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7396 DPIO_CHV_M1_DIV_BY_2 |
7397 1 << DPIO_CHV_N_DIV_SHIFT);
7399 /* M2 fraction division */
7400 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7402 /* M2 fraction division enable */
7403 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7404 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7405 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7407 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7408 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7410 /* Program digital lock detect threshold */
7411 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7412 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7413 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7414 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7416 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7417 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7420 if (vco == 5400000) {
7421 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7422 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7423 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424 tribuf_calcntr = 0x9;
7425 } else if (vco <= 6200000) {
7426 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7427 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7428 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7429 tribuf_calcntr = 0x9;
7430 } else if (vco <= 6480000) {
7431 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7432 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7433 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7434 tribuf_calcntr = 0x8;
7436 /* Not supported. Apply the same limits as in the max case */
7437 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7438 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7439 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7442 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7444 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7445 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7446 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7447 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7450 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7451 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7454 mutex_unlock(&dev_priv->sb_lock);
7458 * vlv_force_pll_on - forcibly enable just the PLL
7459 * @dev_priv: i915 private structure
7460 * @pipe: pipe PLL to enable
7461 * @dpll: PLL configuration
7463 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7464 * in cases where we need the PLL enabled even when @pipe is not going to
7467 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7468 const struct dpll *dpll)
7470 struct intel_crtc *crtc =
7471 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7472 struct intel_crtc_state *pipe_config;
7474 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7478 pipe_config->base.crtc = &crtc->base;
7479 pipe_config->pixel_multiplier = 1;
7480 pipe_config->dpll = *dpll;
7482 if (IS_CHERRYVIEW(dev)) {
7483 chv_compute_dpll(crtc, pipe_config);
7484 chv_prepare_pll(crtc, pipe_config);
7485 chv_enable_pll(crtc, pipe_config);
7487 vlv_compute_dpll(crtc, pipe_config);
7488 vlv_prepare_pll(crtc, pipe_config);
7489 vlv_enable_pll(crtc, pipe_config);
7498 * vlv_force_pll_off - forcibly disable just the PLL
7499 * @dev_priv: i915 private structure
7500 * @pipe: pipe PLL to disable
7502 * Disable the PLL for @pipe. To be used in cases where we need
7503 * the PLL enabled even when @pipe is not going to be enabled.
7505 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7507 if (IS_CHERRYVIEW(dev))
7508 chv_disable_pll(to_i915(dev), pipe);
7510 vlv_disable_pll(to_i915(dev), pipe);
7513 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7514 struct intel_crtc_state *crtc_state,
7515 intel_clock_t *reduced_clock,
7518 struct drm_device *dev = crtc->base.dev;
7519 struct drm_i915_private *dev_priv = dev->dev_private;
7522 struct dpll *clock = &crtc_state->dpll;
7524 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7526 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7527 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7529 dpll = DPLL_VGA_MODE_DIS;
7531 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7532 dpll |= DPLLB_MODE_LVDS;
7534 dpll |= DPLLB_MODE_DAC_SERIAL;
7536 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7537 dpll |= (crtc_state->pixel_multiplier - 1)
7538 << SDVO_MULTIPLIER_SHIFT_HIRES;
7542 dpll |= DPLL_SDVO_HIGH_SPEED;
7544 if (crtc_state->has_dp_encoder)
7545 dpll |= DPLL_SDVO_HIGH_SPEED;
7547 /* compute bitmask from p1 value */
7548 if (IS_PINEVIEW(dev))
7549 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7551 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7552 if (IS_G4X(dev) && reduced_clock)
7553 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7555 switch (clock->p2) {
7557 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7560 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7563 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7566 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7569 if (INTEL_INFO(dev)->gen >= 4)
7570 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7572 if (crtc_state->sdvo_tv_clock)
7573 dpll |= PLL_REF_INPUT_TVCLKINBC;
7574 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7575 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7576 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7578 dpll |= PLL_REF_INPUT_DREFCLK;
7580 dpll |= DPLL_VCO_ENABLE;
7581 crtc_state->dpll_hw_state.dpll = dpll;
7583 if (INTEL_INFO(dev)->gen >= 4) {
7584 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7585 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7586 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7590 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7591 struct intel_crtc_state *crtc_state,
7592 intel_clock_t *reduced_clock,
7595 struct drm_device *dev = crtc->base.dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
7598 struct dpll *clock = &crtc_state->dpll;
7600 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7602 dpll = DPLL_VGA_MODE_DIS;
7604 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7605 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7608 dpll |= PLL_P1_DIVIDE_BY_TWO;
7610 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7612 dpll |= PLL_P2_DIVIDE_BY_4;
7615 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7616 dpll |= DPLL_DVO_2X_MODE;
7618 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7619 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7620 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7622 dpll |= PLL_REF_INPUT_DREFCLK;
7624 dpll |= DPLL_VCO_ENABLE;
7625 crtc_state->dpll_hw_state.dpll = dpll;
7628 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7630 struct drm_device *dev = intel_crtc->base.dev;
7631 struct drm_i915_private *dev_priv = dev->dev_private;
7632 enum pipe pipe = intel_crtc->pipe;
7633 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7634 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7635 uint32_t crtc_vtotal, crtc_vblank_end;
7638 /* We need to be careful not to changed the adjusted mode, for otherwise
7639 * the hw state checker will get angry at the mismatch. */
7640 crtc_vtotal = adjusted_mode->crtc_vtotal;
7641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7643 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7644 /* the chip adds 2 halflines automatically */
7646 crtc_vblank_end -= 1;
7648 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7649 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7651 vsyncshift = adjusted_mode->crtc_hsync_start -
7652 adjusted_mode->crtc_htotal / 2;
7654 vsyncshift += adjusted_mode->crtc_htotal;
7657 if (INTEL_INFO(dev)->gen > 3)
7658 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7660 I915_WRITE(HTOTAL(cpu_transcoder),
7661 (adjusted_mode->crtc_hdisplay - 1) |
7662 ((adjusted_mode->crtc_htotal - 1) << 16));
7663 I915_WRITE(HBLANK(cpu_transcoder),
7664 (adjusted_mode->crtc_hblank_start - 1) |
7665 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7666 I915_WRITE(HSYNC(cpu_transcoder),
7667 (adjusted_mode->crtc_hsync_start - 1) |
7668 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7670 I915_WRITE(VTOTAL(cpu_transcoder),
7671 (adjusted_mode->crtc_vdisplay - 1) |
7672 ((crtc_vtotal - 1) << 16));
7673 I915_WRITE(VBLANK(cpu_transcoder),
7674 (adjusted_mode->crtc_vblank_start - 1) |
7675 ((crtc_vblank_end - 1) << 16));
7676 I915_WRITE(VSYNC(cpu_transcoder),
7677 (adjusted_mode->crtc_vsync_start - 1) |
7678 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7680 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7681 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7682 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7684 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7685 (pipe == PIPE_B || pipe == PIPE_C))
7686 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7690 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7692 struct drm_device *dev = intel_crtc->base.dev;
7693 struct drm_i915_private *dev_priv = dev->dev_private;
7694 enum pipe pipe = intel_crtc->pipe;
7696 /* pipesrc controls the size that is scaled from, which should
7697 * always be the user's requested size.
7699 I915_WRITE(PIPESRC(pipe),
7700 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7701 (intel_crtc->config->pipe_src_h - 1));
7704 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7705 struct intel_crtc_state *pipe_config)
7707 struct drm_device *dev = crtc->base.dev;
7708 struct drm_i915_private *dev_priv = dev->dev_private;
7709 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7712 tmp = I915_READ(HTOTAL(cpu_transcoder));
7713 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7714 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7715 tmp = I915_READ(HBLANK(cpu_transcoder));
7716 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7717 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7718 tmp = I915_READ(HSYNC(cpu_transcoder));
7719 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7720 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7722 tmp = I915_READ(VTOTAL(cpu_transcoder));
7723 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7724 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7725 tmp = I915_READ(VBLANK(cpu_transcoder));
7726 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7727 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7728 tmp = I915_READ(VSYNC(cpu_transcoder));
7729 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7730 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7732 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7733 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7734 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7735 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7739 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7740 struct intel_crtc_state *pipe_config)
7742 struct drm_device *dev = crtc->base.dev;
7743 struct drm_i915_private *dev_priv = dev->dev_private;
7746 tmp = I915_READ(PIPESRC(crtc->pipe));
7747 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7748 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7750 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7751 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7754 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7755 struct intel_crtc_state *pipe_config)
7757 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7758 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7759 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7760 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7762 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7763 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7764 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7765 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7767 mode->flags = pipe_config->base.adjusted_mode.flags;
7768 mode->type = DRM_MODE_TYPE_DRIVER;
7770 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7771 mode->flags |= pipe_config->base.adjusted_mode.flags;
7773 mode->hsync = drm_mode_hsync(mode);
7774 mode->vrefresh = drm_mode_vrefresh(mode);
7775 drm_mode_set_name(mode);
7778 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7780 struct drm_device *dev = intel_crtc->base.dev;
7781 struct drm_i915_private *dev_priv = dev->dev_private;
7786 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7787 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7788 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7790 if (intel_crtc->config->double_wide)
7791 pipeconf |= PIPECONF_DOUBLE_WIDE;
7793 /* only g4x and later have fancy bpc/dither controls */
7794 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7795 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7796 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7797 pipeconf |= PIPECONF_DITHER_EN |
7798 PIPECONF_DITHER_TYPE_SP;
7800 switch (intel_crtc->config->pipe_bpp) {
7802 pipeconf |= PIPECONF_6BPC;
7805 pipeconf |= PIPECONF_8BPC;
7808 pipeconf |= PIPECONF_10BPC;
7811 /* Case prevented by intel_choose_pipe_bpp_dither. */
7816 if (HAS_PIPE_CXSR(dev)) {
7817 if (intel_crtc->lowfreq_avail) {
7818 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7819 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7821 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7825 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7826 if (INTEL_INFO(dev)->gen < 4 ||
7827 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7828 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7830 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7832 pipeconf |= PIPECONF_PROGRESSIVE;
7834 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7835 intel_crtc->config->limited_color_range)
7836 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7838 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7839 POSTING_READ(PIPECONF(intel_crtc->pipe));
7842 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7843 struct intel_crtc_state *crtc_state)
7845 struct drm_device *dev = crtc->base.dev;
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847 int refclk, num_connectors = 0;
7848 intel_clock_t clock;
7850 const intel_limit_t *limit;
7851 struct drm_atomic_state *state = crtc_state->base.state;
7852 struct drm_connector *connector;
7853 struct drm_connector_state *connector_state;
7856 memset(&crtc_state->dpll_hw_state, 0,
7857 sizeof(crtc_state->dpll_hw_state));
7859 if (crtc_state->has_dsi_encoder)
7862 for_each_connector_in_state(state, connector, connector_state, i) {
7863 if (connector_state->crtc == &crtc->base)
7867 if (!crtc_state->clock_set) {
7868 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7871 * Returns a set of divisors for the desired target clock with
7872 * the given refclk, or FALSE. The returned values represent
7873 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7876 limit = intel_limit(crtc_state, refclk);
7877 ok = dev_priv->display.find_dpll(limit, crtc_state,
7878 crtc_state->port_clock,
7879 refclk, NULL, &clock);
7881 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7885 /* Compat-code for transition, will disappear. */
7886 crtc_state->dpll.n = clock.n;
7887 crtc_state->dpll.m1 = clock.m1;
7888 crtc_state->dpll.m2 = clock.m2;
7889 crtc_state->dpll.p1 = clock.p1;
7890 crtc_state->dpll.p2 = clock.p2;
7894 i8xx_compute_dpll(crtc, crtc_state, NULL,
7896 } else if (IS_CHERRYVIEW(dev)) {
7897 chv_compute_dpll(crtc, crtc_state);
7898 } else if (IS_VALLEYVIEW(dev)) {
7899 vlv_compute_dpll(crtc, crtc_state);
7901 i9xx_compute_dpll(crtc, crtc_state, NULL,
7908 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7909 struct intel_crtc_state *pipe_config)
7911 struct drm_device *dev = crtc->base.dev;
7912 struct drm_i915_private *dev_priv = dev->dev_private;
7915 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7918 tmp = I915_READ(PFIT_CONTROL);
7919 if (!(tmp & PFIT_ENABLE))
7922 /* Check whether the pfit is attached to our pipe. */
7923 if (INTEL_INFO(dev)->gen < 4) {
7924 if (crtc->pipe != PIPE_B)
7927 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7931 pipe_config->gmch_pfit.control = tmp;
7932 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7933 if (INTEL_INFO(dev)->gen < 5)
7934 pipe_config->gmch_pfit.lvds_border_bits =
7935 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7938 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7939 struct intel_crtc_state *pipe_config)
7941 struct drm_device *dev = crtc->base.dev;
7942 struct drm_i915_private *dev_priv = dev->dev_private;
7943 int pipe = pipe_config->cpu_transcoder;
7944 intel_clock_t clock;
7946 int refclk = 100000;
7948 /* In case of MIPI DPLL will not even be used */
7949 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7952 mutex_lock(&dev_priv->sb_lock);
7953 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7954 mutex_unlock(&dev_priv->sb_lock);
7956 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7957 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7958 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7959 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7960 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7962 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7966 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7967 struct intel_initial_plane_config *plane_config)
7969 struct drm_device *dev = crtc->base.dev;
7970 struct drm_i915_private *dev_priv = dev->dev_private;
7971 u32 val, base, offset;
7972 int pipe = crtc->pipe, plane = crtc->plane;
7973 int fourcc, pixel_format;
7974 unsigned int aligned_height;
7975 struct drm_framebuffer *fb;
7976 struct intel_framebuffer *intel_fb;
7978 val = I915_READ(DSPCNTR(plane));
7979 if (!(val & DISPLAY_PLANE_ENABLE))
7982 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7984 DRM_DEBUG_KMS("failed to alloc fb\n");
7988 fb = &intel_fb->base;
7990 if (INTEL_INFO(dev)->gen >= 4) {
7991 if (val & DISPPLANE_TILED) {
7992 plane_config->tiling = I915_TILING_X;
7993 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7997 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7998 fourcc = i9xx_format_to_fourcc(pixel_format);
7999 fb->pixel_format = fourcc;
8000 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8002 if (INTEL_INFO(dev)->gen >= 4) {
8003 if (plane_config->tiling)
8004 offset = I915_READ(DSPTILEOFF(plane));
8006 offset = I915_READ(DSPLINOFF(plane));
8007 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8009 base = I915_READ(DSPADDR(plane));
8011 plane_config->base = base;
8013 val = I915_READ(PIPESRC(pipe));
8014 fb->width = ((val >> 16) & 0xfff) + 1;
8015 fb->height = ((val >> 0) & 0xfff) + 1;
8017 val = I915_READ(DSPSTRIDE(pipe));
8018 fb->pitches[0] = val & 0xffffffc0;
8020 aligned_height = intel_fb_align_height(dev, fb->height,
8024 plane_config->size = fb->pitches[0] * aligned_height;
8026 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8027 pipe_name(pipe), plane, fb->width, fb->height,
8028 fb->bits_per_pixel, base, fb->pitches[0],
8029 plane_config->size);
8031 plane_config->fb = intel_fb;
8034 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8035 struct intel_crtc_state *pipe_config)
8037 struct drm_device *dev = crtc->base.dev;
8038 struct drm_i915_private *dev_priv = dev->dev_private;
8039 int pipe = pipe_config->cpu_transcoder;
8040 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8041 intel_clock_t clock;
8042 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8043 int refclk = 100000;
8045 mutex_lock(&dev_priv->sb_lock);
8046 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8047 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8048 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8049 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8050 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8051 mutex_unlock(&dev_priv->sb_lock);
8053 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8054 clock.m2 = (pll_dw0 & 0xff) << 22;
8055 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8056 clock.m2 |= pll_dw2 & 0x3fffff;
8057 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8058 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8059 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8061 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8064 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8065 struct intel_crtc_state *pipe_config)
8067 struct drm_device *dev = crtc->base.dev;
8068 struct drm_i915_private *dev_priv = dev->dev_private;
8069 enum intel_display_power_domain power_domain;
8073 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8074 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8077 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8078 pipe_config->shared_dpll = NULL;
8082 tmp = I915_READ(PIPECONF(crtc->pipe));
8083 if (!(tmp & PIPECONF_ENABLE))
8086 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8087 switch (tmp & PIPECONF_BPC_MASK) {
8089 pipe_config->pipe_bpp = 18;
8092 pipe_config->pipe_bpp = 24;
8094 case PIPECONF_10BPC:
8095 pipe_config->pipe_bpp = 30;
8102 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8103 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8104 pipe_config->limited_color_range = true;
8106 if (INTEL_INFO(dev)->gen < 4)
8107 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8109 intel_get_pipe_timings(crtc, pipe_config);
8110 intel_get_pipe_src_size(crtc, pipe_config);
8112 i9xx_get_pfit_config(crtc, pipe_config);
8114 if (INTEL_INFO(dev)->gen >= 4) {
8115 tmp = I915_READ(DPLL_MD(crtc->pipe));
8116 pipe_config->pixel_multiplier =
8117 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8118 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8119 pipe_config->dpll_hw_state.dpll_md = tmp;
8120 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8121 tmp = I915_READ(DPLL(crtc->pipe));
8122 pipe_config->pixel_multiplier =
8123 ((tmp & SDVO_MULTIPLIER_MASK)
8124 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8126 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8127 * port and will be fixed up in the encoder->get_config
8129 pipe_config->pixel_multiplier = 1;
8131 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8132 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8134 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8135 * on 830. Filter it out here so that we don't
8136 * report errors due to that.
8139 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8141 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8142 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8144 /* Mask out read-only status bits. */
8145 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8146 DPLL_PORTC_READY_MASK |
8147 DPLL_PORTB_READY_MASK);
8150 if (IS_CHERRYVIEW(dev))
8151 chv_crtc_clock_get(crtc, pipe_config);
8152 else if (IS_VALLEYVIEW(dev))
8153 vlv_crtc_clock_get(crtc, pipe_config);
8155 i9xx_crtc_clock_get(crtc, pipe_config);
8158 * Normally the dotclock is filled in by the encoder .get_config()
8159 * but in case the pipe is enabled w/o any ports we need a sane
8162 pipe_config->base.adjusted_mode.crtc_clock =
8163 pipe_config->port_clock / pipe_config->pixel_multiplier;
8168 intel_display_power_put(dev_priv, power_domain);
8173 static void ironlake_init_pch_refclk(struct drm_device *dev)
8175 struct drm_i915_private *dev_priv = dev->dev_private;
8176 struct intel_encoder *encoder;
8178 bool has_lvds = false;
8179 bool has_cpu_edp = false;
8180 bool has_panel = false;
8181 bool has_ck505 = false;
8182 bool can_ssc = false;
8184 /* We need to take the global config into account */
8185 for_each_intel_encoder(dev, encoder) {
8186 switch (encoder->type) {
8187 case INTEL_OUTPUT_LVDS:
8191 case INTEL_OUTPUT_EDP:
8193 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8201 if (HAS_PCH_IBX(dev)) {
8202 has_ck505 = dev_priv->vbt.display_clock_mode;
8203 can_ssc = has_ck505;
8209 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8210 has_panel, has_lvds, has_ck505);
8212 /* Ironlake: try to setup display ref clock before DPLL
8213 * enabling. This is only under driver's control after
8214 * PCH B stepping, previous chipset stepping should be
8215 * ignoring this setting.
8217 val = I915_READ(PCH_DREF_CONTROL);
8219 /* As we must carefully and slowly disable/enable each source in turn,
8220 * compute the final state we want first and check if we need to
8221 * make any changes at all.
8224 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8226 final |= DREF_NONSPREAD_CK505_ENABLE;
8228 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8230 final &= ~DREF_SSC_SOURCE_MASK;
8231 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8232 final &= ~DREF_SSC1_ENABLE;
8235 final |= DREF_SSC_SOURCE_ENABLE;
8237 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8238 final |= DREF_SSC1_ENABLE;
8241 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8242 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8244 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8246 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8248 final |= DREF_SSC_SOURCE_DISABLE;
8249 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8255 /* Always enable nonspread source */
8256 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8259 val |= DREF_NONSPREAD_CK505_ENABLE;
8261 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8264 val &= ~DREF_SSC_SOURCE_MASK;
8265 val |= DREF_SSC_SOURCE_ENABLE;
8267 /* SSC must be turned on before enabling the CPU output */
8268 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8269 DRM_DEBUG_KMS("Using SSC on panel\n");
8270 val |= DREF_SSC1_ENABLE;
8272 val &= ~DREF_SSC1_ENABLE;
8274 /* Get SSC going before enabling the outputs */
8275 I915_WRITE(PCH_DREF_CONTROL, val);
8276 POSTING_READ(PCH_DREF_CONTROL);
8279 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8281 /* Enable CPU source on CPU attached eDP */
8283 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8284 DRM_DEBUG_KMS("Using SSC on eDP\n");
8285 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8287 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8289 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8291 I915_WRITE(PCH_DREF_CONTROL, val);
8292 POSTING_READ(PCH_DREF_CONTROL);
8295 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8297 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8299 /* Turn off CPU output */
8300 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8302 I915_WRITE(PCH_DREF_CONTROL, val);
8303 POSTING_READ(PCH_DREF_CONTROL);
8306 /* Turn off the SSC source */
8307 val &= ~DREF_SSC_SOURCE_MASK;
8308 val |= DREF_SSC_SOURCE_DISABLE;
8311 val &= ~DREF_SSC1_ENABLE;
8313 I915_WRITE(PCH_DREF_CONTROL, val);
8314 POSTING_READ(PCH_DREF_CONTROL);
8318 BUG_ON(val != final);
8321 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8325 tmp = I915_READ(SOUTH_CHICKEN2);
8326 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8327 I915_WRITE(SOUTH_CHICKEN2, tmp);
8329 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8330 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8331 DRM_ERROR("FDI mPHY reset assert timeout\n");
8333 tmp = I915_READ(SOUTH_CHICKEN2);
8334 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8335 I915_WRITE(SOUTH_CHICKEN2, tmp);
8337 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8338 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8339 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8342 /* WaMPhyProgramming:hsw */
8343 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8347 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8348 tmp &= ~(0xFF << 24);
8349 tmp |= (0x12 << 24);
8350 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8352 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8354 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8356 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8358 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8360 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8361 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8362 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8364 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8365 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8366 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8368 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8371 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8373 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8376 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8378 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8381 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8383 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8386 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8388 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8389 tmp &= ~(0xFF << 16);
8390 tmp |= (0x1C << 16);
8391 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8393 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8394 tmp &= ~(0xFF << 16);
8395 tmp |= (0x1C << 16);
8396 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8398 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8400 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8402 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8404 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8406 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8407 tmp &= ~(0xF << 28);
8409 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8411 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8412 tmp &= ~(0xF << 28);
8414 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8417 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8418 * Programming" based on the parameters passed:
8419 * - Sequence to enable CLKOUT_DP
8420 * - Sequence to enable CLKOUT_DP without spread
8421 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8423 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8426 struct drm_i915_private *dev_priv = dev->dev_private;
8429 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8431 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8434 mutex_lock(&dev_priv->sb_lock);
8436 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8437 tmp &= ~SBI_SSCCTL_DISABLE;
8438 tmp |= SBI_SSCCTL_PATHALT;
8439 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8444 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8445 tmp &= ~SBI_SSCCTL_PATHALT;
8446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8449 lpt_reset_fdi_mphy(dev_priv);
8450 lpt_program_fdi_mphy(dev_priv);
8454 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8455 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8456 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8457 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8459 mutex_unlock(&dev_priv->sb_lock);
8462 /* Sequence to disable CLKOUT_DP */
8463 static void lpt_disable_clkout_dp(struct drm_device *dev)
8465 struct drm_i915_private *dev_priv = dev->dev_private;
8468 mutex_lock(&dev_priv->sb_lock);
8470 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8471 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8472 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8473 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8475 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8476 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8477 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8478 tmp |= SBI_SSCCTL_PATHALT;
8479 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8482 tmp |= SBI_SSCCTL_DISABLE;
8483 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486 mutex_unlock(&dev_priv->sb_lock);
8489 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8491 static const uint16_t sscdivintphase[] = {
8492 [BEND_IDX( 50)] = 0x3B23,
8493 [BEND_IDX( 45)] = 0x3B23,
8494 [BEND_IDX( 40)] = 0x3C23,
8495 [BEND_IDX( 35)] = 0x3C23,
8496 [BEND_IDX( 30)] = 0x3D23,
8497 [BEND_IDX( 25)] = 0x3D23,
8498 [BEND_IDX( 20)] = 0x3E23,
8499 [BEND_IDX( 15)] = 0x3E23,
8500 [BEND_IDX( 10)] = 0x3F23,
8501 [BEND_IDX( 5)] = 0x3F23,
8502 [BEND_IDX( 0)] = 0x0025,
8503 [BEND_IDX( -5)] = 0x0025,
8504 [BEND_IDX(-10)] = 0x0125,
8505 [BEND_IDX(-15)] = 0x0125,
8506 [BEND_IDX(-20)] = 0x0225,
8507 [BEND_IDX(-25)] = 0x0225,
8508 [BEND_IDX(-30)] = 0x0325,
8509 [BEND_IDX(-35)] = 0x0325,
8510 [BEND_IDX(-40)] = 0x0425,
8511 [BEND_IDX(-45)] = 0x0425,
8512 [BEND_IDX(-50)] = 0x0525,
8517 * steps -50 to 50 inclusive, in steps of 5
8518 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8519 * change in clock period = -(steps / 10) * 5.787 ps
8521 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8524 int idx = BEND_IDX(steps);
8526 if (WARN_ON(steps % 5 != 0))
8529 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8532 mutex_lock(&dev_priv->sb_lock);
8534 if (steps % 10 != 0)
8538 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8540 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8542 tmp |= sscdivintphase[idx];
8543 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8545 mutex_unlock(&dev_priv->sb_lock);
8550 static void lpt_init_pch_refclk(struct drm_device *dev)
8552 struct intel_encoder *encoder;
8553 bool has_vga = false;
8555 for_each_intel_encoder(dev, encoder) {
8556 switch (encoder->type) {
8557 case INTEL_OUTPUT_ANALOG:
8566 lpt_bend_clkout_dp(to_i915(dev), 0);
8567 lpt_enable_clkout_dp(dev, true, true);
8569 lpt_disable_clkout_dp(dev);
8574 * Initialize reference clocks when the driver loads
8576 void intel_init_pch_refclk(struct drm_device *dev)
8578 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8579 ironlake_init_pch_refclk(dev);
8580 else if (HAS_PCH_LPT(dev))
8581 lpt_init_pch_refclk(dev);
8584 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8586 struct drm_device *dev = crtc_state->base.crtc->dev;
8587 struct drm_i915_private *dev_priv = dev->dev_private;
8588 struct drm_atomic_state *state = crtc_state->base.state;
8589 struct drm_connector *connector;
8590 struct drm_connector_state *connector_state;
8591 struct intel_encoder *encoder;
8592 int num_connectors = 0, i;
8593 bool is_lvds = false;
8595 for_each_connector_in_state(state, connector, connector_state, i) {
8596 if (connector_state->crtc != crtc_state->base.crtc)
8599 encoder = to_intel_encoder(connector_state->best_encoder);
8601 switch (encoder->type) {
8602 case INTEL_OUTPUT_LVDS:
8611 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8612 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8613 dev_priv->vbt.lvds_ssc_freq);
8614 return dev_priv->vbt.lvds_ssc_freq;
8620 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8622 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8624 int pipe = intel_crtc->pipe;
8629 switch (intel_crtc->config->pipe_bpp) {
8631 val |= PIPECONF_6BPC;
8634 val |= PIPECONF_8BPC;
8637 val |= PIPECONF_10BPC;
8640 val |= PIPECONF_12BPC;
8643 /* Case prevented by intel_choose_pipe_bpp_dither. */
8647 if (intel_crtc->config->dither)
8648 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8650 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8651 val |= PIPECONF_INTERLACED_ILK;
8653 val |= PIPECONF_PROGRESSIVE;
8655 if (intel_crtc->config->limited_color_range)
8656 val |= PIPECONF_COLOR_RANGE_SELECT;
8658 I915_WRITE(PIPECONF(pipe), val);
8659 POSTING_READ(PIPECONF(pipe));
8662 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8664 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8669 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8670 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8672 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8673 val |= PIPECONF_INTERLACED_ILK;
8675 val |= PIPECONF_PROGRESSIVE;
8677 I915_WRITE(PIPECONF(cpu_transcoder), val);
8678 POSTING_READ(PIPECONF(cpu_transcoder));
8681 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8683 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8686 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8689 switch (intel_crtc->config->pipe_bpp) {
8691 val |= PIPEMISC_DITHER_6_BPC;
8694 val |= PIPEMISC_DITHER_8_BPC;
8697 val |= PIPEMISC_DITHER_10_BPC;
8700 val |= PIPEMISC_DITHER_12_BPC;
8703 /* Case prevented by pipe_config_set_bpp. */
8707 if (intel_crtc->config->dither)
8708 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8710 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8714 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8715 struct intel_crtc_state *crtc_state,
8716 intel_clock_t *clock,
8717 bool *has_reduced_clock,
8718 intel_clock_t *reduced_clock)
8720 struct drm_device *dev = crtc->dev;
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8723 const intel_limit_t *limit;
8726 refclk = ironlake_get_refclk(crtc_state);
8729 * Returns a set of divisors for the desired target clock with the given
8730 * refclk, or FALSE. The returned values represent the clock equation:
8731 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8733 limit = intel_limit(crtc_state, refclk);
8734 ret = dev_priv->display.find_dpll(limit, crtc_state,
8735 crtc_state->port_clock,
8736 refclk, NULL, clock);
8743 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8746 * Account for spread spectrum to avoid
8747 * oversubscribing the link. Max center spread
8748 * is 2.5%; use 5% for safety's sake.
8750 u32 bps = target_clock * bpp * 21 / 20;
8751 return DIV_ROUND_UP(bps, link_bw * 8);
8754 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8756 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8759 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8760 struct intel_crtc_state *crtc_state,
8762 intel_clock_t *reduced_clock, u32 *fp2)
8764 struct drm_crtc *crtc = &intel_crtc->base;
8765 struct drm_device *dev = crtc->dev;
8766 struct drm_i915_private *dev_priv = dev->dev_private;
8767 struct drm_atomic_state *state = crtc_state->base.state;
8768 struct drm_connector *connector;
8769 struct drm_connector_state *connector_state;
8770 struct intel_encoder *encoder;
8772 int factor, num_connectors = 0, i;
8773 bool is_lvds = false, is_sdvo = false;
8775 for_each_connector_in_state(state, connector, connector_state, i) {
8776 if (connector_state->crtc != crtc_state->base.crtc)
8779 encoder = to_intel_encoder(connector_state->best_encoder);
8781 switch (encoder->type) {
8782 case INTEL_OUTPUT_LVDS:
8785 case INTEL_OUTPUT_SDVO:
8786 case INTEL_OUTPUT_HDMI:
8796 /* Enable autotuning of the PLL clock (if permissible) */
8799 if ((intel_panel_use_ssc(dev_priv) &&
8800 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8801 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8803 } else if (crtc_state->sdvo_tv_clock)
8806 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8809 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8815 dpll |= DPLLB_MODE_LVDS;
8817 dpll |= DPLLB_MODE_DAC_SERIAL;
8819 dpll |= (crtc_state->pixel_multiplier - 1)
8820 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8823 dpll |= DPLL_SDVO_HIGH_SPEED;
8824 if (crtc_state->has_dp_encoder)
8825 dpll |= DPLL_SDVO_HIGH_SPEED;
8827 /* compute bitmask from p1 value */
8828 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8830 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8832 switch (crtc_state->dpll.p2) {
8834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8847 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8848 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8850 dpll |= PLL_REF_INPUT_DREFCLK;
8852 return dpll | DPLL_VCO_ENABLE;
8855 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8856 struct intel_crtc_state *crtc_state)
8858 struct drm_device *dev = crtc->base.dev;
8859 intel_clock_t clock, reduced_clock;
8860 u32 dpll = 0, fp = 0, fp2 = 0;
8861 bool ok, has_reduced_clock = false;
8862 bool is_lvds = false;
8863 struct intel_shared_dpll *pll;
8865 memset(&crtc_state->dpll_hw_state, 0,
8866 sizeof(crtc_state->dpll_hw_state));
8868 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8870 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8871 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8873 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8874 &has_reduced_clock, &reduced_clock);
8875 if (!ok && !crtc_state->clock_set) {
8876 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8879 /* Compat-code for transition, will disappear. */
8880 if (!crtc_state->clock_set) {
8881 crtc_state->dpll.n = clock.n;
8882 crtc_state->dpll.m1 = clock.m1;
8883 crtc_state->dpll.m2 = clock.m2;
8884 crtc_state->dpll.p1 = clock.p1;
8885 crtc_state->dpll.p2 = clock.p2;
8888 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8889 if (crtc_state->has_pch_encoder) {
8890 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8891 if (has_reduced_clock)
8892 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8894 dpll = ironlake_compute_dpll(crtc, crtc_state,
8895 &fp, &reduced_clock,
8896 has_reduced_clock ? &fp2 : NULL);
8898 crtc_state->dpll_hw_state.dpll = dpll;
8899 crtc_state->dpll_hw_state.fp0 = fp;
8900 if (has_reduced_clock)
8901 crtc_state->dpll_hw_state.fp1 = fp2;
8903 crtc_state->dpll_hw_state.fp1 = fp;
8905 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8907 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8908 pipe_name(crtc->pipe));
8913 if (is_lvds && has_reduced_clock)
8914 crtc->lowfreq_avail = true;
8916 crtc->lowfreq_avail = false;
8921 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8922 struct intel_link_m_n *m_n)
8924 struct drm_device *dev = crtc->base.dev;
8925 struct drm_i915_private *dev_priv = dev->dev_private;
8926 enum pipe pipe = crtc->pipe;
8928 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8929 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8930 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8932 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8933 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8934 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8937 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8938 enum transcoder transcoder,
8939 struct intel_link_m_n *m_n,
8940 struct intel_link_m_n *m2_n2)
8942 struct drm_device *dev = crtc->base.dev;
8943 struct drm_i915_private *dev_priv = dev->dev_private;
8944 enum pipe pipe = crtc->pipe;
8946 if (INTEL_INFO(dev)->gen >= 5) {
8947 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8948 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8949 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8951 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8952 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8953 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8955 * gen < 8) and if DRRS is supported (to make sure the
8956 * registers are not unnecessarily read).
8958 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8959 crtc->config->has_drrs) {
8960 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8961 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8962 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8964 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8965 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8966 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8969 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8970 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8971 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8973 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8974 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8975 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8979 void intel_dp_get_m_n(struct intel_crtc *crtc,
8980 struct intel_crtc_state *pipe_config)
8982 if (pipe_config->has_pch_encoder)
8983 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8985 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8986 &pipe_config->dp_m_n,
8987 &pipe_config->dp_m2_n2);
8990 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8991 struct intel_crtc_state *pipe_config)
8993 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8994 &pipe_config->fdi_m_n, NULL);
8997 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8998 struct intel_crtc_state *pipe_config)
9000 struct drm_device *dev = crtc->base.dev;
9001 struct drm_i915_private *dev_priv = dev->dev_private;
9002 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9003 uint32_t ps_ctrl = 0;
9007 /* find scaler attached to this pipe */
9008 for (i = 0; i < crtc->num_scalers; i++) {
9009 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9010 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9012 pipe_config->pch_pfit.enabled = true;
9013 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9014 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9019 scaler_state->scaler_id = id;
9021 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9023 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9028 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9029 struct intel_initial_plane_config *plane_config)
9031 struct drm_device *dev = crtc->base.dev;
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 u32 val, base, offset, stride_mult, tiling;
9034 int pipe = crtc->pipe;
9035 int fourcc, pixel_format;
9036 unsigned int aligned_height;
9037 struct drm_framebuffer *fb;
9038 struct intel_framebuffer *intel_fb;
9040 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9042 DRM_DEBUG_KMS("failed to alloc fb\n");
9046 fb = &intel_fb->base;
9048 val = I915_READ(PLANE_CTL(pipe, 0));
9049 if (!(val & PLANE_CTL_ENABLE))
9052 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9053 fourcc = skl_format_to_fourcc(pixel_format,
9054 val & PLANE_CTL_ORDER_RGBX,
9055 val & PLANE_CTL_ALPHA_MASK);
9056 fb->pixel_format = fourcc;
9057 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9059 tiling = val & PLANE_CTL_TILED_MASK;
9061 case PLANE_CTL_TILED_LINEAR:
9062 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9064 case PLANE_CTL_TILED_X:
9065 plane_config->tiling = I915_TILING_X;
9066 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9068 case PLANE_CTL_TILED_Y:
9069 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9071 case PLANE_CTL_TILED_YF:
9072 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9075 MISSING_CASE(tiling);
9079 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9080 plane_config->base = base;
9082 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9084 val = I915_READ(PLANE_SIZE(pipe, 0));
9085 fb->height = ((val >> 16) & 0xfff) + 1;
9086 fb->width = ((val >> 0) & 0x1fff) + 1;
9088 val = I915_READ(PLANE_STRIDE(pipe, 0));
9089 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9091 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9093 aligned_height = intel_fb_align_height(dev, fb->height,
9097 plane_config->size = fb->pitches[0] * aligned_height;
9099 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9100 pipe_name(pipe), fb->width, fb->height,
9101 fb->bits_per_pixel, base, fb->pitches[0],
9102 plane_config->size);
9104 plane_config->fb = intel_fb;
9111 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9112 struct intel_crtc_state *pipe_config)
9114 struct drm_device *dev = crtc->base.dev;
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9118 tmp = I915_READ(PF_CTL(crtc->pipe));
9120 if (tmp & PF_ENABLE) {
9121 pipe_config->pch_pfit.enabled = true;
9122 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9123 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9125 /* We currently do not free assignements of panel fitters on
9126 * ivb/hsw (since we don't use the higher upscaling modes which
9127 * differentiates them) so just WARN about this case for now. */
9129 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9130 PF_PIPE_SEL_IVB(crtc->pipe));
9136 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9137 struct intel_initial_plane_config *plane_config)
9139 struct drm_device *dev = crtc->base.dev;
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141 u32 val, base, offset;
9142 int pipe = crtc->pipe;
9143 int fourcc, pixel_format;
9144 unsigned int aligned_height;
9145 struct drm_framebuffer *fb;
9146 struct intel_framebuffer *intel_fb;
9148 val = I915_READ(DSPCNTR(pipe));
9149 if (!(val & DISPLAY_PLANE_ENABLE))
9152 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9154 DRM_DEBUG_KMS("failed to alloc fb\n");
9158 fb = &intel_fb->base;
9160 if (INTEL_INFO(dev)->gen >= 4) {
9161 if (val & DISPPLANE_TILED) {
9162 plane_config->tiling = I915_TILING_X;
9163 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9167 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9168 fourcc = i9xx_format_to_fourcc(pixel_format);
9169 fb->pixel_format = fourcc;
9170 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9172 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9173 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9174 offset = I915_READ(DSPOFFSET(pipe));
9176 if (plane_config->tiling)
9177 offset = I915_READ(DSPTILEOFF(pipe));
9179 offset = I915_READ(DSPLINOFF(pipe));
9181 plane_config->base = base;
9183 val = I915_READ(PIPESRC(pipe));
9184 fb->width = ((val >> 16) & 0xfff) + 1;
9185 fb->height = ((val >> 0) & 0xfff) + 1;
9187 val = I915_READ(DSPSTRIDE(pipe));
9188 fb->pitches[0] = val & 0xffffffc0;
9190 aligned_height = intel_fb_align_height(dev, fb->height,
9194 plane_config->size = fb->pitches[0] * aligned_height;
9196 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9197 pipe_name(pipe), fb->width, fb->height,
9198 fb->bits_per_pixel, base, fb->pitches[0],
9199 plane_config->size);
9201 plane_config->fb = intel_fb;
9204 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9205 struct intel_crtc_state *pipe_config)
9207 struct drm_device *dev = crtc->base.dev;
9208 struct drm_i915_private *dev_priv = dev->dev_private;
9209 enum intel_display_power_domain power_domain;
9213 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9214 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9217 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9218 pipe_config->shared_dpll = NULL;
9221 tmp = I915_READ(PIPECONF(crtc->pipe));
9222 if (!(tmp & PIPECONF_ENABLE))
9225 switch (tmp & PIPECONF_BPC_MASK) {
9227 pipe_config->pipe_bpp = 18;
9230 pipe_config->pipe_bpp = 24;
9232 case PIPECONF_10BPC:
9233 pipe_config->pipe_bpp = 30;
9235 case PIPECONF_12BPC:
9236 pipe_config->pipe_bpp = 36;
9242 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9243 pipe_config->limited_color_range = true;
9245 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9246 struct intel_shared_dpll *pll;
9247 enum intel_dpll_id pll_id;
9249 pipe_config->has_pch_encoder = true;
9251 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9252 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9253 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9255 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9257 if (HAS_PCH_IBX(dev_priv->dev)) {
9258 pll_id = (enum intel_dpll_id) crtc->pipe;
9260 tmp = I915_READ(PCH_DPLL_SEL);
9261 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9262 pll_id = DPLL_ID_PCH_PLL_B;
9264 pll_id= DPLL_ID_PCH_PLL_A;
9267 pipe_config->shared_dpll =
9268 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9269 pll = pipe_config->shared_dpll;
9271 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9272 &pipe_config->dpll_hw_state));
9274 tmp = pipe_config->dpll_hw_state.dpll;
9275 pipe_config->pixel_multiplier =
9276 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9277 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9279 ironlake_pch_clock_get(crtc, pipe_config);
9281 pipe_config->pixel_multiplier = 1;
9284 intel_get_pipe_timings(crtc, pipe_config);
9285 intel_get_pipe_src_size(crtc, pipe_config);
9287 ironlake_get_pfit_config(crtc, pipe_config);
9292 intel_display_power_put(dev_priv, power_domain);
9297 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9299 struct drm_device *dev = dev_priv->dev;
9300 struct intel_crtc *crtc;
9302 for_each_intel_crtc(dev, crtc)
9303 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9304 pipe_name(crtc->pipe));
9306 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9307 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9308 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9309 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9310 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9311 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9312 "CPU PWM1 enabled\n");
9313 if (IS_HASWELL(dev))
9314 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9315 "CPU PWM2 enabled\n");
9316 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9317 "PCH PWM1 enabled\n");
9318 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9319 "Utility pin enabled\n");
9320 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9323 * In theory we can still leave IRQs enabled, as long as only the HPD
9324 * interrupts remain enabled. We used to check for that, but since it's
9325 * gen-specific and since we only disable LCPLL after we fully disable
9326 * the interrupts, the check below should be enough.
9328 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9331 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9333 struct drm_device *dev = dev_priv->dev;
9335 if (IS_HASWELL(dev))
9336 return I915_READ(D_COMP_HSW);
9338 return I915_READ(D_COMP_BDW);
9341 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9343 struct drm_device *dev = dev_priv->dev;
9345 if (IS_HASWELL(dev)) {
9346 mutex_lock(&dev_priv->rps.hw_lock);
9347 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9349 DRM_ERROR("Failed to write to D_COMP\n");
9350 mutex_unlock(&dev_priv->rps.hw_lock);
9352 I915_WRITE(D_COMP_BDW, val);
9353 POSTING_READ(D_COMP_BDW);
9358 * This function implements pieces of two sequences from BSpec:
9359 * - Sequence for display software to disable LCPLL
9360 * - Sequence for display software to allow package C8+
9361 * The steps implemented here are just the steps that actually touch the LCPLL
9362 * register. Callers should take care of disabling all the display engine
9363 * functions, doing the mode unset, fixing interrupts, etc.
9365 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9366 bool switch_to_fclk, bool allow_power_down)
9370 assert_can_disable_lcpll(dev_priv);
9372 val = I915_READ(LCPLL_CTL);
9374 if (switch_to_fclk) {
9375 val |= LCPLL_CD_SOURCE_FCLK;
9376 I915_WRITE(LCPLL_CTL, val);
9378 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9379 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9380 DRM_ERROR("Switching to FCLK failed\n");
9382 val = I915_READ(LCPLL_CTL);
9385 val |= LCPLL_PLL_DISABLE;
9386 I915_WRITE(LCPLL_CTL, val);
9387 POSTING_READ(LCPLL_CTL);
9389 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9390 DRM_ERROR("LCPLL still locked\n");
9392 val = hsw_read_dcomp(dev_priv);
9393 val |= D_COMP_COMP_DISABLE;
9394 hsw_write_dcomp(dev_priv, val);
9397 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9399 DRM_ERROR("D_COMP RCOMP still in progress\n");
9401 if (allow_power_down) {
9402 val = I915_READ(LCPLL_CTL);
9403 val |= LCPLL_POWER_DOWN_ALLOW;
9404 I915_WRITE(LCPLL_CTL, val);
9405 POSTING_READ(LCPLL_CTL);
9410 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9413 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9417 val = I915_READ(LCPLL_CTL);
9419 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9420 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9424 * Make sure we're not on PC8 state before disabling PC8, otherwise
9425 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9427 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9429 if (val & LCPLL_POWER_DOWN_ALLOW) {
9430 val &= ~LCPLL_POWER_DOWN_ALLOW;
9431 I915_WRITE(LCPLL_CTL, val);
9432 POSTING_READ(LCPLL_CTL);
9435 val = hsw_read_dcomp(dev_priv);
9436 val |= D_COMP_COMP_FORCE;
9437 val &= ~D_COMP_COMP_DISABLE;
9438 hsw_write_dcomp(dev_priv, val);
9440 val = I915_READ(LCPLL_CTL);
9441 val &= ~LCPLL_PLL_DISABLE;
9442 I915_WRITE(LCPLL_CTL, val);
9444 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9445 DRM_ERROR("LCPLL not locked yet\n");
9447 if (val & LCPLL_CD_SOURCE_FCLK) {
9448 val = I915_READ(LCPLL_CTL);
9449 val &= ~LCPLL_CD_SOURCE_FCLK;
9450 I915_WRITE(LCPLL_CTL, val);
9452 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9453 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9454 DRM_ERROR("Switching back to LCPLL failed\n");
9457 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9458 intel_update_cdclk(dev_priv->dev);
9462 * Package states C8 and deeper are really deep PC states that can only be
9463 * reached when all the devices on the system allow it, so even if the graphics
9464 * device allows PC8+, it doesn't mean the system will actually get to these
9465 * states. Our driver only allows PC8+ when going into runtime PM.
9467 * The requirements for PC8+ are that all the outputs are disabled, the power
9468 * well is disabled and most interrupts are disabled, and these are also
9469 * requirements for runtime PM. When these conditions are met, we manually do
9470 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9471 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9474 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9475 * the state of some registers, so when we come back from PC8+ we need to
9476 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9477 * need to take care of the registers kept by RC6. Notice that this happens even
9478 * if we don't put the device in PCI D3 state (which is what currently happens
9479 * because of the runtime PM support).
9481 * For more, read "Display Sequences for Package C8" on the hardware
9484 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9486 struct drm_device *dev = dev_priv->dev;
9489 DRM_DEBUG_KMS("Enabling package C8+\n");
9491 if (HAS_PCH_LPT_LP(dev)) {
9492 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9493 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9494 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9497 lpt_disable_clkout_dp(dev);
9498 hsw_disable_lcpll(dev_priv, true, true);
9501 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9503 struct drm_device *dev = dev_priv->dev;
9506 DRM_DEBUG_KMS("Disabling package C8+\n");
9508 hsw_restore_lcpll(dev_priv);
9509 lpt_init_pch_refclk(dev);
9511 if (HAS_PCH_LPT_LP(dev)) {
9512 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9513 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9514 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9518 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9520 struct drm_device *dev = old_state->dev;
9521 struct intel_atomic_state *old_intel_state =
9522 to_intel_atomic_state(old_state);
9523 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9525 broxton_set_cdclk(dev, req_cdclk);
9528 /* compute the max rate for new configuration */
9529 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9531 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9532 struct drm_i915_private *dev_priv = state->dev->dev_private;
9533 struct drm_crtc *crtc;
9534 struct drm_crtc_state *cstate;
9535 struct intel_crtc_state *crtc_state;
9536 unsigned max_pixel_rate = 0, i;
9539 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9540 sizeof(intel_state->min_pixclk));
9542 for_each_crtc_in_state(state, crtc, cstate, i) {
9545 crtc_state = to_intel_crtc_state(cstate);
9546 if (!crtc_state->base.enable) {
9547 intel_state->min_pixclk[i] = 0;
9551 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9553 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9554 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9555 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9557 intel_state->min_pixclk[i] = pixel_rate;
9560 for_each_pipe(dev_priv, pipe)
9561 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9563 return max_pixel_rate;
9566 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9568 struct drm_i915_private *dev_priv = dev->dev_private;
9572 if (WARN((I915_READ(LCPLL_CTL) &
9573 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9574 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9575 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9576 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9577 "trying to change cdclk frequency with cdclk not enabled\n"))
9580 mutex_lock(&dev_priv->rps.hw_lock);
9581 ret = sandybridge_pcode_write(dev_priv,
9582 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9583 mutex_unlock(&dev_priv->rps.hw_lock);
9585 DRM_ERROR("failed to inform pcode about cdclk change\n");
9589 val = I915_READ(LCPLL_CTL);
9590 val |= LCPLL_CD_SOURCE_FCLK;
9591 I915_WRITE(LCPLL_CTL, val);
9593 if (wait_for_us(I915_READ(LCPLL_CTL) &
9594 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9595 DRM_ERROR("Switching to FCLK failed\n");
9597 val = I915_READ(LCPLL_CTL);
9598 val &= ~LCPLL_CLK_FREQ_MASK;
9602 val |= LCPLL_CLK_FREQ_450;
9606 val |= LCPLL_CLK_FREQ_54O_BDW;
9610 val |= LCPLL_CLK_FREQ_337_5_BDW;
9614 val |= LCPLL_CLK_FREQ_675_BDW;
9618 WARN(1, "invalid cdclk frequency\n");
9622 I915_WRITE(LCPLL_CTL, val);
9624 val = I915_READ(LCPLL_CTL);
9625 val &= ~LCPLL_CD_SOURCE_FCLK;
9626 I915_WRITE(LCPLL_CTL, val);
9628 if (wait_for_us((I915_READ(LCPLL_CTL) &
9629 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9630 DRM_ERROR("Switching back to LCPLL failed\n");
9632 mutex_lock(&dev_priv->rps.hw_lock);
9633 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9634 mutex_unlock(&dev_priv->rps.hw_lock);
9636 intel_update_cdclk(dev);
9638 WARN(cdclk != dev_priv->cdclk_freq,
9639 "cdclk requested %d kHz but got %d kHz\n",
9640 cdclk, dev_priv->cdclk_freq);
9643 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9645 struct drm_i915_private *dev_priv = to_i915(state->dev);
9646 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9647 int max_pixclk = ilk_max_pixel_rate(state);
9651 * FIXME should also account for plane ratio
9652 * once 64bpp pixel formats are supported.
9654 if (max_pixclk > 540000)
9656 else if (max_pixclk > 450000)
9658 else if (max_pixclk > 337500)
9663 if (cdclk > dev_priv->max_cdclk_freq) {
9664 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9665 cdclk, dev_priv->max_cdclk_freq);
9669 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9670 if (!intel_state->active_crtcs)
9671 intel_state->dev_cdclk = 337500;
9676 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9678 struct drm_device *dev = old_state->dev;
9679 struct intel_atomic_state *old_intel_state =
9680 to_intel_atomic_state(old_state);
9681 unsigned req_cdclk = old_intel_state->dev_cdclk;
9683 broadwell_set_cdclk(dev, req_cdclk);
9686 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9687 struct intel_crtc_state *crtc_state)
9689 struct intel_encoder *intel_encoder =
9690 intel_ddi_get_crtc_new_encoder(crtc_state);
9692 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9693 if (!intel_ddi_pll_select(crtc, crtc_state))
9697 crtc->lowfreq_avail = false;
9702 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9704 struct intel_crtc_state *pipe_config)
9706 enum intel_dpll_id id;
9710 pipe_config->ddi_pll_sel = SKL_DPLL0;
9711 id = DPLL_ID_SKL_DPLL0;
9714 pipe_config->ddi_pll_sel = SKL_DPLL1;
9715 id = DPLL_ID_SKL_DPLL1;
9718 pipe_config->ddi_pll_sel = SKL_DPLL2;
9719 id = DPLL_ID_SKL_DPLL2;
9722 DRM_ERROR("Incorrect port type\n");
9726 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9729 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9731 struct intel_crtc_state *pipe_config)
9733 enum intel_dpll_id id;
9736 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9737 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9739 switch (pipe_config->ddi_pll_sel) {
9741 id = DPLL_ID_SKL_DPLL0;
9744 id = DPLL_ID_SKL_DPLL1;
9747 id = DPLL_ID_SKL_DPLL2;
9750 id = DPLL_ID_SKL_DPLL3;
9753 MISSING_CASE(pipe_config->ddi_pll_sel);
9757 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9760 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9762 struct intel_crtc_state *pipe_config)
9764 enum intel_dpll_id id;
9766 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9768 switch (pipe_config->ddi_pll_sel) {
9769 case PORT_CLK_SEL_WRPLL1:
9770 id = DPLL_ID_WRPLL1;
9772 case PORT_CLK_SEL_WRPLL2:
9773 id = DPLL_ID_WRPLL2;
9775 case PORT_CLK_SEL_SPLL:
9778 case PORT_CLK_SEL_LCPLL_810:
9779 id = DPLL_ID_LCPLL_810;
9781 case PORT_CLK_SEL_LCPLL_1350:
9782 id = DPLL_ID_LCPLL_1350;
9784 case PORT_CLK_SEL_LCPLL_2700:
9785 id = DPLL_ID_LCPLL_2700;
9788 MISSING_CASE(pipe_config->ddi_pll_sel);
9790 case PORT_CLK_SEL_NONE:
9794 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9797 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9798 struct intel_crtc_state *pipe_config,
9799 unsigned long *power_domain_mask)
9801 struct drm_device *dev = crtc->base.dev;
9802 struct drm_i915_private *dev_priv = dev->dev_private;
9803 enum intel_display_power_domain power_domain;
9806 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9809 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9810 * consistency and less surprising code; it's in always on power).
9812 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9813 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9814 enum pipe trans_edp_pipe;
9815 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9817 WARN(1, "unknown pipe linked to edp transcoder\n");
9818 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9819 case TRANS_DDI_EDP_INPUT_A_ON:
9820 trans_edp_pipe = PIPE_A;
9822 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9823 trans_edp_pipe = PIPE_B;
9825 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9826 trans_edp_pipe = PIPE_C;
9830 if (trans_edp_pipe == crtc->pipe)
9831 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9834 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9835 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9837 *power_domain_mask |= BIT(power_domain);
9839 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9841 return tmp & PIPECONF_ENABLE;
9844 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9845 struct intel_crtc_state *pipe_config,
9846 unsigned long *power_domain_mask)
9848 struct drm_device *dev = crtc->base.dev;
9849 struct drm_i915_private *dev_priv = dev->dev_private;
9850 enum intel_display_power_domain power_domain;
9852 enum transcoder cpu_transcoder;
9855 pipe_config->has_dsi_encoder = false;
9857 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9859 cpu_transcoder = TRANSCODER_DSI_A;
9861 cpu_transcoder = TRANSCODER_DSI_C;
9863 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9864 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9866 *power_domain_mask |= BIT(power_domain);
9868 /* XXX: this works for video mode only */
9869 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9870 if (!(tmp & DPI_ENABLE))
9873 tmp = I915_READ(MIPI_CTRL(port));
9874 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9877 pipe_config->cpu_transcoder = cpu_transcoder;
9878 pipe_config->has_dsi_encoder = true;
9882 return pipe_config->has_dsi_encoder;
9885 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9886 struct intel_crtc_state *pipe_config)
9888 struct drm_device *dev = crtc->base.dev;
9889 struct drm_i915_private *dev_priv = dev->dev_private;
9890 struct intel_shared_dpll *pll;
9894 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9896 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9898 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9899 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9900 else if (IS_BROXTON(dev))
9901 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9903 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9905 pll = pipe_config->shared_dpll;
9907 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9908 &pipe_config->dpll_hw_state));
9912 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9913 * DDI E. So just check whether this pipe is wired to DDI E and whether
9914 * the PCH transcoder is on.
9916 if (INTEL_INFO(dev)->gen < 9 &&
9917 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9918 pipe_config->has_pch_encoder = true;
9920 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9921 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9922 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9924 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9928 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9929 struct intel_crtc_state *pipe_config)
9931 struct drm_device *dev = crtc->base.dev;
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9933 enum intel_display_power_domain power_domain;
9934 unsigned long power_domain_mask;
9937 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9938 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9940 power_domain_mask = BIT(power_domain);
9942 pipe_config->shared_dpll = NULL;
9944 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9946 if (IS_BROXTON(dev_priv)) {
9947 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9948 &power_domain_mask);
9949 WARN_ON(active && pipe_config->has_dsi_encoder);
9950 if (pipe_config->has_dsi_encoder)
9957 if (!pipe_config->has_dsi_encoder) {
9958 haswell_get_ddi_port_state(crtc, pipe_config);
9959 intel_get_pipe_timings(crtc, pipe_config);
9962 intel_get_pipe_src_size(crtc, pipe_config);
9964 pipe_config->gamma_mode =
9965 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9967 if (INTEL_INFO(dev)->gen >= 9) {
9968 skl_init_scalers(dev, crtc, pipe_config);
9971 if (INTEL_INFO(dev)->gen >= 9) {
9972 pipe_config->scaler_state.scaler_id = -1;
9973 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9976 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9977 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9978 power_domain_mask |= BIT(power_domain);
9979 if (INTEL_INFO(dev)->gen >= 9)
9980 skylake_get_pfit_config(crtc, pipe_config);
9982 ironlake_get_pfit_config(crtc, pipe_config);
9985 if (IS_HASWELL(dev))
9986 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9987 (I915_READ(IPS_CTL) & IPS_ENABLE);
9989 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9990 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9991 pipe_config->pixel_multiplier =
9992 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9994 pipe_config->pixel_multiplier = 1;
9998 for_each_power_domain(power_domain, power_domain_mask)
9999 intel_display_power_put(dev_priv, power_domain);
10004 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10005 const struct intel_plane_state *plane_state)
10007 struct drm_device *dev = crtc->dev;
10008 struct drm_i915_private *dev_priv = dev->dev_private;
10009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10010 uint32_t cntl = 0, size = 0;
10012 if (plane_state && plane_state->visible) {
10013 unsigned int width = plane_state->base.crtc_w;
10014 unsigned int height = plane_state->base.crtc_h;
10015 unsigned int stride = roundup_pow_of_two(width) * 4;
10019 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10030 cntl |= CURSOR_ENABLE |
10031 CURSOR_GAMMA_ENABLE |
10032 CURSOR_FORMAT_ARGB |
10033 CURSOR_STRIDE(stride);
10035 size = (height << 12) | width;
10038 if (intel_crtc->cursor_cntl != 0 &&
10039 (intel_crtc->cursor_base != base ||
10040 intel_crtc->cursor_size != size ||
10041 intel_crtc->cursor_cntl != cntl)) {
10042 /* On these chipsets we can only modify the base/size/stride
10043 * whilst the cursor is disabled.
10045 I915_WRITE(CURCNTR(PIPE_A), 0);
10046 POSTING_READ(CURCNTR(PIPE_A));
10047 intel_crtc->cursor_cntl = 0;
10050 if (intel_crtc->cursor_base != base) {
10051 I915_WRITE(CURBASE(PIPE_A), base);
10052 intel_crtc->cursor_base = base;
10055 if (intel_crtc->cursor_size != size) {
10056 I915_WRITE(CURSIZE, size);
10057 intel_crtc->cursor_size = size;
10060 if (intel_crtc->cursor_cntl != cntl) {
10061 I915_WRITE(CURCNTR(PIPE_A), cntl);
10062 POSTING_READ(CURCNTR(PIPE_A));
10063 intel_crtc->cursor_cntl = cntl;
10067 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10068 const struct intel_plane_state *plane_state)
10070 struct drm_device *dev = crtc->dev;
10071 struct drm_i915_private *dev_priv = dev->dev_private;
10072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10073 int pipe = intel_crtc->pipe;
10076 if (plane_state && plane_state->visible) {
10077 cntl = MCURSOR_GAMMA_ENABLE;
10078 switch (plane_state->base.crtc_w) {
10080 cntl |= CURSOR_MODE_64_ARGB_AX;
10083 cntl |= CURSOR_MODE_128_ARGB_AX;
10086 cntl |= CURSOR_MODE_256_ARGB_AX;
10089 MISSING_CASE(plane_state->base.crtc_w);
10092 cntl |= pipe << 28; /* Connect to correct pipe */
10095 cntl |= CURSOR_PIPE_CSC_ENABLE;
10097 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10098 cntl |= CURSOR_ROTATE_180;
10101 if (intel_crtc->cursor_cntl != cntl) {
10102 I915_WRITE(CURCNTR(pipe), cntl);
10103 POSTING_READ(CURCNTR(pipe));
10104 intel_crtc->cursor_cntl = cntl;
10107 /* and commit changes on next vblank */
10108 I915_WRITE(CURBASE(pipe), base);
10109 POSTING_READ(CURBASE(pipe));
10111 intel_crtc->cursor_base = base;
10114 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10115 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10116 const struct intel_plane_state *plane_state)
10118 struct drm_device *dev = crtc->dev;
10119 struct drm_i915_private *dev_priv = dev->dev_private;
10120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10121 int pipe = intel_crtc->pipe;
10122 u32 base = intel_crtc->cursor_addr;
10126 int x = plane_state->base.crtc_x;
10127 int y = plane_state->base.crtc_y;
10130 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10133 pos |= x << CURSOR_X_SHIFT;
10136 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10139 pos |= y << CURSOR_Y_SHIFT;
10141 /* ILK+ do this automagically */
10142 if (HAS_GMCH_DISPLAY(dev) &&
10143 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10144 base += (plane_state->base.crtc_h *
10145 plane_state->base.crtc_w - 1) * 4;
10149 I915_WRITE(CURPOS(pipe), pos);
10151 if (IS_845G(dev) || IS_I865G(dev))
10152 i845_update_cursor(crtc, base, plane_state);
10154 i9xx_update_cursor(crtc, base, plane_state);
10157 static bool cursor_size_ok(struct drm_device *dev,
10158 uint32_t width, uint32_t height)
10160 if (width == 0 || height == 0)
10164 * 845g/865g are special in that they are only limited by
10165 * the width of their cursors, the height is arbitrary up to
10166 * the precision of the register. Everything else requires
10167 * square cursors, limited to a few power-of-two sizes.
10169 if (IS_845G(dev) || IS_I865G(dev)) {
10170 if ((width & 63) != 0)
10173 if (width > (IS_845G(dev) ? 64 : 512))
10179 switch (width | height) {
10194 /* VESA 640x480x72Hz mode to set on the pipe */
10195 static struct drm_display_mode load_detect_mode = {
10196 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10197 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10200 struct drm_framebuffer *
10201 __intel_framebuffer_create(struct drm_device *dev,
10202 struct drm_mode_fb_cmd2 *mode_cmd,
10203 struct drm_i915_gem_object *obj)
10205 struct intel_framebuffer *intel_fb;
10208 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10210 return ERR_PTR(-ENOMEM);
10212 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10216 return &intel_fb->base;
10220 return ERR_PTR(ret);
10223 static struct drm_framebuffer *
10224 intel_framebuffer_create(struct drm_device *dev,
10225 struct drm_mode_fb_cmd2 *mode_cmd,
10226 struct drm_i915_gem_object *obj)
10228 struct drm_framebuffer *fb;
10231 ret = i915_mutex_lock_interruptible(dev);
10233 return ERR_PTR(ret);
10234 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10235 mutex_unlock(&dev->struct_mutex);
10241 intel_framebuffer_pitch_for_width(int width, int bpp)
10243 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10244 return ALIGN(pitch, 64);
10248 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10250 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10251 return PAGE_ALIGN(pitch * mode->vdisplay);
10254 static struct drm_framebuffer *
10255 intel_framebuffer_create_for_mode(struct drm_device *dev,
10256 struct drm_display_mode *mode,
10257 int depth, int bpp)
10259 struct drm_framebuffer *fb;
10260 struct drm_i915_gem_object *obj;
10261 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10263 obj = i915_gem_alloc_object(dev,
10264 intel_framebuffer_size_for_mode(mode, bpp));
10266 return ERR_PTR(-ENOMEM);
10268 mode_cmd.width = mode->hdisplay;
10269 mode_cmd.height = mode->vdisplay;
10270 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10272 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10274 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10276 drm_gem_object_unreference_unlocked(&obj->base);
10281 static struct drm_framebuffer *
10282 mode_fits_in_fbdev(struct drm_device *dev,
10283 struct drm_display_mode *mode)
10285 #ifdef CONFIG_DRM_FBDEV_EMULATION
10286 struct drm_i915_private *dev_priv = dev->dev_private;
10287 struct drm_i915_gem_object *obj;
10288 struct drm_framebuffer *fb;
10290 if (!dev_priv->fbdev)
10293 if (!dev_priv->fbdev->fb)
10296 obj = dev_priv->fbdev->fb->obj;
10299 fb = &dev_priv->fbdev->fb->base;
10300 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10301 fb->bits_per_pixel))
10304 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10307 drm_framebuffer_reference(fb);
10314 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10315 struct drm_crtc *crtc,
10316 struct drm_display_mode *mode,
10317 struct drm_framebuffer *fb,
10320 struct drm_plane_state *plane_state;
10321 int hdisplay, vdisplay;
10324 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10325 if (IS_ERR(plane_state))
10326 return PTR_ERR(plane_state);
10329 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10331 hdisplay = vdisplay = 0;
10333 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10336 drm_atomic_set_fb_for_plane(plane_state, fb);
10337 plane_state->crtc_x = 0;
10338 plane_state->crtc_y = 0;
10339 plane_state->crtc_w = hdisplay;
10340 plane_state->crtc_h = vdisplay;
10341 plane_state->src_x = x << 16;
10342 plane_state->src_y = y << 16;
10343 plane_state->src_w = hdisplay << 16;
10344 plane_state->src_h = vdisplay << 16;
10349 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10350 struct drm_display_mode *mode,
10351 struct intel_load_detect_pipe *old,
10352 struct drm_modeset_acquire_ctx *ctx)
10354 struct intel_crtc *intel_crtc;
10355 struct intel_encoder *intel_encoder =
10356 intel_attached_encoder(connector);
10357 struct drm_crtc *possible_crtc;
10358 struct drm_encoder *encoder = &intel_encoder->base;
10359 struct drm_crtc *crtc = NULL;
10360 struct drm_device *dev = encoder->dev;
10361 struct drm_framebuffer *fb;
10362 struct drm_mode_config *config = &dev->mode_config;
10363 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10364 struct drm_connector_state *connector_state;
10365 struct intel_crtc_state *crtc_state;
10368 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10369 connector->base.id, connector->name,
10370 encoder->base.id, encoder->name);
10372 old->restore_state = NULL;
10375 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10380 * Algorithm gets a little messy:
10382 * - if the connector already has an assigned crtc, use it (but make
10383 * sure it's on first)
10385 * - try to find the first unused crtc that can drive this connector,
10386 * and use that if we find one
10389 /* See if we already have a CRTC for this connector */
10390 if (connector->state->crtc) {
10391 crtc = connector->state->crtc;
10393 ret = drm_modeset_lock(&crtc->mutex, ctx);
10397 /* Make sure the crtc and connector are running */
10401 /* Find an unused one (if possible) */
10402 for_each_crtc(dev, possible_crtc) {
10404 if (!(encoder->possible_crtcs & (1 << i)))
10407 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10411 if (possible_crtc->state->enable) {
10412 drm_modeset_unlock(&possible_crtc->mutex);
10416 crtc = possible_crtc;
10421 * If we didn't find an unused CRTC, don't use any.
10424 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10429 intel_crtc = to_intel_crtc(crtc);
10431 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10435 state = drm_atomic_state_alloc(dev);
10436 restore_state = drm_atomic_state_alloc(dev);
10437 if (!state || !restore_state) {
10442 state->acquire_ctx = ctx;
10443 restore_state->acquire_ctx = ctx;
10445 connector_state = drm_atomic_get_connector_state(state, connector);
10446 if (IS_ERR(connector_state)) {
10447 ret = PTR_ERR(connector_state);
10451 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10455 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10456 if (IS_ERR(crtc_state)) {
10457 ret = PTR_ERR(crtc_state);
10461 crtc_state->base.active = crtc_state->base.enable = true;
10464 mode = &load_detect_mode;
10466 /* We need a framebuffer large enough to accommodate all accesses
10467 * that the plane may generate whilst we perform load detection.
10468 * We can not rely on the fbcon either being present (we get called
10469 * during its initialisation to detect all boot displays, or it may
10470 * not even exist) or that it is large enough to satisfy the
10473 fb = mode_fits_in_fbdev(dev, mode);
10475 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10476 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10478 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10480 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10484 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10488 drm_framebuffer_unreference(fb);
10490 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10494 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10496 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10498 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10500 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10504 ret = drm_atomic_commit(state);
10506 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10510 old->restore_state = restore_state;
10512 /* let the connector get through one full cycle before testing */
10513 intel_wait_for_vblank(dev, intel_crtc->pipe);
10517 drm_atomic_state_free(state);
10518 drm_atomic_state_free(restore_state);
10519 restore_state = state = NULL;
10521 if (ret == -EDEADLK) {
10522 drm_modeset_backoff(ctx);
10529 void intel_release_load_detect_pipe(struct drm_connector *connector,
10530 struct intel_load_detect_pipe *old,
10531 struct drm_modeset_acquire_ctx *ctx)
10533 struct intel_encoder *intel_encoder =
10534 intel_attached_encoder(connector);
10535 struct drm_encoder *encoder = &intel_encoder->base;
10536 struct drm_atomic_state *state = old->restore_state;
10539 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10540 connector->base.id, connector->name,
10541 encoder->base.id, encoder->name);
10546 ret = drm_atomic_commit(state);
10548 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10549 drm_atomic_state_free(state);
10553 static int i9xx_pll_refclk(struct drm_device *dev,
10554 const struct intel_crtc_state *pipe_config)
10556 struct drm_i915_private *dev_priv = dev->dev_private;
10557 u32 dpll = pipe_config->dpll_hw_state.dpll;
10559 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10560 return dev_priv->vbt.lvds_ssc_freq;
10561 else if (HAS_PCH_SPLIT(dev))
10563 else if (!IS_GEN2(dev))
10569 /* Returns the clock of the currently programmed mode of the given pipe. */
10570 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10571 struct intel_crtc_state *pipe_config)
10573 struct drm_device *dev = crtc->base.dev;
10574 struct drm_i915_private *dev_priv = dev->dev_private;
10575 int pipe = pipe_config->cpu_transcoder;
10576 u32 dpll = pipe_config->dpll_hw_state.dpll;
10578 intel_clock_t clock;
10580 int refclk = i9xx_pll_refclk(dev, pipe_config);
10582 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10583 fp = pipe_config->dpll_hw_state.fp0;
10585 fp = pipe_config->dpll_hw_state.fp1;
10587 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10588 if (IS_PINEVIEW(dev)) {
10589 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10590 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10592 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10593 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10596 if (!IS_GEN2(dev)) {
10597 if (IS_PINEVIEW(dev))
10598 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10599 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10601 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10602 DPLL_FPA01_P1_POST_DIV_SHIFT);
10604 switch (dpll & DPLL_MODE_MASK) {
10605 case DPLLB_MODE_DAC_SERIAL:
10606 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10609 case DPLLB_MODE_LVDS:
10610 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10614 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10615 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10619 if (IS_PINEVIEW(dev))
10620 port_clock = pnv_calc_dpll_params(refclk, &clock);
10622 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10624 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10625 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10628 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10629 DPLL_FPA01_P1_POST_DIV_SHIFT);
10631 if (lvds & LVDS_CLKB_POWER_UP)
10636 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10639 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10640 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10642 if (dpll & PLL_P2_DIVIDE_BY_4)
10648 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10652 * This value includes pixel_multiplier. We will use
10653 * port_clock to compute adjusted_mode.crtc_clock in the
10654 * encoder's get_config() function.
10656 pipe_config->port_clock = port_clock;
10659 int intel_dotclock_calculate(int link_freq,
10660 const struct intel_link_m_n *m_n)
10663 * The calculation for the data clock is:
10664 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10665 * But we want to avoid losing precison if possible, so:
10666 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10668 * and the link clock is simpler:
10669 * link_clock = (m * link_clock) / n
10675 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10678 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10679 struct intel_crtc_state *pipe_config)
10681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10683 /* read out port_clock from the DPLL */
10684 i9xx_crtc_clock_get(crtc, pipe_config);
10687 * In case there is an active pipe without active ports,
10688 * we may need some idea for the dotclock anyway.
10689 * Calculate one based on the FDI configuration.
10691 pipe_config->base.adjusted_mode.crtc_clock =
10692 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10693 &pipe_config->fdi_m_n);
10696 /** Returns the currently programmed mode of the given pipe. */
10697 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10698 struct drm_crtc *crtc)
10700 struct drm_i915_private *dev_priv = dev->dev_private;
10701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10703 struct drm_display_mode *mode;
10704 struct intel_crtc_state *pipe_config;
10705 int htot = I915_READ(HTOTAL(cpu_transcoder));
10706 int hsync = I915_READ(HSYNC(cpu_transcoder));
10707 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10708 int vsync = I915_READ(VSYNC(cpu_transcoder));
10709 enum pipe pipe = intel_crtc->pipe;
10711 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10715 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10716 if (!pipe_config) {
10722 * Construct a pipe_config sufficient for getting the clock info
10723 * back out of crtc_clock_get.
10725 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10726 * to use a real value here instead.
10728 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10729 pipe_config->pixel_multiplier = 1;
10730 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10731 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10732 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10733 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10735 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10736 mode->hdisplay = (htot & 0xffff) + 1;
10737 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10738 mode->hsync_start = (hsync & 0xffff) + 1;
10739 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10740 mode->vdisplay = (vtot & 0xffff) + 1;
10741 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10742 mode->vsync_start = (vsync & 0xffff) + 1;
10743 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10745 drm_mode_set_name(mode);
10747 kfree(pipe_config);
10752 void intel_mark_busy(struct drm_device *dev)
10754 struct drm_i915_private *dev_priv = dev->dev_private;
10756 if (dev_priv->mm.busy)
10759 intel_runtime_pm_get(dev_priv);
10760 i915_update_gfx_val(dev_priv);
10761 if (INTEL_INFO(dev)->gen >= 6)
10762 gen6_rps_busy(dev_priv);
10763 dev_priv->mm.busy = true;
10766 void intel_mark_idle(struct drm_device *dev)
10768 struct drm_i915_private *dev_priv = dev->dev_private;
10770 if (!dev_priv->mm.busy)
10773 dev_priv->mm.busy = false;
10775 if (INTEL_INFO(dev)->gen >= 6)
10776 gen6_rps_idle(dev->dev_private);
10778 intel_runtime_pm_put(dev_priv);
10781 static void intel_crtc_destroy(struct drm_crtc *crtc)
10783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10784 struct drm_device *dev = crtc->dev;
10785 struct intel_unpin_work *work;
10787 spin_lock_irq(&dev->event_lock);
10788 work = intel_crtc->unpin_work;
10789 intel_crtc->unpin_work = NULL;
10790 spin_unlock_irq(&dev->event_lock);
10793 cancel_work_sync(&work->work);
10797 drm_crtc_cleanup(crtc);
10802 static void intel_unpin_work_fn(struct work_struct *__work)
10804 struct intel_unpin_work *work =
10805 container_of(__work, struct intel_unpin_work, work);
10806 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10807 struct drm_device *dev = crtc->base.dev;
10808 struct drm_plane *primary = crtc->base.primary;
10810 mutex_lock(&dev->struct_mutex);
10811 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10812 drm_gem_object_unreference(&work->pending_flip_obj->base);
10814 if (work->flip_queued_req)
10815 i915_gem_request_assign(&work->flip_queued_req, NULL);
10816 mutex_unlock(&dev->struct_mutex);
10818 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10819 intel_fbc_post_update(crtc);
10820 drm_framebuffer_unreference(work->old_fb);
10822 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10823 atomic_dec(&crtc->unpin_work_count);
10828 static void do_intel_finish_page_flip(struct drm_device *dev,
10829 struct drm_crtc *crtc)
10831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10832 struct intel_unpin_work *work;
10833 unsigned long flags;
10835 /* Ignore early vblank irqs */
10836 if (intel_crtc == NULL)
10840 * This is called both by irq handlers and the reset code (to complete
10841 * lost pageflips) so needs the full irqsave spinlocks.
10843 spin_lock_irqsave(&dev->event_lock, flags);
10844 work = intel_crtc->unpin_work;
10846 /* Ensure we don't miss a work->pending update ... */
10849 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10850 spin_unlock_irqrestore(&dev->event_lock, flags);
10854 page_flip_completed(intel_crtc);
10856 spin_unlock_irqrestore(&dev->event_lock, flags);
10859 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10861 struct drm_i915_private *dev_priv = dev->dev_private;
10862 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10864 do_intel_finish_page_flip(dev, crtc);
10867 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10869 struct drm_i915_private *dev_priv = dev->dev_private;
10870 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10872 do_intel_finish_page_flip(dev, crtc);
10875 /* Is 'a' after or equal to 'b'? */
10876 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10878 return !((a - b) & 0x80000000);
10881 static bool page_flip_finished(struct intel_crtc *crtc)
10883 struct drm_device *dev = crtc->base.dev;
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10886 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10887 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10891 * The relevant registers doen't exist on pre-ctg.
10892 * As the flip done interrupt doesn't trigger for mmio
10893 * flips on gmch platforms, a flip count check isn't
10894 * really needed there. But since ctg has the registers,
10895 * include it in the check anyway.
10897 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10901 * BDW signals flip done immediately if the plane
10902 * is disabled, even if the plane enable is already
10903 * armed to occur at the next vblank :(
10907 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10908 * used the same base address. In that case the mmio flip might
10909 * have completed, but the CS hasn't even executed the flip yet.
10911 * A flip count check isn't enough as the CS might have updated
10912 * the base address just after start of vblank, but before we
10913 * managed to process the interrupt. This means we'd complete the
10914 * CS flip too soon.
10916 * Combining both checks should get us a good enough result. It may
10917 * still happen that the CS flip has been executed, but has not
10918 * yet actually completed. But in case the base address is the same
10919 * anyway, we don't really care.
10921 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10922 crtc->unpin_work->gtt_offset &&
10923 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10924 crtc->unpin_work->flip_count);
10927 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10929 struct drm_i915_private *dev_priv = dev->dev_private;
10930 struct intel_crtc *intel_crtc =
10931 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10932 unsigned long flags;
10936 * This is called both by irq handlers and the reset code (to complete
10937 * lost pageflips) so needs the full irqsave spinlocks.
10939 * NB: An MMIO update of the plane base pointer will also
10940 * generate a page-flip completion irq, i.e. every modeset
10941 * is also accompanied by a spurious intel_prepare_page_flip().
10943 spin_lock_irqsave(&dev->event_lock, flags);
10944 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10945 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10946 spin_unlock_irqrestore(&dev->event_lock, flags);
10949 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10951 /* Ensure that the work item is consistent when activating it ... */
10953 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10954 /* and that it is marked active as soon as the irq could fire. */
10958 static int intel_gen2_queue_flip(struct drm_device *dev,
10959 struct drm_crtc *crtc,
10960 struct drm_framebuffer *fb,
10961 struct drm_i915_gem_object *obj,
10962 struct drm_i915_gem_request *req,
10965 struct intel_engine_cs *engine = req->engine;
10966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10970 ret = intel_ring_begin(req, 6);
10974 /* Can't queue multiple flips, so wait for the previous
10975 * one to finish before executing the next.
10977 if (intel_crtc->plane)
10978 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10980 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10981 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
10982 intel_ring_emit(engine, MI_NOOP);
10983 intel_ring_emit(engine, MI_DISPLAY_FLIP |
10984 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10985 intel_ring_emit(engine, fb->pitches[0]);
10986 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
10987 intel_ring_emit(engine, 0); /* aux display base address, unused */
10989 intel_mark_page_flip_active(intel_crtc->unpin_work);
10993 static int intel_gen3_queue_flip(struct drm_device *dev,
10994 struct drm_crtc *crtc,
10995 struct drm_framebuffer *fb,
10996 struct drm_i915_gem_object *obj,
10997 struct drm_i915_gem_request *req,
11000 struct intel_engine_cs *engine = req->engine;
11001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11005 ret = intel_ring_begin(req, 6);
11009 if (intel_crtc->plane)
11010 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11012 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11013 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11014 intel_ring_emit(engine, MI_NOOP);
11015 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11016 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11017 intel_ring_emit(engine, fb->pitches[0]);
11018 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11019 intel_ring_emit(engine, MI_NOOP);
11021 intel_mark_page_flip_active(intel_crtc->unpin_work);
11025 static int intel_gen4_queue_flip(struct drm_device *dev,
11026 struct drm_crtc *crtc,
11027 struct drm_framebuffer *fb,
11028 struct drm_i915_gem_object *obj,
11029 struct drm_i915_gem_request *req,
11032 struct intel_engine_cs *engine = req->engine;
11033 struct drm_i915_private *dev_priv = dev->dev_private;
11034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11035 uint32_t pf, pipesrc;
11038 ret = intel_ring_begin(req, 4);
11042 /* i965+ uses the linear or tiled offsets from the
11043 * Display Registers (which do not change across a page-flip)
11044 * so we need only reprogram the base address.
11046 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11047 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11048 intel_ring_emit(engine, fb->pitches[0]);
11049 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11052 /* XXX Enabling the panel-fitter across page-flip is so far
11053 * untested on non-native modes, so ignore it for now.
11054 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11057 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11058 intel_ring_emit(engine, pf | pipesrc);
11060 intel_mark_page_flip_active(intel_crtc->unpin_work);
11064 static int intel_gen6_queue_flip(struct drm_device *dev,
11065 struct drm_crtc *crtc,
11066 struct drm_framebuffer *fb,
11067 struct drm_i915_gem_object *obj,
11068 struct drm_i915_gem_request *req,
11071 struct intel_engine_cs *engine = req->engine;
11072 struct drm_i915_private *dev_priv = dev->dev_private;
11073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11074 uint32_t pf, pipesrc;
11077 ret = intel_ring_begin(req, 4);
11081 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11082 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11083 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11084 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11086 /* Contrary to the suggestions in the documentation,
11087 * "Enable Panel Fitter" does not seem to be required when page
11088 * flipping with a non-native mode, and worse causes a normal
11090 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11093 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11094 intel_ring_emit(engine, pf | pipesrc);
11096 intel_mark_page_flip_active(intel_crtc->unpin_work);
11100 static int intel_gen7_queue_flip(struct drm_device *dev,
11101 struct drm_crtc *crtc,
11102 struct drm_framebuffer *fb,
11103 struct drm_i915_gem_object *obj,
11104 struct drm_i915_gem_request *req,
11107 struct intel_engine_cs *engine = req->engine;
11108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11109 uint32_t plane_bit = 0;
11112 switch (intel_crtc->plane) {
11114 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11117 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11120 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11123 WARN_ONCE(1, "unknown plane in flip command\n");
11128 if (engine->id == RCS) {
11131 * On Gen 8, SRM is now taking an extra dword to accommodate
11132 * 48bits addresses, and we need a NOOP for the batch size to
11140 * BSpec MI_DISPLAY_FLIP for IVB:
11141 * "The full packet must be contained within the same cache line."
11143 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11144 * cacheline, if we ever start emitting more commands before
11145 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11146 * then do the cacheline alignment, and finally emit the
11149 ret = intel_ring_cacheline_align(req);
11153 ret = intel_ring_begin(req, len);
11157 /* Unmask the flip-done completion message. Note that the bspec says that
11158 * we should do this for both the BCS and RCS, and that we must not unmask
11159 * more than one flip event at any time (or ensure that one flip message
11160 * can be sent by waiting for flip-done prior to queueing new flips).
11161 * Experimentation says that BCS works despite DERRMR masking all
11162 * flip-done completion events and that unmasking all planes at once
11163 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11164 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11166 if (engine->id == RCS) {
11167 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11168 intel_ring_emit_reg(engine, DERRMR);
11169 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11170 DERRMR_PIPEB_PRI_FLIP_DONE |
11171 DERRMR_PIPEC_PRI_FLIP_DONE));
11173 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11174 MI_SRM_LRM_GLOBAL_GTT);
11176 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11177 MI_SRM_LRM_GLOBAL_GTT);
11178 intel_ring_emit_reg(engine, DERRMR);
11179 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11180 if (IS_GEN8(dev)) {
11181 intel_ring_emit(engine, 0);
11182 intel_ring_emit(engine, MI_NOOP);
11186 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11187 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11188 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11189 intel_ring_emit(engine, (MI_NOOP));
11191 intel_mark_page_flip_active(intel_crtc->unpin_work);
11195 static bool use_mmio_flip(struct intel_engine_cs *engine,
11196 struct drm_i915_gem_object *obj)
11199 * This is not being used for older platforms, because
11200 * non-availability of flip done interrupt forces us to use
11201 * CS flips. Older platforms derive flip done using some clever
11202 * tricks involving the flip_pending status bits and vblank irqs.
11203 * So using MMIO flips there would disrupt this mechanism.
11206 if (engine == NULL)
11209 if (INTEL_INFO(engine->dev)->gen < 5)
11212 if (i915.use_mmio_flip < 0)
11214 else if (i915.use_mmio_flip > 0)
11216 else if (i915.enable_execlists)
11218 else if (obj->base.dma_buf &&
11219 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11223 return engine != i915_gem_request_get_engine(obj->last_write_req);
11226 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11227 unsigned int rotation,
11228 struct intel_unpin_work *work)
11230 struct drm_device *dev = intel_crtc->base.dev;
11231 struct drm_i915_private *dev_priv = dev->dev_private;
11232 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11233 const enum pipe pipe = intel_crtc->pipe;
11234 u32 ctl, stride, tile_height;
11236 ctl = I915_READ(PLANE_CTL(pipe, 0));
11237 ctl &= ~PLANE_CTL_TILED_MASK;
11238 switch (fb->modifier[0]) {
11239 case DRM_FORMAT_MOD_NONE:
11241 case I915_FORMAT_MOD_X_TILED:
11242 ctl |= PLANE_CTL_TILED_X;
11244 case I915_FORMAT_MOD_Y_TILED:
11245 ctl |= PLANE_CTL_TILED_Y;
11247 case I915_FORMAT_MOD_Yf_TILED:
11248 ctl |= PLANE_CTL_TILED_YF;
11251 MISSING_CASE(fb->modifier[0]);
11255 * The stride is either expressed as a multiple of 64 bytes chunks for
11256 * linear buffers or in number of tiles for tiled buffers.
11258 if (intel_rotation_90_or_270(rotation)) {
11259 /* stride = Surface height in tiles */
11260 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11261 stride = DIV_ROUND_UP(fb->height, tile_height);
11263 stride = fb->pitches[0] /
11264 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11269 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11270 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11272 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11273 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11275 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11276 POSTING_READ(PLANE_SURF(pipe, 0));
11279 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11280 struct intel_unpin_work *work)
11282 struct drm_device *dev = intel_crtc->base.dev;
11283 struct drm_i915_private *dev_priv = dev->dev_private;
11284 struct intel_framebuffer *intel_fb =
11285 to_intel_framebuffer(intel_crtc->base.primary->fb);
11286 struct drm_i915_gem_object *obj = intel_fb->obj;
11287 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11290 dspcntr = I915_READ(reg);
11292 if (obj->tiling_mode != I915_TILING_NONE)
11293 dspcntr |= DISPPLANE_TILED;
11295 dspcntr &= ~DISPPLANE_TILED;
11297 I915_WRITE(reg, dspcntr);
11299 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11300 POSTING_READ(DSPSURF(intel_crtc->plane));
11304 * XXX: This is the temporary way to update the plane registers until we get
11305 * around to using the usual plane update functions for MMIO flips
11307 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11309 struct intel_crtc *crtc = mmio_flip->crtc;
11310 struct intel_unpin_work *work;
11312 spin_lock_irq(&crtc->base.dev->event_lock);
11313 work = crtc->unpin_work;
11314 spin_unlock_irq(&crtc->base.dev->event_lock);
11318 intel_mark_page_flip_active(work);
11320 intel_pipe_update_start(crtc);
11322 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11323 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11325 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11326 ilk_do_mmio_flip(crtc, work);
11328 intel_pipe_update_end(crtc);
11331 static void intel_mmio_flip_work_func(struct work_struct *work)
11333 struct intel_mmio_flip *mmio_flip =
11334 container_of(work, struct intel_mmio_flip, work);
11335 struct intel_framebuffer *intel_fb =
11336 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11337 struct drm_i915_gem_object *obj = intel_fb->obj;
11339 if (mmio_flip->req) {
11340 WARN_ON(__i915_wait_request(mmio_flip->req,
11341 mmio_flip->crtc->reset_counter,
11343 &mmio_flip->i915->rps.mmioflips));
11344 i915_gem_request_unreference__unlocked(mmio_flip->req);
11347 /* For framebuffer backed by dmabuf, wait for fence */
11348 if (obj->base.dma_buf)
11349 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11351 MAX_SCHEDULE_TIMEOUT) < 0);
11353 intel_do_mmio_flip(mmio_flip);
11357 static int intel_queue_mmio_flip(struct drm_device *dev,
11358 struct drm_crtc *crtc,
11359 struct drm_i915_gem_object *obj)
11361 struct intel_mmio_flip *mmio_flip;
11363 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11364 if (mmio_flip == NULL)
11367 mmio_flip->i915 = to_i915(dev);
11368 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11369 mmio_flip->crtc = to_intel_crtc(crtc);
11370 mmio_flip->rotation = crtc->primary->state->rotation;
11372 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11373 schedule_work(&mmio_flip->work);
11378 static int intel_default_queue_flip(struct drm_device *dev,
11379 struct drm_crtc *crtc,
11380 struct drm_framebuffer *fb,
11381 struct drm_i915_gem_object *obj,
11382 struct drm_i915_gem_request *req,
11388 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11389 struct drm_crtc *crtc)
11391 struct drm_i915_private *dev_priv = dev->dev_private;
11392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11393 struct intel_unpin_work *work = intel_crtc->unpin_work;
11396 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11399 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11402 if (!work->enable_stall_check)
11405 if (work->flip_ready_vblank == 0) {
11406 if (work->flip_queued_req &&
11407 !i915_gem_request_completed(work->flip_queued_req, true))
11410 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11413 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11416 /* Potential stall - if we see that the flip has happened,
11417 * assume a missed interrupt. */
11418 if (INTEL_INFO(dev)->gen >= 4)
11419 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11421 addr = I915_READ(DSPADDR(intel_crtc->plane));
11423 /* There is a potential issue here with a false positive after a flip
11424 * to the same address. We could address this by checking for a
11425 * non-incrementing frame counter.
11427 return addr == work->gtt_offset;
11430 void intel_check_page_flip(struct drm_device *dev, int pipe)
11432 struct drm_i915_private *dev_priv = dev->dev_private;
11433 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11435 struct intel_unpin_work *work;
11437 WARN_ON(!in_interrupt());
11442 spin_lock(&dev->event_lock);
11443 work = intel_crtc->unpin_work;
11444 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11445 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11446 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11447 page_flip_completed(intel_crtc);
11450 if (work != NULL &&
11451 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11452 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11453 spin_unlock(&dev->event_lock);
11456 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11457 struct drm_framebuffer *fb,
11458 struct drm_pending_vblank_event *event,
11459 uint32_t page_flip_flags)
11461 struct drm_device *dev = crtc->dev;
11462 struct drm_i915_private *dev_priv = dev->dev_private;
11463 struct drm_framebuffer *old_fb = crtc->primary->fb;
11464 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11466 struct drm_plane *primary = crtc->primary;
11467 enum pipe pipe = intel_crtc->pipe;
11468 struct intel_unpin_work *work;
11469 struct intel_engine_cs *engine;
11471 struct drm_i915_gem_request *request = NULL;
11475 * drm_mode_page_flip_ioctl() should already catch this, but double
11476 * check to be safe. In the future we may enable pageflipping from
11477 * a disabled primary plane.
11479 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11482 /* Can't change pixel format via MI display flips. */
11483 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11487 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11488 * Note that pitch changes could also affect these register.
11490 if (INTEL_INFO(dev)->gen > 3 &&
11491 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11492 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11495 if (i915_terminally_wedged(&dev_priv->gpu_error))
11498 work = kzalloc(sizeof(*work), GFP_KERNEL);
11502 work->event = event;
11504 work->old_fb = old_fb;
11505 INIT_WORK(&work->work, intel_unpin_work_fn);
11507 ret = drm_crtc_vblank_get(crtc);
11511 /* We borrow the event spin lock for protecting unpin_work */
11512 spin_lock_irq(&dev->event_lock);
11513 if (intel_crtc->unpin_work) {
11514 /* Before declaring the flip queue wedged, check if
11515 * the hardware completed the operation behind our backs.
11517 if (__intel_pageflip_stall_check(dev, crtc)) {
11518 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11519 page_flip_completed(intel_crtc);
11521 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11522 spin_unlock_irq(&dev->event_lock);
11524 drm_crtc_vblank_put(crtc);
11529 intel_crtc->unpin_work = work;
11530 spin_unlock_irq(&dev->event_lock);
11532 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11533 flush_workqueue(dev_priv->wq);
11535 /* Reference the objects for the scheduled work. */
11536 drm_framebuffer_reference(work->old_fb);
11537 drm_gem_object_reference(&obj->base);
11539 crtc->primary->fb = fb;
11540 update_state_fb(crtc->primary);
11541 intel_fbc_pre_update(intel_crtc);
11543 work->pending_flip_obj = obj;
11545 ret = i915_mutex_lock_interruptible(dev);
11549 atomic_inc(&intel_crtc->unpin_work_count);
11550 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11552 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11553 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11555 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11556 engine = &dev_priv->engine[BCS];
11557 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11558 /* vlv: DISPLAY_FLIP fails to change tiling */
11560 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11561 engine = &dev_priv->engine[BCS];
11562 } else if (INTEL_INFO(dev)->gen >= 7) {
11563 engine = i915_gem_request_get_engine(obj->last_write_req);
11564 if (engine == NULL || engine->id != RCS)
11565 engine = &dev_priv->engine[BCS];
11567 engine = &dev_priv->engine[RCS];
11570 mmio_flip = use_mmio_flip(engine, obj);
11572 /* When using CS flips, we want to emit semaphores between rings.
11573 * However, when using mmio flips we will create a task to do the
11574 * synchronisation, so all we want here is to pin the framebuffer
11575 * into the display plane and skip any waits.
11578 ret = i915_gem_object_sync(obj, engine, &request);
11580 goto cleanup_pending;
11583 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11585 goto cleanup_pending;
11587 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11589 work->gtt_offset += intel_crtc->dspaddr_offset;
11592 ret = intel_queue_mmio_flip(dev, crtc, obj);
11594 goto cleanup_unpin;
11596 i915_gem_request_assign(&work->flip_queued_req,
11597 obj->last_write_req);
11600 request = i915_gem_request_alloc(engine, NULL);
11601 if (IS_ERR(request)) {
11602 ret = PTR_ERR(request);
11603 goto cleanup_unpin;
11607 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11610 goto cleanup_unpin;
11612 i915_gem_request_assign(&work->flip_queued_req, request);
11616 i915_add_request_no_flush(request);
11618 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11619 work->enable_stall_check = true;
11621 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11622 to_intel_plane(primary)->frontbuffer_bit);
11623 mutex_unlock(&dev->struct_mutex);
11625 intel_frontbuffer_flip_prepare(dev,
11626 to_intel_plane(primary)->frontbuffer_bit);
11628 trace_i915_flip_request(intel_crtc->plane, obj);
11633 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11635 if (!IS_ERR_OR_NULL(request))
11636 i915_gem_request_cancel(request);
11637 atomic_dec(&intel_crtc->unpin_work_count);
11638 mutex_unlock(&dev->struct_mutex);
11640 crtc->primary->fb = old_fb;
11641 update_state_fb(crtc->primary);
11643 drm_gem_object_unreference_unlocked(&obj->base);
11644 drm_framebuffer_unreference(work->old_fb);
11646 spin_lock_irq(&dev->event_lock);
11647 intel_crtc->unpin_work = NULL;
11648 spin_unlock_irq(&dev->event_lock);
11650 drm_crtc_vblank_put(crtc);
11655 struct drm_atomic_state *state;
11656 struct drm_plane_state *plane_state;
11659 state = drm_atomic_state_alloc(dev);
11662 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11665 plane_state = drm_atomic_get_plane_state(state, primary);
11666 ret = PTR_ERR_OR_ZERO(plane_state);
11668 drm_atomic_set_fb_for_plane(plane_state, fb);
11670 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11672 ret = drm_atomic_commit(state);
11675 if (ret == -EDEADLK) {
11676 drm_modeset_backoff(state->acquire_ctx);
11677 drm_atomic_state_clear(state);
11682 drm_atomic_state_free(state);
11684 if (ret == 0 && event) {
11685 spin_lock_irq(&dev->event_lock);
11686 drm_send_vblank_event(dev, pipe, event);
11687 spin_unlock_irq(&dev->event_lock);
11695 * intel_wm_need_update - Check whether watermarks need updating
11696 * @plane: drm plane
11697 * @state: new plane state
11699 * Check current plane state versus the new one to determine whether
11700 * watermarks need to be recalculated.
11702 * Returns true or false.
11704 static bool intel_wm_need_update(struct drm_plane *plane,
11705 struct drm_plane_state *state)
11707 struct intel_plane_state *new = to_intel_plane_state(state);
11708 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11710 /* Update watermarks on tiling or size changes. */
11711 if (new->visible != cur->visible)
11714 if (!cur->base.fb || !new->base.fb)
11717 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11718 cur->base.rotation != new->base.rotation ||
11719 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11720 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11721 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11722 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11728 static bool needs_scaling(struct intel_plane_state *state)
11730 int src_w = drm_rect_width(&state->src) >> 16;
11731 int src_h = drm_rect_height(&state->src) >> 16;
11732 int dst_w = drm_rect_width(&state->dst);
11733 int dst_h = drm_rect_height(&state->dst);
11735 return (src_w != dst_w || src_h != dst_h);
11738 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11739 struct drm_plane_state *plane_state)
11741 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11742 struct drm_crtc *crtc = crtc_state->crtc;
11743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11744 struct drm_plane *plane = plane_state->plane;
11745 struct drm_device *dev = crtc->dev;
11746 struct drm_i915_private *dev_priv = to_i915(dev);
11747 struct intel_plane_state *old_plane_state =
11748 to_intel_plane_state(plane->state);
11749 int idx = intel_crtc->base.base.id, ret;
11750 bool mode_changed = needs_modeset(crtc_state);
11751 bool was_crtc_enabled = crtc->state->active;
11752 bool is_crtc_enabled = crtc_state->active;
11753 bool turn_off, turn_on, visible, was_visible;
11754 struct drm_framebuffer *fb = plane_state->fb;
11756 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11757 plane->type != DRM_PLANE_TYPE_CURSOR) {
11758 ret = skl_update_scaler_plane(
11759 to_intel_crtc_state(crtc_state),
11760 to_intel_plane_state(plane_state));
11765 was_visible = old_plane_state->visible;
11766 visible = to_intel_plane_state(plane_state)->visible;
11768 if (!was_crtc_enabled && WARN_ON(was_visible))
11769 was_visible = false;
11772 * Visibility is calculated as if the crtc was on, but
11773 * after scaler setup everything depends on it being off
11774 * when the crtc isn't active.
11776 if (!is_crtc_enabled)
11777 to_intel_plane_state(plane_state)->visible = visible = false;
11779 if (!was_visible && !visible)
11782 if (fb != old_plane_state->base.fb)
11783 pipe_config->fb_changed = true;
11785 turn_off = was_visible && (!visible || mode_changed);
11786 turn_on = visible && (!was_visible || mode_changed);
11788 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11789 plane->base.id, fb ? fb->base.id : -1);
11791 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11792 plane->base.id, was_visible, visible,
11793 turn_off, turn_on, mode_changed);
11796 pipe_config->update_wm_pre = true;
11798 /* must disable cxsr around plane enable/disable */
11799 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11800 pipe_config->disable_cxsr = true;
11801 } else if (turn_off) {
11802 pipe_config->update_wm_post = true;
11804 /* must disable cxsr around plane enable/disable */
11805 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11806 pipe_config->disable_cxsr = true;
11807 } else if (intel_wm_need_update(plane, plane_state)) {
11808 /* FIXME bollocks */
11809 pipe_config->update_wm_pre = true;
11810 pipe_config->update_wm_post = true;
11813 /* Pre-gen9 platforms need two-step watermark updates */
11814 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11815 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11816 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11818 if (visible || was_visible)
11819 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11822 * WaCxSRDisabledForSpriteScaling:ivb
11824 * cstate->update_wm was already set above, so this flag will
11825 * take effect when we commit and program watermarks.
11827 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11828 needs_scaling(to_intel_plane_state(plane_state)) &&
11829 !needs_scaling(old_plane_state))
11830 pipe_config->disable_lp_wm = true;
11835 static bool encoders_cloneable(const struct intel_encoder *a,
11836 const struct intel_encoder *b)
11838 /* masks could be asymmetric, so check both ways */
11839 return a == b || (a->cloneable & (1 << b->type) &&
11840 b->cloneable & (1 << a->type));
11843 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11844 struct intel_crtc *crtc,
11845 struct intel_encoder *encoder)
11847 struct intel_encoder *source_encoder;
11848 struct drm_connector *connector;
11849 struct drm_connector_state *connector_state;
11852 for_each_connector_in_state(state, connector, connector_state, i) {
11853 if (connector_state->crtc != &crtc->base)
11857 to_intel_encoder(connector_state->best_encoder);
11858 if (!encoders_cloneable(encoder, source_encoder))
11865 static bool check_encoder_cloning(struct drm_atomic_state *state,
11866 struct intel_crtc *crtc)
11868 struct intel_encoder *encoder;
11869 struct drm_connector *connector;
11870 struct drm_connector_state *connector_state;
11873 for_each_connector_in_state(state, connector, connector_state, i) {
11874 if (connector_state->crtc != &crtc->base)
11877 encoder = to_intel_encoder(connector_state->best_encoder);
11878 if (!check_single_encoder_cloning(state, crtc, encoder))
11885 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11886 struct drm_crtc_state *crtc_state)
11888 struct drm_device *dev = crtc->dev;
11889 struct drm_i915_private *dev_priv = dev->dev_private;
11890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11891 struct intel_crtc_state *pipe_config =
11892 to_intel_crtc_state(crtc_state);
11893 struct drm_atomic_state *state = crtc_state->state;
11895 bool mode_changed = needs_modeset(crtc_state);
11897 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11898 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11902 if (mode_changed && !crtc_state->active)
11903 pipe_config->update_wm_post = true;
11905 if (mode_changed && crtc_state->enable &&
11906 dev_priv->display.crtc_compute_clock &&
11907 !WARN_ON(pipe_config->shared_dpll)) {
11908 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11915 if (dev_priv->display.compute_pipe_wm) {
11916 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11918 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11923 if (dev_priv->display.compute_intermediate_wm &&
11924 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11925 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11929 * Calculate 'intermediate' watermarks that satisfy both the
11930 * old state and the new state. We can program these
11933 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11937 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11942 if (INTEL_INFO(dev)->gen >= 9) {
11944 ret = skl_update_scaler_crtc(pipe_config);
11947 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11954 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11955 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11956 .load_lut = intel_color_load_luts,
11957 .atomic_begin = intel_begin_crtc_commit,
11958 .atomic_flush = intel_finish_crtc_commit,
11959 .atomic_check = intel_crtc_atomic_check,
11962 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11964 struct intel_connector *connector;
11966 for_each_intel_connector(dev, connector) {
11967 if (connector->base.encoder) {
11968 connector->base.state->best_encoder =
11969 connector->base.encoder;
11970 connector->base.state->crtc =
11971 connector->base.encoder->crtc;
11973 connector->base.state->best_encoder = NULL;
11974 connector->base.state->crtc = NULL;
11980 connected_sink_compute_bpp(struct intel_connector *connector,
11981 struct intel_crtc_state *pipe_config)
11983 int bpp = pipe_config->pipe_bpp;
11985 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11986 connector->base.base.id,
11987 connector->base.name);
11989 /* Don't use an invalid EDID bpc value */
11990 if (connector->base.display_info.bpc &&
11991 connector->base.display_info.bpc * 3 < bpp) {
11992 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11993 bpp, connector->base.display_info.bpc*3);
11994 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11997 /* Clamp bpp to default limit on screens without EDID 1.4 */
11998 if (connector->base.display_info.bpc == 0) {
11999 int type = connector->base.connector_type;
12000 int clamp_bpp = 24;
12002 /* Fall back to 18 bpp when DP sink capability is unknown. */
12003 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12004 type == DRM_MODE_CONNECTOR_eDP)
12007 if (bpp > clamp_bpp) {
12008 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12010 pipe_config->pipe_bpp = clamp_bpp;
12016 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12017 struct intel_crtc_state *pipe_config)
12019 struct drm_device *dev = crtc->base.dev;
12020 struct drm_atomic_state *state;
12021 struct drm_connector *connector;
12022 struct drm_connector_state *connector_state;
12025 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12027 else if (INTEL_INFO(dev)->gen >= 5)
12033 pipe_config->pipe_bpp = bpp;
12035 state = pipe_config->base.state;
12037 /* Clamp display bpp to EDID value */
12038 for_each_connector_in_state(state, connector, connector_state, i) {
12039 if (connector_state->crtc != &crtc->base)
12042 connected_sink_compute_bpp(to_intel_connector(connector),
12049 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12051 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12052 "type: 0x%x flags: 0x%x\n",
12054 mode->crtc_hdisplay, mode->crtc_hsync_start,
12055 mode->crtc_hsync_end, mode->crtc_htotal,
12056 mode->crtc_vdisplay, mode->crtc_vsync_start,
12057 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12060 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12061 struct intel_crtc_state *pipe_config,
12062 const char *context)
12064 struct drm_device *dev = crtc->base.dev;
12065 struct drm_plane *plane;
12066 struct intel_plane *intel_plane;
12067 struct intel_plane_state *state;
12068 struct drm_framebuffer *fb;
12070 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12071 context, pipe_config, pipe_name(crtc->pipe));
12073 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12074 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12075 pipe_config->pipe_bpp, pipe_config->dither);
12076 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12077 pipe_config->has_pch_encoder,
12078 pipe_config->fdi_lanes,
12079 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12080 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12081 pipe_config->fdi_m_n.tu);
12082 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12083 pipe_config->has_dp_encoder,
12084 pipe_config->lane_count,
12085 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12086 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12087 pipe_config->dp_m_n.tu);
12089 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12090 pipe_config->has_dp_encoder,
12091 pipe_config->lane_count,
12092 pipe_config->dp_m2_n2.gmch_m,
12093 pipe_config->dp_m2_n2.gmch_n,
12094 pipe_config->dp_m2_n2.link_m,
12095 pipe_config->dp_m2_n2.link_n,
12096 pipe_config->dp_m2_n2.tu);
12098 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12099 pipe_config->has_audio,
12100 pipe_config->has_infoframe);
12102 DRM_DEBUG_KMS("requested mode:\n");
12103 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12104 DRM_DEBUG_KMS("adjusted mode:\n");
12105 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12106 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12107 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12108 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12109 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12110 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12112 pipe_config->scaler_state.scaler_users,
12113 pipe_config->scaler_state.scaler_id);
12114 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12115 pipe_config->gmch_pfit.control,
12116 pipe_config->gmch_pfit.pgm_ratios,
12117 pipe_config->gmch_pfit.lvds_border_bits);
12118 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12119 pipe_config->pch_pfit.pos,
12120 pipe_config->pch_pfit.size,
12121 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12122 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12123 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12125 if (IS_BROXTON(dev)) {
12126 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12127 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12128 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12129 pipe_config->ddi_pll_sel,
12130 pipe_config->dpll_hw_state.ebb0,
12131 pipe_config->dpll_hw_state.ebb4,
12132 pipe_config->dpll_hw_state.pll0,
12133 pipe_config->dpll_hw_state.pll1,
12134 pipe_config->dpll_hw_state.pll2,
12135 pipe_config->dpll_hw_state.pll3,
12136 pipe_config->dpll_hw_state.pll6,
12137 pipe_config->dpll_hw_state.pll8,
12138 pipe_config->dpll_hw_state.pll9,
12139 pipe_config->dpll_hw_state.pll10,
12140 pipe_config->dpll_hw_state.pcsdw12);
12141 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12142 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12143 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12144 pipe_config->ddi_pll_sel,
12145 pipe_config->dpll_hw_state.ctrl1,
12146 pipe_config->dpll_hw_state.cfgcr1,
12147 pipe_config->dpll_hw_state.cfgcr2);
12148 } else if (HAS_DDI(dev)) {
12149 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12150 pipe_config->ddi_pll_sel,
12151 pipe_config->dpll_hw_state.wrpll,
12152 pipe_config->dpll_hw_state.spll);
12154 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12155 "fp0: 0x%x, fp1: 0x%x\n",
12156 pipe_config->dpll_hw_state.dpll,
12157 pipe_config->dpll_hw_state.dpll_md,
12158 pipe_config->dpll_hw_state.fp0,
12159 pipe_config->dpll_hw_state.fp1);
12162 DRM_DEBUG_KMS("planes on this crtc\n");
12163 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12164 intel_plane = to_intel_plane(plane);
12165 if (intel_plane->pipe != crtc->pipe)
12168 state = to_intel_plane_state(plane->state);
12169 fb = state->base.fb;
12171 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12172 "disabled, scaler_id = %d\n",
12173 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12174 plane->base.id, intel_plane->pipe,
12175 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12176 drm_plane_index(plane), state->scaler_id);
12180 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12181 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12182 plane->base.id, intel_plane->pipe,
12183 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12184 drm_plane_index(plane));
12185 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12186 fb->base.id, fb->width, fb->height, fb->pixel_format);
12187 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12189 state->src.x1 >> 16, state->src.y1 >> 16,
12190 drm_rect_width(&state->src) >> 16,
12191 drm_rect_height(&state->src) >> 16,
12192 state->dst.x1, state->dst.y1,
12193 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12197 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12199 struct drm_device *dev = state->dev;
12200 struct drm_connector *connector;
12201 unsigned int used_ports = 0;
12204 * Walk the connector list instead of the encoder
12205 * list to detect the problem on ddi platforms
12206 * where there's just one encoder per digital port.
12208 drm_for_each_connector(connector, dev) {
12209 struct drm_connector_state *connector_state;
12210 struct intel_encoder *encoder;
12212 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12213 if (!connector_state)
12214 connector_state = connector->state;
12216 if (!connector_state->best_encoder)
12219 encoder = to_intel_encoder(connector_state->best_encoder);
12221 WARN_ON(!connector_state->crtc);
12223 switch (encoder->type) {
12224 unsigned int port_mask;
12225 case INTEL_OUTPUT_UNKNOWN:
12226 if (WARN_ON(!HAS_DDI(dev)))
12228 case INTEL_OUTPUT_DISPLAYPORT:
12229 case INTEL_OUTPUT_HDMI:
12230 case INTEL_OUTPUT_EDP:
12231 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12233 /* the same port mustn't appear more than once */
12234 if (used_ports & port_mask)
12237 used_ports |= port_mask;
12247 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12249 struct drm_crtc_state tmp_state;
12250 struct intel_crtc_scaler_state scaler_state;
12251 struct intel_dpll_hw_state dpll_hw_state;
12252 struct intel_shared_dpll *shared_dpll;
12253 uint32_t ddi_pll_sel;
12256 /* FIXME: before the switch to atomic started, a new pipe_config was
12257 * kzalloc'd. Code that depends on any field being zero should be
12258 * fixed, so that the crtc_state can be safely duplicated. For now,
12259 * only fields that are know to not cause problems are preserved. */
12261 tmp_state = crtc_state->base;
12262 scaler_state = crtc_state->scaler_state;
12263 shared_dpll = crtc_state->shared_dpll;
12264 dpll_hw_state = crtc_state->dpll_hw_state;
12265 ddi_pll_sel = crtc_state->ddi_pll_sel;
12266 force_thru = crtc_state->pch_pfit.force_thru;
12268 memset(crtc_state, 0, sizeof *crtc_state);
12270 crtc_state->base = tmp_state;
12271 crtc_state->scaler_state = scaler_state;
12272 crtc_state->shared_dpll = shared_dpll;
12273 crtc_state->dpll_hw_state = dpll_hw_state;
12274 crtc_state->ddi_pll_sel = ddi_pll_sel;
12275 crtc_state->pch_pfit.force_thru = force_thru;
12279 intel_modeset_pipe_config(struct drm_crtc *crtc,
12280 struct intel_crtc_state *pipe_config)
12282 struct drm_atomic_state *state = pipe_config->base.state;
12283 struct intel_encoder *encoder;
12284 struct drm_connector *connector;
12285 struct drm_connector_state *connector_state;
12286 int base_bpp, ret = -EINVAL;
12290 clear_intel_crtc_state(pipe_config);
12292 pipe_config->cpu_transcoder =
12293 (enum transcoder) to_intel_crtc(crtc)->pipe;
12296 * Sanitize sync polarity flags based on requested ones. If neither
12297 * positive or negative polarity is requested, treat this as meaning
12298 * negative polarity.
12300 if (!(pipe_config->base.adjusted_mode.flags &
12301 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12302 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12304 if (!(pipe_config->base.adjusted_mode.flags &
12305 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12306 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12308 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12314 * Determine the real pipe dimensions. Note that stereo modes can
12315 * increase the actual pipe size due to the frame doubling and
12316 * insertion of additional space for blanks between the frame. This
12317 * is stored in the crtc timings. We use the requested mode to do this
12318 * computation to clearly distinguish it from the adjusted mode, which
12319 * can be changed by the connectors in the below retry loop.
12321 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12322 &pipe_config->pipe_src_w,
12323 &pipe_config->pipe_src_h);
12326 /* Ensure the port clock defaults are reset when retrying. */
12327 pipe_config->port_clock = 0;
12328 pipe_config->pixel_multiplier = 1;
12330 /* Fill in default crtc timings, allow encoders to overwrite them. */
12331 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12332 CRTC_STEREO_DOUBLE);
12334 /* Pass our mode to the connectors and the CRTC to give them a chance to
12335 * adjust it according to limitations or connector properties, and also
12336 * a chance to reject the mode entirely.
12338 for_each_connector_in_state(state, connector, connector_state, i) {
12339 if (connector_state->crtc != crtc)
12342 encoder = to_intel_encoder(connector_state->best_encoder);
12344 if (!(encoder->compute_config(encoder, pipe_config))) {
12345 DRM_DEBUG_KMS("Encoder config failure\n");
12350 /* Set default port clock if not overwritten by the encoder. Needs to be
12351 * done afterwards in case the encoder adjusts the mode. */
12352 if (!pipe_config->port_clock)
12353 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12354 * pipe_config->pixel_multiplier;
12356 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12358 DRM_DEBUG_KMS("CRTC fixup failed\n");
12362 if (ret == RETRY) {
12363 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12368 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12370 goto encoder_retry;
12373 /* Dithering seems to not pass-through bits correctly when it should, so
12374 * only enable it on 6bpc panels. */
12375 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12376 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12377 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12384 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12386 struct drm_crtc *crtc;
12387 struct drm_crtc_state *crtc_state;
12390 /* Double check state. */
12391 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12392 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12394 /* Update hwmode for vblank functions */
12395 if (crtc->state->active)
12396 crtc->hwmode = crtc->state->adjusted_mode;
12398 crtc->hwmode.crtc_clock = 0;
12401 * Update legacy state to satisfy fbc code. This can
12402 * be removed when fbc uses the atomic state.
12404 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12405 struct drm_plane_state *plane_state = crtc->primary->state;
12407 crtc->primary->fb = plane_state->fb;
12408 crtc->x = plane_state->src_x >> 16;
12409 crtc->y = plane_state->src_y >> 16;
12414 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12418 if (clock1 == clock2)
12421 if (!clock1 || !clock2)
12424 diff = abs(clock1 - clock2);
12426 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12432 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12433 list_for_each_entry((intel_crtc), \
12434 &(dev)->mode_config.crtc_list, \
12436 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12439 intel_compare_m_n(unsigned int m, unsigned int n,
12440 unsigned int m2, unsigned int n2,
12443 if (m == m2 && n == n2)
12446 if (exact || !m || !n || !m2 || !n2)
12449 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12456 } else if (n < n2) {
12466 return intel_fuzzy_clock_check(m, m2);
12470 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12471 struct intel_link_m_n *m2_n2,
12474 if (m_n->tu == m2_n2->tu &&
12475 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12476 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12477 intel_compare_m_n(m_n->link_m, m_n->link_n,
12478 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12489 intel_pipe_config_compare(struct drm_device *dev,
12490 struct intel_crtc_state *current_config,
12491 struct intel_crtc_state *pipe_config,
12496 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12499 DRM_ERROR(fmt, ##__VA_ARGS__); \
12501 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12504 #define PIPE_CONF_CHECK_X(name) \
12505 if (current_config->name != pipe_config->name) { \
12506 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12507 "(expected 0x%08x, found 0x%08x)\n", \
12508 current_config->name, \
12509 pipe_config->name); \
12513 #define PIPE_CONF_CHECK_I(name) \
12514 if (current_config->name != pipe_config->name) { \
12515 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12516 "(expected %i, found %i)\n", \
12517 current_config->name, \
12518 pipe_config->name); \
12522 #define PIPE_CONF_CHECK_P(name) \
12523 if (current_config->name != pipe_config->name) { \
12524 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12525 "(expected %p, found %p)\n", \
12526 current_config->name, \
12527 pipe_config->name); \
12531 #define PIPE_CONF_CHECK_M_N(name) \
12532 if (!intel_compare_link_m_n(¤t_config->name, \
12533 &pipe_config->name,\
12535 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12536 "(expected tu %i gmch %i/%i link %i/%i, " \
12537 "found tu %i, gmch %i/%i link %i/%i)\n", \
12538 current_config->name.tu, \
12539 current_config->name.gmch_m, \
12540 current_config->name.gmch_n, \
12541 current_config->name.link_m, \
12542 current_config->name.link_n, \
12543 pipe_config->name.tu, \
12544 pipe_config->name.gmch_m, \
12545 pipe_config->name.gmch_n, \
12546 pipe_config->name.link_m, \
12547 pipe_config->name.link_n); \
12551 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12552 if (!intel_compare_link_m_n(¤t_config->name, \
12553 &pipe_config->name, adjust) && \
12554 !intel_compare_link_m_n(¤t_config->alt_name, \
12555 &pipe_config->name, adjust)) { \
12556 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12557 "(expected tu %i gmch %i/%i link %i/%i, " \
12558 "or tu %i gmch %i/%i link %i/%i, " \
12559 "found tu %i, gmch %i/%i link %i/%i)\n", \
12560 current_config->name.tu, \
12561 current_config->name.gmch_m, \
12562 current_config->name.gmch_n, \
12563 current_config->name.link_m, \
12564 current_config->name.link_n, \
12565 current_config->alt_name.tu, \
12566 current_config->alt_name.gmch_m, \
12567 current_config->alt_name.gmch_n, \
12568 current_config->alt_name.link_m, \
12569 current_config->alt_name.link_n, \
12570 pipe_config->name.tu, \
12571 pipe_config->name.gmch_m, \
12572 pipe_config->name.gmch_n, \
12573 pipe_config->name.link_m, \
12574 pipe_config->name.link_n); \
12578 /* This is required for BDW+ where there is only one set of registers for
12579 * switching between high and low RR.
12580 * This macro can be used whenever a comparison has to be made between one
12581 * hw state and multiple sw state variables.
12583 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12584 if ((current_config->name != pipe_config->name) && \
12585 (current_config->alt_name != pipe_config->name)) { \
12586 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12587 "(expected %i or %i, found %i)\n", \
12588 current_config->name, \
12589 current_config->alt_name, \
12590 pipe_config->name); \
12594 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12595 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12596 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12597 "(expected %i, found %i)\n", \
12598 current_config->name & (mask), \
12599 pipe_config->name & (mask)); \
12603 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12604 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12605 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12606 "(expected %i, found %i)\n", \
12607 current_config->name, \
12608 pipe_config->name); \
12612 #define PIPE_CONF_QUIRK(quirk) \
12613 ((current_config->quirks | pipe_config->quirks) & (quirk))
12615 PIPE_CONF_CHECK_I(cpu_transcoder);
12617 PIPE_CONF_CHECK_I(has_pch_encoder);
12618 PIPE_CONF_CHECK_I(fdi_lanes);
12619 PIPE_CONF_CHECK_M_N(fdi_m_n);
12621 PIPE_CONF_CHECK_I(has_dp_encoder);
12622 PIPE_CONF_CHECK_I(lane_count);
12624 if (INTEL_INFO(dev)->gen < 8) {
12625 PIPE_CONF_CHECK_M_N(dp_m_n);
12627 if (current_config->has_drrs)
12628 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12630 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12632 PIPE_CONF_CHECK_I(has_dsi_encoder);
12634 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12635 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12636 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12637 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12638 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12639 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12641 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12642 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12643 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12644 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12645 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12646 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12648 PIPE_CONF_CHECK_I(pixel_multiplier);
12649 PIPE_CONF_CHECK_I(has_hdmi_sink);
12650 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12651 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12652 PIPE_CONF_CHECK_I(limited_color_range);
12653 PIPE_CONF_CHECK_I(has_infoframe);
12655 PIPE_CONF_CHECK_I(has_audio);
12657 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12658 DRM_MODE_FLAG_INTERLACE);
12660 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12661 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12662 DRM_MODE_FLAG_PHSYNC);
12663 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12664 DRM_MODE_FLAG_NHSYNC);
12665 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12666 DRM_MODE_FLAG_PVSYNC);
12667 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12668 DRM_MODE_FLAG_NVSYNC);
12671 PIPE_CONF_CHECK_X(gmch_pfit.control);
12672 /* pfit ratios are autocomputed by the hw on gen4+ */
12673 if (INTEL_INFO(dev)->gen < 4)
12674 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12675 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12678 PIPE_CONF_CHECK_I(pipe_src_w);
12679 PIPE_CONF_CHECK_I(pipe_src_h);
12681 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12682 if (current_config->pch_pfit.enabled) {
12683 PIPE_CONF_CHECK_X(pch_pfit.pos);
12684 PIPE_CONF_CHECK_X(pch_pfit.size);
12687 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12690 /* BDW+ don't expose a synchronous way to read the state */
12691 if (IS_HASWELL(dev))
12692 PIPE_CONF_CHECK_I(ips_enabled);
12694 PIPE_CONF_CHECK_I(double_wide);
12696 PIPE_CONF_CHECK_X(ddi_pll_sel);
12698 PIPE_CONF_CHECK_P(shared_dpll);
12699 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12700 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12701 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12702 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12703 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12704 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12705 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12706 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12707 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12709 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12710 PIPE_CONF_CHECK_I(pipe_bpp);
12712 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12713 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12715 #undef PIPE_CONF_CHECK_X
12716 #undef PIPE_CONF_CHECK_I
12717 #undef PIPE_CONF_CHECK_P
12718 #undef PIPE_CONF_CHECK_I_ALT
12719 #undef PIPE_CONF_CHECK_FLAGS
12720 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12721 #undef PIPE_CONF_QUIRK
12722 #undef INTEL_ERR_OR_DBG_KMS
12727 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12728 const struct intel_crtc_state *pipe_config)
12730 if (pipe_config->has_pch_encoder) {
12731 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12732 &pipe_config->fdi_m_n);
12733 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12736 * FDI already provided one idea for the dotclock.
12737 * Yell if the encoder disagrees.
12739 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12740 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12741 fdi_dotclock, dotclock);
12745 static void check_wm_state(struct drm_device *dev)
12747 struct drm_i915_private *dev_priv = dev->dev_private;
12748 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12749 struct intel_crtc *intel_crtc;
12752 if (INTEL_INFO(dev)->gen < 9)
12755 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12756 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12758 for_each_intel_crtc(dev, intel_crtc) {
12759 struct skl_ddb_entry *hw_entry, *sw_entry;
12760 const enum pipe pipe = intel_crtc->pipe;
12762 if (!intel_crtc->active)
12766 for_each_plane(dev_priv, pipe, plane) {
12767 hw_entry = &hw_ddb.plane[pipe][plane];
12768 sw_entry = &sw_ddb->plane[pipe][plane];
12770 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12773 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12774 "(expected (%u,%u), found (%u,%u))\n",
12775 pipe_name(pipe), plane + 1,
12776 sw_entry->start, sw_entry->end,
12777 hw_entry->start, hw_entry->end);
12781 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12782 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12784 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12787 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12788 "(expected (%u,%u), found (%u,%u))\n",
12790 sw_entry->start, sw_entry->end,
12791 hw_entry->start, hw_entry->end);
12796 check_connector_state(struct drm_device *dev,
12797 struct drm_atomic_state *old_state)
12799 struct drm_connector_state *old_conn_state;
12800 struct drm_connector *connector;
12803 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12804 struct drm_encoder *encoder = connector->encoder;
12805 struct drm_connector_state *state = connector->state;
12807 /* This also checks the encoder/connector hw state with the
12808 * ->get_hw_state callbacks. */
12809 intel_connector_check_state(to_intel_connector(connector));
12811 I915_STATE_WARN(state->best_encoder != encoder,
12812 "connector's atomic encoder doesn't match legacy encoder\n");
12817 check_encoder_state(struct drm_device *dev)
12819 struct intel_encoder *encoder;
12820 struct intel_connector *connector;
12822 for_each_intel_encoder(dev, encoder) {
12823 bool enabled = false;
12826 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12827 encoder->base.base.id,
12828 encoder->base.name);
12830 for_each_intel_connector(dev, connector) {
12831 if (connector->base.state->best_encoder != &encoder->base)
12835 I915_STATE_WARN(connector->base.state->crtc !=
12836 encoder->base.crtc,
12837 "connector's crtc doesn't match encoder crtc\n");
12840 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12841 "encoder's enabled state mismatch "
12842 "(expected %i, found %i)\n",
12843 !!encoder->base.crtc, enabled);
12845 if (!encoder->base.crtc) {
12848 active = encoder->get_hw_state(encoder, &pipe);
12849 I915_STATE_WARN(active,
12850 "encoder detached but still enabled on pipe %c.\n",
12857 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12859 struct drm_i915_private *dev_priv = dev->dev_private;
12860 struct intel_encoder *encoder;
12861 struct drm_crtc_state *old_crtc_state;
12862 struct drm_crtc *crtc;
12865 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12867 struct intel_crtc_state *pipe_config, *sw_config;
12870 if (!needs_modeset(crtc->state) &&
12871 !to_intel_crtc_state(crtc->state)->update_pipe)
12874 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12875 pipe_config = to_intel_crtc_state(old_crtc_state);
12876 memset(pipe_config, 0, sizeof(*pipe_config));
12877 pipe_config->base.crtc = crtc;
12878 pipe_config->base.state = old_state;
12880 DRM_DEBUG_KMS("[CRTC:%d]\n",
12883 active = dev_priv->display.get_pipe_config(intel_crtc,
12886 /* hw state is inconsistent with the pipe quirk */
12887 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12888 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12889 active = crtc->state->active;
12891 I915_STATE_WARN(crtc->state->active != active,
12892 "crtc active state doesn't match with hw state "
12893 "(expected %i, found %i)\n", crtc->state->active, active);
12895 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12896 "transitional active state does not match atomic hw state "
12897 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12899 for_each_encoder_on_crtc(dev, crtc, encoder) {
12902 active = encoder->get_hw_state(encoder, &pipe);
12903 I915_STATE_WARN(active != crtc->state->active,
12904 "[ENCODER:%i] active %i with crtc active %i\n",
12905 encoder->base.base.id, active, crtc->state->active);
12907 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12908 "Encoder connected to wrong pipe %c\n",
12912 encoder->get_config(encoder, pipe_config);
12915 if (!crtc->state->active)
12918 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12920 sw_config = to_intel_crtc_state(crtc->state);
12921 if (!intel_pipe_config_compare(dev, sw_config,
12922 pipe_config, false)) {
12923 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12924 intel_dump_pipe_config(intel_crtc, pipe_config,
12926 intel_dump_pipe_config(intel_crtc, sw_config,
12933 check_shared_dpll_state(struct drm_device *dev)
12935 struct drm_i915_private *dev_priv = dev->dev_private;
12936 struct intel_crtc *crtc;
12937 struct intel_dpll_hw_state dpll_hw_state;
12940 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12941 struct intel_shared_dpll *pll =
12942 intel_get_shared_dpll_by_id(dev_priv, i);
12943 unsigned enabled_crtcs = 0, active_crtcs = 0;
12946 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12948 DRM_DEBUG_KMS("%s\n", pll->name);
12950 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12952 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12953 "more active pll users than references: %x vs %x\n",
12954 pll->active_mask, pll->config.crtc_mask);
12956 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12957 I915_STATE_WARN(!pll->on && pll->active_mask,
12958 "pll in active use but not on in sw tracking\n");
12959 I915_STATE_WARN(pll->on && !pll->active_mask,
12960 "pll is on but not used by any active crtc\n");
12961 I915_STATE_WARN(pll->on != active,
12962 "pll on state mismatch (expected %i, found %i)\n",
12966 for_each_intel_crtc(dev, crtc) {
12967 if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12968 enabled_crtcs |= 1 << drm_crtc_index(&crtc->base);
12969 if (crtc->base.state->active && crtc->config->shared_dpll == pll)
12970 active_crtcs |= 1 << drm_crtc_index(&crtc->base);
12973 I915_STATE_WARN(pll->active_mask != active_crtcs,
12974 "pll active crtcs mismatch (expected %x, found %x)\n",
12975 pll->active_mask, active_crtcs);
12976 I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs,
12977 "pll enabled crtcs mismatch (expected %x, found %x)\n",
12978 pll->config.crtc_mask, enabled_crtcs);
12980 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12981 sizeof(dpll_hw_state)),
12982 "pll hw state mismatch\n");
12987 intel_modeset_check_state(struct drm_device *dev,
12988 struct drm_atomic_state *old_state)
12990 check_wm_state(dev);
12991 check_connector_state(dev, old_state);
12992 check_encoder_state(dev);
12993 check_crtc_state(dev, old_state);
12994 check_shared_dpll_state(dev);
12997 static void update_scanline_offset(struct intel_crtc *crtc)
12999 struct drm_device *dev = crtc->base.dev;
13002 * The scanline counter increments at the leading edge of hsync.
13004 * On most platforms it starts counting from vtotal-1 on the
13005 * first active line. That means the scanline counter value is
13006 * always one less than what we would expect. Ie. just after
13007 * start of vblank, which also occurs at start of hsync (on the
13008 * last active line), the scanline counter will read vblank_start-1.
13010 * On gen2 the scanline counter starts counting from 1 instead
13011 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13012 * to keep the value positive), instead of adding one.
13014 * On HSW+ the behaviour of the scanline counter depends on the output
13015 * type. For DP ports it behaves like most other platforms, but on HDMI
13016 * there's an extra 1 line difference. So we need to add two instead of
13017 * one to the value.
13019 if (IS_GEN2(dev)) {
13020 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13023 vtotal = adjusted_mode->crtc_vtotal;
13024 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13027 crtc->scanline_offset = vtotal - 1;
13028 } else if (HAS_DDI(dev) &&
13029 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13030 crtc->scanline_offset = 2;
13032 crtc->scanline_offset = 1;
13035 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13037 struct drm_device *dev = state->dev;
13038 struct drm_i915_private *dev_priv = to_i915(dev);
13039 struct intel_shared_dpll_config *shared_dpll = NULL;
13040 struct drm_crtc *crtc;
13041 struct drm_crtc_state *crtc_state;
13044 if (!dev_priv->display.crtc_compute_clock)
13047 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13049 struct intel_shared_dpll *old_dpll =
13050 to_intel_crtc_state(crtc->state)->shared_dpll;
13052 if (!needs_modeset(crtc_state))
13055 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13061 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13063 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13068 * This implements the workaround described in the "notes" section of the mode
13069 * set sequence documentation. When going from no pipes or single pipe to
13070 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13071 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13073 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13075 struct drm_crtc_state *crtc_state;
13076 struct intel_crtc *intel_crtc;
13077 struct drm_crtc *crtc;
13078 struct intel_crtc_state *first_crtc_state = NULL;
13079 struct intel_crtc_state *other_crtc_state = NULL;
13080 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13083 /* look at all crtc's that are going to be enabled in during modeset */
13084 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13085 intel_crtc = to_intel_crtc(crtc);
13087 if (!crtc_state->active || !needs_modeset(crtc_state))
13090 if (first_crtc_state) {
13091 other_crtc_state = to_intel_crtc_state(crtc_state);
13094 first_crtc_state = to_intel_crtc_state(crtc_state);
13095 first_pipe = intel_crtc->pipe;
13099 /* No workaround needed? */
13100 if (!first_crtc_state)
13103 /* w/a possibly needed, check how many crtc's are already enabled. */
13104 for_each_intel_crtc(state->dev, intel_crtc) {
13105 struct intel_crtc_state *pipe_config;
13107 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13108 if (IS_ERR(pipe_config))
13109 return PTR_ERR(pipe_config);
13111 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13113 if (!pipe_config->base.active ||
13114 needs_modeset(&pipe_config->base))
13117 /* 2 or more enabled crtcs means no need for w/a */
13118 if (enabled_pipe != INVALID_PIPE)
13121 enabled_pipe = intel_crtc->pipe;
13124 if (enabled_pipe != INVALID_PIPE)
13125 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13126 else if (other_crtc_state)
13127 other_crtc_state->hsw_workaround_pipe = first_pipe;
13132 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13134 struct drm_crtc *crtc;
13135 struct drm_crtc_state *crtc_state;
13138 /* add all active pipes to the state */
13139 for_each_crtc(state->dev, crtc) {
13140 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13141 if (IS_ERR(crtc_state))
13142 return PTR_ERR(crtc_state);
13144 if (!crtc_state->active || needs_modeset(crtc_state))
13147 crtc_state->mode_changed = true;
13149 ret = drm_atomic_add_affected_connectors(state, crtc);
13153 ret = drm_atomic_add_affected_planes(state, crtc);
13161 static int intel_modeset_checks(struct drm_atomic_state *state)
13163 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13164 struct drm_i915_private *dev_priv = state->dev->dev_private;
13165 struct drm_crtc *crtc;
13166 struct drm_crtc_state *crtc_state;
13169 if (!check_digital_port_conflicts(state)) {
13170 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13174 intel_state->modeset = true;
13175 intel_state->active_crtcs = dev_priv->active_crtcs;
13177 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13178 if (crtc_state->active)
13179 intel_state->active_crtcs |= 1 << i;
13181 intel_state->active_crtcs &= ~(1 << i);
13185 * See if the config requires any additional preparation, e.g.
13186 * to adjust global state with pipes off. We need to do this
13187 * here so we can get the modeset_pipe updated config for the new
13188 * mode set on this crtc. For other crtcs we need to use the
13189 * adjusted_mode bits in the crtc directly.
13191 if (dev_priv->display.modeset_calc_cdclk) {
13192 ret = dev_priv->display.modeset_calc_cdclk(state);
13194 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13195 ret = intel_modeset_all_pipes(state);
13200 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13201 intel_state->cdclk, intel_state->dev_cdclk);
13203 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13205 intel_modeset_clear_plls(state);
13207 if (IS_HASWELL(dev_priv))
13208 return haswell_mode_set_planes_workaround(state);
13214 * Handle calculation of various watermark data at the end of the atomic check
13215 * phase. The code here should be run after the per-crtc and per-plane 'check'
13216 * handlers to ensure that all derived state has been updated.
13218 static void calc_watermark_data(struct drm_atomic_state *state)
13220 struct drm_device *dev = state->dev;
13221 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13222 struct drm_crtc *crtc;
13223 struct drm_crtc_state *cstate;
13224 struct drm_plane *plane;
13225 struct drm_plane_state *pstate;
13228 * Calculate watermark configuration details now that derived
13229 * plane/crtc state is all properly updated.
13231 drm_for_each_crtc(crtc, dev) {
13232 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13235 if (cstate->active)
13236 intel_state->wm_config.num_pipes_active++;
13238 drm_for_each_legacy_plane(plane, dev) {
13239 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13242 if (!to_intel_plane_state(pstate)->visible)
13245 intel_state->wm_config.sprites_enabled = true;
13246 if (pstate->crtc_w != pstate->src_w >> 16 ||
13247 pstate->crtc_h != pstate->src_h >> 16)
13248 intel_state->wm_config.sprites_scaled = true;
13253 * intel_atomic_check - validate state object
13255 * @state: state to validate
13257 static int intel_atomic_check(struct drm_device *dev,
13258 struct drm_atomic_state *state)
13260 struct drm_i915_private *dev_priv = to_i915(dev);
13261 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13262 struct drm_crtc *crtc;
13263 struct drm_crtc_state *crtc_state;
13265 bool any_ms = false;
13267 ret = drm_atomic_helper_check_modeset(dev, state);
13271 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13272 struct intel_crtc_state *pipe_config =
13273 to_intel_crtc_state(crtc_state);
13275 /* Catch I915_MODE_FLAG_INHERITED */
13276 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13277 crtc_state->mode_changed = true;
13279 if (!crtc_state->enable) {
13280 if (needs_modeset(crtc_state))
13285 if (!needs_modeset(crtc_state))
13288 /* FIXME: For only active_changed we shouldn't need to do any
13289 * state recomputation at all. */
13291 ret = drm_atomic_add_affected_connectors(state, crtc);
13295 ret = intel_modeset_pipe_config(crtc, pipe_config);
13299 if (i915.fastboot &&
13300 intel_pipe_config_compare(dev,
13301 to_intel_crtc_state(crtc->state),
13302 pipe_config, true)) {
13303 crtc_state->mode_changed = false;
13304 to_intel_crtc_state(crtc_state)->update_pipe = true;
13307 if (needs_modeset(crtc_state)) {
13310 ret = drm_atomic_add_affected_planes(state, crtc);
13315 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13316 needs_modeset(crtc_state) ?
13317 "[modeset]" : "[fastset]");
13321 ret = intel_modeset_checks(state);
13326 intel_state->cdclk = dev_priv->cdclk_freq;
13328 ret = drm_atomic_helper_check_planes(dev, state);
13332 intel_fbc_choose_crtc(dev_priv, state);
13333 calc_watermark_data(state);
13338 static int intel_atomic_prepare_commit(struct drm_device *dev,
13339 struct drm_atomic_state *state,
13342 struct drm_i915_private *dev_priv = dev->dev_private;
13343 struct drm_plane_state *plane_state;
13344 struct drm_crtc_state *crtc_state;
13345 struct drm_plane *plane;
13346 struct drm_crtc *crtc;
13350 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13354 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13355 ret = intel_crtc_wait_for_pending_flips(crtc);
13359 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13360 flush_workqueue(dev_priv->wq);
13363 ret = mutex_lock_interruptible(&dev->struct_mutex);
13367 ret = drm_atomic_helper_prepare_planes(dev, state);
13368 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13371 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13372 mutex_unlock(&dev->struct_mutex);
13374 for_each_plane_in_state(state, plane, plane_state, i) {
13375 struct intel_plane_state *intel_plane_state =
13376 to_intel_plane_state(plane_state);
13378 if (!intel_plane_state->wait_req)
13381 ret = __i915_wait_request(intel_plane_state->wait_req,
13382 reset_counter, true,
13385 /* Swallow -EIO errors to allow updates during hw lockup. */
13396 mutex_lock(&dev->struct_mutex);
13397 drm_atomic_helper_cleanup_planes(dev, state);
13400 mutex_unlock(&dev->struct_mutex);
13404 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13405 struct drm_i915_private *dev_priv,
13406 unsigned crtc_mask)
13408 unsigned last_vblank_count[I915_MAX_PIPES];
13415 for_each_pipe(dev_priv, pipe) {
13416 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13418 if (!((1 << pipe) & crtc_mask))
13421 ret = drm_crtc_vblank_get(crtc);
13422 if (WARN_ON(ret != 0)) {
13423 crtc_mask &= ~(1 << pipe);
13427 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13430 for_each_pipe(dev_priv, pipe) {
13431 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13434 if (!((1 << pipe) & crtc_mask))
13437 lret = wait_event_timeout(dev->vblank[pipe].queue,
13438 last_vblank_count[pipe] !=
13439 drm_crtc_vblank_count(crtc),
13440 msecs_to_jiffies(50));
13444 drm_crtc_vblank_put(crtc);
13448 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13450 /* fb updated, need to unpin old fb */
13451 if (crtc_state->fb_changed)
13454 /* wm changes, need vblank before final wm's */
13455 if (crtc_state->update_wm_post)
13459 * cxsr is re-enabled after vblank.
13460 * This is already handled by crtc_state->update_wm_post,
13461 * but added for clarity.
13463 if (crtc_state->disable_cxsr)
13470 * intel_atomic_commit - commit validated state object
13472 * @state: the top-level driver state object
13473 * @async: asynchronous commit
13475 * This function commits a top-level state object that has been validated
13476 * with drm_atomic_helper_check().
13478 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13479 * we can only handle plane-related operations and do not yet support
13480 * asynchronous commit.
13483 * Zero for success or -errno.
13485 static int intel_atomic_commit(struct drm_device *dev,
13486 struct drm_atomic_state *state,
13489 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13490 struct drm_i915_private *dev_priv = dev->dev_private;
13491 struct drm_crtc_state *old_crtc_state;
13492 struct drm_crtc *crtc;
13493 struct intel_crtc_state *intel_cstate;
13495 bool hw_check = intel_state->modeset;
13496 unsigned long put_domains[I915_MAX_PIPES] = {};
13497 unsigned crtc_vblank_mask = 0;
13499 ret = intel_atomic_prepare_commit(dev, state, async);
13501 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13505 drm_atomic_helper_swap_state(dev, state);
13506 dev_priv->wm.config = intel_state->wm_config;
13507 intel_shared_dpll_commit(state);
13509 if (intel_state->modeset) {
13510 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13511 sizeof(intel_state->min_pixclk));
13512 dev_priv->active_crtcs = intel_state->active_crtcs;
13513 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13515 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13518 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13521 if (needs_modeset(crtc->state) ||
13522 to_intel_crtc_state(crtc->state)->update_pipe) {
13525 put_domains[to_intel_crtc(crtc)->pipe] =
13526 modeset_get_crtc_power_domains(crtc,
13527 to_intel_crtc_state(crtc->state));
13530 if (!needs_modeset(crtc->state))
13533 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13535 if (old_crtc_state->active) {
13536 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13537 dev_priv->display.crtc_disable(crtc);
13538 intel_crtc->active = false;
13539 intel_fbc_disable(intel_crtc);
13540 intel_disable_shared_dpll(intel_crtc);
13543 * Underruns don't always raise
13544 * interrupts, so check manually.
13546 intel_check_cpu_fifo_underruns(dev_priv);
13547 intel_check_pch_fifo_underruns(dev_priv);
13549 if (!crtc->state->active)
13550 intel_update_watermarks(crtc);
13554 /* Only after disabling all output pipelines that will be changed can we
13555 * update the the output configuration. */
13556 intel_modeset_update_crtc_state(state);
13558 if (intel_state->modeset) {
13559 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13561 if (dev_priv->display.modeset_commit_cdclk &&
13562 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13563 dev_priv->display.modeset_commit_cdclk(state);
13566 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13567 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13569 bool modeset = needs_modeset(crtc->state);
13570 struct intel_crtc_state *pipe_config =
13571 to_intel_crtc_state(crtc->state);
13572 bool update_pipe = !modeset && pipe_config->update_pipe;
13574 if (modeset && crtc->state->active) {
13575 update_scanline_offset(to_intel_crtc(crtc));
13576 dev_priv->display.crtc_enable(crtc);
13580 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13582 if (crtc->state->active &&
13583 drm_atomic_get_existing_plane_state(state, crtc->primary))
13584 intel_fbc_enable(intel_crtc);
13586 if (crtc->state->active &&
13587 (crtc->state->planes_changed || update_pipe))
13588 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13590 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13591 crtc_vblank_mask |= 1 << i;
13594 /* FIXME: add subpixel order */
13596 if (!state->legacy_cursor_update)
13597 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13599 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13600 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13602 if (put_domains[i])
13603 modeset_put_power_domains(dev_priv, put_domains[i]);
13606 if (intel_state->modeset)
13607 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13610 * Now that the vblank has passed, we can go ahead and program the
13611 * optimal watermarks on platforms that need two-step watermark
13614 * TODO: Move this (and other cleanup) to an async worker eventually.
13616 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13617 intel_cstate = to_intel_crtc_state(crtc->state);
13619 if (dev_priv->display.optimize_watermarks)
13620 dev_priv->display.optimize_watermarks(intel_cstate);
13623 mutex_lock(&dev->struct_mutex);
13624 drm_atomic_helper_cleanup_planes(dev, state);
13625 mutex_unlock(&dev->struct_mutex);
13628 intel_modeset_check_state(dev, state);
13630 drm_atomic_state_free(state);
13632 /* As one of the primary mmio accessors, KMS has a high likelihood
13633 * of triggering bugs in unclaimed access. After we finish
13634 * modesetting, see if an error has been flagged, and if so
13635 * enable debugging for the next modeset - and hope we catch
13638 * XXX note that we assume display power is on at this point.
13639 * This might hold true now but we need to add pm helper to check
13640 * unclaimed only when the hardware is on, as atomic commits
13641 * can happen also when the device is completely off.
13643 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13648 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13650 struct drm_device *dev = crtc->dev;
13651 struct drm_atomic_state *state;
13652 struct drm_crtc_state *crtc_state;
13655 state = drm_atomic_state_alloc(dev);
13657 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13662 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13665 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13666 ret = PTR_ERR_OR_ZERO(crtc_state);
13668 if (!crtc_state->active)
13671 crtc_state->mode_changed = true;
13672 ret = drm_atomic_commit(state);
13675 if (ret == -EDEADLK) {
13676 drm_atomic_state_clear(state);
13677 drm_modeset_backoff(state->acquire_ctx);
13683 drm_atomic_state_free(state);
13686 #undef for_each_intel_crtc_masked
13688 static const struct drm_crtc_funcs intel_crtc_funcs = {
13689 .gamma_set = intel_color_legacy_gamma_set,
13690 .set_config = drm_atomic_helper_set_config,
13691 .destroy = intel_crtc_destroy,
13692 .page_flip = intel_crtc_page_flip,
13693 .atomic_duplicate_state = intel_crtc_duplicate_state,
13694 .atomic_destroy_state = intel_crtc_destroy_state,
13698 * intel_prepare_plane_fb - Prepare fb for usage on plane
13699 * @plane: drm plane to prepare for
13700 * @fb: framebuffer to prepare for presentation
13702 * Prepares a framebuffer for usage on a display plane. Generally this
13703 * involves pinning the underlying object and updating the frontbuffer tracking
13704 * bits. Some older platforms need special physical address handling for
13707 * Must be called with struct_mutex held.
13709 * Returns 0 on success, negative error code on failure.
13712 intel_prepare_plane_fb(struct drm_plane *plane,
13713 const struct drm_plane_state *new_state)
13715 struct drm_device *dev = plane->dev;
13716 struct drm_framebuffer *fb = new_state->fb;
13717 struct intel_plane *intel_plane = to_intel_plane(plane);
13718 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13719 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13722 if (!obj && !old_obj)
13726 struct drm_crtc_state *crtc_state =
13727 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13729 /* Big Hammer, we also need to ensure that any pending
13730 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13731 * current scanout is retired before unpinning the old
13732 * framebuffer. Note that we rely on userspace rendering
13733 * into the buffer attached to the pipe they are waiting
13734 * on. If not, userspace generates a GPU hang with IPEHR
13735 * point to the MI_WAIT_FOR_EVENT.
13737 * This should only fail upon a hung GPU, in which case we
13738 * can safely continue.
13740 if (needs_modeset(crtc_state))
13741 ret = i915_gem_object_wait_rendering(old_obj, true);
13743 /* Swallow -EIO errors to allow updates during hw lockup. */
13744 if (ret && ret != -EIO)
13748 /* For framebuffer backed by dmabuf, wait for fence */
13749 if (obj && obj->base.dma_buf) {
13752 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13754 MAX_SCHEDULE_TIMEOUT);
13755 if (lret == -ERESTARTSYS)
13758 WARN(lret < 0, "waiting returns %li\n", lret);
13763 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13764 INTEL_INFO(dev)->cursor_needs_physical) {
13765 int align = IS_I830(dev) ? 16 * 1024 : 256;
13766 ret = i915_gem_object_attach_phys(obj, align);
13768 DRM_DEBUG_KMS("failed to attach phys object\n");
13770 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13775 struct intel_plane_state *plane_state =
13776 to_intel_plane_state(new_state);
13778 i915_gem_request_assign(&plane_state->wait_req,
13779 obj->last_write_req);
13782 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13789 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13790 * @plane: drm plane to clean up for
13791 * @fb: old framebuffer that was on plane
13793 * Cleans up a framebuffer that has just been removed from a plane.
13795 * Must be called with struct_mutex held.
13798 intel_cleanup_plane_fb(struct drm_plane *plane,
13799 const struct drm_plane_state *old_state)
13801 struct drm_device *dev = plane->dev;
13802 struct intel_plane *intel_plane = to_intel_plane(plane);
13803 struct intel_plane_state *old_intel_state;
13804 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13805 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13807 old_intel_state = to_intel_plane_state(old_state);
13809 if (!obj && !old_obj)
13812 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13813 !INTEL_INFO(dev)->cursor_needs_physical))
13814 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13816 /* prepare_fb aborted? */
13817 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13818 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13819 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13821 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13825 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13828 struct drm_device *dev;
13829 struct drm_i915_private *dev_priv;
13830 int crtc_clock, cdclk;
13832 if (!intel_crtc || !crtc_state->base.enable)
13833 return DRM_PLANE_HELPER_NO_SCALING;
13835 dev = intel_crtc->base.dev;
13836 dev_priv = dev->dev_private;
13837 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13838 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13840 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13841 return DRM_PLANE_HELPER_NO_SCALING;
13844 * skl max scale is lower of:
13845 * close to 3 but not 3, -1 is for that purpose
13849 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13855 intel_check_primary_plane(struct drm_plane *plane,
13856 struct intel_crtc_state *crtc_state,
13857 struct intel_plane_state *state)
13859 struct drm_crtc *crtc = state->base.crtc;
13860 struct drm_framebuffer *fb = state->base.fb;
13861 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13862 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13863 bool can_position = false;
13865 if (INTEL_INFO(plane->dev)->gen >= 9) {
13866 /* use scaler when colorkey is not required */
13867 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13869 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13871 can_position = true;
13874 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13875 &state->dst, &state->clip,
13876 min_scale, max_scale,
13877 can_position, true,
13881 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13882 struct drm_crtc_state *old_crtc_state)
13884 struct drm_device *dev = crtc->dev;
13885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13886 struct intel_crtc_state *old_intel_state =
13887 to_intel_crtc_state(old_crtc_state);
13888 bool modeset = needs_modeset(crtc->state);
13890 /* Perform vblank evasion around commit operation */
13891 intel_pipe_update_start(intel_crtc);
13896 if (to_intel_crtc_state(crtc->state)->update_pipe)
13897 intel_update_pipe_config(intel_crtc, old_intel_state);
13898 else if (INTEL_INFO(dev)->gen >= 9)
13899 skl_detach_scalers(intel_crtc);
13902 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13903 struct drm_crtc_state *old_crtc_state)
13905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13907 intel_pipe_update_end(intel_crtc);
13911 * intel_plane_destroy - destroy a plane
13912 * @plane: plane to destroy
13914 * Common destruction function for all types of planes (primary, cursor,
13917 void intel_plane_destroy(struct drm_plane *plane)
13919 struct intel_plane *intel_plane = to_intel_plane(plane);
13920 drm_plane_cleanup(plane);
13921 kfree(intel_plane);
13924 const struct drm_plane_funcs intel_plane_funcs = {
13925 .update_plane = drm_atomic_helper_update_plane,
13926 .disable_plane = drm_atomic_helper_disable_plane,
13927 .destroy = intel_plane_destroy,
13928 .set_property = drm_atomic_helper_plane_set_property,
13929 .atomic_get_property = intel_plane_atomic_get_property,
13930 .atomic_set_property = intel_plane_atomic_set_property,
13931 .atomic_duplicate_state = intel_plane_duplicate_state,
13932 .atomic_destroy_state = intel_plane_destroy_state,
13936 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13939 struct intel_plane *primary;
13940 struct intel_plane_state *state;
13941 const uint32_t *intel_primary_formats;
13942 unsigned int num_formats;
13944 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13945 if (primary == NULL)
13948 state = intel_create_plane_state(&primary->base);
13953 primary->base.state = &state->base;
13955 primary->can_scale = false;
13956 primary->max_downscale = 1;
13957 if (INTEL_INFO(dev)->gen >= 9) {
13958 primary->can_scale = true;
13959 state->scaler_id = -1;
13961 primary->pipe = pipe;
13962 primary->plane = pipe;
13963 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13964 primary->check_plane = intel_check_primary_plane;
13965 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13966 primary->plane = !pipe;
13968 if (INTEL_INFO(dev)->gen >= 9) {
13969 intel_primary_formats = skl_primary_formats;
13970 num_formats = ARRAY_SIZE(skl_primary_formats);
13972 primary->update_plane = skylake_update_primary_plane;
13973 primary->disable_plane = skylake_disable_primary_plane;
13974 } else if (HAS_PCH_SPLIT(dev)) {
13975 intel_primary_formats = i965_primary_formats;
13976 num_formats = ARRAY_SIZE(i965_primary_formats);
13978 primary->update_plane = ironlake_update_primary_plane;
13979 primary->disable_plane = i9xx_disable_primary_plane;
13980 } else if (INTEL_INFO(dev)->gen >= 4) {
13981 intel_primary_formats = i965_primary_formats;
13982 num_formats = ARRAY_SIZE(i965_primary_formats);
13984 primary->update_plane = i9xx_update_primary_plane;
13985 primary->disable_plane = i9xx_disable_primary_plane;
13987 intel_primary_formats = i8xx_primary_formats;
13988 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13990 primary->update_plane = i9xx_update_primary_plane;
13991 primary->disable_plane = i9xx_disable_primary_plane;
13994 drm_universal_plane_init(dev, &primary->base, 0,
13995 &intel_plane_funcs,
13996 intel_primary_formats, num_formats,
13997 DRM_PLANE_TYPE_PRIMARY, NULL);
13999 if (INTEL_INFO(dev)->gen >= 4)
14000 intel_create_rotation_property(dev, primary);
14002 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14004 return &primary->base;
14007 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14009 if (!dev->mode_config.rotation_property) {
14010 unsigned long flags = BIT(DRM_ROTATE_0) |
14011 BIT(DRM_ROTATE_180);
14013 if (INTEL_INFO(dev)->gen >= 9)
14014 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14016 dev->mode_config.rotation_property =
14017 drm_mode_create_rotation_property(dev, flags);
14019 if (dev->mode_config.rotation_property)
14020 drm_object_attach_property(&plane->base.base,
14021 dev->mode_config.rotation_property,
14022 plane->base.state->rotation);
14026 intel_check_cursor_plane(struct drm_plane *plane,
14027 struct intel_crtc_state *crtc_state,
14028 struct intel_plane_state *state)
14030 struct drm_crtc *crtc = crtc_state->base.crtc;
14031 struct drm_framebuffer *fb = state->base.fb;
14032 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14033 enum pipe pipe = to_intel_plane(plane)->pipe;
14037 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14038 &state->dst, &state->clip,
14039 DRM_PLANE_HELPER_NO_SCALING,
14040 DRM_PLANE_HELPER_NO_SCALING,
14041 true, true, &state->visible);
14045 /* if we want to turn off the cursor ignore width and height */
14049 /* Check for which cursor types we support */
14050 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14051 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14052 state->base.crtc_w, state->base.crtc_h);
14056 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14057 if (obj->base.size < stride * state->base.crtc_h) {
14058 DRM_DEBUG_KMS("buffer is too small\n");
14062 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14063 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14068 * There's something wrong with the cursor on CHV pipe C.
14069 * If it straddles the left edge of the screen then
14070 * moving it away from the edge or disabling it often
14071 * results in a pipe underrun, and often that can lead to
14072 * dead pipe (constant underrun reported, and it scans
14073 * out just a solid color). To recover from that, the
14074 * display power well must be turned off and on again.
14075 * Refuse the put the cursor into that compromised position.
14077 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14078 state->visible && state->base.crtc_x < 0) {
14079 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14087 intel_disable_cursor_plane(struct drm_plane *plane,
14088 struct drm_crtc *crtc)
14090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14092 intel_crtc->cursor_addr = 0;
14093 intel_crtc_update_cursor(crtc, NULL);
14097 intel_update_cursor_plane(struct drm_plane *plane,
14098 const struct intel_crtc_state *crtc_state,
14099 const struct intel_plane_state *state)
14101 struct drm_crtc *crtc = crtc_state->base.crtc;
14102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14103 struct drm_device *dev = plane->dev;
14104 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14109 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14110 addr = i915_gem_obj_ggtt_offset(obj);
14112 addr = obj->phys_handle->busaddr;
14114 intel_crtc->cursor_addr = addr;
14115 intel_crtc_update_cursor(crtc, state);
14118 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14121 struct intel_plane *cursor;
14122 struct intel_plane_state *state;
14124 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14125 if (cursor == NULL)
14128 state = intel_create_plane_state(&cursor->base);
14133 cursor->base.state = &state->base;
14135 cursor->can_scale = false;
14136 cursor->max_downscale = 1;
14137 cursor->pipe = pipe;
14138 cursor->plane = pipe;
14139 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14140 cursor->check_plane = intel_check_cursor_plane;
14141 cursor->update_plane = intel_update_cursor_plane;
14142 cursor->disable_plane = intel_disable_cursor_plane;
14144 drm_universal_plane_init(dev, &cursor->base, 0,
14145 &intel_plane_funcs,
14146 intel_cursor_formats,
14147 ARRAY_SIZE(intel_cursor_formats),
14148 DRM_PLANE_TYPE_CURSOR, NULL);
14150 if (INTEL_INFO(dev)->gen >= 4) {
14151 if (!dev->mode_config.rotation_property)
14152 dev->mode_config.rotation_property =
14153 drm_mode_create_rotation_property(dev,
14154 BIT(DRM_ROTATE_0) |
14155 BIT(DRM_ROTATE_180));
14156 if (dev->mode_config.rotation_property)
14157 drm_object_attach_property(&cursor->base.base,
14158 dev->mode_config.rotation_property,
14159 state->base.rotation);
14162 if (INTEL_INFO(dev)->gen >=9)
14163 state->scaler_id = -1;
14165 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14167 return &cursor->base;
14170 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14171 struct intel_crtc_state *crtc_state)
14174 struct intel_scaler *intel_scaler;
14175 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14177 for (i = 0; i < intel_crtc->num_scalers; i++) {
14178 intel_scaler = &scaler_state->scalers[i];
14179 intel_scaler->in_use = 0;
14180 intel_scaler->mode = PS_SCALER_MODE_DYN;
14183 scaler_state->scaler_id = -1;
14186 static void intel_crtc_init(struct drm_device *dev, int pipe)
14188 struct drm_i915_private *dev_priv = dev->dev_private;
14189 struct intel_crtc *intel_crtc;
14190 struct intel_crtc_state *crtc_state = NULL;
14191 struct drm_plane *primary = NULL;
14192 struct drm_plane *cursor = NULL;
14195 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14196 if (intel_crtc == NULL)
14199 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14202 intel_crtc->config = crtc_state;
14203 intel_crtc->base.state = &crtc_state->base;
14204 crtc_state->base.crtc = &intel_crtc->base;
14206 /* initialize shared scalers */
14207 if (INTEL_INFO(dev)->gen >= 9) {
14208 if (pipe == PIPE_C)
14209 intel_crtc->num_scalers = 1;
14211 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14213 skl_init_scalers(dev, intel_crtc, crtc_state);
14216 primary = intel_primary_plane_create(dev, pipe);
14220 cursor = intel_cursor_plane_create(dev, pipe);
14224 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14225 cursor, &intel_crtc_funcs, NULL);
14230 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14231 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14233 intel_crtc->pipe = pipe;
14234 intel_crtc->plane = pipe;
14235 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14236 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14237 intel_crtc->plane = !pipe;
14240 intel_crtc->cursor_base = ~0;
14241 intel_crtc->cursor_cntl = ~0;
14242 intel_crtc->cursor_size = ~0;
14244 intel_crtc->wm.cxsr_allowed = true;
14246 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14247 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14248 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14249 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14251 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14253 intel_color_init(&intel_crtc->base);
14255 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14260 drm_plane_cleanup(primary);
14262 drm_plane_cleanup(cursor);
14267 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14269 struct drm_encoder *encoder = connector->base.encoder;
14270 struct drm_device *dev = connector->base.dev;
14272 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14274 if (!encoder || WARN_ON(!encoder->crtc))
14275 return INVALID_PIPE;
14277 return to_intel_crtc(encoder->crtc)->pipe;
14280 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14281 struct drm_file *file)
14283 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14284 struct drm_crtc *drmmode_crtc;
14285 struct intel_crtc *crtc;
14287 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14289 if (!drmmode_crtc) {
14290 DRM_ERROR("no such CRTC id\n");
14294 crtc = to_intel_crtc(drmmode_crtc);
14295 pipe_from_crtc_id->pipe = crtc->pipe;
14300 static int intel_encoder_clones(struct intel_encoder *encoder)
14302 struct drm_device *dev = encoder->base.dev;
14303 struct intel_encoder *source_encoder;
14304 int index_mask = 0;
14307 for_each_intel_encoder(dev, source_encoder) {
14308 if (encoders_cloneable(encoder, source_encoder))
14309 index_mask |= (1 << entry);
14317 static bool has_edp_a(struct drm_device *dev)
14319 struct drm_i915_private *dev_priv = dev->dev_private;
14321 if (!IS_MOBILE(dev))
14324 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14327 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14333 static bool intel_crt_present(struct drm_device *dev)
14335 struct drm_i915_private *dev_priv = dev->dev_private;
14337 if (INTEL_INFO(dev)->gen >= 9)
14340 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14343 if (IS_CHERRYVIEW(dev))
14346 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14349 /* DDI E can't be used if DDI A requires 4 lanes */
14350 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14353 if (!dev_priv->vbt.int_crt_support)
14359 static void intel_setup_outputs(struct drm_device *dev)
14361 struct drm_i915_private *dev_priv = dev->dev_private;
14362 struct intel_encoder *encoder;
14363 bool dpd_is_edp = false;
14365 intel_lvds_init(dev);
14367 if (intel_crt_present(dev))
14368 intel_crt_init(dev);
14370 if (IS_BROXTON(dev)) {
14372 * FIXME: Broxton doesn't support port detection via the
14373 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14374 * detect the ports.
14376 intel_ddi_init(dev, PORT_A);
14377 intel_ddi_init(dev, PORT_B);
14378 intel_ddi_init(dev, PORT_C);
14379 } else if (HAS_DDI(dev)) {
14383 * Haswell uses DDI functions to detect digital outputs.
14384 * On SKL pre-D0 the strap isn't connected, so we assume
14387 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14388 /* WaIgnoreDDIAStrap: skl */
14389 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14390 intel_ddi_init(dev, PORT_A);
14392 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14394 found = I915_READ(SFUSE_STRAP);
14396 if (found & SFUSE_STRAP_DDIB_DETECTED)
14397 intel_ddi_init(dev, PORT_B);
14398 if (found & SFUSE_STRAP_DDIC_DETECTED)
14399 intel_ddi_init(dev, PORT_C);
14400 if (found & SFUSE_STRAP_DDID_DETECTED)
14401 intel_ddi_init(dev, PORT_D);
14403 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14405 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14406 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14407 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14408 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14409 intel_ddi_init(dev, PORT_E);
14411 } else if (HAS_PCH_SPLIT(dev)) {
14413 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14415 if (has_edp_a(dev))
14416 intel_dp_init(dev, DP_A, PORT_A);
14418 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14419 /* PCH SDVOB multiplex with HDMIB */
14420 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14422 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14423 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14424 intel_dp_init(dev, PCH_DP_B, PORT_B);
14427 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14428 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14430 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14431 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14433 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14434 intel_dp_init(dev, PCH_DP_C, PORT_C);
14436 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14437 intel_dp_init(dev, PCH_DP_D, PORT_D);
14438 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14440 * The DP_DETECTED bit is the latched state of the DDC
14441 * SDA pin at boot. However since eDP doesn't require DDC
14442 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14443 * eDP ports may have been muxed to an alternate function.
14444 * Thus we can't rely on the DP_DETECTED bit alone to detect
14445 * eDP ports. Consult the VBT as well as DP_DETECTED to
14446 * detect eDP ports.
14448 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14449 !intel_dp_is_edp(dev, PORT_B))
14450 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14451 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14452 intel_dp_is_edp(dev, PORT_B))
14453 intel_dp_init(dev, VLV_DP_B, PORT_B);
14455 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14456 !intel_dp_is_edp(dev, PORT_C))
14457 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14458 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14459 intel_dp_is_edp(dev, PORT_C))
14460 intel_dp_init(dev, VLV_DP_C, PORT_C);
14462 if (IS_CHERRYVIEW(dev)) {
14463 /* eDP not supported on port D, so don't check VBT */
14464 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14465 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14466 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14467 intel_dp_init(dev, CHV_DP_D, PORT_D);
14470 intel_dsi_init(dev);
14471 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14472 bool found = false;
14474 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14475 DRM_DEBUG_KMS("probing SDVOB\n");
14476 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14477 if (!found && IS_G4X(dev)) {
14478 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14479 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14482 if (!found && IS_G4X(dev))
14483 intel_dp_init(dev, DP_B, PORT_B);
14486 /* Before G4X SDVOC doesn't have its own detect register */
14488 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14489 DRM_DEBUG_KMS("probing SDVOC\n");
14490 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14493 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14496 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14497 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14500 intel_dp_init(dev, DP_C, PORT_C);
14504 (I915_READ(DP_D) & DP_DETECTED))
14505 intel_dp_init(dev, DP_D, PORT_D);
14506 } else if (IS_GEN2(dev))
14507 intel_dvo_init(dev);
14509 if (SUPPORTS_TV(dev))
14510 intel_tv_init(dev);
14512 intel_psr_init(dev);
14514 for_each_intel_encoder(dev, encoder) {
14515 encoder->base.possible_crtcs = encoder->crtc_mask;
14516 encoder->base.possible_clones =
14517 intel_encoder_clones(encoder);
14520 intel_init_pch_refclk(dev);
14522 drm_helper_move_panel_connectors_to_head(dev);
14525 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14527 struct drm_device *dev = fb->dev;
14528 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14530 drm_framebuffer_cleanup(fb);
14531 mutex_lock(&dev->struct_mutex);
14532 WARN_ON(!intel_fb->obj->framebuffer_references--);
14533 drm_gem_object_unreference(&intel_fb->obj->base);
14534 mutex_unlock(&dev->struct_mutex);
14538 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14539 struct drm_file *file,
14540 unsigned int *handle)
14542 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14543 struct drm_i915_gem_object *obj = intel_fb->obj;
14545 if (obj->userptr.mm) {
14546 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14550 return drm_gem_handle_create(file, &obj->base, handle);
14553 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14554 struct drm_file *file,
14555 unsigned flags, unsigned color,
14556 struct drm_clip_rect *clips,
14557 unsigned num_clips)
14559 struct drm_device *dev = fb->dev;
14560 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14561 struct drm_i915_gem_object *obj = intel_fb->obj;
14563 mutex_lock(&dev->struct_mutex);
14564 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14565 mutex_unlock(&dev->struct_mutex);
14570 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14571 .destroy = intel_user_framebuffer_destroy,
14572 .create_handle = intel_user_framebuffer_create_handle,
14573 .dirty = intel_user_framebuffer_dirty,
14577 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14578 uint32_t pixel_format)
14580 u32 gen = INTEL_INFO(dev)->gen;
14583 int cpp = drm_format_plane_cpp(pixel_format, 0);
14585 /* "The stride in bytes must not exceed the of the size of 8K
14586 * pixels and 32K bytes."
14588 return min(8192 * cpp, 32768);
14589 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14591 } else if (gen >= 4) {
14592 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14596 } else if (gen >= 3) {
14597 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14602 /* XXX DSPC is limited to 4k tiled */
14607 static int intel_framebuffer_init(struct drm_device *dev,
14608 struct intel_framebuffer *intel_fb,
14609 struct drm_mode_fb_cmd2 *mode_cmd,
14610 struct drm_i915_gem_object *obj)
14612 struct drm_i915_private *dev_priv = to_i915(dev);
14613 unsigned int aligned_height;
14615 u32 pitch_limit, stride_alignment;
14617 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14619 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14620 /* Enforce that fb modifier and tiling mode match, but only for
14621 * X-tiled. This is needed for FBC. */
14622 if (!!(obj->tiling_mode == I915_TILING_X) !=
14623 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14624 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14628 if (obj->tiling_mode == I915_TILING_X)
14629 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14630 else if (obj->tiling_mode == I915_TILING_Y) {
14631 DRM_DEBUG("No Y tiling for legacy addfb\n");
14636 /* Passed in modifier sanity checking. */
14637 switch (mode_cmd->modifier[0]) {
14638 case I915_FORMAT_MOD_Y_TILED:
14639 case I915_FORMAT_MOD_Yf_TILED:
14640 if (INTEL_INFO(dev)->gen < 9) {
14641 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14642 mode_cmd->modifier[0]);
14645 case DRM_FORMAT_MOD_NONE:
14646 case I915_FORMAT_MOD_X_TILED:
14649 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14650 mode_cmd->modifier[0]);
14654 stride_alignment = intel_fb_stride_alignment(dev_priv,
14655 mode_cmd->modifier[0],
14656 mode_cmd->pixel_format);
14657 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14658 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14659 mode_cmd->pitches[0], stride_alignment);
14663 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14664 mode_cmd->pixel_format);
14665 if (mode_cmd->pitches[0] > pitch_limit) {
14666 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14667 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14668 "tiled" : "linear",
14669 mode_cmd->pitches[0], pitch_limit);
14673 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14674 mode_cmd->pitches[0] != obj->stride) {
14675 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14676 mode_cmd->pitches[0], obj->stride);
14680 /* Reject formats not supported by any plane early. */
14681 switch (mode_cmd->pixel_format) {
14682 case DRM_FORMAT_C8:
14683 case DRM_FORMAT_RGB565:
14684 case DRM_FORMAT_XRGB8888:
14685 case DRM_FORMAT_ARGB8888:
14687 case DRM_FORMAT_XRGB1555:
14688 if (INTEL_INFO(dev)->gen > 3) {
14689 DRM_DEBUG("unsupported pixel format: %s\n",
14690 drm_get_format_name(mode_cmd->pixel_format));
14694 case DRM_FORMAT_ABGR8888:
14695 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14696 INTEL_INFO(dev)->gen < 9) {
14697 DRM_DEBUG("unsupported pixel format: %s\n",
14698 drm_get_format_name(mode_cmd->pixel_format));
14702 case DRM_FORMAT_XBGR8888:
14703 case DRM_FORMAT_XRGB2101010:
14704 case DRM_FORMAT_XBGR2101010:
14705 if (INTEL_INFO(dev)->gen < 4) {
14706 DRM_DEBUG("unsupported pixel format: %s\n",
14707 drm_get_format_name(mode_cmd->pixel_format));
14711 case DRM_FORMAT_ABGR2101010:
14712 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14713 DRM_DEBUG("unsupported pixel format: %s\n",
14714 drm_get_format_name(mode_cmd->pixel_format));
14718 case DRM_FORMAT_YUYV:
14719 case DRM_FORMAT_UYVY:
14720 case DRM_FORMAT_YVYU:
14721 case DRM_FORMAT_VYUY:
14722 if (INTEL_INFO(dev)->gen < 5) {
14723 DRM_DEBUG("unsupported pixel format: %s\n",
14724 drm_get_format_name(mode_cmd->pixel_format));
14729 DRM_DEBUG("unsupported pixel format: %s\n",
14730 drm_get_format_name(mode_cmd->pixel_format));
14734 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14735 if (mode_cmd->offsets[0] != 0)
14738 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14739 mode_cmd->pixel_format,
14740 mode_cmd->modifier[0]);
14741 /* FIXME drm helper for size checks (especially planar formats)? */
14742 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14745 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14746 intel_fb->obj = obj;
14748 intel_fill_fb_info(dev_priv, &intel_fb->base);
14750 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14752 DRM_ERROR("framebuffer init failed %d\n", ret);
14756 intel_fb->obj->framebuffer_references++;
14761 static struct drm_framebuffer *
14762 intel_user_framebuffer_create(struct drm_device *dev,
14763 struct drm_file *filp,
14764 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14766 struct drm_framebuffer *fb;
14767 struct drm_i915_gem_object *obj;
14768 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14770 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14771 mode_cmd.handles[0]));
14772 if (&obj->base == NULL)
14773 return ERR_PTR(-ENOENT);
14775 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14777 drm_gem_object_unreference_unlocked(&obj->base);
14782 #ifndef CONFIG_DRM_FBDEV_EMULATION
14783 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14788 static const struct drm_mode_config_funcs intel_mode_funcs = {
14789 .fb_create = intel_user_framebuffer_create,
14790 .output_poll_changed = intel_fbdev_output_poll_changed,
14791 .atomic_check = intel_atomic_check,
14792 .atomic_commit = intel_atomic_commit,
14793 .atomic_state_alloc = intel_atomic_state_alloc,
14794 .atomic_state_clear = intel_atomic_state_clear,
14798 * intel_init_display_hooks - initialize the display modesetting hooks
14799 * @dev_priv: device private
14801 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14803 if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
14804 dev_priv->display.find_dpll = g4x_find_best_dpll;
14805 else if (IS_CHERRYVIEW(dev_priv))
14806 dev_priv->display.find_dpll = chv_find_best_dpll;
14807 else if (IS_VALLEYVIEW(dev_priv))
14808 dev_priv->display.find_dpll = vlv_find_best_dpll;
14809 else if (IS_PINEVIEW(dev_priv))
14810 dev_priv->display.find_dpll = pnv_find_best_dpll;
14812 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14814 if (INTEL_INFO(dev_priv)->gen >= 9) {
14815 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14816 dev_priv->display.get_initial_plane_config =
14817 skylake_get_initial_plane_config;
14818 dev_priv->display.crtc_compute_clock =
14819 haswell_crtc_compute_clock;
14820 dev_priv->display.crtc_enable = haswell_crtc_enable;
14821 dev_priv->display.crtc_disable = haswell_crtc_disable;
14822 } else if (HAS_DDI(dev_priv)) {
14823 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14824 dev_priv->display.get_initial_plane_config =
14825 ironlake_get_initial_plane_config;
14826 dev_priv->display.crtc_compute_clock =
14827 haswell_crtc_compute_clock;
14828 dev_priv->display.crtc_enable = haswell_crtc_enable;
14829 dev_priv->display.crtc_disable = haswell_crtc_disable;
14830 } else if (HAS_PCH_SPLIT(dev_priv)) {
14831 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14832 dev_priv->display.get_initial_plane_config =
14833 ironlake_get_initial_plane_config;
14834 dev_priv->display.crtc_compute_clock =
14835 ironlake_crtc_compute_clock;
14836 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14837 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14838 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14839 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14840 dev_priv->display.get_initial_plane_config =
14841 i9xx_get_initial_plane_config;
14842 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14843 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14844 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14846 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14847 dev_priv->display.get_initial_plane_config =
14848 i9xx_get_initial_plane_config;
14849 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14850 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14851 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14854 /* Returns the core display clock speed */
14855 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14856 dev_priv->display.get_display_clock_speed =
14857 skylake_get_display_clock_speed;
14858 else if (IS_BROXTON(dev_priv))
14859 dev_priv->display.get_display_clock_speed =
14860 broxton_get_display_clock_speed;
14861 else if (IS_BROADWELL(dev_priv))
14862 dev_priv->display.get_display_clock_speed =
14863 broadwell_get_display_clock_speed;
14864 else if (IS_HASWELL(dev_priv))
14865 dev_priv->display.get_display_clock_speed =
14866 haswell_get_display_clock_speed;
14867 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14868 dev_priv->display.get_display_clock_speed =
14869 valleyview_get_display_clock_speed;
14870 else if (IS_GEN5(dev_priv))
14871 dev_priv->display.get_display_clock_speed =
14872 ilk_get_display_clock_speed;
14873 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14874 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14875 dev_priv->display.get_display_clock_speed =
14876 i945_get_display_clock_speed;
14877 else if (IS_GM45(dev_priv))
14878 dev_priv->display.get_display_clock_speed =
14879 gm45_get_display_clock_speed;
14880 else if (IS_CRESTLINE(dev_priv))
14881 dev_priv->display.get_display_clock_speed =
14882 i965gm_get_display_clock_speed;
14883 else if (IS_PINEVIEW(dev_priv))
14884 dev_priv->display.get_display_clock_speed =
14885 pnv_get_display_clock_speed;
14886 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14887 dev_priv->display.get_display_clock_speed =
14888 g33_get_display_clock_speed;
14889 else if (IS_I915G(dev_priv))
14890 dev_priv->display.get_display_clock_speed =
14891 i915_get_display_clock_speed;
14892 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14893 dev_priv->display.get_display_clock_speed =
14894 i9xx_misc_get_display_clock_speed;
14895 else if (IS_I915GM(dev_priv))
14896 dev_priv->display.get_display_clock_speed =
14897 i915gm_get_display_clock_speed;
14898 else if (IS_I865G(dev_priv))
14899 dev_priv->display.get_display_clock_speed =
14900 i865_get_display_clock_speed;
14901 else if (IS_I85X(dev_priv))
14902 dev_priv->display.get_display_clock_speed =
14903 i85x_get_display_clock_speed;
14905 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14906 dev_priv->display.get_display_clock_speed =
14907 i830_get_display_clock_speed;
14910 if (IS_GEN5(dev_priv)) {
14911 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14912 } else if (IS_GEN6(dev_priv)) {
14913 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14914 } else if (IS_IVYBRIDGE(dev_priv)) {
14915 /* FIXME: detect B0+ stepping and use auto training */
14916 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14917 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14918 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14919 if (IS_BROADWELL(dev_priv)) {
14920 dev_priv->display.modeset_commit_cdclk =
14921 broadwell_modeset_commit_cdclk;
14922 dev_priv->display.modeset_calc_cdclk =
14923 broadwell_modeset_calc_cdclk;
14925 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14926 dev_priv->display.modeset_commit_cdclk =
14927 valleyview_modeset_commit_cdclk;
14928 dev_priv->display.modeset_calc_cdclk =
14929 valleyview_modeset_calc_cdclk;
14930 } else if (IS_BROXTON(dev_priv)) {
14931 dev_priv->display.modeset_commit_cdclk =
14932 broxton_modeset_commit_cdclk;
14933 dev_priv->display.modeset_calc_cdclk =
14934 broxton_modeset_calc_cdclk;
14937 switch (INTEL_INFO(dev_priv)->gen) {
14939 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14943 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14948 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14952 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14955 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14956 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14959 /* Drop through - unsupported since execlist only. */
14961 /* Default just returns -ENODEV to indicate unsupported */
14962 dev_priv->display.queue_flip = intel_default_queue_flip;
14967 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14968 * resume, or other times. This quirk makes sure that's the case for
14969 * affected systems.
14971 static void quirk_pipea_force(struct drm_device *dev)
14973 struct drm_i915_private *dev_priv = dev->dev_private;
14975 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14976 DRM_INFO("applying pipe a force quirk\n");
14979 static void quirk_pipeb_force(struct drm_device *dev)
14981 struct drm_i915_private *dev_priv = dev->dev_private;
14983 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14984 DRM_INFO("applying pipe b force quirk\n");
14988 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14990 static void quirk_ssc_force_disable(struct drm_device *dev)
14992 struct drm_i915_private *dev_priv = dev->dev_private;
14993 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14994 DRM_INFO("applying lvds SSC disable quirk\n");
14998 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15001 static void quirk_invert_brightness(struct drm_device *dev)
15003 struct drm_i915_private *dev_priv = dev->dev_private;
15004 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15005 DRM_INFO("applying inverted panel brightness quirk\n");
15008 /* Some VBT's incorrectly indicate no backlight is present */
15009 static void quirk_backlight_present(struct drm_device *dev)
15011 struct drm_i915_private *dev_priv = dev->dev_private;
15012 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15013 DRM_INFO("applying backlight present quirk\n");
15016 struct intel_quirk {
15018 int subsystem_vendor;
15019 int subsystem_device;
15020 void (*hook)(struct drm_device *dev);
15023 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15024 struct intel_dmi_quirk {
15025 void (*hook)(struct drm_device *dev);
15026 const struct dmi_system_id (*dmi_id_list)[];
15029 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15031 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15035 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15037 .dmi_id_list = &(const struct dmi_system_id[]) {
15039 .callback = intel_dmi_reverse_brightness,
15040 .ident = "NCR Corporation",
15041 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15042 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15045 { } /* terminating entry */
15047 .hook = quirk_invert_brightness,
15051 static struct intel_quirk intel_quirks[] = {
15052 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15053 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15055 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15056 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15058 /* 830 needs to leave pipe A & dpll A up */
15059 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15061 /* 830 needs to leave pipe B & dpll B up */
15062 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15064 /* Lenovo U160 cannot use SSC on LVDS */
15065 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15067 /* Sony Vaio Y cannot use SSC on LVDS */
15068 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15070 /* Acer Aspire 5734Z must invert backlight brightness */
15071 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15073 /* Acer/eMachines G725 */
15074 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15076 /* Acer/eMachines e725 */
15077 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15079 /* Acer/Packard Bell NCL20 */
15080 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15082 /* Acer Aspire 4736Z */
15083 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15085 /* Acer Aspire 5336 */
15086 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15088 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15089 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15091 /* Acer C720 Chromebook (Core i3 4005U) */
15092 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15094 /* Apple Macbook 2,1 (Core 2 T7400) */
15095 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15097 /* Apple Macbook 4,1 */
15098 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15100 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15101 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15103 /* HP Chromebook 14 (Celeron 2955U) */
15104 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15106 /* Dell Chromebook 11 */
15107 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15109 /* Dell Chromebook 11 (2015 version) */
15110 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15113 static void intel_init_quirks(struct drm_device *dev)
15115 struct pci_dev *d = dev->pdev;
15118 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15119 struct intel_quirk *q = &intel_quirks[i];
15121 if (d->device == q->device &&
15122 (d->subsystem_vendor == q->subsystem_vendor ||
15123 q->subsystem_vendor == PCI_ANY_ID) &&
15124 (d->subsystem_device == q->subsystem_device ||
15125 q->subsystem_device == PCI_ANY_ID))
15128 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15129 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15130 intel_dmi_quirks[i].hook(dev);
15134 /* Disable the VGA plane that we never use */
15135 static void i915_disable_vga(struct drm_device *dev)
15137 struct drm_i915_private *dev_priv = dev->dev_private;
15139 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15141 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15142 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15143 outb(SR01, VGA_SR_INDEX);
15144 sr1 = inb(VGA_SR_DATA);
15145 outb(sr1 | 1<<5, VGA_SR_DATA);
15146 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15149 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15150 POSTING_READ(vga_reg);
15153 void intel_modeset_init_hw(struct drm_device *dev)
15155 struct drm_i915_private *dev_priv = dev->dev_private;
15157 intel_update_cdclk(dev);
15159 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15161 intel_init_clock_gating(dev);
15162 intel_enable_gt_powersave(dev);
15166 * Calculate what we think the watermarks should be for the state we've read
15167 * out of the hardware and then immediately program those watermarks so that
15168 * we ensure the hardware settings match our internal state.
15170 * We can calculate what we think WM's should be by creating a duplicate of the
15171 * current state (which was constructed during hardware readout) and running it
15172 * through the atomic check code to calculate new watermark values in the
15175 static void sanitize_watermarks(struct drm_device *dev)
15177 struct drm_i915_private *dev_priv = to_i915(dev);
15178 struct drm_atomic_state *state;
15179 struct drm_crtc *crtc;
15180 struct drm_crtc_state *cstate;
15181 struct drm_modeset_acquire_ctx ctx;
15185 /* Only supported on platforms that use atomic watermark design */
15186 if (!dev_priv->display.optimize_watermarks)
15190 * We need to hold connection_mutex before calling duplicate_state so
15191 * that the connector loop is protected.
15193 drm_modeset_acquire_init(&ctx, 0);
15195 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15196 if (ret == -EDEADLK) {
15197 drm_modeset_backoff(&ctx);
15199 } else if (WARN_ON(ret)) {
15203 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15204 if (WARN_ON(IS_ERR(state)))
15208 * Hardware readout is the only time we don't want to calculate
15209 * intermediate watermarks (since we don't trust the current
15212 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15214 ret = intel_atomic_check(dev, state);
15217 * If we fail here, it means that the hardware appears to be
15218 * programmed in a way that shouldn't be possible, given our
15219 * understanding of watermark requirements. This might mean a
15220 * mistake in the hardware readout code or a mistake in the
15221 * watermark calculations for a given platform. Raise a WARN
15222 * so that this is noticeable.
15224 * If this actually happens, we'll have to just leave the
15225 * BIOS-programmed watermarks untouched and hope for the best.
15227 WARN(true, "Could not determine valid watermarks for inherited state\n");
15231 /* Write calculated watermark values back */
15232 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15233 for_each_crtc_in_state(state, crtc, cstate, i) {
15234 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15236 cs->wm.need_postvbl_update = true;
15237 dev_priv->display.optimize_watermarks(cs);
15240 drm_atomic_state_free(state);
15242 drm_modeset_drop_locks(&ctx);
15243 drm_modeset_acquire_fini(&ctx);
15246 void intel_modeset_init(struct drm_device *dev)
15248 struct drm_i915_private *dev_priv = dev->dev_private;
15251 struct intel_crtc *crtc;
15253 drm_mode_config_init(dev);
15255 dev->mode_config.min_width = 0;
15256 dev->mode_config.min_height = 0;
15258 dev->mode_config.preferred_depth = 24;
15259 dev->mode_config.prefer_shadow = 1;
15261 dev->mode_config.allow_fb_modifiers = true;
15263 dev->mode_config.funcs = &intel_mode_funcs;
15265 intel_init_quirks(dev);
15267 intel_init_pm(dev);
15269 if (INTEL_INFO(dev)->num_pipes == 0)
15273 * There may be no VBT; and if the BIOS enabled SSC we can
15274 * just keep using it to avoid unnecessary flicker. Whereas if the
15275 * BIOS isn't using it, don't assume it will work even if the VBT
15276 * indicates as much.
15278 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15279 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15282 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15283 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15284 bios_lvds_use_ssc ? "en" : "dis",
15285 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15286 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15290 if (IS_GEN2(dev)) {
15291 dev->mode_config.max_width = 2048;
15292 dev->mode_config.max_height = 2048;
15293 } else if (IS_GEN3(dev)) {
15294 dev->mode_config.max_width = 4096;
15295 dev->mode_config.max_height = 4096;
15297 dev->mode_config.max_width = 8192;
15298 dev->mode_config.max_height = 8192;
15301 if (IS_845G(dev) || IS_I865G(dev)) {
15302 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15303 dev->mode_config.cursor_height = 1023;
15304 } else if (IS_GEN2(dev)) {
15305 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15306 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15308 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15309 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15312 dev->mode_config.fb_base = dev_priv->ggtt.mappable_base;
15314 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15315 INTEL_INFO(dev)->num_pipes,
15316 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15318 for_each_pipe(dev_priv, pipe) {
15319 intel_crtc_init(dev, pipe);
15320 for_each_sprite(dev_priv, pipe, sprite) {
15321 ret = intel_plane_init(dev, pipe, sprite);
15323 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15324 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15328 intel_update_czclk(dev_priv);
15329 intel_update_rawclk(dev_priv);
15330 intel_update_cdclk(dev);
15332 intel_shared_dpll_init(dev);
15334 /* Just disable it once at startup */
15335 i915_disable_vga(dev);
15336 intel_setup_outputs(dev);
15338 drm_modeset_lock_all(dev);
15339 intel_modeset_setup_hw_state(dev);
15340 drm_modeset_unlock_all(dev);
15342 for_each_intel_crtc(dev, crtc) {
15343 struct intel_initial_plane_config plane_config = {};
15349 * Note that reserving the BIOS fb up front prevents us
15350 * from stuffing other stolen allocations like the ring
15351 * on top. This prevents some ugliness at boot time, and
15352 * can even allow for smooth boot transitions if the BIOS
15353 * fb is large enough for the active pipe configuration.
15355 dev_priv->display.get_initial_plane_config(crtc,
15359 * If the fb is shared between multiple heads, we'll
15360 * just get the first one.
15362 intel_find_initial_plane_obj(crtc, &plane_config);
15366 * Make sure hardware watermarks really match the state we read out.
15367 * Note that we need to do this after reconstructing the BIOS fb's
15368 * since the watermark calculation done here will use pstate->fb.
15370 sanitize_watermarks(dev);
15373 static void intel_enable_pipe_a(struct drm_device *dev)
15375 struct intel_connector *connector;
15376 struct drm_connector *crt = NULL;
15377 struct intel_load_detect_pipe load_detect_temp;
15378 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15380 /* We can't just switch on the pipe A, we need to set things up with a
15381 * proper mode and output configuration. As a gross hack, enable pipe A
15382 * by enabling the load detect pipe once. */
15383 for_each_intel_connector(dev, connector) {
15384 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15385 crt = &connector->base;
15393 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15394 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15398 intel_check_plane_mapping(struct intel_crtc *crtc)
15400 struct drm_device *dev = crtc->base.dev;
15401 struct drm_i915_private *dev_priv = dev->dev_private;
15404 if (INTEL_INFO(dev)->num_pipes == 1)
15407 val = I915_READ(DSPCNTR(!crtc->plane));
15409 if ((val & DISPLAY_PLANE_ENABLE) &&
15410 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15416 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15418 struct drm_device *dev = crtc->base.dev;
15419 struct intel_encoder *encoder;
15421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15427 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15429 struct drm_device *dev = encoder->base.dev;
15430 struct intel_connector *connector;
15432 for_each_connector_on_encoder(dev, &encoder->base, connector)
15438 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15440 struct drm_device *dev = crtc->base.dev;
15441 struct drm_i915_private *dev_priv = dev->dev_private;
15442 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15444 /* Clear any frame start delays used for debugging left by the BIOS */
15445 if (!transcoder_is_dsi(cpu_transcoder)) {
15446 i915_reg_t reg = PIPECONF(cpu_transcoder);
15449 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15452 /* restore vblank interrupts to correct state */
15453 drm_crtc_vblank_reset(&crtc->base);
15454 if (crtc->active) {
15455 struct intel_plane *plane;
15457 drm_crtc_vblank_on(&crtc->base);
15459 /* Disable everything but the primary plane */
15460 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15461 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15464 plane->disable_plane(&plane->base, &crtc->base);
15468 /* We need to sanitize the plane -> pipe mapping first because this will
15469 * disable the crtc (and hence change the state) if it is wrong. Note
15470 * that gen4+ has a fixed plane -> pipe mapping. */
15471 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15474 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15475 crtc->base.base.id);
15477 /* Pipe has the wrong plane attached and the plane is active.
15478 * Temporarily change the plane mapping and disable everything
15480 plane = crtc->plane;
15481 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15482 crtc->plane = !plane;
15483 intel_crtc_disable_noatomic(&crtc->base);
15484 crtc->plane = plane;
15487 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15488 crtc->pipe == PIPE_A && !crtc->active) {
15489 /* BIOS forgot to enable pipe A, this mostly happens after
15490 * resume. Force-enable the pipe to fix this, the update_dpms
15491 * call below we restore the pipe to the right state, but leave
15492 * the required bits on. */
15493 intel_enable_pipe_a(dev);
15496 /* Adjust the state of the output pipe according to whether we
15497 * have active connectors/encoders. */
15498 if (crtc->active && !intel_crtc_has_encoders(crtc))
15499 intel_crtc_disable_noatomic(&crtc->base);
15501 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15503 * We start out with underrun reporting disabled to avoid races.
15504 * For correct bookkeeping mark this on active crtcs.
15506 * Also on gmch platforms we dont have any hardware bits to
15507 * disable the underrun reporting. Which means we need to start
15508 * out with underrun reporting disabled also on inactive pipes,
15509 * since otherwise we'll complain about the garbage we read when
15510 * e.g. coming up after runtime pm.
15512 * No protection against concurrent access is required - at
15513 * worst a fifo underrun happens which also sets this to false.
15515 crtc->cpu_fifo_underrun_disabled = true;
15516 crtc->pch_fifo_underrun_disabled = true;
15520 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15522 struct intel_connector *connector;
15523 struct drm_device *dev = encoder->base.dev;
15525 /* We need to check both for a crtc link (meaning that the
15526 * encoder is active and trying to read from a pipe) and the
15527 * pipe itself being active. */
15528 bool has_active_crtc = encoder->base.crtc &&
15529 to_intel_crtc(encoder->base.crtc)->active;
15531 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15532 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15533 encoder->base.base.id,
15534 encoder->base.name);
15536 /* Connector is active, but has no active pipe. This is
15537 * fallout from our resume register restoring. Disable
15538 * the encoder manually again. */
15539 if (encoder->base.crtc) {
15540 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15541 encoder->base.base.id,
15542 encoder->base.name);
15543 encoder->disable(encoder);
15544 if (encoder->post_disable)
15545 encoder->post_disable(encoder);
15547 encoder->base.crtc = NULL;
15549 /* Inconsistent output/port/pipe state happens presumably due to
15550 * a bug in one of the get_hw_state functions. Or someplace else
15551 * in our code, like the register restore mess on resume. Clamp
15552 * things to off as a safer default. */
15553 for_each_intel_connector(dev, connector) {
15554 if (connector->encoder != encoder)
15556 connector->base.dpms = DRM_MODE_DPMS_OFF;
15557 connector->base.encoder = NULL;
15560 /* Enabled encoders without active connectors will be fixed in
15561 * the crtc fixup. */
15564 void i915_redisable_vga_power_on(struct drm_device *dev)
15566 struct drm_i915_private *dev_priv = dev->dev_private;
15567 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15569 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15570 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15571 i915_disable_vga(dev);
15575 void i915_redisable_vga(struct drm_device *dev)
15577 struct drm_i915_private *dev_priv = dev->dev_private;
15579 /* This function can be called both from intel_modeset_setup_hw_state or
15580 * at a very early point in our resume sequence, where the power well
15581 * structures are not yet restored. Since this function is at a very
15582 * paranoid "someone might have enabled VGA while we were not looking"
15583 * level, just check if the power well is enabled instead of trying to
15584 * follow the "don't touch the power well if we don't need it" policy
15585 * the rest of the driver uses. */
15586 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15589 i915_redisable_vga_power_on(dev);
15591 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15594 static bool primary_get_hw_state(struct intel_plane *plane)
15596 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15598 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15601 /* FIXME read out full plane state for all planes */
15602 static void readout_plane_state(struct intel_crtc *crtc)
15604 struct drm_plane *primary = crtc->base.primary;
15605 struct intel_plane_state *plane_state =
15606 to_intel_plane_state(primary->state);
15608 plane_state->visible = crtc->active &&
15609 primary_get_hw_state(to_intel_plane(primary));
15611 if (plane_state->visible)
15612 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15615 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15617 struct drm_i915_private *dev_priv = dev->dev_private;
15619 struct intel_crtc *crtc;
15620 struct intel_encoder *encoder;
15621 struct intel_connector *connector;
15624 dev_priv->active_crtcs = 0;
15626 for_each_intel_crtc(dev, crtc) {
15627 struct intel_crtc_state *crtc_state = crtc->config;
15630 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15631 memset(crtc_state, 0, sizeof(*crtc_state));
15632 crtc_state->base.crtc = &crtc->base;
15634 crtc_state->base.active = crtc_state->base.enable =
15635 dev_priv->display.get_pipe_config(crtc, crtc_state);
15637 crtc->base.enabled = crtc_state->base.enable;
15638 crtc->active = crtc_state->base.active;
15640 if (crtc_state->base.active) {
15641 dev_priv->active_crtcs |= 1 << crtc->pipe;
15643 if (IS_BROADWELL(dev_priv)) {
15644 pixclk = ilk_pipe_pixel_rate(crtc_state);
15646 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15647 if (crtc_state->ips_enabled)
15648 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15649 } else if (IS_VALLEYVIEW(dev_priv) ||
15650 IS_CHERRYVIEW(dev_priv) ||
15651 IS_BROXTON(dev_priv))
15652 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15654 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15657 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15659 readout_plane_state(crtc);
15661 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15662 crtc->base.base.id,
15663 crtc->active ? "enabled" : "disabled");
15666 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15667 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15669 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15670 &pll->config.hw_state);
15671 pll->config.crtc_mask = 0;
15672 for_each_intel_crtc(dev, crtc) {
15673 if (crtc->active && crtc->config->shared_dpll == pll)
15674 pll->config.crtc_mask |= 1 << crtc->pipe;
15676 pll->active_mask = pll->config.crtc_mask;
15678 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15679 pll->name, pll->config.crtc_mask, pll->on);
15682 for_each_intel_encoder(dev, encoder) {
15685 if (encoder->get_hw_state(encoder, &pipe)) {
15686 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15687 encoder->base.crtc = &crtc->base;
15688 encoder->get_config(encoder, crtc->config);
15690 encoder->base.crtc = NULL;
15693 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15694 encoder->base.base.id,
15695 encoder->base.name,
15696 encoder->base.crtc ? "enabled" : "disabled",
15700 for_each_intel_connector(dev, connector) {
15701 if (connector->get_hw_state(connector)) {
15702 connector->base.dpms = DRM_MODE_DPMS_ON;
15704 encoder = connector->encoder;
15705 connector->base.encoder = &encoder->base;
15707 if (encoder->base.crtc &&
15708 encoder->base.crtc->state->active) {
15710 * This has to be done during hardware readout
15711 * because anything calling .crtc_disable may
15712 * rely on the connector_mask being accurate.
15714 encoder->base.crtc->state->connector_mask |=
15715 1 << drm_connector_index(&connector->base);
15716 encoder->base.crtc->state->encoder_mask |=
15717 1 << drm_encoder_index(&encoder->base);
15721 connector->base.dpms = DRM_MODE_DPMS_OFF;
15722 connector->base.encoder = NULL;
15724 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15725 connector->base.base.id,
15726 connector->base.name,
15727 connector->base.encoder ? "enabled" : "disabled");
15730 for_each_intel_crtc(dev, crtc) {
15731 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15733 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15734 if (crtc->base.state->active) {
15735 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15736 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15737 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15740 * The initial mode needs to be set in order to keep
15741 * the atomic core happy. It wants a valid mode if the
15742 * crtc's enabled, so we do the above call.
15744 * At this point some state updated by the connectors
15745 * in their ->detect() callback has not run yet, so
15746 * no recalculation can be done yet.
15748 * Even if we could do a recalculation and modeset
15749 * right now it would cause a double modeset if
15750 * fbdev or userspace chooses a different initial mode.
15752 * If that happens, someone indicated they wanted a
15753 * mode change, which means it's safe to do a full
15756 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15758 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15759 update_scanline_offset(crtc);
15762 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15766 /* Scan out the current hw modeset state,
15767 * and sanitizes it to the current state
15770 intel_modeset_setup_hw_state(struct drm_device *dev)
15772 struct drm_i915_private *dev_priv = dev->dev_private;
15774 struct intel_crtc *crtc;
15775 struct intel_encoder *encoder;
15778 intel_modeset_readout_hw_state(dev);
15780 /* HW state is read out, now we need to sanitize this mess. */
15781 for_each_intel_encoder(dev, encoder) {
15782 intel_sanitize_encoder(encoder);
15785 for_each_pipe(dev_priv, pipe) {
15786 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15787 intel_sanitize_crtc(crtc);
15788 intel_dump_pipe_config(crtc, crtc->config,
15789 "[setup_hw_state]");
15792 intel_modeset_update_connector_atomic_state(dev);
15794 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15795 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15797 if (!pll->on || pll->active_mask)
15800 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15802 pll->funcs.disable(dev_priv, pll);
15806 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15807 vlv_wm_get_hw_state(dev);
15808 else if (IS_GEN9(dev))
15809 skl_wm_get_hw_state(dev);
15810 else if (HAS_PCH_SPLIT(dev))
15811 ilk_wm_get_hw_state(dev);
15813 for_each_intel_crtc(dev, crtc) {
15814 unsigned long put_domains;
15816 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15817 if (WARN_ON(put_domains))
15818 modeset_put_power_domains(dev_priv, put_domains);
15820 intel_display_set_init_power(dev_priv, false);
15822 intel_fbc_init_pipe_state(dev_priv);
15825 void intel_display_resume(struct drm_device *dev)
15827 struct drm_i915_private *dev_priv = to_i915(dev);
15828 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15829 struct drm_modeset_acquire_ctx ctx;
15831 bool setup = false;
15833 dev_priv->modeset_restore_state = NULL;
15836 * This is a cludge because with real atomic modeset mode_config.mutex
15837 * won't be taken. Unfortunately some probed state like
15838 * audio_codec_enable is still protected by mode_config.mutex, so lock
15841 mutex_lock(&dev->mode_config.mutex);
15842 drm_modeset_acquire_init(&ctx, 0);
15845 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15847 if (ret == 0 && !setup) {
15850 intel_modeset_setup_hw_state(dev);
15851 i915_redisable_vga(dev);
15854 if (ret == 0 && state) {
15855 struct drm_crtc_state *crtc_state;
15856 struct drm_crtc *crtc;
15859 state->acquire_ctx = &ctx;
15861 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15863 * Force recalculation even if we restore
15864 * current state. With fast modeset this may not result
15865 * in a modeset when the state is compatible.
15867 crtc_state->mode_changed = true;
15870 ret = drm_atomic_commit(state);
15873 if (ret == -EDEADLK) {
15874 drm_modeset_backoff(&ctx);
15878 drm_modeset_drop_locks(&ctx);
15879 drm_modeset_acquire_fini(&ctx);
15880 mutex_unlock(&dev->mode_config.mutex);
15883 DRM_ERROR("Restoring old state failed with %i\n", ret);
15884 drm_atomic_state_free(state);
15888 void intel_modeset_gem_init(struct drm_device *dev)
15890 struct drm_crtc *c;
15891 struct drm_i915_gem_object *obj;
15894 intel_init_gt_powersave(dev);
15896 intel_modeset_init_hw(dev);
15898 intel_setup_overlay(dev);
15901 * Make sure any fbs we allocated at startup are properly
15902 * pinned & fenced. When we do the allocation it's too early
15905 for_each_crtc(dev, c) {
15906 obj = intel_fb_obj(c->primary->fb);
15910 mutex_lock(&dev->struct_mutex);
15911 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15912 c->primary->state->rotation);
15913 mutex_unlock(&dev->struct_mutex);
15915 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15916 to_intel_crtc(c)->pipe);
15917 drm_framebuffer_unreference(c->primary->fb);
15918 c->primary->fb = NULL;
15919 c->primary->crtc = c->primary->state->crtc = NULL;
15920 update_state_fb(c->primary);
15921 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15925 intel_backlight_register(dev);
15928 void intel_connector_unregister(struct intel_connector *intel_connector)
15930 struct drm_connector *connector = &intel_connector->base;
15932 intel_panel_destroy_backlight(connector);
15933 drm_connector_unregister(connector);
15936 void intel_modeset_cleanup(struct drm_device *dev)
15938 struct drm_i915_private *dev_priv = dev->dev_private;
15939 struct intel_connector *connector;
15941 intel_disable_gt_powersave(dev);
15943 intel_backlight_unregister(dev);
15946 * Interrupts and polling as the first thing to avoid creating havoc.
15947 * Too much stuff here (turning of connectors, ...) would
15948 * experience fancy races otherwise.
15950 intel_irq_uninstall(dev_priv);
15953 * Due to the hpd irq storm handling the hotplug work can re-arm the
15954 * poll handlers. Hence disable polling after hpd handling is shut down.
15956 drm_kms_helper_poll_fini(dev);
15958 intel_unregister_dsm_handler();
15960 intel_fbc_global_disable(dev_priv);
15962 /* flush any delayed tasks or pending work */
15963 flush_scheduled_work();
15965 /* destroy the backlight and sysfs files before encoders/connectors */
15966 for_each_intel_connector(dev, connector)
15967 connector->unregister(connector);
15969 drm_mode_config_cleanup(dev);
15971 intel_cleanup_overlay(dev);
15973 intel_cleanup_gt_powersave(dev);
15975 intel_teardown_gmbus(dev);
15979 * Return which encoder is currently attached for connector.
15981 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15983 return &intel_attached_encoder(connector)->base;
15986 void intel_connector_attach_encoder(struct intel_connector *connector,
15987 struct intel_encoder *encoder)
15989 connector->encoder = encoder;
15990 drm_mode_connector_attach_encoder(&connector->base,
15995 * set vga decode state - true == enable VGA decode
15997 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15999 struct drm_i915_private *dev_priv = dev->dev_private;
16000 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16003 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16004 DRM_ERROR("failed to read control word\n");
16008 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16012 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16014 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16016 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16017 DRM_ERROR("failed to write control word\n");
16024 struct intel_display_error_state {
16026 u32 power_well_driver;
16028 int num_transcoders;
16030 struct intel_cursor_error_state {
16035 } cursor[I915_MAX_PIPES];
16037 struct intel_pipe_error_state {
16038 bool power_domain_on;
16041 } pipe[I915_MAX_PIPES];
16043 struct intel_plane_error_state {
16051 } plane[I915_MAX_PIPES];
16053 struct intel_transcoder_error_state {
16054 bool power_domain_on;
16055 enum transcoder cpu_transcoder;
16068 struct intel_display_error_state *
16069 intel_display_capture_error_state(struct drm_device *dev)
16071 struct drm_i915_private *dev_priv = dev->dev_private;
16072 struct intel_display_error_state *error;
16073 int transcoders[] = {
16081 if (INTEL_INFO(dev)->num_pipes == 0)
16084 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16088 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16089 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16091 for_each_pipe(dev_priv, i) {
16092 error->pipe[i].power_domain_on =
16093 __intel_display_power_is_enabled(dev_priv,
16094 POWER_DOMAIN_PIPE(i));
16095 if (!error->pipe[i].power_domain_on)
16098 error->cursor[i].control = I915_READ(CURCNTR(i));
16099 error->cursor[i].position = I915_READ(CURPOS(i));
16100 error->cursor[i].base = I915_READ(CURBASE(i));
16102 error->plane[i].control = I915_READ(DSPCNTR(i));
16103 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16104 if (INTEL_INFO(dev)->gen <= 3) {
16105 error->plane[i].size = I915_READ(DSPSIZE(i));
16106 error->plane[i].pos = I915_READ(DSPPOS(i));
16108 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16109 error->plane[i].addr = I915_READ(DSPADDR(i));
16110 if (INTEL_INFO(dev)->gen >= 4) {
16111 error->plane[i].surface = I915_READ(DSPSURF(i));
16112 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16115 error->pipe[i].source = I915_READ(PIPESRC(i));
16117 if (HAS_GMCH_DISPLAY(dev))
16118 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16121 /* Note: this does not include DSI transcoders. */
16122 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16123 if (HAS_DDI(dev_priv->dev))
16124 error->num_transcoders++; /* Account for eDP. */
16126 for (i = 0; i < error->num_transcoders; i++) {
16127 enum transcoder cpu_transcoder = transcoders[i];
16129 error->transcoder[i].power_domain_on =
16130 __intel_display_power_is_enabled(dev_priv,
16131 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16132 if (!error->transcoder[i].power_domain_on)
16135 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16137 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16138 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16139 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16140 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16141 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16142 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16143 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16149 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16152 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16153 struct drm_device *dev,
16154 struct intel_display_error_state *error)
16156 struct drm_i915_private *dev_priv = dev->dev_private;
16162 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16163 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16164 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16165 error->power_well_driver);
16166 for_each_pipe(dev_priv, i) {
16167 err_printf(m, "Pipe [%d]:\n", i);
16168 err_printf(m, " Power: %s\n",
16169 onoff(error->pipe[i].power_domain_on));
16170 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16171 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16173 err_printf(m, "Plane [%d]:\n", i);
16174 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16175 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16176 if (INTEL_INFO(dev)->gen <= 3) {
16177 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16178 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16180 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16181 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16182 if (INTEL_INFO(dev)->gen >= 4) {
16183 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16184 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16187 err_printf(m, "Cursor [%d]:\n", i);
16188 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16189 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16190 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16193 for (i = 0; i < error->num_transcoders; i++) {
16194 err_printf(m, "CPU transcoder: %s\n",
16195 transcoder_name(error->transcoder[i].cpu_transcoder));
16196 err_printf(m, " Power: %s\n",
16197 onoff(error->transcoder[i].power_domain_on));
16198 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16199 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16200 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16201 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16202 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16203 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16204 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);