drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 static int
 173 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 174 {
 175         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 176 }
 177
 178 static int
 179 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 180 {
 181         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 182                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 183 }
 184
 185 static int
 186 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 187 {
 188         uint32_t clkcfg;
 189
 190         /* hrawclock is 1/4 the FSB frequency */
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100000;
 195         case CLKCFG_FSB_533:
 196                 return 133333;
 197         case CLKCFG_FSB_667:
 198                 return 166667;
 199         case CLKCFG_FSB_800:
 200                 return 200000;
 201         case CLKCFG_FSB_1067:
 202                 return 266667;
 203         case CLKCFG_FSB_1333:
 204                 return 333333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400000;
 209         default:
 210                 return 133333;
 211         }
 212 }
 213
 214 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (HAS_PCH_SPLIT(dev_priv))
 217                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 218         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 219                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 220         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 221                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 222         else
 223                 return; /* no rawclk on other platforms, or no need to know it */
 224
 225         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 226 }
 227
 228 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 229 {
 230         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 231                 return;
 232
 233         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 234                                                       CCK_CZ_CLOCK_CONTROL);
 235
 236         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 237 }
 238
 239 static inline u32 /* units of 100MHz */
 240 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 241                     const struct intel_crtc_state *pipe_config)
 242 {
 243         if (HAS_DDI(dev_priv))
 244                 return pipe_config->port_clock; /* SPLL */
 245         else if (IS_GEN5(dev_priv))
 246                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 247         else
 248                 return 270000;
 249 }
 250
 251 static const intel_limit_t intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const intel_limit_t intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const intel_limit_t intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const intel_limit_t intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const intel_limit_t intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const intel_limit_t intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const intel_limit_t intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const intel_limit_t intel_limits_pineview_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const intel_limit_t intel_limits_ironlake_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const intel_limit_t intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const intel_limit_t intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const intel_limit_t intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 static bool
 517 needs_modeset(struct drm_crtc_state *state)
 518 {
 519         return drm_atomic_crtc_needs_modeset(state);
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe is of the specified type
 524  */
 525 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 526 {
 527         struct drm_device *dev = crtc->base.dev;
 528         struct intel_encoder *encoder;
 529
 530         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 531                 if (encoder->type == type)
 532                         return true;
 533
 534         return false;
 535 }
 536
 537 /**
 538  * Returns whether any output on the specified pipe will have the specified
 539  * type after a staged modeset is complete, i.e., the same as
 540  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 541  * encoder->crtc.
 542  */
 543 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 544                                       int type)
 545 {
 546         struct drm_atomic_state *state = crtc_state->base.state;
 547         struct drm_connector *connector;
 548         struct drm_connector_state *connector_state;
 549         struct intel_encoder *encoder;
 550         int i, num_connectors = 0;
 551
 552         for_each_connector_in_state(state, connector, connector_state, i) {
 553                 if (connector_state->crtc != crtc_state->base.crtc)
 554                         continue;
 555
 556                 num_connectors++;
 557
 558                 encoder = to_intel_encoder(connector_state->best_encoder);
 559                 if (encoder->type == type)
 560                         return true;
 561         }
 562
 563         WARN_ON(num_connectors == 0);
 564
 565         return false;
 566 }
 567
 568 static const intel_limit_t *
 569 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 570 {
 571         struct drm_device *dev = crtc_state->base.crtc->dev;
 572         const intel_limit_t *limit;
 573
 574         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 575                 if (intel_is_dual_link_lvds(dev)) {
 576                         if (refclk == 100000)
 577                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 578                         else
 579                                 limit = &intel_limits_ironlake_dual_lvds;
 580                 } else {
 581                         if (refclk == 100000)
 582                                 limit = &intel_limits_ironlake_single_lvds_100m;
 583                         else
 584                                 limit = &intel_limits_ironlake_single_lvds;
 585                 }
 586         } else
 587                 limit = &intel_limits_ironlake_dac;
 588
 589         return limit;
 590 }
 591
 592 static const intel_limit_t *
 593 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 594 {
 595         struct drm_device *dev = crtc_state->base.crtc->dev;
 596         const intel_limit_t *limit;
 597
 598         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 599                 if (intel_is_dual_link_lvds(dev))
 600                         limit = &intel_limits_g4x_dual_channel_lvds;
 601                 else
 602                         limit = &intel_limits_g4x_single_channel_lvds;
 603         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 604                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 605                 limit = &intel_limits_g4x_hdmi;
 606         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 607                 limit = &intel_limits_g4x_sdvo;
 608         } else /* The option is for other outputs */
 609                 limit = &intel_limits_i9xx_sdvo;
 610
 611         return limit;
 612 }
 613
 614 static const intel_limit_t *
 615 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 616 {
 617         struct drm_device *dev = crtc_state->base.crtc->dev;
 618         const intel_limit_t *limit;
 619
 620         if (IS_BROXTON(dev))
 621                 limit = &intel_limits_bxt;
 622         else if (HAS_PCH_SPLIT(dev))
 623                 limit = intel_ironlake_limit(crtc_state, refclk);
 624         else if (IS_G4X(dev)) {
 625                 limit = intel_g4x_limit(crtc_state);
 626         } else if (IS_PINEVIEW(dev)) {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_pineview_lvds;
 629                 else
 630                         limit = &intel_limits_pineview_sdvo;
 631         } else if (IS_CHERRYVIEW(dev)) {
 632                 limit = &intel_limits_chv;
 633         } else if (IS_VALLEYVIEW(dev)) {
 634                 limit = &intel_limits_vlv;
 635         } else if (!IS_GEN2(dev)) {
 636                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 637                         limit = &intel_limits_i9xx_lvds;
 638                 else
 639                         limit = &intel_limits_i9xx_sdvo;
 640         } else {
 641                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 642                         limit = &intel_limits_i8xx_lvds;
 643                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 644                         limit = &intel_limits_i8xx_dvo;
 645                 else
 646                         limit = &intel_limits_i8xx_dac;
 647         }
 648         return limit;
 649 }
 650
 651 /*
 652  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 653  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 654  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 655  * The helpers' return value is the rate of the clock that is fed to the
 656  * display engine's pipe which can be the above fast dot clock rate or a
 657  * divided-down version of it.
 658  */
 659 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 660 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 661 {
 662         clock->m = clock->m2 + 2;
 663         clock->p = clock->p1 * clock->p2;
 664         if (WARN_ON(clock->n == 0 || clock->p == 0))
 665                 return 0;
 666         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 667         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 668
 669         return clock->dot;
 670 }
 671
 672 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 673 {
 674         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 675 }
 676
 677 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 678 {
 679         clock->m = i9xx_dpll_compute_m(clock);
 680         clock->p = clock->p1 * clock->p2;
 681         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 682                 return 0;
 683         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 684         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 685
 686         return clock->dot;
 687 }
 688
 689 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 690 {
 691         clock->m = clock->m1 * clock->m2;
 692         clock->p = clock->p1 * clock->p2;
 693         if (WARN_ON(clock->n == 0 || clock->p == 0))
 694                 return 0;
 695         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 696         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 697
 698         return clock->dot / 5;
 699 }
 700
 701 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 702 {
 703         clock->m = clock->m1 * clock->m2;
 704         clock->p = clock->p1 * clock->p2;
 705         if (WARN_ON(clock->n == 0 || clock->p == 0))
 706                 return 0;
 707         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 708                         clock->n << 22);
 709         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 710
 711         return clock->dot / 5;
 712 }
 713
 714 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 715 /**
 716  * Returns whether the given set of divisors are valid for a given refclk with
 717  * the given connectors.
 718  */
 719
 720 static bool intel_PLL_is_valid(struct drm_device *dev,
 721                                const intel_limit_t *limit,
 722                                const intel_clock_t *clock)
 723 {
 724         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 725                 INTELPllInvalid("n out of range\n");
 726         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 727                 INTELPllInvalid("p1 out of range\n");
 728         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 729                 INTELPllInvalid("m2 out of range\n");
 730         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 731                 INTELPllInvalid("m1 out of range\n");
 732
 733         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 734             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 735                 if (clock->m1 <= clock->m2)
 736                         INTELPllInvalid("m1 <= m2\n");
 737
 738         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 739                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 740                         INTELPllInvalid("p out of range\n");
 741                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 742                         INTELPllInvalid("m out of range\n");
 743         }
 744
 745         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 746                 INTELPllInvalid("vco out of range\n");
 747         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 748          * connector, etc., rather than just a single range.
 749          */
 750         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 751                 INTELPllInvalid("dot out of range\n");
 752
 753         return true;
 754 }
 755
 756 static int
 757 i9xx_select_p2_div(const intel_limit_t *limit,
 758                    const struct intel_crtc_state *crtc_state,
 759                    int target)
 760 {
 761         struct drm_device *dev = crtc_state->base.crtc->dev;
 762
 763         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 764                 /*
 765                  * For LVDS just rely on its current settings for dual-channel.
 766                  * We haven't figured out how to reliably set up different
 767                  * single/dual channel state, if we even can.
 768                  */
 769                 if (intel_is_dual_link_lvds(dev))
 770                         return limit->p2.p2_fast;
 771                 else
 772                         return limit->p2.p2_slow;
 773         } else {
 774                 if (target < limit->p2.dot_limit)
 775                         return limit->p2.p2_slow;
 776                 else
 777                         return limit->p2.p2_fast;
 778         }
 779 }
 780
 781 static bool
 782 i9xx_find_best_dpll(const intel_limit_t *limit,
 783                     struct intel_crtc_state *crtc_state,
 784                     int target, int refclk, intel_clock_t *match_clock,
 785                     intel_clock_t *best_clock)
 786 {
 787         struct drm_device *dev = crtc_state->base.crtc->dev;
 788         intel_clock_t clock;
 789         int err = target;
 790
 791         memset(best_clock, 0, sizeof(*best_clock));
 792
 793         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 794
 795         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 796              clock.m1++) {
 797                 for (clock.m2 = limit->m2.min;
 798                      clock.m2 <= limit->m2.max; clock.m2++) {
 799                         if (clock.m2 >= clock.m1)
 800                                 break;
 801                         for (clock.n = limit->n.min;
 802                              clock.n <= limit->n.max; clock.n++) {
 803                                 for (clock.p1 = limit->p1.min;
 804                                         clock.p1 <= limit->p1.max; clock.p1++) {
 805                                         int this_err;
 806
 807                                         i9xx_calc_dpll_params(refclk, &clock);
 808                                         if (!intel_PLL_is_valid(dev, limit,
 809                                                                 &clock))
 810                                                 continue;
 811                                         if (match_clock &&
 812                                             clock.p != match_clock->p)
 813                                                 continue;
 814
 815                                         this_err = abs(clock.dot - target);
 816                                         if (this_err < err) {
 817                                                 *best_clock = clock;
 818                                                 err = this_err;
 819                                         }
 820                                 }
 821                         }
 822                 }
 823         }
 824
 825         return (err != target);
 826 }
 827
 828 static bool
 829 pnv_find_best_dpll(const intel_limit_t *limit,
 830                    struct intel_crtc_state *crtc_state,
 831                    int target, int refclk, intel_clock_t *match_clock,
 832                    intel_clock_t *best_clock)
 833 {
 834         struct drm_device *dev = crtc_state->base.crtc->dev;
 835         intel_clock_t clock;
 836         int err = target;
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         for (clock.n = limit->n.min;
 847                              clock.n <= limit->n.max; clock.n++) {
 848                                 for (clock.p1 = limit->p1.min;
 849                                         clock.p1 <= limit->p1.max; clock.p1++) {
 850                                         int this_err;
 851
 852                                         pnv_calc_dpll_params(refclk, &clock);
 853                                         if (!intel_PLL_is_valid(dev, limit,
 854                                                                 &clock))
 855                                                 continue;
 856                                         if (match_clock &&
 857                                             clock.p != match_clock->p)
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 g4x_find_best_dpll(const intel_limit_t *limit,
 875                    struct intel_crtc_state *crtc_state,
 876                    int target, int refclk, intel_clock_t *match_clock,
 877                    intel_clock_t *best_clock)
 878 {
 879         struct drm_device *dev = crtc_state->base.crtc->dev;
 880         intel_clock_t clock;
 881         int max_n;
 882         bool found = false;
 883         /* approximately equals target * 0.00585 */
 884         int err_most = (target >> 8) + (target >> 9);
 885
 886         memset(best_clock, 0, sizeof(*best_clock));
 887
 888         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 889
 890         max_n = limit->n.max;
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 893                 /* based on hardware requirement, prefere larger m1,m2 */
 894                 for (clock.m1 = limit->m1.max;
 895                      clock.m1 >= limit->m1.min; clock.m1--) {
 896                         for (clock.m2 = limit->m2.max;
 897                              clock.m2 >= limit->m2.min; clock.m2--) {
 898                                 for (clock.p1 = limit->p1.max;
 899                                      clock.p1 >= limit->p1.min; clock.p1--) {
 900                                         int this_err;
 901
 902                                         i9xx_calc_dpll_params(refclk, &clock);
 903                                         if (!intel_PLL_is_valid(dev, limit,
 904                                                                 &clock))
 905                                                 continue;
 906
 907                                         this_err = abs(clock.dot - target);
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918         return found;
 919 }
 920
 921 /*
 922  * Check if the calculated PLL configuration is more optimal compared to the
 923  * best configuration and error found so far. Return the calculated error.
 924  */
 925 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 926                                const intel_clock_t *calculated_clock,
 927                                const intel_clock_t *best_clock,
 928                                unsigned int best_error_ppm,
 929                                unsigned int *error_ppm)
 930 {
 931         /*
 932          * For CHV ignore the error and consider only the P value.
 933          * Prefer a bigger P value based on HW requirements.
 934          */
 935         if (IS_CHERRYVIEW(dev)) {
 936                 *error_ppm = 0;
 937
 938                 return calculated_clock->p > best_clock->p;
 939         }
 940
 941         if (WARN_ON_ONCE(!target_freq))
 942                 return false;
 943
 944         *error_ppm = div_u64(1000000ULL *
 945                                 abs(target_freq - calculated_clock->dot),
 946                              target_freq);
 947         /*
 948          * Prefer a better P value over a better (smaller) error if the error
 949          * is small. Ensure this preference for future configurations too by
 950          * setting the error to 0.
 951          */
 952         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 953                 *error_ppm = 0;
 954
 955                 return true;
 956         }
 957
 958         return *error_ppm + 10 < best_error_ppm;
 959 }
 960
 961 static bool
 962 vlv_find_best_dpll(const intel_limit_t *limit,
 963                    struct intel_crtc_state *crtc_state,
 964                    int target, int refclk, intel_clock_t *match_clock,
 965                    intel_clock_t *best_clock)
 966 {
 967         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 968         struct drm_device *dev = crtc->base.dev;
 969         intel_clock_t clock;
 970         unsigned int bestppm = 1000000;
 971         /* min update 19.2 MHz */
 972         int max_n = min(limit->n.max, refclk / 19200);
 973         bool found = false;
 974
 975         target *= 5; /* fast clock */
 976
 977         memset(best_clock, 0, sizeof(*best_clock));
 978
 979         /* based on hardware requirement, prefer smaller n to precision */
 980         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 981                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 982                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 983                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 984                                 clock.p = clock.p1 * clock.p2;
 985                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 986                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 987                                         unsigned int ppm;
 988
 989                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 990                                                                      refclk * clock.m1);
 991
 992                                         vlv_calc_dpll_params(refclk, &clock);
 993
 994                                         if (!intel_PLL_is_valid(dev, limit,
 995                                                                 &clock))
 996                                                 continue;
 997
 998                                         if (!vlv_PLL_is_optimal(dev, target,
 999                                                                 &clock,
1000                                                                 best_clock,
1001                                                                 bestppm, &ppm))
1002                                                 continue;
1003
1004                                         *best_clock = clock;
1005                                         bestppm = ppm;
1006                                         found = true;
1007                                 }
1008                         }
1009                 }
1010         }
1011
1012         return found;
1013 }
1014
1015 static bool
1016 chv_find_best_dpll(const intel_limit_t *limit,
1017                    struct intel_crtc_state *crtc_state,
1018                    int target, int refclk, intel_clock_t *match_clock,
1019                    intel_clock_t *best_clock)
1020 {
1021         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1022         struct drm_device *dev = crtc->base.dev;
1023         unsigned int best_error_ppm;
1024         intel_clock_t clock;
1025         uint64_t m2;
1026         int found = false;
1027
1028         memset(best_clock, 0, sizeof(*best_clock));
1029         best_error_ppm = 1000000;
1030
1031         /*
1032          * Based on hardware doc, the n always set to 1, and m1 always
1033          * set to 2.  If requires to support 200Mhz refclk, we need to
1034          * revisit this because n may not 1 anymore.
1035          */
1036         clock.n = 1, clock.m1 = 2;
1037         target *= 5;    /* fast clock */
1038
1039         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1040                 for (clock.p2 = limit->p2.p2_fast;
1041                                 clock.p2 >= limit->p2.p2_slow;
1042                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1043                         unsigned int error_ppm;
1044
1045                         clock.p = clock.p1 * clock.p2;
1046
1047                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1048                                         clock.n) << 22, refclk * clock.m1);
1049
1050                         if (m2 > INT_MAX/clock.m1)
1051                                 continue;
1052
1053                         clock.m2 = m2;
1054
1055                         chv_calc_dpll_params(refclk, &clock);
1056
1057                         if (!intel_PLL_is_valid(dev, limit, &clock))
1058                                 continue;
1059
1060                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1061                                                 best_error_ppm, &error_ppm))
1062                                 continue;
1063
1064                         *best_clock = clock;
1065                         best_error_ppm = error_ppm;
1066                         found = true;
1067                 }
1068         }
1069
1070         return found;
1071 }
1072
1073 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1074                         intel_clock_t *best_clock)
1075 {
1076         int refclk = i9xx_get_refclk(crtc_state, 0);
1077
1078         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1079                                   target_clock, refclk, NULL, best_clock);
1080 }
1081
1082 bool intel_crtc_active(struct drm_crtc *crtc)
1083 {
1084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1085
1086         /* Be paranoid as we can arrive here with only partial
1087          * state retrieved from the hardware during setup.
1088          *
1089          * We can ditch the adjusted_mode.crtc_clock check as soon
1090          * as Haswell has gained clock readout/fastboot support.
1091          *
1092          * We can ditch the crtc->primary->fb check as soon as we can
1093          * properly reconstruct framebuffers.
1094          *
1095          * FIXME: The intel_crtc->active here should be switched to
1096          * crtc->state->active once we have proper CRTC states wired up
1097          * for atomic.
1098          */
1099         return intel_crtc->active && crtc->primary->state->fb &&
1100                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1101 }
1102
1103 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1104                                              enum pipe pipe)
1105 {
1106         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1108
1109         return intel_crtc->config->cpu_transcoder;
1110 }
1111
1112 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         i915_reg_t reg = PIPEDSL(pipe);
1116         u32 line1, line2;
1117         u32 line_mask;
1118
1119         if (IS_GEN2(dev))
1120                 line_mask = DSL_LINEMASK_GEN2;
1121         else
1122                 line_mask = DSL_LINEMASK_GEN3;
1123
1124         line1 = I915_READ(reg) & line_mask;
1125         msleep(5);
1126         line2 = I915_READ(reg) & line_mask;
1127
1128         return line1 == line2;
1129 }
1130
1131 /*
1132  * intel_wait_for_pipe_off - wait for pipe to turn off
1133  * @crtc: crtc whose pipe to wait for
1134  *
1135  * After disabling a pipe, we can't wait for vblank in the usual way,
1136  * spinning on the vblank interrupt status bit, since we won't actually
1137  * see an interrupt when the pipe is disabled.
1138  *
1139  * On Gen4 and above:
1140  *   wait for the pipe register state bit to turn off
1141  *
1142  * Otherwise:
1143  *   wait for the display line value to settle (it usually
1144  *   ends up stopping at the start of the next frame).
1145  *
1146  */
1147 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1148 {
1149         struct drm_device *dev = crtc->base.dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1152         enum pipe pipe = crtc->pipe;
1153
1154         if (INTEL_INFO(dev)->gen >= 4) {
1155                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1156
1157                 /* Wait for the Pipe State to go off */
1158                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1159                              100))
1160                         WARN(1, "pipe_off wait timed out\n");
1161         } else {
1162                 /* Wait for the display line to settle */
1163                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1164                         WARN(1, "pipe_off wait timed out\n");
1165         }
1166 }
1167
1168 /* Only for pre-ILK configs */
1169 void assert_pll(struct drm_i915_private *dev_priv,
1170                 enum pipe pipe, bool state)
1171 {
1172         u32 val;
1173         bool cur_state;
1174
1175         val = I915_READ(DPLL(pipe));
1176         cur_state = !!(val & DPLL_VCO_ENABLE);
1177         I915_STATE_WARN(cur_state != state,
1178              "PLL state assertion failure (expected %s, current %s)\n",
1179                         onoff(state), onoff(cur_state));
1180 }
1181
1182 /* XXX: the dsi pll is shared between MIPI DSI ports */
1183 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1184 {
1185         u32 val;
1186         bool cur_state;
1187
1188         mutex_lock(&dev_priv->sb_lock);
1189         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1190         mutex_unlock(&dev_priv->sb_lock);
1191
1192         cur_state = val & DSI_PLL_VCO_EN;
1193         I915_STATE_WARN(cur_state != state,
1194              "DSI PLL state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1198 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1199
1200 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1201                           enum pipe pipe, bool state)
1202 {
1203         bool cur_state;
1204         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205                                                                       pipe);
1206
1207         if (HAS_DDI(dev_priv->dev)) {
1208                 /* DDI does not have a specific FDI_TX register */
1209                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1210                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1211         } else {
1212                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1213                 cur_state = !!(val & FDI_TX_ENABLE);
1214         }
1215         I915_STATE_WARN(cur_state != state,
1216              "FDI TX state assertion failure (expected %s, current %s)\n",
1217                         onoff(state), onoff(cur_state));
1218 }
1219 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1220 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1221
1222 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1223                           enum pipe pipe, bool state)
1224 {
1225         u32 val;
1226         bool cur_state;
1227
1228         val = I915_READ(FDI_RX_CTL(pipe));
1229         cur_state = !!(val & FDI_RX_ENABLE);
1230         I915_STATE_WARN(cur_state != state,
1231              "FDI RX state assertion failure (expected %s, current %s)\n",
1232                         onoff(state), onoff(cur_state));
1233 }
1234 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1235 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1236
1237 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1238                                       enum pipe pipe)
1239 {
1240         u32 val;
1241
1242         /* ILK FDI PLL is always enabled */
1243         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1244                 return;
1245
1246         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1247         if (HAS_DDI(dev_priv->dev))
1248                 return;
1249
1250         val = I915_READ(FDI_TX_CTL(pipe));
1251         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1252 }
1253
1254 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1255                        enum pipe pipe, bool state)
1256 {
1257         u32 val;
1258         bool cur_state;
1259
1260         val = I915_READ(FDI_RX_CTL(pipe));
1261         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1262         I915_STATE_WARN(cur_state != state,
1263              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1264                         onoff(state), onoff(cur_state));
1265 }
1266
1267 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1268                            enum pipe pipe)
1269 {
1270         struct drm_device *dev = dev_priv->dev;
1271         i915_reg_t pp_reg;
1272         u32 val;
1273         enum pipe panel_pipe = PIPE_A;
1274         bool locked = true;
1275
1276         if (WARN_ON(HAS_DDI(dev)))
1277                 return;
1278
1279         if (HAS_PCH_SPLIT(dev)) {
1280                 u32 port_sel;
1281
1282                 pp_reg = PCH_PP_CONTROL;
1283                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284
1285                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1286                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1287                         panel_pipe = PIPE_B;
1288                 /* XXX: else fix for eDP */
1289         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1290                 /* presumably write lock depends on pipe, not port select */
1291                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1292                 panel_pipe = pipe;
1293         } else {
1294                 pp_reg = PP_CONTROL;
1295                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1296                         panel_pipe = PIPE_B;
1297         }
1298
1299         val = I915_READ(pp_reg);
1300         if (!(val & PANEL_POWER_ON) ||
1301             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1302                 locked = false;
1303
1304         I915_STATE_WARN(panel_pipe == pipe && locked,
1305              "panel assertion failure, pipe %c regs locked\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static void assert_cursor(struct drm_i915_private *dev_priv,
1310                           enum pipe pipe, bool state)
1311 {
1312         struct drm_device *dev = dev_priv->dev;
1313         bool cur_state;
1314
1315         if (IS_845G(dev) || IS_I865G(dev))
1316                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1317         else
1318                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1319
1320         I915_STATE_WARN(cur_state != state,
1321              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1322                         pipe_name(pipe), onoff(state), onoff(cur_state));
1323 }
1324 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1325 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326
1327 void assert_pipe(struct drm_i915_private *dev_priv,
1328                  enum pipe pipe, bool state)
1329 {
1330         bool cur_state;
1331         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1332                                                                       pipe);
1333         enum intel_display_power_domain power_domain;
1334
1335         /* if we need the pipe quirk it must be always on */
1336         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338                 state = true;
1339
1340         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1341         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1342                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1343                 cur_state = !!(val & PIPECONF_ENABLE);
1344
1345                 intel_display_power_put(dev_priv, power_domain);
1346         } else {
1347                 cur_state = false;
1348         }
1349
1350         I915_STATE_WARN(cur_state != state,
1351              "pipe %c assertion failure (expected %s, current %s)\n",
1352                         pipe_name(pipe), onoff(state), onoff(cur_state));
1353 }
1354
1355 static void assert_plane(struct drm_i915_private *dev_priv,
1356                          enum plane plane, bool state)
1357 {
1358         u32 val;
1359         bool cur_state;
1360
1361         val = I915_READ(DSPCNTR(plane));
1362         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1363         I915_STATE_WARN(cur_state != state,
1364              "plane %c assertion failure (expected %s, current %s)\n",
1365                         plane_name(plane), onoff(state), onoff(cur_state));
1366 }
1367
1368 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1369 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1370
1371 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe)
1373 {
1374         struct drm_device *dev = dev_priv->dev;
1375         int i;
1376
1377         /* Primary planes are fixed to pipes on gen4+ */
1378         if (INTEL_INFO(dev)->gen >= 4) {
1379                 u32 val = I915_READ(DSPCNTR(pipe));
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 u32 val = I915_READ(DSPCNTR(i));
1389                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390                         DISPPLANE_SEL_PIPE_SHIFT;
1391                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393                      plane_name(i), pipe_name(pipe));
1394         }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398                                     enum pipe pipe)
1399 {
1400         struct drm_device *dev = dev_priv->dev;
1401         int sprite;
1402
1403         if (INTEL_INFO(dev)->gen >= 9) {
1404                 for_each_sprite(dev_priv, pipe, sprite) {
1405                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1406                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1407                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1408                              sprite, pipe_name(pipe));
1409                 }
1410         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1411                 for_each_sprite(dev_priv, pipe, sprite) {
1412                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1413                         I915_STATE_WARN(val & SP_ENABLE,
1414                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415                              sprite_name(pipe, sprite), pipe_name(pipe));
1416                 }
1417         } else if (INTEL_INFO(dev)->gen >= 7) {
1418                 u32 val = I915_READ(SPRCTL(pipe));
1419                 I915_STATE_WARN(val & SPRITE_ENABLE,
1420                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1421                      plane_name(pipe), pipe_name(pipe));
1422         } else if (INTEL_INFO(dev)->gen >= 5) {
1423                 u32 val = I915_READ(DVSCNTR(pipe));
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1437                                     enum pipe pipe)
1438 {
1439         u32 val;
1440         bool enabled;
1441
1442         val = I915_READ(PCH_TRANSCONF(pipe));
1443         enabled = !!(val & TRANS_ENABLE);
1444         I915_STATE_WARN(enabled,
1445              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1446              pipe_name(pipe));
1447 }
1448
1449 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1450                             enum pipe pipe, u32 port_sel, u32 val)
1451 {
1452         if ((val & DP_PORT_EN) == 0)
1453                 return false;
1454
1455         if (HAS_PCH_CPT(dev_priv->dev)) {
1456                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1457                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1458                         return false;
1459         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1460                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1461                         return false;
1462         } else {
1463                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1464                         return false;
1465         }
1466         return true;
1467 }
1468
1469 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1470                               enum pipe pipe, u32 val)
1471 {
1472         if ((val & SDVO_ENABLE) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1477                         return false;
1478         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1479                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1480                         return false;
1481         } else {
1482                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1483                         return false;
1484         }
1485         return true;
1486 }
1487
1488 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1489                               enum pipe pipe, u32 val)
1490 {
1491         if ((val & LVDS_PORT_EN) == 0)
1492                 return false;
1493
1494         if (HAS_PCH_CPT(dev_priv->dev)) {
1495                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & ADPA_DAC_ENABLE) == 0)
1508                 return false;
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511                         return false;
1512         } else {
1513                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1514                         return false;
1515         }
1516         return true;
1517 }
1518
1519 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1520                                    enum pipe pipe, i915_reg_t reg,
1521                                    u32 port_sel)
1522 {
1523         u32 val = I915_READ(reg);
1524         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1525              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1526              i915_mmio_reg_offset(reg), pipe_name(pipe));
1527
1528         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1529              && (val & DP_PIPEB_SELECT),
1530              "IBX PCH dp port still using transcoder B\n");
1531 }
1532
1533 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1534                                      enum pipe pipe, i915_reg_t reg)
1535 {
1536         u32 val = I915_READ(reg);
1537         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1538              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1539              i915_mmio_reg_offset(reg), pipe_name(pipe));
1540
1541         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1542              && (val & SDVO_PIPE_B_SELECT),
1543              "IBX PCH hdmi port still using transcoder B\n");
1544 }
1545
1546 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1547                                       enum pipe pipe)
1548 {
1549         u32 val;
1550
1551         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1552         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1553         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1554
1555         val = I915_READ(PCH_ADPA);
1556         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1557              "PCH VGA enabled on transcoder %c, should be disabled\n",
1558              pipe_name(pipe));
1559
1560         val = I915_READ(PCH_LVDS);
1561         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1562              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1563              pipe_name(pipe));
1564
1565         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1566         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1567         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1568 }
1569
1570 static void vlv_enable_pll(struct intel_crtc *crtc,
1571                            const struct intel_crtc_state *pipe_config)
1572 {
1573         struct drm_device *dev = crtc->base.dev;
1574         struct drm_i915_private *dev_priv = dev->dev_private;
1575         i915_reg_t reg = DPLL(crtc->pipe);
1576         u32 dpll = pipe_config->dpll_hw_state.dpll;
1577
1578         assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580         /* PLL is protected by panel, make sure we can write it */
1581         if (IS_MOBILE(dev_priv->dev))
1582                 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584         I915_WRITE(reg, dpll);
1585         POSTING_READ(reg);
1586         udelay(150);
1587
1588         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1589                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1590
1591         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1592         POSTING_READ(DPLL_MD(crtc->pipe));
1593
1594         /* We do this three times for luck */
1595         I915_WRITE(reg, dpll);
1596         POSTING_READ(reg);
1597         udelay(150); /* wait for warmup */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604 }
1605
1606 static void chv_enable_pll(struct intel_crtc *crtc,
1607                            const struct intel_crtc_state *pipe_config)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int pipe = crtc->pipe;
1612         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1613         u32 tmp;
1614
1615         assert_pipe_disabled(dev_priv, crtc->pipe);
1616
1617         mutex_lock(&dev_priv->sb_lock);
1618
1619         /* Enable back the 10bit clock to display controller */
1620         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1621         tmp |= DPIO_DCLKP_EN;
1622         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1623
1624         mutex_unlock(&dev_priv->sb_lock);
1625
1626         /*
1627          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1628          */
1629         udelay(1);
1630
1631         /* Enable PLL */
1632         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1633
1634         /* Check PLL is locked */
1635         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1636                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1637
1638         /* not sure when this should be written */
1639         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640         POSTING_READ(DPLL_MD(pipe));
1641 }
1642
1643 static int intel_num_dvo_pipes(struct drm_device *dev)
1644 {
1645         struct intel_crtc *crtc;
1646         int count = 0;
1647
1648         for_each_intel_crtc(dev, crtc)
1649                 count += crtc->base.state->active &&
1650                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1651
1652         return count;
1653 }
1654
1655 static void i9xx_enable_pll(struct intel_crtc *crtc)
1656 {
1657         struct drm_device *dev = crtc->base.dev;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659         i915_reg_t reg = DPLL(crtc->pipe);
1660         u32 dpll = crtc->config->dpll_hw_state.dpll;
1661
1662         assert_pipe_disabled(dev_priv, crtc->pipe);
1663
1664         /* No really, not for ILK+ */
1665         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1666
1667         /* PLL is protected by panel, make sure we can write it */
1668         if (IS_MOBILE(dev) && !IS_I830(dev))
1669                 assert_panel_unlocked(dev_priv, crtc->pipe);
1670
1671         /* Enable DVO 2x clock on both PLLs if necessary */
1672         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1673                 /*
1674                  * It appears to be important that we don't enable this
1675                  * for the current pipe before otherwise configuring the
1676                  * PLL. No idea how this should be handled if multiple
1677                  * DVO outputs are enabled simultaneosly.
1678                  */
1679                 dpll |= DPLL_DVO_2X_MODE;
1680                 I915_WRITE(DPLL(!crtc->pipe),
1681                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1682         }
1683
1684         /*
1685          * Apparently we need to have VGA mode enabled prior to changing
1686          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1687          * dividers, even though the register value does change.
1688          */
1689         I915_WRITE(reg, 0);
1690
1691         I915_WRITE(reg, dpll);
1692
1693         /* Wait for the clocks to stabilize. */
1694         POSTING_READ(reg);
1695         udelay(150);
1696
1697         if (INTEL_INFO(dev)->gen >= 4) {
1698                 I915_WRITE(DPLL_MD(crtc->pipe),
1699                            crtc->config->dpll_hw_state.dpll_md);
1700         } else {
1701                 /* The pixel multiplier can only be updated once the
1702                  * DPLL is enabled and the clocks are stable.
1703                  *
1704                  * So write it again.
1705                  */
1706                 I915_WRITE(reg, dpll);
1707         }
1708
1709         /* We do this three times for luck */
1710         I915_WRITE(reg, dpll);
1711         POSTING_READ(reg);
1712         udelay(150); /* wait for warmup */
1713         I915_WRITE(reg, dpll);
1714         POSTING_READ(reg);
1715         udelay(150); /* wait for warmup */
1716         I915_WRITE(reg, dpll);
1717         POSTING_READ(reg);
1718         udelay(150); /* wait for warmup */
1719 }
1720
1721 /**
1722  * i9xx_disable_pll - disable a PLL
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe PLL to disable
1725  *
1726  * Disable the PLL for @pipe, making sure the pipe is off first.
1727  *
1728  * Note!  This is for pre-ILK only.
1729  */
1730 static void i9xx_disable_pll(struct intel_crtc *crtc)
1731 {
1732         struct drm_device *dev = crtc->base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         enum pipe pipe = crtc->pipe;
1735
1736         /* Disable DVO 2x clock on both PLLs if necessary */
1737         if (IS_I830(dev) &&
1738             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1739             !intel_num_dvo_pipes(dev)) {
1740                 I915_WRITE(DPLL(PIPE_B),
1741                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1742                 I915_WRITE(DPLL(PIPE_A),
1743                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1744         }
1745
1746         /* Don't disable pipe or pipe PLLs if needed */
1747         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1748             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1749                 return;
1750
1751         /* Make sure the pipe isn't still relying on us */
1752         assert_pipe_disabled(dev_priv, pipe);
1753
1754         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1755         POSTING_READ(DPLL(pipe));
1756 }
1757
1758 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1759 {
1760         u32 val;
1761
1762         /* Make sure the pipe isn't still relying on us */
1763         assert_pipe_disabled(dev_priv, pipe);
1764
1765         /*
1766          * Leave integrated clock source and reference clock enabled for pipe B.
1767          * The latter is needed for VGA hotplug / manual detection.
1768          */
1769         val = DPLL_VGA_MODE_DIS;
1770         if (pipe == PIPE_B)
1771                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1772         I915_WRITE(DPLL(pipe), val);
1773         POSTING_READ(DPLL(pipe));
1774
1775 }
1776
1777 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1778 {
1779         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1780         u32 val;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         /* Set PLL en = 0 */
1786         val = DPLL_SSC_REF_CLK_CHV |
1787                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1788         if (pipe != PIPE_A)
1789                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1790         I915_WRITE(DPLL(pipe), val);
1791         POSTING_READ(DPLL(pipe));
1792
1793         mutex_lock(&dev_priv->sb_lock);
1794
1795         /* Disable 10bit clock to display controller */
1796         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1797         val &= ~DPIO_DCLKP_EN;
1798         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1799
1800         mutex_unlock(&dev_priv->sb_lock);
1801 }
1802
1803 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1804                          struct intel_digital_port *dport,
1805                          unsigned int expected_mask)
1806 {
1807         u32 port_mask;
1808         i915_reg_t dpll_reg;
1809
1810         switch (dport->port) {
1811         case PORT_B:
1812                 port_mask = DPLL_PORTB_READY_MASK;
1813                 dpll_reg = DPLL(0);
1814                 break;
1815         case PORT_C:
1816                 port_mask = DPLL_PORTC_READY_MASK;
1817                 dpll_reg = DPLL(0);
1818                 expected_mask <<= 4;
1819                 break;
1820         case PORT_D:
1821                 port_mask = DPLL_PORTD_READY_MASK;
1822                 dpll_reg = DPIO_PHY_STATUS;
1823                 break;
1824         default:
1825                 BUG();
1826         }
1827
1828         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1829                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1830                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1831 }
1832
1833 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834                                            enum pipe pipe)
1835 {
1836         struct drm_device *dev = dev_priv->dev;
1837         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839         i915_reg_t reg;
1840         uint32_t val, pipeconf_val;
1841
1842         /* PCH only available on ILK+ */
1843         BUG_ON(!HAS_PCH_SPLIT(dev));
1844
1845         /* Make sure PCH DPLL is enabled */
1846         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1847
1848         /* FDI must be feeding us bits for PCH ports */
1849         assert_fdi_tx_enabled(dev_priv, pipe);
1850         assert_fdi_rx_enabled(dev_priv, pipe);
1851
1852         if (HAS_PCH_CPT(dev)) {
1853                 /* Workaround: Set the timing override bit before enabling the
1854                  * pch transcoder. */
1855                 reg = TRANS_CHICKEN2(pipe);
1856                 val = I915_READ(reg);
1857                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858                 I915_WRITE(reg, val);
1859         }
1860
1861         reg = PCH_TRANSCONF(pipe);
1862         val = I915_READ(reg);
1863         pipeconf_val = I915_READ(PIPECONF(pipe));
1864
1865         if (HAS_PCH_IBX(dev_priv->dev)) {
1866                 /*
1867                  * Make the BPC in transcoder be consistent with
1868                  * that in pipeconf reg. For HDMI we must use 8bpc
1869                  * here for both 8bpc and 12bpc.
1870                  */
1871                 val &= ~PIPECONF_BPC_MASK;
1872                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1873                         val |= PIPECONF_8BPC;
1874                 else
1875                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1876         }
1877
1878         val &= ~TRANS_INTERLACE_MASK;
1879         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1880                 if (HAS_PCH_IBX(dev_priv->dev) &&
1881                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1882                         val |= TRANS_LEGACY_INTERLACED_ILK;
1883                 else
1884                         val |= TRANS_INTERLACED;
1885         else
1886                 val |= TRANS_PROGRESSIVE;
1887
1888         I915_WRITE(reg, val | TRANS_ENABLE);
1889         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1890                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1891 }
1892
1893 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1894                                       enum transcoder cpu_transcoder)
1895 {
1896         u32 val, pipeconf_val;
1897
1898         /* PCH only available on ILK+ */
1899         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1900
1901         /* FDI must be feeding us bits for PCH ports */
1902         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1903         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1904
1905         /* Workaround: set timing override bit. */
1906         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1907         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1908         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1909
1910         val = TRANS_ENABLE;
1911         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1912
1913         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1914             PIPECONF_INTERLACED_ILK)
1915                 val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(LPT_TRANSCONF, val);
1920         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("Failed to enable PCH transcoder\n");
1922 }
1923
1924 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                             enum pipe pipe)
1926 {
1927         struct drm_device *dev = dev_priv->dev;
1928         i915_reg_t reg;
1929         uint32_t val;
1930
1931         /* FDI relies on the transcoder */
1932         assert_fdi_tx_disabled(dev_priv, pipe);
1933         assert_fdi_rx_disabled(dev_priv, pipe);
1934
1935         /* Ports must be off as well */
1936         assert_pch_ports_disabled(dev_priv, pipe);
1937
1938         reg = PCH_TRANSCONF(pipe);
1939         val = I915_READ(reg);
1940         val &= ~TRANS_ENABLE;
1941         I915_WRITE(reg, val);
1942         /* wait for PCH transcoder off, transcoder state */
1943         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1944                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1945
1946         if (HAS_PCH_CPT(dev)) {
1947                 /* Workaround: Clear the timing override chicken bit again. */
1948                 reg = TRANS_CHICKEN2(pipe);
1949                 val = I915_READ(reg);
1950                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951                 I915_WRITE(reg, val);
1952         }
1953 }
1954
1955 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1956 {
1957         u32 val;
1958
1959         val = I915_READ(LPT_TRANSCONF);
1960         val &= ~TRANS_ENABLE;
1961         I915_WRITE(LPT_TRANSCONF, val);
1962         /* wait for PCH transcoder off, transcoder state */
1963         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1964                 DRM_ERROR("Failed to disable PCH transcoder\n");
1965
1966         /* Workaround: clear timing override bit. */
1967         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1968         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1969         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1970 }
1971
1972 /**
1973  * intel_enable_pipe - enable a pipe, asserting requirements
1974  * @crtc: crtc responsible for the pipe
1975  *
1976  * Enable @crtc's pipe, making sure that various hardware specific requirements
1977  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1978  */
1979 static void intel_enable_pipe(struct intel_crtc *crtc)
1980 {
1981         struct drm_device *dev = crtc->base.dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         enum pipe pipe = crtc->pipe;
1984         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1985         enum pipe pch_transcoder;
1986         i915_reg_t reg;
1987         u32 val;
1988
1989         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1990
1991         assert_planes_disabled(dev_priv, pipe);
1992         assert_cursor_disabled(dev_priv, pipe);
1993         assert_sprites_disabled(dev_priv, pipe);
1994
1995         if (HAS_PCH_LPT(dev_priv->dev))
1996                 pch_transcoder = TRANSCODER_A;
1997         else
1998                 pch_transcoder = pipe;
1999
2000         /*
2001          * A pipe without a PLL won't actually be able to drive bits from
2002          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2003          * need the check.
2004          */
2005         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2006                 if (crtc->config->has_dsi_encoder)
2007                         assert_dsi_pll_enabled(dev_priv);
2008                 else
2009                         assert_pll_enabled(dev_priv, pipe);
2010         else {
2011                 if (crtc->config->has_pch_encoder) {
2012                         /* if driving the PCH, we need FDI enabled */
2013                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2014                         assert_fdi_tx_pll_enabled(dev_priv,
2015                                                   (enum pipe) cpu_transcoder);
2016                 }
2017                 /* FIXME: assert CPU port conditions for SNB+ */
2018         }
2019
2020         reg = PIPECONF(cpu_transcoder);
2021         val = I915_READ(reg);
2022         if (val & PIPECONF_ENABLE) {
2023                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2024                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2025                 return;
2026         }
2027
2028         I915_WRITE(reg, val | PIPECONF_ENABLE);
2029         POSTING_READ(reg);
2030
2031         /*
2032          * Until the pipe starts DSL will read as 0, which would cause
2033          * an apparent vblank timestamp jump, which messes up also the
2034          * frame count when it's derived from the timestamps. So let's
2035          * wait for the pipe to start properly before we call
2036          * drm_crtc_vblank_on()
2037          */
2038         if (dev->max_vblank_count == 0 &&
2039             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2040                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2041 }
2042
2043 /**
2044  * intel_disable_pipe - disable a pipe, asserting requirements
2045  * @crtc: crtc whose pipes is to be disabled
2046  *
2047  * Disable the pipe of @crtc, making sure that various hardware
2048  * specific requirements are met, if applicable, e.g. plane
2049  * disabled, panel fitter off, etc.
2050  *
2051  * Will wait until the pipe has shut down before returning.
2052  */
2053 static void intel_disable_pipe(struct intel_crtc *crtc)
2054 {
2055         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2056         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2057         enum pipe pipe = crtc->pipe;
2058         i915_reg_t reg;
2059         u32 val;
2060
2061         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2062
2063         /*
2064          * Make sure planes won't keep trying to pump pixels to us,
2065          * or we might hang the display.
2066          */
2067         assert_planes_disabled(dev_priv, pipe);
2068         assert_cursor_disabled(dev_priv, pipe);
2069         assert_sprites_disabled(dev_priv, pipe);
2070
2071         reg = PIPECONF(cpu_transcoder);
2072         val = I915_READ(reg);
2073         if ((val & PIPECONF_ENABLE) == 0)
2074                 return;
2075
2076         /*
2077          * Double wide has implications for planes
2078          * so best keep it disabled when not needed.
2079          */
2080         if (crtc->config->double_wide)
2081                 val &= ~PIPECONF_DOUBLE_WIDE;
2082
2083         /* Don't disable pipe or pipe PLLs if needed */
2084         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2085             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2086                 val &= ~PIPECONF_ENABLE;
2087
2088         I915_WRITE(reg, val);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 intel_wait_for_pipe_off(crtc);
2091 }
2092
2093 static bool need_vtd_wa(struct drm_device *dev)
2094 {
2095 #ifdef CONFIG_INTEL_IOMMU
2096         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2097                 return true;
2098 #endif
2099         return false;
2100 }
2101
2102 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2103 {
2104         return IS_GEN2(dev_priv) ? 2048 : 4096;
2105 }
2106
2107 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2108                                            uint64_t fb_modifier, unsigned int cpp)
2109 {
2110         switch (fb_modifier) {
2111         case DRM_FORMAT_MOD_NONE:
2112                 return cpp;
2113         case I915_FORMAT_MOD_X_TILED:
2114                 if (IS_GEN2(dev_priv))
2115                         return 128;
2116                 else
2117                         return 512;
2118         case I915_FORMAT_MOD_Y_TILED:
2119                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2120                         return 128;
2121                 else
2122                         return 512;
2123         case I915_FORMAT_MOD_Yf_TILED:
2124                 switch (cpp) {
2125                 case 1:
2126                         return 64;
2127                 case 2:
2128                 case 4:
2129                         return 128;
2130                 case 8:
2131                 case 16:
2132                         return 256;
2133                 default:
2134                         MISSING_CASE(cpp);
2135                         return cpp;
2136                 }
2137                 break;
2138         default:
2139                 MISSING_CASE(fb_modifier);
2140                 return cpp;
2141         }
2142 }
2143
2144 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2145                                uint64_t fb_modifier, unsigned int cpp)
2146 {
2147         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2148                 return 1;
2149         else
2150                 return intel_tile_size(dev_priv) /
2151                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2152 }
2153
2154 /* Return the tile dimensions in pixel units */
2155 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2156                             unsigned int *tile_width,
2157                             unsigned int *tile_height,
2158                             uint64_t fb_modifier,
2159                             unsigned int cpp)
2160 {
2161         unsigned int tile_width_bytes =
2162                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2163
2164         *tile_width = tile_width_bytes / cpp;
2165         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2166 }
2167
2168 unsigned int
2169 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2170                       uint32_t pixel_format, uint64_t fb_modifier)
2171 {
2172         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2173         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2174
2175         return ALIGN(height, tile_height);
2176 }
2177
2178 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2179 {
2180         unsigned int size = 0;
2181         int i;
2182
2183         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2184                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2185
2186         return size;
2187 }
2188
2189 static void
2190 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2191                         const struct drm_framebuffer *fb,
2192                         unsigned int rotation)
2193 {
2194         if (intel_rotation_90_or_270(rotation)) {
2195                 *view = i915_ggtt_view_rotated;
2196                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2197         } else {
2198                 *view = i915_ggtt_view_normal;
2199         }
2200 }
2201
2202 static void
2203 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2204                    struct drm_framebuffer *fb)
2205 {
2206         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2207         unsigned int tile_size, tile_width, tile_height, cpp;
2208
2209         tile_size = intel_tile_size(dev_priv);
2210
2211         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2212         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2213                         fb->modifier[0], cpp);
2214
2215         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2216         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2217
2218         if (info->pixel_format == DRM_FORMAT_NV12) {
2219                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2220                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2221                                 fb->modifier[1], cpp);
2222
2223                 info->uv_offset = fb->offsets[1];
2224                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2225                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2226         }
2227 }
2228
2229 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2230 {
2231         if (INTEL_INFO(dev_priv)->gen >= 9)
2232                 return 256 * 1024;
2233         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2234                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2235                 return 128 * 1024;
2236         else if (INTEL_INFO(dev_priv)->gen >= 4)
2237                 return 4 * 1024;
2238         else
2239                 return 0;
2240 }
2241
2242 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2243                                          uint64_t fb_modifier)
2244 {
2245         switch (fb_modifier) {
2246         case DRM_FORMAT_MOD_NONE:
2247                 return intel_linear_alignment(dev_priv);
2248         case I915_FORMAT_MOD_X_TILED:
2249                 if (INTEL_INFO(dev_priv)->gen >= 9)
2250                         return 256 * 1024;
2251                 return 0;
2252         case I915_FORMAT_MOD_Y_TILED:
2253         case I915_FORMAT_MOD_Yf_TILED:
2254                 return 1 * 1024 * 1024;
2255         default:
2256                 MISSING_CASE(fb_modifier);
2257                 return 0;
2258         }
2259 }
2260
2261 int
2262 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2263                            unsigned int rotation)
2264 {
2265         struct drm_device *dev = fb->dev;
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2268         struct i915_ggtt_view view;
2269         u32 alignment;
2270         int ret;
2271
2272         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2273
2274         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2275
2276         intel_fill_fb_ggtt_view(&view, fb, rotation);
2277
2278         /* Note that the w/a also requires 64 PTE of padding following the
2279          * bo. We currently fill all unused PTE with the shadow page and so
2280          * we should always have valid PTE following the scanout preventing
2281          * the VT-d warning.
2282          */
2283         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2284                 alignment = 256 * 1024;
2285
2286         /*
2287          * Global gtt pte registers are special registers which actually forward
2288          * writes to a chunk of system memory. Which means that there is no risk
2289          * that the register values disappear as soon as we call
2290          * intel_runtime_pm_put(), so it is correct to wrap only the
2291          * pin/unpin/fence and not more.
2292          */
2293         intel_runtime_pm_get(dev_priv);
2294
2295         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2296                                                    &view);
2297         if (ret)
2298                 goto err_pm;
2299
2300         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2301          * fence, whereas 965+ only requires a fence if using
2302          * framebuffer compression.  For simplicity, we always install
2303          * a fence as the cost is not that onerous.
2304          */
2305         if (view.type == I915_GGTT_VIEW_NORMAL) {
2306                 ret = i915_gem_object_get_fence(obj);
2307                 if (ret == -EDEADLK) {
2308                         /*
2309                          * -EDEADLK means there are no free fences
2310                          * no pending flips.
2311                          *
2312                          * This is propagated to atomic, but it uses
2313                          * -EDEADLK to force a locking recovery, so
2314                          * change the returned error to -EBUSY.
2315                          */
2316                         ret = -EBUSY;
2317                         goto err_unpin;
2318                 } else if (ret)
2319                         goto err_unpin;
2320
2321                 i915_gem_object_pin_fence(obj);
2322         }
2323
2324         intel_runtime_pm_put(dev_priv);
2325         return 0;
2326
2327 err_unpin:
2328         i915_gem_object_unpin_from_display_plane(obj, &view);
2329 err_pm:
2330         intel_runtime_pm_put(dev_priv);
2331         return ret;
2332 }
2333
2334 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2335 {
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338
2339         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2340
2341         intel_fill_fb_ggtt_view(&view, fb, rotation);
2342
2343         if (view.type == I915_GGTT_VIEW_NORMAL)
2344                 i915_gem_object_unpin_fence(obj);
2345
2346         i915_gem_object_unpin_from_display_plane(obj, &view);
2347 }
2348
2349 /*
2350  * Adjust the tile offset by moving the difference into
2351  * the x/y offsets.
2352  *
2353  * Input tile dimensions and pitch must already be
2354  * rotated to match x and y, and in pixel units.
2355  */
2356 static u32 intel_adjust_tile_offset(int *x, int *y,
2357                                     unsigned int tile_width,
2358                                     unsigned int tile_height,
2359                                     unsigned int tile_size,
2360                                     unsigned int pitch_tiles,
2361                                     u32 old_offset,
2362                                     u32 new_offset)
2363 {
2364         unsigned int tiles;
2365
2366         WARN_ON(old_offset & (tile_size - 1));
2367         WARN_ON(new_offset & (tile_size - 1));
2368         WARN_ON(new_offset > old_offset);
2369
2370         tiles = (old_offset - new_offset) / tile_size;
2371
2372         *y += tiles / pitch_tiles * tile_height;
2373         *x += tiles % pitch_tiles * tile_width;
2374
2375         return new_offset;
2376 }
2377
2378 /*
2379  * Computes the linear offset to the base tile and adjusts
2380  * x, y. bytes per pixel is assumed to be a power-of-two.
2381  *
2382  * In the 90/270 rotated case, x and y are assumed
2383  * to be already rotated to match the rotated GTT view, and
2384  * pitch is the tile_height aligned framebuffer height.
2385  */
2386 u32 intel_compute_tile_offset(int *x, int *y,
2387                               const struct drm_framebuffer *fb, int plane,
2388                               unsigned int pitch,
2389                               unsigned int rotation)
2390 {
2391         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2392         uint64_t fb_modifier = fb->modifier[plane];
2393         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2394         u32 offset, offset_aligned, alignment;
2395
2396         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2397         if (alignment)
2398                 alignment--;
2399
2400         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2401                 unsigned int tile_size, tile_width, tile_height;
2402                 unsigned int tile_rows, tiles, pitch_tiles;
2403
2404                 tile_size = intel_tile_size(dev_priv);
2405                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2406                                 fb_modifier, cpp);
2407
2408                 if (intel_rotation_90_or_270(rotation)) {
2409                         pitch_tiles = pitch / tile_height;
2410                         swap(tile_width, tile_height);
2411                 } else {
2412                         pitch_tiles = pitch / (tile_width * cpp);
2413                 }
2414
2415                 tile_rows = *y / tile_height;
2416                 *y %= tile_height;
2417
2418                 tiles = *x / tile_width;
2419                 *x %= tile_width;
2420
2421                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2422                 offset_aligned = offset & ~alignment;
2423
2424                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2425                                          tile_size, pitch_tiles,
2426                                          offset, offset_aligned);
2427         } else {
2428                 offset = *y * pitch + *x * cpp;
2429                 offset_aligned = offset & ~alignment;
2430
2431                 *y = (offset & alignment) / pitch;
2432                 *x = ((offset & alignment) - *y * pitch) / cpp;
2433         }
2434
2435         return offset_aligned;
2436 }
2437
2438 static int i9xx_format_to_fourcc(int format)
2439 {
2440         switch (format) {
2441         case DISPPLANE_8BPP:
2442                 return DRM_FORMAT_C8;
2443         case DISPPLANE_BGRX555:
2444                 return DRM_FORMAT_XRGB1555;
2445         case DISPPLANE_BGRX565:
2446                 return DRM_FORMAT_RGB565;
2447         default:
2448         case DISPPLANE_BGRX888:
2449                 return DRM_FORMAT_XRGB8888;
2450         case DISPPLANE_RGBX888:
2451                 return DRM_FORMAT_XBGR8888;
2452         case DISPPLANE_BGRX101010:
2453                 return DRM_FORMAT_XRGB2101010;
2454         case DISPPLANE_RGBX101010:
2455                 return DRM_FORMAT_XBGR2101010;
2456         }
2457 }
2458
2459 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2460 {
2461         switch (format) {
2462         case PLANE_CTL_FORMAT_RGB_565:
2463                 return DRM_FORMAT_RGB565;
2464         default:
2465         case PLANE_CTL_FORMAT_XRGB_8888:
2466                 if (rgb_order) {
2467                         if (alpha)
2468                                 return DRM_FORMAT_ABGR8888;
2469                         else
2470                                 return DRM_FORMAT_XBGR8888;
2471                 } else {
2472                         if (alpha)
2473                                 return DRM_FORMAT_ARGB8888;
2474                         else
2475                                 return DRM_FORMAT_XRGB8888;
2476                 }
2477         case PLANE_CTL_FORMAT_XRGB_2101010:
2478                 if (rgb_order)
2479                         return DRM_FORMAT_XBGR2101010;
2480                 else
2481                         return DRM_FORMAT_XRGB2101010;
2482         }
2483 }
2484
2485 static bool
2486 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2487                               struct intel_initial_plane_config *plane_config)
2488 {
2489         struct drm_device *dev = crtc->base.dev;
2490         struct drm_i915_private *dev_priv = to_i915(dev);
2491         struct drm_i915_gem_object *obj = NULL;
2492         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2493         struct drm_framebuffer *fb = &plane_config->fb->base;
2494         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2495         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2496                                     PAGE_SIZE);
2497
2498         size_aligned -= base_aligned;
2499
2500         if (plane_config->size == 0)
2501                 return false;
2502
2503         /* If the FB is too big, just don't use it since fbdev is not very
2504          * important and we should probably use that space with FBC or other
2505          * features. */
2506         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2507                 return false;
2508
2509         mutex_lock(&dev->struct_mutex);
2510
2511         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2512                                                              base_aligned,
2513                                                              base_aligned,
2514                                                              size_aligned);
2515         if (!obj) {
2516                 mutex_unlock(&dev->struct_mutex);
2517                 return false;
2518         }
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2532                                    &mode_cmd, obj)) {
2533                 DRM_DEBUG_KMS("intel fb init failed\n");
2534                 goto out_unref_obj;
2535         }
2536
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2574         struct intel_plane *intel_plane = to_intel_plane(primary);
2575         struct intel_plane_state *intel_state =
2576                 to_intel_plane_state(plane_state);
2577         struct drm_framebuffer *fb;
2578
2579         if (!plane_config->fb)
2580                 return;
2581
2582         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2583                 fb = &plane_config->fb->base;
2584                 goto valid_fb;
2585         }
2586
2587         kfree(plane_config->fb);
2588
2589         /*
2590          * Failed to alloc the obj, check to see if we should share
2591          * an fb with another CRTC instead
2592          */
2593         for_each_crtc(dev, c) {
2594                 i = to_intel_crtc(c);
2595
2596                 if (c == &intel_crtc->base)
2597                         continue;
2598
2599                 if (!i->active)
2600                         continue;
2601
2602                 fb = c->primary->fb;
2603                 if (!fb)
2604                         continue;
2605
2606                 obj = intel_fb_obj(fb);
2607                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2608                         drm_framebuffer_reference(fb);
2609                         goto valid_fb;
2610                 }
2611         }
2612
2613         /*
2614          * We've failed to reconstruct the BIOS FB.  Current display state
2615          * indicates that the primary plane is visible, but has a NULL FB,
2616          * which will lead to problems later if we don't fix it up.  The
2617          * simplest solution is to just disable the primary plane now and
2618          * pretend the BIOS never had it enabled.
2619          */
2620         to_intel_plane_state(plane_state)->visible = false;
2621         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622         intel_pre_disable_primary(&intel_crtc->base);
2623         intel_plane->disable_plane(primary, &intel_crtc->base);
2624
2625         return;
2626
2627 valid_fb:
2628         plane_state->src_x = 0;
2629         plane_state->src_y = 0;
2630         plane_state->src_w = fb->width << 16;
2631         plane_state->src_h = fb->height << 16;
2632
2633         plane_state->crtc_x = 0;
2634         plane_state->crtc_y = 0;
2635         plane_state->crtc_w = fb->width;
2636         plane_state->crtc_h = fb->height;
2637
2638         intel_state->src.x1 = plane_state->src_x;
2639         intel_state->src.y1 = plane_state->src_y;
2640         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2641         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2642         intel_state->dst.x1 = plane_state->crtc_x;
2643         intel_state->dst.y1 = plane_state->crtc_y;
2644         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2645         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2646
2647         obj = intel_fb_obj(fb);
2648         if (obj->tiling_mode != I915_TILING_NONE)
2649                 dev_priv->preserve_bios_swizzle = true;
2650
2651         drm_framebuffer_reference(fb);
2652         primary->fb = primary->state->fb = fb;
2653         primary->crtc = primary->state->crtc = &intel_crtc->base;
2654         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_plane *primary,
2659                                       const struct intel_crtc_state *crtc_state,
2660                                       const struct intel_plane_state *plane_state)
2661 {
2662         struct drm_device *dev = primary->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2665         struct drm_framebuffer *fb = plane_state->base.fb;
2666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2667         int plane = intel_crtc->plane;
2668         u32 linear_offset;
2669         u32 dspcntr;
2670         i915_reg_t reg = DSPCNTR(plane);
2671         unsigned int rotation = plane_state->base.rotation;
2672         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2673         int x = plane_state->src.x1 >> 16;
2674         int y = plane_state->src.y1 >> 16;
2675
2676         dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678         dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680         if (INTEL_INFO(dev)->gen < 4) {
2681                 if (intel_crtc->pipe == PIPE_B)
2682                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684                 /* pipesrc and dspsize control the size that is scaled from,
2685                  * which should always be the user's requested size.
2686                  */
2687                 I915_WRITE(DSPSIZE(plane),
2688                            ((crtc_state->pipe_src_h - 1) << 16) |
2689                            (crtc_state->pipe_src_w - 1));
2690                 I915_WRITE(DSPPOS(plane), 0);
2691         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692                 I915_WRITE(PRIMSIZE(plane),
2693                            ((crtc_state->pipe_src_h - 1) << 16) |
2694                            (crtc_state->pipe_src_w - 1));
2695                 I915_WRITE(PRIMPOS(plane), 0);
2696                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697         }
2698
2699         switch (fb->pixel_format) {
2700         case DRM_FORMAT_C8:
2701                 dspcntr |= DISPPLANE_8BPP;
2702                 break;
2703         case DRM_FORMAT_XRGB1555:
2704                 dspcntr |= DISPPLANE_BGRX555;
2705                 break;
2706         case DRM_FORMAT_RGB565:
2707                 dspcntr |= DISPPLANE_BGRX565;
2708                 break;
2709         case DRM_FORMAT_XRGB8888:
2710                 dspcntr |= DISPPLANE_BGRX888;
2711                 break;
2712         case DRM_FORMAT_XBGR8888:
2713                 dspcntr |= DISPPLANE_RGBX888;
2714                 break;
2715         case DRM_FORMAT_XRGB2101010:
2716                 dspcntr |= DISPPLANE_BGRX101010;
2717                 break;
2718         case DRM_FORMAT_XBGR2101010:
2719                 dspcntr |= DISPPLANE_RGBX101010;
2720                 break;
2721         default:
2722                 BUG();
2723         }
2724
2725         if (INTEL_INFO(dev)->gen >= 4 &&
2726             obj->tiling_mode != I915_TILING_NONE)
2727                 dspcntr |= DISPPLANE_TILED;
2728
2729         if (IS_G4X(dev))
2730                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732         linear_offset = y * fb->pitches[0] + x * cpp;
2733
2734         if (INTEL_INFO(dev)->gen >= 4) {
2735                 intel_crtc->dspaddr_offset =
2736                         intel_compute_tile_offset(&x, &y, fb, 0,
2737                                                   fb->pitches[0], rotation);
2738                 linear_offset -= intel_crtc->dspaddr_offset;
2739         } else {
2740                 intel_crtc->dspaddr_offset = linear_offset;
2741         }
2742
2743         if (rotation == BIT(DRM_ROTATE_180)) {
2744                 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746                 x += (crtc_state->pipe_src_w - 1);
2747                 y += (crtc_state->pipe_src_h - 1);
2748
2749                 /* Finding the last pixel of the last line of the display
2750                 data and adding to linear_offset*/
2751                 linear_offset +=
2752                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2753                         (crtc_state->pipe_src_w - 1) * cpp;
2754         }
2755
2756         intel_crtc->adjusted_x = x;
2757         intel_crtc->adjusted_y = y;
2758
2759         I915_WRITE(reg, dspcntr);
2760
2761         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2762         if (INTEL_INFO(dev)->gen >= 4) {
2763                 I915_WRITE(DSPSURF(plane),
2764                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2766                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767         } else
2768                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769         POSTING_READ(reg);
2770 }
2771
2772 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2773                                        struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int plane = intel_crtc->plane;
2779
2780         I915_WRITE(DSPCNTR(plane), 0);
2781         if (INTEL_INFO(dev_priv)->gen >= 4)
2782                 I915_WRITE(DSPSURF(plane), 0);
2783         else
2784                 I915_WRITE(DSPADDR(plane), 0);
2785         POSTING_READ(DSPCNTR(plane));
2786 }
2787
2788 static void ironlake_update_primary_plane(struct drm_plane *primary,
2789                                           const struct intel_crtc_state *crtc_state,
2790                                           const struct intel_plane_state *plane_state)
2791 {
2792         struct drm_device *dev = primary->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2795         struct drm_framebuffer *fb = plane_state->base.fb;
2796         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2797         int plane = intel_crtc->plane;
2798         u32 linear_offset;
2799         u32 dspcntr;
2800         i915_reg_t reg = DSPCNTR(plane);
2801         unsigned int rotation = plane_state->base.rotation;
2802         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2803         int x = plane_state->src.x1 >> 16;
2804         int y = plane_state->src.y1 >> 16;
2805
2806         dspcntr = DISPPLANE_GAMMA_ENABLE;
2807         dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812         switch (fb->pixel_format) {
2813         case DRM_FORMAT_C8:
2814                 dspcntr |= DISPPLANE_8BPP;
2815                 break;
2816         case DRM_FORMAT_RGB565:
2817                 dspcntr |= DISPPLANE_BGRX565;
2818                 break;
2819         case DRM_FORMAT_XRGB8888:
2820                 dspcntr |= DISPPLANE_BGRX888;
2821                 break;
2822         case DRM_FORMAT_XBGR8888:
2823                 dspcntr |= DISPPLANE_RGBX888;
2824                 break;
2825         case DRM_FORMAT_XRGB2101010:
2826                 dspcntr |= DISPPLANE_BGRX101010;
2827                 break;
2828         case DRM_FORMAT_XBGR2101010:
2829                 dspcntr |= DISPPLANE_RGBX101010;
2830                 break;
2831         default:
2832                 BUG();
2833         }
2834
2835         if (obj->tiling_mode != I915_TILING_NONE)
2836                 dspcntr |= DISPPLANE_TILED;
2837
2838         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2839                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2840
2841         linear_offset = y * fb->pitches[0] + x * cpp;
2842         intel_crtc->dspaddr_offset =
2843                 intel_compute_tile_offset(&x, &y, fb, 0,
2844                                           fb->pitches[0], rotation);
2845         linear_offset -= intel_crtc->dspaddr_offset;
2846         if (rotation == BIT(DRM_ROTATE_180)) {
2847                 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850                         x += (crtc_state->pipe_src_w - 1);
2851                         y += (crtc_state->pipe_src_h - 1);
2852
2853                         /* Finding the last pixel of the last line of the display
2854                         data and adding to linear_offset*/
2855                         linear_offset +=
2856                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2857                                 (crtc_state->pipe_src_w - 1) * cpp;
2858                 }
2859         }
2860
2861         intel_crtc->adjusted_x = x;
2862         intel_crtc->adjusted_y = y;
2863
2864         I915_WRITE(reg, dspcntr);
2865
2866         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867         I915_WRITE(DSPSURF(plane),
2868                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871         } else {
2872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874         }
2875         POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2879                               uint64_t fb_modifier, uint32_t pixel_format)
2880 {
2881         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2882                 return 64;
2883         } else {
2884                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2885
2886                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2887         }
2888 }
2889
2890 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2891                            struct drm_i915_gem_object *obj,
2892                            unsigned int plane)
2893 {
2894         struct i915_ggtt_view view;
2895         struct i915_vma *vma;
2896         u64 offset;
2897
2898         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2899                                 intel_plane->base.state->rotation);
2900
2901         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2902         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2903                 view.type))
2904                 return -1;
2905
2906         offset = vma->node.start;
2907
2908         if (plane == 1) {
2909                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2910                           PAGE_SIZE;
2911         }
2912
2913         WARN_ON(upper_32_bits(offset));
2914
2915         return lower_32_bits(offset);
2916 }
2917
2918 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 {
2920         struct drm_device *dev = intel_crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922
2923         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2925         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2926 }
2927
2928 /*
2929  * This function detaches (aka. unbinds) unused scalers in hardware
2930  */
2931 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 {
2933         struct intel_crtc_scaler_state *scaler_state;
2934         int i;
2935
2936         scaler_state = &intel_crtc->config->scaler_state;
2937
2938         /* loop through and disable scalers that aren't in use */
2939         for (i = 0; i < intel_crtc->num_scalers; i++) {
2940                 if (!scaler_state->scalers[i].in_use)
2941                         skl_detach_scaler(intel_crtc, i);
2942         }
2943 }
2944
2945 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 {
2947         switch (pixel_format) {
2948         case DRM_FORMAT_C8:
2949                 return PLANE_CTL_FORMAT_INDEXED;
2950         case DRM_FORMAT_RGB565:
2951                 return PLANE_CTL_FORMAT_RGB_565;
2952         case DRM_FORMAT_XBGR8888:
2953                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2954         case DRM_FORMAT_XRGB8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888;
2956         /*
2957          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2958          * to be already pre-multiplied. We need to add a knob (or a different
2959          * DRM_FORMAT) for user-space to configure that.
2960          */
2961         case DRM_FORMAT_ABGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2963                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2964         case DRM_FORMAT_ARGB8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888 |
2966                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2967         case DRM_FORMAT_XRGB2101010:
2968                 return PLANE_CTL_FORMAT_XRGB_2101010;
2969         case DRM_FORMAT_XBGR2101010:
2970                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2971         case DRM_FORMAT_YUYV:
2972                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2973         case DRM_FORMAT_YVYU:
2974                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2975         case DRM_FORMAT_UYVY:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2977         case DRM_FORMAT_VYUY:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979         default:
2980                 MISSING_CASE(pixel_format);
2981         }
2982
2983         return 0;
2984 }
2985
2986 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 {
2988         switch (fb_modifier) {
2989         case DRM_FORMAT_MOD_NONE:
2990                 break;
2991         case I915_FORMAT_MOD_X_TILED:
2992                 return PLANE_CTL_TILED_X;
2993         case I915_FORMAT_MOD_Y_TILED:
2994                 return PLANE_CTL_TILED_Y;
2995         case I915_FORMAT_MOD_Yf_TILED:
2996                 return PLANE_CTL_TILED_YF;
2997         default:
2998                 MISSING_CASE(fb_modifier);
2999         }
3000
3001         return 0;
3002 }
3003
3004 u32 skl_plane_ctl_rotation(unsigned int rotation)
3005 {
3006         switch (rotation) {
3007         case BIT(DRM_ROTATE_0):
3008                 break;
3009         /*
3010          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3011          * while i915 HW rotation is clockwise, thats why this swapping.
3012          */
3013         case BIT(DRM_ROTATE_90):
3014                 return PLANE_CTL_ROTATE_270;
3015         case BIT(DRM_ROTATE_180):
3016                 return PLANE_CTL_ROTATE_180;
3017         case BIT(DRM_ROTATE_270):
3018                 return PLANE_CTL_ROTATE_90;
3019         default:
3020                 MISSING_CASE(rotation);
3021         }
3022
3023         return 0;
3024 }
3025
3026 static void skylake_update_primary_plane(struct drm_plane *plane,
3027                                          const struct intel_crtc_state *crtc_state,
3028                                          const struct intel_plane_state *plane_state)
3029 {
3030         struct drm_device *dev = plane->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3033         struct drm_framebuffer *fb = plane_state->base.fb;
3034         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3035         int pipe = intel_crtc->pipe;
3036         u32 plane_ctl, stride_div, stride;
3037         u32 tile_height, plane_offset, plane_size;
3038         unsigned int rotation = plane_state->base.rotation;
3039         int x_offset, y_offset;
3040         u32 surf_addr;
3041         int scaler_id = plane_state->scaler_id;
3042         int src_x = plane_state->src.x1 >> 16;
3043         int src_y = plane_state->src.y1 >> 16;
3044         int src_w = drm_rect_width(&plane_state->src) >> 16;
3045         int src_h = drm_rect_height(&plane_state->src) >> 16;
3046         int dst_x = plane_state->dst.x1;
3047         int dst_y = plane_state->dst.y1;
3048         int dst_w = drm_rect_width(&plane_state->dst);
3049         int dst_h = drm_rect_height(&plane_state->dst);
3050
3051         plane_ctl = PLANE_CTL_ENABLE |
3052                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3053                     PLANE_CTL_PIPE_CSC_ENABLE;
3054
3055         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3056         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3057         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3058         plane_ctl |= skl_plane_ctl_rotation(rotation);
3059
3060         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3061                                                fb->pixel_format);
3062         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3063
3064         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3065
3066         if (intel_rotation_90_or_270(rotation)) {
3067                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3068
3069                 /* stride = Surface height in tiles */
3070                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3071                 stride = DIV_ROUND_UP(fb->height, tile_height);
3072                 x_offset = stride * tile_height - src_y - src_h;
3073                 y_offset = src_x;
3074                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3075         } else {
3076                 stride = fb->pitches[0] / stride_div;
3077                 x_offset = src_x;
3078                 y_offset = src_y;
3079                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3080         }
3081         plane_offset = y_offset << 16 | x_offset;
3082
3083         intel_crtc->adjusted_x = x_offset;
3084         intel_crtc->adjusted_y = y_offset;
3085
3086         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3087         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3088         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3089         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3090
3091         if (scaler_id >= 0) {
3092                 uint32_t ps_ctrl = 0;
3093
3094                 WARN_ON(!dst_w || !dst_h);
3095                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3096                         crtc_state->scaler_state.scalers[scaler_id].mode;
3097                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3098                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3099                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3100                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3101                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3102         } else {
3103                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3104         }
3105
3106         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3107
3108         POSTING_READ(PLANE_SURF(pipe, 0));
3109 }
3110
3111 static void skylake_disable_primary_plane(struct drm_plane *primary,
3112                                           struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int pipe = to_intel_crtc(crtc)->pipe;
3117
3118         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3119         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3120         POSTING_READ(PLANE_SURF(pipe, 0));
3121 }
3122
3123 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3124 static int
3125 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3126                            int x, int y, enum mode_set_atomic state)
3127 {
3128         /* Support for kgdboc is disabled, this needs a major rework. */
3129         DRM_ERROR("legacy panic handler not supported any more.\n");
3130
3131         return -ENODEV;
3132 }
3133
3134 static void intel_complete_page_flips(struct drm_device *dev)
3135 {
3136         struct drm_crtc *crtc;
3137
3138         for_each_crtc(dev, crtc) {
3139                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3140                 enum plane plane = intel_crtc->plane;
3141
3142                 intel_prepare_page_flip(dev, plane);
3143                 intel_finish_page_flip_plane(dev, plane);
3144         }
3145 }
3146
3147 static void intel_update_primary_planes(struct drm_device *dev)
3148 {
3149         struct drm_crtc *crtc;
3150
3151         for_each_crtc(dev, crtc) {
3152                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3153                 struct intel_plane_state *plane_state;
3154
3155                 drm_modeset_lock_crtc(crtc, &plane->base);
3156                 plane_state = to_intel_plane_state(plane->base.state);
3157
3158                 if (plane_state->visible)
3159                         plane->update_plane(&plane->base,
3160                                             to_intel_crtc_state(crtc->state),
3161                                             plane_state);
3162
3163                 drm_modeset_unlock_crtc(crtc);
3164         }
3165 }
3166
3167 void intel_prepare_reset(struct drm_device *dev)
3168 {
3169         /* no reset support for gen2 */
3170         if (IS_GEN2(dev))
3171                 return;
3172
3173         /* reset doesn't touch the display */
3174         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3175                 return;
3176
3177         drm_modeset_lock_all(dev);
3178         /*
3179          * Disabling the crtcs gracefully seems nicer. Also the
3180          * g33 docs say we should at least disable all the planes.
3181          */
3182         intel_display_suspend(dev);
3183 }
3184
3185 void intel_finish_reset(struct drm_device *dev)
3186 {
3187         struct drm_i915_private *dev_priv = to_i915(dev);
3188
3189         /*
3190          * Flips in the rings will be nuked by the reset,
3191          * so complete all pending flips so that user space
3192          * will get its events and not get stuck.
3193          */
3194         intel_complete_page_flips(dev);
3195
3196         /* no reset support for gen2 */
3197         if (IS_GEN2(dev))
3198                 return;
3199
3200         /* reset doesn't touch the display */
3201         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3202                 /*
3203                  * Flips in the rings have been nuked by the reset,
3204                  * so update the base address of all primary
3205                  * planes to the the last fb to make sure we're
3206                  * showing the correct fb after a reset.
3207                  *
3208                  * FIXME: Atomic will make this obsolete since we won't schedule
3209                  * CS-based flips (which might get lost in gpu resets) any more.
3210                  */
3211                 intel_update_primary_planes(dev);
3212                 return;
3213         }
3214
3215         /*
3216          * The display has been reset as well,
3217          * so need a full re-initialization.
3218          */
3219         intel_runtime_pm_disable_interrupts(dev_priv);
3220         intel_runtime_pm_enable_interrupts(dev_priv);
3221
3222         intel_modeset_init_hw(dev);
3223
3224         spin_lock_irq(&dev_priv->irq_lock);
3225         if (dev_priv->display.hpd_irq_setup)
3226                 dev_priv->display.hpd_irq_setup(dev);
3227         spin_unlock_irq(&dev_priv->irq_lock);
3228
3229         intel_display_resume(dev);
3230
3231         intel_hpd_init(dev_priv);
3232
3233         drm_modeset_unlock_all(dev);
3234 }
3235
3236 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         bool pending;
3242
3243         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3244             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3245                 return false;
3246
3247         spin_lock_irq(&dev->event_lock);
3248         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3249         spin_unlock_irq(&dev->event_lock);
3250
3251         return pending;
3252 }
3253
3254 static void intel_update_pipe_config(struct intel_crtc *crtc,
3255                                      struct intel_crtc_state *old_crtc_state)
3256 {
3257         struct drm_device *dev = crtc->base.dev;
3258         struct drm_i915_private *dev_priv = dev->dev_private;
3259         struct intel_crtc_state *pipe_config =
3260                 to_intel_crtc_state(crtc->base.state);
3261
3262         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3263         crtc->base.mode = crtc->base.state->mode;
3264
3265         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3266                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3267                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3268
3269         if (HAS_DDI(dev))
3270                 intel_set_pipe_csc(&crtc->base);
3271
3272         /*
3273          * Update pipe size and adjust fitter if needed: the reason for this is
3274          * that in compute_mode_changes we check the native mode (not the pfit
3275          * mode) to see if we can flip rather than do a full mode set. In the
3276          * fastboot case, we'll flip, but if we don't update the pipesrc and
3277          * pfit state, we'll end up with a big fb scanned out into the wrong
3278          * sized surface.
3279          */
3280
3281         I915_WRITE(PIPESRC(crtc->pipe),
3282                    ((pipe_config->pipe_src_w - 1) << 16) |
3283                    (pipe_config->pipe_src_h - 1));
3284
3285         /* on skylake this is done by detaching scalers */
3286         if (INTEL_INFO(dev)->gen >= 9) {
3287                 skl_detach_scalers(crtc);
3288
3289                 if (pipe_config->pch_pfit.enabled)
3290                         skylake_pfit_enable(crtc);
3291         } else if (HAS_PCH_SPLIT(dev)) {
3292                 if (pipe_config->pch_pfit.enabled)
3293                         ironlake_pfit_enable(crtc);
3294                 else if (old_crtc_state->pch_pfit.enabled)
3295                         ironlake_pfit_disable(crtc, true);
3296         }
3297 }
3298
3299 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3300 {
3301         struct drm_device *dev = crtc->dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304         int pipe = intel_crtc->pipe;
3305         i915_reg_t reg;
3306         u32 temp;
3307
3308         /* enable normal train */
3309         reg = FDI_TX_CTL(pipe);
3310         temp = I915_READ(reg);
3311         if (IS_IVYBRIDGE(dev)) {
3312                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3313                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3314         } else {
3315                 temp &= ~FDI_LINK_TRAIN_NONE;
3316                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3317         }
3318         I915_WRITE(reg, temp);
3319
3320         reg = FDI_RX_CTL(pipe);
3321         temp = I915_READ(reg);
3322         if (HAS_PCH_CPT(dev)) {
3323                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3324                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3325         } else {
3326                 temp &= ~FDI_LINK_TRAIN_NONE;
3327                 temp |= FDI_LINK_TRAIN_NONE;
3328         }
3329         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3330
3331         /* wait one idle pattern time */
3332         POSTING_READ(reg);
3333         udelay(1000);
3334
3335         /* IVB wants error correction enabled */
3336         if (IS_IVYBRIDGE(dev))
3337                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3338                            FDI_FE_ERRC_ENABLE);
3339 }
3340
3341 /* The FDI link training functions for ILK/Ibexpeak. */
3342 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3343 {
3344         struct drm_device *dev = crtc->dev;
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347         int pipe = intel_crtc->pipe;
3348         i915_reg_t reg;
3349         u32 temp, tries;
3350
3351         /* FDI needs bits from pipe first */
3352         assert_pipe_enabled(dev_priv, pipe);
3353
3354         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3355            for train result */
3356         reg = FDI_RX_IMR(pipe);
3357         temp = I915_READ(reg);
3358         temp &= ~FDI_RX_SYMBOL_LOCK;
3359         temp &= ~FDI_RX_BIT_LOCK;
3360         I915_WRITE(reg, temp);
3361         I915_READ(reg);
3362         udelay(150);
3363
3364         /* enable CPU FDI TX and PCH FDI RX */
3365         reg = FDI_TX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3368         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_1;
3371         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3372
3373         reg = FDI_RX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         temp &= ~FDI_LINK_TRAIN_NONE;
3376         temp |= FDI_LINK_TRAIN_PATTERN_1;
3377         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379         POSTING_READ(reg);
3380         udelay(150);
3381
3382         /* Ironlake workaround, enable clock pointer after FDI enable*/
3383         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3384         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3385                    FDI_RX_PHASE_SYNC_POINTER_EN);
3386
3387         reg = FDI_RX_IIR(pipe);
3388         for (tries = 0; tries < 5; tries++) {
3389                 temp = I915_READ(reg);
3390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391
3392                 if ((temp & FDI_RX_BIT_LOCK)) {
3393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3395                         break;
3396                 }
3397         }
3398         if (tries == 5)
3399                 DRM_ERROR("FDI train 1 fail!\n");
3400
3401         /* Train 2 */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_2;
3406         I915_WRITE(reg, temp);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_LINK_TRAIN_NONE;
3411         temp |= FDI_LINK_TRAIN_PATTERN_2;
3412         I915_WRITE(reg, temp);
3413
3414         POSTING_READ(reg);
3415         udelay(150);
3416
3417         reg = FDI_RX_IIR(pipe);
3418         for (tries = 0; tries < 5; tries++) {
3419                 temp = I915_READ(reg);
3420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422                 if (temp & FDI_RX_SYMBOL_LOCK) {
3423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3425                         break;
3426                 }
3427         }
3428         if (tries == 5)
3429                 DRM_ERROR("FDI train 2 fail!\n");
3430
3431         DRM_DEBUG_KMS("FDI train done\n");
3432
3433 }
3434
3435 static const int snb_b_fdi_train_param[] = {
3436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3440 };
3441
3442 /* The FDI link training functions for SNB/Cougarpoint. */
3443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_private *dev_priv = dev->dev_private;
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449         i915_reg_t reg;
3450         u32 temp, i, retry;
3451
3452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453            for train result */
3454         reg = FDI_RX_IMR(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_RX_SYMBOL_LOCK;
3457         temp &= ~FDI_RX_BIT_LOCK;
3458         I915_WRITE(reg, temp);
3459
3460         POSTING_READ(reg);
3461         udelay(150);
3462
3463         /* enable CPU FDI TX and PCH FDI RX */
3464         reg = FDI_TX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3467         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3468         temp &= ~FDI_LINK_TRAIN_NONE;
3469         temp |= FDI_LINK_TRAIN_PATTERN_1;
3470         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471         /* SNB-B */
3472         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3473         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3474
3475         I915_WRITE(FDI_RX_MISC(pipe),
3476                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3477
3478         reg = FDI_RX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         if (HAS_PCH_CPT(dev)) {
3481                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3482                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483         } else {
3484                 temp &= ~FDI_LINK_TRAIN_NONE;
3485                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486         }
3487         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3488
3489         POSTING_READ(reg);
3490         udelay(150);
3491
3492         for (i = 0; i < 4; i++) {
3493                 reg = FDI_TX_CTL(pipe);
3494                 temp = I915_READ(reg);
3495                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3496                 temp |= snb_b_fdi_train_param[i];
3497                 I915_WRITE(reg, temp);
3498
3499                 POSTING_READ(reg);
3500                 udelay(500);
3501
3502                 for (retry = 0; retry < 5; retry++) {
3503                         reg = FDI_RX_IIR(pipe);
3504                         temp = I915_READ(reg);
3505                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3506                         if (temp & FDI_RX_BIT_LOCK) {
3507                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3508                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3509                                 break;
3510                         }
3511                         udelay(50);
3512                 }
3513                 if (retry < 5)
3514                         break;
3515         }
3516         if (i == 4)
3517                 DRM_ERROR("FDI train 1 fail!\n");
3518
3519         /* Train 2 */
3520         reg = FDI_TX_CTL(pipe);
3521         temp = I915_READ(reg);
3522         temp &= ~FDI_LINK_TRAIN_NONE;
3523         temp |= FDI_LINK_TRAIN_PATTERN_2;
3524         if (IS_GEN6(dev)) {
3525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526                 /* SNB-B */
3527                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3528         }
3529         I915_WRITE(reg, temp);
3530
3531         reg = FDI_RX_CTL(pipe);
3532         temp = I915_READ(reg);
3533         if (HAS_PCH_CPT(dev)) {
3534                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3536         } else {
3537                 temp &= ~FDI_LINK_TRAIN_NONE;
3538                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3539         }
3540         I915_WRITE(reg, temp);
3541
3542         POSTING_READ(reg);
3543         udelay(150);
3544
3545         for (i = 0; i < 4; i++) {
3546                 reg = FDI_TX_CTL(pipe);
3547                 temp = I915_READ(reg);
3548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549                 temp |= snb_b_fdi_train_param[i];
3550                 I915_WRITE(reg, temp);
3551
3552                 POSTING_READ(reg);
3553                 udelay(500);
3554
3555                 for (retry = 0; retry < 5; retry++) {
3556                         reg = FDI_RX_IIR(pipe);
3557                         temp = I915_READ(reg);
3558                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3559                         if (temp & FDI_RX_SYMBOL_LOCK) {
3560                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3561                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3562                                 break;
3563                         }
3564                         udelay(50);
3565                 }
3566                 if (retry < 5)
3567                         break;
3568         }
3569         if (i == 4)
3570                 DRM_ERROR("FDI train 2 fail!\n");
3571
3572         DRM_DEBUG_KMS("FDI train done.\n");
3573 }
3574
3575 /* Manual link training for Ivy Bridge A0 parts */
3576 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581         int pipe = intel_crtc->pipe;
3582         i915_reg_t reg;
3583         u32 temp, i, j;
3584
3585         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3586            for train result */
3587         reg = FDI_RX_IMR(pipe);
3588         temp = I915_READ(reg);
3589         temp &= ~FDI_RX_SYMBOL_LOCK;
3590         temp &= ~FDI_RX_BIT_LOCK;
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3597                       I915_READ(FDI_RX_IIR(pipe)));
3598
3599         /* Try each vswing and preemphasis setting twice before moving on */
3600         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3601                 /* disable first in case we need to retry */
3602                 reg = FDI_TX_CTL(pipe);
3603                 temp = I915_READ(reg);
3604                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3605                 temp &= ~FDI_TX_ENABLE;
3606                 I915_WRITE(reg, temp);
3607
3608                 reg = FDI_RX_CTL(pipe);
3609                 temp = I915_READ(reg);
3610                 temp &= ~FDI_LINK_TRAIN_AUTO;
3611                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3612                 temp &= ~FDI_RX_ENABLE;
3613                 I915_WRITE(reg, temp);
3614
3615                 /* enable CPU FDI TX and PCH FDI RX */
3616                 reg = FDI_TX_CTL(pipe);
3617                 temp = I915_READ(reg);
3618                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3619                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3620                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3622                 temp |= snb_b_fdi_train_param[j/2];
3623                 temp |= FDI_COMPOSITE_SYNC;
3624                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3625
3626                 I915_WRITE(FDI_RX_MISC(pipe),
3627                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3628
3629                 reg = FDI_RX_CTL(pipe);
3630                 temp = I915_READ(reg);
3631                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3632                 temp |= FDI_COMPOSITE_SYNC;
3633                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3634
3635                 POSTING_READ(reg);
3636                 udelay(1); /* should be 0.5us */
3637
3638                 for (i = 0; i < 4; i++) {
3639                         reg = FDI_RX_IIR(pipe);
3640                         temp = I915_READ(reg);
3641                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3642
3643                         if (temp & FDI_RX_BIT_LOCK ||
3644                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3645                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3646                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3647                                               i);
3648                                 break;
3649                         }
3650                         udelay(1); /* should be 0.5us */
3651                 }
3652                 if (i == 4) {
3653                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3654                         continue;
3655                 }
3656
3657                 /* Train 2 */
3658                 reg = FDI_TX_CTL(pipe);
3659                 temp = I915_READ(reg);
3660                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3661                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3662                 I915_WRITE(reg, temp);
3663
3664                 reg = FDI_RX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3667                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3668                 I915_WRITE(reg, temp);
3669
3670                 POSTING_READ(reg);
3671                 udelay(2); /* should be 1.5us */
3672
3673                 for (i = 0; i < 4; i++) {
3674                         reg = FDI_RX_IIR(pipe);
3675                         temp = I915_READ(reg);
3676                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678                         if (temp & FDI_RX_SYMBOL_LOCK ||
3679                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3680                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3681                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3682                                               i);
3683                                 goto train_done;
3684                         }
3685                         udelay(2); /* should be 1.5us */
3686                 }
3687                 if (i == 4)
3688                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3689         }
3690
3691 train_done:
3692         DRM_DEBUG_KMS("FDI train done.\n");
3693 }
3694
3695 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3696 {
3697         struct drm_device *dev = intel_crtc->base.dev;
3698         struct drm_i915_private *dev_priv = dev->dev_private;
3699         int pipe = intel_crtc->pipe;
3700         i915_reg_t reg;
3701         u32 temp;
3702
3703         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3704         reg = FDI_RX_CTL(pipe);
3705         temp = I915_READ(reg);
3706         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3707         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3708         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3709         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3710
3711         POSTING_READ(reg);
3712         udelay(200);
3713
3714         /* Switch from Rawclk to PCDclk */
3715         temp = I915_READ(reg);
3716         I915_WRITE(reg, temp | FDI_PCDCLK);
3717
3718         POSTING_READ(reg);
3719         udelay(200);
3720
3721         /* Enable CPU FDI TX PLL, always on for Ironlake */
3722         reg = FDI_TX_CTL(pipe);
3723         temp = I915_READ(reg);
3724         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3725                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3726
3727                 POSTING_READ(reg);
3728                 udelay(100);
3729         }
3730 }
3731
3732 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3733 {
3734         struct drm_device *dev = intel_crtc->base.dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         int pipe = intel_crtc->pipe;
3737         i915_reg_t reg;
3738         u32 temp;
3739
3740         /* Switch from PCDclk to Rawclk */
3741         reg = FDI_RX_CTL(pipe);
3742         temp = I915_READ(reg);
3743         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3744
3745         /* Disable CPU FDI TX PLL */
3746         reg = FDI_TX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3749
3750         POSTING_READ(reg);
3751         udelay(100);
3752
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3756
3757         /* Wait for the clocks to turn off. */
3758         POSTING_READ(reg);
3759         udelay(100);
3760 }
3761
3762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         int pipe = intel_crtc->pipe;
3768         i915_reg_t reg;
3769         u32 temp;
3770
3771         /* disable CPU FDI tx and PCH FDI rx */
3772         reg = FDI_TX_CTL(pipe);
3773         temp = I915_READ(reg);
3774         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3775         POSTING_READ(reg);
3776
3777         reg = FDI_RX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~(0x7 << 16);
3780         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3781         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3782
3783         POSTING_READ(reg);
3784         udelay(100);
3785
3786         /* Ironlake workaround, disable clock pointer after downing FDI */
3787         if (HAS_PCH_IBX(dev))
3788                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3789
3790         /* still set train pattern 1 */
3791         reg = FDI_TX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         temp &= ~FDI_LINK_TRAIN_NONE;
3794         temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         I915_WRITE(reg, temp);
3796
3797         reg = FDI_RX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         if (HAS_PCH_CPT(dev)) {
3800                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3801                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3802         } else {
3803                 temp &= ~FDI_LINK_TRAIN_NONE;
3804                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3805         }
3806         /* BPC in FDI rx is consistent with that in PIPECONF */
3807         temp &= ~(0x07 << 16);
3808         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3809         I915_WRITE(reg, temp);
3810
3811         POSTING_READ(reg);
3812         udelay(100);
3813 }
3814
3815 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3816 {
3817         struct intel_crtc *crtc;
3818
3819         /* Note that we don't need to be called with mode_config.lock here
3820          * as our list of CRTC objects is static for the lifetime of the
3821          * device and so cannot disappear as we iterate. Similarly, we can
3822          * happily treat the predicates as racy, atomic checks as userspace
3823          * cannot claim and pin a new fb without at least acquring the
3824          * struct_mutex and so serialising with us.
3825          */
3826         for_each_intel_crtc(dev, crtc) {
3827                 if (atomic_read(&crtc->unpin_work_count) == 0)
3828                         continue;
3829
3830                 if (crtc->unpin_work)
3831                         intel_wait_for_vblank(dev, crtc->pipe);
3832
3833                 return true;
3834         }
3835
3836         return false;
3837 }
3838
3839 static void page_flip_completed(struct intel_crtc *intel_crtc)
3840 {
3841         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3842         struct intel_unpin_work *work = intel_crtc->unpin_work;
3843
3844         /* ensure that the unpin work is consistent wrt ->pending. */
3845         smp_rmb();
3846         intel_crtc->unpin_work = NULL;
3847
3848         if (work->event)
3849                 drm_send_vblank_event(intel_crtc->base.dev,
3850                                       intel_crtc->pipe,
3851                                       work->event);
3852
3853         drm_crtc_vblank_put(&intel_crtc->base);
3854
3855         wake_up_all(&dev_priv->pending_flip_queue);
3856         queue_work(dev_priv->wq, &work->work);
3857
3858         trace_i915_flip_complete(intel_crtc->plane,
3859                                  work->pending_flip_obj);
3860 }
3861
3862 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3863 {
3864         struct drm_device *dev = crtc->dev;
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         long ret;
3867
3868         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3869
3870         ret = wait_event_interruptible_timeout(
3871                                         dev_priv->pending_flip_queue,
3872                                         !intel_crtc_has_pending_flip(crtc),
3873                                         60*HZ);
3874
3875         if (ret < 0)
3876                 return ret;
3877
3878         if (ret == 0) {
3879                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880
3881                 spin_lock_irq(&dev->event_lock);
3882                 if (intel_crtc->unpin_work) {
3883                         WARN_ONCE(1, "Removing stuck page flip\n");
3884                         page_flip_completed(intel_crtc);
3885                 }
3886                 spin_unlock_irq(&dev->event_lock);
3887         }
3888
3889         return 0;
3890 }
3891
3892 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3893 {
3894         u32 temp;
3895
3896         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3897
3898         mutex_lock(&dev_priv->sb_lock);
3899
3900         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3901         temp |= SBI_SSCCTL_DISABLE;
3902         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3903
3904         mutex_unlock(&dev_priv->sb_lock);
3905 }
3906
3907 /* Program iCLKIP clock to the desired frequency */
3908 static void lpt_program_iclkip(struct drm_crtc *crtc)
3909 {
3910         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3911         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3912         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3913         u32 temp;
3914
3915         lpt_disable_iclkip(dev_priv);
3916
3917         /* The iCLK virtual clock root frequency is in MHz,
3918          * but the adjusted_mode->crtc_clock in in KHz. To get the
3919          * divisors, it is necessary to divide one by another, so we
3920          * convert the virtual clock precision to KHz here for higher
3921          * precision.
3922          */
3923         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3924                 u32 iclk_virtual_root_freq = 172800 * 1000;
3925                 u32 iclk_pi_range = 64;
3926                 u32 desired_divisor;
3927
3928                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3929                                                     clock << auxdiv);
3930                 divsel = (desired_divisor / iclk_pi_range) - 2;
3931                 phaseinc = desired_divisor % iclk_pi_range;
3932
3933                 /*
3934                  * Near 20MHz is a corner case which is
3935                  * out of range for the 7-bit divisor
3936                  */
3937                 if (divsel <= 0x7f)
3938                         break;
3939         }
3940
3941         /* This should not happen with any sane values */
3942         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3943                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3944         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3945                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3946
3947         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3948                         clock,
3949                         auxdiv,
3950                         divsel,
3951                         phasedir,
3952                         phaseinc);
3953
3954         mutex_lock(&dev_priv->sb_lock);
3955
3956         /* Program SSCDIVINTPHASE6 */
3957         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3958         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3959         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3960         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3961         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3962         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3963         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3964         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3965
3966         /* Program SSCAUXDIV */
3967         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3968         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3969         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3970         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3971
3972         /* Enable modulator and associated divider */
3973         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3974         temp &= ~SBI_SSCCTL_DISABLE;
3975         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3976
3977         mutex_unlock(&dev_priv->sb_lock);
3978
3979         /* Wait for initialization time */
3980         udelay(24);
3981
3982         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3983 }
3984
3985 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3986 {
3987         u32 divsel, phaseinc, auxdiv;
3988         u32 iclk_virtual_root_freq = 172800 * 1000;
3989         u32 iclk_pi_range = 64;
3990         u32 desired_divisor;
3991         u32 temp;
3992
3993         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3994                 return 0;
3995
3996         mutex_lock(&dev_priv->sb_lock);
3997
3998         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999         if (temp & SBI_SSCCTL_DISABLE) {
4000                 mutex_unlock(&dev_priv->sb_lock);
4001                 return 0;
4002         }
4003
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4006                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4007         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4008                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4009
4010         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4011         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4012                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4013
4014         mutex_unlock(&dev_priv->sb_lock);
4015
4016         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4017
4018         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4019                                  desired_divisor << auxdiv);
4020 }
4021
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023                                                 enum pipe pch_transcoder)
4024 {
4025         struct drm_device *dev = crtc->base.dev;
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028
4029         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030                    I915_READ(HTOTAL(cpu_transcoder)));
4031         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032                    I915_READ(HBLANK(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034                    I915_READ(HSYNC(cpu_transcoder)));
4035
4036         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037                    I915_READ(VTOTAL(cpu_transcoder)));
4038         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039                    I915_READ(VBLANK(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041                    I915_READ(VSYNC(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044 }
4045
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         uint32_t temp;
4050
4051         temp = I915_READ(SOUTH_CHICKEN1);
4052         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4053                 return;
4054
4055         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
4058         temp &= ~FDI_BC_BIFURCATION_SELECT;
4059         if (enable)
4060                 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4063         I915_WRITE(SOUTH_CHICKEN1, temp);
4064         POSTING_READ(SOUTH_CHICKEN1);
4065 }
4066
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 {
4069         struct drm_device *dev = intel_crtc->base.dev;
4070
4071         switch (intel_crtc->pipe) {
4072         case PIPE_A:
4073                 break;
4074         case PIPE_B:
4075                 if (intel_crtc->config->fdi_lanes > 2)
4076                         cpt_set_fdi_bc_bifurcation(dev, false);
4077                 else
4078                         cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080                 break;
4081         case PIPE_C:
4082                 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084                 break;
4085         default:
4086                 BUG();
4087         }
4088 }
4089
4090 /* Return which DP Port should be selected for Transcoder DP control */
4091 static enum port
4092 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4093 {
4094         struct drm_device *dev = crtc->dev;
4095         struct intel_encoder *encoder;
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder) {
4098                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4099                     encoder->type == INTEL_OUTPUT_EDP)
4100                         return enc_to_dig_port(&encoder->base)->port;
4101         }
4102
4103         return -1;
4104 }
4105
4106 /*
4107  * Enable PCH resources required for PCH ports:
4108  *   - PCH PLLs
4109  *   - FDI training & RX/TX
4110  *   - update transcoder timings
4111  *   - DP transcoding bits
4112  *   - transcoder
4113  */
4114 static void ironlake_pch_enable(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120         u32 temp;
4121
4122         assert_pch_transcoder_disabled(dev_priv, pipe);
4123
4124         if (IS_IVYBRIDGE(dev))
4125                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4126
4127         /* Write the TU size bits before fdi link training, so that error
4128          * detection works. */
4129         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4130                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4131
4132         /*
4133          * Sometimes spurious CPU pipe underruns happen during FDI
4134          * training, at least with VGA+HDMI cloning. Suppress them.
4135          */
4136         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4137
4138         /* For PCH output, training FDI link */
4139         dev_priv->display.fdi_link_train(crtc);
4140
4141         /* We need to program the right clock selection before writing the pixel
4142          * mutliplier into the DPLL. */
4143         if (HAS_PCH_CPT(dev)) {
4144                 u32 sel;
4145
4146                 temp = I915_READ(PCH_DPLL_SEL);
4147                 temp |= TRANS_DPLL_ENABLE(pipe);
4148                 sel = TRANS_DPLLB_SEL(pipe);
4149                 if (intel_crtc->config->shared_dpll ==
4150                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4151                         temp |= sel;
4152                 else
4153                         temp &= ~sel;
4154                 I915_WRITE(PCH_DPLL_SEL, temp);
4155         }
4156
4157         /* XXX: pch pll's can be enabled any time before we enable the PCH
4158          * transcoder, and we actually should do this to not upset any PCH
4159          * transcoder that already use the clock when we share it.
4160          *
4161          * Note that enable_shared_dpll tries to do the right thing, but
4162          * get_shared_dpll unconditionally resets the pll - we need that to have
4163          * the right LVDS enable sequence. */
4164         intel_enable_shared_dpll(intel_crtc);
4165
4166         /* set transcoder timing, panel must allow it */
4167         assert_panel_unlocked(dev_priv, pipe);
4168         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4169
4170         intel_fdi_normal_train(crtc);
4171
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173
4174         /* For PCH DP, enable TRANS_DP_CTL */
4175         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4176                 const struct drm_display_mode *adjusted_mode =
4177                         &intel_crtc->config->base.adjusted_mode;
4178                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4179                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4180                 temp = I915_READ(reg);
4181                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4182                           TRANS_DP_SYNC_MASK |
4183                           TRANS_DP_BPC_MASK);
4184                 temp |= TRANS_DP_OUTPUT_ENABLE;
4185                 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4188                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4190                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192                 switch (intel_trans_dp_port_sel(crtc)) {
4193                 case PORT_B:
4194                         temp |= TRANS_DP_PORT_SEL_B;
4195                         break;
4196                 case PORT_C:
4197                         temp |= TRANS_DP_PORT_SEL_C;
4198                         break;
4199                 case PORT_D:
4200                         temp |= TRANS_DP_PORT_SEL_D;
4201                         break;
4202                 default:
4203                         BUG();
4204                 }
4205
4206                 I915_WRITE(reg, temp);
4207         }
4208
4209         ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221         lpt_program_iclkip(crtc);
4222
4223         /* Set transcoder timing. */
4224         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4230 {
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         i915_reg_t dslreg = PIPEDSL(pipe);
4233         u32 temp;
4234
4235         temp = I915_READ(dslreg);
4236         udelay(500);
4237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4238                 if (wait_for(I915_READ(dslreg) != temp, 5))
4239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4240         }
4241 }
4242
4243 static int
4244 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4245                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4246                   int src_w, int src_h, int dst_w, int dst_h)
4247 {
4248         struct intel_crtc_scaler_state *scaler_state =
4249                 &crtc_state->scaler_state;
4250         struct intel_crtc *intel_crtc =
4251                 to_intel_crtc(crtc_state->base.crtc);
4252         int need_scaling;
4253
4254         need_scaling = intel_rotation_90_or_270(rotation) ?
4255                 (src_h != dst_w || src_w != dst_h):
4256                 (src_w != dst_w || src_h != dst_h);
4257
4258         /*
4259          * if plane is being disabled or scaler is no more required or force detach
4260          *  - free scaler binded to this plane/crtc
4261          *  - in order to do this, update crtc->scaler_usage
4262          *
4263          * Here scaler state in crtc_state is set free so that
4264          * scaler can be assigned to other user. Actual register
4265          * update to free the scaler is done in plane/panel-fit programming.
4266          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4267          */
4268         if (force_detach || !need_scaling) {
4269                 if (*scaler_id >= 0) {
4270                         scaler_state->scaler_users &= ~(1 << scaler_user);
4271                         scaler_state->scalers[*scaler_id].in_use = 0;
4272
4273                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4274                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4275                                 intel_crtc->pipe, scaler_user, *scaler_id,
4276                                 scaler_state->scaler_users);
4277                         *scaler_id = -1;
4278                 }
4279                 return 0;
4280         }
4281
4282         /* range checks */
4283         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4284                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4285
4286                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4287                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4288                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4289                         "size is out of scaler range\n",
4290                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4291                 return -EINVAL;
4292         }
4293
4294         /* mark this plane as a scaler user in crtc_state */
4295         scaler_state->scaler_users |= (1 << scaler_user);
4296         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4297                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4298                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4299                 scaler_state->scaler_users);
4300
4301         return 0;
4302 }
4303
4304 /**
4305  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4306  *
4307  * @state: crtc's scaler state
4308  *
4309  * Return
4310  *     0 - scaler_usage updated successfully
4311  *    error - requested scaling cannot be supported or other error condition
4312  */
4313 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4314 {
4315         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4316         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4317
4318         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4319                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4320
4321         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4322                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4323                 state->pipe_src_w, state->pipe_src_h,
4324                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4325 }
4326
4327 /**
4328  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4329  *
4330  * @state: crtc's scaler state
4331  * @plane_state: atomic plane state to update
4332  *
4333  * Return
4334  *     0 - scaler_usage updated successfully
4335  *    error - requested scaling cannot be supported or other error condition
4336  */
4337 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4338                                    struct intel_plane_state *plane_state)
4339 {
4340
4341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4342         struct intel_plane *intel_plane =
4343                 to_intel_plane(plane_state->base.plane);
4344         struct drm_framebuffer *fb = plane_state->base.fb;
4345         int ret;
4346
4347         bool force_detach = !fb || !plane_state->visible;
4348
4349         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4350                       intel_plane->base.base.id, intel_crtc->pipe,
4351                       drm_plane_index(&intel_plane->base));
4352
4353         ret = skl_update_scaler(crtc_state, force_detach,
4354                                 drm_plane_index(&intel_plane->base),
4355                                 &plane_state->scaler_id,
4356                                 plane_state->base.rotation,
4357                                 drm_rect_width(&plane_state->src) >> 16,
4358                                 drm_rect_height(&plane_state->src) >> 16,
4359                                 drm_rect_width(&plane_state->dst),
4360                                 drm_rect_height(&plane_state->dst));
4361
4362         if (ret || plane_state->scaler_id < 0)
4363                 return ret;
4364
4365         /* check colorkey */
4366         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4367                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4368                               intel_plane->base.base.id);
4369                 return -EINVAL;
4370         }
4371
4372         /* Check src format */
4373         switch (fb->pixel_format) {
4374         case DRM_FORMAT_RGB565:
4375         case DRM_FORMAT_XBGR8888:
4376         case DRM_FORMAT_XRGB8888:
4377         case DRM_FORMAT_ABGR8888:
4378         case DRM_FORMAT_ARGB8888:
4379         case DRM_FORMAT_XRGB2101010:
4380         case DRM_FORMAT_XBGR2101010:
4381         case DRM_FORMAT_YUYV:
4382         case DRM_FORMAT_YVYU:
4383         case DRM_FORMAT_UYVY:
4384         case DRM_FORMAT_VYUY:
4385                 break;
4386         default:
4387                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4388                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4389                 return -EINVAL;
4390         }
4391
4392         return 0;
4393 }
4394
4395 static void skylake_scaler_disable(struct intel_crtc *crtc)
4396 {
4397         int i;
4398
4399         for (i = 0; i < crtc->num_scalers; i++)
4400                 skl_detach_scaler(crtc, i);
4401 }
4402
4403 static void skylake_pfit_enable(struct intel_crtc *crtc)
4404 {
4405         struct drm_device *dev = crtc->base.dev;
4406         struct drm_i915_private *dev_priv = dev->dev_private;
4407         int pipe = crtc->pipe;
4408         struct intel_crtc_scaler_state *scaler_state =
4409                 &crtc->config->scaler_state;
4410
4411         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4412
4413         if (crtc->config->pch_pfit.enabled) {
4414                 int id;
4415
4416                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4417                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4418                         return;
4419                 }
4420
4421                 id = scaler_state->scaler_id;
4422                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4423                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4424                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4425                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4426
4427                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4428         }
4429 }
4430
4431 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4432 {
4433         struct drm_device *dev = crtc->base.dev;
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         int pipe = crtc->pipe;
4436
4437         if (crtc->config->pch_pfit.enabled) {
4438                 /* Force use of hard-coded filter coefficients
4439                  * as some pre-programmed values are broken,
4440                  * e.g. x201.
4441                  */
4442                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4443                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4444                                                  PF_PIPE_SEL_IVB(pipe));
4445                 else
4446                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4447                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4448                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4449         }
4450 }
4451
4452 void hsw_enable_ips(struct intel_crtc *crtc)
4453 {
4454         struct drm_device *dev = crtc->base.dev;
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457         if (!crtc->config->ips_enabled)
4458                 return;
4459
4460         /* We can only enable IPS after we enable a plane and wait for a vblank */
4461         intel_wait_for_vblank(dev, crtc->pipe);
4462
4463         assert_plane_enabled(dev_priv, crtc->plane);
4464         if (IS_BROADWELL(dev)) {
4465                 mutex_lock(&dev_priv->rps.hw_lock);
4466                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4467                 mutex_unlock(&dev_priv->rps.hw_lock);
4468                 /* Quoting Art Runyan: "its not safe to expect any particular
4469                  * value in IPS_CTL bit 31 after enabling IPS through the
4470                  * mailbox." Moreover, the mailbox may return a bogus state,
4471                  * so we need to just enable it and continue on.
4472                  */
4473         } else {
4474                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4475                 /* The bit only becomes 1 in the next vblank, so this wait here
4476                  * is essentially intel_wait_for_vblank. If we don't have this
4477                  * and don't wait for vblanks until the end of crtc_enable, then
4478                  * the HW state readout code will complain that the expected
4479                  * IPS_CTL value is not the one we read. */
4480                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4481                         DRM_ERROR("Timed out waiting for IPS enable\n");
4482         }
4483 }
4484
4485 void hsw_disable_ips(struct intel_crtc *crtc)
4486 {
4487         struct drm_device *dev = crtc->base.dev;
4488         struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490         if (!crtc->config->ips_enabled)
4491                 return;
4492
4493         assert_plane_enabled(dev_priv, crtc->plane);
4494         if (IS_BROADWELL(dev)) {
4495                 mutex_lock(&dev_priv->rps.hw_lock);
4496                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4497                 mutex_unlock(&dev_priv->rps.hw_lock);
4498                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4499                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4500                         DRM_ERROR("Timed out waiting for IPS disable\n");
4501         } else {
4502                 I915_WRITE(IPS_CTL, 0);
4503                 POSTING_READ(IPS_CTL);
4504         }
4505
4506         /* We need to wait for a vblank before we can disable the plane. */
4507         intel_wait_for_vblank(dev, crtc->pipe);
4508 }
4509
4510 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4511 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516         enum pipe pipe = intel_crtc->pipe;
4517         int i;
4518         bool reenable_ips = false;
4519
4520         /* The clocks have to be on to load the palette. */
4521         if (!crtc->state->active)
4522                 return;
4523
4524         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4525                 if (intel_crtc->config->has_dsi_encoder)
4526                         assert_dsi_pll_enabled(dev_priv);
4527                 else
4528                         assert_pll_enabled(dev_priv, pipe);
4529         }
4530
4531         /* Workaround : Do not read or write the pipe palette/gamma data while
4532          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4533          */
4534         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4535             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4536              GAMMA_MODE_MODE_SPLIT)) {
4537                 hsw_disable_ips(intel_crtc);
4538                 reenable_ips = true;
4539         }
4540
4541         for (i = 0; i < 256; i++) {
4542                 i915_reg_t palreg;
4543
4544                 if (HAS_GMCH_DISPLAY(dev))
4545                         palreg = PALETTE(pipe, i);
4546                 else
4547                         palreg = LGC_PALETTE(pipe, i);
4548
4549                 I915_WRITE(palreg,
4550                            (intel_crtc->lut_r[i] << 16) |
4551                            (intel_crtc->lut_g[i] << 8) |
4552                            intel_crtc->lut_b[i]);
4553         }
4554
4555         if (reenable_ips)
4556                 hsw_enable_ips(intel_crtc);
4557 }
4558
4559 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4560 {
4561         if (intel_crtc->overlay) {
4562                 struct drm_device *dev = intel_crtc->base.dev;
4563                 struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565                 mutex_lock(&dev->struct_mutex);
4566                 dev_priv->mm.interruptible = false;
4567                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4568                 dev_priv->mm.interruptible = true;
4569                 mutex_unlock(&dev->struct_mutex);
4570         }
4571
4572         /* Let userspace switch the overlay on again. In most cases userspace
4573          * has to recompute where to put it anyway.
4574          */
4575 }
4576
4577 /**
4578  * intel_post_enable_primary - Perform operations after enabling primary plane
4579  * @crtc: the CRTC whose primary plane was just enabled
4580  *
4581  * Performs potentially sleeping operations that must be done after the primary
4582  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4583  * called due to an explicit primary plane update, or due to an implicit
4584  * re-enable that is caused when a sprite plane is updated to no longer
4585  * completely hide the primary plane.
4586  */
4587 static void
4588 intel_post_enable_primary(struct drm_crtc *crtc)
4589 {
4590         struct drm_device *dev = crtc->dev;
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         int pipe = intel_crtc->pipe;
4594
4595         /*
4596          * FIXME IPS should be fine as long as one plane is
4597          * enabled, but in practice it seems to have problems
4598          * when going from primary only to sprite only and vice
4599          * versa.
4600          */
4601         hsw_enable_ips(intel_crtc);
4602
4603         /*
4604          * Gen2 reports pipe underruns whenever all planes are disabled.
4605          * So don't enable underrun reporting before at least some planes
4606          * are enabled.
4607          * FIXME: Need to fix the logic to work when we turn off all planes
4608          * but leave the pipe running.
4609          */
4610         if (IS_GEN2(dev))
4611                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4612
4613         /* Underruns don't always raise interrupts, so check manually. */
4614         intel_check_cpu_fifo_underruns(dev_priv);
4615         intel_check_pch_fifo_underruns(dev_priv);
4616 }
4617
4618 /**
4619  * intel_pre_disable_primary - Perform operations before disabling primary plane
4620  * @crtc: the CRTC whose primary plane is to be disabled
4621  *
4622  * Performs potentially sleeping operations that must be done before the
4623  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4624  * be called due to an explicit primary plane update, or due to an implicit
4625  * disable that is caused when a sprite plane completely hides the primary
4626  * plane.
4627  */
4628 static void
4629 intel_pre_disable_primary(struct drm_crtc *crtc)
4630 {
4631         struct drm_device *dev = crtc->dev;
4632         struct drm_i915_private *dev_priv = dev->dev_private;
4633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634         int pipe = intel_crtc->pipe;
4635
4636         /*
4637          * Gen2 reports pipe underruns whenever all planes are disabled.
4638          * So diasble underrun reporting before all the planes get disabled.
4639          * FIXME: Need to fix the logic to work when we turn off all planes
4640          * but leave the pipe running.
4641          */
4642         if (IS_GEN2(dev))
4643                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4644
4645         /*
4646          * Vblank time updates from the shadow to live plane control register
4647          * are blocked if the memory self-refresh mode is active at that
4648          * moment. So to make sure the plane gets truly disabled, disable
4649          * first the self-refresh mode. The self-refresh enable bit in turn
4650          * will be checked/applied by the HW only at the next frame start
4651          * event which is after the vblank start event, so we need to have a
4652          * wait-for-vblank between disabling the plane and the pipe.
4653          */
4654         if (HAS_GMCH_DISPLAY(dev)) {
4655                 intel_set_memory_cxsr(dev_priv, false);
4656                 dev_priv->wm.vlv.cxsr = false;
4657                 intel_wait_for_vblank(dev, pipe);
4658         }
4659
4660         /*
4661          * FIXME IPS should be fine as long as one plane is
4662          * enabled, but in practice it seems to have problems
4663          * when going from primary only to sprite only and vice
4664          * versa.
4665          */
4666         hsw_disable_ips(intel_crtc);
4667 }
4668
4669 static void intel_post_plane_update(struct intel_crtc *crtc)
4670 {
4671         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4672         struct intel_crtc_state *pipe_config =
4673                 to_intel_crtc_state(crtc->base.state);
4674         struct drm_device *dev = crtc->base.dev;
4675
4676         intel_frontbuffer_flip(dev, atomic->fb_bits);
4677
4678         crtc->wm.cxsr_allowed = true;
4679
4680         if (pipe_config->wm_changed && pipe_config->base.active)
4681                 intel_update_watermarks(&crtc->base);
4682
4683         if (atomic->update_fbc)
4684                 intel_fbc_post_update(crtc);
4685
4686         if (atomic->post_enable_primary)
4687                 intel_post_enable_primary(&crtc->base);
4688
4689         memset(atomic, 0, sizeof(*atomic));
4690 }
4691
4692 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4693 {
4694         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4695         struct drm_device *dev = crtc->base.dev;
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4698         struct intel_crtc_state *pipe_config =
4699                 to_intel_crtc_state(crtc->base.state);
4700         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4701         struct drm_plane *primary = crtc->base.primary;
4702         struct drm_plane_state *old_pri_state =
4703                 drm_atomic_get_existing_plane_state(old_state, primary);
4704         bool modeset = needs_modeset(&pipe_config->base);
4705
4706         if (atomic->update_fbc)
4707                 intel_fbc_pre_update(crtc);
4708
4709         if (old_pri_state) {
4710                 struct intel_plane_state *primary_state =
4711                         to_intel_plane_state(primary->state);
4712                 struct intel_plane_state *old_primary_state =
4713                         to_intel_plane_state(old_pri_state);
4714
4715                 if (old_primary_state->visible &&
4716                     (modeset || !primary_state->visible))
4717                         intel_pre_disable_primary(&crtc->base);
4718         }
4719
4720         if (pipe_config->disable_cxsr) {
4721                 crtc->wm.cxsr_allowed = false;
4722
4723                 if (old_crtc_state->base.active)
4724                         intel_set_memory_cxsr(dev_priv, false);
4725         }
4726
4727         /*
4728          * IVB workaround: must disable low power watermarks for at least
4729          * one frame before enabling scaling.  LP watermarks can be re-enabled
4730          * when scaling is disabled.
4731          *
4732          * WaCxSRDisabledForSpriteScaling:ivb
4733          */
4734         if (pipe_config->disable_lp_wm) {
4735                 ilk_disable_lp_wm(dev);
4736                 intel_wait_for_vblank(dev, crtc->pipe);
4737         }
4738
4739         /*
4740          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4741          * watermark programming here.
4742          */
4743         if (needs_modeset(&pipe_config->base))
4744                 return;
4745
4746         /*
4747          * For platforms that support atomic watermarks, program the
4748          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4749          * will be the intermediate values that are safe for both pre- and
4750          * post- vblank; when vblank happens, the 'active' values will be set
4751          * to the final 'target' values and we'll do this again to get the
4752          * optimal watermarks.  For gen9+ platforms, the values we program here
4753          * will be the final target values which will get automatically latched
4754          * at vblank time; no further programming will be necessary.
4755          *
4756          * If a platform hasn't been transitioned to atomic watermarks yet,
4757          * we'll continue to update watermarks the old way, if flags tell
4758          * us to.
4759          */
4760         if (dev_priv->display.initial_watermarks != NULL)
4761                 dev_priv->display.initial_watermarks(pipe_config);
4762         else if (pipe_config->wm_changed)
4763                 intel_update_watermarks(&crtc->base);
4764 }
4765
4766 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4767 {
4768         struct drm_device *dev = crtc->dev;
4769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770         struct drm_plane *p;
4771         int pipe = intel_crtc->pipe;
4772
4773         intel_crtc_dpms_overlay_disable(intel_crtc);
4774
4775         drm_for_each_plane_mask(p, dev, plane_mask)
4776                 to_intel_plane(p)->disable_plane(p, crtc);
4777
4778         /*
4779          * FIXME: Once we grow proper nuclear flip support out of this we need
4780          * to compute the mask of flip planes precisely. For the time being
4781          * consider this a flip to a NULL plane.
4782          */
4783         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4784 }
4785
4786 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4787 {
4788         struct drm_device *dev = crtc->dev;
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4791         struct intel_encoder *encoder;
4792         int pipe = intel_crtc->pipe;
4793
4794         if (WARN_ON(intel_crtc->active))
4795                 return;
4796
4797         if (intel_crtc->config->has_pch_encoder)
4798                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4799
4800         if (intel_crtc->config->has_pch_encoder)
4801                 intel_prepare_shared_dpll(intel_crtc);
4802
4803         if (intel_crtc->config->has_dp_encoder)
4804                 intel_dp_set_m_n(intel_crtc, M1_N1);
4805
4806         intel_set_pipe_timings(intel_crtc);
4807
4808         if (intel_crtc->config->has_pch_encoder) {
4809                 intel_cpu_transcoder_set_m_n(intel_crtc,
4810                                      &intel_crtc->config->fdi_m_n, NULL);
4811         }
4812
4813         ironlake_set_pipeconf(crtc);
4814
4815         intel_crtc->active = true;
4816
4817         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4818
4819         for_each_encoder_on_crtc(dev, crtc, encoder)
4820                 if (encoder->pre_enable)
4821                         encoder->pre_enable(encoder);
4822
4823         if (intel_crtc->config->has_pch_encoder) {
4824                 /* Note: FDI PLL enabling _must_ be done before we enable the
4825                  * cpu pipes, hence this is separate from all the other fdi/pch
4826                  * enabling. */
4827                 ironlake_fdi_pll_enable(intel_crtc);
4828         } else {
4829                 assert_fdi_tx_disabled(dev_priv, pipe);
4830                 assert_fdi_rx_disabled(dev_priv, pipe);
4831         }
4832
4833         ironlake_pfit_enable(intel_crtc);
4834
4835         /*
4836          * On ILK+ LUT must be loaded before the pipe is running but with
4837          * clocks enabled
4838          */
4839         intel_crtc_load_lut(crtc);
4840
4841         if (dev_priv->display.initial_watermarks != NULL)
4842                 dev_priv->display.initial_watermarks(intel_crtc->config);
4843         intel_enable_pipe(intel_crtc);
4844
4845         if (intel_crtc->config->has_pch_encoder)
4846                 ironlake_pch_enable(crtc);
4847
4848         assert_vblank_disabled(crtc);
4849         drm_crtc_vblank_on(crtc);
4850
4851         for_each_encoder_on_crtc(dev, crtc, encoder)
4852                 encoder->enable(encoder);
4853
4854         if (HAS_PCH_CPT(dev))
4855                 cpt_verify_modeset(dev, intel_crtc->pipe);
4856
4857         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4858         if (intel_crtc->config->has_pch_encoder)
4859                 intel_wait_for_vblank(dev, pipe);
4860         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4861 }
4862
4863 /* IPS only exists on ULT machines and is tied to pipe A. */
4864 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4865 {
4866         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4867 }
4868
4869 static void haswell_crtc_enable(struct drm_crtc *crtc)
4870 {
4871         struct drm_device *dev = crtc->dev;
4872         struct drm_i915_private *dev_priv = dev->dev_private;
4873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4874         struct intel_encoder *encoder;
4875         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4876         struct intel_crtc_state *pipe_config =
4877                 to_intel_crtc_state(crtc->state);
4878
4879         if (WARN_ON(intel_crtc->active))
4880                 return;
4881
4882         if (intel_crtc->config->has_pch_encoder)
4883                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4884                                                       false);
4885
4886         if (intel_crtc->config->shared_dpll)
4887                 intel_enable_shared_dpll(intel_crtc);
4888
4889         if (intel_crtc->config->has_dp_encoder)
4890                 intel_dp_set_m_n(intel_crtc, M1_N1);
4891
4892         intel_set_pipe_timings(intel_crtc);
4893
4894         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4895                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4896                            intel_crtc->config->pixel_multiplier - 1);
4897         }
4898
4899         if (intel_crtc->config->has_pch_encoder) {
4900                 intel_cpu_transcoder_set_m_n(intel_crtc,
4901                                      &intel_crtc->config->fdi_m_n, NULL);
4902         }
4903
4904         haswell_set_pipeconf(crtc);
4905
4906         intel_set_pipe_csc(crtc);
4907
4908         intel_crtc->active = true;
4909
4910         if (intel_crtc->config->has_pch_encoder)
4911                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4912         else
4913                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4914
4915         for_each_encoder_on_crtc(dev, crtc, encoder) {
4916                 if (encoder->pre_enable)
4917                         encoder->pre_enable(encoder);
4918         }
4919
4920         if (intel_crtc->config->has_pch_encoder)
4921                 dev_priv->display.fdi_link_train(crtc);
4922
4923         if (!intel_crtc->config->has_dsi_encoder)
4924                 intel_ddi_enable_pipe_clock(intel_crtc);
4925
4926         if (INTEL_INFO(dev)->gen >= 9)
4927                 skylake_pfit_enable(intel_crtc);
4928         else
4929                 ironlake_pfit_enable(intel_crtc);
4930
4931         /*
4932          * On ILK+ LUT must be loaded before the pipe is running but with
4933          * clocks enabled
4934          */
4935         intel_crtc_load_lut(crtc);
4936
4937         intel_ddi_set_pipe_settings(crtc);
4938         if (!intel_crtc->config->has_dsi_encoder)
4939                 intel_ddi_enable_transcoder_func(crtc);
4940
4941         if (dev_priv->display.initial_watermarks != NULL)
4942                 dev_priv->display.initial_watermarks(pipe_config);
4943         else
4944                 intel_update_watermarks(crtc);
4945         intel_enable_pipe(intel_crtc);
4946
4947         if (intel_crtc->config->has_pch_encoder)
4948                 lpt_pch_enable(crtc);
4949
4950         if (intel_crtc->config->dp_encoder_is_mst)
4951                 intel_ddi_set_vc_payload_alloc(crtc, true);
4952
4953         assert_vblank_disabled(crtc);
4954         drm_crtc_vblank_on(crtc);
4955
4956         for_each_encoder_on_crtc(dev, crtc, encoder) {
4957                 encoder->enable(encoder);
4958                 intel_opregion_notify_encoder(encoder, true);
4959         }
4960
4961         if (intel_crtc->config->has_pch_encoder) {
4962                 intel_wait_for_vblank(dev, pipe);
4963                 intel_wait_for_vblank(dev, pipe);
4964                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4965                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4966                                                       true);
4967         }
4968
4969         /* If we change the relative order between pipe/planes enabling, we need
4970          * to change the workaround. */
4971         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4972         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4973                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4974                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4975         }
4976 }
4977
4978 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4979 {
4980         struct drm_device *dev = crtc->base.dev;
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         int pipe = crtc->pipe;
4983
4984         /* To avoid upsetting the power well on haswell only disable the pfit if
4985          * it's in use. The hw state code will make sure we get this right. */
4986         if (force || crtc->config->pch_pfit.enabled) {
4987                 I915_WRITE(PF_CTL(pipe), 0);
4988                 I915_WRITE(PF_WIN_POS(pipe), 0);
4989                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4990         }
4991 }
4992
4993 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct drm_i915_private *dev_priv = dev->dev_private;
4997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4998         struct intel_encoder *encoder;
4999         int pipe = intel_crtc->pipe;
5000
5001         if (intel_crtc->config->has_pch_encoder)
5002                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5003
5004         for_each_encoder_on_crtc(dev, crtc, encoder)
5005                 encoder->disable(encoder);
5006
5007         drm_crtc_vblank_off(crtc);
5008         assert_vblank_disabled(crtc);
5009
5010         /*
5011          * Sometimes spurious CPU pipe underruns happen when the
5012          * pipe is already disabled, but FDI RX/TX is still enabled.
5013          * Happens at least with VGA+HDMI cloning. Suppress them.
5014          */
5015         if (intel_crtc->config->has_pch_encoder)
5016                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5017
5018         intel_disable_pipe(intel_crtc);
5019
5020         ironlake_pfit_disable(intel_crtc, false);
5021
5022         if (intel_crtc->config->has_pch_encoder) {
5023                 ironlake_fdi_disable(crtc);
5024                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025         }
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 if (encoder->post_disable)
5029                         encoder->post_disable(encoder);
5030
5031         if (intel_crtc->config->has_pch_encoder) {
5032                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5033
5034                 if (HAS_PCH_CPT(dev)) {
5035                         i915_reg_t reg;
5036                         u32 temp;
5037
5038                         /* disable TRANS_DP_CTL */
5039                         reg = TRANS_DP_CTL(pipe);
5040                         temp = I915_READ(reg);
5041                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5042                                   TRANS_DP_PORT_SEL_MASK);
5043                         temp |= TRANS_DP_PORT_SEL_NONE;
5044                         I915_WRITE(reg, temp);
5045
5046                         /* disable DPLL_SEL */
5047                         temp = I915_READ(PCH_DPLL_SEL);
5048                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5049                         I915_WRITE(PCH_DPLL_SEL, temp);
5050                 }
5051
5052                 ironlake_fdi_pll_disable(intel_crtc);
5053         }
5054
5055         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5056 }
5057
5058 static void haswell_crtc_disable(struct drm_crtc *crtc)
5059 {
5060         struct drm_device *dev = crtc->dev;
5061         struct drm_i915_private *dev_priv = dev->dev_private;
5062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5063         struct intel_encoder *encoder;
5064         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5065
5066         if (intel_crtc->config->has_pch_encoder)
5067                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5068                                                       false);
5069
5070         for_each_encoder_on_crtc(dev, crtc, encoder) {
5071                 intel_opregion_notify_encoder(encoder, false);
5072                 encoder->disable(encoder);
5073         }
5074
5075         drm_crtc_vblank_off(crtc);
5076         assert_vblank_disabled(crtc);
5077
5078         intel_disable_pipe(intel_crtc);
5079
5080         if (intel_crtc->config->dp_encoder_is_mst)
5081                 intel_ddi_set_vc_payload_alloc(crtc, false);
5082
5083         if (!intel_crtc->config->has_dsi_encoder)
5084                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5085
5086         if (INTEL_INFO(dev)->gen >= 9)
5087                 skylake_scaler_disable(intel_crtc);
5088         else
5089                 ironlake_pfit_disable(intel_crtc, false);
5090
5091         if (!intel_crtc->config->has_dsi_encoder)
5092                 intel_ddi_disable_pipe_clock(intel_crtc);
5093
5094         for_each_encoder_on_crtc(dev, crtc, encoder)
5095                 if (encoder->post_disable)
5096                         encoder->post_disable(encoder);
5097
5098         if (intel_crtc->config->has_pch_encoder) {
5099                 lpt_disable_pch_transcoder(dev_priv);
5100                 lpt_disable_iclkip(dev_priv);
5101                 intel_ddi_fdi_disable(crtc);
5102
5103                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5104                                                       true);
5105         }
5106 }
5107
5108 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5109 {
5110         struct drm_device *dev = crtc->base.dev;
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         struct intel_crtc_state *pipe_config = crtc->config;
5113
5114         if (!pipe_config->gmch_pfit.control)
5115                 return;
5116
5117         /*
5118          * The panel fitter should only be adjusted whilst the pipe is disabled,
5119          * according to register description and PRM.
5120          */
5121         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5122         assert_pipe_disabled(dev_priv, crtc->pipe);
5123
5124         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5125         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5126
5127         /* Border color in case we don't scale up to the full screen. Black by
5128          * default, change to something else for debugging. */
5129         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5130 }
5131
5132 static enum intel_display_power_domain port_to_power_domain(enum port port)
5133 {
5134         switch (port) {
5135         case PORT_A:
5136                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5137         case PORT_B:
5138                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5139         case PORT_C:
5140                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5141         case PORT_D:
5142                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5143         case PORT_E:
5144                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5145         default:
5146                 MISSING_CASE(port);
5147                 return POWER_DOMAIN_PORT_OTHER;
5148         }
5149 }
5150
5151 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5152 {
5153         switch (port) {
5154         case PORT_A:
5155                 return POWER_DOMAIN_AUX_A;
5156         case PORT_B:
5157                 return POWER_DOMAIN_AUX_B;
5158         case PORT_C:
5159                 return POWER_DOMAIN_AUX_C;
5160         case PORT_D:
5161                 return POWER_DOMAIN_AUX_D;
5162         case PORT_E:
5163                 /* FIXME: Check VBT for actual wiring of PORT E */
5164                 return POWER_DOMAIN_AUX_D;
5165         default:
5166                 MISSING_CASE(port);
5167                 return POWER_DOMAIN_AUX_A;
5168         }
5169 }
5170
5171 enum intel_display_power_domain
5172 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5173 {
5174         struct drm_device *dev = intel_encoder->base.dev;
5175         struct intel_digital_port *intel_dig_port;
5176
5177         switch (intel_encoder->type) {
5178         case INTEL_OUTPUT_UNKNOWN:
5179                 /* Only DDI platforms should ever use this output type */
5180                 WARN_ON_ONCE(!HAS_DDI(dev));
5181         case INTEL_OUTPUT_DISPLAYPORT:
5182         case INTEL_OUTPUT_HDMI:
5183         case INTEL_OUTPUT_EDP:
5184                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5185                 return port_to_power_domain(intel_dig_port->port);
5186         case INTEL_OUTPUT_DP_MST:
5187                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5188                 return port_to_power_domain(intel_dig_port->port);
5189         case INTEL_OUTPUT_ANALOG:
5190                 return POWER_DOMAIN_PORT_CRT;
5191         case INTEL_OUTPUT_DSI:
5192                 return POWER_DOMAIN_PORT_DSI;
5193         default:
5194                 return POWER_DOMAIN_PORT_OTHER;
5195         }
5196 }
5197
5198 enum intel_display_power_domain
5199 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5200 {
5201         struct drm_device *dev = intel_encoder->base.dev;
5202         struct intel_digital_port *intel_dig_port;
5203
5204         switch (intel_encoder->type) {
5205         case INTEL_OUTPUT_UNKNOWN:
5206         case INTEL_OUTPUT_HDMI:
5207                 /*
5208                  * Only DDI platforms should ever use these output types.
5209                  * We can get here after the HDMI detect code has already set
5210                  * the type of the shared encoder. Since we can't be sure
5211                  * what's the status of the given connectors, play safe and
5212                  * run the DP detection too.
5213                  */
5214                 WARN_ON_ONCE(!HAS_DDI(dev));
5215         case INTEL_OUTPUT_DISPLAYPORT:
5216         case INTEL_OUTPUT_EDP:
5217                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5218                 return port_to_aux_power_domain(intel_dig_port->port);
5219         case INTEL_OUTPUT_DP_MST:
5220                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5221                 return port_to_aux_power_domain(intel_dig_port->port);
5222         default:
5223                 MISSING_CASE(intel_encoder->type);
5224                 return POWER_DOMAIN_AUX_A;
5225         }
5226 }
5227
5228 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5229                                             struct intel_crtc_state *crtc_state)
5230 {
5231         struct drm_device *dev = crtc->dev;
5232         struct drm_encoder *encoder;
5233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5234         enum pipe pipe = intel_crtc->pipe;
5235         unsigned long mask;
5236         enum transcoder transcoder = crtc_state->cpu_transcoder;
5237
5238         if (!crtc_state->base.active)
5239                 return 0;
5240
5241         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5242         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5243         if (crtc_state->pch_pfit.enabled ||
5244             crtc_state->pch_pfit.force_thru)
5245                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5246
5247         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5248                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5249
5250                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5251         }
5252
5253         return mask;
5254 }
5255
5256 static unsigned long
5257 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5258                                struct intel_crtc_state *crtc_state)
5259 {
5260         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262         enum intel_display_power_domain domain;
5263         unsigned long domains, new_domains, old_domains;
5264
5265         old_domains = intel_crtc->enabled_power_domains;
5266         intel_crtc->enabled_power_domains = new_domains =
5267                 get_crtc_power_domains(crtc, crtc_state);
5268
5269         domains = new_domains & ~old_domains;
5270
5271         for_each_power_domain(domain, domains)
5272                 intel_display_power_get(dev_priv, domain);
5273
5274         return old_domains & ~new_domains;
5275 }
5276
5277 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5278                                       unsigned long domains)
5279 {
5280         enum intel_display_power_domain domain;
5281
5282         for_each_power_domain(domain, domains)
5283                 intel_display_power_put(dev_priv, domain);
5284 }
5285
5286 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5287 {
5288         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5289
5290         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5291             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5292                 return max_cdclk_freq;
5293         else if (IS_CHERRYVIEW(dev_priv))
5294                 return max_cdclk_freq*95/100;
5295         else if (INTEL_INFO(dev_priv)->gen < 4)
5296                 return 2*max_cdclk_freq*90/100;
5297         else
5298                 return max_cdclk_freq*90/100;
5299 }
5300
5301 static void intel_update_max_cdclk(struct drm_device *dev)
5302 {
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304
5305         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5306                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5307
5308                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5309                         dev_priv->max_cdclk_freq = 675000;
5310                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5311                         dev_priv->max_cdclk_freq = 540000;
5312                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5313                         dev_priv->max_cdclk_freq = 450000;
5314                 else
5315                         dev_priv->max_cdclk_freq = 337500;
5316         } else if (IS_BROADWELL(dev))  {
5317                 /*
5318                  * FIXME with extra cooling we can allow
5319                  * 540 MHz for ULX and 675 Mhz for ULT.
5320                  * How can we know if extra cooling is
5321                  * available? PCI ID, VTB, something else?
5322                  */
5323                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5324                         dev_priv->max_cdclk_freq = 450000;
5325                 else if (IS_BDW_ULX(dev))
5326                         dev_priv->max_cdclk_freq = 450000;
5327                 else if (IS_BDW_ULT(dev))
5328                         dev_priv->max_cdclk_freq = 540000;
5329                 else
5330                         dev_priv->max_cdclk_freq = 675000;
5331         } else if (IS_CHERRYVIEW(dev)) {
5332                 dev_priv->max_cdclk_freq = 320000;
5333         } else if (IS_VALLEYVIEW(dev)) {
5334                 dev_priv->max_cdclk_freq = 400000;
5335         } else {
5336                 /* otherwise assume cdclk is fixed */
5337                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5338         }
5339
5340         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5341
5342         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5343                          dev_priv->max_cdclk_freq);
5344
5345         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5346                          dev_priv->max_dotclk_freq);
5347 }
5348
5349 static void intel_update_cdclk(struct drm_device *dev)
5350 {
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352
5353         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5354         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5355                          dev_priv->cdclk_freq);
5356
5357         /*
5358          * Program the gmbus_freq based on the cdclk frequency.
5359          * BSpec erroneously claims we should aim for 4MHz, but
5360          * in fact 1MHz is the correct frequency.
5361          */
5362         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5363                 /*
5364                  * Program the gmbus_freq based on the cdclk frequency.
5365                  * BSpec erroneously claims we should aim for 4MHz, but
5366                  * in fact 1MHz is the correct frequency.
5367                  */
5368                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5369         }
5370
5371         if (dev_priv->max_cdclk_freq == 0)
5372                 intel_update_max_cdclk(dev);
5373 }
5374
5375 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5376 {
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         uint32_t divider;
5379         uint32_t ratio;
5380         uint32_t current_freq;
5381         int ret;
5382
5383         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5384         switch (frequency) {
5385         case 144000:
5386                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5387                 ratio = BXT_DE_PLL_RATIO(60);
5388                 break;
5389         case 288000:
5390                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5391                 ratio = BXT_DE_PLL_RATIO(60);
5392                 break;
5393         case 384000:
5394                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5395                 ratio = BXT_DE_PLL_RATIO(60);
5396                 break;
5397         case 576000:
5398                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5399                 ratio = BXT_DE_PLL_RATIO(60);
5400                 break;
5401         case 624000:
5402                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5403                 ratio = BXT_DE_PLL_RATIO(65);
5404                 break;
5405         case 19200:
5406                 /*
5407                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5408                  * to suppress GCC warning.
5409                  */
5410                 ratio = 0;
5411                 divider = 0;
5412                 break;
5413         default:
5414                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5415
5416                 return;
5417         }
5418
5419         mutex_lock(&dev_priv->rps.hw_lock);
5420         /* Inform power controller of upcoming frequency change */
5421         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5422                                       0x80000000);
5423         mutex_unlock(&dev_priv->rps.hw_lock);
5424
5425         if (ret) {
5426                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5427                           ret, frequency);
5428                 return;
5429         }
5430
5431         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5432         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5433         current_freq = current_freq * 500 + 1000;
5434
5435         /*
5436          * DE PLL has to be disabled when
5437          * - setting to 19.2MHz (bypass, PLL isn't used)
5438          * - before setting to 624MHz (PLL needs toggling)
5439          * - before setting to any frequency from 624MHz (PLL needs toggling)
5440          */
5441         if (frequency == 19200 || frequency == 624000 ||
5442             current_freq == 624000) {
5443                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5444                 /* Timeout 200us */
5445                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5446                              1))
5447                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5448         }
5449
5450         if (frequency != 19200) {
5451                 uint32_t val;
5452
5453                 val = I915_READ(BXT_DE_PLL_CTL);
5454                 val &= ~BXT_DE_PLL_RATIO_MASK;
5455                 val |= ratio;
5456                 I915_WRITE(BXT_DE_PLL_CTL, val);
5457
5458                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5459                 /* Timeout 200us */
5460                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5461                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5462
5463                 val = I915_READ(CDCLK_CTL);
5464                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5465                 val |= divider;
5466                 /*
5467                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5468                  * enable otherwise.
5469                  */
5470                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5471                 if (frequency >= 500000)
5472                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5473
5474                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5475                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5476                 val |= (frequency - 1000) / 500;
5477                 I915_WRITE(CDCLK_CTL, val);
5478         }
5479
5480         mutex_lock(&dev_priv->rps.hw_lock);
5481         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5482                                       DIV_ROUND_UP(frequency, 25000));
5483         mutex_unlock(&dev_priv->rps.hw_lock);
5484
5485         if (ret) {
5486                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5487                           ret, frequency);
5488                 return;
5489         }
5490
5491         intel_update_cdclk(dev);
5492 }
5493
5494 void broxton_init_cdclk(struct drm_device *dev)
5495 {
5496         struct drm_i915_private *dev_priv = dev->dev_private;
5497         uint32_t val;
5498
5499         /*
5500          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5501          * or else the reset will hang because there is no PCH to respond.
5502          * Move the handshake programming to initialization sequence.
5503          * Previously was left up to BIOS.
5504          */
5505         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5506         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5507         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5508
5509         /* Enable PG1 for cdclk */
5510         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5511
5512         /* check if cd clock is enabled */
5513         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5514                 DRM_DEBUG_KMS("Display already initialized\n");
5515                 return;
5516         }
5517
5518         /*
5519          * FIXME:
5520          * - The initial CDCLK needs to be read from VBT.
5521          *   Need to make this change after VBT has changes for BXT.
5522          * - check if setting the max (or any) cdclk freq is really necessary
5523          *   here, it belongs to modeset time
5524          */
5525         broxton_set_cdclk(dev, 624000);
5526
5527         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5528         POSTING_READ(DBUF_CTL);
5529
5530         udelay(10);
5531
5532         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5533                 DRM_ERROR("DBuf power enable timeout!\n");
5534 }
5535
5536 void broxton_uninit_cdclk(struct drm_device *dev)
5537 {
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539
5540         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5541         POSTING_READ(DBUF_CTL);
5542
5543         udelay(10);
5544
5545         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5546                 DRM_ERROR("DBuf power disable timeout!\n");
5547
5548         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5549         broxton_set_cdclk(dev, 19200);
5550
5551         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5552 }
5553
5554 static const struct skl_cdclk_entry {
5555         unsigned int freq;
5556         unsigned int vco;
5557 } skl_cdclk_frequencies[] = {
5558         { .freq = 308570, .vco = 8640 },
5559         { .freq = 337500, .vco = 8100 },
5560         { .freq = 432000, .vco = 8640 },
5561         { .freq = 450000, .vco = 8100 },
5562         { .freq = 540000, .vco = 8100 },
5563         { .freq = 617140, .vco = 8640 },
5564         { .freq = 675000, .vco = 8100 },
5565 };
5566
5567 static unsigned int skl_cdclk_decimal(unsigned int freq)
5568 {
5569         return (freq - 1000) / 500;
5570 }
5571
5572 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5573 {
5574         unsigned int i;
5575
5576         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5577                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5578
5579                 if (e->freq == freq)
5580                         return e->vco;
5581         }
5582
5583         return 8100;
5584 }
5585
5586 static void
5587 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5588 {
5589         unsigned int min_freq;
5590         u32 val;
5591
5592         /* select the minimum CDCLK before enabling DPLL 0 */
5593         val = I915_READ(CDCLK_CTL);
5594         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5595         val |= CDCLK_FREQ_337_308;
5596
5597         if (required_vco == 8640)
5598                 min_freq = 308570;
5599         else
5600                 min_freq = 337500;
5601
5602         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5603
5604         I915_WRITE(CDCLK_CTL, val);
5605         POSTING_READ(CDCLK_CTL);
5606
5607         /*
5608          * We always enable DPLL0 with the lowest link rate possible, but still
5609          * taking into account the VCO required to operate the eDP panel at the
5610          * desired frequency. The usual DP link rates operate with a VCO of
5611          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5612          * The modeset code is responsible for the selection of the exact link
5613          * rate later on, with the constraint of choosing a frequency that
5614          * works with required_vco.
5615          */
5616         val = I915_READ(DPLL_CTRL1);
5617
5618         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5619                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5620         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5621         if (required_vco == 8640)
5622                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5623                                             SKL_DPLL0);
5624         else
5625                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5626                                             SKL_DPLL0);
5627
5628         I915_WRITE(DPLL_CTRL1, val);
5629         POSTING_READ(DPLL_CTRL1);
5630
5631         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5632
5633         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5634                 DRM_ERROR("DPLL0 not locked\n");
5635 }
5636
5637 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5638 {
5639         int ret;
5640         u32 val;
5641
5642         /* inform PCU we want to change CDCLK */
5643         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5644         mutex_lock(&dev_priv->rps.hw_lock);
5645         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5646         mutex_unlock(&dev_priv->rps.hw_lock);
5647
5648         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5649 }
5650
5651 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5652 {
5653         unsigned int i;
5654
5655         for (i = 0; i < 15; i++) {
5656                 if (skl_cdclk_pcu_ready(dev_priv))
5657                         return true;
5658                 udelay(10);
5659         }
5660
5661         return false;
5662 }
5663
5664 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5665 {
5666         struct drm_device *dev = dev_priv->dev;
5667         u32 freq_select, pcu_ack;
5668
5669         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5670
5671         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5672                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5673                 return;
5674         }
5675
5676         /* set CDCLK_CTL */
5677         switch(freq) {
5678         case 450000:
5679         case 432000:
5680                 freq_select = CDCLK_FREQ_450_432;
5681                 pcu_ack = 1;
5682                 break;
5683         case 540000:
5684                 freq_select = CDCLK_FREQ_540;
5685                 pcu_ack = 2;
5686                 break;
5687         case 308570:
5688         case 337500:
5689         default:
5690                 freq_select = CDCLK_FREQ_337_308;
5691                 pcu_ack = 0;
5692                 break;
5693         case 617140:
5694         case 675000:
5695                 freq_select = CDCLK_FREQ_675_617;
5696                 pcu_ack = 3;
5697                 break;
5698         }
5699
5700         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5701         POSTING_READ(CDCLK_CTL);
5702
5703         /* inform PCU of the change */
5704         mutex_lock(&dev_priv->rps.hw_lock);
5705         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5706         mutex_unlock(&dev_priv->rps.hw_lock);
5707
5708         intel_update_cdclk(dev);
5709 }
5710
5711 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5712 {
5713         /* disable DBUF power */
5714         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5715         POSTING_READ(DBUF_CTL);
5716
5717         udelay(10);
5718
5719         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5720                 DRM_ERROR("DBuf power disable timeout\n");
5721
5722         /* disable DPLL0 */
5723         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5724         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5725                 DRM_ERROR("Couldn't disable DPLL0\n");
5726 }
5727
5728 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5729 {
5730         unsigned int required_vco;
5731
5732         /* DPLL0 not enabled (happens on early BIOS versions) */
5733         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5734                 /* enable DPLL0 */
5735                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5736                 skl_dpll0_enable(dev_priv, required_vco);
5737         }
5738
5739         /* set CDCLK to the frequency the BIOS chose */
5740         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5741
5742         /* enable DBUF power */
5743         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5744         POSTING_READ(DBUF_CTL);
5745
5746         udelay(10);
5747
5748         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5749                 DRM_ERROR("DBuf power enable timeout\n");
5750 }
5751
5752 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5753 {
5754         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5755         uint32_t cdctl = I915_READ(CDCLK_CTL);
5756         int freq = dev_priv->skl_boot_cdclk;
5757
5758         /*
5759          * check if the pre-os intialized the display
5760          * There is SWF18 scratchpad register defined which is set by the
5761          * pre-os which can be used by the OS drivers to check the status
5762          */
5763         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5764                 goto sanitize;
5765
5766         /* Is PLL enabled and locked ? */
5767         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5768                 goto sanitize;
5769
5770         /* DPLL okay; verify the cdclock
5771          *
5772          * Noticed in some instances that the freq selection is correct but
5773          * decimal part is programmed wrong from BIOS where pre-os does not
5774          * enable display. Verify the same as well.
5775          */
5776         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5777                 /* All well; nothing to sanitize */
5778                 return false;
5779 sanitize:
5780         /*
5781          * As of now initialize with max cdclk till
5782          * we get dynamic cdclk support
5783          * */
5784         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5785         skl_init_cdclk(dev_priv);
5786
5787         /* we did have to sanitize */
5788         return true;
5789 }
5790
5791 /* Adjust CDclk dividers to allow high res or save power if possible */
5792 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5793 {
5794         struct drm_i915_private *dev_priv = dev->dev_private;
5795         u32 val, cmd;
5796
5797         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5798                                         != dev_priv->cdclk_freq);
5799
5800         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5801                 cmd = 2;
5802         else if (cdclk == 266667)
5803                 cmd = 1;
5804         else
5805                 cmd = 0;
5806
5807         mutex_lock(&dev_priv->rps.hw_lock);
5808         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809         val &= ~DSPFREQGUAR_MASK;
5810         val |= (cmd << DSPFREQGUAR_SHIFT);
5811         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5814                      50)) {
5815                 DRM_ERROR("timed out waiting for CDclk change\n");
5816         }
5817         mutex_unlock(&dev_priv->rps.hw_lock);
5818
5819         mutex_lock(&dev_priv->sb_lock);
5820
5821         if (cdclk == 400000) {
5822                 u32 divider;
5823
5824                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5825
5826                 /* adjust cdclk divider */
5827                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5828                 val &= ~CCK_FREQUENCY_VALUES;
5829                 val |= divider;
5830                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5831
5832                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5833                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5834                              50))
5835                         DRM_ERROR("timed out waiting for CDclk change\n");
5836         }
5837
5838         /* adjust self-refresh exit latency value */
5839         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5840         val &= ~0x7f;
5841
5842         /*
5843          * For high bandwidth configs, we set a higher latency in the bunit
5844          * so that the core display fetch happens in time to avoid underruns.
5845          */
5846         if (cdclk == 400000)
5847                 val |= 4500 / 250; /* 4.5 usec */
5848         else
5849                 val |= 3000 / 250; /* 3.0 usec */
5850         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5851
5852         mutex_unlock(&dev_priv->sb_lock);
5853
5854         intel_update_cdclk(dev);
5855 }
5856
5857 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5858 {
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860         u32 val, cmd;
5861
5862         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5863                                                 != dev_priv->cdclk_freq);
5864
5865         switch (cdclk) {
5866         case 333333:
5867         case 320000:
5868         case 266667:
5869         case 200000:
5870                 break;
5871         default:
5872                 MISSING_CASE(cdclk);
5873                 return;
5874         }
5875
5876         /*
5877          * Specs are full of misinformation, but testing on actual
5878          * hardware has shown that we just need to write the desired
5879          * CCK divider into the Punit register.
5880          */
5881         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5882
5883         mutex_lock(&dev_priv->rps.hw_lock);
5884         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5885         val &= ~DSPFREQGUAR_MASK_CHV;
5886         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5887         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5888         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5889                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5890                      50)) {
5891                 DRM_ERROR("timed out waiting for CDclk change\n");
5892         }
5893         mutex_unlock(&dev_priv->rps.hw_lock);
5894
5895         intel_update_cdclk(dev);
5896 }
5897
5898 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5899                                  int max_pixclk)
5900 {
5901         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5902         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5903
5904         /*
5905          * Really only a few cases to deal with, as only 4 CDclks are supported:
5906          *   200MHz
5907          *   267MHz
5908          *   320/333MHz (depends on HPLL freq)
5909          *   400MHz (VLV only)
5910          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5911          * of the lower bin and adjust if needed.
5912          *
5913          * We seem to get an unstable or solid color picture at 200MHz.
5914          * Not sure what's wrong. For now use 200MHz only when all pipes
5915          * are off.
5916          */
5917         if (!IS_CHERRYVIEW(dev_priv) &&
5918             max_pixclk > freq_320*limit/100)
5919                 return 400000;
5920         else if (max_pixclk > 266667*limit/100)
5921                 return freq_320;
5922         else if (max_pixclk > 0)
5923                 return 266667;
5924         else
5925                 return 200000;
5926 }
5927
5928 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5929                               int max_pixclk)
5930 {
5931         /*
5932          * FIXME:
5933          * - remove the guardband, it's not needed on BXT
5934          * - set 19.2MHz bypass frequency if there are no active pipes
5935          */
5936         if (max_pixclk > 576000*9/10)
5937                 return 624000;
5938         else if (max_pixclk > 384000*9/10)
5939                 return 576000;
5940         else if (max_pixclk > 288000*9/10)
5941                 return 384000;
5942         else if (max_pixclk > 144000*9/10)
5943                 return 288000;
5944         else
5945                 return 144000;
5946 }
5947
5948 /* Compute the max pixel clock for new configuration. */
5949 static int intel_mode_max_pixclk(struct drm_device *dev,
5950                                  struct drm_atomic_state *state)
5951 {
5952         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5953         struct drm_i915_private *dev_priv = dev->dev_private;
5954         struct drm_crtc *crtc;
5955         struct drm_crtc_state *crtc_state;
5956         unsigned max_pixclk = 0, i;
5957         enum pipe pipe;
5958
5959         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5960                sizeof(intel_state->min_pixclk));
5961
5962         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5963                 int pixclk = 0;
5964
5965                 if (crtc_state->enable)
5966                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5967
5968                 intel_state->min_pixclk[i] = pixclk;
5969         }
5970
5971         for_each_pipe(dev_priv, pipe)
5972                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5973
5974         return max_pixclk;
5975 }
5976
5977 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5978 {
5979         struct drm_device *dev = state->dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         int max_pixclk = intel_mode_max_pixclk(dev, state);
5982         struct intel_atomic_state *intel_state =
5983                 to_intel_atomic_state(state);
5984
5985         if (max_pixclk < 0)
5986                 return max_pixclk;
5987
5988         intel_state->cdclk = intel_state->dev_cdclk =
5989                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5990
5991         if (!intel_state->active_crtcs)
5992                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5993
5994         return 0;
5995 }
5996
5997 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5998 {
5999         struct drm_device *dev = state->dev;
6000         struct drm_i915_private *dev_priv = dev->dev_private;
6001         int max_pixclk = intel_mode_max_pixclk(dev, state);
6002         struct intel_atomic_state *intel_state =
6003                 to_intel_atomic_state(state);
6004
6005         if (max_pixclk < 0)
6006                 return max_pixclk;
6007
6008         intel_state->cdclk = intel_state->dev_cdclk =
6009                 broxton_calc_cdclk(dev_priv, max_pixclk);
6010
6011         if (!intel_state->active_crtcs)
6012                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6013
6014         return 0;
6015 }
6016
6017 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6018 {
6019         unsigned int credits, default_credits;
6020
6021         if (IS_CHERRYVIEW(dev_priv))
6022                 default_credits = PFI_CREDIT(12);
6023         else
6024                 default_credits = PFI_CREDIT(8);
6025
6026         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6027                 /* CHV suggested value is 31 or 63 */
6028                 if (IS_CHERRYVIEW(dev_priv))
6029                         credits = PFI_CREDIT_63;
6030                 else
6031                         credits = PFI_CREDIT(15);
6032         } else {
6033                 credits = default_credits;
6034         }
6035
6036         /*
6037          * WA - write default credits before re-programming
6038          * FIXME: should we also set the resend bit here?
6039          */
6040         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6041                    default_credits);
6042
6043         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6044                    credits | PFI_CREDIT_RESEND);
6045
6046         /*
6047          * FIXME is this guaranteed to clear
6048          * immediately or should we poll for it?
6049          */
6050         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6051 }
6052
6053 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6054 {
6055         struct drm_device *dev = old_state->dev;
6056         struct drm_i915_private *dev_priv = dev->dev_private;
6057         struct intel_atomic_state *old_intel_state =
6058                 to_intel_atomic_state(old_state);
6059         unsigned req_cdclk = old_intel_state->dev_cdclk;
6060
6061         /*
6062          * FIXME: We can end up here with all power domains off, yet
6063          * with a CDCLK frequency other than the minimum. To account
6064          * for this take the PIPE-A power domain, which covers the HW
6065          * blocks needed for the following programming. This can be
6066          * removed once it's guaranteed that we get here either with
6067          * the minimum CDCLK set, or the required power domains
6068          * enabled.
6069          */
6070         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6071
6072         if (IS_CHERRYVIEW(dev))
6073                 cherryview_set_cdclk(dev, req_cdclk);
6074         else
6075                 valleyview_set_cdclk(dev, req_cdclk);
6076
6077         vlv_program_pfi_credits(dev_priv);
6078
6079         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6080 }
6081
6082 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6083 {
6084         struct drm_device *dev = crtc->dev;
6085         struct drm_i915_private *dev_priv = to_i915(dev);
6086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087         struct intel_encoder *encoder;
6088         int pipe = intel_crtc->pipe;
6089
6090         if (WARN_ON(intel_crtc->active))
6091                 return;
6092
6093         if (intel_crtc->config->has_dp_encoder)
6094                 intel_dp_set_m_n(intel_crtc, M1_N1);
6095
6096         intel_set_pipe_timings(intel_crtc);
6097
6098         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6099                 struct drm_i915_private *dev_priv = dev->dev_private;
6100
6101                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6102                 I915_WRITE(CHV_CANVAS(pipe), 0);
6103         }
6104
6105         i9xx_set_pipeconf(intel_crtc);
6106
6107         intel_crtc->active = true;
6108
6109         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6110
6111         for_each_encoder_on_crtc(dev, crtc, encoder)
6112                 if (encoder->pre_pll_enable)
6113                         encoder->pre_pll_enable(encoder);
6114
6115         if (!intel_crtc->config->has_dsi_encoder) {
6116                 if (IS_CHERRYVIEW(dev)) {
6117                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6118                         chv_enable_pll(intel_crtc, intel_crtc->config);
6119                 } else {
6120                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6121                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6122                 }
6123         }
6124
6125         for_each_encoder_on_crtc(dev, crtc, encoder)
6126                 if (encoder->pre_enable)
6127                         encoder->pre_enable(encoder);
6128
6129         i9xx_pfit_enable(intel_crtc);
6130
6131         intel_crtc_load_lut(crtc);
6132
6133         intel_enable_pipe(intel_crtc);
6134
6135         assert_vblank_disabled(crtc);
6136         drm_crtc_vblank_on(crtc);
6137
6138         for_each_encoder_on_crtc(dev, crtc, encoder)
6139                 encoder->enable(encoder);
6140 }
6141
6142 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6143 {
6144         struct drm_device *dev = crtc->base.dev;
6145         struct drm_i915_private *dev_priv = dev->dev_private;
6146
6147         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6148         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6149 }
6150
6151 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6152 {
6153         struct drm_device *dev = crtc->dev;
6154         struct drm_i915_private *dev_priv = to_i915(dev);
6155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6156         struct intel_encoder *encoder;
6157         int pipe = intel_crtc->pipe;
6158
6159         if (WARN_ON(intel_crtc->active))
6160                 return;
6161
6162         i9xx_set_pll_dividers(intel_crtc);
6163
6164         if (intel_crtc->config->has_dp_encoder)
6165                 intel_dp_set_m_n(intel_crtc, M1_N1);
6166
6167         intel_set_pipe_timings(intel_crtc);
6168
6169         i9xx_set_pipeconf(intel_crtc);
6170
6171         intel_crtc->active = true;
6172
6173         if (!IS_GEN2(dev))
6174                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6175
6176         for_each_encoder_on_crtc(dev, crtc, encoder)
6177                 if (encoder->pre_enable)
6178                         encoder->pre_enable(encoder);
6179
6180         i9xx_enable_pll(intel_crtc);
6181
6182         i9xx_pfit_enable(intel_crtc);
6183
6184         intel_crtc_load_lut(crtc);
6185
6186         intel_update_watermarks(crtc);
6187         intel_enable_pipe(intel_crtc);
6188
6189         assert_vblank_disabled(crtc);
6190         drm_crtc_vblank_on(crtc);
6191
6192         for_each_encoder_on_crtc(dev, crtc, encoder)
6193                 encoder->enable(encoder);
6194 }
6195
6196 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6197 {
6198         struct drm_device *dev = crtc->base.dev;
6199         struct drm_i915_private *dev_priv = dev->dev_private;
6200
6201         if (!crtc->config->gmch_pfit.control)
6202                 return;
6203
6204         assert_pipe_disabled(dev_priv, crtc->pipe);
6205
6206         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6207                          I915_READ(PFIT_CONTROL));
6208         I915_WRITE(PFIT_CONTROL, 0);
6209 }
6210
6211 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6212 {
6213         struct drm_device *dev = crtc->dev;
6214         struct drm_i915_private *dev_priv = dev->dev_private;
6215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216         struct intel_encoder *encoder;
6217         int pipe = intel_crtc->pipe;
6218
6219         /*
6220          * On gen2 planes are double buffered but the pipe isn't, so we must
6221          * wait for planes to fully turn off before disabling the pipe.
6222          * We also need to wait on all gmch platforms because of the
6223          * self-refresh mode constraint explained above.
6224          */
6225         intel_wait_for_vblank(dev, pipe);
6226
6227         for_each_encoder_on_crtc(dev, crtc, encoder)
6228                 encoder->disable(encoder);
6229
6230         drm_crtc_vblank_off(crtc);
6231         assert_vblank_disabled(crtc);
6232
6233         intel_disable_pipe(intel_crtc);
6234
6235         i9xx_pfit_disable(intel_crtc);
6236
6237         for_each_encoder_on_crtc(dev, crtc, encoder)
6238                 if (encoder->post_disable)
6239                         encoder->post_disable(encoder);
6240
6241         if (!intel_crtc->config->has_dsi_encoder) {
6242                 if (IS_CHERRYVIEW(dev))
6243                         chv_disable_pll(dev_priv, pipe);
6244                 else if (IS_VALLEYVIEW(dev))
6245                         vlv_disable_pll(dev_priv, pipe);
6246                 else
6247                         i9xx_disable_pll(intel_crtc);
6248         }
6249
6250         for_each_encoder_on_crtc(dev, crtc, encoder)
6251                 if (encoder->post_pll_disable)
6252                         encoder->post_pll_disable(encoder);
6253
6254         if (!IS_GEN2(dev))
6255                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6256 }
6257
6258 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6259 {
6260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6261         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6262         enum intel_display_power_domain domain;
6263         unsigned long domains;
6264
6265         if (!intel_crtc->active)
6266                 return;
6267
6268         if (to_intel_plane_state(crtc->primary->state)->visible) {
6269                 WARN_ON(intel_crtc->unpin_work);
6270
6271                 intel_pre_disable_primary(crtc);
6272
6273                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6274                 to_intel_plane_state(crtc->primary->state)->visible = false;
6275         }
6276
6277         dev_priv->display.crtc_disable(crtc);
6278         intel_crtc->active = false;
6279         intel_fbc_disable(intel_crtc);
6280         intel_update_watermarks(crtc);
6281         intel_disable_shared_dpll(intel_crtc);
6282
6283         domains = intel_crtc->enabled_power_domains;
6284         for_each_power_domain(domain, domains)
6285                 intel_display_power_put(dev_priv, domain);
6286         intel_crtc->enabled_power_domains = 0;
6287
6288         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6289         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6290 }
6291
6292 /*
6293  * turn all crtc's off, but do not adjust state
6294  * This has to be paired with a call to intel_modeset_setup_hw_state.
6295  */
6296 int intel_display_suspend(struct drm_device *dev)
6297 {
6298         struct drm_i915_private *dev_priv = to_i915(dev);
6299         struct drm_atomic_state *state;
6300         int ret;
6301
6302         state = drm_atomic_helper_suspend(dev);
6303         ret = PTR_ERR_OR_ZERO(state);
6304         if (ret)
6305                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6306         else
6307                 dev_priv->modeset_restore_state = state;
6308         return ret;
6309 }
6310
6311 void intel_encoder_destroy(struct drm_encoder *encoder)
6312 {
6313         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6314
6315         drm_encoder_cleanup(encoder);
6316         kfree(intel_encoder);
6317 }
6318
6319 /* Cross check the actual hw state with our own modeset state tracking (and it's
6320  * internal consistency). */
6321 static void intel_connector_check_state(struct intel_connector *connector)
6322 {
6323         struct drm_crtc *crtc = connector->base.state->crtc;
6324
6325         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6326                       connector->base.base.id,
6327                       connector->base.name);
6328
6329         if (connector->get_hw_state(connector)) {
6330                 struct intel_encoder *encoder = connector->encoder;
6331                 struct drm_connector_state *conn_state = connector->base.state;
6332
6333                 I915_STATE_WARN(!crtc,
6334                          "connector enabled without attached crtc\n");
6335
6336                 if (!crtc)
6337                         return;
6338
6339                 I915_STATE_WARN(!crtc->state->active,
6340                       "connector is active, but attached crtc isn't\n");
6341
6342                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6343                         return;
6344
6345                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6346                         "atomic encoder doesn't match attached encoder\n");
6347
6348                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6349                         "attached encoder crtc differs from connector crtc\n");
6350         } else {
6351                 I915_STATE_WARN(crtc && crtc->state->active,
6352                         "attached crtc is active, but connector isn't\n");
6353                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6354                         "best encoder set without crtc!\n");
6355         }
6356 }
6357
6358 int intel_connector_init(struct intel_connector *connector)
6359 {
6360         drm_atomic_helper_connector_reset(&connector->base);
6361
6362         if (!connector->base.state)
6363                 return -ENOMEM;
6364
6365         return 0;
6366 }
6367
6368 struct intel_connector *intel_connector_alloc(void)
6369 {
6370         struct intel_connector *connector;
6371
6372         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6373         if (!connector)
6374                 return NULL;
6375
6376         if (intel_connector_init(connector) < 0) {
6377                 kfree(connector);
6378                 return NULL;
6379         }
6380
6381         return connector;
6382 }
6383
6384 /* Simple connector->get_hw_state implementation for encoders that support only
6385  * one connector and no cloning and hence the encoder state determines the state
6386  * of the connector. */
6387 bool intel_connector_get_hw_state(struct intel_connector *connector)
6388 {
6389         enum pipe pipe = 0;
6390         struct intel_encoder *encoder = connector->encoder;
6391
6392         return encoder->get_hw_state(encoder, &pipe);
6393 }
6394
6395 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6396 {
6397         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6398                 return crtc_state->fdi_lanes;
6399
6400         return 0;
6401 }
6402
6403 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6404                                      struct intel_crtc_state *pipe_config)
6405 {
6406         struct drm_atomic_state *state = pipe_config->base.state;
6407         struct intel_crtc *other_crtc;
6408         struct intel_crtc_state *other_crtc_state;
6409
6410         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6411                       pipe_name(pipe), pipe_config->fdi_lanes);
6412         if (pipe_config->fdi_lanes > 4) {
6413                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6414                               pipe_name(pipe), pipe_config->fdi_lanes);
6415                 return -EINVAL;
6416         }
6417
6418         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6419                 if (pipe_config->fdi_lanes > 2) {
6420                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6421                                       pipe_config->fdi_lanes);
6422                         return -EINVAL;
6423                 } else {
6424                         return 0;
6425                 }
6426         }
6427
6428         if (INTEL_INFO(dev)->num_pipes == 2)
6429                 return 0;
6430
6431         /* Ivybridge 3 pipe is really complicated */
6432         switch (pipe) {
6433         case PIPE_A:
6434                 return 0;
6435         case PIPE_B:
6436                 if (pipe_config->fdi_lanes <= 2)
6437                         return 0;
6438
6439                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6440                 other_crtc_state =
6441                         intel_atomic_get_crtc_state(state, other_crtc);
6442                 if (IS_ERR(other_crtc_state))
6443                         return PTR_ERR(other_crtc_state);
6444
6445                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6446                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6447                                       pipe_name(pipe), pipe_config->fdi_lanes);
6448                         return -EINVAL;
6449                 }
6450                 return 0;
6451         case PIPE_C:
6452                 if (pipe_config->fdi_lanes > 2) {
6453                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6454                                       pipe_name(pipe), pipe_config->fdi_lanes);
6455                         return -EINVAL;
6456                 }
6457
6458                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6459                 other_crtc_state =
6460                         intel_atomic_get_crtc_state(state, other_crtc);
6461                 if (IS_ERR(other_crtc_state))
6462                         return PTR_ERR(other_crtc_state);
6463
6464                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6465                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6466                         return -EINVAL;
6467                 }
6468                 return 0;
6469         default:
6470                 BUG();
6471         }
6472 }
6473
6474 #define RETRY 1
6475 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6476                                        struct intel_crtc_state *pipe_config)
6477 {
6478         struct drm_device *dev = intel_crtc->base.dev;
6479         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6480         int lane, link_bw, fdi_dotclock, ret;
6481         bool needs_recompute = false;
6482
6483 retry:
6484         /* FDI is a binary signal running at ~2.7GHz, encoding
6485          * each output octet as 10 bits. The actual frequency
6486          * is stored as a divider into a 100MHz clock, and the
6487          * mode pixel clock is stored in units of 1KHz.
6488          * Hence the bw of each lane in terms of the mode signal
6489          * is:
6490          */
6491         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6492
6493         fdi_dotclock = adjusted_mode->crtc_clock;
6494
6495         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6496                                            pipe_config->pipe_bpp);
6497
6498         pipe_config->fdi_lanes = lane;
6499
6500         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6501                                link_bw, &pipe_config->fdi_m_n);
6502
6503         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6504         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6505                 pipe_config->pipe_bpp -= 2*3;
6506                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6507                               pipe_config->pipe_bpp);
6508                 needs_recompute = true;
6509                 pipe_config->bw_constrained = true;
6510
6511                 goto retry;
6512         }
6513
6514         if (needs_recompute)
6515                 return RETRY;
6516
6517         return ret;
6518 }
6519
6520 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6521                                      struct intel_crtc_state *pipe_config)
6522 {
6523         if (pipe_config->pipe_bpp > 24)
6524                 return false;
6525
6526         /* HSW can handle pixel rate up to cdclk? */
6527         if (IS_HASWELL(dev_priv->dev))
6528                 return true;
6529
6530         /*
6531          * We compare against max which means we must take
6532          * the increased cdclk requirement into account when
6533          * calculating the new cdclk.
6534          *
6535          * Should measure whether using a lower cdclk w/o IPS
6536          */
6537         return ilk_pipe_pixel_rate(pipe_config) <=
6538                 dev_priv->max_cdclk_freq * 95 / 100;
6539 }
6540
6541 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6542                                    struct intel_crtc_state *pipe_config)
6543 {
6544         struct drm_device *dev = crtc->base.dev;
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546
6547         pipe_config->ips_enabled = i915.enable_ips &&
6548                 hsw_crtc_supports_ips(crtc) &&
6549                 pipe_config_supports_ips(dev_priv, pipe_config);
6550 }
6551
6552 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6553 {
6554         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6555
6556         /* GDG double wide on either pipe, otherwise pipe A only */
6557         return INTEL_INFO(dev_priv)->gen < 4 &&
6558                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6559 }
6560
6561 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6562                                      struct intel_crtc_state *pipe_config)
6563 {
6564         struct drm_device *dev = crtc->base.dev;
6565         struct drm_i915_private *dev_priv = dev->dev_private;
6566         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6567
6568         /* FIXME should check pixel clock limits on all platforms */
6569         if (INTEL_INFO(dev)->gen < 4) {
6570                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6571
6572                 /*
6573                  * Enable double wide mode when the dot clock
6574                  * is > 90% of the (display) core speed.
6575                  */
6576                 if (intel_crtc_supports_double_wide(crtc) &&
6577                     adjusted_mode->crtc_clock > clock_limit) {
6578                         clock_limit *= 2;
6579                         pipe_config->double_wide = true;
6580                 }
6581
6582                 if (adjusted_mode->crtc_clock > clock_limit) {
6583                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6584                                       adjusted_mode->crtc_clock, clock_limit,
6585                                       yesno(pipe_config->double_wide));
6586                         return -EINVAL;
6587                 }
6588         }
6589
6590         /*
6591          * Pipe horizontal size must be even in:
6592          * - DVO ganged mode
6593          * - LVDS dual channel mode
6594          * - Double wide pipe
6595          */
6596         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6597              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6598                 pipe_config->pipe_src_w &= ~1;
6599
6600         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6601          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6602          */
6603         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6604                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6605                 return -EINVAL;
6606
6607         if (HAS_IPS(dev))
6608                 hsw_compute_ips_config(crtc, pipe_config);
6609
6610         if (pipe_config->has_pch_encoder)
6611                 return ironlake_fdi_compute_config(crtc, pipe_config);
6612
6613         return 0;
6614 }
6615
6616 static int skylake_get_display_clock_speed(struct drm_device *dev)
6617 {
6618         struct drm_i915_private *dev_priv = to_i915(dev);
6619         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6620         uint32_t cdctl = I915_READ(CDCLK_CTL);
6621         uint32_t linkrate;
6622
6623         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6624                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6625
6626         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6627                 return 540000;
6628
6629         linkrate = (I915_READ(DPLL_CTRL1) &
6630                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6631
6632         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6633             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6634                 /* vco 8640 */
6635                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6636                 case CDCLK_FREQ_450_432:
6637                         return 432000;
6638                 case CDCLK_FREQ_337_308:
6639                         return 308570;
6640                 case CDCLK_FREQ_675_617:
6641                         return 617140;
6642                 default:
6643                         WARN(1, "Unknown cd freq selection\n");
6644                 }
6645         } else {
6646                 /* vco 8100 */
6647                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6648                 case CDCLK_FREQ_450_432:
6649                         return 450000;
6650                 case CDCLK_FREQ_337_308:
6651                         return 337500;
6652                 case CDCLK_FREQ_675_617:
6653                         return 675000;
6654                 default:
6655                         WARN(1, "Unknown cd freq selection\n");
6656                 }
6657         }
6658
6659         /* error case, do as if DPLL0 isn't enabled */
6660         return 24000;
6661 }
6662
6663 static int broxton_get_display_clock_speed(struct drm_device *dev)
6664 {
6665         struct drm_i915_private *dev_priv = to_i915(dev);
6666         uint32_t cdctl = I915_READ(CDCLK_CTL);
6667         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6668         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6669         int cdclk;
6670
6671         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6672                 return 19200;
6673
6674         cdclk = 19200 * pll_ratio / 2;
6675
6676         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6677         case BXT_CDCLK_CD2X_DIV_SEL_1:
6678                 return cdclk;  /* 576MHz or 624MHz */
6679         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6680                 return cdclk * 2 / 3; /* 384MHz */
6681         case BXT_CDCLK_CD2X_DIV_SEL_2:
6682                 return cdclk / 2; /* 288MHz */
6683         case BXT_CDCLK_CD2X_DIV_SEL_4:
6684                 return cdclk / 4; /* 144MHz */
6685         }
6686
6687         /* error case, do as if DE PLL isn't enabled */
6688         return 19200;
6689 }
6690
6691 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6692 {
6693         struct drm_i915_private *dev_priv = dev->dev_private;
6694         uint32_t lcpll = I915_READ(LCPLL_CTL);
6695         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6696
6697         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6698                 return 800000;
6699         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6700                 return 450000;
6701         else if (freq == LCPLL_CLK_FREQ_450)
6702                 return 450000;
6703         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6704                 return 540000;
6705         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6706                 return 337500;
6707         else
6708                 return 675000;
6709 }
6710
6711 static int haswell_get_display_clock_speed(struct drm_device *dev)
6712 {
6713         struct drm_i915_private *dev_priv = dev->dev_private;
6714         uint32_t lcpll = I915_READ(LCPLL_CTL);
6715         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6716
6717         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6718                 return 800000;
6719         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6720                 return 450000;
6721         else if (freq == LCPLL_CLK_FREQ_450)
6722                 return 450000;
6723         else if (IS_HSW_ULT(dev))
6724                 return 337500;
6725         else
6726                 return 540000;
6727 }
6728
6729 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6730 {
6731         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6732                                       CCK_DISPLAY_CLOCK_CONTROL);
6733 }
6734
6735 static int ilk_get_display_clock_speed(struct drm_device *dev)
6736 {
6737         return 450000;
6738 }
6739
6740 static int i945_get_display_clock_speed(struct drm_device *dev)
6741 {
6742         return 400000;
6743 }
6744
6745 static int i915_get_display_clock_speed(struct drm_device *dev)
6746 {
6747         return 333333;
6748 }
6749
6750 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6751 {
6752         return 200000;
6753 }
6754
6755 static int pnv_get_display_clock_speed(struct drm_device *dev)
6756 {
6757         u16 gcfgc = 0;
6758
6759         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6760
6761         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6762         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6763                 return 266667;
6764         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6765                 return 333333;
6766         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6767                 return 444444;
6768         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6769                 return 200000;
6770         default:
6771                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6772         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6773                 return 133333;
6774         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6775                 return 166667;
6776         }
6777 }
6778
6779 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6780 {
6781         u16 gcfgc = 0;
6782
6783         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6784
6785         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6786                 return 133333;
6787         else {
6788                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6789                 case GC_DISPLAY_CLOCK_333_MHZ:
6790                         return 333333;
6791                 default:
6792                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6793                         return 190000;
6794                 }
6795         }
6796 }
6797
6798 static int i865_get_display_clock_speed(struct drm_device *dev)
6799 {
6800         return 266667;
6801 }
6802
6803 static int i85x_get_display_clock_speed(struct drm_device *dev)
6804 {
6805         u16 hpllcc = 0;
6806
6807         /*
6808          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6809          * encoding is different :(
6810          * FIXME is this the right way to detect 852GM/852GMV?
6811          */
6812         if (dev->pdev->revision == 0x1)
6813                 return 133333;
6814
6815         pci_bus_read_config_word(dev->pdev->bus,
6816                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6817
6818         /* Assume that the hardware is in the high speed state.  This
6819          * should be the default.
6820          */
6821         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6822         case GC_CLOCK_133_200:
6823         case GC_CLOCK_133_200_2:
6824         case GC_CLOCK_100_200:
6825                 return 200000;
6826         case GC_CLOCK_166_250:
6827                 return 250000;
6828         case GC_CLOCK_100_133:
6829                 return 133333;
6830         case GC_CLOCK_133_266:
6831         case GC_CLOCK_133_266_2:
6832         case GC_CLOCK_166_266:
6833                 return 266667;
6834         }
6835
6836         /* Shouldn't happen */
6837         return 0;
6838 }
6839
6840 static int i830_get_display_clock_speed(struct drm_device *dev)
6841 {
6842         return 133333;
6843 }
6844
6845 static unsigned int intel_hpll_vco(struct drm_device *dev)
6846 {
6847         struct drm_i915_private *dev_priv = dev->dev_private;
6848         static const unsigned int blb_vco[8] = {
6849                 [0] = 3200000,
6850                 [1] = 4000000,
6851                 [2] = 5333333,
6852                 [3] = 4800000,
6853                 [4] = 6400000,
6854         };
6855         static const unsigned int pnv_vco[8] = {
6856                 [0] = 3200000,
6857                 [1] = 4000000,
6858                 [2] = 5333333,
6859                 [3] = 4800000,
6860                 [4] = 2666667,
6861         };
6862         static const unsigned int cl_vco[8] = {
6863                 [0] = 3200000,
6864                 [1] = 4000000,
6865                 [2] = 5333333,
6866                 [3] = 6400000,
6867                 [4] = 3333333,
6868                 [5] = 3566667,
6869                 [6] = 4266667,
6870         };
6871         static const unsigned int elk_vco[8] = {
6872                 [0] = 3200000,
6873                 [1] = 4000000,
6874                 [2] = 5333333,
6875                 [3] = 4800000,
6876         };
6877         static const unsigned int ctg_vco[8] = {
6878                 [0] = 3200000,
6879                 [1] = 4000000,
6880                 [2] = 5333333,
6881                 [3] = 6400000,
6882                 [4] = 2666667,
6883                 [5] = 4266667,
6884         };
6885         const unsigned int *vco_table;
6886         unsigned int vco;
6887         uint8_t tmp = 0;
6888
6889         /* FIXME other chipsets? */
6890         if (IS_GM45(dev))
6891                 vco_table = ctg_vco;
6892         else if (IS_G4X(dev))
6893                 vco_table = elk_vco;
6894         else if (IS_CRESTLINE(dev))
6895                 vco_table = cl_vco;
6896         else if (IS_PINEVIEW(dev))
6897                 vco_table = pnv_vco;
6898         else if (IS_G33(dev))
6899                 vco_table = blb_vco;
6900         else
6901                 return 0;
6902
6903         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6904
6905         vco = vco_table[tmp & 0x7];
6906         if (vco == 0)
6907                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6908         else
6909                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6910
6911         return vco;
6912 }
6913
6914 static int gm45_get_display_clock_speed(struct drm_device *dev)
6915 {
6916         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6917         uint16_t tmp = 0;
6918
6919         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6920
6921         cdclk_sel = (tmp >> 12) & 0x1;
6922
6923         switch (vco) {
6924         case 2666667:
6925         case 4000000:
6926         case 5333333:
6927                 return cdclk_sel ? 333333 : 222222;
6928         case 3200000:
6929                 return cdclk_sel ? 320000 : 228571;
6930         default:
6931                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6932                 return 222222;
6933         }
6934 }
6935
6936 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6937 {
6938         static const uint8_t div_3200[] = { 16, 10,  8 };
6939         static const uint8_t div_4000[] = { 20, 12, 10 };
6940         static const uint8_t div_5333[] = { 24, 16, 14 };
6941         const uint8_t *div_table;
6942         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6943         uint16_t tmp = 0;
6944
6945         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6946
6947         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6948
6949         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6950                 goto fail;
6951
6952         switch (vco) {
6953         case 3200000:
6954                 div_table = div_3200;
6955                 break;
6956         case 4000000:
6957                 div_table = div_4000;
6958                 break;
6959         case 5333333:
6960                 div_table = div_5333;
6961                 break;
6962         default:
6963                 goto fail;
6964         }
6965
6966         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6967
6968 fail:
6969         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6970         return 200000;
6971 }
6972
6973 static int g33_get_display_clock_speed(struct drm_device *dev)
6974 {
6975         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6976         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6977         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6978         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6979         const uint8_t *div_table;
6980         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6981         uint16_t tmp = 0;
6982
6983         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6984
6985         cdclk_sel = (tmp >> 4) & 0x7;
6986
6987         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6988                 goto fail;
6989
6990         switch (vco) {
6991         case 3200000:
6992                 div_table = div_3200;
6993                 break;
6994         case 4000000:
6995                 div_table = div_4000;
6996                 break;
6997         case 4800000:
6998                 div_table = div_4800;
6999                 break;
7000         case 5333333:
7001                 div_table = div_5333;
7002                 break;
7003         default:
7004                 goto fail;
7005         }
7006
7007         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7008
7009 fail:
7010         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7011         return 190476;
7012 }
7013
7014 static void
7015 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7016 {
7017         while (*num > DATA_LINK_M_N_MASK ||
7018                *den > DATA_LINK_M_N_MASK) {
7019                 *num >>= 1;
7020                 *den >>= 1;
7021         }
7022 }
7023
7024 static void compute_m_n(unsigned int m, unsigned int n,
7025                         uint32_t *ret_m, uint32_t *ret_n)
7026 {
7027         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7028         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7029         intel_reduce_m_n_ratio(ret_m, ret_n);
7030 }
7031
7032 void
7033 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7034                        int pixel_clock, int link_clock,
7035                        struct intel_link_m_n *m_n)
7036 {
7037         m_n->tu = 64;
7038
7039         compute_m_n(bits_per_pixel * pixel_clock,
7040                     link_clock * nlanes * 8,
7041                     &m_n->gmch_m, &m_n->gmch_n);
7042
7043         compute_m_n(pixel_clock, link_clock,
7044                     &m_n->link_m, &m_n->link_n);
7045 }
7046
7047 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7048 {
7049         if (i915.panel_use_ssc >= 0)
7050                 return i915.panel_use_ssc != 0;
7051         return dev_priv->vbt.lvds_use_ssc
7052                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7053 }
7054
7055 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7056                            int num_connectors)
7057 {
7058         struct drm_device *dev = crtc_state->base.crtc->dev;
7059         struct drm_i915_private *dev_priv = dev->dev_private;
7060         int refclk;
7061
7062         WARN_ON(!crtc_state->base.state);
7063
7064         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7065                 refclk = 100000;
7066         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7067             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7068                 refclk = dev_priv->vbt.lvds_ssc_freq;
7069                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7070         } else if (!IS_GEN2(dev)) {
7071                 refclk = 96000;
7072         } else {
7073                 refclk = 48000;
7074         }
7075
7076         return refclk;
7077 }
7078
7079 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7080 {
7081         return (1 << dpll->n) << 16 | dpll->m2;
7082 }
7083
7084 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7085 {
7086         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7087 }
7088
7089 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7090                                      struct intel_crtc_state *crtc_state,
7091                                      intel_clock_t *reduced_clock)
7092 {
7093         struct drm_device *dev = crtc->base.dev;
7094         u32 fp, fp2 = 0;
7095
7096         if (IS_PINEVIEW(dev)) {
7097                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7098                 if (reduced_clock)
7099                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7100         } else {
7101                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7102                 if (reduced_clock)
7103                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7104         }
7105
7106         crtc_state->dpll_hw_state.fp0 = fp;
7107
7108         crtc->lowfreq_avail = false;
7109         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7110             reduced_clock) {
7111                 crtc_state->dpll_hw_state.fp1 = fp2;
7112                 crtc->lowfreq_avail = true;
7113         } else {
7114                 crtc_state->dpll_hw_state.fp1 = fp;
7115         }
7116 }
7117
7118 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7119                 pipe)
7120 {
7121         u32 reg_val;
7122
7123         /*
7124          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7125          * and set it to a reasonable value instead.
7126          */
7127         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7128         reg_val &= 0xffffff00;
7129         reg_val |= 0x00000030;
7130         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7131
7132         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7133         reg_val &= 0x8cffffff;
7134         reg_val = 0x8c000000;
7135         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7136
7137         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7138         reg_val &= 0xffffff00;
7139         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7140
7141         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7142         reg_val &= 0x00ffffff;
7143         reg_val |= 0xb0000000;
7144         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7145 }
7146
7147 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7148                                          struct intel_link_m_n *m_n)
7149 {
7150         struct drm_device *dev = crtc->base.dev;
7151         struct drm_i915_private *dev_priv = dev->dev_private;
7152         int pipe = crtc->pipe;
7153
7154         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7155         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7156         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7157         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7158 }
7159
7160 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7161                                          struct intel_link_m_n *m_n,
7162                                          struct intel_link_m_n *m2_n2)
7163 {
7164         struct drm_device *dev = crtc->base.dev;
7165         struct drm_i915_private *dev_priv = dev->dev_private;
7166         int pipe = crtc->pipe;
7167         enum transcoder transcoder = crtc->config->cpu_transcoder;
7168
7169         if (INTEL_INFO(dev)->gen >= 5) {
7170                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7171                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7172                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7173                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7174                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7175                  * for gen < 8) and if DRRS is supported (to make sure the
7176                  * registers are not unnecessarily accessed).
7177                  */
7178                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7179                         crtc->config->has_drrs) {
7180                         I915_WRITE(PIPE_DATA_M2(transcoder),
7181                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7182                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7183                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7184                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7185                 }
7186         } else {
7187                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7188                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7189                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7190                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7191         }
7192 }
7193
7194 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7195 {
7196         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7197
7198         if (m_n == M1_N1) {
7199                 dp_m_n = &crtc->config->dp_m_n;
7200                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7201         } else if (m_n == M2_N2) {
7202
7203                 /*
7204                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7205                  * needs to be programmed into M1_N1.
7206                  */
7207                 dp_m_n = &crtc->config->dp_m2_n2;
7208         } else {
7209                 DRM_ERROR("Unsupported divider value\n");
7210                 return;
7211         }
7212
7213         if (crtc->config->has_pch_encoder)
7214                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7215         else
7216                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7217 }
7218
7219 static void vlv_compute_dpll(struct intel_crtc *crtc,
7220                              struct intel_crtc_state *pipe_config)
7221 {
7222         u32 dpll, dpll_md;
7223
7224         /*
7225          * Enable DPIO clock input. We should never disable the reference
7226          * clock for pipe B, since VGA hotplug / manual detection depends
7227          * on it.
7228          */
7229         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7230                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7231         /* We should never disable this, set it here for state tracking */
7232         if (crtc->pipe == PIPE_B)
7233                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7234         dpll |= DPLL_VCO_ENABLE;
7235         pipe_config->dpll_hw_state.dpll = dpll;
7236
7237         dpll_md = (pipe_config->pixel_multiplier - 1)
7238                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7239         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7240 }
7241
7242 static void vlv_prepare_pll(struct intel_crtc *crtc,
7243                             const struct intel_crtc_state *pipe_config)
7244 {
7245         struct drm_device *dev = crtc->base.dev;
7246         struct drm_i915_private *dev_priv = dev->dev_private;
7247         int pipe = crtc->pipe;
7248         u32 mdiv;
7249         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7250         u32 coreclk, reg_val;
7251
7252         mutex_lock(&dev_priv->sb_lock);
7253
7254         bestn = pipe_config->dpll.n;
7255         bestm1 = pipe_config->dpll.m1;
7256         bestm2 = pipe_config->dpll.m2;
7257         bestp1 = pipe_config->dpll.p1;
7258         bestp2 = pipe_config->dpll.p2;
7259
7260         /* See eDP HDMI DPIO driver vbios notes doc */
7261
7262         /* PLL B needs special handling */
7263         if (pipe == PIPE_B)
7264                 vlv_pllb_recal_opamp(dev_priv, pipe);
7265
7266         /* Set up Tx target for periodic Rcomp update */
7267         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7268
7269         /* Disable target IRef on PLL */
7270         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7271         reg_val &= 0x00ffffff;
7272         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7273
7274         /* Disable fast lock */
7275         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7276
7277         /* Set idtafcrecal before PLL is enabled */
7278         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7279         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7280         mdiv |= ((bestn << DPIO_N_SHIFT));
7281         mdiv |= (1 << DPIO_K_SHIFT);
7282
7283         /*
7284          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7285          * but we don't support that).
7286          * Note: don't use the DAC post divider as it seems unstable.
7287          */
7288         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7289         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7290
7291         mdiv |= DPIO_ENABLE_CALIBRATION;
7292         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7293
7294         /* Set HBR and RBR LPF coefficients */
7295         if (pipe_config->port_clock == 162000 ||
7296             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7297             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7298                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7299                                  0x009f0003);
7300         else
7301                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7302                                  0x00d0000f);
7303
7304         if (pipe_config->has_dp_encoder) {
7305                 /* Use SSC source */
7306                 if (pipe == PIPE_A)
7307                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7308                                          0x0df40000);
7309                 else
7310                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7311                                          0x0df70000);
7312         } else { /* HDMI or VGA */
7313                 /* Use bend source */
7314                 if (pipe == PIPE_A)
7315                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7316                                          0x0df70000);
7317                 else
7318                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319                                          0x0df40000);
7320         }
7321
7322         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7323         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7324         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7325             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7326                 coreclk |= 0x01000000;
7327         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7328
7329         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7330         mutex_unlock(&dev_priv->sb_lock);
7331 }
7332
7333 static void chv_compute_dpll(struct intel_crtc *crtc,
7334                              struct intel_crtc_state *pipe_config)
7335 {
7336         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7337                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7338                 DPLL_VCO_ENABLE;
7339         if (crtc->pipe != PIPE_A)
7340                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7341
7342         pipe_config->dpll_hw_state.dpll_md =
7343                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7344 }
7345
7346 static void chv_prepare_pll(struct intel_crtc *crtc,
7347                             const struct intel_crtc_state *pipe_config)
7348 {
7349         struct drm_device *dev = crtc->base.dev;
7350         struct drm_i915_private *dev_priv = dev->dev_private;
7351         int pipe = crtc->pipe;
7352         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7353         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7354         u32 loopfilter, tribuf_calcntr;
7355         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7356         u32 dpio_val;
7357         int vco;
7358
7359         bestn = pipe_config->dpll.n;
7360         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7361         bestm1 = pipe_config->dpll.m1;
7362         bestm2 = pipe_config->dpll.m2 >> 22;
7363         bestp1 = pipe_config->dpll.p1;
7364         bestp2 = pipe_config->dpll.p2;
7365         vco = pipe_config->dpll.vco;
7366         dpio_val = 0;
7367         loopfilter = 0;
7368
7369         /*
7370          * Enable Refclk and SSC
7371          */
7372         I915_WRITE(dpll_reg,
7373                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7374
7375         mutex_lock(&dev_priv->sb_lock);
7376
7377         /* p1 and p2 divider */
7378         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7379                         5 << DPIO_CHV_S1_DIV_SHIFT |
7380                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7381                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7382                         1 << DPIO_CHV_K_DIV_SHIFT);
7383
7384         /* Feedback post-divider - m2 */
7385         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7386
7387         /* Feedback refclk divider - n and m1 */
7388         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7389                         DPIO_CHV_M1_DIV_BY_2 |
7390                         1 << DPIO_CHV_N_DIV_SHIFT);
7391
7392         /* M2 fraction division */
7393         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7394
7395         /* M2 fraction division enable */
7396         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7397         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7398         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7399         if (bestm2_frac)
7400                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7401         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7402
7403         /* Program digital lock detect threshold */
7404         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7405         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7406                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7407         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7408         if (!bestm2_frac)
7409                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7410         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7411
7412         /* Loop filter */
7413         if (vco == 5400000) {
7414                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7415                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7416                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7417                 tribuf_calcntr = 0x9;
7418         } else if (vco <= 6200000) {
7419                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7420                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7421                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7422                 tribuf_calcntr = 0x9;
7423         } else if (vco <= 6480000) {
7424                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7425                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7426                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7427                 tribuf_calcntr = 0x8;
7428         } else {
7429                 /* Not supported. Apply the same limits as in the max case */
7430                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7431                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7432                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433                 tribuf_calcntr = 0;
7434         }
7435         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7436
7437         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7438         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7439         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7440         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7441
7442         /* AFC Recal */
7443         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7444                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7445                         DPIO_AFC_RECAL);
7446
7447         mutex_unlock(&dev_priv->sb_lock);
7448 }
7449
7450 /**
7451  * vlv_force_pll_on - forcibly enable just the PLL
7452  * @dev_priv: i915 private structure
7453  * @pipe: pipe PLL to enable
7454  * @dpll: PLL configuration
7455  *
7456  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7457  * in cases where we need the PLL enabled even when @pipe is not going to
7458  * be enabled.
7459  */
7460 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7461                      const struct dpll *dpll)
7462 {
7463         struct intel_crtc *crtc =
7464                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7465         struct intel_crtc_state *pipe_config;
7466
7467         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7468         if (!pipe_config)
7469                 return -ENOMEM;
7470
7471         pipe_config->base.crtc = &crtc->base;
7472         pipe_config->pixel_multiplier = 1;
7473         pipe_config->dpll = *dpll;
7474
7475         if (IS_CHERRYVIEW(dev)) {
7476                 chv_compute_dpll(crtc, pipe_config);
7477                 chv_prepare_pll(crtc, pipe_config);
7478                 chv_enable_pll(crtc, pipe_config);
7479         } else {
7480                 vlv_compute_dpll(crtc, pipe_config);
7481                 vlv_prepare_pll(crtc, pipe_config);
7482                 vlv_enable_pll(crtc, pipe_config);
7483         }
7484
7485         kfree(pipe_config);
7486
7487         return 0;
7488 }
7489
7490 /**
7491  * vlv_force_pll_off - forcibly disable just the PLL
7492  * @dev_priv: i915 private structure
7493  * @pipe: pipe PLL to disable
7494  *
7495  * Disable the PLL for @pipe. To be used in cases where we need
7496  * the PLL enabled even when @pipe is not going to be enabled.
7497  */
7498 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7499 {
7500         if (IS_CHERRYVIEW(dev))
7501                 chv_disable_pll(to_i915(dev), pipe);
7502         else
7503                 vlv_disable_pll(to_i915(dev), pipe);
7504 }
7505
7506 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7507                               struct intel_crtc_state *crtc_state,
7508                               intel_clock_t *reduced_clock,
7509                               int num_connectors)
7510 {
7511         struct drm_device *dev = crtc->base.dev;
7512         struct drm_i915_private *dev_priv = dev->dev_private;
7513         u32 dpll;
7514         bool is_sdvo;
7515         struct dpll *clock = &crtc_state->dpll;
7516
7517         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7518
7519         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7520                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7521
7522         dpll = DPLL_VGA_MODE_DIS;
7523
7524         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7525                 dpll |= DPLLB_MODE_LVDS;
7526         else
7527                 dpll |= DPLLB_MODE_DAC_SERIAL;
7528
7529         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7530                 dpll |= (crtc_state->pixel_multiplier - 1)
7531                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7532         }
7533
7534         if (is_sdvo)
7535                 dpll |= DPLL_SDVO_HIGH_SPEED;
7536
7537         if (crtc_state->has_dp_encoder)
7538                 dpll |= DPLL_SDVO_HIGH_SPEED;
7539
7540         /* compute bitmask from p1 value */
7541         if (IS_PINEVIEW(dev))
7542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7543         else {
7544                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7545                 if (IS_G4X(dev) && reduced_clock)
7546                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7547         }
7548         switch (clock->p2) {
7549         case 5:
7550                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7551                 break;
7552         case 7:
7553                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7554                 break;
7555         case 10:
7556                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7557                 break;
7558         case 14:
7559                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7560                 break;
7561         }
7562         if (INTEL_INFO(dev)->gen >= 4)
7563                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7564
7565         if (crtc_state->sdvo_tv_clock)
7566                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7567         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7568                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7569                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7570         else
7571                 dpll |= PLL_REF_INPUT_DREFCLK;
7572
7573         dpll |= DPLL_VCO_ENABLE;
7574         crtc_state->dpll_hw_state.dpll = dpll;
7575
7576         if (INTEL_INFO(dev)->gen >= 4) {
7577                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7578                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7579                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7580         }
7581 }
7582
7583 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7584                               struct intel_crtc_state *crtc_state,
7585                               intel_clock_t *reduced_clock,
7586                               int num_connectors)
7587 {
7588         struct drm_device *dev = crtc->base.dev;
7589         struct drm_i915_private *dev_priv = dev->dev_private;
7590         u32 dpll;
7591         struct dpll *clock = &crtc_state->dpll;
7592
7593         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7594
7595         dpll = DPLL_VGA_MODE_DIS;
7596
7597         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7598                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7599         } else {
7600                 if (clock->p1 == 2)
7601                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7602                 else
7603                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7604                 if (clock->p2 == 4)
7605                         dpll |= PLL_P2_DIVIDE_BY_4;
7606         }
7607
7608         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7609                 dpll |= DPLL_DVO_2X_MODE;
7610
7611         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7612                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7613                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7614         else
7615                 dpll |= PLL_REF_INPUT_DREFCLK;
7616
7617         dpll |= DPLL_VCO_ENABLE;
7618         crtc_state->dpll_hw_state.dpll = dpll;
7619 }
7620
7621 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7622 {
7623         struct drm_device *dev = intel_crtc->base.dev;
7624         struct drm_i915_private *dev_priv = dev->dev_private;
7625         enum pipe pipe = intel_crtc->pipe;
7626         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7627         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7628         uint32_t crtc_vtotal, crtc_vblank_end;
7629         int vsyncshift = 0;
7630
7631         /* We need to be careful not to changed the adjusted mode, for otherwise
7632          * the hw state checker will get angry at the mismatch. */
7633         crtc_vtotal = adjusted_mode->crtc_vtotal;
7634         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7635
7636         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7637                 /* the chip adds 2 halflines automatically */
7638                 crtc_vtotal -= 1;
7639                 crtc_vblank_end -= 1;
7640
7641                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7642                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7643                 else
7644                         vsyncshift = adjusted_mode->crtc_hsync_start -
7645                                 adjusted_mode->crtc_htotal / 2;
7646                 if (vsyncshift < 0)
7647                         vsyncshift += adjusted_mode->crtc_htotal;
7648         }
7649
7650         if (INTEL_INFO(dev)->gen > 3)
7651                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7652
7653         I915_WRITE(HTOTAL(cpu_transcoder),
7654                    (adjusted_mode->crtc_hdisplay - 1) |
7655                    ((adjusted_mode->crtc_htotal - 1) << 16));
7656         I915_WRITE(HBLANK(cpu_transcoder),
7657                    (adjusted_mode->crtc_hblank_start - 1) |
7658                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7659         I915_WRITE(HSYNC(cpu_transcoder),
7660                    (adjusted_mode->crtc_hsync_start - 1) |
7661                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7662
7663         I915_WRITE(VTOTAL(cpu_transcoder),
7664                    (adjusted_mode->crtc_vdisplay - 1) |
7665                    ((crtc_vtotal - 1) << 16));
7666         I915_WRITE(VBLANK(cpu_transcoder),
7667                    (adjusted_mode->crtc_vblank_start - 1) |
7668                    ((crtc_vblank_end - 1) << 16));
7669         I915_WRITE(VSYNC(cpu_transcoder),
7670                    (adjusted_mode->crtc_vsync_start - 1) |
7671                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7672
7673         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7674          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7675          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7676          * bits. */
7677         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7678             (pipe == PIPE_B || pipe == PIPE_C))
7679                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7680
7681         /* pipesrc controls the size that is scaled from, which should
7682          * always be the user's requested size.
7683          */
7684         I915_WRITE(PIPESRC(pipe),
7685                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7686                    (intel_crtc->config->pipe_src_h - 1));
7687 }
7688
7689 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7690                                    struct intel_crtc_state *pipe_config)
7691 {
7692         struct drm_device *dev = crtc->base.dev;
7693         struct drm_i915_private *dev_priv = dev->dev_private;
7694         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7695         uint32_t tmp;
7696
7697         tmp = I915_READ(HTOTAL(cpu_transcoder));
7698         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7699         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7700         tmp = I915_READ(HBLANK(cpu_transcoder));
7701         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7702         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7703         tmp = I915_READ(HSYNC(cpu_transcoder));
7704         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7705         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7706
7707         tmp = I915_READ(VTOTAL(cpu_transcoder));
7708         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7709         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7710         tmp = I915_READ(VBLANK(cpu_transcoder));
7711         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7712         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7713         tmp = I915_READ(VSYNC(cpu_transcoder));
7714         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7715         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7716
7717         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7718                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7719                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7720                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7721         }
7722
7723         tmp = I915_READ(PIPESRC(crtc->pipe));
7724         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7725         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7726
7727         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7728         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7729 }
7730
7731 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7732                                  struct intel_crtc_state *pipe_config)
7733 {
7734         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7735         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7736         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7737         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7738
7739         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7740         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7741         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7742         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7743
7744         mode->flags = pipe_config->base.adjusted_mode.flags;
7745         mode->type = DRM_MODE_TYPE_DRIVER;
7746
7747         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7748         mode->flags |= pipe_config->base.adjusted_mode.flags;
7749
7750         mode->hsync = drm_mode_hsync(mode);
7751         mode->vrefresh = drm_mode_vrefresh(mode);
7752         drm_mode_set_name(mode);
7753 }
7754
7755 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7756 {
7757         struct drm_device *dev = intel_crtc->base.dev;
7758         struct drm_i915_private *dev_priv = dev->dev_private;
7759         uint32_t pipeconf;
7760
7761         pipeconf = 0;
7762
7763         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7764             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7765                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7766
7767         if (intel_crtc->config->double_wide)
7768                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7769
7770         /* only g4x and later have fancy bpc/dither controls */
7771         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7772                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7773                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7774                         pipeconf |= PIPECONF_DITHER_EN |
7775                                     PIPECONF_DITHER_TYPE_SP;
7776
7777                 switch (intel_crtc->config->pipe_bpp) {
7778                 case 18:
7779                         pipeconf |= PIPECONF_6BPC;
7780                         break;
7781                 case 24:
7782                         pipeconf |= PIPECONF_8BPC;
7783                         break;
7784                 case 30:
7785                         pipeconf |= PIPECONF_10BPC;
7786                         break;
7787                 default:
7788                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7789                         BUG();
7790                 }
7791         }
7792
7793         if (HAS_PIPE_CXSR(dev)) {
7794                 if (intel_crtc->lowfreq_avail) {
7795                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7796                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7797                 } else {
7798                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7799                 }
7800         }
7801
7802         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7803                 if (INTEL_INFO(dev)->gen < 4 ||
7804                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7805                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7806                 else
7807                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7808         } else
7809                 pipeconf |= PIPECONF_PROGRESSIVE;
7810
7811         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7812              intel_crtc->config->limited_color_range)
7813                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7814
7815         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7816         POSTING_READ(PIPECONF(intel_crtc->pipe));
7817 }
7818
7819 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7820                                    struct intel_crtc_state *crtc_state)
7821 {
7822         struct drm_device *dev = crtc->base.dev;
7823         struct drm_i915_private *dev_priv = dev->dev_private;
7824         int refclk, num_connectors = 0;
7825         intel_clock_t clock;
7826         bool ok;
7827         const intel_limit_t *limit;
7828         struct drm_atomic_state *state = crtc_state->base.state;
7829         struct drm_connector *connector;
7830         struct drm_connector_state *connector_state;
7831         int i;
7832
7833         memset(&crtc_state->dpll_hw_state, 0,
7834                sizeof(crtc_state->dpll_hw_state));
7835
7836         if (crtc_state->has_dsi_encoder)
7837                 return 0;
7838
7839         for_each_connector_in_state(state, connector, connector_state, i) {
7840                 if (connector_state->crtc == &crtc->base)
7841                         num_connectors++;
7842         }
7843
7844         if (!crtc_state->clock_set) {
7845                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7846
7847                 /*
7848                  * Returns a set of divisors for the desired target clock with
7849                  * the given refclk, or FALSE.  The returned values represent
7850                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7851                  * 2) / p1 / p2.
7852                  */
7853                 limit = intel_limit(crtc_state, refclk);
7854                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7855                                                  crtc_state->port_clock,
7856                                                  refclk, NULL, &clock);
7857                 if (!ok) {
7858                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7859                         return -EINVAL;
7860                 }
7861
7862                 /* Compat-code for transition, will disappear. */
7863                 crtc_state->dpll.n = clock.n;
7864                 crtc_state->dpll.m1 = clock.m1;
7865                 crtc_state->dpll.m2 = clock.m2;
7866                 crtc_state->dpll.p1 = clock.p1;
7867                 crtc_state->dpll.p2 = clock.p2;
7868         }
7869
7870         if (IS_GEN2(dev)) {
7871                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7872                                   num_connectors);
7873         } else if (IS_CHERRYVIEW(dev)) {
7874                 chv_compute_dpll(crtc, crtc_state);
7875         } else if (IS_VALLEYVIEW(dev)) {
7876                 vlv_compute_dpll(crtc, crtc_state);
7877         } else {
7878                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7879                                   num_connectors);
7880         }
7881
7882         return 0;
7883 }
7884
7885 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7886                                  struct intel_crtc_state *pipe_config)
7887 {
7888         struct drm_device *dev = crtc->base.dev;
7889         struct drm_i915_private *dev_priv = dev->dev_private;
7890         uint32_t tmp;
7891
7892         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7893                 return;
7894
7895         tmp = I915_READ(PFIT_CONTROL);
7896         if (!(tmp & PFIT_ENABLE))
7897                 return;
7898
7899         /* Check whether the pfit is attached to our pipe. */
7900         if (INTEL_INFO(dev)->gen < 4) {
7901                 if (crtc->pipe != PIPE_B)
7902                         return;
7903         } else {
7904                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7905                         return;
7906         }
7907
7908         pipe_config->gmch_pfit.control = tmp;
7909         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7910         if (INTEL_INFO(dev)->gen < 5)
7911                 pipe_config->gmch_pfit.lvds_border_bits =
7912                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7913 }
7914
7915 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7916                                struct intel_crtc_state *pipe_config)
7917 {
7918         struct drm_device *dev = crtc->base.dev;
7919         struct drm_i915_private *dev_priv = dev->dev_private;
7920         int pipe = pipe_config->cpu_transcoder;
7921         intel_clock_t clock;
7922         u32 mdiv;
7923         int refclk = 100000;
7924
7925         /* In case of MIPI DPLL will not even be used */
7926         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7927                 return;
7928
7929         mutex_lock(&dev_priv->sb_lock);
7930         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7931         mutex_unlock(&dev_priv->sb_lock);
7932
7933         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7934         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7935         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7936         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7937         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7938
7939         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7940 }
7941
7942 static void
7943 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7944                               struct intel_initial_plane_config *plane_config)
7945 {
7946         struct drm_device *dev = crtc->base.dev;
7947         struct drm_i915_private *dev_priv = dev->dev_private;
7948         u32 val, base, offset;
7949         int pipe = crtc->pipe, plane = crtc->plane;
7950         int fourcc, pixel_format;
7951         unsigned int aligned_height;
7952         struct drm_framebuffer *fb;
7953         struct intel_framebuffer *intel_fb;
7954
7955         val = I915_READ(DSPCNTR(plane));
7956         if (!(val & DISPLAY_PLANE_ENABLE))
7957                 return;
7958
7959         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7960         if (!intel_fb) {
7961                 DRM_DEBUG_KMS("failed to alloc fb\n");
7962                 return;
7963         }
7964
7965         fb = &intel_fb->base;
7966
7967         if (INTEL_INFO(dev)->gen >= 4) {
7968                 if (val & DISPPLANE_TILED) {
7969                         plane_config->tiling = I915_TILING_X;
7970                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7971                 }
7972         }
7973
7974         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7975         fourcc = i9xx_format_to_fourcc(pixel_format);
7976         fb->pixel_format = fourcc;
7977         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7978
7979         if (INTEL_INFO(dev)->gen >= 4) {
7980                 if (plane_config->tiling)
7981                         offset = I915_READ(DSPTILEOFF(plane));
7982                 else
7983                         offset = I915_READ(DSPLINOFF(plane));
7984                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7985         } else {
7986                 base = I915_READ(DSPADDR(plane));
7987         }
7988         plane_config->base = base;
7989
7990         val = I915_READ(PIPESRC(pipe));
7991         fb->width = ((val >> 16) & 0xfff) + 1;
7992         fb->height = ((val >> 0) & 0xfff) + 1;
7993
7994         val = I915_READ(DSPSTRIDE(pipe));
7995         fb->pitches[0] = val & 0xffffffc0;
7996
7997         aligned_height = intel_fb_align_height(dev, fb->height,
7998                                                fb->pixel_format,
7999                                                fb->modifier[0]);
8000
8001         plane_config->size = fb->pitches[0] * aligned_height;
8002
8003         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8004                       pipe_name(pipe), plane, fb->width, fb->height,
8005                       fb->bits_per_pixel, base, fb->pitches[0],
8006                       plane_config->size);
8007
8008         plane_config->fb = intel_fb;
8009 }
8010
8011 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8012                                struct intel_crtc_state *pipe_config)
8013 {
8014         struct drm_device *dev = crtc->base.dev;
8015         struct drm_i915_private *dev_priv = dev->dev_private;
8016         int pipe = pipe_config->cpu_transcoder;
8017         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8018         intel_clock_t clock;
8019         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8020         int refclk = 100000;
8021
8022         mutex_lock(&dev_priv->sb_lock);
8023         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8024         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8025         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8026         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8027         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8028         mutex_unlock(&dev_priv->sb_lock);
8029
8030         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8031         clock.m2 = (pll_dw0 & 0xff) << 22;
8032         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8033                 clock.m2 |= pll_dw2 & 0x3fffff;
8034         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8035         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8036         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8037
8038         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8039 }
8040
8041 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8042                                  struct intel_crtc_state *pipe_config)
8043 {
8044         struct drm_device *dev = crtc->base.dev;
8045         struct drm_i915_private *dev_priv = dev->dev_private;
8046         enum intel_display_power_domain power_domain;
8047         uint32_t tmp;
8048         bool ret;
8049
8050         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8051         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8052                 return false;
8053
8054         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8055         pipe_config->shared_dpll = NULL;
8056
8057         ret = false;
8058
8059         tmp = I915_READ(PIPECONF(crtc->pipe));
8060         if (!(tmp & PIPECONF_ENABLE))
8061                 goto out;
8062
8063         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8064                 switch (tmp & PIPECONF_BPC_MASK) {
8065                 case PIPECONF_6BPC:
8066                         pipe_config->pipe_bpp = 18;
8067                         break;
8068                 case PIPECONF_8BPC:
8069                         pipe_config->pipe_bpp = 24;
8070                         break;
8071                 case PIPECONF_10BPC:
8072                         pipe_config->pipe_bpp = 30;
8073                         break;
8074                 default:
8075                         break;
8076                 }
8077         }
8078
8079         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8080             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8081                 pipe_config->limited_color_range = true;
8082
8083         if (INTEL_INFO(dev)->gen < 4)
8084                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8085
8086         intel_get_pipe_timings(crtc, pipe_config);
8087
8088         i9xx_get_pfit_config(crtc, pipe_config);
8089
8090         if (INTEL_INFO(dev)->gen >= 4) {
8091                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8092                 pipe_config->pixel_multiplier =
8093                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8094                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8095                 pipe_config->dpll_hw_state.dpll_md = tmp;
8096         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8097                 tmp = I915_READ(DPLL(crtc->pipe));
8098                 pipe_config->pixel_multiplier =
8099                         ((tmp & SDVO_MULTIPLIER_MASK)
8100                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8101         } else {
8102                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8103                  * port and will be fixed up in the encoder->get_config
8104                  * function. */
8105                 pipe_config->pixel_multiplier = 1;
8106         }
8107         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8108         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8109                 /*
8110                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8111                  * on 830. Filter it out here so that we don't
8112                  * report errors due to that.
8113                  */
8114                 if (IS_I830(dev))
8115                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8116
8117                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8118                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8119         } else {
8120                 /* Mask out read-only status bits. */
8121                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8122                                                      DPLL_PORTC_READY_MASK |
8123                                                      DPLL_PORTB_READY_MASK);
8124         }
8125
8126         if (IS_CHERRYVIEW(dev))
8127                 chv_crtc_clock_get(crtc, pipe_config);
8128         else if (IS_VALLEYVIEW(dev))
8129                 vlv_crtc_clock_get(crtc, pipe_config);
8130         else
8131                 i9xx_crtc_clock_get(crtc, pipe_config);
8132
8133         /*
8134          * Normally the dotclock is filled in by the encoder .get_config()
8135          * but in case the pipe is enabled w/o any ports we need a sane
8136          * default.
8137          */
8138         pipe_config->base.adjusted_mode.crtc_clock =
8139                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8140
8141         ret = true;
8142
8143 out:
8144         intel_display_power_put(dev_priv, power_domain);
8145
8146         return ret;
8147 }
8148
8149 static void ironlake_init_pch_refclk(struct drm_device *dev)
8150 {
8151         struct drm_i915_private *dev_priv = dev->dev_private;
8152         struct intel_encoder *encoder;
8153         u32 val, final;
8154         bool has_lvds = false;
8155         bool has_cpu_edp = false;
8156         bool has_panel = false;
8157         bool has_ck505 = false;
8158         bool can_ssc = false;
8159
8160         /* We need to take the global config into account */
8161         for_each_intel_encoder(dev, encoder) {
8162                 switch (encoder->type) {
8163                 case INTEL_OUTPUT_LVDS:
8164                         has_panel = true;
8165                         has_lvds = true;
8166                         break;
8167                 case INTEL_OUTPUT_EDP:
8168                         has_panel = true;
8169                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8170                                 has_cpu_edp = true;
8171                         break;
8172                 default:
8173                         break;
8174                 }
8175         }
8176
8177         if (HAS_PCH_IBX(dev)) {
8178                 has_ck505 = dev_priv->vbt.display_clock_mode;
8179                 can_ssc = has_ck505;
8180         } else {
8181                 has_ck505 = false;
8182                 can_ssc = true;
8183         }
8184
8185         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8186                       has_panel, has_lvds, has_ck505);
8187
8188         /* Ironlake: try to setup display ref clock before DPLL
8189          * enabling. This is only under driver's control after
8190          * PCH B stepping, previous chipset stepping should be
8191          * ignoring this setting.
8192          */
8193         val = I915_READ(PCH_DREF_CONTROL);
8194
8195         /* As we must carefully and slowly disable/enable each source in turn,
8196          * compute the final state we want first and check if we need to
8197          * make any changes at all.
8198          */
8199         final = val;
8200         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8201         if (has_ck505)
8202                 final |= DREF_NONSPREAD_CK505_ENABLE;
8203         else
8204                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8205
8206         final &= ~DREF_SSC_SOURCE_MASK;
8207         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8208         final &= ~DREF_SSC1_ENABLE;
8209
8210         if (has_panel) {
8211                 final |= DREF_SSC_SOURCE_ENABLE;
8212
8213                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8214                         final |= DREF_SSC1_ENABLE;
8215
8216                 if (has_cpu_edp) {
8217                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8218                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8219                         else
8220                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8221                 } else
8222                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8223         } else {
8224                 final |= DREF_SSC_SOURCE_DISABLE;
8225                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8226         }
8227
8228         if (final == val)
8229                 return;
8230
8231         /* Always enable nonspread source */
8232         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8233
8234         if (has_ck505)
8235                 val |= DREF_NONSPREAD_CK505_ENABLE;
8236         else
8237                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8238
8239         if (has_panel) {
8240                 val &= ~DREF_SSC_SOURCE_MASK;
8241                 val |= DREF_SSC_SOURCE_ENABLE;
8242
8243                 /* SSC must be turned on before enabling the CPU output  */
8244                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8245                         DRM_DEBUG_KMS("Using SSC on panel\n");
8246                         val |= DREF_SSC1_ENABLE;
8247                 } else
8248                         val &= ~DREF_SSC1_ENABLE;
8249
8250                 /* Get SSC going before enabling the outputs */
8251                 I915_WRITE(PCH_DREF_CONTROL, val);
8252                 POSTING_READ(PCH_DREF_CONTROL);
8253                 udelay(200);
8254
8255                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8256
8257                 /* Enable CPU source on CPU attached eDP */
8258                 if (has_cpu_edp) {
8259                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8260                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8261                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8262                         } else
8263                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8264                 } else
8265                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8266
8267                 I915_WRITE(PCH_DREF_CONTROL, val);
8268                 POSTING_READ(PCH_DREF_CONTROL);
8269                 udelay(200);
8270         } else {
8271                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8272
8273                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8274
8275                 /* Turn off CPU output */
8276                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8277
8278                 I915_WRITE(PCH_DREF_CONTROL, val);
8279                 POSTING_READ(PCH_DREF_CONTROL);
8280                 udelay(200);
8281
8282                 /* Turn off the SSC source */
8283                 val &= ~DREF_SSC_SOURCE_MASK;
8284                 val |= DREF_SSC_SOURCE_DISABLE;
8285
8286                 /* Turn off SSC1 */
8287                 val &= ~DREF_SSC1_ENABLE;
8288
8289                 I915_WRITE(PCH_DREF_CONTROL, val);
8290                 POSTING_READ(PCH_DREF_CONTROL);
8291                 udelay(200);
8292         }
8293
8294         BUG_ON(val != final);
8295 }
8296
8297 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8298 {
8299         uint32_t tmp;
8300
8301         tmp = I915_READ(SOUTH_CHICKEN2);
8302         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8303         I915_WRITE(SOUTH_CHICKEN2, tmp);
8304
8305         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8306                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8307                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8308
8309         tmp = I915_READ(SOUTH_CHICKEN2);
8310         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8311         I915_WRITE(SOUTH_CHICKEN2, tmp);
8312
8313         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8314                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8315                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8316 }
8317
8318 /* WaMPhyProgramming:hsw */
8319 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8320 {
8321         uint32_t tmp;
8322
8323         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8324         tmp &= ~(0xFF << 24);
8325         tmp |= (0x12 << 24);
8326         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8327
8328         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8329         tmp |= (1 << 11);
8330         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8331
8332         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8333         tmp |= (1 << 11);
8334         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8335
8336         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8337         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8338         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8339
8340         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8341         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8342         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8343
8344         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8345         tmp &= ~(7 << 13);
8346         tmp |= (5 << 13);
8347         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8348
8349         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8350         tmp &= ~(7 << 13);
8351         tmp |= (5 << 13);
8352         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8355         tmp &= ~0xFF;
8356         tmp |= 0x1C;
8357         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8358
8359         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8360         tmp &= ~0xFF;
8361         tmp |= 0x1C;
8362         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8363
8364         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8365         tmp &= ~(0xFF << 16);
8366         tmp |= (0x1C << 16);
8367         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8368
8369         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8370         tmp &= ~(0xFF << 16);
8371         tmp |= (0x1C << 16);
8372         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8373
8374         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8375         tmp |= (1 << 27);
8376         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8377
8378         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8379         tmp |= (1 << 27);
8380         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8381
8382         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8383         tmp &= ~(0xF << 28);
8384         tmp |= (4 << 28);
8385         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8386
8387         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8388         tmp &= ~(0xF << 28);
8389         tmp |= (4 << 28);
8390         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8391 }
8392
8393 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8394  * Programming" based on the parameters passed:
8395  * - Sequence to enable CLKOUT_DP
8396  * - Sequence to enable CLKOUT_DP without spread
8397  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8398  */
8399 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8400                                  bool with_fdi)
8401 {
8402         struct drm_i915_private *dev_priv = dev->dev_private;
8403         uint32_t reg, tmp;
8404
8405         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8406                 with_spread = true;
8407         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8408                 with_fdi = false;
8409
8410         mutex_lock(&dev_priv->sb_lock);
8411
8412         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8413         tmp &= ~SBI_SSCCTL_DISABLE;
8414         tmp |= SBI_SSCCTL_PATHALT;
8415         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8416
8417         udelay(24);
8418
8419         if (with_spread) {
8420                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8421                 tmp &= ~SBI_SSCCTL_PATHALT;
8422                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8423
8424                 if (with_fdi) {
8425                         lpt_reset_fdi_mphy(dev_priv);
8426                         lpt_program_fdi_mphy(dev_priv);
8427                 }
8428         }
8429
8430         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8431         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8432         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8433         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8434
8435         mutex_unlock(&dev_priv->sb_lock);
8436 }
8437
8438 /* Sequence to disable CLKOUT_DP */
8439 static void lpt_disable_clkout_dp(struct drm_device *dev)
8440 {
8441         struct drm_i915_private *dev_priv = dev->dev_private;
8442         uint32_t reg, tmp;
8443
8444         mutex_lock(&dev_priv->sb_lock);
8445
8446         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8447         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8448         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8449         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8450
8451         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8452         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8453                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8454                         tmp |= SBI_SSCCTL_PATHALT;
8455                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8456                         udelay(32);
8457                 }
8458                 tmp |= SBI_SSCCTL_DISABLE;
8459                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8460         }
8461
8462         mutex_unlock(&dev_priv->sb_lock);
8463 }
8464
8465 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8466
8467 static const uint16_t sscdivintphase[] = {
8468         [BEND_IDX( 50)] = 0x3B23,
8469         [BEND_IDX( 45)] = 0x3B23,
8470         [BEND_IDX( 40)] = 0x3C23,
8471         [BEND_IDX( 35)] = 0x3C23,
8472         [BEND_IDX( 30)] = 0x3D23,
8473         [BEND_IDX( 25)] = 0x3D23,
8474         [BEND_IDX( 20)] = 0x3E23,
8475         [BEND_IDX( 15)] = 0x3E23,
8476         [BEND_IDX( 10)] = 0x3F23,
8477         [BEND_IDX(  5)] = 0x3F23,
8478         [BEND_IDX(  0)] = 0x0025,
8479         [BEND_IDX( -5)] = 0x0025,
8480         [BEND_IDX(-10)] = 0x0125,
8481         [BEND_IDX(-15)] = 0x0125,
8482         [BEND_IDX(-20)] = 0x0225,
8483         [BEND_IDX(-25)] = 0x0225,
8484         [BEND_IDX(-30)] = 0x0325,
8485         [BEND_IDX(-35)] = 0x0325,
8486         [BEND_IDX(-40)] = 0x0425,
8487         [BEND_IDX(-45)] = 0x0425,
8488         [BEND_IDX(-50)] = 0x0525,
8489 };
8490
8491 /*
8492  * Bend CLKOUT_DP
8493  * steps -50 to 50 inclusive, in steps of 5
8494  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8495  * change in clock period = -(steps / 10) * 5.787 ps
8496  */
8497 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8498 {
8499         uint32_t tmp;
8500         int idx = BEND_IDX(steps);
8501
8502         if (WARN_ON(steps % 5 != 0))
8503                 return;
8504
8505         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8506                 return;
8507
8508         mutex_lock(&dev_priv->sb_lock);
8509
8510         if (steps % 10 != 0)
8511                 tmp = 0xAAAAAAAB;
8512         else
8513                 tmp = 0x00000000;
8514         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8515
8516         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8517         tmp &= 0xffff0000;
8518         tmp |= sscdivintphase[idx];
8519         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8520
8521         mutex_unlock(&dev_priv->sb_lock);
8522 }
8523
8524 #undef BEND_IDX
8525
8526 static void lpt_init_pch_refclk(struct drm_device *dev)
8527 {
8528         struct intel_encoder *encoder;
8529         bool has_vga = false;
8530
8531         for_each_intel_encoder(dev, encoder) {
8532                 switch (encoder->type) {
8533                 case INTEL_OUTPUT_ANALOG:
8534                         has_vga = true;
8535                         break;
8536                 default:
8537                         break;
8538                 }
8539         }
8540
8541         if (has_vga) {
8542                 lpt_bend_clkout_dp(to_i915(dev), 0);
8543                 lpt_enable_clkout_dp(dev, true, true);
8544         } else {
8545                 lpt_disable_clkout_dp(dev);
8546         }
8547 }
8548
8549 /*
8550  * Initialize reference clocks when the driver loads
8551  */
8552 void intel_init_pch_refclk(struct drm_device *dev)
8553 {
8554         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8555                 ironlake_init_pch_refclk(dev);
8556         else if (HAS_PCH_LPT(dev))
8557                 lpt_init_pch_refclk(dev);
8558 }
8559
8560 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8561 {
8562         struct drm_device *dev = crtc_state->base.crtc->dev;
8563         struct drm_i915_private *dev_priv = dev->dev_private;
8564         struct drm_atomic_state *state = crtc_state->base.state;
8565         struct drm_connector *connector;
8566         struct drm_connector_state *connector_state;
8567         struct intel_encoder *encoder;
8568         int num_connectors = 0, i;
8569         bool is_lvds = false;
8570
8571         for_each_connector_in_state(state, connector, connector_state, i) {
8572                 if (connector_state->crtc != crtc_state->base.crtc)
8573                         continue;
8574
8575                 encoder = to_intel_encoder(connector_state->best_encoder);
8576
8577                 switch (encoder->type) {
8578                 case INTEL_OUTPUT_LVDS:
8579                         is_lvds = true;
8580                         break;
8581                 default:
8582                         break;
8583                 }
8584                 num_connectors++;
8585         }
8586
8587         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8588                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8589                               dev_priv->vbt.lvds_ssc_freq);
8590                 return dev_priv->vbt.lvds_ssc_freq;
8591         }
8592
8593         return 120000;
8594 }
8595
8596 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8597 {
8598         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8600         int pipe = intel_crtc->pipe;
8601         uint32_t val;
8602
8603         val = 0;
8604
8605         switch (intel_crtc->config->pipe_bpp) {
8606         case 18:
8607                 val |= PIPECONF_6BPC;
8608                 break;
8609         case 24:
8610                 val |= PIPECONF_8BPC;
8611                 break;
8612         case 30:
8613                 val |= PIPECONF_10BPC;
8614                 break;
8615         case 36:
8616                 val |= PIPECONF_12BPC;
8617                 break;
8618         default:
8619                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8620                 BUG();
8621         }
8622
8623         if (intel_crtc->config->dither)
8624                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8625
8626         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8627                 val |= PIPECONF_INTERLACED_ILK;
8628         else
8629                 val |= PIPECONF_PROGRESSIVE;
8630
8631         if (intel_crtc->config->limited_color_range)
8632                 val |= PIPECONF_COLOR_RANGE_SELECT;
8633
8634         I915_WRITE(PIPECONF(pipe), val);
8635         POSTING_READ(PIPECONF(pipe));
8636 }
8637
8638 /*
8639  * Set up the pipe CSC unit.
8640  *
8641  * Currently only full range RGB to limited range RGB conversion
8642  * is supported, but eventually this should handle various
8643  * RGB<->YCbCr scenarios as well.
8644  */
8645 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8646 {
8647         struct drm_device *dev = crtc->dev;
8648         struct drm_i915_private *dev_priv = dev->dev_private;
8649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8650         int pipe = intel_crtc->pipe;
8651         uint16_t coeff = 0x7800; /* 1.0 */
8652
8653         /*
8654          * TODO: Check what kind of values actually come out of the pipe
8655          * with these coeff/postoff values and adjust to get the best
8656          * accuracy. Perhaps we even need to take the bpc value into
8657          * consideration.
8658          */
8659
8660         if (intel_crtc->config->limited_color_range)
8661                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8662
8663         /*
8664          * GY/GU and RY/RU should be the other way around according
8665          * to BSpec, but reality doesn't agree. Just set them up in
8666          * a way that results in the correct picture.
8667          */
8668         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8669         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8670
8671         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8672         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8673
8674         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8675         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8676
8677         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8678         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8679         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8680
8681         if (INTEL_INFO(dev)->gen > 6) {
8682                 uint16_t postoff = 0;
8683
8684                 if (intel_crtc->config->limited_color_range)
8685                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8686
8687                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8688                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8689                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8690
8691                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8692         } else {
8693                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8694
8695                 if (intel_crtc->config->limited_color_range)
8696                         mode |= CSC_BLACK_SCREEN_OFFSET;
8697
8698                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8699         }
8700 }
8701
8702 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8703 {
8704         struct drm_device *dev = crtc->dev;
8705         struct drm_i915_private *dev_priv = dev->dev_private;
8706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8707         enum pipe pipe = intel_crtc->pipe;
8708         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8709         uint32_t val;
8710
8711         val = 0;
8712
8713         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8714                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8715
8716         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8717                 val |= PIPECONF_INTERLACED_ILK;
8718         else
8719                 val |= PIPECONF_PROGRESSIVE;
8720
8721         I915_WRITE(PIPECONF(cpu_transcoder), val);
8722         POSTING_READ(PIPECONF(cpu_transcoder));
8723
8724         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8725         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8726
8727         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8728                 val = 0;
8729
8730                 switch (intel_crtc->config->pipe_bpp) {
8731                 case 18:
8732                         val |= PIPEMISC_DITHER_6_BPC;
8733                         break;
8734                 case 24:
8735                         val |= PIPEMISC_DITHER_8_BPC;
8736                         break;
8737                 case 30:
8738                         val |= PIPEMISC_DITHER_10_BPC;
8739                         break;
8740                 case 36:
8741                         val |= PIPEMISC_DITHER_12_BPC;
8742                         break;
8743                 default:
8744                         /* Case prevented by pipe_config_set_bpp. */
8745                         BUG();
8746                 }
8747
8748                 if (intel_crtc->config->dither)
8749                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8750
8751                 I915_WRITE(PIPEMISC(pipe), val);
8752         }
8753 }
8754
8755 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8756                                     struct intel_crtc_state *crtc_state,
8757                                     intel_clock_t *clock,
8758                                     bool *has_reduced_clock,
8759                                     intel_clock_t *reduced_clock)
8760 {
8761         struct drm_device *dev = crtc->dev;
8762         struct drm_i915_private *dev_priv = dev->dev_private;
8763         int refclk;
8764         const intel_limit_t *limit;
8765         bool ret;
8766
8767         refclk = ironlake_get_refclk(crtc_state);
8768
8769         /*
8770          * Returns a set of divisors for the desired target clock with the given
8771          * refclk, or FALSE.  The returned values represent the clock equation:
8772          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8773          */
8774         limit = intel_limit(crtc_state, refclk);
8775         ret = dev_priv->display.find_dpll(limit, crtc_state,
8776                                           crtc_state->port_clock,
8777                                           refclk, NULL, clock);
8778         if (!ret)
8779                 return false;
8780
8781         return true;
8782 }
8783
8784 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8785 {
8786         /*
8787          * Account for spread spectrum to avoid
8788          * oversubscribing the link. Max center spread
8789          * is 2.5%; use 5% for safety's sake.
8790          */
8791         u32 bps = target_clock * bpp * 21 / 20;
8792         return DIV_ROUND_UP(bps, link_bw * 8);
8793 }
8794
8795 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8796 {
8797         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8798 }
8799
8800 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8801                                       struct intel_crtc_state *crtc_state,
8802                                       u32 *fp,
8803                                       intel_clock_t *reduced_clock, u32 *fp2)
8804 {
8805         struct drm_crtc *crtc = &intel_crtc->base;
8806         struct drm_device *dev = crtc->dev;
8807         struct drm_i915_private *dev_priv = dev->dev_private;
8808         struct drm_atomic_state *state = crtc_state->base.state;
8809         struct drm_connector *connector;
8810         struct drm_connector_state *connector_state;
8811         struct intel_encoder *encoder;
8812         uint32_t dpll;
8813         int factor, num_connectors = 0, i;
8814         bool is_lvds = false, is_sdvo = false;
8815
8816         for_each_connector_in_state(state, connector, connector_state, i) {
8817                 if (connector_state->crtc != crtc_state->base.crtc)
8818                         continue;
8819
8820                 encoder = to_intel_encoder(connector_state->best_encoder);
8821
8822                 switch (encoder->type) {
8823                 case INTEL_OUTPUT_LVDS:
8824                         is_lvds = true;
8825                         break;
8826                 case INTEL_OUTPUT_SDVO:
8827                 case INTEL_OUTPUT_HDMI:
8828                         is_sdvo = true;
8829                         break;
8830                 default:
8831                         break;
8832                 }
8833
8834                 num_connectors++;
8835         }
8836
8837         /* Enable autotuning of the PLL clock (if permissible) */
8838         factor = 21;
8839         if (is_lvds) {
8840                 if ((intel_panel_use_ssc(dev_priv) &&
8841                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8842                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8843                         factor = 25;
8844         } else if (crtc_state->sdvo_tv_clock)
8845                 factor = 20;
8846
8847         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8848                 *fp |= FP_CB_TUNE;
8849
8850         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8851                 *fp2 |= FP_CB_TUNE;
8852
8853         dpll = 0;
8854
8855         if (is_lvds)
8856                 dpll |= DPLLB_MODE_LVDS;
8857         else
8858                 dpll |= DPLLB_MODE_DAC_SERIAL;
8859
8860         dpll |= (crtc_state->pixel_multiplier - 1)
8861                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8862
8863         if (is_sdvo)
8864                 dpll |= DPLL_SDVO_HIGH_SPEED;
8865         if (crtc_state->has_dp_encoder)
8866                 dpll |= DPLL_SDVO_HIGH_SPEED;
8867
8868         /* compute bitmask from p1 value */
8869         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8870         /* also FPA1 */
8871         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8872
8873         switch (crtc_state->dpll.p2) {
8874         case 5:
8875                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8876                 break;
8877         case 7:
8878                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8879                 break;
8880         case 10:
8881                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8882                 break;
8883         case 14:
8884                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8885                 break;
8886         }
8887
8888         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8889                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8890         else
8891                 dpll |= PLL_REF_INPUT_DREFCLK;
8892
8893         return dpll | DPLL_VCO_ENABLE;
8894 }
8895
8896 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8897                                        struct intel_crtc_state *crtc_state)
8898 {
8899         struct drm_device *dev = crtc->base.dev;
8900         intel_clock_t clock, reduced_clock;
8901         u32 dpll = 0, fp = 0, fp2 = 0;
8902         bool ok, has_reduced_clock = false;
8903         bool is_lvds = false;
8904         struct intel_shared_dpll *pll;
8905
8906         memset(&crtc_state->dpll_hw_state, 0,
8907                sizeof(crtc_state->dpll_hw_state));
8908
8909         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8910
8911         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8912              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8913
8914         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8915                                      &has_reduced_clock, &reduced_clock);
8916         if (!ok && !crtc_state->clock_set) {
8917                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8918                 return -EINVAL;
8919         }
8920         /* Compat-code for transition, will disappear. */
8921         if (!crtc_state->clock_set) {
8922                 crtc_state->dpll.n = clock.n;
8923                 crtc_state->dpll.m1 = clock.m1;
8924                 crtc_state->dpll.m2 = clock.m2;
8925                 crtc_state->dpll.p1 = clock.p1;
8926                 crtc_state->dpll.p2 = clock.p2;
8927         }
8928
8929         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8930         if (crtc_state->has_pch_encoder) {
8931                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8932                 if (has_reduced_clock)
8933                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8934
8935                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8936                                              &fp, &reduced_clock,
8937                                              has_reduced_clock ? &fp2 : NULL);
8938
8939                 crtc_state->dpll_hw_state.dpll = dpll;
8940                 crtc_state->dpll_hw_state.fp0 = fp;
8941                 if (has_reduced_clock)
8942                         crtc_state->dpll_hw_state.fp1 = fp2;
8943                 else
8944                         crtc_state->dpll_hw_state.fp1 = fp;
8945
8946                 pll = intel_get_shared_dpll(crtc, crtc_state);
8947                 if (pll == NULL) {
8948                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8949                                          pipe_name(crtc->pipe));
8950                         return -EINVAL;
8951                 }
8952         }
8953
8954         if (is_lvds && has_reduced_clock)
8955                 crtc->lowfreq_avail = true;
8956         else
8957                 crtc->lowfreq_avail = false;
8958
8959         return 0;
8960 }
8961
8962 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8963                                          struct intel_link_m_n *m_n)
8964 {
8965         struct drm_device *dev = crtc->base.dev;
8966         struct drm_i915_private *dev_priv = dev->dev_private;
8967         enum pipe pipe = crtc->pipe;
8968
8969         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8970         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8971         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8972                 & ~TU_SIZE_MASK;
8973         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8974         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8975                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976 }
8977
8978 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8979                                          enum transcoder transcoder,
8980                                          struct intel_link_m_n *m_n,
8981                                          struct intel_link_m_n *m2_n2)
8982 {
8983         struct drm_device *dev = crtc->base.dev;
8984         struct drm_i915_private *dev_priv = dev->dev_private;
8985         enum pipe pipe = crtc->pipe;
8986
8987         if (INTEL_INFO(dev)->gen >= 5) {
8988                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8989                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8990                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8991                         & ~TU_SIZE_MASK;
8992                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8993                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8994                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8995                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8996                  * gen < 8) and if DRRS is supported (to make sure the
8997                  * registers are not unnecessarily read).
8998                  */
8999                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9000                         crtc->config->has_drrs) {
9001                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9002                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9003                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9004                                         & ~TU_SIZE_MASK;
9005                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9006                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9007                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9008                 }
9009         } else {
9010                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9011                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9012                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9013                         & ~TU_SIZE_MASK;
9014                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9015                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9016                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9017         }
9018 }
9019
9020 void intel_dp_get_m_n(struct intel_crtc *crtc,
9021                       struct intel_crtc_state *pipe_config)
9022 {
9023         if (pipe_config->has_pch_encoder)
9024                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9025         else
9026                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9027                                              &pipe_config->dp_m_n,
9028                                              &pipe_config->dp_m2_n2);
9029 }
9030
9031 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9032                                         struct intel_crtc_state *pipe_config)
9033 {
9034         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9035                                      &pipe_config->fdi_m_n, NULL);
9036 }
9037
9038 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9039                                     struct intel_crtc_state *pipe_config)
9040 {
9041         struct drm_device *dev = crtc->base.dev;
9042         struct drm_i915_private *dev_priv = dev->dev_private;
9043         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9044         uint32_t ps_ctrl = 0;
9045         int id = -1;
9046         int i;
9047
9048         /* find scaler attached to this pipe */
9049         for (i = 0; i < crtc->num_scalers; i++) {
9050                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9051                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9052                         id = i;
9053                         pipe_config->pch_pfit.enabled = true;
9054                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9055                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9056                         break;
9057                 }
9058         }
9059
9060         scaler_state->scaler_id = id;
9061         if (id >= 0) {
9062                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9063         } else {
9064                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9065         }
9066 }
9067
9068 static void
9069 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9070                                  struct intel_initial_plane_config *plane_config)
9071 {
9072         struct drm_device *dev = crtc->base.dev;
9073         struct drm_i915_private *dev_priv = dev->dev_private;
9074         u32 val, base, offset, stride_mult, tiling;
9075         int pipe = crtc->pipe;
9076         int fourcc, pixel_format;
9077         unsigned int aligned_height;
9078         struct drm_framebuffer *fb;
9079         struct intel_framebuffer *intel_fb;
9080
9081         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9082         if (!intel_fb) {
9083                 DRM_DEBUG_KMS("failed to alloc fb\n");
9084                 return;
9085         }
9086
9087         fb = &intel_fb->base;
9088
9089         val = I915_READ(PLANE_CTL(pipe, 0));
9090         if (!(val & PLANE_CTL_ENABLE))
9091                 goto error;
9092
9093         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9094         fourcc = skl_format_to_fourcc(pixel_format,
9095                                       val & PLANE_CTL_ORDER_RGBX,
9096                                       val & PLANE_CTL_ALPHA_MASK);
9097         fb->pixel_format = fourcc;
9098         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9099
9100         tiling = val & PLANE_CTL_TILED_MASK;
9101         switch (tiling) {
9102         case PLANE_CTL_TILED_LINEAR:
9103                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9104                 break;
9105         case PLANE_CTL_TILED_X:
9106                 plane_config->tiling = I915_TILING_X;
9107                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9108                 break;
9109         case PLANE_CTL_TILED_Y:
9110                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9111                 break;
9112         case PLANE_CTL_TILED_YF:
9113                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9114                 break;
9115         default:
9116                 MISSING_CASE(tiling);
9117                 goto error;
9118         }
9119
9120         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9121         plane_config->base = base;
9122
9123         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9124
9125         val = I915_READ(PLANE_SIZE(pipe, 0));
9126         fb->height = ((val >> 16) & 0xfff) + 1;
9127         fb->width = ((val >> 0) & 0x1fff) + 1;
9128
9129         val = I915_READ(PLANE_STRIDE(pipe, 0));
9130         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9131                                                 fb->pixel_format);
9132         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9133
9134         aligned_height = intel_fb_align_height(dev, fb->height,
9135                                                fb->pixel_format,
9136                                                fb->modifier[0]);
9137
9138         plane_config->size = fb->pitches[0] * aligned_height;
9139
9140         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9141                       pipe_name(pipe), fb->width, fb->height,
9142                       fb->bits_per_pixel, base, fb->pitches[0],
9143                       plane_config->size);
9144
9145         plane_config->fb = intel_fb;
9146         return;
9147
9148 error:
9149         kfree(fb);
9150 }
9151
9152 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9153                                      struct intel_crtc_state *pipe_config)
9154 {
9155         struct drm_device *dev = crtc->base.dev;
9156         struct drm_i915_private *dev_priv = dev->dev_private;
9157         uint32_t tmp;
9158
9159         tmp = I915_READ(PF_CTL(crtc->pipe));
9160
9161         if (tmp & PF_ENABLE) {
9162                 pipe_config->pch_pfit.enabled = true;
9163                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9164                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9165
9166                 /* We currently do not free assignements of panel fitters on
9167                  * ivb/hsw (since we don't use the higher upscaling modes which
9168                  * differentiates them) so just WARN about this case for now. */
9169                 if (IS_GEN7(dev)) {
9170                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9171                                 PF_PIPE_SEL_IVB(crtc->pipe));
9172                 }
9173         }
9174 }
9175
9176 static void
9177 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9178                                   struct intel_initial_plane_config *plane_config)
9179 {
9180         struct drm_device *dev = crtc->base.dev;
9181         struct drm_i915_private *dev_priv = dev->dev_private;
9182         u32 val, base, offset;
9183         int pipe = crtc->pipe;
9184         int fourcc, pixel_format;
9185         unsigned int aligned_height;
9186         struct drm_framebuffer *fb;
9187         struct intel_framebuffer *intel_fb;
9188
9189         val = I915_READ(DSPCNTR(pipe));
9190         if (!(val & DISPLAY_PLANE_ENABLE))
9191                 return;
9192
9193         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9194         if (!intel_fb) {
9195                 DRM_DEBUG_KMS("failed to alloc fb\n");
9196                 return;
9197         }
9198
9199         fb = &intel_fb->base;
9200
9201         if (INTEL_INFO(dev)->gen >= 4) {
9202                 if (val & DISPPLANE_TILED) {
9203                         plane_config->tiling = I915_TILING_X;
9204                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9205                 }
9206         }
9207
9208         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9209         fourcc = i9xx_format_to_fourcc(pixel_format);
9210         fb->pixel_format = fourcc;
9211         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9212
9213         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9214         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9215                 offset = I915_READ(DSPOFFSET(pipe));
9216         } else {
9217                 if (plane_config->tiling)
9218                         offset = I915_READ(DSPTILEOFF(pipe));
9219                 else
9220                         offset = I915_READ(DSPLINOFF(pipe));
9221         }
9222         plane_config->base = base;
9223
9224         val = I915_READ(PIPESRC(pipe));
9225         fb->width = ((val >> 16) & 0xfff) + 1;
9226         fb->height = ((val >> 0) & 0xfff) + 1;
9227
9228         val = I915_READ(DSPSTRIDE(pipe));
9229         fb->pitches[0] = val & 0xffffffc0;
9230
9231         aligned_height = intel_fb_align_height(dev, fb->height,
9232                                                fb->pixel_format,
9233                                                fb->modifier[0]);
9234
9235         plane_config->size = fb->pitches[0] * aligned_height;
9236
9237         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9238                       pipe_name(pipe), fb->width, fb->height,
9239                       fb->bits_per_pixel, base, fb->pitches[0],
9240                       plane_config->size);
9241
9242         plane_config->fb = intel_fb;
9243 }
9244
9245 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9246                                      struct intel_crtc_state *pipe_config)
9247 {
9248         struct drm_device *dev = crtc->base.dev;
9249         struct drm_i915_private *dev_priv = dev->dev_private;
9250         enum intel_display_power_domain power_domain;
9251         uint32_t tmp;
9252         bool ret;
9253
9254         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9255         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9256                 return false;
9257
9258         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9259         pipe_config->shared_dpll = NULL;
9260
9261         ret = false;
9262         tmp = I915_READ(PIPECONF(crtc->pipe));
9263         if (!(tmp & PIPECONF_ENABLE))
9264                 goto out;
9265
9266         switch (tmp & PIPECONF_BPC_MASK) {
9267         case PIPECONF_6BPC:
9268                 pipe_config->pipe_bpp = 18;
9269                 break;
9270         case PIPECONF_8BPC:
9271                 pipe_config->pipe_bpp = 24;
9272                 break;
9273         case PIPECONF_10BPC:
9274                 pipe_config->pipe_bpp = 30;
9275                 break;
9276         case PIPECONF_12BPC:
9277                 pipe_config->pipe_bpp = 36;
9278                 break;
9279         default:
9280                 break;
9281         }
9282
9283         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9284                 pipe_config->limited_color_range = true;
9285
9286         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9287                 struct intel_shared_dpll *pll;
9288                 enum intel_dpll_id pll_id;
9289
9290                 pipe_config->has_pch_encoder = true;
9291
9292                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9293                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9294                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9295
9296                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9297
9298                 if (HAS_PCH_IBX(dev_priv->dev)) {
9299                         pll_id = (enum intel_dpll_id) crtc->pipe;
9300                 } else {
9301                         tmp = I915_READ(PCH_DPLL_SEL);
9302                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9303                                 pll_id = DPLL_ID_PCH_PLL_B;
9304                         else
9305                                 pll_id= DPLL_ID_PCH_PLL_A;
9306                 }
9307
9308                 pipe_config->shared_dpll =
9309                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9310                 pll = pipe_config->shared_dpll;
9311
9312                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9313                                                  &pipe_config->dpll_hw_state));
9314
9315                 tmp = pipe_config->dpll_hw_state.dpll;
9316                 pipe_config->pixel_multiplier =
9317                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9318                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9319
9320                 ironlake_pch_clock_get(crtc, pipe_config);
9321         } else {
9322                 pipe_config->pixel_multiplier = 1;
9323         }
9324
9325         intel_get_pipe_timings(crtc, pipe_config);
9326
9327         ironlake_get_pfit_config(crtc, pipe_config);
9328
9329         ret = true;
9330
9331 out:
9332         intel_display_power_put(dev_priv, power_domain);
9333
9334         return ret;
9335 }
9336
9337 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9338 {
9339         struct drm_device *dev = dev_priv->dev;
9340         struct intel_crtc *crtc;
9341
9342         for_each_intel_crtc(dev, crtc)
9343                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9344                      pipe_name(crtc->pipe));
9345
9346         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9347         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9348         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9349         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9350         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9351         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9352              "CPU PWM1 enabled\n");
9353         if (IS_HASWELL(dev))
9354                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9355                      "CPU PWM2 enabled\n");
9356         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9357              "PCH PWM1 enabled\n");
9358         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9359              "Utility pin enabled\n");
9360         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9361
9362         /*
9363          * In theory we can still leave IRQs enabled, as long as only the HPD
9364          * interrupts remain enabled. We used to check for that, but since it's
9365          * gen-specific and since we only disable LCPLL after we fully disable
9366          * the interrupts, the check below should be enough.
9367          */
9368         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9369 }
9370
9371 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9372 {
9373         struct drm_device *dev = dev_priv->dev;
9374
9375         if (IS_HASWELL(dev))
9376                 return I915_READ(D_COMP_HSW);
9377         else
9378                 return I915_READ(D_COMP_BDW);
9379 }
9380
9381 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9382 {
9383         struct drm_device *dev = dev_priv->dev;
9384
9385         if (IS_HASWELL(dev)) {
9386                 mutex_lock(&dev_priv->rps.hw_lock);
9387                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9388                                             val))
9389                         DRM_ERROR("Failed to write to D_COMP\n");
9390                 mutex_unlock(&dev_priv->rps.hw_lock);
9391         } else {
9392                 I915_WRITE(D_COMP_BDW, val);
9393                 POSTING_READ(D_COMP_BDW);
9394         }
9395 }
9396
9397 /*
9398  * This function implements pieces of two sequences from BSpec:
9399  * - Sequence for display software to disable LCPLL
9400  * - Sequence for display software to allow package C8+
9401  * The steps implemented here are just the steps that actually touch the LCPLL
9402  * register. Callers should take care of disabling all the display engine
9403  * functions, doing the mode unset, fixing interrupts, etc.
9404  */
9405 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9406                               bool switch_to_fclk, bool allow_power_down)
9407 {
9408         uint32_t val;
9409
9410         assert_can_disable_lcpll(dev_priv);
9411
9412         val = I915_READ(LCPLL_CTL);
9413
9414         if (switch_to_fclk) {
9415                 val |= LCPLL_CD_SOURCE_FCLK;
9416                 I915_WRITE(LCPLL_CTL, val);
9417
9418                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9419                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9420                         DRM_ERROR("Switching to FCLK failed\n");
9421
9422                 val = I915_READ(LCPLL_CTL);
9423         }
9424
9425         val |= LCPLL_PLL_DISABLE;
9426         I915_WRITE(LCPLL_CTL, val);
9427         POSTING_READ(LCPLL_CTL);
9428
9429         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9430                 DRM_ERROR("LCPLL still locked\n");
9431
9432         val = hsw_read_dcomp(dev_priv);
9433         val |= D_COMP_COMP_DISABLE;
9434         hsw_write_dcomp(dev_priv, val);
9435         ndelay(100);
9436
9437         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9438                      1))
9439                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9440
9441         if (allow_power_down) {
9442                 val = I915_READ(LCPLL_CTL);
9443                 val |= LCPLL_POWER_DOWN_ALLOW;
9444                 I915_WRITE(LCPLL_CTL, val);
9445                 POSTING_READ(LCPLL_CTL);
9446         }
9447 }
9448
9449 /*
9450  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9451  * source.
9452  */
9453 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9454 {
9455         uint32_t val;
9456
9457         val = I915_READ(LCPLL_CTL);
9458
9459         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9460                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9461                 return;
9462
9463         /*
9464          * Make sure we're not on PC8 state before disabling PC8, otherwise
9465          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9466          */
9467         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9468
9469         if (val & LCPLL_POWER_DOWN_ALLOW) {
9470                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9471                 I915_WRITE(LCPLL_CTL, val);
9472                 POSTING_READ(LCPLL_CTL);
9473         }
9474
9475         val = hsw_read_dcomp(dev_priv);
9476         val |= D_COMP_COMP_FORCE;
9477         val &= ~D_COMP_COMP_DISABLE;
9478         hsw_write_dcomp(dev_priv, val);
9479
9480         val = I915_READ(LCPLL_CTL);
9481         val &= ~LCPLL_PLL_DISABLE;
9482         I915_WRITE(LCPLL_CTL, val);
9483
9484         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9485                 DRM_ERROR("LCPLL not locked yet\n");
9486
9487         if (val & LCPLL_CD_SOURCE_FCLK) {
9488                 val = I915_READ(LCPLL_CTL);
9489                 val &= ~LCPLL_CD_SOURCE_FCLK;
9490                 I915_WRITE(LCPLL_CTL, val);
9491
9492                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9493                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9494                         DRM_ERROR("Switching back to LCPLL failed\n");
9495         }
9496
9497         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9498         intel_update_cdclk(dev_priv->dev);
9499 }
9500
9501 /*
9502  * Package states C8 and deeper are really deep PC states that can only be
9503  * reached when all the devices on the system allow it, so even if the graphics
9504  * device allows PC8+, it doesn't mean the system will actually get to these
9505  * states. Our driver only allows PC8+ when going into runtime PM.
9506  *
9507  * The requirements for PC8+ are that all the outputs are disabled, the power
9508  * well is disabled and most interrupts are disabled, and these are also
9509  * requirements for runtime PM. When these conditions are met, we manually do
9510  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9511  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9512  * hang the machine.
9513  *
9514  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9515  * the state of some registers, so when we come back from PC8+ we need to
9516  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9517  * need to take care of the registers kept by RC6. Notice that this happens even
9518  * if we don't put the device in PCI D3 state (which is what currently happens
9519  * because of the runtime PM support).
9520  *
9521  * For more, read "Display Sequences for Package C8" on the hardware
9522  * documentation.
9523  */
9524 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9525 {
9526         struct drm_device *dev = dev_priv->dev;
9527         uint32_t val;
9528
9529         DRM_DEBUG_KMS("Enabling package C8+\n");
9530
9531         if (HAS_PCH_LPT_LP(dev)) {
9532                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9533                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9534                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9535         }
9536
9537         lpt_disable_clkout_dp(dev);
9538         hsw_disable_lcpll(dev_priv, true, true);
9539 }
9540
9541 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9542 {
9543         struct drm_device *dev = dev_priv->dev;
9544         uint32_t val;
9545
9546         DRM_DEBUG_KMS("Disabling package C8+\n");
9547
9548         hsw_restore_lcpll(dev_priv);
9549         lpt_init_pch_refclk(dev);
9550
9551         if (HAS_PCH_LPT_LP(dev)) {
9552                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9553                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9554                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9555         }
9556 }
9557
9558 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9559 {
9560         struct drm_device *dev = old_state->dev;
9561         struct intel_atomic_state *old_intel_state =
9562                 to_intel_atomic_state(old_state);
9563         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9564
9565         broxton_set_cdclk(dev, req_cdclk);
9566 }
9567
9568 /* compute the max rate for new configuration */
9569 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9570 {
9571         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9572         struct drm_i915_private *dev_priv = state->dev->dev_private;
9573         struct drm_crtc *crtc;
9574         struct drm_crtc_state *cstate;
9575         struct intel_crtc_state *crtc_state;
9576         unsigned max_pixel_rate = 0, i;
9577         enum pipe pipe;
9578
9579         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9580                sizeof(intel_state->min_pixclk));
9581
9582         for_each_crtc_in_state(state, crtc, cstate, i) {
9583                 int pixel_rate;
9584
9585                 crtc_state = to_intel_crtc_state(cstate);
9586                 if (!crtc_state->base.enable) {
9587                         intel_state->min_pixclk[i] = 0;
9588                         continue;
9589                 }
9590
9591                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9592
9593                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9594                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9595                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9596
9597                 intel_state->min_pixclk[i] = pixel_rate;
9598         }
9599
9600         for_each_pipe(dev_priv, pipe)
9601                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9602
9603         return max_pixel_rate;
9604 }
9605
9606 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9607 {
9608         struct drm_i915_private *dev_priv = dev->dev_private;
9609         uint32_t val, data;
9610         int ret;
9611
9612         if (WARN((I915_READ(LCPLL_CTL) &
9613                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9614                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9615                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9616                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9617                  "trying to change cdclk frequency with cdclk not enabled\n"))
9618                 return;
9619
9620         mutex_lock(&dev_priv->rps.hw_lock);
9621         ret = sandybridge_pcode_write(dev_priv,
9622                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9623         mutex_unlock(&dev_priv->rps.hw_lock);
9624         if (ret) {
9625                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9626                 return;
9627         }
9628
9629         val = I915_READ(LCPLL_CTL);
9630         val |= LCPLL_CD_SOURCE_FCLK;
9631         I915_WRITE(LCPLL_CTL, val);
9632
9633         if (wait_for_us(I915_READ(LCPLL_CTL) &
9634                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9635                 DRM_ERROR("Switching to FCLK failed\n");
9636
9637         val = I915_READ(LCPLL_CTL);
9638         val &= ~LCPLL_CLK_FREQ_MASK;
9639
9640         switch (cdclk) {
9641         case 450000:
9642                 val |= LCPLL_CLK_FREQ_450;
9643                 data = 0;
9644                 break;
9645         case 540000:
9646                 val |= LCPLL_CLK_FREQ_54O_BDW;
9647                 data = 1;
9648                 break;
9649         case 337500:
9650                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9651                 data = 2;
9652                 break;
9653         case 675000:
9654                 val |= LCPLL_CLK_FREQ_675_BDW;
9655                 data = 3;
9656                 break;
9657         default:
9658                 WARN(1, "invalid cdclk frequency\n");
9659                 return;
9660         }
9661
9662         I915_WRITE(LCPLL_CTL, val);
9663
9664         val = I915_READ(LCPLL_CTL);
9665         val &= ~LCPLL_CD_SOURCE_FCLK;
9666         I915_WRITE(LCPLL_CTL, val);
9667
9668         if (wait_for_us((I915_READ(LCPLL_CTL) &
9669                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9670                 DRM_ERROR("Switching back to LCPLL failed\n");
9671
9672         mutex_lock(&dev_priv->rps.hw_lock);
9673         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9674         mutex_unlock(&dev_priv->rps.hw_lock);
9675
9676         intel_update_cdclk(dev);
9677
9678         WARN(cdclk != dev_priv->cdclk_freq,
9679              "cdclk requested %d kHz but got %d kHz\n",
9680              cdclk, dev_priv->cdclk_freq);
9681 }
9682
9683 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9684 {
9685         struct drm_i915_private *dev_priv = to_i915(state->dev);
9686         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9687         int max_pixclk = ilk_max_pixel_rate(state);
9688         int cdclk;
9689
9690         /*
9691          * FIXME should also account for plane ratio
9692          * once 64bpp pixel formats are supported.
9693          */
9694         if (max_pixclk > 540000)
9695                 cdclk = 675000;
9696         else if (max_pixclk > 450000)
9697                 cdclk = 540000;
9698         else if (max_pixclk > 337500)
9699                 cdclk = 450000;
9700         else
9701                 cdclk = 337500;
9702
9703         if (cdclk > dev_priv->max_cdclk_freq) {
9704                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9705                               cdclk, dev_priv->max_cdclk_freq);
9706                 return -EINVAL;
9707         }
9708
9709         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9710         if (!intel_state->active_crtcs)
9711                 intel_state->dev_cdclk = 337500;
9712
9713         return 0;
9714 }
9715
9716 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9717 {
9718         struct drm_device *dev = old_state->dev;
9719         struct intel_atomic_state *old_intel_state =
9720                 to_intel_atomic_state(old_state);
9721         unsigned req_cdclk = old_intel_state->dev_cdclk;
9722
9723         broadwell_set_cdclk(dev, req_cdclk);
9724 }
9725
9726 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9727                                       struct intel_crtc_state *crtc_state)
9728 {
9729         struct intel_encoder *intel_encoder =
9730                 intel_ddi_get_crtc_new_encoder(crtc_state);
9731
9732         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9733                 if (!intel_ddi_pll_select(crtc, crtc_state))
9734                         return -EINVAL;
9735         }
9736
9737         crtc->lowfreq_avail = false;
9738
9739         return 0;
9740 }
9741
9742 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9743                                 enum port port,
9744                                 struct intel_crtc_state *pipe_config)
9745 {
9746         enum intel_dpll_id id;
9747
9748         switch (port) {
9749         case PORT_A:
9750                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9751                 id = DPLL_ID_SKL_DPLL1;
9752                 break;
9753         case PORT_B:
9754                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9755                 id = DPLL_ID_SKL_DPLL2;
9756                 break;
9757         case PORT_C:
9758                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9759                 id = DPLL_ID_SKL_DPLL3;
9760                 break;
9761         default:
9762                 DRM_ERROR("Incorrect port type\n");
9763                 return;
9764         }
9765
9766         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9767 }
9768
9769 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9770                                 enum port port,
9771                                 struct intel_crtc_state *pipe_config)
9772 {
9773         enum intel_dpll_id id;
9774         u32 temp, dpll_ctl1;
9775
9776         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9777         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9778
9779         switch (pipe_config->ddi_pll_sel) {
9780         case SKL_DPLL0:
9781                 /*
9782                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9783                  * of the shared DPLL framework and thus needs to be read out
9784                  * separately
9785                  */
9786                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9787                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9788                 return;
9789         case SKL_DPLL1:
9790                 id = DPLL_ID_SKL_DPLL1;
9791                 break;
9792         case SKL_DPLL2:
9793                 id = DPLL_ID_SKL_DPLL2;
9794                 break;
9795         case SKL_DPLL3:
9796                 id = DPLL_ID_SKL_DPLL3;
9797                 break;
9798         default:
9799                 MISSING_CASE(pipe_config->ddi_pll_sel);
9800                 return;
9801         }
9802
9803         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9804 }
9805
9806 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9807                                 enum port port,
9808                                 struct intel_crtc_state *pipe_config)
9809 {
9810         enum intel_dpll_id id;
9811
9812         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9813
9814         switch (pipe_config->ddi_pll_sel) {
9815         case PORT_CLK_SEL_WRPLL1:
9816                 id = DPLL_ID_WRPLL1;
9817                 break;
9818         case PORT_CLK_SEL_WRPLL2:
9819                 id = DPLL_ID_WRPLL2;
9820                 break;
9821         case PORT_CLK_SEL_SPLL:
9822                 id = DPLL_ID_SPLL;
9823                 break;
9824         default:
9825                 MISSING_CASE(pipe_config->ddi_pll_sel);
9826                 /* fall through */
9827         case PORT_CLK_SEL_NONE:
9828         case PORT_CLK_SEL_LCPLL_810:
9829         case PORT_CLK_SEL_LCPLL_1350:
9830         case PORT_CLK_SEL_LCPLL_2700:
9831                 return;
9832         }
9833
9834         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9835 }
9836
9837 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9838                                        struct intel_crtc_state *pipe_config)
9839 {
9840         struct drm_device *dev = crtc->base.dev;
9841         struct drm_i915_private *dev_priv = dev->dev_private;
9842         struct intel_shared_dpll *pll;
9843         enum port port;
9844         uint32_t tmp;
9845
9846         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9847
9848         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9849
9850         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9851                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9852         else if (IS_BROXTON(dev))
9853                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9854         else
9855                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9856
9857         pll = pipe_config->shared_dpll;
9858         if (pll) {
9859                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9860                                                  &pipe_config->dpll_hw_state));
9861         }
9862
9863         /*
9864          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9865          * DDI E. So just check whether this pipe is wired to DDI E and whether
9866          * the PCH transcoder is on.
9867          */
9868         if (INTEL_INFO(dev)->gen < 9 &&
9869             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9870                 pipe_config->has_pch_encoder = true;
9871
9872                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9873                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9874                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9875
9876                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9877         }
9878 }
9879
9880 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9881                                     struct intel_crtc_state *pipe_config)
9882 {
9883         struct drm_device *dev = crtc->base.dev;
9884         struct drm_i915_private *dev_priv = dev->dev_private;
9885         enum intel_display_power_domain power_domain;
9886         unsigned long power_domain_mask;
9887         uint32_t tmp;
9888         bool ret;
9889
9890         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9891         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9892                 return false;
9893         power_domain_mask = BIT(power_domain);
9894
9895         ret = false;
9896
9897         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9898         pipe_config->shared_dpll = NULL;
9899
9900         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9901         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9902                 enum pipe trans_edp_pipe;
9903                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9904                 default:
9905                         WARN(1, "unknown pipe linked to edp transcoder\n");
9906                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9907                 case TRANS_DDI_EDP_INPUT_A_ON:
9908                         trans_edp_pipe = PIPE_A;
9909                         break;
9910                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9911                         trans_edp_pipe = PIPE_B;
9912                         break;
9913                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9914                         trans_edp_pipe = PIPE_C;
9915                         break;
9916                 }
9917
9918                 if (trans_edp_pipe == crtc->pipe)
9919                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9920         }
9921
9922         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9923         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9924                 goto out;
9925         power_domain_mask |= BIT(power_domain);
9926
9927         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9928         if (!(tmp & PIPECONF_ENABLE))
9929                 goto out;
9930
9931         haswell_get_ddi_port_state(crtc, pipe_config);
9932
9933         intel_get_pipe_timings(crtc, pipe_config);
9934
9935         if (INTEL_INFO(dev)->gen >= 9) {
9936                 skl_init_scalers(dev, crtc, pipe_config);
9937         }
9938
9939         if (INTEL_INFO(dev)->gen >= 9) {
9940                 pipe_config->scaler_state.scaler_id = -1;
9941                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9942         }
9943
9944         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9945         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9946                 power_domain_mask |= BIT(power_domain);
9947                 if (INTEL_INFO(dev)->gen >= 9)
9948                         skylake_get_pfit_config(crtc, pipe_config);
9949                 else
9950                         ironlake_get_pfit_config(crtc, pipe_config);
9951         }
9952
9953         if (IS_HASWELL(dev))
9954                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9955                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9956
9957         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9958                 pipe_config->pixel_multiplier =
9959                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9960         } else {
9961                 pipe_config->pixel_multiplier = 1;
9962         }
9963
9964         ret = true;
9965
9966 out:
9967         for_each_power_domain(power_domain, power_domain_mask)
9968                 intel_display_power_put(dev_priv, power_domain);
9969
9970         return ret;
9971 }
9972
9973 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9974                                const struct intel_plane_state *plane_state)
9975 {
9976         struct drm_device *dev = crtc->dev;
9977         struct drm_i915_private *dev_priv = dev->dev_private;
9978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9979         uint32_t cntl = 0, size = 0;
9980
9981         if (plane_state && plane_state->visible) {
9982                 unsigned int width = plane_state->base.crtc_w;
9983                 unsigned int height = plane_state->base.crtc_h;
9984                 unsigned int stride = roundup_pow_of_two(width) * 4;
9985
9986                 switch (stride) {
9987                 default:
9988                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9989                                   width, stride);
9990                         stride = 256;
9991                         /* fallthrough */
9992                 case 256:
9993                 case 512:
9994                 case 1024:
9995                 case 2048:
9996                         break;
9997                 }
9998
9999                 cntl |= CURSOR_ENABLE |
10000                         CURSOR_GAMMA_ENABLE |
10001                         CURSOR_FORMAT_ARGB |
10002                         CURSOR_STRIDE(stride);
10003
10004                 size = (height << 12) | width;
10005         }
10006
10007         if (intel_crtc->cursor_cntl != 0 &&
10008             (intel_crtc->cursor_base != base ||
10009              intel_crtc->cursor_size != size ||
10010              intel_crtc->cursor_cntl != cntl)) {
10011                 /* On these chipsets we can only modify the base/size/stride
10012                  * whilst the cursor is disabled.
10013                  */
10014                 I915_WRITE(CURCNTR(PIPE_A), 0);
10015                 POSTING_READ(CURCNTR(PIPE_A));
10016                 intel_crtc->cursor_cntl = 0;
10017         }
10018
10019         if (intel_crtc->cursor_base != base) {
10020                 I915_WRITE(CURBASE(PIPE_A), base);
10021                 intel_crtc->cursor_base = base;
10022         }
10023
10024         if (intel_crtc->cursor_size != size) {
10025                 I915_WRITE(CURSIZE, size);
10026                 intel_crtc->cursor_size = size;
10027         }
10028
10029         if (intel_crtc->cursor_cntl != cntl) {
10030                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10031                 POSTING_READ(CURCNTR(PIPE_A));
10032                 intel_crtc->cursor_cntl = cntl;
10033         }
10034 }
10035
10036 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10037                                const struct intel_plane_state *plane_state)
10038 {
10039         struct drm_device *dev = crtc->dev;
10040         struct drm_i915_private *dev_priv = dev->dev_private;
10041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10042         int pipe = intel_crtc->pipe;
10043         uint32_t cntl = 0;
10044
10045         if (plane_state && plane_state->visible) {
10046                 cntl = MCURSOR_GAMMA_ENABLE;
10047                 switch (plane_state->base.crtc_w) {
10048                         case 64:
10049                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10050                                 break;
10051                         case 128:
10052                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10053                                 break;
10054                         case 256:
10055                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10056                                 break;
10057                         default:
10058                                 MISSING_CASE(plane_state->base.crtc_w);
10059                                 return;
10060                 }
10061                 cntl |= pipe << 28; /* Connect to correct pipe */
10062
10063                 if (HAS_DDI(dev))
10064                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10065
10066                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10067                         cntl |= CURSOR_ROTATE_180;
10068         }
10069
10070         if (intel_crtc->cursor_cntl != cntl) {
10071                 I915_WRITE(CURCNTR(pipe), cntl);
10072                 POSTING_READ(CURCNTR(pipe));
10073                 intel_crtc->cursor_cntl = cntl;
10074         }
10075
10076         /* and commit changes on next vblank */
10077         I915_WRITE(CURBASE(pipe), base);
10078         POSTING_READ(CURBASE(pipe));
10079
10080         intel_crtc->cursor_base = base;
10081 }
10082
10083 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10084 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10085                                      const struct intel_plane_state *plane_state)
10086 {
10087         struct drm_device *dev = crtc->dev;
10088         struct drm_i915_private *dev_priv = dev->dev_private;
10089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10090         int pipe = intel_crtc->pipe;
10091         u32 base = intel_crtc->cursor_addr;
10092         u32 pos = 0;
10093
10094         if (plane_state) {
10095                 int x = plane_state->base.crtc_x;
10096                 int y = plane_state->base.crtc_y;
10097
10098                 if (x < 0) {
10099                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10100                         x = -x;
10101                 }
10102                 pos |= x << CURSOR_X_SHIFT;
10103
10104                 if (y < 0) {
10105                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10106                         y = -y;
10107                 }
10108                 pos |= y << CURSOR_Y_SHIFT;
10109
10110                 /* ILK+ do this automagically */
10111                 if (HAS_GMCH_DISPLAY(dev) &&
10112                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10113                         base += (plane_state->base.crtc_h *
10114                                  plane_state->base.crtc_w - 1) * 4;
10115                 }
10116         }
10117
10118         I915_WRITE(CURPOS(pipe), pos);
10119
10120         if (IS_845G(dev) || IS_I865G(dev))
10121                 i845_update_cursor(crtc, base, plane_state);
10122         else
10123                 i9xx_update_cursor(crtc, base, plane_state);
10124 }
10125
10126 static bool cursor_size_ok(struct drm_device *dev,
10127                            uint32_t width, uint32_t height)
10128 {
10129         if (width == 0 || height == 0)
10130                 return false;
10131
10132         /*
10133          * 845g/865g are special in that they are only limited by
10134          * the width of their cursors, the height is arbitrary up to
10135          * the precision of the register. Everything else requires
10136          * square cursors, limited to a few power-of-two sizes.
10137          */
10138         if (IS_845G(dev) || IS_I865G(dev)) {
10139                 if ((width & 63) != 0)
10140                         return false;
10141
10142                 if (width > (IS_845G(dev) ? 64 : 512))
10143                         return false;
10144
10145                 if (height > 1023)
10146                         return false;
10147         } else {
10148                 switch (width | height) {
10149                 case 256:
10150                 case 128:
10151                         if (IS_GEN2(dev))
10152                                 return false;
10153                 case 64:
10154                         break;
10155                 default:
10156                         return false;
10157                 }
10158         }
10159
10160         return true;
10161 }
10162
10163 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10164                                  u16 *blue, uint32_t start, uint32_t size)
10165 {
10166         int end = (start + size > 256) ? 256 : start + size, i;
10167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10168
10169         for (i = start; i < end; i++) {
10170                 intel_crtc->lut_r[i] = red[i] >> 8;
10171                 intel_crtc->lut_g[i] = green[i] >> 8;
10172                 intel_crtc->lut_b[i] = blue[i] >> 8;
10173         }
10174
10175         intel_crtc_load_lut(crtc);
10176 }
10177
10178 /* VESA 640x480x72Hz mode to set on the pipe */
10179 static struct drm_display_mode load_detect_mode = {
10180         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10181                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10182 };
10183
10184 struct drm_framebuffer *
10185 __intel_framebuffer_create(struct drm_device *dev,
10186                            struct drm_mode_fb_cmd2 *mode_cmd,
10187                            struct drm_i915_gem_object *obj)
10188 {
10189         struct intel_framebuffer *intel_fb;
10190         int ret;
10191
10192         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10193         if (!intel_fb)
10194                 return ERR_PTR(-ENOMEM);
10195
10196         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10197         if (ret)
10198                 goto err;
10199
10200         return &intel_fb->base;
10201
10202 err:
10203         kfree(intel_fb);
10204         return ERR_PTR(ret);
10205 }
10206
10207 static struct drm_framebuffer *
10208 intel_framebuffer_create(struct drm_device *dev,
10209                          struct drm_mode_fb_cmd2 *mode_cmd,
10210                          struct drm_i915_gem_object *obj)
10211 {
10212         struct drm_framebuffer *fb;
10213         int ret;
10214
10215         ret = i915_mutex_lock_interruptible(dev);
10216         if (ret)
10217                 return ERR_PTR(ret);
10218         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10219         mutex_unlock(&dev->struct_mutex);
10220
10221         return fb;
10222 }
10223
10224 static u32
10225 intel_framebuffer_pitch_for_width(int width, int bpp)
10226 {
10227         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10228         return ALIGN(pitch, 64);
10229 }
10230
10231 static u32
10232 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10233 {
10234         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10235         return PAGE_ALIGN(pitch * mode->vdisplay);
10236 }
10237
10238 static struct drm_framebuffer *
10239 intel_framebuffer_create_for_mode(struct drm_device *dev,
10240                                   struct drm_display_mode *mode,
10241                                   int depth, int bpp)
10242 {
10243         struct drm_framebuffer *fb;
10244         struct drm_i915_gem_object *obj;
10245         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10246
10247         obj = i915_gem_alloc_object(dev,
10248                                     intel_framebuffer_size_for_mode(mode, bpp));
10249         if (obj == NULL)
10250                 return ERR_PTR(-ENOMEM);
10251
10252         mode_cmd.width = mode->hdisplay;
10253         mode_cmd.height = mode->vdisplay;
10254         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10255                                                                 bpp);
10256         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10257
10258         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10259         if (IS_ERR(fb))
10260                 drm_gem_object_unreference_unlocked(&obj->base);
10261
10262         return fb;
10263 }
10264
10265 static struct drm_framebuffer *
10266 mode_fits_in_fbdev(struct drm_device *dev,
10267                    struct drm_display_mode *mode)
10268 {
10269 #ifdef CONFIG_DRM_FBDEV_EMULATION
10270         struct drm_i915_private *dev_priv = dev->dev_private;
10271         struct drm_i915_gem_object *obj;
10272         struct drm_framebuffer *fb;
10273
10274         if (!dev_priv->fbdev)
10275                 return NULL;
10276
10277         if (!dev_priv->fbdev->fb)
10278                 return NULL;
10279
10280         obj = dev_priv->fbdev->fb->obj;
10281         BUG_ON(!obj);
10282
10283         fb = &dev_priv->fbdev->fb->base;
10284         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10285                                                                fb->bits_per_pixel))
10286                 return NULL;
10287
10288         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10289                 return NULL;
10290
10291         drm_framebuffer_reference(fb);
10292         return fb;
10293 #else
10294         return NULL;
10295 #endif
10296 }
10297
10298 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10299                                            struct drm_crtc *crtc,
10300                                            struct drm_display_mode *mode,
10301                                            struct drm_framebuffer *fb,
10302                                            int x, int y)
10303 {
10304         struct drm_plane_state *plane_state;
10305         int hdisplay, vdisplay;
10306         int ret;
10307
10308         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10309         if (IS_ERR(plane_state))
10310                 return PTR_ERR(plane_state);
10311
10312         if (mode)
10313                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10314         else
10315                 hdisplay = vdisplay = 0;
10316
10317         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10318         if (ret)
10319                 return ret;
10320         drm_atomic_set_fb_for_plane(plane_state, fb);
10321         plane_state->crtc_x = 0;
10322         plane_state->crtc_y = 0;
10323         plane_state->crtc_w = hdisplay;
10324         plane_state->crtc_h = vdisplay;
10325         plane_state->src_x = x << 16;
10326         plane_state->src_y = y << 16;
10327         plane_state->src_w = hdisplay << 16;
10328         plane_state->src_h = vdisplay << 16;
10329
10330         return 0;
10331 }
10332
10333 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10334                                 struct drm_display_mode *mode,
10335                                 struct intel_load_detect_pipe *old,
10336                                 struct drm_modeset_acquire_ctx *ctx)
10337 {
10338         struct intel_crtc *intel_crtc;
10339         struct intel_encoder *intel_encoder =
10340                 intel_attached_encoder(connector);
10341         struct drm_crtc *possible_crtc;
10342         struct drm_encoder *encoder = &intel_encoder->base;
10343         struct drm_crtc *crtc = NULL;
10344         struct drm_device *dev = encoder->dev;
10345         struct drm_framebuffer *fb;
10346         struct drm_mode_config *config = &dev->mode_config;
10347         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10348         struct drm_connector_state *connector_state;
10349         struct intel_crtc_state *crtc_state;
10350         int ret, i = -1;
10351
10352         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10353                       connector->base.id, connector->name,
10354                       encoder->base.id, encoder->name);
10355
10356         old->restore_state = NULL;
10357
10358 retry:
10359         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10360         if (ret)
10361                 goto fail;
10362
10363         /*
10364          * Algorithm gets a little messy:
10365          *
10366          *   - if the connector already has an assigned crtc, use it (but make
10367          *     sure it's on first)
10368          *
10369          *   - try to find the first unused crtc that can drive this connector,
10370          *     and use that if we find one
10371          */
10372
10373         /* See if we already have a CRTC for this connector */
10374         if (connector->state->crtc) {
10375                 crtc = connector->state->crtc;
10376
10377                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10378                 if (ret)
10379                         goto fail;
10380
10381                 /* Make sure the crtc and connector are running */
10382                 goto found;
10383         }
10384
10385         /* Find an unused one (if possible) */
10386         for_each_crtc(dev, possible_crtc) {
10387                 i++;
10388                 if (!(encoder->possible_crtcs & (1 << i)))
10389                         continue;
10390
10391                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10392                 if (ret)
10393                         goto fail;
10394
10395                 if (possible_crtc->state->enable) {
10396                         drm_modeset_unlock(&possible_crtc->mutex);
10397                         continue;
10398                 }
10399
10400                 crtc = possible_crtc;
10401                 break;
10402         }
10403
10404         /*
10405          * If we didn't find an unused CRTC, don't use any.
10406          */
10407         if (!crtc) {
10408                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10409                 goto fail;
10410         }
10411
10412 found:
10413         intel_crtc = to_intel_crtc(crtc);
10414
10415         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10416         if (ret)
10417                 goto fail;
10418
10419         state = drm_atomic_state_alloc(dev);
10420         restore_state = drm_atomic_state_alloc(dev);
10421         if (!state || !restore_state) {
10422                 ret = -ENOMEM;
10423                 goto fail;
10424         }
10425
10426         state->acquire_ctx = ctx;
10427         restore_state->acquire_ctx = ctx;
10428
10429         connector_state = drm_atomic_get_connector_state(state, connector);
10430         if (IS_ERR(connector_state)) {
10431                 ret = PTR_ERR(connector_state);
10432                 goto fail;
10433         }
10434
10435         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10436         if (ret)
10437                 goto fail;
10438
10439         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10440         if (IS_ERR(crtc_state)) {
10441                 ret = PTR_ERR(crtc_state);
10442                 goto fail;
10443         }
10444
10445         crtc_state->base.active = crtc_state->base.enable = true;
10446
10447         if (!mode)
10448                 mode = &load_detect_mode;
10449
10450         /* We need a framebuffer large enough to accommodate all accesses
10451          * that the plane may generate whilst we perform load detection.
10452          * We can not rely on the fbcon either being present (we get called
10453          * during its initialisation to detect all boot displays, or it may
10454          * not even exist) or that it is large enough to satisfy the
10455          * requested mode.
10456          */
10457         fb = mode_fits_in_fbdev(dev, mode);
10458         if (fb == NULL) {
10459                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10460                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10461         } else
10462                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10463         if (IS_ERR(fb)) {
10464                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10465                 goto fail;
10466         }
10467
10468         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10469         if (ret)
10470                 goto fail;
10471
10472         drm_framebuffer_unreference(fb);
10473
10474         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10475         if (ret)
10476                 goto fail;
10477
10478         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10479         if (!ret)
10480                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10481         if (!ret)
10482                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10483         if (ret) {
10484                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10485                 goto fail;
10486         }
10487
10488         ret = drm_atomic_commit(state);
10489         if (ret) {
10490                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10491                 goto fail;
10492         }
10493
10494         old->restore_state = restore_state;
10495
10496         /* let the connector get through one full cycle before testing */
10497         intel_wait_for_vblank(dev, intel_crtc->pipe);
10498         return true;
10499
10500 fail:
10501         drm_atomic_state_free(state);
10502         drm_atomic_state_free(restore_state);
10503         restore_state = state = NULL;
10504
10505         if (ret == -EDEADLK) {
10506                 drm_modeset_backoff(ctx);
10507                 goto retry;
10508         }
10509
10510         return false;
10511 }
10512
10513 void intel_release_load_detect_pipe(struct drm_connector *connector,
10514                                     struct intel_load_detect_pipe *old,
10515                                     struct drm_modeset_acquire_ctx *ctx)
10516 {
10517         struct intel_encoder *intel_encoder =
10518                 intel_attached_encoder(connector);
10519         struct drm_encoder *encoder = &intel_encoder->base;
10520         struct drm_atomic_state *state = old->restore_state;
10521         int ret;
10522
10523         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10524                       connector->base.id, connector->name,
10525                       encoder->base.id, encoder->name);
10526
10527         if (!state)
10528                 return;
10529
10530         ret = drm_atomic_commit(state);
10531         if (ret) {
10532                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10533                 drm_atomic_state_free(state);
10534         }
10535 }
10536
10537 static int i9xx_pll_refclk(struct drm_device *dev,
10538                            const struct intel_crtc_state *pipe_config)
10539 {
10540         struct drm_i915_private *dev_priv = dev->dev_private;
10541         u32 dpll = pipe_config->dpll_hw_state.dpll;
10542
10543         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10544                 return dev_priv->vbt.lvds_ssc_freq;
10545         else if (HAS_PCH_SPLIT(dev))
10546                 return 120000;
10547         else if (!IS_GEN2(dev))
10548                 return 96000;
10549         else
10550                 return 48000;
10551 }
10552
10553 /* Returns the clock of the currently programmed mode of the given pipe. */
10554 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10555                                 struct intel_crtc_state *pipe_config)
10556 {
10557         struct drm_device *dev = crtc->base.dev;
10558         struct drm_i915_private *dev_priv = dev->dev_private;
10559         int pipe = pipe_config->cpu_transcoder;
10560         u32 dpll = pipe_config->dpll_hw_state.dpll;
10561         u32 fp;
10562         intel_clock_t clock;
10563         int port_clock;
10564         int refclk = i9xx_pll_refclk(dev, pipe_config);
10565
10566         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10567                 fp = pipe_config->dpll_hw_state.fp0;
10568         else
10569                 fp = pipe_config->dpll_hw_state.fp1;
10570
10571         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10572         if (IS_PINEVIEW(dev)) {
10573                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10574                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10575         } else {
10576                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10577                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10578         }
10579
10580         if (!IS_GEN2(dev)) {
10581                 if (IS_PINEVIEW(dev))
10582                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10583                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10584                 else
10585                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10586                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10587
10588                 switch (dpll & DPLL_MODE_MASK) {
10589                 case DPLLB_MODE_DAC_SERIAL:
10590                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10591                                 5 : 10;
10592                         break;
10593                 case DPLLB_MODE_LVDS:
10594                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10595                                 7 : 14;
10596                         break;
10597                 default:
10598                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10599                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10600                         return;
10601                 }
10602
10603                 if (IS_PINEVIEW(dev))
10604                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10605                 else
10606                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10607         } else {
10608                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10609                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10610
10611                 if (is_lvds) {
10612                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10613                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10614
10615                         if (lvds & LVDS_CLKB_POWER_UP)
10616                                 clock.p2 = 7;
10617                         else
10618                                 clock.p2 = 14;
10619                 } else {
10620                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10621                                 clock.p1 = 2;
10622                         else {
10623                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10624                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10625                         }
10626                         if (dpll & PLL_P2_DIVIDE_BY_4)
10627                                 clock.p2 = 4;
10628                         else
10629                                 clock.p2 = 2;
10630                 }
10631
10632                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10633         }
10634
10635         /*
10636          * This value includes pixel_multiplier. We will use
10637          * port_clock to compute adjusted_mode.crtc_clock in the
10638          * encoder's get_config() function.
10639          */
10640         pipe_config->port_clock = port_clock;
10641 }
10642
10643 int intel_dotclock_calculate(int link_freq,
10644                              const struct intel_link_m_n *m_n)
10645 {
10646         /*
10647          * The calculation for the data clock is:
10648          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10649          * But we want to avoid losing precison if possible, so:
10650          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10651          *
10652          * and the link clock is simpler:
10653          * link_clock = (m * link_clock) / n
10654          */
10655
10656         if (!m_n->link_n)
10657                 return 0;
10658
10659         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10660 }
10661
10662 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10663                                    struct intel_crtc_state *pipe_config)
10664 {
10665         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10666
10667         /* read out port_clock from the DPLL */
10668         i9xx_crtc_clock_get(crtc, pipe_config);
10669
10670         /*
10671          * In case there is an active pipe without active ports,
10672          * we may need some idea for the dotclock anyway.
10673          * Calculate one based on the FDI configuration.
10674          */
10675         pipe_config->base.adjusted_mode.crtc_clock =
10676                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10677                                          &pipe_config->fdi_m_n);
10678 }
10679
10680 /** Returns the currently programmed mode of the given pipe. */
10681 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10682                                              struct drm_crtc *crtc)
10683 {
10684         struct drm_i915_private *dev_priv = dev->dev_private;
10685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10686         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10687         struct drm_display_mode *mode;
10688         struct intel_crtc_state *pipe_config;
10689         int htot = I915_READ(HTOTAL(cpu_transcoder));
10690         int hsync = I915_READ(HSYNC(cpu_transcoder));
10691         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10692         int vsync = I915_READ(VSYNC(cpu_transcoder));
10693         enum pipe pipe = intel_crtc->pipe;
10694
10695         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10696         if (!mode)
10697                 return NULL;
10698
10699         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10700         if (!pipe_config) {
10701                 kfree(mode);
10702                 return NULL;
10703         }
10704
10705         /*
10706          * Construct a pipe_config sufficient for getting the clock info
10707          * back out of crtc_clock_get.
10708          *
10709          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10710          * to use a real value here instead.
10711          */
10712         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10713         pipe_config->pixel_multiplier = 1;
10714         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10715         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10716         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10717         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10718
10719         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10720         mode->hdisplay = (htot & 0xffff) + 1;
10721         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10722         mode->hsync_start = (hsync & 0xffff) + 1;
10723         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10724         mode->vdisplay = (vtot & 0xffff) + 1;
10725         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10726         mode->vsync_start = (vsync & 0xffff) + 1;
10727         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10728
10729         drm_mode_set_name(mode);
10730
10731         kfree(pipe_config);
10732
10733         return mode;
10734 }
10735
10736 void intel_mark_busy(struct drm_device *dev)
10737 {
10738         struct drm_i915_private *dev_priv = dev->dev_private;
10739
10740         if (dev_priv->mm.busy)
10741                 return;
10742
10743         intel_runtime_pm_get(dev_priv);
10744         i915_update_gfx_val(dev_priv);
10745         if (INTEL_INFO(dev)->gen >= 6)
10746                 gen6_rps_busy(dev_priv);
10747         dev_priv->mm.busy = true;
10748 }
10749
10750 void intel_mark_idle(struct drm_device *dev)
10751 {
10752         struct drm_i915_private *dev_priv = dev->dev_private;
10753
10754         if (!dev_priv->mm.busy)
10755                 return;
10756
10757         dev_priv->mm.busy = false;
10758
10759         if (INTEL_INFO(dev)->gen >= 6)
10760                 gen6_rps_idle(dev->dev_private);
10761
10762         intel_runtime_pm_put(dev_priv);
10763 }
10764
10765 static void intel_crtc_destroy(struct drm_crtc *crtc)
10766 {
10767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10768         struct drm_device *dev = crtc->dev;
10769         struct intel_unpin_work *work;
10770
10771         spin_lock_irq(&dev->event_lock);
10772         work = intel_crtc->unpin_work;
10773         intel_crtc->unpin_work = NULL;
10774         spin_unlock_irq(&dev->event_lock);
10775
10776         if (work) {
10777                 cancel_work_sync(&work->work);
10778                 kfree(work);
10779         }
10780
10781         drm_crtc_cleanup(crtc);
10782
10783         kfree(intel_crtc);
10784 }
10785
10786 static void intel_unpin_work_fn(struct work_struct *__work)
10787 {
10788         struct intel_unpin_work *work =
10789                 container_of(__work, struct intel_unpin_work, work);
10790         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10791         struct drm_device *dev = crtc->base.dev;
10792         struct drm_plane *primary = crtc->base.primary;
10793
10794         mutex_lock(&dev->struct_mutex);
10795         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10796         drm_gem_object_unreference(&work->pending_flip_obj->base);
10797
10798         if (work->flip_queued_req)
10799                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10800         mutex_unlock(&dev->struct_mutex);
10801
10802         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10803         intel_fbc_post_update(crtc);
10804         drm_framebuffer_unreference(work->old_fb);
10805
10806         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10807         atomic_dec(&crtc->unpin_work_count);
10808
10809         kfree(work);
10810 }
10811
10812 static void do_intel_finish_page_flip(struct drm_device *dev,
10813                                       struct drm_crtc *crtc)
10814 {
10815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10816         struct intel_unpin_work *work;
10817         unsigned long flags;
10818
10819         /* Ignore early vblank irqs */
10820         if (intel_crtc == NULL)
10821                 return;
10822
10823         /*
10824          * This is called both by irq handlers and the reset code (to complete
10825          * lost pageflips) so needs the full irqsave spinlocks.
10826          */
10827         spin_lock_irqsave(&dev->event_lock, flags);
10828         work = intel_crtc->unpin_work;
10829
10830         /* Ensure we don't miss a work->pending update ... */
10831         smp_rmb();
10832
10833         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10834                 spin_unlock_irqrestore(&dev->event_lock, flags);
10835                 return;
10836         }
10837
10838         page_flip_completed(intel_crtc);
10839
10840         spin_unlock_irqrestore(&dev->event_lock, flags);
10841 }
10842
10843 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10844 {
10845         struct drm_i915_private *dev_priv = dev->dev_private;
10846         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10847
10848         do_intel_finish_page_flip(dev, crtc);
10849 }
10850
10851 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10852 {
10853         struct drm_i915_private *dev_priv = dev->dev_private;
10854         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10855
10856         do_intel_finish_page_flip(dev, crtc);
10857 }
10858
10859 /* Is 'a' after or equal to 'b'? */
10860 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10861 {
10862         return !((a - b) & 0x80000000);
10863 }
10864
10865 static bool page_flip_finished(struct intel_crtc *crtc)
10866 {
10867         struct drm_device *dev = crtc->base.dev;
10868         struct drm_i915_private *dev_priv = dev->dev_private;
10869
10870         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10871             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10872                 return true;
10873
10874         /*
10875          * The relevant registers doen't exist on pre-ctg.
10876          * As the flip done interrupt doesn't trigger for mmio
10877          * flips on gmch platforms, a flip count check isn't
10878          * really needed there. But since ctg has the registers,
10879          * include it in the check anyway.
10880          */
10881         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10882                 return true;
10883
10884         /*
10885          * BDW signals flip done immediately if the plane
10886          * is disabled, even if the plane enable is already
10887          * armed to occur at the next vblank :(
10888          */
10889
10890         /*
10891          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10892          * used the same base address. In that case the mmio flip might
10893          * have completed, but the CS hasn't even executed the flip yet.
10894          *
10895          * A flip count check isn't enough as the CS might have updated
10896          * the base address just after start of vblank, but before we
10897          * managed to process the interrupt. This means we'd complete the
10898          * CS flip too soon.
10899          *
10900          * Combining both checks should get us a good enough result. It may
10901          * still happen that the CS flip has been executed, but has not
10902          * yet actually completed. But in case the base address is the same
10903          * anyway, we don't really care.
10904          */
10905         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10906                 crtc->unpin_work->gtt_offset &&
10907                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10908                                     crtc->unpin_work->flip_count);
10909 }
10910
10911 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10912 {
10913         struct drm_i915_private *dev_priv = dev->dev_private;
10914         struct intel_crtc *intel_crtc =
10915                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10916         unsigned long flags;
10917
10918
10919         /*
10920          * This is called both by irq handlers and the reset code (to complete
10921          * lost pageflips) so needs the full irqsave spinlocks.
10922          *
10923          * NB: An MMIO update of the plane base pointer will also
10924          * generate a page-flip completion irq, i.e. every modeset
10925          * is also accompanied by a spurious intel_prepare_page_flip().
10926          */
10927         spin_lock_irqsave(&dev->event_lock, flags);
10928         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10929                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10930         spin_unlock_irqrestore(&dev->event_lock, flags);
10931 }
10932
10933 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10934 {
10935         /* Ensure that the work item is consistent when activating it ... */
10936         smp_wmb();
10937         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10938         /* and that it is marked active as soon as the irq could fire. */
10939         smp_wmb();
10940 }
10941
10942 static int intel_gen2_queue_flip(struct drm_device *dev,
10943                                  struct drm_crtc *crtc,
10944                                  struct drm_framebuffer *fb,
10945                                  struct drm_i915_gem_object *obj,
10946                                  struct drm_i915_gem_request *req,
10947                                  uint32_t flags)
10948 {
10949         struct intel_engine_cs *ring = req->ring;
10950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10951         u32 flip_mask;
10952         int ret;
10953
10954         ret = intel_ring_begin(req, 6);
10955         if (ret)
10956                 return ret;
10957
10958         /* Can't queue multiple flips, so wait for the previous
10959          * one to finish before executing the next.
10960          */
10961         if (intel_crtc->plane)
10962                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10963         else
10964                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10965         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10966         intel_ring_emit(ring, MI_NOOP);
10967         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10968                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10969         intel_ring_emit(ring, fb->pitches[0]);
10970         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10971         intel_ring_emit(ring, 0); /* aux display base address, unused */
10972
10973         intel_mark_page_flip_active(intel_crtc->unpin_work);
10974         return 0;
10975 }
10976
10977 static int intel_gen3_queue_flip(struct drm_device *dev,
10978                                  struct drm_crtc *crtc,
10979                                  struct drm_framebuffer *fb,
10980                                  struct drm_i915_gem_object *obj,
10981                                  struct drm_i915_gem_request *req,
10982                                  uint32_t flags)
10983 {
10984         struct intel_engine_cs *ring = req->ring;
10985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10986         u32 flip_mask;
10987         int ret;
10988
10989         ret = intel_ring_begin(req, 6);
10990         if (ret)
10991                 return ret;
10992
10993         if (intel_crtc->plane)
10994                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10995         else
10996                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10997         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10998         intel_ring_emit(ring, MI_NOOP);
10999         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11000                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11001         intel_ring_emit(ring, fb->pitches[0]);
11002         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11003         intel_ring_emit(ring, MI_NOOP);
11004
11005         intel_mark_page_flip_active(intel_crtc->unpin_work);
11006         return 0;
11007 }
11008
11009 static int intel_gen4_queue_flip(struct drm_device *dev,
11010                                  struct drm_crtc *crtc,
11011                                  struct drm_framebuffer *fb,
11012                                  struct drm_i915_gem_object *obj,
11013                                  struct drm_i915_gem_request *req,
11014                                  uint32_t flags)
11015 {
11016         struct intel_engine_cs *ring = req->ring;
11017         struct drm_i915_private *dev_priv = dev->dev_private;
11018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11019         uint32_t pf, pipesrc;
11020         int ret;
11021
11022         ret = intel_ring_begin(req, 4);
11023         if (ret)
11024                 return ret;
11025
11026         /* i965+ uses the linear or tiled offsets from the
11027          * Display Registers (which do not change across a page-flip)
11028          * so we need only reprogram the base address.
11029          */
11030         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11031                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11032         intel_ring_emit(ring, fb->pitches[0]);
11033         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11034                         obj->tiling_mode);
11035
11036         /* XXX Enabling the panel-fitter across page-flip is so far
11037          * untested on non-native modes, so ignore it for now.
11038          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11039          */
11040         pf = 0;
11041         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11042         intel_ring_emit(ring, pf | pipesrc);
11043
11044         intel_mark_page_flip_active(intel_crtc->unpin_work);
11045         return 0;
11046 }
11047
11048 static int intel_gen6_queue_flip(struct drm_device *dev,
11049                                  struct drm_crtc *crtc,
11050                                  struct drm_framebuffer *fb,
11051                                  struct drm_i915_gem_object *obj,
11052                                  struct drm_i915_gem_request *req,
11053                                  uint32_t flags)
11054 {
11055         struct intel_engine_cs *ring = req->ring;
11056         struct drm_i915_private *dev_priv = dev->dev_private;
11057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11058         uint32_t pf, pipesrc;
11059         int ret;
11060
11061         ret = intel_ring_begin(req, 4);
11062         if (ret)
11063                 return ret;
11064
11065         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11066                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11067         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11068         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11069
11070         /* Contrary to the suggestions in the documentation,
11071          * "Enable Panel Fitter" does not seem to be required when page
11072          * flipping with a non-native mode, and worse causes a normal
11073          * modeset to fail.
11074          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11075          */
11076         pf = 0;
11077         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11078         intel_ring_emit(ring, pf | pipesrc);
11079
11080         intel_mark_page_flip_active(intel_crtc->unpin_work);
11081         return 0;
11082 }
11083
11084 static int intel_gen7_queue_flip(struct drm_device *dev,
11085                                  struct drm_crtc *crtc,
11086                                  struct drm_framebuffer *fb,
11087                                  struct drm_i915_gem_object *obj,
11088                                  struct drm_i915_gem_request *req,
11089                                  uint32_t flags)
11090 {
11091         struct intel_engine_cs *ring = req->ring;
11092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11093         uint32_t plane_bit = 0;
11094         int len, ret;
11095
11096         switch (intel_crtc->plane) {
11097         case PLANE_A:
11098                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11099                 break;
11100         case PLANE_B:
11101                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11102                 break;
11103         case PLANE_C:
11104                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11105                 break;
11106         default:
11107                 WARN_ONCE(1, "unknown plane in flip command\n");
11108                 return -ENODEV;
11109         }
11110
11111         len = 4;
11112         if (ring->id == RCS) {
11113                 len += 6;
11114                 /*
11115                  * On Gen 8, SRM is now taking an extra dword to accommodate
11116                  * 48bits addresses, and we need a NOOP for the batch size to
11117                  * stay even.
11118                  */
11119                 if (IS_GEN8(dev))
11120                         len += 2;
11121         }
11122
11123         /*
11124          * BSpec MI_DISPLAY_FLIP for IVB:
11125          * "The full packet must be contained within the same cache line."
11126          *
11127          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11128          * cacheline, if we ever start emitting more commands before
11129          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11130          * then do the cacheline alignment, and finally emit the
11131          * MI_DISPLAY_FLIP.
11132          */
11133         ret = intel_ring_cacheline_align(req);
11134         if (ret)
11135                 return ret;
11136
11137         ret = intel_ring_begin(req, len);
11138         if (ret)
11139                 return ret;
11140
11141         /* Unmask the flip-done completion message. Note that the bspec says that
11142          * we should do this for both the BCS and RCS, and that we must not unmask
11143          * more than one flip event at any time (or ensure that one flip message
11144          * can be sent by waiting for flip-done prior to queueing new flips).
11145          * Experimentation says that BCS works despite DERRMR masking all
11146          * flip-done completion events and that unmasking all planes at once
11147          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11148          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11149          */
11150         if (ring->id == RCS) {
11151                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11152                 intel_ring_emit_reg(ring, DERRMR);
11153                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11154                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11155                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11156                 if (IS_GEN8(dev))
11157                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11158                                               MI_SRM_LRM_GLOBAL_GTT);
11159                 else
11160                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11161                                               MI_SRM_LRM_GLOBAL_GTT);
11162                 intel_ring_emit_reg(ring, DERRMR);
11163                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11164                 if (IS_GEN8(dev)) {
11165                         intel_ring_emit(ring, 0);
11166                         intel_ring_emit(ring, MI_NOOP);
11167                 }
11168         }
11169
11170         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11171         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11172         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11173         intel_ring_emit(ring, (MI_NOOP));
11174
11175         intel_mark_page_flip_active(intel_crtc->unpin_work);
11176         return 0;
11177 }
11178
11179 static bool use_mmio_flip(struct intel_engine_cs *ring,
11180                           struct drm_i915_gem_object *obj)
11181 {
11182         /*
11183          * This is not being used for older platforms, because
11184          * non-availability of flip done interrupt forces us to use
11185          * CS flips. Older platforms derive flip done using some clever
11186          * tricks involving the flip_pending status bits and vblank irqs.
11187          * So using MMIO flips there would disrupt this mechanism.
11188          */
11189
11190         if (ring == NULL)
11191                 return true;
11192
11193         if (INTEL_INFO(ring->dev)->gen < 5)
11194                 return false;
11195
11196         if (i915.use_mmio_flip < 0)
11197                 return false;
11198         else if (i915.use_mmio_flip > 0)
11199                 return true;
11200         else if (i915.enable_execlists)
11201                 return true;
11202         else if (obj->base.dma_buf &&
11203                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11204                                                        false))
11205                 return true;
11206         else
11207                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11208 }
11209
11210 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11211                              unsigned int rotation,
11212                              struct intel_unpin_work *work)
11213 {
11214         struct drm_device *dev = intel_crtc->base.dev;
11215         struct drm_i915_private *dev_priv = dev->dev_private;
11216         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11217         const enum pipe pipe = intel_crtc->pipe;
11218         u32 ctl, stride, tile_height;
11219
11220         ctl = I915_READ(PLANE_CTL(pipe, 0));
11221         ctl &= ~PLANE_CTL_TILED_MASK;
11222         switch (fb->modifier[0]) {
11223         case DRM_FORMAT_MOD_NONE:
11224                 break;
11225         case I915_FORMAT_MOD_X_TILED:
11226                 ctl |= PLANE_CTL_TILED_X;
11227                 break;
11228         case I915_FORMAT_MOD_Y_TILED:
11229                 ctl |= PLANE_CTL_TILED_Y;
11230                 break;
11231         case I915_FORMAT_MOD_Yf_TILED:
11232                 ctl |= PLANE_CTL_TILED_YF;
11233                 break;
11234         default:
11235                 MISSING_CASE(fb->modifier[0]);
11236         }
11237
11238         /*
11239          * The stride is either expressed as a multiple of 64 bytes chunks for
11240          * linear buffers or in number of tiles for tiled buffers.
11241          */
11242         if (intel_rotation_90_or_270(rotation)) {
11243                 /* stride = Surface height in tiles */
11244                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11245                 stride = DIV_ROUND_UP(fb->height, tile_height);
11246         } else {
11247                 stride = fb->pitches[0] /
11248                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11249                                                   fb->pixel_format);
11250         }
11251
11252         /*
11253          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11254          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11255          */
11256         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11257         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11258
11259         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11260         POSTING_READ(PLANE_SURF(pipe, 0));
11261 }
11262
11263 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11264                              struct intel_unpin_work *work)
11265 {
11266         struct drm_device *dev = intel_crtc->base.dev;
11267         struct drm_i915_private *dev_priv = dev->dev_private;
11268         struct intel_framebuffer *intel_fb =
11269                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11270         struct drm_i915_gem_object *obj = intel_fb->obj;
11271         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11272         u32 dspcntr;
11273
11274         dspcntr = I915_READ(reg);
11275
11276         if (obj->tiling_mode != I915_TILING_NONE)
11277                 dspcntr |= DISPPLANE_TILED;
11278         else
11279                 dspcntr &= ~DISPPLANE_TILED;
11280
11281         I915_WRITE(reg, dspcntr);
11282
11283         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11284         POSTING_READ(DSPSURF(intel_crtc->plane));
11285 }
11286
11287 /*
11288  * XXX: This is the temporary way to update the plane registers until we get
11289  * around to using the usual plane update functions for MMIO flips
11290  */
11291 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11292 {
11293         struct intel_crtc *crtc = mmio_flip->crtc;
11294         struct intel_unpin_work *work;
11295
11296         spin_lock_irq(&crtc->base.dev->event_lock);
11297         work = crtc->unpin_work;
11298         spin_unlock_irq(&crtc->base.dev->event_lock);
11299         if (work == NULL)
11300                 return;
11301
11302         intel_mark_page_flip_active(work);
11303
11304         intel_pipe_update_start(crtc);
11305
11306         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11307                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11308         else
11309                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11310                 ilk_do_mmio_flip(crtc, work);
11311
11312         intel_pipe_update_end(crtc);
11313 }
11314
11315 static void intel_mmio_flip_work_func(struct work_struct *work)
11316 {
11317         struct intel_mmio_flip *mmio_flip =
11318                 container_of(work, struct intel_mmio_flip, work);
11319         struct intel_framebuffer *intel_fb =
11320                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11321         struct drm_i915_gem_object *obj = intel_fb->obj;
11322
11323         if (mmio_flip->req) {
11324                 WARN_ON(__i915_wait_request(mmio_flip->req,
11325                                             mmio_flip->crtc->reset_counter,
11326                                             false, NULL,
11327                                             &mmio_flip->i915->rps.mmioflips));
11328                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11329         }
11330
11331         /* For framebuffer backed by dmabuf, wait for fence */
11332         if (obj->base.dma_buf)
11333                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11334                                                             false, false,
11335                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11336
11337         intel_do_mmio_flip(mmio_flip);
11338         kfree(mmio_flip);
11339 }
11340
11341 static int intel_queue_mmio_flip(struct drm_device *dev,
11342                                  struct drm_crtc *crtc,
11343                                  struct drm_i915_gem_object *obj)
11344 {
11345         struct intel_mmio_flip *mmio_flip;
11346
11347         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11348         if (mmio_flip == NULL)
11349                 return -ENOMEM;
11350
11351         mmio_flip->i915 = to_i915(dev);
11352         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11353         mmio_flip->crtc = to_intel_crtc(crtc);
11354         mmio_flip->rotation = crtc->primary->state->rotation;
11355
11356         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11357         schedule_work(&mmio_flip->work);
11358
11359         return 0;
11360 }
11361
11362 static int intel_default_queue_flip(struct drm_device *dev,
11363                                     struct drm_crtc *crtc,
11364                                     struct drm_framebuffer *fb,
11365                                     struct drm_i915_gem_object *obj,
11366                                     struct drm_i915_gem_request *req,
11367                                     uint32_t flags)
11368 {
11369         return -ENODEV;
11370 }
11371
11372 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11373                                          struct drm_crtc *crtc)
11374 {
11375         struct drm_i915_private *dev_priv = dev->dev_private;
11376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11377         struct intel_unpin_work *work = intel_crtc->unpin_work;
11378         u32 addr;
11379
11380         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11381                 return true;
11382
11383         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11384                 return false;
11385
11386         if (!work->enable_stall_check)
11387                 return false;
11388
11389         if (work->flip_ready_vblank == 0) {
11390                 if (work->flip_queued_req &&
11391                     !i915_gem_request_completed(work->flip_queued_req, true))
11392                         return false;
11393
11394                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11395         }
11396
11397         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11398                 return false;
11399
11400         /* Potential stall - if we see that the flip has happened,
11401          * assume a missed interrupt. */
11402         if (INTEL_INFO(dev)->gen >= 4)
11403                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11404         else
11405                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11406
11407         /* There is a potential issue here with a false positive after a flip
11408          * to the same address. We could address this by checking for a
11409          * non-incrementing frame counter.
11410          */
11411         return addr == work->gtt_offset;
11412 }
11413
11414 void intel_check_page_flip(struct drm_device *dev, int pipe)
11415 {
11416         struct drm_i915_private *dev_priv = dev->dev_private;
11417         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11419         struct intel_unpin_work *work;
11420
11421         WARN_ON(!in_interrupt());
11422
11423         if (crtc == NULL)
11424                 return;
11425
11426         spin_lock(&dev->event_lock);
11427         work = intel_crtc->unpin_work;
11428         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11429                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11430                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11431                 page_flip_completed(intel_crtc);
11432                 work = NULL;
11433         }
11434         if (work != NULL &&
11435             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11436                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11437         spin_unlock(&dev->event_lock);
11438 }
11439
11440 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11441                                 struct drm_framebuffer *fb,
11442                                 struct drm_pending_vblank_event *event,
11443                                 uint32_t page_flip_flags)
11444 {
11445         struct drm_device *dev = crtc->dev;
11446         struct drm_i915_private *dev_priv = dev->dev_private;
11447         struct drm_framebuffer *old_fb = crtc->primary->fb;
11448         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11450         struct drm_plane *primary = crtc->primary;
11451         enum pipe pipe = intel_crtc->pipe;
11452         struct intel_unpin_work *work;
11453         struct intel_engine_cs *ring;
11454         bool mmio_flip;
11455         struct drm_i915_gem_request *request = NULL;
11456         int ret;
11457
11458         /*
11459          * drm_mode_page_flip_ioctl() should already catch this, but double
11460          * check to be safe.  In the future we may enable pageflipping from
11461          * a disabled primary plane.
11462          */
11463         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11464                 return -EBUSY;
11465
11466         /* Can't change pixel format via MI display flips. */
11467         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11468                 return -EINVAL;
11469
11470         /*
11471          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11472          * Note that pitch changes could also affect these register.
11473          */
11474         if (INTEL_INFO(dev)->gen > 3 &&
11475             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11476              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11477                 return -EINVAL;
11478
11479         if (i915_terminally_wedged(&dev_priv->gpu_error))
11480                 goto out_hang;
11481
11482         work = kzalloc(sizeof(*work), GFP_KERNEL);
11483         if (work == NULL)
11484                 return -ENOMEM;
11485
11486         work->event = event;
11487         work->crtc = crtc;
11488         work->old_fb = old_fb;
11489         INIT_WORK(&work->work, intel_unpin_work_fn);
11490
11491         ret = drm_crtc_vblank_get(crtc);
11492         if (ret)
11493                 goto free_work;
11494
11495         /* We borrow the event spin lock for protecting unpin_work */
11496         spin_lock_irq(&dev->event_lock);
11497         if (intel_crtc->unpin_work) {
11498                 /* Before declaring the flip queue wedged, check if
11499                  * the hardware completed the operation behind our backs.
11500                  */
11501                 if (__intel_pageflip_stall_check(dev, crtc)) {
11502                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11503                         page_flip_completed(intel_crtc);
11504                 } else {
11505                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11506                         spin_unlock_irq(&dev->event_lock);
11507
11508                         drm_crtc_vblank_put(crtc);
11509                         kfree(work);
11510                         return -EBUSY;
11511                 }
11512         }
11513         intel_crtc->unpin_work = work;
11514         spin_unlock_irq(&dev->event_lock);
11515
11516         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11517                 flush_workqueue(dev_priv->wq);
11518
11519         /* Reference the objects for the scheduled work. */
11520         drm_framebuffer_reference(work->old_fb);
11521         drm_gem_object_reference(&obj->base);
11522
11523         crtc->primary->fb = fb;
11524         update_state_fb(crtc->primary);
11525         intel_fbc_pre_update(intel_crtc);
11526
11527         work->pending_flip_obj = obj;
11528
11529         ret = i915_mutex_lock_interruptible(dev);
11530         if (ret)
11531                 goto cleanup;
11532
11533         atomic_inc(&intel_crtc->unpin_work_count);
11534         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11535
11536         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11537                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11538
11539         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11540                 ring = &dev_priv->ring[BCS];
11541                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11542                         /* vlv: DISPLAY_FLIP fails to change tiling */
11543                         ring = NULL;
11544         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11545                 ring = &dev_priv->ring[BCS];
11546         } else if (INTEL_INFO(dev)->gen >= 7) {
11547                 ring = i915_gem_request_get_ring(obj->last_write_req);
11548                 if (ring == NULL || ring->id != RCS)
11549                         ring = &dev_priv->ring[BCS];
11550         } else {
11551                 ring = &dev_priv->ring[RCS];
11552         }
11553
11554         mmio_flip = use_mmio_flip(ring, obj);
11555
11556         /* When using CS flips, we want to emit semaphores between rings.
11557          * However, when using mmio flips we will create a task to do the
11558          * synchronisation, so all we want here is to pin the framebuffer
11559          * into the display plane and skip any waits.
11560          */
11561         if (!mmio_flip) {
11562                 ret = i915_gem_object_sync(obj, ring, &request);
11563                 if (ret)
11564                         goto cleanup_pending;
11565         }
11566
11567         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11568         if (ret)
11569                 goto cleanup_pending;
11570
11571         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11572                                                   obj, 0);
11573         work->gtt_offset += intel_crtc->dspaddr_offset;
11574
11575         if (mmio_flip) {
11576                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11577                 if (ret)
11578                         goto cleanup_unpin;
11579
11580                 i915_gem_request_assign(&work->flip_queued_req,
11581                                         obj->last_write_req);
11582         } else {
11583                 if (!request) {
11584                         request = i915_gem_request_alloc(ring, NULL);
11585                         if (IS_ERR(request)) {
11586                                 ret = PTR_ERR(request);
11587                                 goto cleanup_unpin;
11588                         }
11589                 }
11590
11591                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11592                                                    page_flip_flags);
11593                 if (ret)
11594                         goto cleanup_unpin;
11595
11596                 i915_gem_request_assign(&work->flip_queued_req, request);
11597         }
11598
11599         if (request)
11600                 i915_add_request_no_flush(request);
11601
11602         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11603         work->enable_stall_check = true;
11604
11605         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11606                           to_intel_plane(primary)->frontbuffer_bit);
11607         mutex_unlock(&dev->struct_mutex);
11608
11609         intel_frontbuffer_flip_prepare(dev,
11610                                        to_intel_plane(primary)->frontbuffer_bit);
11611
11612         trace_i915_flip_request(intel_crtc->plane, obj);
11613
11614         return 0;
11615
11616 cleanup_unpin:
11617         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11618 cleanup_pending:
11619         if (!IS_ERR_OR_NULL(request))
11620                 i915_gem_request_cancel(request);
11621         atomic_dec(&intel_crtc->unpin_work_count);
11622         mutex_unlock(&dev->struct_mutex);
11623 cleanup:
11624         crtc->primary->fb = old_fb;
11625         update_state_fb(crtc->primary);
11626
11627         drm_gem_object_unreference_unlocked(&obj->base);
11628         drm_framebuffer_unreference(work->old_fb);
11629
11630         spin_lock_irq(&dev->event_lock);
11631         intel_crtc->unpin_work = NULL;
11632         spin_unlock_irq(&dev->event_lock);
11633
11634         drm_crtc_vblank_put(crtc);
11635 free_work:
11636         kfree(work);
11637
11638         if (ret == -EIO) {
11639                 struct drm_atomic_state *state;
11640                 struct drm_plane_state *plane_state;
11641
11642 out_hang:
11643                 state = drm_atomic_state_alloc(dev);
11644                 if (!state)
11645                         return -ENOMEM;
11646                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11647
11648 retry:
11649                 plane_state = drm_atomic_get_plane_state(state, primary);
11650                 ret = PTR_ERR_OR_ZERO(plane_state);
11651                 if (!ret) {
11652                         drm_atomic_set_fb_for_plane(plane_state, fb);
11653
11654                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11655                         if (!ret)
11656                                 ret = drm_atomic_commit(state);
11657                 }
11658
11659                 if (ret == -EDEADLK) {
11660                         drm_modeset_backoff(state->acquire_ctx);
11661                         drm_atomic_state_clear(state);
11662                         goto retry;
11663                 }
11664
11665                 if (ret)
11666                         drm_atomic_state_free(state);
11667
11668                 if (ret == 0 && event) {
11669                         spin_lock_irq(&dev->event_lock);
11670                         drm_send_vblank_event(dev, pipe, event);
11671                         spin_unlock_irq(&dev->event_lock);
11672                 }
11673         }
11674         return ret;
11675 }
11676
11677
11678 /**
11679  * intel_wm_need_update - Check whether watermarks need updating
11680  * @plane: drm plane
11681  * @state: new plane state
11682  *
11683  * Check current plane state versus the new one to determine whether
11684  * watermarks need to be recalculated.
11685  *
11686  * Returns true or false.
11687  */
11688 static bool intel_wm_need_update(struct drm_plane *plane,
11689                                  struct drm_plane_state *state)
11690 {
11691         struct intel_plane_state *new = to_intel_plane_state(state);
11692         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11693
11694         /* Update watermarks on tiling or size changes. */
11695         if (new->visible != cur->visible)
11696                 return true;
11697
11698         if (!cur->base.fb || !new->base.fb)
11699                 return false;
11700
11701         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11702             cur->base.rotation != new->base.rotation ||
11703             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11704             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11705             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11706             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11707                 return true;
11708
11709         return false;
11710 }
11711
11712 static bool needs_scaling(struct intel_plane_state *state)
11713 {
11714         int src_w = drm_rect_width(&state->src) >> 16;
11715         int src_h = drm_rect_height(&state->src) >> 16;
11716         int dst_w = drm_rect_width(&state->dst);
11717         int dst_h = drm_rect_height(&state->dst);
11718
11719         return (src_w != dst_w || src_h != dst_h);
11720 }
11721
11722 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11723                                     struct drm_plane_state *plane_state)
11724 {
11725         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11726         struct drm_crtc *crtc = crtc_state->crtc;
11727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11728         struct drm_plane *plane = plane_state->plane;
11729         struct drm_device *dev = crtc->dev;
11730         struct drm_i915_private *dev_priv = to_i915(dev);
11731         struct intel_plane_state *old_plane_state =
11732                 to_intel_plane_state(plane->state);
11733         int idx = intel_crtc->base.base.id, ret;
11734         bool mode_changed = needs_modeset(crtc_state);
11735         bool was_crtc_enabled = crtc->state->active;
11736         bool is_crtc_enabled = crtc_state->active;
11737         bool turn_off, turn_on, visible, was_visible;
11738         struct drm_framebuffer *fb = plane_state->fb;
11739
11740         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11741             plane->type != DRM_PLANE_TYPE_CURSOR) {
11742                 ret = skl_update_scaler_plane(
11743                         to_intel_crtc_state(crtc_state),
11744                         to_intel_plane_state(plane_state));
11745                 if (ret)
11746                         return ret;
11747         }
11748
11749         was_visible = old_plane_state->visible;
11750         visible = to_intel_plane_state(plane_state)->visible;
11751
11752         if (!was_crtc_enabled && WARN_ON(was_visible))
11753                 was_visible = false;
11754
11755         /*
11756          * Visibility is calculated as if the crtc was on, but
11757          * after scaler setup everything depends on it being off
11758          * when the crtc isn't active.
11759          */
11760         if (!is_crtc_enabled)
11761                 to_intel_plane_state(plane_state)->visible = visible = false;
11762
11763         if (!was_visible && !visible)
11764                 return 0;
11765
11766         if (fb != old_plane_state->base.fb)
11767                 pipe_config->fb_changed = true;
11768
11769         turn_off = was_visible && (!visible || mode_changed);
11770         turn_on = visible && (!was_visible || mode_changed);
11771
11772         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11773                          plane->base.id, fb ? fb->base.id : -1);
11774
11775         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11776                          plane->base.id, was_visible, visible,
11777                          turn_off, turn_on, mode_changed);
11778
11779         if (turn_on || turn_off) {
11780                 pipe_config->wm_changed = true;
11781
11782                 /* must disable cxsr around plane enable/disable */
11783                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11784                         pipe_config->disable_cxsr = true;
11785         } else if (intel_wm_need_update(plane, plane_state)) {
11786                 pipe_config->wm_changed = true;
11787         }
11788
11789         /* Pre-gen9 platforms need two-step watermark updates */
11790         if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 &&
11791             dev_priv->display.optimize_watermarks)
11792                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11793
11794         if (visible || was_visible)
11795                 intel_crtc->atomic.fb_bits |=
11796                         to_intel_plane(plane)->frontbuffer_bit;
11797
11798         switch (plane->type) {
11799         case DRM_PLANE_TYPE_PRIMARY:
11800                 intel_crtc->atomic.post_enable_primary = turn_on;
11801                 intel_crtc->atomic.update_fbc = true;
11802
11803                 break;
11804         case DRM_PLANE_TYPE_CURSOR:
11805                 break;
11806         case DRM_PLANE_TYPE_OVERLAY:
11807                 /*
11808                  * WaCxSRDisabledForSpriteScaling:ivb
11809                  *
11810                  * cstate->update_wm was already set above, so this flag will
11811                  * take effect when we commit and program watermarks.
11812                  */
11813                 if (IS_IVYBRIDGE(dev) &&
11814                     needs_scaling(to_intel_plane_state(plane_state)) &&
11815                     !needs_scaling(old_plane_state))
11816                         pipe_config->disable_lp_wm = true;
11817
11818                 break;
11819         }
11820         return 0;
11821 }
11822
11823 static bool encoders_cloneable(const struct intel_encoder *a,
11824                                const struct intel_encoder *b)
11825 {
11826         /* masks could be asymmetric, so check both ways */
11827         return a == b || (a->cloneable & (1 << b->type) &&
11828                           b->cloneable & (1 << a->type));
11829 }
11830
11831 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11832                                          struct intel_crtc *crtc,
11833                                          struct intel_encoder *encoder)
11834 {
11835         struct intel_encoder *source_encoder;
11836         struct drm_connector *connector;
11837         struct drm_connector_state *connector_state;
11838         int i;
11839
11840         for_each_connector_in_state(state, connector, connector_state, i) {
11841                 if (connector_state->crtc != &crtc->base)
11842                         continue;
11843
11844                 source_encoder =
11845                         to_intel_encoder(connector_state->best_encoder);
11846                 if (!encoders_cloneable(encoder, source_encoder))
11847                         return false;
11848         }
11849
11850         return true;
11851 }
11852
11853 static bool check_encoder_cloning(struct drm_atomic_state *state,
11854                                   struct intel_crtc *crtc)
11855 {
11856         struct intel_encoder *encoder;
11857         struct drm_connector *connector;
11858         struct drm_connector_state *connector_state;
11859         int i;
11860
11861         for_each_connector_in_state(state, connector, connector_state, i) {
11862                 if (connector_state->crtc != &crtc->base)
11863                         continue;
11864
11865                 encoder = to_intel_encoder(connector_state->best_encoder);
11866                 if (!check_single_encoder_cloning(state, crtc, encoder))
11867                         return false;
11868         }
11869
11870         return true;
11871 }
11872
11873 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11874                                    struct drm_crtc_state *crtc_state)
11875 {
11876         struct drm_device *dev = crtc->dev;
11877         struct drm_i915_private *dev_priv = dev->dev_private;
11878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11879         struct intel_crtc_state *pipe_config =
11880                 to_intel_crtc_state(crtc_state);
11881         struct drm_atomic_state *state = crtc_state->state;
11882         int ret;
11883         bool mode_changed = needs_modeset(crtc_state);
11884
11885         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11886                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11887                 return -EINVAL;
11888         }
11889
11890         if (mode_changed && !crtc_state->active)
11891                 pipe_config->wm_changed = true;
11892
11893         if (mode_changed && crtc_state->enable &&
11894             dev_priv->display.crtc_compute_clock &&
11895             !WARN_ON(pipe_config->shared_dpll)) {
11896                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11897                                                            pipe_config);
11898                 if (ret)
11899                         return ret;
11900         }
11901
11902         ret = 0;
11903         if (dev_priv->display.compute_pipe_wm) {
11904                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11905                 if (ret) {
11906                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11907                         return ret;
11908                 }
11909         }
11910
11911         if (dev_priv->display.compute_intermediate_wm &&
11912             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11913                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11914                         return 0;
11915
11916                 /*
11917                  * Calculate 'intermediate' watermarks that satisfy both the
11918                  * old state and the new state.  We can program these
11919                  * immediately.
11920                  */
11921                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11922                                                                 intel_crtc,
11923                                                                 pipe_config);
11924                 if (ret) {
11925                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11926                         return ret;
11927                 }
11928         }
11929
11930         if (INTEL_INFO(dev)->gen >= 9) {
11931                 if (mode_changed)
11932                         ret = skl_update_scaler_crtc(pipe_config);
11933
11934                 if (!ret)
11935                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11936                                                          pipe_config);
11937         }
11938
11939         return ret;
11940 }
11941
11942 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11943         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11944         .load_lut = intel_crtc_load_lut,
11945         .atomic_begin = intel_begin_crtc_commit,
11946         .atomic_flush = intel_finish_crtc_commit,
11947         .atomic_check = intel_crtc_atomic_check,
11948 };
11949
11950 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11951 {
11952         struct intel_connector *connector;
11953
11954         for_each_intel_connector(dev, connector) {
11955                 if (connector->base.encoder) {
11956                         connector->base.state->best_encoder =
11957                                 connector->base.encoder;
11958                         connector->base.state->crtc =
11959                                 connector->base.encoder->crtc;
11960                 } else {
11961                         connector->base.state->best_encoder = NULL;
11962                         connector->base.state->crtc = NULL;
11963                 }
11964         }
11965 }
11966
11967 static void
11968 connected_sink_compute_bpp(struct intel_connector *connector,
11969                            struct intel_crtc_state *pipe_config)
11970 {
11971         int bpp = pipe_config->pipe_bpp;
11972
11973         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11974                 connector->base.base.id,
11975                 connector->base.name);
11976
11977         /* Don't use an invalid EDID bpc value */
11978         if (connector->base.display_info.bpc &&
11979             connector->base.display_info.bpc * 3 < bpp) {
11980                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11981                               bpp, connector->base.display_info.bpc*3);
11982                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11983         }
11984
11985         /* Clamp bpp to default limit on screens without EDID 1.4 */
11986         if (connector->base.display_info.bpc == 0) {
11987                 int type = connector->base.connector_type;
11988                 int clamp_bpp = 24;
11989
11990                 /* Fall back to 18 bpp when DP sink capability is unknown. */
11991                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
11992                     type == DRM_MODE_CONNECTOR_eDP)
11993                         clamp_bpp = 18;
11994
11995                 if (bpp > clamp_bpp) {
11996                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11997                                       bpp, clamp_bpp);
11998                         pipe_config->pipe_bpp = clamp_bpp;
11999                 }
12000         }
12001 }
12002
12003 static int
12004 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12005                           struct intel_crtc_state *pipe_config)
12006 {
12007         struct drm_device *dev = crtc->base.dev;
12008         struct drm_atomic_state *state;
12009         struct drm_connector *connector;
12010         struct drm_connector_state *connector_state;
12011         int bpp, i;
12012
12013         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12014                 bpp = 10*3;
12015         else if (INTEL_INFO(dev)->gen >= 5)
12016                 bpp = 12*3;
12017         else
12018                 bpp = 8*3;
12019
12020
12021         pipe_config->pipe_bpp = bpp;
12022
12023         state = pipe_config->base.state;
12024
12025         /* Clamp display bpp to EDID value */
12026         for_each_connector_in_state(state, connector, connector_state, i) {
12027                 if (connector_state->crtc != &crtc->base)
12028                         continue;
12029
12030                 connected_sink_compute_bpp(to_intel_connector(connector),
12031                                            pipe_config);
12032         }
12033
12034         return bpp;
12035 }
12036
12037 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12038 {
12039         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12040                         "type: 0x%x flags: 0x%x\n",
12041                 mode->crtc_clock,
12042                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12043                 mode->crtc_hsync_end, mode->crtc_htotal,
12044                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12045                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12046 }
12047
12048 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12049                                    struct intel_crtc_state *pipe_config,
12050                                    const char *context)
12051 {
12052         struct drm_device *dev = crtc->base.dev;
12053         struct drm_plane *plane;
12054         struct intel_plane *intel_plane;
12055         struct intel_plane_state *state;
12056         struct drm_framebuffer *fb;
12057
12058         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12059                       context, pipe_config, pipe_name(crtc->pipe));
12060
12061         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12062         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12063                       pipe_config->pipe_bpp, pipe_config->dither);
12064         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12065                       pipe_config->has_pch_encoder,
12066                       pipe_config->fdi_lanes,
12067                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12068                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12069                       pipe_config->fdi_m_n.tu);
12070         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12071                       pipe_config->has_dp_encoder,
12072                       pipe_config->lane_count,
12073                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12074                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12075                       pipe_config->dp_m_n.tu);
12076
12077         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12078                       pipe_config->has_dp_encoder,
12079                       pipe_config->lane_count,
12080                       pipe_config->dp_m2_n2.gmch_m,
12081                       pipe_config->dp_m2_n2.gmch_n,
12082                       pipe_config->dp_m2_n2.link_m,
12083                       pipe_config->dp_m2_n2.link_n,
12084                       pipe_config->dp_m2_n2.tu);
12085
12086         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12087                       pipe_config->has_audio,
12088                       pipe_config->has_infoframe);
12089
12090         DRM_DEBUG_KMS("requested mode:\n");
12091         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12092         DRM_DEBUG_KMS("adjusted mode:\n");
12093         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12094         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12095         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12096         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12097                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12098         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12099                       crtc->num_scalers,
12100                       pipe_config->scaler_state.scaler_users,
12101                       pipe_config->scaler_state.scaler_id);
12102         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12103                       pipe_config->gmch_pfit.control,
12104                       pipe_config->gmch_pfit.pgm_ratios,
12105                       pipe_config->gmch_pfit.lvds_border_bits);
12106         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12107                       pipe_config->pch_pfit.pos,
12108                       pipe_config->pch_pfit.size,
12109                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12110         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12111         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12112
12113         if (IS_BROXTON(dev)) {
12114                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12115                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12116                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12117                               pipe_config->ddi_pll_sel,
12118                               pipe_config->dpll_hw_state.ebb0,
12119                               pipe_config->dpll_hw_state.ebb4,
12120                               pipe_config->dpll_hw_state.pll0,
12121                               pipe_config->dpll_hw_state.pll1,
12122                               pipe_config->dpll_hw_state.pll2,
12123                               pipe_config->dpll_hw_state.pll3,
12124                               pipe_config->dpll_hw_state.pll6,
12125                               pipe_config->dpll_hw_state.pll8,
12126                               pipe_config->dpll_hw_state.pll9,
12127                               pipe_config->dpll_hw_state.pll10,
12128                               pipe_config->dpll_hw_state.pcsdw12);
12129         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12130                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12131                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12132                               pipe_config->ddi_pll_sel,
12133                               pipe_config->dpll_hw_state.ctrl1,
12134                               pipe_config->dpll_hw_state.cfgcr1,
12135                               pipe_config->dpll_hw_state.cfgcr2);
12136         } else if (HAS_DDI(dev)) {
12137                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12138                               pipe_config->ddi_pll_sel,
12139                               pipe_config->dpll_hw_state.wrpll,
12140                               pipe_config->dpll_hw_state.spll);
12141         } else {
12142                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12143                               "fp0: 0x%x, fp1: 0x%x\n",
12144                               pipe_config->dpll_hw_state.dpll,
12145                               pipe_config->dpll_hw_state.dpll_md,
12146                               pipe_config->dpll_hw_state.fp0,
12147                               pipe_config->dpll_hw_state.fp1);
12148         }
12149
12150         DRM_DEBUG_KMS("planes on this crtc\n");
12151         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12152                 intel_plane = to_intel_plane(plane);
12153                 if (intel_plane->pipe != crtc->pipe)
12154                         continue;
12155
12156                 state = to_intel_plane_state(plane->state);
12157                 fb = state->base.fb;
12158                 if (!fb) {
12159                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12160                                 "disabled, scaler_id = %d\n",
12161                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12162                                 plane->base.id, intel_plane->pipe,
12163                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12164                                 drm_plane_index(plane), state->scaler_id);
12165                         continue;
12166                 }
12167
12168                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12169                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12170                         plane->base.id, intel_plane->pipe,
12171                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12172                         drm_plane_index(plane));
12173                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12174                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12175                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12176                         state->scaler_id,
12177                         state->src.x1 >> 16, state->src.y1 >> 16,
12178                         drm_rect_width(&state->src) >> 16,
12179                         drm_rect_height(&state->src) >> 16,
12180                         state->dst.x1, state->dst.y1,
12181                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12182         }
12183 }
12184
12185 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12186 {
12187         struct drm_device *dev = state->dev;
12188         struct drm_connector *connector;
12189         unsigned int used_ports = 0;
12190
12191         /*
12192          * Walk the connector list instead of the encoder
12193          * list to detect the problem on ddi platforms
12194          * where there's just one encoder per digital port.
12195          */
12196         drm_for_each_connector(connector, dev) {
12197                 struct drm_connector_state *connector_state;
12198                 struct intel_encoder *encoder;
12199
12200                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12201                 if (!connector_state)
12202                         connector_state = connector->state;
12203
12204                 if (!connector_state->best_encoder)
12205                         continue;
12206
12207                 encoder = to_intel_encoder(connector_state->best_encoder);
12208
12209                 WARN_ON(!connector_state->crtc);
12210
12211                 switch (encoder->type) {
12212                         unsigned int port_mask;
12213                 case INTEL_OUTPUT_UNKNOWN:
12214                         if (WARN_ON(!HAS_DDI(dev)))
12215                                 break;
12216                 case INTEL_OUTPUT_DISPLAYPORT:
12217                 case INTEL_OUTPUT_HDMI:
12218                 case INTEL_OUTPUT_EDP:
12219                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12220
12221                         /* the same port mustn't appear more than once */
12222                         if (used_ports & port_mask)
12223                                 return false;
12224
12225                         used_ports |= port_mask;
12226                 default:
12227                         break;
12228                 }
12229         }
12230
12231         return true;
12232 }
12233
12234 static void
12235 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12236 {
12237         struct drm_crtc_state tmp_state;
12238         struct intel_crtc_scaler_state scaler_state;
12239         struct intel_dpll_hw_state dpll_hw_state;
12240         struct intel_shared_dpll *shared_dpll;
12241         uint32_t ddi_pll_sel;
12242         bool force_thru;
12243
12244         /* FIXME: before the switch to atomic started, a new pipe_config was
12245          * kzalloc'd. Code that depends on any field being zero should be
12246          * fixed, so that the crtc_state can be safely duplicated. For now,
12247          * only fields that are know to not cause problems are preserved. */
12248
12249         tmp_state = crtc_state->base;
12250         scaler_state = crtc_state->scaler_state;
12251         shared_dpll = crtc_state->shared_dpll;
12252         dpll_hw_state = crtc_state->dpll_hw_state;
12253         ddi_pll_sel = crtc_state->ddi_pll_sel;
12254         force_thru = crtc_state->pch_pfit.force_thru;
12255
12256         memset(crtc_state, 0, sizeof *crtc_state);
12257
12258         crtc_state->base = tmp_state;
12259         crtc_state->scaler_state = scaler_state;
12260         crtc_state->shared_dpll = shared_dpll;
12261         crtc_state->dpll_hw_state = dpll_hw_state;
12262         crtc_state->ddi_pll_sel = ddi_pll_sel;
12263         crtc_state->pch_pfit.force_thru = force_thru;
12264 }
12265
12266 static int
12267 intel_modeset_pipe_config(struct drm_crtc *crtc,
12268                           struct intel_crtc_state *pipe_config)
12269 {
12270         struct drm_atomic_state *state = pipe_config->base.state;
12271         struct intel_encoder *encoder;
12272         struct drm_connector *connector;
12273         struct drm_connector_state *connector_state;
12274         int base_bpp, ret = -EINVAL;
12275         int i;
12276         bool retry = true;
12277
12278         clear_intel_crtc_state(pipe_config);
12279
12280         pipe_config->cpu_transcoder =
12281                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12282
12283         /*
12284          * Sanitize sync polarity flags based on requested ones. If neither
12285          * positive or negative polarity is requested, treat this as meaning
12286          * negative polarity.
12287          */
12288         if (!(pipe_config->base.adjusted_mode.flags &
12289               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12290                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12291
12292         if (!(pipe_config->base.adjusted_mode.flags &
12293               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12294                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12295
12296         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12297                                              pipe_config);
12298         if (base_bpp < 0)
12299                 goto fail;
12300
12301         /*
12302          * Determine the real pipe dimensions. Note that stereo modes can
12303          * increase the actual pipe size due to the frame doubling and
12304          * insertion of additional space for blanks between the frame. This
12305          * is stored in the crtc timings. We use the requested mode to do this
12306          * computation to clearly distinguish it from the adjusted mode, which
12307          * can be changed by the connectors in the below retry loop.
12308          */
12309         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12310                                &pipe_config->pipe_src_w,
12311                                &pipe_config->pipe_src_h);
12312
12313 encoder_retry:
12314         /* Ensure the port clock defaults are reset when retrying. */
12315         pipe_config->port_clock = 0;
12316         pipe_config->pixel_multiplier = 1;
12317
12318         /* Fill in default crtc timings, allow encoders to overwrite them. */
12319         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12320                               CRTC_STEREO_DOUBLE);
12321
12322         /* Pass our mode to the connectors and the CRTC to give them a chance to
12323          * adjust it according to limitations or connector properties, and also
12324          * a chance to reject the mode entirely.
12325          */
12326         for_each_connector_in_state(state, connector, connector_state, i) {
12327                 if (connector_state->crtc != crtc)
12328                         continue;
12329
12330                 encoder = to_intel_encoder(connector_state->best_encoder);
12331
12332                 if (!(encoder->compute_config(encoder, pipe_config))) {
12333                         DRM_DEBUG_KMS("Encoder config failure\n");
12334                         goto fail;
12335                 }
12336         }
12337
12338         /* Set default port clock if not overwritten by the encoder. Needs to be
12339          * done afterwards in case the encoder adjusts the mode. */
12340         if (!pipe_config->port_clock)
12341                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12342                         * pipe_config->pixel_multiplier;
12343
12344         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12345         if (ret < 0) {
12346                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12347                 goto fail;
12348         }
12349
12350         if (ret == RETRY) {
12351                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12352                         ret = -EINVAL;
12353                         goto fail;
12354                 }
12355
12356                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12357                 retry = false;
12358                 goto encoder_retry;
12359         }
12360
12361         /* Dithering seems to not pass-through bits correctly when it should, so
12362          * only enable it on 6bpc panels. */
12363         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12364         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12365                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12366
12367 fail:
12368         return ret;
12369 }
12370
12371 static void
12372 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12373 {
12374         struct drm_crtc *crtc;
12375         struct drm_crtc_state *crtc_state;
12376         int i;
12377
12378         /* Double check state. */
12379         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12380                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12381
12382                 /* Update hwmode for vblank functions */
12383                 if (crtc->state->active)
12384                         crtc->hwmode = crtc->state->adjusted_mode;
12385                 else
12386                         crtc->hwmode.crtc_clock = 0;
12387
12388                 /*
12389                  * Update legacy state to satisfy fbc code. This can
12390                  * be removed when fbc uses the atomic state.
12391                  */
12392                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12393                         struct drm_plane_state *plane_state = crtc->primary->state;
12394
12395                         crtc->primary->fb = plane_state->fb;
12396                         crtc->x = plane_state->src_x >> 16;
12397                         crtc->y = plane_state->src_y >> 16;
12398                 }
12399         }
12400 }
12401
12402 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12403 {
12404         int diff;
12405
12406         if (clock1 == clock2)
12407                 return true;
12408
12409         if (!clock1 || !clock2)
12410                 return false;
12411
12412         diff = abs(clock1 - clock2);
12413
12414         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12415                 return true;
12416
12417         return false;
12418 }
12419
12420 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12421         list_for_each_entry((intel_crtc), \
12422                             &(dev)->mode_config.crtc_list, \
12423                             base.head) \
12424                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12425
12426 static bool
12427 intel_compare_m_n(unsigned int m, unsigned int n,
12428                   unsigned int m2, unsigned int n2,
12429                   bool exact)
12430 {
12431         if (m == m2 && n == n2)
12432                 return true;
12433
12434         if (exact || !m || !n || !m2 || !n2)
12435                 return false;
12436
12437         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12438
12439         if (n > n2) {
12440                 while (n > n2) {
12441                         m2 <<= 1;
12442                         n2 <<= 1;
12443                 }
12444         } else if (n < n2) {
12445                 while (n < n2) {
12446                         m <<= 1;
12447                         n <<= 1;
12448                 }
12449         }
12450
12451         if (n != n2)
12452                 return false;
12453
12454         return intel_fuzzy_clock_check(m, m2);
12455 }
12456
12457 static bool
12458 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12459                        struct intel_link_m_n *m2_n2,
12460                        bool adjust)
12461 {
12462         if (m_n->tu == m2_n2->tu &&
12463             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12464                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12465             intel_compare_m_n(m_n->link_m, m_n->link_n,
12466                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12467                 if (adjust)
12468                         *m2_n2 = *m_n;
12469
12470                 return true;
12471         }
12472
12473         return false;
12474 }
12475
12476 static bool
12477 intel_pipe_config_compare(struct drm_device *dev,
12478                           struct intel_crtc_state *current_config,
12479                           struct intel_crtc_state *pipe_config,
12480                           bool adjust)
12481 {
12482         bool ret = true;
12483
12484 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12485         do { \
12486                 if (!adjust) \
12487                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12488                 else \
12489                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12490         } while (0)
12491
12492 #define PIPE_CONF_CHECK_X(name) \
12493         if (current_config->name != pipe_config->name) { \
12494                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12495                           "(expected 0x%08x, found 0x%08x)\n", \
12496                           current_config->name, \
12497                           pipe_config->name); \
12498                 ret = false; \
12499         }
12500
12501 #define PIPE_CONF_CHECK_I(name) \
12502         if (current_config->name != pipe_config->name) { \
12503                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12504                           "(expected %i, found %i)\n", \
12505                           current_config->name, \
12506                           pipe_config->name); \
12507                 ret = false; \
12508         }
12509
12510 #define PIPE_CONF_CHECK_P(name) \
12511         if (current_config->name != pipe_config->name) { \
12512                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12513                           "(expected %p, found %p)\n", \
12514                           current_config->name, \
12515                           pipe_config->name); \
12516                 ret = false; \
12517         }
12518
12519 #define PIPE_CONF_CHECK_M_N(name) \
12520         if (!intel_compare_link_m_n(&current_config->name, \
12521                                     &pipe_config->name,\
12522                                     adjust)) { \
12523                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12524                           "(expected tu %i gmch %i/%i link %i/%i, " \
12525                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12526                           current_config->name.tu, \
12527                           current_config->name.gmch_m, \
12528                           current_config->name.gmch_n, \
12529                           current_config->name.link_m, \
12530                           current_config->name.link_n, \
12531                           pipe_config->name.tu, \
12532                           pipe_config->name.gmch_m, \
12533                           pipe_config->name.gmch_n, \
12534                           pipe_config->name.link_m, \
12535                           pipe_config->name.link_n); \
12536                 ret = false; \
12537         }
12538
12539 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12540         if (!intel_compare_link_m_n(&current_config->name, \
12541                                     &pipe_config->name, adjust) && \
12542             !intel_compare_link_m_n(&current_config->alt_name, \
12543                                     &pipe_config->name, adjust)) { \
12544                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12545                           "(expected tu %i gmch %i/%i link %i/%i, " \
12546                           "or tu %i gmch %i/%i link %i/%i, " \
12547                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12548                           current_config->name.tu, \
12549                           current_config->name.gmch_m, \
12550                           current_config->name.gmch_n, \
12551                           current_config->name.link_m, \
12552                           current_config->name.link_n, \
12553                           current_config->alt_name.tu, \
12554                           current_config->alt_name.gmch_m, \
12555                           current_config->alt_name.gmch_n, \
12556                           current_config->alt_name.link_m, \
12557                           current_config->alt_name.link_n, \
12558                           pipe_config->name.tu, \
12559                           pipe_config->name.gmch_m, \
12560                           pipe_config->name.gmch_n, \
12561                           pipe_config->name.link_m, \
12562                           pipe_config->name.link_n); \
12563                 ret = false; \
12564         }
12565
12566 /* This is required for BDW+ where there is only one set of registers for
12567  * switching between high and low RR.
12568  * This macro can be used whenever a comparison has to be made between one
12569  * hw state and multiple sw state variables.
12570  */
12571 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12572         if ((current_config->name != pipe_config->name) && \
12573                 (current_config->alt_name != pipe_config->name)) { \
12574                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12575                                   "(expected %i or %i, found %i)\n", \
12576                                   current_config->name, \
12577                                   current_config->alt_name, \
12578                                   pipe_config->name); \
12579                         ret = false; \
12580         }
12581
12582 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12583         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12584                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12585                           "(expected %i, found %i)\n", \
12586                           current_config->name & (mask), \
12587                           pipe_config->name & (mask)); \
12588                 ret = false; \
12589         }
12590
12591 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12592         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12593                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12594                           "(expected %i, found %i)\n", \
12595                           current_config->name, \
12596                           pipe_config->name); \
12597                 ret = false; \
12598         }
12599
12600 #define PIPE_CONF_QUIRK(quirk)  \
12601         ((current_config->quirks | pipe_config->quirks) & (quirk))
12602
12603         PIPE_CONF_CHECK_I(cpu_transcoder);
12604
12605         PIPE_CONF_CHECK_I(has_pch_encoder);
12606         PIPE_CONF_CHECK_I(fdi_lanes);
12607         PIPE_CONF_CHECK_M_N(fdi_m_n);
12608
12609         PIPE_CONF_CHECK_I(has_dp_encoder);
12610         PIPE_CONF_CHECK_I(lane_count);
12611
12612         if (INTEL_INFO(dev)->gen < 8) {
12613                 PIPE_CONF_CHECK_M_N(dp_m_n);
12614
12615                 if (current_config->has_drrs)
12616                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12617         } else
12618                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12619
12620         PIPE_CONF_CHECK_I(has_dsi_encoder);
12621
12622         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12623         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12624         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12625         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12626         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12627         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12628
12629         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12630         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12631         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12632         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12633         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12634         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12635
12636         PIPE_CONF_CHECK_I(pixel_multiplier);
12637         PIPE_CONF_CHECK_I(has_hdmi_sink);
12638         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12639             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12640                 PIPE_CONF_CHECK_I(limited_color_range);
12641         PIPE_CONF_CHECK_I(has_infoframe);
12642
12643         PIPE_CONF_CHECK_I(has_audio);
12644
12645         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12646                               DRM_MODE_FLAG_INTERLACE);
12647
12648         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12649                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12650                                       DRM_MODE_FLAG_PHSYNC);
12651                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12652                                       DRM_MODE_FLAG_NHSYNC);
12653                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12654                                       DRM_MODE_FLAG_PVSYNC);
12655                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12656                                       DRM_MODE_FLAG_NVSYNC);
12657         }
12658
12659         PIPE_CONF_CHECK_X(gmch_pfit.control);
12660         /* pfit ratios are autocomputed by the hw on gen4+ */
12661         if (INTEL_INFO(dev)->gen < 4)
12662                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12663         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12664
12665         if (!adjust) {
12666                 PIPE_CONF_CHECK_I(pipe_src_w);
12667                 PIPE_CONF_CHECK_I(pipe_src_h);
12668
12669                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12670                 if (current_config->pch_pfit.enabled) {
12671                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12672                         PIPE_CONF_CHECK_X(pch_pfit.size);
12673                 }
12674
12675                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12676         }
12677
12678         /* BDW+ don't expose a synchronous way to read the state */
12679         if (IS_HASWELL(dev))
12680                 PIPE_CONF_CHECK_I(ips_enabled);
12681
12682         PIPE_CONF_CHECK_I(double_wide);
12683
12684         PIPE_CONF_CHECK_X(ddi_pll_sel);
12685
12686         PIPE_CONF_CHECK_P(shared_dpll);
12687         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12688         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12689         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12690         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12691         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12692         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12693         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12694         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12695         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12696
12697         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12698                 PIPE_CONF_CHECK_I(pipe_bpp);
12699
12700         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12701         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12702
12703 #undef PIPE_CONF_CHECK_X
12704 #undef PIPE_CONF_CHECK_I
12705 #undef PIPE_CONF_CHECK_P
12706 #undef PIPE_CONF_CHECK_I_ALT
12707 #undef PIPE_CONF_CHECK_FLAGS
12708 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12709 #undef PIPE_CONF_QUIRK
12710 #undef INTEL_ERR_OR_DBG_KMS
12711
12712         return ret;
12713 }
12714
12715 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12716                                            const struct intel_crtc_state *pipe_config)
12717 {
12718         if (pipe_config->has_pch_encoder) {
12719                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12720                                                             &pipe_config->fdi_m_n);
12721                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12722
12723                 /*
12724                  * FDI already provided one idea for the dotclock.
12725                  * Yell if the encoder disagrees.
12726                  */
12727                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12728                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12729                      fdi_dotclock, dotclock);
12730         }
12731 }
12732
12733 static void check_wm_state(struct drm_device *dev)
12734 {
12735         struct drm_i915_private *dev_priv = dev->dev_private;
12736         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12737         struct intel_crtc *intel_crtc;
12738         int plane;
12739
12740         if (INTEL_INFO(dev)->gen < 9)
12741                 return;
12742
12743         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12744         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12745
12746         for_each_intel_crtc(dev, intel_crtc) {
12747                 struct skl_ddb_entry *hw_entry, *sw_entry;
12748                 const enum pipe pipe = intel_crtc->pipe;
12749
12750                 if (!intel_crtc->active)
12751                         continue;
12752
12753                 /* planes */
12754                 for_each_plane(dev_priv, pipe, plane) {
12755                         hw_entry = &hw_ddb.plane[pipe][plane];
12756                         sw_entry = &sw_ddb->plane[pipe][plane];
12757
12758                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12759                                 continue;
12760
12761                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12762                                   "(expected (%u,%u), found (%u,%u))\n",
12763                                   pipe_name(pipe), plane + 1,
12764                                   sw_entry->start, sw_entry->end,
12765                                   hw_entry->start, hw_entry->end);
12766                 }
12767
12768                 /* cursor */
12769                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12770                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12771
12772                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12773                         continue;
12774
12775                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12776                           "(expected (%u,%u), found (%u,%u))\n",
12777                           pipe_name(pipe),
12778                           sw_entry->start, sw_entry->end,
12779                           hw_entry->start, hw_entry->end);
12780         }
12781 }
12782
12783 static void
12784 check_connector_state(struct drm_device *dev,
12785                       struct drm_atomic_state *old_state)
12786 {
12787         struct drm_connector_state *old_conn_state;
12788         struct drm_connector *connector;
12789         int i;
12790
12791         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12792                 struct drm_encoder *encoder = connector->encoder;
12793                 struct drm_connector_state *state = connector->state;
12794
12795                 /* This also checks the encoder/connector hw state with the
12796                  * ->get_hw_state callbacks. */
12797                 intel_connector_check_state(to_intel_connector(connector));
12798
12799                 I915_STATE_WARN(state->best_encoder != encoder,
12800                      "connector's atomic encoder doesn't match legacy encoder\n");
12801         }
12802 }
12803
12804 static void
12805 check_encoder_state(struct drm_device *dev)
12806 {
12807         struct intel_encoder *encoder;
12808         struct intel_connector *connector;
12809
12810         for_each_intel_encoder(dev, encoder) {
12811                 bool enabled = false;
12812                 enum pipe pipe;
12813
12814                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12815                               encoder->base.base.id,
12816                               encoder->base.name);
12817
12818                 for_each_intel_connector(dev, connector) {
12819                         if (connector->base.state->best_encoder != &encoder->base)
12820                                 continue;
12821                         enabled = true;
12822
12823                         I915_STATE_WARN(connector->base.state->crtc !=
12824                                         encoder->base.crtc,
12825                              "connector's crtc doesn't match encoder crtc\n");
12826                 }
12827
12828                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12829                      "encoder's enabled state mismatch "
12830                      "(expected %i, found %i)\n",
12831                      !!encoder->base.crtc, enabled);
12832
12833                 if (!encoder->base.crtc) {
12834                         bool active;
12835
12836                         active = encoder->get_hw_state(encoder, &pipe);
12837                         I915_STATE_WARN(active,
12838                              "encoder detached but still enabled on pipe %c.\n",
12839                              pipe_name(pipe));
12840                 }
12841         }
12842 }
12843
12844 static void
12845 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12846 {
12847         struct drm_i915_private *dev_priv = dev->dev_private;
12848         struct intel_encoder *encoder;
12849         struct drm_crtc_state *old_crtc_state;
12850         struct drm_crtc *crtc;
12851         int i;
12852
12853         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12854                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12855                 struct intel_crtc_state *pipe_config, *sw_config;
12856                 bool active;
12857
12858                 if (!needs_modeset(crtc->state) &&
12859                     !to_intel_crtc_state(crtc->state)->update_pipe)
12860                         continue;
12861
12862                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12863                 pipe_config = to_intel_crtc_state(old_crtc_state);
12864                 memset(pipe_config, 0, sizeof(*pipe_config));
12865                 pipe_config->base.crtc = crtc;
12866                 pipe_config->base.state = old_state;
12867
12868                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12869                               crtc->base.id);
12870
12871                 active = dev_priv->display.get_pipe_config(intel_crtc,
12872                                                            pipe_config);
12873
12874                 /* hw state is inconsistent with the pipe quirk */
12875                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12876                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12877                         active = crtc->state->active;
12878
12879                 I915_STATE_WARN(crtc->state->active != active,
12880                      "crtc active state doesn't match with hw state "
12881                      "(expected %i, found %i)\n", crtc->state->active, active);
12882
12883                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12884                      "transitional active state does not match atomic hw state "
12885                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12886
12887                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12888                         enum pipe pipe;
12889
12890                         active = encoder->get_hw_state(encoder, &pipe);
12891                         I915_STATE_WARN(active != crtc->state->active,
12892                                 "[ENCODER:%i] active %i with crtc active %i\n",
12893                                 encoder->base.base.id, active, crtc->state->active);
12894
12895                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12896                                         "Encoder connected to wrong pipe %c\n",
12897                                         pipe_name(pipe));
12898
12899                         if (active)
12900                                 encoder->get_config(encoder, pipe_config);
12901                 }
12902
12903                 if (!crtc->state->active)
12904                         continue;
12905
12906                 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12907
12908                 sw_config = to_intel_crtc_state(crtc->state);
12909                 if (!intel_pipe_config_compare(dev, sw_config,
12910                                                pipe_config, false)) {
12911                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12912                         intel_dump_pipe_config(intel_crtc, pipe_config,
12913                                                "[hw state]");
12914                         intel_dump_pipe_config(intel_crtc, sw_config,
12915                                                "[sw state]");
12916                 }
12917         }
12918 }
12919
12920 static void
12921 check_shared_dpll_state(struct drm_device *dev)
12922 {
12923         struct drm_i915_private *dev_priv = dev->dev_private;
12924         struct intel_crtc *crtc;
12925         struct intel_dpll_hw_state dpll_hw_state;
12926         int i;
12927
12928         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12929                 struct intel_shared_dpll *pll =
12930                         intel_get_shared_dpll_by_id(dev_priv, i);
12931                 int enabled_crtcs = 0, active_crtcs = 0;
12932                 bool active;
12933
12934                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12935
12936                 DRM_DEBUG_KMS("%s\n", pll->name);
12937
12938                 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12939
12940                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12941                      "more active pll users than references: %i vs %i\n",
12942                      pll->active, hweight32(pll->config.crtc_mask));
12943                 I915_STATE_WARN(pll->active && !pll->on,
12944                      "pll in active use but not on in sw tracking\n");
12945                 I915_STATE_WARN(pll->on && !pll->active,
12946                      "pll in on but not on in use in sw tracking\n");
12947                 I915_STATE_WARN(pll->on != active,
12948                      "pll on state mismatch (expected %i, found %i)\n",
12949                      pll->on, active);
12950
12951                 for_each_intel_crtc(dev, crtc) {
12952                         if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12953                                 enabled_crtcs++;
12954                         if (crtc->active && crtc->config->shared_dpll == pll)
12955                                 active_crtcs++;
12956                 }
12957                 I915_STATE_WARN(pll->active != active_crtcs,
12958                      "pll active crtcs mismatch (expected %i, found %i)\n",
12959                      pll->active, active_crtcs);
12960                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12961                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12962                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12963
12964                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12965                                        sizeof(dpll_hw_state)),
12966                      "pll hw state mismatch\n");
12967         }
12968 }
12969
12970 static void
12971 intel_modeset_check_state(struct drm_device *dev,
12972                           struct drm_atomic_state *old_state)
12973 {
12974         check_wm_state(dev);
12975         check_connector_state(dev, old_state);
12976         check_encoder_state(dev);
12977         check_crtc_state(dev, old_state);
12978         check_shared_dpll_state(dev);
12979 }
12980
12981 static void update_scanline_offset(struct intel_crtc *crtc)
12982 {
12983         struct drm_device *dev = crtc->base.dev;
12984
12985         /*
12986          * The scanline counter increments at the leading edge of hsync.
12987          *
12988          * On most platforms it starts counting from vtotal-1 on the
12989          * first active line. That means the scanline counter value is
12990          * always one less than what we would expect. Ie. just after
12991          * start of vblank, which also occurs at start of hsync (on the
12992          * last active line), the scanline counter will read vblank_start-1.
12993          *
12994          * On gen2 the scanline counter starts counting from 1 instead
12995          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12996          * to keep the value positive), instead of adding one.
12997          *
12998          * On HSW+ the behaviour of the scanline counter depends on the output
12999          * type. For DP ports it behaves like most other platforms, but on HDMI
13000          * there's an extra 1 line difference. So we need to add two instead of
13001          * one to the value.
13002          */
13003         if (IS_GEN2(dev)) {
13004                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13005                 int vtotal;
13006
13007                 vtotal = adjusted_mode->crtc_vtotal;
13008                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13009                         vtotal /= 2;
13010
13011                 crtc->scanline_offset = vtotal - 1;
13012         } else if (HAS_DDI(dev) &&
13013                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13014                 crtc->scanline_offset = 2;
13015         } else
13016                 crtc->scanline_offset = 1;
13017 }
13018
13019 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13020 {
13021         struct drm_device *dev = state->dev;
13022         struct drm_i915_private *dev_priv = to_i915(dev);
13023         struct intel_shared_dpll_config *shared_dpll = NULL;
13024         struct drm_crtc *crtc;
13025         struct drm_crtc_state *crtc_state;
13026         int i;
13027
13028         if (!dev_priv->display.crtc_compute_clock)
13029                 return;
13030
13031         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13032                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13033                 struct intel_shared_dpll *old_dpll =
13034                         to_intel_crtc_state(crtc->state)->shared_dpll;
13035
13036                 if (!needs_modeset(crtc_state))
13037                         continue;
13038
13039                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13040
13041                 if (!old_dpll)
13042                         continue;
13043
13044                 if (!shared_dpll)
13045                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13046
13047                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13048         }
13049 }
13050
13051 /*
13052  * This implements the workaround described in the "notes" section of the mode
13053  * set sequence documentation. When going from no pipes or single pipe to
13054  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13055  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13056  */
13057 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13058 {
13059         struct drm_crtc_state *crtc_state;
13060         struct intel_crtc *intel_crtc;
13061         struct drm_crtc *crtc;
13062         struct intel_crtc_state *first_crtc_state = NULL;
13063         struct intel_crtc_state *other_crtc_state = NULL;
13064         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13065         int i;
13066
13067         /* look at all crtc's that are going to be enabled in during modeset */
13068         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13069                 intel_crtc = to_intel_crtc(crtc);
13070
13071                 if (!crtc_state->active || !needs_modeset(crtc_state))
13072                         continue;
13073
13074                 if (first_crtc_state) {
13075                         other_crtc_state = to_intel_crtc_state(crtc_state);
13076                         break;
13077                 } else {
13078                         first_crtc_state = to_intel_crtc_state(crtc_state);
13079                         first_pipe = intel_crtc->pipe;
13080                 }
13081         }
13082
13083         /* No workaround needed? */
13084         if (!first_crtc_state)
13085                 return 0;
13086
13087         /* w/a possibly needed, check how many crtc's are already enabled. */
13088         for_each_intel_crtc(state->dev, intel_crtc) {
13089                 struct intel_crtc_state *pipe_config;
13090
13091                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13092                 if (IS_ERR(pipe_config))
13093                         return PTR_ERR(pipe_config);
13094
13095                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13096
13097                 if (!pipe_config->base.active ||
13098                     needs_modeset(&pipe_config->base))
13099                         continue;
13100
13101                 /* 2 or more enabled crtcs means no need for w/a */
13102                 if (enabled_pipe != INVALID_PIPE)
13103                         return 0;
13104
13105                 enabled_pipe = intel_crtc->pipe;
13106         }
13107
13108         if (enabled_pipe != INVALID_PIPE)
13109                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13110         else if (other_crtc_state)
13111                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13112
13113         return 0;
13114 }
13115
13116 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13117 {
13118         struct drm_crtc *crtc;
13119         struct drm_crtc_state *crtc_state;
13120         int ret = 0;
13121
13122         /* add all active pipes to the state */
13123         for_each_crtc(state->dev, crtc) {
13124                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13125                 if (IS_ERR(crtc_state))
13126                         return PTR_ERR(crtc_state);
13127
13128                 if (!crtc_state->active || needs_modeset(crtc_state))
13129                         continue;
13130
13131                 crtc_state->mode_changed = true;
13132
13133                 ret = drm_atomic_add_affected_connectors(state, crtc);
13134                 if (ret)
13135                         break;
13136
13137                 ret = drm_atomic_add_affected_planes(state, crtc);
13138                 if (ret)
13139                         break;
13140         }
13141
13142         return ret;
13143 }
13144
13145 static int intel_modeset_checks(struct drm_atomic_state *state)
13146 {
13147         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13148         struct drm_i915_private *dev_priv = state->dev->dev_private;
13149         struct drm_crtc *crtc;
13150         struct drm_crtc_state *crtc_state;
13151         int ret = 0, i;
13152
13153         if (!check_digital_port_conflicts(state)) {
13154                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13155                 return -EINVAL;
13156         }
13157
13158         intel_state->modeset = true;
13159         intel_state->active_crtcs = dev_priv->active_crtcs;
13160
13161         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13162                 if (crtc_state->active)
13163                         intel_state->active_crtcs |= 1 << i;
13164                 else
13165                         intel_state->active_crtcs &= ~(1 << i);
13166         }
13167
13168         /*
13169          * See if the config requires any additional preparation, e.g.
13170          * to adjust global state with pipes off.  We need to do this
13171          * here so we can get the modeset_pipe updated config for the new
13172          * mode set on this crtc.  For other crtcs we need to use the
13173          * adjusted_mode bits in the crtc directly.
13174          */
13175         if (dev_priv->display.modeset_calc_cdclk) {
13176                 ret = dev_priv->display.modeset_calc_cdclk(state);
13177
13178                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13179                         ret = intel_modeset_all_pipes(state);
13180
13181                 if (ret < 0)
13182                         return ret;
13183
13184                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13185                               intel_state->cdclk, intel_state->dev_cdclk);
13186         } else
13187                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13188
13189         intel_modeset_clear_plls(state);
13190
13191         if (IS_HASWELL(dev_priv))
13192                 return haswell_mode_set_planes_workaround(state);
13193
13194         return 0;
13195 }
13196
13197 /*
13198  * Handle calculation of various watermark data at the end of the atomic check
13199  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13200  * handlers to ensure that all derived state has been updated.
13201  */
13202 static void calc_watermark_data(struct drm_atomic_state *state)
13203 {
13204         struct drm_device *dev = state->dev;
13205         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13206         struct drm_crtc *crtc;
13207         struct drm_crtc_state *cstate;
13208         struct drm_plane *plane;
13209         struct drm_plane_state *pstate;
13210
13211         /*
13212          * Calculate watermark configuration details now that derived
13213          * plane/crtc state is all properly updated.
13214          */
13215         drm_for_each_crtc(crtc, dev) {
13216                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13217                         crtc->state;
13218
13219                 if (cstate->active)
13220                         intel_state->wm_config.num_pipes_active++;
13221         }
13222         drm_for_each_legacy_plane(plane, dev) {
13223                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13224                         plane->state;
13225
13226                 if (!to_intel_plane_state(pstate)->visible)
13227                         continue;
13228
13229                 intel_state->wm_config.sprites_enabled = true;
13230                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13231                     pstate->crtc_h != pstate->src_h >> 16)
13232                         intel_state->wm_config.sprites_scaled = true;
13233         }
13234 }
13235
13236 /**
13237  * intel_atomic_check - validate state object
13238  * @dev: drm device
13239  * @state: state to validate
13240  */
13241 static int intel_atomic_check(struct drm_device *dev,
13242                               struct drm_atomic_state *state)
13243 {
13244         struct drm_i915_private *dev_priv = to_i915(dev);
13245         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13246         struct drm_crtc *crtc;
13247         struct drm_crtc_state *crtc_state;
13248         int ret, i;
13249         bool any_ms = false;
13250
13251         ret = drm_atomic_helper_check_modeset(dev, state);
13252         if (ret)
13253                 return ret;
13254
13255         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13256                 struct intel_crtc_state *pipe_config =
13257                         to_intel_crtc_state(crtc_state);
13258
13259                 memset(&to_intel_crtc(crtc)->atomic, 0,
13260                        sizeof(struct intel_crtc_atomic_commit));
13261
13262                 /* Catch I915_MODE_FLAG_INHERITED */
13263                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13264                         crtc_state->mode_changed = true;
13265
13266                 if (!crtc_state->enable) {
13267                         if (needs_modeset(crtc_state))
13268                                 any_ms = true;
13269                         continue;
13270                 }
13271
13272                 if (!needs_modeset(crtc_state))
13273                         continue;
13274
13275                 /* FIXME: For only active_changed we shouldn't need to do any
13276                  * state recomputation at all. */
13277
13278                 ret = drm_atomic_add_affected_connectors(state, crtc);
13279                 if (ret)
13280                         return ret;
13281
13282                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13283                 if (ret)
13284                         return ret;
13285
13286                 if (i915.fastboot &&
13287                     intel_pipe_config_compare(dev,
13288                                         to_intel_crtc_state(crtc->state),
13289                                         pipe_config, true)) {
13290                         crtc_state->mode_changed = false;
13291                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13292                 }
13293
13294                 if (needs_modeset(crtc_state)) {
13295                         any_ms = true;
13296
13297                         ret = drm_atomic_add_affected_planes(state, crtc);
13298                         if (ret)
13299                                 return ret;
13300                 }
13301
13302                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13303                                        needs_modeset(crtc_state) ?
13304                                        "[modeset]" : "[fastset]");
13305         }
13306
13307         if (any_ms) {
13308                 ret = intel_modeset_checks(state);
13309
13310                 if (ret)
13311                         return ret;
13312         } else
13313                 intel_state->cdclk = dev_priv->cdclk_freq;
13314
13315         ret = drm_atomic_helper_check_planes(dev, state);
13316         if (ret)
13317                 return ret;
13318
13319         intel_fbc_choose_crtc(dev_priv, state);
13320         calc_watermark_data(state);
13321
13322         return 0;
13323 }
13324
13325 static int intel_atomic_prepare_commit(struct drm_device *dev,
13326                                        struct drm_atomic_state *state,
13327                                        bool async)
13328 {
13329         struct drm_i915_private *dev_priv = dev->dev_private;
13330         struct drm_plane_state *plane_state;
13331         struct drm_crtc_state *crtc_state;
13332         struct drm_plane *plane;
13333         struct drm_crtc *crtc;
13334         int i, ret;
13335
13336         if (async) {
13337                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13338                 return -EINVAL;
13339         }
13340
13341         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13342                 ret = intel_crtc_wait_for_pending_flips(crtc);
13343                 if (ret)
13344                         return ret;
13345
13346                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13347                         flush_workqueue(dev_priv->wq);
13348         }
13349
13350         ret = mutex_lock_interruptible(&dev->struct_mutex);
13351         if (ret)
13352                 return ret;
13353
13354         ret = drm_atomic_helper_prepare_planes(dev, state);
13355         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13356                 u32 reset_counter;
13357
13358                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13359                 mutex_unlock(&dev->struct_mutex);
13360
13361                 for_each_plane_in_state(state, plane, plane_state, i) {
13362                         struct intel_plane_state *intel_plane_state =
13363                                 to_intel_plane_state(plane_state);
13364
13365                         if (!intel_plane_state->wait_req)
13366                                 continue;
13367
13368                         ret = __i915_wait_request(intel_plane_state->wait_req,
13369                                                   reset_counter, true,
13370                                                   NULL, NULL);
13371
13372                         /* Swallow -EIO errors to allow updates during hw lockup. */
13373                         if (ret == -EIO)
13374                                 ret = 0;
13375
13376                         if (ret)
13377                                 break;
13378                 }
13379
13380                 if (!ret)
13381                         return 0;
13382
13383                 mutex_lock(&dev->struct_mutex);
13384                 drm_atomic_helper_cleanup_planes(dev, state);
13385         }
13386
13387         mutex_unlock(&dev->struct_mutex);
13388         return ret;
13389 }
13390
13391 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13392                                           struct drm_i915_private *dev_priv,
13393                                           unsigned crtc_mask)
13394 {
13395         unsigned last_vblank_count[I915_MAX_PIPES];
13396         enum pipe pipe;
13397         int ret;
13398
13399         if (!crtc_mask)
13400                 return;
13401
13402         for_each_pipe(dev_priv, pipe) {
13403                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13404
13405                 if (!((1 << pipe) & crtc_mask))
13406                         continue;
13407
13408                 ret = drm_crtc_vblank_get(crtc);
13409                 if (WARN_ON(ret != 0)) {
13410                         crtc_mask &= ~(1 << pipe);
13411                         continue;
13412                 }
13413
13414                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13415         }
13416
13417         for_each_pipe(dev_priv, pipe) {
13418                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13419                 long lret;
13420
13421                 if (!((1 << pipe) & crtc_mask))
13422                         continue;
13423
13424                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13425                                 last_vblank_count[pipe] !=
13426                                         drm_crtc_vblank_count(crtc),
13427                                 msecs_to_jiffies(50));
13428
13429                 WARN_ON(!lret);
13430
13431                 drm_crtc_vblank_put(crtc);
13432         }
13433 }
13434
13435 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13436 {
13437         /* fb updated, need to unpin old fb */
13438         if (crtc_state->fb_changed)
13439                 return true;
13440
13441         /* wm changes, need vblank before final wm's */
13442         if (crtc_state->wm_changed)
13443                 return true;
13444
13445         /*
13446          * cxsr is re-enabled after vblank.
13447          * This is already handled by crtc_state->wm_changed,
13448          * but added for clarity.
13449          */
13450         if (crtc_state->disable_cxsr)
13451                 return true;
13452
13453         return false;
13454 }
13455
13456 /**
13457  * intel_atomic_commit - commit validated state object
13458  * @dev: DRM device
13459  * @state: the top-level driver state object
13460  * @async: asynchronous commit
13461  *
13462  * This function commits a top-level state object that has been validated
13463  * with drm_atomic_helper_check().
13464  *
13465  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13466  * we can only handle plane-related operations and do not yet support
13467  * asynchronous commit.
13468  *
13469  * RETURNS
13470  * Zero for success or -errno.
13471  */
13472 static int intel_atomic_commit(struct drm_device *dev,
13473                                struct drm_atomic_state *state,
13474                                bool async)
13475 {
13476         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13477         struct drm_i915_private *dev_priv = dev->dev_private;
13478         struct drm_crtc_state *crtc_state;
13479         struct drm_crtc *crtc;
13480         struct intel_crtc_state *intel_cstate;
13481         int ret = 0, i;
13482         bool hw_check = intel_state->modeset;
13483         unsigned long put_domains[I915_MAX_PIPES] = {};
13484         unsigned crtc_vblank_mask = 0;
13485
13486         ret = intel_atomic_prepare_commit(dev, state, async);
13487         if (ret) {
13488                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13489                 return ret;
13490         }
13491
13492         drm_atomic_helper_swap_state(dev, state);
13493         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13494
13495         if (intel_state->modeset) {
13496                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13497                        sizeof(intel_state->min_pixclk));
13498                 dev_priv->active_crtcs = intel_state->active_crtcs;
13499                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13500
13501                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13502         }
13503
13504         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13505                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13506
13507                 if (needs_modeset(crtc->state) ||
13508                     to_intel_crtc_state(crtc->state)->update_pipe) {
13509                         hw_check = true;
13510
13511                         put_domains[to_intel_crtc(crtc)->pipe] =
13512                                 modeset_get_crtc_power_domains(crtc,
13513                                         to_intel_crtc_state(crtc->state));
13514                 }
13515
13516                 if (!needs_modeset(crtc->state))
13517                         continue;
13518
13519                 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13520
13521                 if (crtc_state->active) {
13522                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13523                         dev_priv->display.crtc_disable(crtc);
13524                         intel_crtc->active = false;
13525                         intel_fbc_disable(intel_crtc);
13526                         intel_disable_shared_dpll(intel_crtc);
13527
13528                         /*
13529                          * Underruns don't always raise
13530                          * interrupts, so check manually.
13531                          */
13532                         intel_check_cpu_fifo_underruns(dev_priv);
13533                         intel_check_pch_fifo_underruns(dev_priv);
13534
13535                         if (!crtc->state->active)
13536                                 intel_update_watermarks(crtc);
13537                 }
13538         }
13539
13540         /* Only after disabling all output pipelines that will be changed can we
13541          * update the the output configuration. */
13542         intel_modeset_update_crtc_state(state);
13543
13544         if (intel_state->modeset) {
13545                 intel_shared_dpll_commit(state);
13546
13547                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13548
13549                 if (dev_priv->display.modeset_commit_cdclk &&
13550                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13551                         dev_priv->display.modeset_commit_cdclk(state);
13552         }
13553
13554         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13555         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13556                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13557                 bool modeset = needs_modeset(crtc->state);
13558                 struct intel_crtc_state *pipe_config =
13559                         to_intel_crtc_state(crtc->state);
13560                 bool update_pipe = !modeset && pipe_config->update_pipe;
13561
13562                 if (modeset && crtc->state->active) {
13563                         update_scanline_offset(to_intel_crtc(crtc));
13564                         dev_priv->display.crtc_enable(crtc);
13565                 }
13566
13567                 if (!modeset)
13568                         intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13569
13570                 if (crtc->state->active && intel_crtc->atomic.update_fbc)
13571                         intel_fbc_enable(intel_crtc);
13572
13573                 if (crtc->state->active &&
13574                     (crtc->state->planes_changed || update_pipe))
13575                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13576
13577                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13578                         crtc_vblank_mask |= 1 << i;
13579         }
13580
13581         /* FIXME: add subpixel order */
13582
13583         if (!state->legacy_cursor_update)
13584                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13585
13586         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13587                 intel_post_plane_update(to_intel_crtc(crtc));
13588
13589                 if (put_domains[i])
13590                         modeset_put_power_domains(dev_priv, put_domains[i]);
13591         }
13592
13593         if (intel_state->modeset)
13594                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13595
13596         /*
13597          * Now that the vblank has passed, we can go ahead and program the
13598          * optimal watermarks on platforms that need two-step watermark
13599          * programming.
13600          *
13601          * TODO: Move this (and other cleanup) to an async worker eventually.
13602          */
13603         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13604                 intel_cstate = to_intel_crtc_state(crtc->state);
13605
13606                 if (dev_priv->display.optimize_watermarks)
13607                         dev_priv->display.optimize_watermarks(intel_cstate);
13608         }
13609
13610         mutex_lock(&dev->struct_mutex);
13611         drm_atomic_helper_cleanup_planes(dev, state);
13612         mutex_unlock(&dev->struct_mutex);
13613
13614         if (hw_check)
13615                 intel_modeset_check_state(dev, state);
13616
13617         drm_atomic_state_free(state);
13618
13619         /* As one of the primary mmio accessors, KMS has a high likelihood
13620          * of triggering bugs in unclaimed access. After we finish
13621          * modesetting, see if an error has been flagged, and if so
13622          * enable debugging for the next modeset - and hope we catch
13623          * the culprit.
13624          *
13625          * XXX note that we assume display power is on at this point.
13626          * This might hold true now but we need to add pm helper to check
13627          * unclaimed only when the hardware is on, as atomic commits
13628          * can happen also when the device is completely off.
13629          */
13630         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13631
13632         return 0;
13633 }
13634
13635 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13636 {
13637         struct drm_device *dev = crtc->dev;
13638         struct drm_atomic_state *state;
13639         struct drm_crtc_state *crtc_state;
13640         int ret;
13641
13642         state = drm_atomic_state_alloc(dev);
13643         if (!state) {
13644                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13645                               crtc->base.id);
13646                 return;
13647         }
13648
13649         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13650
13651 retry:
13652         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13653         ret = PTR_ERR_OR_ZERO(crtc_state);
13654         if (!ret) {
13655                 if (!crtc_state->active)
13656                         goto out;
13657
13658                 crtc_state->mode_changed = true;
13659                 ret = drm_atomic_commit(state);
13660         }
13661
13662         if (ret == -EDEADLK) {
13663                 drm_atomic_state_clear(state);
13664                 drm_modeset_backoff(state->acquire_ctx);
13665                 goto retry;
13666         }
13667
13668         if (ret)
13669 out:
13670                 drm_atomic_state_free(state);
13671 }
13672
13673 #undef for_each_intel_crtc_masked
13674
13675 static const struct drm_crtc_funcs intel_crtc_funcs = {
13676         .gamma_set = intel_crtc_gamma_set,
13677         .set_config = drm_atomic_helper_set_config,
13678         .destroy = intel_crtc_destroy,
13679         .page_flip = intel_crtc_page_flip,
13680         .atomic_duplicate_state = intel_crtc_duplicate_state,
13681         .atomic_destroy_state = intel_crtc_destroy_state,
13682 };
13683
13684 /**
13685  * intel_prepare_plane_fb - Prepare fb for usage on plane
13686  * @plane: drm plane to prepare for
13687  * @fb: framebuffer to prepare for presentation
13688  *
13689  * Prepares a framebuffer for usage on a display plane.  Generally this
13690  * involves pinning the underlying object and updating the frontbuffer tracking
13691  * bits.  Some older platforms need special physical address handling for
13692  * cursor planes.
13693  *
13694  * Must be called with struct_mutex held.
13695  *
13696  * Returns 0 on success, negative error code on failure.
13697  */
13698 int
13699 intel_prepare_plane_fb(struct drm_plane *plane,
13700                        const struct drm_plane_state *new_state)
13701 {
13702         struct drm_device *dev = plane->dev;
13703         struct drm_framebuffer *fb = new_state->fb;
13704         struct intel_plane *intel_plane = to_intel_plane(plane);
13705         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13706         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13707         int ret = 0;
13708
13709         if (!obj && !old_obj)
13710                 return 0;
13711
13712         if (old_obj) {
13713                 struct drm_crtc_state *crtc_state =
13714                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13715
13716                 /* Big Hammer, we also need to ensure that any pending
13717                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13718                  * current scanout is retired before unpinning the old
13719                  * framebuffer. Note that we rely on userspace rendering
13720                  * into the buffer attached to the pipe they are waiting
13721                  * on. If not, userspace generates a GPU hang with IPEHR
13722                  * point to the MI_WAIT_FOR_EVENT.
13723                  *
13724                  * This should only fail upon a hung GPU, in which case we
13725                  * can safely continue.
13726                  */
13727                 if (needs_modeset(crtc_state))
13728                         ret = i915_gem_object_wait_rendering(old_obj, true);
13729
13730                 /* Swallow -EIO errors to allow updates during hw lockup. */
13731                 if (ret && ret != -EIO)
13732                         return ret;
13733         }
13734
13735         /* For framebuffer backed by dmabuf, wait for fence */
13736         if (obj && obj->base.dma_buf) {
13737                 long lret;
13738
13739                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13740                                                            false, true,
13741                                                            MAX_SCHEDULE_TIMEOUT);
13742                 if (lret == -ERESTARTSYS)
13743                         return lret;
13744
13745                 WARN(lret < 0, "waiting returns %li\n", lret);
13746         }
13747
13748         if (!obj) {
13749                 ret = 0;
13750         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13751             INTEL_INFO(dev)->cursor_needs_physical) {
13752                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13753                 ret = i915_gem_object_attach_phys(obj, align);
13754                 if (ret)
13755                         DRM_DEBUG_KMS("failed to attach phys object\n");
13756         } else {
13757                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13758         }
13759
13760         if (ret == 0) {
13761                 if (obj) {
13762                         struct intel_plane_state *plane_state =
13763                                 to_intel_plane_state(new_state);
13764
13765                         i915_gem_request_assign(&plane_state->wait_req,
13766                                                 obj->last_write_req);
13767                 }
13768
13769                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13770         }
13771
13772         return ret;
13773 }
13774
13775 /**
13776  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13777  * @plane: drm plane to clean up for
13778  * @fb: old framebuffer that was on plane
13779  *
13780  * Cleans up a framebuffer that has just been removed from a plane.
13781  *
13782  * Must be called with struct_mutex held.
13783  */
13784 void
13785 intel_cleanup_plane_fb(struct drm_plane *plane,
13786                        const struct drm_plane_state *old_state)
13787 {
13788         struct drm_device *dev = plane->dev;
13789         struct intel_plane *intel_plane = to_intel_plane(plane);
13790         struct intel_plane_state *old_intel_state;
13791         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13792         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13793
13794         old_intel_state = to_intel_plane_state(old_state);
13795
13796         if (!obj && !old_obj)
13797                 return;
13798
13799         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13800             !INTEL_INFO(dev)->cursor_needs_physical))
13801                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13802
13803         /* prepare_fb aborted? */
13804         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13805             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13806                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13807
13808         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13809 }
13810
13811 int
13812 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13813 {
13814         int max_scale;
13815         struct drm_device *dev;
13816         struct drm_i915_private *dev_priv;
13817         int crtc_clock, cdclk;
13818
13819         if (!intel_crtc || !crtc_state->base.enable)
13820                 return DRM_PLANE_HELPER_NO_SCALING;
13821
13822         dev = intel_crtc->base.dev;
13823         dev_priv = dev->dev_private;
13824         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13825         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13826
13827         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13828                 return DRM_PLANE_HELPER_NO_SCALING;
13829
13830         /*
13831          * skl max scale is lower of:
13832          *    close to 3 but not 3, -1 is for that purpose
13833          *            or
13834          *    cdclk/crtc_clock
13835          */
13836         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13837
13838         return max_scale;
13839 }
13840
13841 static int
13842 intel_check_primary_plane(struct drm_plane *plane,
13843                           struct intel_crtc_state *crtc_state,
13844                           struct intel_plane_state *state)
13845 {
13846         struct drm_crtc *crtc = state->base.crtc;
13847         struct drm_framebuffer *fb = state->base.fb;
13848         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13849         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13850         bool can_position = false;
13851
13852         if (INTEL_INFO(plane->dev)->gen >= 9) {
13853                 /* use scaler when colorkey is not required */
13854                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13855                         min_scale = 1;
13856                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13857                 }
13858                 can_position = true;
13859         }
13860
13861         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13862                                              &state->dst, &state->clip,
13863                                              min_scale, max_scale,
13864                                              can_position, true,
13865                                              &state->visible);
13866 }
13867
13868 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13869                                     struct drm_crtc_state *old_crtc_state)
13870 {
13871         struct drm_device *dev = crtc->dev;
13872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13873         struct intel_crtc_state *old_intel_state =
13874                 to_intel_crtc_state(old_crtc_state);
13875         bool modeset = needs_modeset(crtc->state);
13876
13877         /* Perform vblank evasion around commit operation */
13878         intel_pipe_update_start(intel_crtc);
13879
13880         if (modeset)
13881                 return;
13882
13883         if (to_intel_crtc_state(crtc->state)->update_pipe)
13884                 intel_update_pipe_config(intel_crtc, old_intel_state);
13885         else if (INTEL_INFO(dev)->gen >= 9)
13886                 skl_detach_scalers(intel_crtc);
13887 }
13888
13889 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13890                                      struct drm_crtc_state *old_crtc_state)
13891 {
13892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13893
13894         intel_pipe_update_end(intel_crtc);
13895 }
13896
13897 /**
13898  * intel_plane_destroy - destroy a plane
13899  * @plane: plane to destroy
13900  *
13901  * Common destruction function for all types of planes (primary, cursor,
13902  * sprite).
13903  */
13904 void intel_plane_destroy(struct drm_plane *plane)
13905 {
13906         struct intel_plane *intel_plane = to_intel_plane(plane);
13907         drm_plane_cleanup(plane);
13908         kfree(intel_plane);
13909 }
13910
13911 const struct drm_plane_funcs intel_plane_funcs = {
13912         .update_plane = drm_atomic_helper_update_plane,
13913         .disable_plane = drm_atomic_helper_disable_plane,
13914         .destroy = intel_plane_destroy,
13915         .set_property = drm_atomic_helper_plane_set_property,
13916         .atomic_get_property = intel_plane_atomic_get_property,
13917         .atomic_set_property = intel_plane_atomic_set_property,
13918         .atomic_duplicate_state = intel_plane_duplicate_state,
13919         .atomic_destroy_state = intel_plane_destroy_state,
13920
13921 };
13922
13923 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13924                                                     int pipe)
13925 {
13926         struct intel_plane *primary;
13927         struct intel_plane_state *state;
13928         const uint32_t *intel_primary_formats;
13929         unsigned int num_formats;
13930
13931         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13932         if (primary == NULL)
13933                 return NULL;
13934
13935         state = intel_create_plane_state(&primary->base);
13936         if (!state) {
13937                 kfree(primary);
13938                 return NULL;
13939         }
13940         primary->base.state = &state->base;
13941
13942         primary->can_scale = false;
13943         primary->max_downscale = 1;
13944         if (INTEL_INFO(dev)->gen >= 9) {
13945                 primary->can_scale = true;
13946                 state->scaler_id = -1;
13947         }
13948         primary->pipe = pipe;
13949         primary->plane = pipe;
13950         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13951         primary->check_plane = intel_check_primary_plane;
13952         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13953                 primary->plane = !pipe;
13954
13955         if (INTEL_INFO(dev)->gen >= 9) {
13956                 intel_primary_formats = skl_primary_formats;
13957                 num_formats = ARRAY_SIZE(skl_primary_formats);
13958
13959                 primary->update_plane = skylake_update_primary_plane;
13960                 primary->disable_plane = skylake_disable_primary_plane;
13961         } else if (HAS_PCH_SPLIT(dev)) {
13962                 intel_primary_formats = i965_primary_formats;
13963                 num_formats = ARRAY_SIZE(i965_primary_formats);
13964
13965                 primary->update_plane = ironlake_update_primary_plane;
13966                 primary->disable_plane = i9xx_disable_primary_plane;
13967         } else if (INTEL_INFO(dev)->gen >= 4) {
13968                 intel_primary_formats = i965_primary_formats;
13969                 num_formats = ARRAY_SIZE(i965_primary_formats);
13970
13971                 primary->update_plane = i9xx_update_primary_plane;
13972                 primary->disable_plane = i9xx_disable_primary_plane;
13973         } else {
13974                 intel_primary_formats = i8xx_primary_formats;
13975                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13976
13977                 primary->update_plane = i9xx_update_primary_plane;
13978                 primary->disable_plane = i9xx_disable_primary_plane;
13979         }
13980
13981         drm_universal_plane_init(dev, &primary->base, 0,
13982                                  &intel_plane_funcs,
13983                                  intel_primary_formats, num_formats,
13984                                  DRM_PLANE_TYPE_PRIMARY, NULL);
13985
13986         if (INTEL_INFO(dev)->gen >= 4)
13987                 intel_create_rotation_property(dev, primary);
13988
13989         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13990
13991         return &primary->base;
13992 }
13993
13994 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13995 {
13996         if (!dev->mode_config.rotation_property) {
13997                 unsigned long flags = BIT(DRM_ROTATE_0) |
13998                         BIT(DRM_ROTATE_180);
13999
14000                 if (INTEL_INFO(dev)->gen >= 9)
14001                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14002
14003                 dev->mode_config.rotation_property =
14004                         drm_mode_create_rotation_property(dev, flags);
14005         }
14006         if (dev->mode_config.rotation_property)
14007                 drm_object_attach_property(&plane->base.base,
14008                                 dev->mode_config.rotation_property,
14009                                 plane->base.state->rotation);
14010 }
14011
14012 static int
14013 intel_check_cursor_plane(struct drm_plane *plane,
14014                          struct intel_crtc_state *crtc_state,
14015                          struct intel_plane_state *state)
14016 {
14017         struct drm_crtc *crtc = crtc_state->base.crtc;
14018         struct drm_framebuffer *fb = state->base.fb;
14019         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14020         enum pipe pipe = to_intel_plane(plane)->pipe;
14021         unsigned stride;
14022         int ret;
14023
14024         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14025                                             &state->dst, &state->clip,
14026                                             DRM_PLANE_HELPER_NO_SCALING,
14027                                             DRM_PLANE_HELPER_NO_SCALING,
14028                                             true, true, &state->visible);
14029         if (ret)
14030                 return ret;
14031
14032         /* if we want to turn off the cursor ignore width and height */
14033         if (!obj)
14034                 return 0;
14035
14036         /* Check for which cursor types we support */
14037         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14038                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14039                           state->base.crtc_w, state->base.crtc_h);
14040                 return -EINVAL;
14041         }
14042
14043         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14044         if (obj->base.size < stride * state->base.crtc_h) {
14045                 DRM_DEBUG_KMS("buffer is too small\n");
14046                 return -ENOMEM;
14047         }
14048
14049         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14050                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14051                 return -EINVAL;
14052         }
14053
14054         /*
14055          * There's something wrong with the cursor on CHV pipe C.
14056          * If it straddles the left edge of the screen then
14057          * moving it away from the edge or disabling it often
14058          * results in a pipe underrun, and often that can lead to
14059          * dead pipe (constant underrun reported, and it scans
14060          * out just a solid color). To recover from that, the
14061          * display power well must be turned off and on again.
14062          * Refuse the put the cursor into that compromised position.
14063          */
14064         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14065             state->visible && state->base.crtc_x < 0) {
14066                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14067                 return -EINVAL;
14068         }
14069
14070         return 0;
14071 }
14072
14073 static void
14074 intel_disable_cursor_plane(struct drm_plane *plane,
14075                            struct drm_crtc *crtc)
14076 {
14077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14078
14079         intel_crtc->cursor_addr = 0;
14080         intel_crtc_update_cursor(crtc, NULL);
14081 }
14082
14083 static void
14084 intel_update_cursor_plane(struct drm_plane *plane,
14085                           const struct intel_crtc_state *crtc_state,
14086                           const struct intel_plane_state *state)
14087 {
14088         struct drm_crtc *crtc = crtc_state->base.crtc;
14089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14090         struct drm_device *dev = plane->dev;
14091         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14092         uint32_t addr;
14093
14094         if (!obj)
14095                 addr = 0;
14096         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14097                 addr = i915_gem_obj_ggtt_offset(obj);
14098         else
14099                 addr = obj->phys_handle->busaddr;
14100
14101         intel_crtc->cursor_addr = addr;
14102         intel_crtc_update_cursor(crtc, state);
14103 }
14104
14105 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14106                                                    int pipe)
14107 {
14108         struct intel_plane *cursor;
14109         struct intel_plane_state *state;
14110
14111         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14112         if (cursor == NULL)
14113                 return NULL;
14114
14115         state = intel_create_plane_state(&cursor->base);
14116         if (!state) {
14117                 kfree(cursor);
14118                 return NULL;
14119         }
14120         cursor->base.state = &state->base;
14121
14122         cursor->can_scale = false;
14123         cursor->max_downscale = 1;
14124         cursor->pipe = pipe;
14125         cursor->plane = pipe;
14126         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14127         cursor->check_plane = intel_check_cursor_plane;
14128         cursor->update_plane = intel_update_cursor_plane;
14129         cursor->disable_plane = intel_disable_cursor_plane;
14130
14131         drm_universal_plane_init(dev, &cursor->base, 0,
14132                                  &intel_plane_funcs,
14133                                  intel_cursor_formats,
14134                                  ARRAY_SIZE(intel_cursor_formats),
14135                                  DRM_PLANE_TYPE_CURSOR, NULL);
14136
14137         if (INTEL_INFO(dev)->gen >= 4) {
14138                 if (!dev->mode_config.rotation_property)
14139                         dev->mode_config.rotation_property =
14140                                 drm_mode_create_rotation_property(dev,
14141                                                         BIT(DRM_ROTATE_0) |
14142                                                         BIT(DRM_ROTATE_180));
14143                 if (dev->mode_config.rotation_property)
14144                         drm_object_attach_property(&cursor->base.base,
14145                                 dev->mode_config.rotation_property,
14146                                 state->base.rotation);
14147         }
14148
14149         if (INTEL_INFO(dev)->gen >=9)
14150                 state->scaler_id = -1;
14151
14152         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14153
14154         return &cursor->base;
14155 }
14156
14157 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14158         struct intel_crtc_state *crtc_state)
14159 {
14160         int i;
14161         struct intel_scaler *intel_scaler;
14162         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14163
14164         for (i = 0; i < intel_crtc->num_scalers; i++) {
14165                 intel_scaler = &scaler_state->scalers[i];
14166                 intel_scaler->in_use = 0;
14167                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14168         }
14169
14170         scaler_state->scaler_id = -1;
14171 }
14172
14173 static void intel_crtc_init(struct drm_device *dev, int pipe)
14174 {
14175         struct drm_i915_private *dev_priv = dev->dev_private;
14176         struct intel_crtc *intel_crtc;
14177         struct intel_crtc_state *crtc_state = NULL;
14178         struct drm_plane *primary = NULL;
14179         struct drm_plane *cursor = NULL;
14180         int i, ret;
14181
14182         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14183         if (intel_crtc == NULL)
14184                 return;
14185
14186         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14187         if (!crtc_state)
14188                 goto fail;
14189         intel_crtc->config = crtc_state;
14190         intel_crtc->base.state = &crtc_state->base;
14191         crtc_state->base.crtc = &intel_crtc->base;
14192
14193         /* initialize shared scalers */
14194         if (INTEL_INFO(dev)->gen >= 9) {
14195                 if (pipe == PIPE_C)
14196                         intel_crtc->num_scalers = 1;
14197                 else
14198                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14199
14200                 skl_init_scalers(dev, intel_crtc, crtc_state);
14201         }
14202
14203         primary = intel_primary_plane_create(dev, pipe);
14204         if (!primary)
14205                 goto fail;
14206
14207         cursor = intel_cursor_plane_create(dev, pipe);
14208         if (!cursor)
14209                 goto fail;
14210
14211         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14212                                         cursor, &intel_crtc_funcs, NULL);
14213         if (ret)
14214                 goto fail;
14215
14216         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14217         for (i = 0; i < 256; i++) {
14218                 intel_crtc->lut_r[i] = i;
14219                 intel_crtc->lut_g[i] = i;
14220                 intel_crtc->lut_b[i] = i;
14221         }
14222
14223         /*
14224          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14225          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14226          */
14227         intel_crtc->pipe = pipe;
14228         intel_crtc->plane = pipe;
14229         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14230                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14231                 intel_crtc->plane = !pipe;
14232         }
14233
14234         intel_crtc->cursor_base = ~0;
14235         intel_crtc->cursor_cntl = ~0;
14236         intel_crtc->cursor_size = ~0;
14237
14238         intel_crtc->wm.cxsr_allowed = true;
14239
14240         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14241                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14242         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14243         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14244
14245         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14246
14247         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14248         return;
14249
14250 fail:
14251         if (primary)
14252                 drm_plane_cleanup(primary);
14253         if (cursor)
14254                 drm_plane_cleanup(cursor);
14255         kfree(crtc_state);
14256         kfree(intel_crtc);
14257 }
14258
14259 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14260 {
14261         struct drm_encoder *encoder = connector->base.encoder;
14262         struct drm_device *dev = connector->base.dev;
14263
14264         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14265
14266         if (!encoder || WARN_ON(!encoder->crtc))
14267                 return INVALID_PIPE;
14268
14269         return to_intel_crtc(encoder->crtc)->pipe;
14270 }
14271
14272 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14273                                 struct drm_file *file)
14274 {
14275         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14276         struct drm_crtc *drmmode_crtc;
14277         struct intel_crtc *crtc;
14278
14279         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14280
14281         if (!drmmode_crtc) {
14282                 DRM_ERROR("no such CRTC id\n");
14283                 return -ENOENT;
14284         }
14285
14286         crtc = to_intel_crtc(drmmode_crtc);
14287         pipe_from_crtc_id->pipe = crtc->pipe;
14288
14289         return 0;
14290 }
14291
14292 static int intel_encoder_clones(struct intel_encoder *encoder)
14293 {
14294         struct drm_device *dev = encoder->base.dev;
14295         struct intel_encoder *source_encoder;
14296         int index_mask = 0;
14297         int entry = 0;
14298
14299         for_each_intel_encoder(dev, source_encoder) {
14300                 if (encoders_cloneable(encoder, source_encoder))
14301                         index_mask |= (1 << entry);
14302
14303                 entry++;
14304         }
14305
14306         return index_mask;
14307 }
14308
14309 static bool has_edp_a(struct drm_device *dev)
14310 {
14311         struct drm_i915_private *dev_priv = dev->dev_private;
14312
14313         if (!IS_MOBILE(dev))
14314                 return false;
14315
14316         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14317                 return false;
14318
14319         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14320                 return false;
14321
14322         return true;
14323 }
14324
14325 static bool intel_crt_present(struct drm_device *dev)
14326 {
14327         struct drm_i915_private *dev_priv = dev->dev_private;
14328
14329         if (INTEL_INFO(dev)->gen >= 9)
14330                 return false;
14331
14332         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14333                 return false;
14334
14335         if (IS_CHERRYVIEW(dev))
14336                 return false;
14337
14338         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14339                 return false;
14340
14341         /* DDI E can't be used if DDI A requires 4 lanes */
14342         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14343                 return false;
14344
14345         if (!dev_priv->vbt.int_crt_support)
14346                 return false;
14347
14348         return true;
14349 }
14350
14351 static void intel_setup_outputs(struct drm_device *dev)
14352 {
14353         struct drm_i915_private *dev_priv = dev->dev_private;
14354         struct intel_encoder *encoder;
14355         bool dpd_is_edp = false;
14356
14357         intel_lvds_init(dev);
14358
14359         if (intel_crt_present(dev))
14360                 intel_crt_init(dev);
14361
14362         if (IS_BROXTON(dev)) {
14363                 /*
14364                  * FIXME: Broxton doesn't support port detection via the
14365                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14366                  * detect the ports.
14367                  */
14368                 intel_ddi_init(dev, PORT_A);
14369                 intel_ddi_init(dev, PORT_B);
14370                 intel_ddi_init(dev, PORT_C);
14371         } else if (HAS_DDI(dev)) {
14372                 int found;
14373
14374                 /*
14375                  * Haswell uses DDI functions to detect digital outputs.
14376                  * On SKL pre-D0 the strap isn't connected, so we assume
14377                  * it's there.
14378                  */
14379                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14380                 /* WaIgnoreDDIAStrap: skl */
14381                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14382                         intel_ddi_init(dev, PORT_A);
14383
14384                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14385                  * register */
14386                 found = I915_READ(SFUSE_STRAP);
14387
14388                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14389                         intel_ddi_init(dev, PORT_B);
14390                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14391                         intel_ddi_init(dev, PORT_C);
14392                 if (found & SFUSE_STRAP_DDID_DETECTED)
14393                         intel_ddi_init(dev, PORT_D);
14394                 /*
14395                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14396                  */
14397                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14398                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14399                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14400                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14401                         intel_ddi_init(dev, PORT_E);
14402
14403         } else if (HAS_PCH_SPLIT(dev)) {
14404                 int found;
14405                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14406
14407                 if (has_edp_a(dev))
14408                         intel_dp_init(dev, DP_A, PORT_A);
14409
14410                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14411                         /* PCH SDVOB multiplex with HDMIB */
14412                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14413                         if (!found)
14414                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14415                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14416                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14417                 }
14418
14419                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14420                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14421
14422                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14423                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14424
14425                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14426                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14427
14428                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14429                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14430         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14431                 /*
14432                  * The DP_DETECTED bit is the latched state of the DDC
14433                  * SDA pin at boot. However since eDP doesn't require DDC
14434                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14435                  * eDP ports may have been muxed to an alternate function.
14436                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14437                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14438                  * detect eDP ports.
14439                  */
14440                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14441                     !intel_dp_is_edp(dev, PORT_B))
14442                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14443                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14444                     intel_dp_is_edp(dev, PORT_B))
14445                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14446
14447                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14448                     !intel_dp_is_edp(dev, PORT_C))
14449                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14450                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14451                     intel_dp_is_edp(dev, PORT_C))
14452                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14453
14454                 if (IS_CHERRYVIEW(dev)) {
14455                         /* eDP not supported on port D, so don't check VBT */
14456                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14457                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14458                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14459                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14460                 }
14461
14462                 intel_dsi_init(dev);
14463         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14464                 bool found = false;
14465
14466                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14467                         DRM_DEBUG_KMS("probing SDVOB\n");
14468                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14469                         if (!found && IS_G4X(dev)) {
14470                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14471                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14472                         }
14473
14474                         if (!found && IS_G4X(dev))
14475                                 intel_dp_init(dev, DP_B, PORT_B);
14476                 }
14477
14478                 /* Before G4X SDVOC doesn't have its own detect register */
14479
14480                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14481                         DRM_DEBUG_KMS("probing SDVOC\n");
14482                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14483                 }
14484
14485                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14486
14487                         if (IS_G4X(dev)) {
14488                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14489                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14490                         }
14491                         if (IS_G4X(dev))
14492                                 intel_dp_init(dev, DP_C, PORT_C);
14493                 }
14494
14495                 if (IS_G4X(dev) &&
14496                     (I915_READ(DP_D) & DP_DETECTED))
14497                         intel_dp_init(dev, DP_D, PORT_D);
14498         } else if (IS_GEN2(dev))
14499                 intel_dvo_init(dev);
14500
14501         if (SUPPORTS_TV(dev))
14502                 intel_tv_init(dev);
14503
14504         intel_psr_init(dev);
14505
14506         for_each_intel_encoder(dev, encoder) {
14507                 encoder->base.possible_crtcs = encoder->crtc_mask;
14508                 encoder->base.possible_clones =
14509                         intel_encoder_clones(encoder);
14510         }
14511
14512         intel_init_pch_refclk(dev);
14513
14514         drm_helper_move_panel_connectors_to_head(dev);
14515 }
14516
14517 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14518 {
14519         struct drm_device *dev = fb->dev;
14520         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14521
14522         drm_framebuffer_cleanup(fb);
14523         mutex_lock(&dev->struct_mutex);
14524         WARN_ON(!intel_fb->obj->framebuffer_references--);
14525         drm_gem_object_unreference(&intel_fb->obj->base);
14526         mutex_unlock(&dev->struct_mutex);
14527         kfree(intel_fb);
14528 }
14529
14530 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14531                                                 struct drm_file *file,
14532                                                 unsigned int *handle)
14533 {
14534         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14535         struct drm_i915_gem_object *obj = intel_fb->obj;
14536
14537         if (obj->userptr.mm) {
14538                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14539                 return -EINVAL;
14540         }
14541
14542         return drm_gem_handle_create(file, &obj->base, handle);
14543 }
14544
14545 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14546                                         struct drm_file *file,
14547                                         unsigned flags, unsigned color,
14548                                         struct drm_clip_rect *clips,
14549                                         unsigned num_clips)
14550 {
14551         struct drm_device *dev = fb->dev;
14552         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14553         struct drm_i915_gem_object *obj = intel_fb->obj;
14554
14555         mutex_lock(&dev->struct_mutex);
14556         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14557         mutex_unlock(&dev->struct_mutex);
14558
14559         return 0;
14560 }
14561
14562 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14563         .destroy = intel_user_framebuffer_destroy,
14564         .create_handle = intel_user_framebuffer_create_handle,
14565         .dirty = intel_user_framebuffer_dirty,
14566 };
14567
14568 static
14569 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14570                          uint32_t pixel_format)
14571 {
14572         u32 gen = INTEL_INFO(dev)->gen;
14573
14574         if (gen >= 9) {
14575                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14576
14577                 /* "The stride in bytes must not exceed the of the size of 8K
14578                  *  pixels and 32K bytes."
14579                  */
14580                 return min(8192 * cpp, 32768);
14581         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14582                 return 32*1024;
14583         } else if (gen >= 4) {
14584                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14585                         return 16*1024;
14586                 else
14587                         return 32*1024;
14588         } else if (gen >= 3) {
14589                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14590                         return 8*1024;
14591                 else
14592                         return 16*1024;
14593         } else {
14594                 /* XXX DSPC is limited to 4k tiled */
14595                 return 8*1024;
14596         }
14597 }
14598
14599 static int intel_framebuffer_init(struct drm_device *dev,
14600                                   struct intel_framebuffer *intel_fb,
14601                                   struct drm_mode_fb_cmd2 *mode_cmd,
14602                                   struct drm_i915_gem_object *obj)
14603 {
14604         struct drm_i915_private *dev_priv = to_i915(dev);
14605         unsigned int aligned_height;
14606         int ret;
14607         u32 pitch_limit, stride_alignment;
14608
14609         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14610
14611         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14612                 /* Enforce that fb modifier and tiling mode match, but only for
14613                  * X-tiled. This is needed for FBC. */
14614                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14615                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14616                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14617                         return -EINVAL;
14618                 }
14619         } else {
14620                 if (obj->tiling_mode == I915_TILING_X)
14621                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14622                 else if (obj->tiling_mode == I915_TILING_Y) {
14623                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14624                         return -EINVAL;
14625                 }
14626         }
14627
14628         /* Passed in modifier sanity checking. */
14629         switch (mode_cmd->modifier[0]) {
14630         case I915_FORMAT_MOD_Y_TILED:
14631         case I915_FORMAT_MOD_Yf_TILED:
14632                 if (INTEL_INFO(dev)->gen < 9) {
14633                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14634                                   mode_cmd->modifier[0]);
14635                         return -EINVAL;
14636                 }
14637         case DRM_FORMAT_MOD_NONE:
14638         case I915_FORMAT_MOD_X_TILED:
14639                 break;
14640         default:
14641                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14642                           mode_cmd->modifier[0]);
14643                 return -EINVAL;
14644         }
14645
14646         stride_alignment = intel_fb_stride_alignment(dev_priv,
14647                                                      mode_cmd->modifier[0],
14648                                                      mode_cmd->pixel_format);
14649         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14650                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14651                           mode_cmd->pitches[0], stride_alignment);
14652                 return -EINVAL;
14653         }
14654
14655         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14656                                            mode_cmd->pixel_format);
14657         if (mode_cmd->pitches[0] > pitch_limit) {
14658                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14659                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14660                           "tiled" : "linear",
14661                           mode_cmd->pitches[0], pitch_limit);
14662                 return -EINVAL;
14663         }
14664
14665         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14666             mode_cmd->pitches[0] != obj->stride) {
14667                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14668                           mode_cmd->pitches[0], obj->stride);
14669                 return -EINVAL;
14670         }
14671
14672         /* Reject formats not supported by any plane early. */
14673         switch (mode_cmd->pixel_format) {
14674         case DRM_FORMAT_C8:
14675         case DRM_FORMAT_RGB565:
14676         case DRM_FORMAT_XRGB8888:
14677         case DRM_FORMAT_ARGB8888:
14678                 break;
14679         case DRM_FORMAT_XRGB1555:
14680                 if (INTEL_INFO(dev)->gen > 3) {
14681                         DRM_DEBUG("unsupported pixel format: %s\n",
14682                                   drm_get_format_name(mode_cmd->pixel_format));
14683                         return -EINVAL;
14684                 }
14685                 break;
14686         case DRM_FORMAT_ABGR8888:
14687                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14688                     INTEL_INFO(dev)->gen < 9) {
14689                         DRM_DEBUG("unsupported pixel format: %s\n",
14690                                   drm_get_format_name(mode_cmd->pixel_format));
14691                         return -EINVAL;
14692                 }
14693                 break;
14694         case DRM_FORMAT_XBGR8888:
14695         case DRM_FORMAT_XRGB2101010:
14696         case DRM_FORMAT_XBGR2101010:
14697                 if (INTEL_INFO(dev)->gen < 4) {
14698                         DRM_DEBUG("unsupported pixel format: %s\n",
14699                                   drm_get_format_name(mode_cmd->pixel_format));
14700                         return -EINVAL;
14701                 }
14702                 break;
14703         case DRM_FORMAT_ABGR2101010:
14704                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14705                         DRM_DEBUG("unsupported pixel format: %s\n",
14706                                   drm_get_format_name(mode_cmd->pixel_format));
14707                         return -EINVAL;
14708                 }
14709                 break;
14710         case DRM_FORMAT_YUYV:
14711         case DRM_FORMAT_UYVY:
14712         case DRM_FORMAT_YVYU:
14713         case DRM_FORMAT_VYUY:
14714                 if (INTEL_INFO(dev)->gen < 5) {
14715                         DRM_DEBUG("unsupported pixel format: %s\n",
14716                                   drm_get_format_name(mode_cmd->pixel_format));
14717                         return -EINVAL;
14718                 }
14719                 break;
14720         default:
14721                 DRM_DEBUG("unsupported pixel format: %s\n",
14722                           drm_get_format_name(mode_cmd->pixel_format));
14723                 return -EINVAL;
14724         }
14725
14726         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14727         if (mode_cmd->offsets[0] != 0)
14728                 return -EINVAL;
14729
14730         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14731                                                mode_cmd->pixel_format,
14732                                                mode_cmd->modifier[0]);
14733         /* FIXME drm helper for size checks (especially planar formats)? */
14734         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14735                 return -EINVAL;
14736
14737         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14738         intel_fb->obj = obj;
14739
14740         intel_fill_fb_info(dev_priv, &intel_fb->base);
14741
14742         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14743         if (ret) {
14744                 DRM_ERROR("framebuffer init failed %d\n", ret);
14745                 return ret;
14746         }
14747
14748         intel_fb->obj->framebuffer_references++;
14749
14750         return 0;
14751 }
14752
14753 static struct drm_framebuffer *
14754 intel_user_framebuffer_create(struct drm_device *dev,
14755                               struct drm_file *filp,
14756                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14757 {
14758         struct drm_framebuffer *fb;
14759         struct drm_i915_gem_object *obj;
14760         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14761
14762         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14763                                                 mode_cmd.handles[0]));
14764         if (&obj->base == NULL)
14765                 return ERR_PTR(-ENOENT);
14766
14767         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14768         if (IS_ERR(fb))
14769                 drm_gem_object_unreference_unlocked(&obj->base);
14770
14771         return fb;
14772 }
14773
14774 #ifndef CONFIG_DRM_FBDEV_EMULATION
14775 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14776 {
14777 }
14778 #endif
14779
14780 static const struct drm_mode_config_funcs intel_mode_funcs = {
14781         .fb_create = intel_user_framebuffer_create,
14782         .output_poll_changed = intel_fbdev_output_poll_changed,
14783         .atomic_check = intel_atomic_check,
14784         .atomic_commit = intel_atomic_commit,
14785         .atomic_state_alloc = intel_atomic_state_alloc,
14786         .atomic_state_clear = intel_atomic_state_clear,
14787 };
14788
14789 /* Set up chip specific display functions */
14790 static void intel_init_display(struct drm_device *dev)
14791 {
14792         struct drm_i915_private *dev_priv = dev->dev_private;
14793
14794         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14795                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14796         else if (IS_CHERRYVIEW(dev))
14797                 dev_priv->display.find_dpll = chv_find_best_dpll;
14798         else if (IS_VALLEYVIEW(dev))
14799                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14800         else if (IS_PINEVIEW(dev))
14801                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14802         else
14803                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14804
14805         if (INTEL_INFO(dev)->gen >= 9) {
14806                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14807                 dev_priv->display.get_initial_plane_config =
14808                         skylake_get_initial_plane_config;
14809                 dev_priv->display.crtc_compute_clock =
14810                         haswell_crtc_compute_clock;
14811                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14812                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14813         } else if (HAS_DDI(dev)) {
14814                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14815                 dev_priv->display.get_initial_plane_config =
14816                         ironlake_get_initial_plane_config;
14817                 dev_priv->display.crtc_compute_clock =
14818                         haswell_crtc_compute_clock;
14819                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14820                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14821         } else if (HAS_PCH_SPLIT(dev)) {
14822                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14823                 dev_priv->display.get_initial_plane_config =
14824                         ironlake_get_initial_plane_config;
14825                 dev_priv->display.crtc_compute_clock =
14826                         ironlake_crtc_compute_clock;
14827                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14828                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14829         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14830                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14831                 dev_priv->display.get_initial_plane_config =
14832                         i9xx_get_initial_plane_config;
14833                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14834                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14835                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14836         } else {
14837                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14838                 dev_priv->display.get_initial_plane_config =
14839                         i9xx_get_initial_plane_config;
14840                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14841                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14842                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14843         }
14844
14845         /* Returns the core display clock speed */
14846         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14847                 dev_priv->display.get_display_clock_speed =
14848                         skylake_get_display_clock_speed;
14849         else if (IS_BROXTON(dev))
14850                 dev_priv->display.get_display_clock_speed =
14851                         broxton_get_display_clock_speed;
14852         else if (IS_BROADWELL(dev))
14853                 dev_priv->display.get_display_clock_speed =
14854                         broadwell_get_display_clock_speed;
14855         else if (IS_HASWELL(dev))
14856                 dev_priv->display.get_display_clock_speed =
14857                         haswell_get_display_clock_speed;
14858         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14859                 dev_priv->display.get_display_clock_speed =
14860                         valleyview_get_display_clock_speed;
14861         else if (IS_GEN5(dev))
14862                 dev_priv->display.get_display_clock_speed =
14863                         ilk_get_display_clock_speed;
14864         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14865                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14866                 dev_priv->display.get_display_clock_speed =
14867                         i945_get_display_clock_speed;
14868         else if (IS_GM45(dev))
14869                 dev_priv->display.get_display_clock_speed =
14870                         gm45_get_display_clock_speed;
14871         else if (IS_CRESTLINE(dev))
14872                 dev_priv->display.get_display_clock_speed =
14873                         i965gm_get_display_clock_speed;
14874         else if (IS_PINEVIEW(dev))
14875                 dev_priv->display.get_display_clock_speed =
14876                         pnv_get_display_clock_speed;
14877         else if (IS_G33(dev) || IS_G4X(dev))
14878                 dev_priv->display.get_display_clock_speed =
14879                         g33_get_display_clock_speed;
14880         else if (IS_I915G(dev))
14881                 dev_priv->display.get_display_clock_speed =
14882                         i915_get_display_clock_speed;
14883         else if (IS_I945GM(dev) || IS_845G(dev))
14884                 dev_priv->display.get_display_clock_speed =
14885                         i9xx_misc_get_display_clock_speed;
14886         else if (IS_I915GM(dev))
14887                 dev_priv->display.get_display_clock_speed =
14888                         i915gm_get_display_clock_speed;
14889         else if (IS_I865G(dev))
14890                 dev_priv->display.get_display_clock_speed =
14891                         i865_get_display_clock_speed;
14892         else if (IS_I85X(dev))
14893                 dev_priv->display.get_display_clock_speed =
14894                         i85x_get_display_clock_speed;
14895         else { /* 830 */
14896                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14897                 dev_priv->display.get_display_clock_speed =
14898                         i830_get_display_clock_speed;
14899         }
14900
14901         if (IS_GEN5(dev)) {
14902                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14903         } else if (IS_GEN6(dev)) {
14904                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14905         } else if (IS_IVYBRIDGE(dev)) {
14906                 /* FIXME: detect B0+ stepping and use auto training */
14907                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14908         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14909                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14910                 if (IS_BROADWELL(dev)) {
14911                         dev_priv->display.modeset_commit_cdclk =
14912                                 broadwell_modeset_commit_cdclk;
14913                         dev_priv->display.modeset_calc_cdclk =
14914                                 broadwell_modeset_calc_cdclk;
14915                 }
14916         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14917                 dev_priv->display.modeset_commit_cdclk =
14918                         valleyview_modeset_commit_cdclk;
14919                 dev_priv->display.modeset_calc_cdclk =
14920                         valleyview_modeset_calc_cdclk;
14921         } else if (IS_BROXTON(dev)) {
14922                 dev_priv->display.modeset_commit_cdclk =
14923                         broxton_modeset_commit_cdclk;
14924                 dev_priv->display.modeset_calc_cdclk =
14925                         broxton_modeset_calc_cdclk;
14926         }
14927
14928         switch (INTEL_INFO(dev)->gen) {
14929         case 2:
14930                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14931                 break;
14932
14933         case 3:
14934                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14935                 break;
14936
14937         case 4:
14938         case 5:
14939                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14940                 break;
14941
14942         case 6:
14943                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14944                 break;
14945         case 7:
14946         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14947                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14948                 break;
14949         case 9:
14950                 /* Drop through - unsupported since execlist only. */
14951         default:
14952                 /* Default just returns -ENODEV to indicate unsupported */
14953                 dev_priv->display.queue_flip = intel_default_queue_flip;
14954         }
14955
14956         mutex_init(&dev_priv->pps_mutex);
14957 }
14958
14959 /*
14960  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14961  * resume, or other times.  This quirk makes sure that's the case for
14962  * affected systems.
14963  */
14964 static void quirk_pipea_force(struct drm_device *dev)
14965 {
14966         struct drm_i915_private *dev_priv = dev->dev_private;
14967
14968         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14969         DRM_INFO("applying pipe a force quirk\n");
14970 }
14971
14972 static void quirk_pipeb_force(struct drm_device *dev)
14973 {
14974         struct drm_i915_private *dev_priv = dev->dev_private;
14975
14976         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14977         DRM_INFO("applying pipe b force quirk\n");
14978 }
14979
14980 /*
14981  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14982  */
14983 static void quirk_ssc_force_disable(struct drm_device *dev)
14984 {
14985         struct drm_i915_private *dev_priv = dev->dev_private;
14986         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14987         DRM_INFO("applying lvds SSC disable quirk\n");
14988 }
14989
14990 /*
14991  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14992  * brightness value
14993  */
14994 static void quirk_invert_brightness(struct drm_device *dev)
14995 {
14996         struct drm_i915_private *dev_priv = dev->dev_private;
14997         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14998         DRM_INFO("applying inverted panel brightness quirk\n");
14999 }
15000
15001 /* Some VBT's incorrectly indicate no backlight is present */
15002 static void quirk_backlight_present(struct drm_device *dev)
15003 {
15004         struct drm_i915_private *dev_priv = dev->dev_private;
15005         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15006         DRM_INFO("applying backlight present quirk\n");
15007 }
15008
15009 struct intel_quirk {
15010         int device;
15011         int subsystem_vendor;
15012         int subsystem_device;
15013         void (*hook)(struct drm_device *dev);
15014 };
15015
15016 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15017 struct intel_dmi_quirk {
15018         void (*hook)(struct drm_device *dev);
15019         const struct dmi_system_id (*dmi_id_list)[];
15020 };
15021
15022 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15023 {
15024         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15025         return 1;
15026 }
15027
15028 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15029         {
15030                 .dmi_id_list = &(const struct dmi_system_id[]) {
15031                         {
15032                                 .callback = intel_dmi_reverse_brightness,
15033                                 .ident = "NCR Corporation",
15034                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15035                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15036                                 },
15037                         },
15038                         { }  /* terminating entry */
15039                 },
15040                 .hook = quirk_invert_brightness,
15041         },
15042 };
15043
15044 static struct intel_quirk intel_quirks[] = {
15045         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15046         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15047
15048         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15049         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15050
15051         /* 830 needs to leave pipe A & dpll A up */
15052         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15053
15054         /* 830 needs to leave pipe B & dpll B up */
15055         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15056
15057         /* Lenovo U160 cannot use SSC on LVDS */
15058         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15059
15060         /* Sony Vaio Y cannot use SSC on LVDS */
15061         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15062
15063         /* Acer Aspire 5734Z must invert backlight brightness */
15064         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15065
15066         /* Acer/eMachines G725 */
15067         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15068
15069         /* Acer/eMachines e725 */
15070         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15071
15072         /* Acer/Packard Bell NCL20 */
15073         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15074
15075         /* Acer Aspire 4736Z */
15076         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15077
15078         /* Acer Aspire 5336 */
15079         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15080
15081         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15082         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15083
15084         /* Acer C720 Chromebook (Core i3 4005U) */
15085         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15086
15087         /* Apple Macbook 2,1 (Core 2 T7400) */
15088         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15089
15090         /* Apple Macbook 4,1 */
15091         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15092
15093         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15094         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15095
15096         /* HP Chromebook 14 (Celeron 2955U) */
15097         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15098
15099         /* Dell Chromebook 11 */
15100         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15101
15102         /* Dell Chromebook 11 (2015 version) */
15103         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15104 };
15105
15106 static void intel_init_quirks(struct drm_device *dev)
15107 {
15108         struct pci_dev *d = dev->pdev;
15109         int i;
15110
15111         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15112                 struct intel_quirk *q = &intel_quirks[i];
15113
15114                 if (d->device == q->device &&
15115                     (d->subsystem_vendor == q->subsystem_vendor ||
15116                      q->subsystem_vendor == PCI_ANY_ID) &&
15117                     (d->subsystem_device == q->subsystem_device ||
15118                      q->subsystem_device == PCI_ANY_ID))
15119                         q->hook(dev);
15120         }
15121         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15122                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15123                         intel_dmi_quirks[i].hook(dev);
15124         }
15125 }
15126
15127 /* Disable the VGA plane that we never use */
15128 static void i915_disable_vga(struct drm_device *dev)
15129 {
15130         struct drm_i915_private *dev_priv = dev->dev_private;
15131         u8 sr1;
15132         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15133
15134         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15135         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15136         outb(SR01, VGA_SR_INDEX);
15137         sr1 = inb(VGA_SR_DATA);
15138         outb(sr1 | 1<<5, VGA_SR_DATA);
15139         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15140         udelay(300);
15141
15142         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15143         POSTING_READ(vga_reg);
15144 }
15145
15146 void intel_modeset_init_hw(struct drm_device *dev)
15147 {
15148         struct drm_i915_private *dev_priv = dev->dev_private;
15149
15150         intel_update_cdclk(dev);
15151
15152         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15153
15154         intel_init_clock_gating(dev);
15155         intel_enable_gt_powersave(dev);
15156 }
15157
15158 /*
15159  * Calculate what we think the watermarks should be for the state we've read
15160  * out of the hardware and then immediately program those watermarks so that
15161  * we ensure the hardware settings match our internal state.
15162  *
15163  * We can calculate what we think WM's should be by creating a duplicate of the
15164  * current state (which was constructed during hardware readout) and running it
15165  * through the atomic check code to calculate new watermark values in the
15166  * state object.
15167  */
15168 static void sanitize_watermarks(struct drm_device *dev)
15169 {
15170         struct drm_i915_private *dev_priv = to_i915(dev);
15171         struct drm_atomic_state *state;
15172         struct drm_crtc *crtc;
15173         struct drm_crtc_state *cstate;
15174         struct drm_modeset_acquire_ctx ctx;
15175         int ret;
15176         int i;
15177
15178         /* Only supported on platforms that use atomic watermark design */
15179         if (!dev_priv->display.optimize_watermarks)
15180                 return;
15181
15182         /*
15183          * We need to hold connection_mutex before calling duplicate_state so
15184          * that the connector loop is protected.
15185          */
15186         drm_modeset_acquire_init(&ctx, 0);
15187 retry:
15188         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15189         if (ret == -EDEADLK) {
15190                 drm_modeset_backoff(&ctx);
15191                 goto retry;
15192         } else if (WARN_ON(ret)) {
15193                 goto fail;
15194         }
15195
15196         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15197         if (WARN_ON(IS_ERR(state)))
15198                 goto fail;
15199
15200         /*
15201          * Hardware readout is the only time we don't want to calculate
15202          * intermediate watermarks (since we don't trust the current
15203          * watermarks).
15204          */
15205         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15206
15207         ret = intel_atomic_check(dev, state);
15208         if (ret) {
15209                 /*
15210                  * If we fail here, it means that the hardware appears to be
15211                  * programmed in a way that shouldn't be possible, given our
15212                  * understanding of watermark requirements.  This might mean a
15213                  * mistake in the hardware readout code or a mistake in the
15214                  * watermark calculations for a given platform.  Raise a WARN
15215                  * so that this is noticeable.
15216                  *
15217                  * If this actually happens, we'll have to just leave the
15218                  * BIOS-programmed watermarks untouched and hope for the best.
15219                  */
15220                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15221                 goto fail;
15222         }
15223
15224         /* Write calculated watermark values back */
15225         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15226         for_each_crtc_in_state(state, crtc, cstate, i) {
15227                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15228
15229                 cs->wm.need_postvbl_update = true;
15230                 dev_priv->display.optimize_watermarks(cs);
15231         }
15232
15233         drm_atomic_state_free(state);
15234 fail:
15235         drm_modeset_drop_locks(&ctx);
15236         drm_modeset_acquire_fini(&ctx);
15237 }
15238
15239 void intel_modeset_init(struct drm_device *dev)
15240 {
15241         struct drm_i915_private *dev_priv = dev->dev_private;
15242         int sprite, ret;
15243         enum pipe pipe;
15244         struct intel_crtc *crtc;
15245
15246         drm_mode_config_init(dev);
15247
15248         dev->mode_config.min_width = 0;
15249         dev->mode_config.min_height = 0;
15250
15251         dev->mode_config.preferred_depth = 24;
15252         dev->mode_config.prefer_shadow = 1;
15253
15254         dev->mode_config.allow_fb_modifiers = true;
15255
15256         dev->mode_config.funcs = &intel_mode_funcs;
15257
15258         intel_init_quirks(dev);
15259
15260         intel_init_pm(dev);
15261
15262         if (INTEL_INFO(dev)->num_pipes == 0)
15263                 return;
15264
15265         /*
15266          * There may be no VBT; and if the BIOS enabled SSC we can
15267          * just keep using it to avoid unnecessary flicker.  Whereas if the
15268          * BIOS isn't using it, don't assume it will work even if the VBT
15269          * indicates as much.
15270          */
15271         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15272                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15273                                             DREF_SSC1_ENABLE);
15274
15275                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15276                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15277                                      bios_lvds_use_ssc ? "en" : "dis",
15278                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15279                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15280                 }
15281         }
15282
15283         intel_init_display(dev);
15284         intel_init_audio(dev);
15285
15286         if (IS_GEN2(dev)) {
15287                 dev->mode_config.max_width = 2048;
15288                 dev->mode_config.max_height = 2048;
15289         } else if (IS_GEN3(dev)) {
15290                 dev->mode_config.max_width = 4096;
15291                 dev->mode_config.max_height = 4096;
15292         } else {
15293                 dev->mode_config.max_width = 8192;
15294                 dev->mode_config.max_height = 8192;
15295         }
15296
15297         if (IS_845G(dev) || IS_I865G(dev)) {
15298                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15299                 dev->mode_config.cursor_height = 1023;
15300         } else if (IS_GEN2(dev)) {
15301                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15302                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15303         } else {
15304                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15305                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15306         }
15307
15308         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15309
15310         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15311                       INTEL_INFO(dev)->num_pipes,
15312                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15313
15314         for_each_pipe(dev_priv, pipe) {
15315                 intel_crtc_init(dev, pipe);
15316                 for_each_sprite(dev_priv, pipe, sprite) {
15317                         ret = intel_plane_init(dev, pipe, sprite);
15318                         if (ret)
15319                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15320                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15321                 }
15322         }
15323
15324         intel_update_czclk(dev_priv);
15325         intel_update_rawclk(dev_priv);
15326         intel_update_cdclk(dev);
15327
15328         intel_shared_dpll_init(dev);
15329
15330         /* Just disable it once at startup */
15331         i915_disable_vga(dev);
15332         intel_setup_outputs(dev);
15333
15334         drm_modeset_lock_all(dev);
15335         intel_modeset_setup_hw_state(dev);
15336         drm_modeset_unlock_all(dev);
15337
15338         for_each_intel_crtc(dev, crtc) {
15339                 struct intel_initial_plane_config plane_config = {};
15340
15341                 if (!crtc->active)
15342                         continue;
15343
15344                 /*
15345                  * Note that reserving the BIOS fb up front prevents us
15346                  * from stuffing other stolen allocations like the ring
15347                  * on top.  This prevents some ugliness at boot time, and
15348                  * can even allow for smooth boot transitions if the BIOS
15349                  * fb is large enough for the active pipe configuration.
15350                  */
15351                 dev_priv->display.get_initial_plane_config(crtc,
15352                                                            &plane_config);
15353
15354                 /*
15355                  * If the fb is shared between multiple heads, we'll
15356                  * just get the first one.
15357                  */
15358                 intel_find_initial_plane_obj(crtc, &plane_config);
15359         }
15360
15361         /*
15362          * Make sure hardware watermarks really match the state we read out.
15363          * Note that we need to do this after reconstructing the BIOS fb's
15364          * since the watermark calculation done here will use pstate->fb.
15365          */
15366         sanitize_watermarks(dev);
15367 }
15368
15369 static void intel_enable_pipe_a(struct drm_device *dev)
15370 {
15371         struct intel_connector *connector;
15372         struct drm_connector *crt = NULL;
15373         struct intel_load_detect_pipe load_detect_temp;
15374         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15375
15376         /* We can't just switch on the pipe A, we need to set things up with a
15377          * proper mode and output configuration. As a gross hack, enable pipe A
15378          * by enabling the load detect pipe once. */
15379         for_each_intel_connector(dev, connector) {
15380                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15381                         crt = &connector->base;
15382                         break;
15383                 }
15384         }
15385
15386         if (!crt)
15387                 return;
15388
15389         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15390                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15391 }
15392
15393 static bool
15394 intel_check_plane_mapping(struct intel_crtc *crtc)
15395 {
15396         struct drm_device *dev = crtc->base.dev;
15397         struct drm_i915_private *dev_priv = dev->dev_private;
15398         u32 val;
15399
15400         if (INTEL_INFO(dev)->num_pipes == 1)
15401                 return true;
15402
15403         val = I915_READ(DSPCNTR(!crtc->plane));
15404
15405         if ((val & DISPLAY_PLANE_ENABLE) &&
15406             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15407                 return false;
15408
15409         return true;
15410 }
15411
15412 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15413 {
15414         struct drm_device *dev = crtc->base.dev;
15415         struct intel_encoder *encoder;
15416
15417         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15418                 return true;
15419
15420         return false;
15421 }
15422
15423 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15424 {
15425         struct drm_device *dev = encoder->base.dev;
15426         struct intel_connector *connector;
15427
15428         for_each_connector_on_encoder(dev, &encoder->base, connector)
15429                 return true;
15430
15431         return false;
15432 }
15433
15434 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15435 {
15436         struct drm_device *dev = crtc->base.dev;
15437         struct drm_i915_private *dev_priv = dev->dev_private;
15438         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15439
15440         /* Clear any frame start delays used for debugging left by the BIOS */
15441         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15442
15443         /* restore vblank interrupts to correct state */
15444         drm_crtc_vblank_reset(&crtc->base);
15445         if (crtc->active) {
15446                 struct intel_plane *plane;
15447
15448                 drm_crtc_vblank_on(&crtc->base);
15449
15450                 /* Disable everything but the primary plane */
15451                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15452                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15453                                 continue;
15454
15455                         plane->disable_plane(&plane->base, &crtc->base);
15456                 }
15457         }
15458
15459         /* We need to sanitize the plane -> pipe mapping first because this will
15460          * disable the crtc (and hence change the state) if it is wrong. Note
15461          * that gen4+ has a fixed plane -> pipe mapping.  */
15462         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15463                 bool plane;
15464
15465                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15466                               crtc->base.base.id);
15467
15468                 /* Pipe has the wrong plane attached and the plane is active.
15469                  * Temporarily change the plane mapping and disable everything
15470                  * ...  */
15471                 plane = crtc->plane;
15472                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15473                 crtc->plane = !plane;
15474                 intel_crtc_disable_noatomic(&crtc->base);
15475                 crtc->plane = plane;
15476         }
15477
15478         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15479             crtc->pipe == PIPE_A && !crtc->active) {
15480                 /* BIOS forgot to enable pipe A, this mostly happens after
15481                  * resume. Force-enable the pipe to fix this, the update_dpms
15482                  * call below we restore the pipe to the right state, but leave
15483                  * the required bits on. */
15484                 intel_enable_pipe_a(dev);
15485         }
15486
15487         /* Adjust the state of the output pipe according to whether we
15488          * have active connectors/encoders. */
15489         if (!intel_crtc_has_encoders(crtc))
15490                 intel_crtc_disable_noatomic(&crtc->base);
15491
15492         if (crtc->active != crtc->base.state->active) {
15493                 struct intel_encoder *encoder;
15494
15495                 /* This can happen either due to bugs in the get_hw_state
15496                  * functions or because of calls to intel_crtc_disable_noatomic,
15497                  * or because the pipe is force-enabled due to the
15498                  * pipe A quirk. */
15499                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15500                               crtc->base.base.id,
15501                               crtc->base.state->enable ? "enabled" : "disabled",
15502                               crtc->active ? "enabled" : "disabled");
15503
15504                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15505                 crtc->base.state->active = crtc->active;
15506                 crtc->base.enabled = crtc->active;
15507                 crtc->base.state->connector_mask = 0;
15508                 crtc->base.state->encoder_mask = 0;
15509
15510                 /* Because we only establish the connector -> encoder ->
15511                  * crtc links if something is active, this means the
15512                  * crtc is now deactivated. Break the links. connector
15513                  * -> encoder links are only establish when things are
15514                  *  actually up, hence no need to break them. */
15515                 WARN_ON(crtc->active);
15516
15517                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15518                         encoder->base.crtc = NULL;
15519         }
15520
15521         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15522                 /*
15523                  * We start out with underrun reporting disabled to avoid races.
15524                  * For correct bookkeeping mark this on active crtcs.
15525                  *
15526                  * Also on gmch platforms we dont have any hardware bits to
15527                  * disable the underrun reporting. Which means we need to start
15528                  * out with underrun reporting disabled also on inactive pipes,
15529                  * since otherwise we'll complain about the garbage we read when
15530                  * e.g. coming up after runtime pm.
15531                  *
15532                  * No protection against concurrent access is required - at
15533                  * worst a fifo underrun happens which also sets this to false.
15534                  */
15535                 crtc->cpu_fifo_underrun_disabled = true;
15536                 crtc->pch_fifo_underrun_disabled = true;
15537         }
15538 }
15539
15540 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15541 {
15542         struct intel_connector *connector;
15543         struct drm_device *dev = encoder->base.dev;
15544
15545         /* We need to check both for a crtc link (meaning that the
15546          * encoder is active and trying to read from a pipe) and the
15547          * pipe itself being active. */
15548         bool has_active_crtc = encoder->base.crtc &&
15549                 to_intel_crtc(encoder->base.crtc)->active;
15550
15551         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15552                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15553                               encoder->base.base.id,
15554                               encoder->base.name);
15555
15556                 /* Connector is active, but has no active pipe. This is
15557                  * fallout from our resume register restoring. Disable
15558                  * the encoder manually again. */
15559                 if (encoder->base.crtc) {
15560                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15561                                       encoder->base.base.id,
15562                                       encoder->base.name);
15563                         encoder->disable(encoder);
15564                         if (encoder->post_disable)
15565                                 encoder->post_disable(encoder);
15566                 }
15567                 encoder->base.crtc = NULL;
15568
15569                 /* Inconsistent output/port/pipe state happens presumably due to
15570                  * a bug in one of the get_hw_state functions. Or someplace else
15571                  * in our code, like the register restore mess on resume. Clamp
15572                  * things to off as a safer default. */
15573                 for_each_intel_connector(dev, connector) {
15574                         if (connector->encoder != encoder)
15575                                 continue;
15576                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15577                         connector->base.encoder = NULL;
15578                 }
15579         }
15580         /* Enabled encoders without active connectors will be fixed in
15581          * the crtc fixup. */
15582 }
15583
15584 void i915_redisable_vga_power_on(struct drm_device *dev)
15585 {
15586         struct drm_i915_private *dev_priv = dev->dev_private;
15587         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15588
15589         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15590                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15591                 i915_disable_vga(dev);
15592         }
15593 }
15594
15595 void i915_redisable_vga(struct drm_device *dev)
15596 {
15597         struct drm_i915_private *dev_priv = dev->dev_private;
15598
15599         /* This function can be called both from intel_modeset_setup_hw_state or
15600          * at a very early point in our resume sequence, where the power well
15601          * structures are not yet restored. Since this function is at a very
15602          * paranoid "someone might have enabled VGA while we were not looking"
15603          * level, just check if the power well is enabled instead of trying to
15604          * follow the "don't touch the power well if we don't need it" policy
15605          * the rest of the driver uses. */
15606         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15607                 return;
15608
15609         i915_redisable_vga_power_on(dev);
15610
15611         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15612 }
15613
15614 static bool primary_get_hw_state(struct intel_plane *plane)
15615 {
15616         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15617
15618         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15619 }
15620
15621 /* FIXME read out full plane state for all planes */
15622 static void readout_plane_state(struct intel_crtc *crtc)
15623 {
15624         struct drm_plane *primary = crtc->base.primary;
15625         struct intel_plane_state *plane_state =
15626                 to_intel_plane_state(primary->state);
15627
15628         plane_state->visible = crtc->active &&
15629                 primary_get_hw_state(to_intel_plane(primary));
15630
15631         if (plane_state->visible)
15632                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15633 }
15634
15635 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15636 {
15637         struct drm_i915_private *dev_priv = dev->dev_private;
15638         enum pipe pipe;
15639         struct intel_crtc *crtc;
15640         struct intel_encoder *encoder;
15641         struct intel_connector *connector;
15642         int i;
15643
15644         dev_priv->active_crtcs = 0;
15645
15646         for_each_intel_crtc(dev, crtc) {
15647                 struct intel_crtc_state *crtc_state = crtc->config;
15648                 int pixclk = 0;
15649
15650                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15651                 memset(crtc_state, 0, sizeof(*crtc_state));
15652                 crtc_state->base.crtc = &crtc->base;
15653
15654                 crtc_state->base.active = crtc_state->base.enable =
15655                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15656
15657                 crtc->base.enabled = crtc_state->base.enable;
15658                 crtc->active = crtc_state->base.active;
15659
15660                 if (crtc_state->base.active) {
15661                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15662
15663                         if (IS_BROADWELL(dev_priv)) {
15664                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15665
15666                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15667                                 if (crtc_state->ips_enabled)
15668                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15669                         } else if (IS_VALLEYVIEW(dev_priv) ||
15670                                    IS_CHERRYVIEW(dev_priv) ||
15671                                    IS_BROXTON(dev_priv))
15672                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15673                         else
15674                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15675                 }
15676
15677                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15678
15679                 readout_plane_state(crtc);
15680
15681                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15682                               crtc->base.base.id,
15683                               crtc->active ? "enabled" : "disabled");
15684         }
15685
15686         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15687                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15688
15689                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15690                                                   &pll->config.hw_state);
15691                 pll->active = 0;
15692                 pll->config.crtc_mask = 0;
15693                 for_each_intel_crtc(dev, crtc) {
15694                         if (crtc->active && crtc->config->shared_dpll == pll) {
15695                                 pll->active++;
15696                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15697                         }
15698                 }
15699
15700                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15701                               pll->name, pll->config.crtc_mask, pll->on);
15702
15703                 if (pll->config.crtc_mask)
15704                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15705         }
15706
15707         for_each_intel_encoder(dev, encoder) {
15708                 pipe = 0;
15709
15710                 if (encoder->get_hw_state(encoder, &pipe)) {
15711                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15712                         encoder->base.crtc = &crtc->base;
15713                         encoder->get_config(encoder, crtc->config);
15714                 } else {
15715                         encoder->base.crtc = NULL;
15716                 }
15717
15718                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15719                               encoder->base.base.id,
15720                               encoder->base.name,
15721                               encoder->base.crtc ? "enabled" : "disabled",
15722                               pipe_name(pipe));
15723         }
15724
15725         for_each_intel_connector(dev, connector) {
15726                 if (connector->get_hw_state(connector)) {
15727                         connector->base.dpms = DRM_MODE_DPMS_ON;
15728
15729                         encoder = connector->encoder;
15730                         connector->base.encoder = &encoder->base;
15731
15732                         if (encoder->base.crtc &&
15733                             encoder->base.crtc->state->active) {
15734                                 /*
15735                                  * This has to be done during hardware readout
15736                                  * because anything calling .crtc_disable may
15737                                  * rely on the connector_mask being accurate.
15738                                  */
15739                                 encoder->base.crtc->state->connector_mask |=
15740                                         1 << drm_connector_index(&connector->base);
15741                                 encoder->base.crtc->state->encoder_mask |=
15742                                         1 << drm_encoder_index(&encoder->base);
15743                         }
15744
15745                 } else {
15746                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15747                         connector->base.encoder = NULL;
15748                 }
15749                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15750                               connector->base.base.id,
15751                               connector->base.name,
15752                               connector->base.encoder ? "enabled" : "disabled");
15753         }
15754
15755         for_each_intel_crtc(dev, crtc) {
15756                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15757
15758                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15759                 if (crtc->base.state->active) {
15760                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15761                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15762                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15763
15764                         /*
15765                          * The initial mode needs to be set in order to keep
15766                          * the atomic core happy. It wants a valid mode if the
15767                          * crtc's enabled, so we do the above call.
15768                          *
15769                          * At this point some state updated by the connectors
15770                          * in their ->detect() callback has not run yet, so
15771                          * no recalculation can be done yet.
15772                          *
15773                          * Even if we could do a recalculation and modeset
15774                          * right now it would cause a double modeset if
15775                          * fbdev or userspace chooses a different initial mode.
15776                          *
15777                          * If that happens, someone indicated they wanted a
15778                          * mode change, which means it's safe to do a full
15779                          * recalculation.
15780                          */
15781                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15782
15783                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15784                         update_scanline_offset(crtc);
15785                 }
15786
15787                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15788         }
15789 }
15790
15791 /* Scan out the current hw modeset state,
15792  * and sanitizes it to the current state
15793  */
15794 static void
15795 intel_modeset_setup_hw_state(struct drm_device *dev)
15796 {
15797         struct drm_i915_private *dev_priv = dev->dev_private;
15798         enum pipe pipe;
15799         struct intel_crtc *crtc;
15800         struct intel_encoder *encoder;
15801         int i;
15802
15803         intel_modeset_readout_hw_state(dev);
15804
15805         /* HW state is read out, now we need to sanitize this mess. */
15806         for_each_intel_encoder(dev, encoder) {
15807                 intel_sanitize_encoder(encoder);
15808         }
15809
15810         for_each_pipe(dev_priv, pipe) {
15811                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15812                 intel_sanitize_crtc(crtc);
15813                 intel_dump_pipe_config(crtc, crtc->config,
15814                                        "[setup_hw_state]");
15815         }
15816
15817         intel_modeset_update_connector_atomic_state(dev);
15818
15819         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15820                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15821
15822                 if (!pll->on || pll->active)
15823                         continue;
15824
15825                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15826
15827                 pll->funcs.disable(dev_priv, pll);
15828                 pll->on = false;
15829         }
15830
15831         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15832                 vlv_wm_get_hw_state(dev);
15833         else if (IS_GEN9(dev))
15834                 skl_wm_get_hw_state(dev);
15835         else if (HAS_PCH_SPLIT(dev))
15836                 ilk_wm_get_hw_state(dev);
15837
15838         for_each_intel_crtc(dev, crtc) {
15839                 unsigned long put_domains;
15840
15841                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15842                 if (WARN_ON(put_domains))
15843                         modeset_put_power_domains(dev_priv, put_domains);
15844         }
15845         intel_display_set_init_power(dev_priv, false);
15846
15847         intel_fbc_init_pipe_state(dev_priv);
15848 }
15849
15850 void intel_display_resume(struct drm_device *dev)
15851 {
15852         struct drm_i915_private *dev_priv = to_i915(dev);
15853         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15854         struct drm_modeset_acquire_ctx ctx;
15855         int ret;
15856         bool setup = false;
15857
15858         dev_priv->modeset_restore_state = NULL;
15859
15860         /*
15861          * This is a cludge because with real atomic modeset mode_config.mutex
15862          * won't be taken. Unfortunately some probed state like
15863          * audio_codec_enable is still protected by mode_config.mutex, so lock
15864          * it here for now.
15865          */
15866         mutex_lock(&dev->mode_config.mutex);
15867         drm_modeset_acquire_init(&ctx, 0);
15868
15869 retry:
15870         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15871
15872         if (ret == 0 && !setup) {
15873                 setup = true;
15874
15875                 intel_modeset_setup_hw_state(dev);
15876                 i915_redisable_vga(dev);
15877         }
15878
15879         if (ret == 0 && state) {
15880                 struct drm_crtc_state *crtc_state;
15881                 struct drm_crtc *crtc;
15882                 int i;
15883
15884                 state->acquire_ctx = &ctx;
15885
15886                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15887                         /*
15888                          * Force recalculation even if we restore
15889                          * current state. With fast modeset this may not result
15890                          * in a modeset when the state is compatible.
15891                          */
15892                         crtc_state->mode_changed = true;
15893                 }
15894
15895                 ret = drm_atomic_commit(state);
15896         }
15897
15898         if (ret == -EDEADLK) {
15899                 drm_modeset_backoff(&ctx);
15900                 goto retry;
15901         }
15902
15903         drm_modeset_drop_locks(&ctx);
15904         drm_modeset_acquire_fini(&ctx);
15905         mutex_unlock(&dev->mode_config.mutex);
15906
15907         if (ret) {
15908                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15909                 drm_atomic_state_free(state);
15910         }
15911 }
15912
15913 void intel_modeset_gem_init(struct drm_device *dev)
15914 {
15915         struct drm_crtc *c;
15916         struct drm_i915_gem_object *obj;
15917         int ret;
15918
15919         intel_init_gt_powersave(dev);
15920
15921         intel_modeset_init_hw(dev);
15922
15923         intel_setup_overlay(dev);
15924
15925         /*
15926          * Make sure any fbs we allocated at startup are properly
15927          * pinned & fenced.  When we do the allocation it's too early
15928          * for this.
15929          */
15930         for_each_crtc(dev, c) {
15931                 obj = intel_fb_obj(c->primary->fb);
15932                 if (obj == NULL)
15933                         continue;
15934
15935                 mutex_lock(&dev->struct_mutex);
15936                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15937                                                  c->primary->state->rotation);
15938                 mutex_unlock(&dev->struct_mutex);
15939                 if (ret) {
15940                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15941                                   to_intel_crtc(c)->pipe);
15942                         drm_framebuffer_unreference(c->primary->fb);
15943                         c->primary->fb = NULL;
15944                         c->primary->crtc = c->primary->state->crtc = NULL;
15945                         update_state_fb(c->primary);
15946                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15947                 }
15948         }
15949
15950         intel_backlight_register(dev);
15951 }
15952
15953 void intel_connector_unregister(struct intel_connector *intel_connector)
15954 {
15955         struct drm_connector *connector = &intel_connector->base;
15956
15957         intel_panel_destroy_backlight(connector);
15958         drm_connector_unregister(connector);
15959 }
15960
15961 void intel_modeset_cleanup(struct drm_device *dev)
15962 {
15963         struct drm_i915_private *dev_priv = dev->dev_private;
15964         struct intel_connector *connector;
15965
15966         intel_disable_gt_powersave(dev);
15967
15968         intel_backlight_unregister(dev);
15969
15970         /*
15971          * Interrupts and polling as the first thing to avoid creating havoc.
15972          * Too much stuff here (turning of connectors, ...) would
15973          * experience fancy races otherwise.
15974          */
15975         intel_irq_uninstall(dev_priv);
15976
15977         /*
15978          * Due to the hpd irq storm handling the hotplug work can re-arm the
15979          * poll handlers. Hence disable polling after hpd handling is shut down.
15980          */
15981         drm_kms_helper_poll_fini(dev);
15982
15983         intel_unregister_dsm_handler();
15984
15985         intel_fbc_global_disable(dev_priv);
15986
15987         /* flush any delayed tasks or pending work */
15988         flush_scheduled_work();
15989
15990         /* destroy the backlight and sysfs files before encoders/connectors */
15991         for_each_intel_connector(dev, connector)
15992                 connector->unregister(connector);
15993
15994         drm_mode_config_cleanup(dev);
15995
15996         intel_cleanup_overlay(dev);
15997
15998         intel_cleanup_gt_powersave(dev);
15999
16000         intel_teardown_gmbus(dev);
16001 }
16002
16003 /*
16004  * Return which encoder is currently attached for connector.
16005  */
16006 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16007 {
16008         return &intel_attached_encoder(connector)->base;
16009 }
16010
16011 void intel_connector_attach_encoder(struct intel_connector *connector,
16012                                     struct intel_encoder *encoder)
16013 {
16014         connector->encoder = encoder;
16015         drm_mode_connector_attach_encoder(&connector->base,
16016                                           &encoder->base);
16017 }
16018
16019 /*
16020  * set vga decode state - true == enable VGA decode
16021  */
16022 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16023 {
16024         struct drm_i915_private *dev_priv = dev->dev_private;
16025         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16026         u16 gmch_ctrl;
16027
16028         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16029                 DRM_ERROR("failed to read control word\n");
16030                 return -EIO;
16031         }
16032
16033         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16034                 return 0;
16035
16036         if (state)
16037                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16038         else
16039                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16040
16041         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16042                 DRM_ERROR("failed to write control word\n");
16043                 return -EIO;
16044         }
16045
16046         return 0;
16047 }
16048
16049 struct intel_display_error_state {
16050
16051         u32 power_well_driver;
16052
16053         int num_transcoders;
16054
16055         struct intel_cursor_error_state {
16056                 u32 control;
16057                 u32 position;
16058                 u32 base;
16059                 u32 size;
16060         } cursor[I915_MAX_PIPES];
16061
16062         struct intel_pipe_error_state {
16063                 bool power_domain_on;
16064                 u32 source;
16065                 u32 stat;
16066         } pipe[I915_MAX_PIPES];
16067
16068         struct intel_plane_error_state {
16069                 u32 control;
16070                 u32 stride;
16071                 u32 size;
16072                 u32 pos;
16073                 u32 addr;
16074                 u32 surface;
16075                 u32 tile_offset;
16076         } plane[I915_MAX_PIPES];
16077
16078         struct intel_transcoder_error_state {
16079                 bool power_domain_on;
16080                 enum transcoder cpu_transcoder;
16081
16082                 u32 conf;
16083
16084                 u32 htotal;
16085                 u32 hblank;
16086                 u32 hsync;
16087                 u32 vtotal;
16088                 u32 vblank;
16089                 u32 vsync;
16090         } transcoder[4];
16091 };
16092
16093 struct intel_display_error_state *
16094 intel_display_capture_error_state(struct drm_device *dev)
16095 {
16096         struct drm_i915_private *dev_priv = dev->dev_private;
16097         struct intel_display_error_state *error;
16098         int transcoders[] = {
16099                 TRANSCODER_A,
16100                 TRANSCODER_B,
16101                 TRANSCODER_C,
16102                 TRANSCODER_EDP,
16103         };
16104         int i;
16105
16106         if (INTEL_INFO(dev)->num_pipes == 0)
16107                 return NULL;
16108
16109         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16110         if (error == NULL)
16111                 return NULL;
16112
16113         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16114                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16115
16116         for_each_pipe(dev_priv, i) {
16117                 error->pipe[i].power_domain_on =
16118                         __intel_display_power_is_enabled(dev_priv,
16119                                                          POWER_DOMAIN_PIPE(i));
16120                 if (!error->pipe[i].power_domain_on)
16121                         continue;
16122
16123                 error->cursor[i].control = I915_READ(CURCNTR(i));
16124                 error->cursor[i].position = I915_READ(CURPOS(i));
16125                 error->cursor[i].base = I915_READ(CURBASE(i));
16126
16127                 error->plane[i].control = I915_READ(DSPCNTR(i));
16128                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16129                 if (INTEL_INFO(dev)->gen <= 3) {
16130                         error->plane[i].size = I915_READ(DSPSIZE(i));
16131                         error->plane[i].pos = I915_READ(DSPPOS(i));
16132                 }
16133                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16134                         error->plane[i].addr = I915_READ(DSPADDR(i));
16135                 if (INTEL_INFO(dev)->gen >= 4) {
16136                         error->plane[i].surface = I915_READ(DSPSURF(i));
16137                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16138                 }
16139
16140                 error->pipe[i].source = I915_READ(PIPESRC(i));
16141
16142                 if (HAS_GMCH_DISPLAY(dev))
16143                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16144         }
16145
16146         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16147         if (HAS_DDI(dev_priv->dev))
16148                 error->num_transcoders++; /* Account for eDP. */
16149
16150         for (i = 0; i < error->num_transcoders; i++) {
16151                 enum transcoder cpu_transcoder = transcoders[i];
16152
16153                 error->transcoder[i].power_domain_on =
16154                         __intel_display_power_is_enabled(dev_priv,
16155                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16156                 if (!error->transcoder[i].power_domain_on)
16157                         continue;
16158
16159                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16160
16161                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16162                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16163                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16164                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16165                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16166                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16167                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16168         }
16169
16170         return error;
16171 }
16172
16173 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16174
16175 void
16176 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16177                                 struct drm_device *dev,
16178                                 struct intel_display_error_state *error)
16179 {
16180         struct drm_i915_private *dev_priv = dev->dev_private;
16181         int i;
16182
16183         if (!error)
16184                 return;
16185
16186         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16187         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16188                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16189                            error->power_well_driver);
16190         for_each_pipe(dev_priv, i) {
16191                 err_printf(m, "Pipe [%d]:\n", i);
16192                 err_printf(m, "  Power: %s\n",
16193                            onoff(error->pipe[i].power_domain_on));
16194                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16195                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16196
16197                 err_printf(m, "Plane [%d]:\n", i);
16198                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16199                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16200                 if (INTEL_INFO(dev)->gen <= 3) {
16201                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16202                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16203                 }
16204                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16205                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16206                 if (INTEL_INFO(dev)->gen >= 4) {
16207                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16208                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16209                 }
16210
16211                 err_printf(m, "Cursor [%d]:\n", i);
16212                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16213                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16214                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16215         }
16216
16217         for (i = 0; i < error->num_transcoders; i++) {
16218                 err_printf(m, "CPU transcoder: %c\n",
16219                            transcoder_name(error->transcoder[i].cpu_transcoder));
16220                 err_printf(m, "  Power: %s\n",
16221                            onoff(error->transcoder[i].power_domain_on));
16222                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16223                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16224                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16225                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16226                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16227                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16228                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16229         }
16230 }