drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 100 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 101                                          struct intel_link_m_n *m_n,
 102                                          struct intel_link_m_n *m2_n2);
 103 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 104 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 106 static void vlv_prepare_pll(struct intel_crtc *crtc,
 107                             const struct intel_crtc_state *pipe_config);
 108 static void chv_prepare_pll(struct intel_crtc *crtc,
 109                             const struct intel_crtc_state *pipe_config);
 110 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 113         struct intel_crtc_state *crtc_state);
 114 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 115                            int num_connectors);
 116 static void skylake_pfit_enable(struct intel_crtc *crtc);
 117 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 118 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 119 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 120 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 121
 122 typedef struct {
 123         int     min, max;
 124 } intel_range_t;
 125
 126 typedef struct {
 127         int     dot_limit;
 128         int     p2_slow, p2_fast;
 129 } intel_p2_t;
 130
 131 typedef struct intel_limit intel_limit_t;
 132 struct intel_limit {
 133         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 134         intel_p2_t          p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 152                                   const char *name, u32 reg)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         if (dev_priv->hpll_freq == 0)
 158                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 171 }
 172
 173 static int
 174 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 175 {
 176         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 177 }
 178
 179 static int
 180 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 181 {
 182         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 183                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 184 }
 185
 186 static int
 187 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 188 {
 189         uint32_t clkcfg;
 190
 191         /* hrawclock is 1/4 the FSB frequency */
 192         clkcfg = I915_READ(CLKCFG);
 193         switch (clkcfg & CLKCFG_FSB_MASK) {
 194         case CLKCFG_FSB_400:
 195                 return 100000;
 196         case CLKCFG_FSB_533:
 197                 return 133333;
 198         case CLKCFG_FSB_667:
 199                 return 166667;
 200         case CLKCFG_FSB_800:
 201                 return 200000;
 202         case CLKCFG_FSB_1067:
 203                 return 266667;
 204         case CLKCFG_FSB_1333:
 205                 return 333333;
 206         /* these two are just a guess; one of them might be right */
 207         case CLKCFG_FSB_1600:
 208         case CLKCFG_FSB_1600_ALT:
 209                 return 400000;
 210         default:
 211                 return 133333;
 212         }
 213 }
 214
 215 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 216 {
 217         if (HAS_PCH_SPLIT(dev_priv))
 218                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 219         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 220                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 221         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 222                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 223         else
 224                 return; /* no rawclk on other platforms, or no need to know it */
 225
 226         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 227 }
 228
 229 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 230 {
 231         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 232                 return;
 233
 234         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 235                                                       CCK_CZ_CLOCK_CONTROL);
 236
 237         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 238 }
 239
 240 static inline u32 /* units of 100MHz */
 241 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 242                     const struct intel_crtc_state *pipe_config)
 243 {
 244         if (HAS_DDI(dev_priv))
 245                 return pipe_config->port_clock; /* SPLL */
 246         else if (IS_GEN5(dev_priv))
 247                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 248         else
 249                 return 270000;
 250 }
 251
 252 static const intel_limit_t intel_limits_i8xx_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 2, .max = 33 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 4, .p2_fast = 2 },
 263 };
 264
 265 static const intel_limit_t intel_limits_i8xx_dvo = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 908000, .max = 1512000 },
 268         .n = { .min = 2, .max = 16 },
 269         .m = { .min = 96, .max = 140 },
 270         .m1 = { .min = 18, .max = 26 },
 271         .m2 = { .min = 6, .max = 16 },
 272         .p = { .min = 4, .max = 128 },
 273         .p1 = { .min = 2, .max = 33 },
 274         .p2 = { .dot_limit = 165000,
 275                 .p2_slow = 4, .p2_fast = 4 },
 276 };
 277
 278 static const intel_limit_t intel_limits_i8xx_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 908000, .max = 1512000 },
 281         .n = { .min = 2, .max = 16 },
 282         .m = { .min = 96, .max = 140 },
 283         .m1 = { .min = 18, .max = 26 },
 284         .m2 = { .min = 6, .max = 16 },
 285         .p = { .min = 4, .max = 128 },
 286         .p1 = { .min = 1, .max = 6 },
 287         .p2 = { .dot_limit = 165000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291 static const intel_limit_t intel_limits_i9xx_sdvo = {
 292         .dot = { .min = 20000, .max = 400000 },
 293         .vco = { .min = 1400000, .max = 2800000 },
 294         .n = { .min = 1, .max = 6 },
 295         .m = { .min = 70, .max = 120 },
 296         .m1 = { .min = 8, .max = 18 },
 297         .m2 = { .min = 3, .max = 7 },
 298         .p = { .min = 5, .max = 80 },
 299         .p1 = { .min = 1, .max = 8 },
 300         .p2 = { .dot_limit = 200000,
 301                 .p2_slow = 10, .p2_fast = 5 },
 302 };
 303
 304 static const intel_limit_t intel_limits_i9xx_lvds = {
 305         .dot = { .min = 20000, .max = 400000 },
 306         .vco = { .min = 1400000, .max = 2800000 },
 307         .n = { .min = 1, .max = 6 },
 308         .m = { .min = 70, .max = 120 },
 309         .m1 = { .min = 8, .max = 18 },
 310         .m2 = { .min = 3, .max = 7 },
 311         .p = { .min = 7, .max = 98 },
 312         .p1 = { .min = 1, .max = 8 },
 313         .p2 = { .dot_limit = 112000,
 314                 .p2_slow = 14, .p2_fast = 7 },
 315 };
 316
 317
 318 static const intel_limit_t intel_limits_g4x_sdvo = {
 319         .dot = { .min = 25000, .max = 270000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 17, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 10, .max = 30 },
 326         .p1 = { .min = 1, .max = 3},
 327         .p2 = { .dot_limit = 270000,
 328                 .p2_slow = 10,
 329                 .p2_fast = 10
 330         },
 331 };
 332
 333 static const intel_limit_t intel_limits_g4x_hdmi = {
 334         .dot = { .min = 22000, .max = 400000 },
 335         .vco = { .min = 1750000, .max = 3500000},
 336         .n = { .min = 1, .max = 4 },
 337         .m = { .min = 104, .max = 138 },
 338         .m1 = { .min = 16, .max = 23 },
 339         .m2 = { .min = 5, .max = 11 },
 340         .p = { .min = 5, .max = 80 },
 341         .p1 = { .min = 1, .max = 8},
 342         .p2 = { .dot_limit = 165000,
 343                 .p2_slow = 10, .p2_fast = 5 },
 344 };
 345
 346 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 347         .dot = { .min = 20000, .max = 115000 },
 348         .vco = { .min = 1750000, .max = 3500000 },
 349         .n = { .min = 1, .max = 3 },
 350         .m = { .min = 104, .max = 138 },
 351         .m1 = { .min = 17, .max = 23 },
 352         .m2 = { .min = 5, .max = 11 },
 353         .p = { .min = 28, .max = 112 },
 354         .p1 = { .min = 2, .max = 8 },
 355         .p2 = { .dot_limit = 0,
 356                 .p2_slow = 14, .p2_fast = 14
 357         },
 358 };
 359
 360 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 361         .dot = { .min = 80000, .max = 224000 },
 362         .vco = { .min = 1750000, .max = 3500000 },
 363         .n = { .min = 1, .max = 3 },
 364         .m = { .min = 104, .max = 138 },
 365         .m1 = { .min = 17, .max = 23 },
 366         .m2 = { .min = 5, .max = 11 },
 367         .p = { .min = 14, .max = 42 },
 368         .p1 = { .min = 2, .max = 6 },
 369         .p2 = { .dot_limit = 0,
 370                 .p2_slow = 7, .p2_fast = 7
 371         },
 372 };
 373
 374 static const intel_limit_t intel_limits_pineview_sdvo = {
 375         .dot = { .min = 20000, .max = 400000},
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         /* Pineview's Ncounter is a ring counter */
 378         .n = { .min = 3, .max = 6 },
 379         .m = { .min = 2, .max = 256 },
 380         /* Pineview only has one combined m divider, which we treat as m2. */
 381         .m1 = { .min = 0, .max = 0 },
 382         .m2 = { .min = 0, .max = 254 },
 383         .p = { .min = 5, .max = 80 },
 384         .p1 = { .min = 1, .max = 8 },
 385         .p2 = { .dot_limit = 200000,
 386                 .p2_slow = 10, .p2_fast = 5 },
 387 };
 388
 389 static const intel_limit_t intel_limits_pineview_lvds = {
 390         .dot = { .min = 20000, .max = 400000 },
 391         .vco = { .min = 1700000, .max = 3500000 },
 392         .n = { .min = 3, .max = 6 },
 393         .m = { .min = 2, .max = 256 },
 394         .m1 = { .min = 0, .max = 0 },
 395         .m2 = { .min = 0, .max = 254 },
 396         .p = { .min = 7, .max = 112 },
 397         .p1 = { .min = 1, .max = 8 },
 398         .p2 = { .dot_limit = 112000,
 399                 .p2_slow = 14, .p2_fast = 14 },
 400 };
 401
 402 /* Ironlake / Sandybridge
 403  *
 404  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 405  * the range value for them is (actual_value - 2).
 406  */
 407 static const intel_limit_t intel_limits_ironlake_dac = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 5 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 5, .max = 80 },
 415         .p1 = { .min = 1, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 10, .p2_fast = 5 },
 418 };
 419
 420 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 421         .dot = { .min = 25000, .max = 350000 },
 422         .vco = { .min = 1760000, .max = 3510000 },
 423         .n = { .min = 1, .max = 3 },
 424         .m = { .min = 79, .max = 118 },
 425         .m1 = { .min = 12, .max = 22 },
 426         .m2 = { .min = 5, .max = 9 },
 427         .p = { .min = 28, .max = 112 },
 428         .p1 = { .min = 2, .max = 8 },
 429         .p2 = { .dot_limit = 225000,
 430                 .p2_slow = 14, .p2_fast = 14 },
 431 };
 432
 433 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 434         .dot = { .min = 25000, .max = 350000 },
 435         .vco = { .min = 1760000, .max = 3510000 },
 436         .n = { .min = 1, .max = 3 },
 437         .m = { .min = 79, .max = 127 },
 438         .m1 = { .min = 12, .max = 22 },
 439         .m2 = { .min = 5, .max = 9 },
 440         .p = { .min = 14, .max = 56 },
 441         .p1 = { .min = 2, .max = 8 },
 442         .p2 = { .dot_limit = 225000,
 443                 .p2_slow = 7, .p2_fast = 7 },
 444 };
 445
 446 /* LVDS 100mhz refclk limits. */
 447 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 448         .dot = { .min = 25000, .max = 350000 },
 449         .vco = { .min = 1760000, .max = 3510000 },
 450         .n = { .min = 1, .max = 2 },
 451         .m = { .min = 79, .max = 126 },
 452         .m1 = { .min = 12, .max = 22 },
 453         .m2 = { .min = 5, .max = 9 },
 454         .p = { .min = 28, .max = 112 },
 455         .p1 = { .min = 2, .max = 8 },
 456         .p2 = { .dot_limit = 225000,
 457                 .p2_slow = 14, .p2_fast = 14 },
 458 };
 459
 460 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 461         .dot = { .min = 25000, .max = 350000 },
 462         .vco = { .min = 1760000, .max = 3510000 },
 463         .n = { .min = 1, .max = 3 },
 464         .m = { .min = 79, .max = 126 },
 465         .m1 = { .min = 12, .max = 22 },
 466         .m2 = { .min = 5, .max = 9 },
 467         .p = { .min = 14, .max = 42 },
 468         .p1 = { .min = 2, .max = 6 },
 469         .p2 = { .dot_limit = 225000,
 470                 .p2_slow = 7, .p2_fast = 7 },
 471 };
 472
 473 static const intel_limit_t intel_limits_vlv = {
 474          /*
 475           * These are the data rate limits (measured in fast clocks)
 476           * since those are the strictest limits we have. The fast
 477           * clock and actual rate limits are more relaxed, so checking
 478           * them would make no difference.
 479           */
 480         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 481         .vco = { .min = 4000000, .max = 6000000 },
 482         .n = { .min = 1, .max = 7 },
 483         .m1 = { .min = 2, .max = 3 },
 484         .m2 = { .min = 11, .max = 156 },
 485         .p1 = { .min = 2, .max = 3 },
 486         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 487 };
 488
 489 static const intel_limit_t intel_limits_chv = {
 490         /*
 491          * These are the data rate limits (measured in fast clocks)
 492          * since those are the strictest limits we have.  The fast
 493          * clock and actual rate limits are more relaxed, so checking
 494          * them would make no difference.
 495          */
 496         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 497         .vco = { .min = 4800000, .max = 6480000 },
 498         .n = { .min = 1, .max = 1 },
 499         .m1 = { .min = 2, .max = 2 },
 500         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 501         .p1 = { .min = 2, .max = 4 },
 502         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 503 };
 504
 505 static const intel_limit_t intel_limits_bxt = {
 506         /* FIXME: find real dot limits */
 507         .dot = { .min = 0, .max = INT_MAX },
 508         .vco = { .min = 4800000, .max = 6700000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         /* FIXME: find real m2 limits */
 512         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 513         .p1 = { .min = 2, .max = 4 },
 514         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 515 };
 516
 517 static bool
 518 needs_modeset(struct drm_crtc_state *state)
 519 {
 520         return drm_atomic_crtc_needs_modeset(state);
 521 }
 522
 523 /**
 524  * Returns whether any output on the specified pipe is of the specified type
 525  */
 526 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 527 {
 528         struct drm_device *dev = crtc->base.dev;
 529         struct intel_encoder *encoder;
 530
 531         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 532                 if (encoder->type == type)
 533                         return true;
 534
 535         return false;
 536 }
 537
 538 /**
 539  * Returns whether any output on the specified pipe will have the specified
 540  * type after a staged modeset is complete, i.e., the same as
 541  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 542  * encoder->crtc.
 543  */
 544 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 545                                       int type)
 546 {
 547         struct drm_atomic_state *state = crtc_state->base.state;
 548         struct drm_connector *connector;
 549         struct drm_connector_state *connector_state;
 550         struct intel_encoder *encoder;
 551         int i, num_connectors = 0;
 552
 553         for_each_connector_in_state(state, connector, connector_state, i) {
 554                 if (connector_state->crtc != crtc_state->base.crtc)
 555                         continue;
 556
 557                 num_connectors++;
 558
 559                 encoder = to_intel_encoder(connector_state->best_encoder);
 560                 if (encoder->type == type)
 561                         return true;
 562         }
 563
 564         WARN_ON(num_connectors == 0);
 565
 566         return false;
 567 }
 568
 569 static const intel_limit_t *
 570 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 571 {
 572         struct drm_device *dev = crtc_state->base.crtc->dev;
 573         const intel_limit_t *limit;
 574
 575         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 576                 if (intel_is_dual_link_lvds(dev)) {
 577                         if (refclk == 100000)
 578                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 579                         else
 580                                 limit = &intel_limits_ironlake_dual_lvds;
 581                 } else {
 582                         if (refclk == 100000)
 583                                 limit = &intel_limits_ironlake_single_lvds_100m;
 584                         else
 585                                 limit = &intel_limits_ironlake_single_lvds;
 586                 }
 587         } else
 588                 limit = &intel_limits_ironlake_dac;
 589
 590         return limit;
 591 }
 592
 593 static const intel_limit_t *
 594 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 595 {
 596         struct drm_device *dev = crtc_state->base.crtc->dev;
 597         const intel_limit_t *limit;
 598
 599         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 600                 if (intel_is_dual_link_lvds(dev))
 601                         limit = &intel_limits_g4x_dual_channel_lvds;
 602                 else
 603                         limit = &intel_limits_g4x_single_channel_lvds;
 604         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 605                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 606                 limit = &intel_limits_g4x_hdmi;
 607         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 608                 limit = &intel_limits_g4x_sdvo;
 609         } else /* The option is for other outputs */
 610                 limit = &intel_limits_i9xx_sdvo;
 611
 612         return limit;
 613 }
 614
 615 static const intel_limit_t *
 616 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 617 {
 618         struct drm_device *dev = crtc_state->base.crtc->dev;
 619         const intel_limit_t *limit;
 620
 621         if (IS_BROXTON(dev))
 622                 limit = &intel_limits_bxt;
 623         else if (HAS_PCH_SPLIT(dev))
 624                 limit = intel_ironlake_limit(crtc_state, refclk);
 625         else if (IS_G4X(dev)) {
 626                 limit = intel_g4x_limit(crtc_state);
 627         } else if (IS_PINEVIEW(dev)) {
 628                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 629                         limit = &intel_limits_pineview_lvds;
 630                 else
 631                         limit = &intel_limits_pineview_sdvo;
 632         } else if (IS_CHERRYVIEW(dev)) {
 633                 limit = &intel_limits_chv;
 634         } else if (IS_VALLEYVIEW(dev)) {
 635                 limit = &intel_limits_vlv;
 636         } else if (!IS_GEN2(dev)) {
 637                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 638                         limit = &intel_limits_i9xx_lvds;
 639                 else
 640                         limit = &intel_limits_i9xx_sdvo;
 641         } else {
 642                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 643                         limit = &intel_limits_i8xx_lvds;
 644                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 645                         limit = &intel_limits_i8xx_dvo;
 646                 else
 647                         limit = &intel_limits_i8xx_dac;
 648         }
 649         return limit;
 650 }
 651
 652 /*
 653  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 654  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 655  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 656  * The helpers' return value is the rate of the clock that is fed to the
 657  * display engine's pipe which can be the above fast dot clock rate or a
 658  * divided-down version of it.
 659  */
 660 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 661 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = clock->m2 + 2;
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 674 {
 675         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 676 }
 677
 678 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 679 {
 680         clock->m = i9xx_dpll_compute_m(clock);
 681         clock->p = clock->p1 * clock->p2;
 682         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 683                 return 0;
 684         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 685         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 686
 687         return clock->dot;
 688 }
 689
 690 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 691 {
 692         clock->m = clock->m1 * clock->m2;
 693         clock->p = clock->p1 * clock->p2;
 694         if (WARN_ON(clock->n == 0 || clock->p == 0))
 695                 return 0;
 696         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 697         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 698
 699         return clock->dot / 5;
 700 }
 701
 702 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 703 {
 704         clock->m = clock->m1 * clock->m2;
 705         clock->p = clock->p1 * clock->p2;
 706         if (WARN_ON(clock->n == 0 || clock->p == 0))
 707                 return 0;
 708         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 709                         clock->n << 22);
 710         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 711
 712         return clock->dot / 5;
 713 }
 714
 715 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 716 /**
 717  * Returns whether the given set of divisors are valid for a given refclk with
 718  * the given connectors.
 719  */
 720
 721 static bool intel_PLL_is_valid(struct drm_device *dev,
 722                                const intel_limit_t *limit,
 723                                const intel_clock_t *clock)
 724 {
 725         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 726                 INTELPllInvalid("n out of range\n");
 727         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 728                 INTELPllInvalid("p1 out of range\n");
 729         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 730                 INTELPllInvalid("m2 out of range\n");
 731         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 732                 INTELPllInvalid("m1 out of range\n");
 733
 734         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 735             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 736                 if (clock->m1 <= clock->m2)
 737                         INTELPllInvalid("m1 <= m2\n");
 738
 739         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 740                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 741                         INTELPllInvalid("p out of range\n");
 742                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 743                         INTELPllInvalid("m out of range\n");
 744         }
 745
 746         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 747                 INTELPllInvalid("vco out of range\n");
 748         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 749          * connector, etc., rather than just a single range.
 750          */
 751         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 752                 INTELPllInvalid("dot out of range\n");
 753
 754         return true;
 755 }
 756
 757 static int
 758 i9xx_select_p2_div(const intel_limit_t *limit,
 759                    const struct intel_crtc_state *crtc_state,
 760                    int target)
 761 {
 762         struct drm_device *dev = crtc_state->base.crtc->dev;
 763
 764         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 765                 /*
 766                  * For LVDS just rely on its current settings for dual-channel.
 767                  * We haven't figured out how to reliably set up different
 768                  * single/dual channel state, if we even can.
 769                  */
 770                 if (intel_is_dual_link_lvds(dev))
 771                         return limit->p2.p2_fast;
 772                 else
 773                         return limit->p2.p2_slow;
 774         } else {
 775                 if (target < limit->p2.dot_limit)
 776                         return limit->p2.p2_slow;
 777                 else
 778                         return limit->p2.p2_fast;
 779         }
 780 }
 781
 782 static bool
 783 i9xx_find_best_dpll(const intel_limit_t *limit,
 784                     struct intel_crtc_state *crtc_state,
 785                     int target, int refclk, intel_clock_t *match_clock,
 786                     intel_clock_t *best_clock)
 787 {
 788         struct drm_device *dev = crtc_state->base.crtc->dev;
 789         intel_clock_t clock;
 790         int err = target;
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 795
 796         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 797              clock.m1++) {
 798                 for (clock.m2 = limit->m2.min;
 799                      clock.m2 <= limit->m2.max; clock.m2++) {
 800                         if (clock.m2 >= clock.m1)
 801                                 break;
 802                         for (clock.n = limit->n.min;
 803                              clock.n <= limit->n.max; clock.n++) {
 804                                 for (clock.p1 = limit->p1.min;
 805                                         clock.p1 <= limit->p1.max; clock.p1++) {
 806                                         int this_err;
 807
 808                                         i9xx_calc_dpll_params(refclk, &clock);
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812                                         if (match_clock &&
 813                                             clock.p != match_clock->p)
 814                                                 continue;
 815
 816                                         this_err = abs(clock.dot - target);
 817                                         if (this_err < err) {
 818                                                 *best_clock = clock;
 819                                                 err = this_err;
 820                                         }
 821                                 }
 822                         }
 823                 }
 824         }
 825
 826         return (err != target);
 827 }
 828
 829 static bool
 830 pnv_find_best_dpll(const intel_limit_t *limit,
 831                    struct intel_crtc_state *crtc_state,
 832                    int target, int refclk, intel_clock_t *match_clock,
 833                    intel_clock_t *best_clock)
 834 {
 835         struct drm_device *dev = crtc_state->base.crtc->dev;
 836         intel_clock_t clock;
 837         int err = target;
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 842
 843         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 844              clock.m1++) {
 845                 for (clock.m2 = limit->m2.min;
 846                      clock.m2 <= limit->m2.max; clock.m2++) {
 847                         for (clock.n = limit->n.min;
 848                              clock.n <= limit->n.max; clock.n++) {
 849                                 for (clock.p1 = limit->p1.min;
 850                                         clock.p1 <= limit->p1.max; clock.p1++) {
 851                                         int this_err;
 852
 853                                         pnv_calc_dpll_params(refclk, &clock);
 854                                         if (!intel_PLL_is_valid(dev, limit,
 855                                                                 &clock))
 856                                                 continue;
 857                                         if (match_clock &&
 858                                             clock.p != match_clock->p)
 859                                                 continue;
 860
 861                                         this_err = abs(clock.dot - target);
 862                                         if (this_err < err) {
 863                                                 *best_clock = clock;
 864                                                 err = this_err;
 865                                         }
 866                                 }
 867                         }
 868                 }
 869         }
 870
 871         return (err != target);
 872 }
 873
 874 static bool
 875 g4x_find_best_dpll(const intel_limit_t *limit,
 876                    struct intel_crtc_state *crtc_state,
 877                    int target, int refclk, intel_clock_t *match_clock,
 878                    intel_clock_t *best_clock)
 879 {
 880         struct drm_device *dev = crtc_state->base.crtc->dev;
 881         intel_clock_t clock;
 882         int max_n;
 883         bool found = false;
 884         /* approximately equals target * 0.00585 */
 885         int err_most = (target >> 8) + (target >> 9);
 886
 887         memset(best_clock, 0, sizeof(*best_clock));
 888
 889         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 890
 891         max_n = limit->n.max;
 892         /* based on hardware requirement, prefer smaller n to precision */
 893         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 894                 /* based on hardware requirement, prefere larger m1,m2 */
 895                 for (clock.m1 = limit->m1.max;
 896                      clock.m1 >= limit->m1.min; clock.m1--) {
 897                         for (clock.m2 = limit->m2.max;
 898                              clock.m2 >= limit->m2.min; clock.m2--) {
 899                                 for (clock.p1 = limit->p1.max;
 900                                      clock.p1 >= limit->p1.min; clock.p1--) {
 901                                         int this_err;
 902
 903                                         i9xx_calc_dpll_params(refclk, &clock);
 904                                         if (!intel_PLL_is_valid(dev, limit,
 905                                                                 &clock))
 906                                                 continue;
 907
 908                                         this_err = abs(clock.dot - target);
 909                                         if (this_err < err_most) {
 910                                                 *best_clock = clock;
 911                                                 err_most = this_err;
 912                                                 max_n = clock.n;
 913                                                 found = true;
 914                                         }
 915                                 }
 916                         }
 917                 }
 918         }
 919         return found;
 920 }
 921
 922 /*
 923  * Check if the calculated PLL configuration is more optimal compared to the
 924  * best configuration and error found so far. Return the calculated error.
 925  */
 926 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 927                                const intel_clock_t *calculated_clock,
 928                                const intel_clock_t *best_clock,
 929                                unsigned int best_error_ppm,
 930                                unsigned int *error_ppm)
 931 {
 932         /*
 933          * For CHV ignore the error and consider only the P value.
 934          * Prefer a bigger P value based on HW requirements.
 935          */
 936         if (IS_CHERRYVIEW(dev)) {
 937                 *error_ppm = 0;
 938
 939                 return calculated_clock->p > best_clock->p;
 940         }
 941
 942         if (WARN_ON_ONCE(!target_freq))
 943                 return false;
 944
 945         *error_ppm = div_u64(1000000ULL *
 946                                 abs(target_freq - calculated_clock->dot),
 947                              target_freq);
 948         /*
 949          * Prefer a better P value over a better (smaller) error if the error
 950          * is small. Ensure this preference for future configurations too by
 951          * setting the error to 0.
 952          */
 953         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 954                 *error_ppm = 0;
 955
 956                 return true;
 957         }
 958
 959         return *error_ppm + 10 < best_error_ppm;
 960 }
 961
 962 static bool
 963 vlv_find_best_dpll(const intel_limit_t *limit,
 964                    struct intel_crtc_state *crtc_state,
 965                    int target, int refclk, intel_clock_t *match_clock,
 966                    intel_clock_t *best_clock)
 967 {
 968         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 969         struct drm_device *dev = crtc->base.dev;
 970         intel_clock_t clock;
 971         unsigned int bestppm = 1000000;
 972         /* min update 19.2 MHz */
 973         int max_n = min(limit->n.max, refclk / 19200);
 974         bool found = false;
 975
 976         target *= 5; /* fast clock */
 977
 978         memset(best_clock, 0, sizeof(*best_clock));
 979
 980         /* based on hardware requirement, prefer smaller n to precision */
 981         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 982                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 983                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 984                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 985                                 clock.p = clock.p1 * clock.p2;
 986                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 987                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 988                                         unsigned int ppm;
 989
 990                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 991                                                                      refclk * clock.m1);
 992
 993                                         vlv_calc_dpll_params(refclk, &clock);
 994
 995                                         if (!intel_PLL_is_valid(dev, limit,
 996                                                                 &clock))
 997                                                 continue;
 998
 999                                         if (!vlv_PLL_is_optimal(dev, target,
1000                                                                 &clock,
1001                                                                 best_clock,
1002                                                                 bestppm, &ppm))
1003                                                 continue;
1004
1005                                         *best_clock = clock;
1006                                         bestppm = ppm;
1007                                         found = true;
1008                                 }
1009                         }
1010                 }
1011         }
1012
1013         return found;
1014 }
1015
1016 static bool
1017 chv_find_best_dpll(const intel_limit_t *limit,
1018                    struct intel_crtc_state *crtc_state,
1019                    int target, int refclk, intel_clock_t *match_clock,
1020                    intel_clock_t *best_clock)
1021 {
1022         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1023         struct drm_device *dev = crtc->base.dev;
1024         unsigned int best_error_ppm;
1025         intel_clock_t clock;
1026         uint64_t m2;
1027         int found = false;
1028
1029         memset(best_clock, 0, sizeof(*best_clock));
1030         best_error_ppm = 1000000;
1031
1032         /*
1033          * Based on hardware doc, the n always set to 1, and m1 always
1034          * set to 2.  If requires to support 200Mhz refclk, we need to
1035          * revisit this because n may not 1 anymore.
1036          */
1037         clock.n = 1, clock.m1 = 2;
1038         target *= 5;    /* fast clock */
1039
1040         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1041                 for (clock.p2 = limit->p2.p2_fast;
1042                                 clock.p2 >= limit->p2.p2_slow;
1043                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1044                         unsigned int error_ppm;
1045
1046                         clock.p = clock.p1 * clock.p2;
1047
1048                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1049                                         clock.n) << 22, refclk * clock.m1);
1050
1051                         if (m2 > INT_MAX/clock.m1)
1052                                 continue;
1053
1054                         clock.m2 = m2;
1055
1056                         chv_calc_dpll_params(refclk, &clock);
1057
1058                         if (!intel_PLL_is_valid(dev, limit, &clock))
1059                                 continue;
1060
1061                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1062                                                 best_error_ppm, &error_ppm))
1063                                 continue;
1064
1065                         *best_clock = clock;
1066                         best_error_ppm = error_ppm;
1067                         found = true;
1068                 }
1069         }
1070
1071         return found;
1072 }
1073
1074 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1075                         intel_clock_t *best_clock)
1076 {
1077         int refclk = i9xx_get_refclk(crtc_state, 0);
1078
1079         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1080                                   target_clock, refclk, NULL, best_clock);
1081 }
1082
1083 bool intel_crtc_active(struct drm_crtc *crtc)
1084 {
1085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1086
1087         /* Be paranoid as we can arrive here with only partial
1088          * state retrieved from the hardware during setup.
1089          *
1090          * We can ditch the adjusted_mode.crtc_clock check as soon
1091          * as Haswell has gained clock readout/fastboot support.
1092          *
1093          * We can ditch the crtc->primary->fb check as soon as we can
1094          * properly reconstruct framebuffers.
1095          *
1096          * FIXME: The intel_crtc->active here should be switched to
1097          * crtc->state->active once we have proper CRTC states wired up
1098          * for atomic.
1099          */
1100         return intel_crtc->active && crtc->primary->state->fb &&
1101                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1102 }
1103
1104 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1105                                              enum pipe pipe)
1106 {
1107         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1109
1110         return intel_crtc->config->cpu_transcoder;
1111 }
1112
1113 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1114 {
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         i915_reg_t reg = PIPEDSL(pipe);
1117         u32 line1, line2;
1118         u32 line_mask;
1119
1120         if (IS_GEN2(dev))
1121                 line_mask = DSL_LINEMASK_GEN2;
1122         else
1123                 line_mask = DSL_LINEMASK_GEN3;
1124
1125         line1 = I915_READ(reg) & line_mask;
1126         msleep(5);
1127         line2 = I915_READ(reg) & line_mask;
1128
1129         return line1 == line2;
1130 }
1131
1132 /*
1133  * intel_wait_for_pipe_off - wait for pipe to turn off
1134  * @crtc: crtc whose pipe to wait for
1135  *
1136  * After disabling a pipe, we can't wait for vblank in the usual way,
1137  * spinning on the vblank interrupt status bit, since we won't actually
1138  * see an interrupt when the pipe is disabled.
1139  *
1140  * On Gen4 and above:
1141  *   wait for the pipe register state bit to turn off
1142  *
1143  * Otherwise:
1144  *   wait for the display line value to settle (it usually
1145  *   ends up stopping at the start of the next frame).
1146  *
1147  */
1148 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1149 {
1150         struct drm_device *dev = crtc->base.dev;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1153         enum pipe pipe = crtc->pipe;
1154
1155         if (INTEL_INFO(dev)->gen >= 4) {
1156                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1157
1158                 /* Wait for the Pipe State to go off */
1159                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1160                              100))
1161                         WARN(1, "pipe_off wait timed out\n");
1162         } else {
1163                 /* Wait for the display line to settle */
1164                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1165                         WARN(1, "pipe_off wait timed out\n");
1166         }
1167 }
1168
1169 /* Only for pre-ILK configs */
1170 void assert_pll(struct drm_i915_private *dev_priv,
1171                 enum pipe pipe, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         val = I915_READ(DPLL(pipe));
1177         cur_state = !!(val & DPLL_VCO_ENABLE);
1178         I915_STATE_WARN(cur_state != state,
1179              "PLL state assertion failure (expected %s, current %s)\n",
1180                         onoff(state), onoff(cur_state));
1181 }
1182
1183 /* XXX: the dsi pll is shared between MIPI DSI ports */
1184 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1185 {
1186         u32 val;
1187         bool cur_state;
1188
1189         mutex_lock(&dev_priv->sb_lock);
1190         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1191         mutex_unlock(&dev_priv->sb_lock);
1192
1193         cur_state = val & DSI_PLL_VCO_EN;
1194         I915_STATE_WARN(cur_state != state,
1195              "DSI PLL state assertion failure (expected %s, current %s)\n",
1196                         onoff(state), onoff(cur_state));
1197 }
1198
1199 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1200                           enum pipe pipe, bool state)
1201 {
1202         bool cur_state;
1203         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1204                                                                       pipe);
1205
1206         if (HAS_DDI(dev_priv->dev)) {
1207                 /* DDI does not have a specific FDI_TX register */
1208                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1209                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1210         } else {
1211                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1212                 cur_state = !!(val & FDI_TX_ENABLE);
1213         }
1214         I915_STATE_WARN(cur_state != state,
1215              "FDI TX state assertion failure (expected %s, current %s)\n",
1216                         onoff(state), onoff(cur_state));
1217 }
1218 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1219 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1220
1221 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1222                           enum pipe pipe, bool state)
1223 {
1224         u32 val;
1225         bool cur_state;
1226
1227         val = I915_READ(FDI_RX_CTL(pipe));
1228         cur_state = !!(val & FDI_RX_ENABLE);
1229         I915_STATE_WARN(cur_state != state,
1230              "FDI RX state assertion failure (expected %s, current %s)\n",
1231                         onoff(state), onoff(cur_state));
1232 }
1233 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1234 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1235
1236 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1237                                       enum pipe pipe)
1238 {
1239         u32 val;
1240
1241         /* ILK FDI PLL is always enabled */
1242         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1243                 return;
1244
1245         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1246         if (HAS_DDI(dev_priv->dev))
1247                 return;
1248
1249         val = I915_READ(FDI_TX_CTL(pipe));
1250         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1251 }
1252
1253 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1254                        enum pipe pipe, bool state)
1255 {
1256         u32 val;
1257         bool cur_state;
1258
1259         val = I915_READ(FDI_RX_CTL(pipe));
1260         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261         I915_STATE_WARN(cur_state != state,
1262              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263                         onoff(state), onoff(cur_state));
1264 }
1265
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267                            enum pipe pipe)
1268 {
1269         struct drm_device *dev = dev_priv->dev;
1270         i915_reg_t pp_reg;
1271         u32 val;
1272         enum pipe panel_pipe = PIPE_A;
1273         bool locked = true;
1274
1275         if (WARN_ON(HAS_DDI(dev)))
1276                 return;
1277
1278         if (HAS_PCH_SPLIT(dev)) {
1279                 u32 port_sel;
1280
1281                 pp_reg = PCH_PP_CONTROL;
1282                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286                         panel_pipe = PIPE_B;
1287                 /* XXX: else fix for eDP */
1288         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1289                 /* presumably write lock depends on pipe, not port select */
1290                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291                 panel_pipe = pipe;
1292         } else {
1293                 pp_reg = PP_CONTROL;
1294                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295                         panel_pipe = PIPE_B;
1296         }
1297
1298         val = I915_READ(pp_reg);
1299         if (!(val & PANEL_POWER_ON) ||
1300             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301                 locked = false;
1302
1303         I915_STATE_WARN(panel_pipe == pipe && locked,
1304              "panel assertion failure, pipe %c regs locked\n",
1305              pipe_name(pipe));
1306 }
1307
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309                           enum pipe pipe, bool state)
1310 {
1311         struct drm_device *dev = dev_priv->dev;
1312         bool cur_state;
1313
1314         if (IS_845G(dev) || IS_I865G(dev))
1315                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1316         else
1317                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319         I915_STATE_WARN(cur_state != state,
1320              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321                         pipe_name(pipe), onoff(state), onoff(cur_state));
1322 }
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327                  enum pipe pipe, bool state)
1328 {
1329         bool cur_state;
1330         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1331                                                                       pipe);
1332         enum intel_display_power_domain power_domain;
1333
1334         /* if we need the pipe quirk it must be always on */
1335         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1336             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1337                 state = true;
1338
1339         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1340         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1341                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1342                 cur_state = !!(val & PIPECONF_ENABLE);
1343
1344                 intel_display_power_put(dev_priv, power_domain);
1345         } else {
1346                 cur_state = false;
1347         }
1348
1349         I915_STATE_WARN(cur_state != state,
1350              "pipe %c assertion failure (expected %s, current %s)\n",
1351                         pipe_name(pipe), onoff(state), onoff(cur_state));
1352 }
1353
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355                          enum plane plane, bool state)
1356 {
1357         u32 val;
1358         bool cur_state;
1359
1360         val = I915_READ(DSPCNTR(plane));
1361         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1362         I915_STATE_WARN(cur_state != state,
1363              "plane %c assertion failure (expected %s, current %s)\n",
1364                         plane_name(plane), onoff(state), onoff(cur_state));
1365 }
1366
1367 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1368 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1369
1370 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1371                                    enum pipe pipe)
1372 {
1373         struct drm_device *dev = dev_priv->dev;
1374         int i;
1375
1376         /* Primary planes are fixed to pipes on gen4+ */
1377         if (INTEL_INFO(dev)->gen >= 4) {
1378                 u32 val = I915_READ(DSPCNTR(pipe));
1379                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380                      "plane %c assertion failure, should be disabled but not\n",
1381                      plane_name(pipe));
1382                 return;
1383         }
1384
1385         /* Need to check both planes against the pipe */
1386         for_each_pipe(dev_priv, i) {
1387                 u32 val = I915_READ(DSPCNTR(i));
1388                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1389                         DISPPLANE_SEL_PIPE_SHIFT;
1390                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1391                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1392                      plane_name(i), pipe_name(pipe));
1393         }
1394 }
1395
1396 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1397                                     enum pipe pipe)
1398 {
1399         struct drm_device *dev = dev_priv->dev;
1400         int sprite;
1401
1402         if (INTEL_INFO(dev)->gen >= 9) {
1403                 for_each_sprite(dev_priv, pipe, sprite) {
1404                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1405                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1406                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1407                              sprite, pipe_name(pipe));
1408                 }
1409         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1410                 for_each_sprite(dev_priv, pipe, sprite) {
1411                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1412                         I915_STATE_WARN(val & SP_ENABLE,
1413                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1414                              sprite_name(pipe, sprite), pipe_name(pipe));
1415                 }
1416         } else if (INTEL_INFO(dev)->gen >= 7) {
1417                 u32 val = I915_READ(SPRCTL(pipe));
1418                 I915_STATE_WARN(val & SPRITE_ENABLE,
1419                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420                      plane_name(pipe), pipe_name(pipe));
1421         } else if (INTEL_INFO(dev)->gen >= 5) {
1422                 u32 val = I915_READ(DVSCNTR(pipe));
1423                 I915_STATE_WARN(val & DVS_ENABLE,
1424                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425                      plane_name(pipe), pipe_name(pipe));
1426         }
1427 }
1428
1429 static void assert_vblank_disabled(struct drm_crtc *crtc)
1430 {
1431         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1432                 drm_crtc_vblank_put(crtc);
1433 }
1434
1435 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1436                                     enum pipe pipe)
1437 {
1438         u32 val;
1439         bool enabled;
1440
1441         val = I915_READ(PCH_TRANSCONF(pipe));
1442         enabled = !!(val & TRANS_ENABLE);
1443         I915_STATE_WARN(enabled,
1444              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1445              pipe_name(pipe));
1446 }
1447
1448 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1449                             enum pipe pipe, u32 port_sel, u32 val)
1450 {
1451         if ((val & DP_PORT_EN) == 0)
1452                 return false;
1453
1454         if (HAS_PCH_CPT(dev_priv->dev)) {
1455                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1456                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1457                         return false;
1458         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1459                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1460                         return false;
1461         } else {
1462                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1463                         return false;
1464         }
1465         return true;
1466 }
1467
1468 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1469                               enum pipe pipe, u32 val)
1470 {
1471         if ((val & SDVO_ENABLE) == 0)
1472                 return false;
1473
1474         if (HAS_PCH_CPT(dev_priv->dev)) {
1475                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1476                         return false;
1477         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1478                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1479                         return false;
1480         } else {
1481                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1482                         return false;
1483         }
1484         return true;
1485 }
1486
1487 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1488                               enum pipe pipe, u32 val)
1489 {
1490         if ((val & LVDS_PORT_EN) == 0)
1491                 return false;
1492
1493         if (HAS_PCH_CPT(dev_priv->dev)) {
1494                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1495                         return false;
1496         } else {
1497                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1498                         return false;
1499         }
1500         return true;
1501 }
1502
1503 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1504                               enum pipe pipe, u32 val)
1505 {
1506         if ((val & ADPA_DAC_ENABLE) == 0)
1507                 return false;
1508         if (HAS_PCH_CPT(dev_priv->dev)) {
1509                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1510                         return false;
1511         } else {
1512                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1513                         return false;
1514         }
1515         return true;
1516 }
1517
1518 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1519                                    enum pipe pipe, i915_reg_t reg,
1520                                    u32 port_sel)
1521 {
1522         u32 val = I915_READ(reg);
1523         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1524              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1525              i915_mmio_reg_offset(reg), pipe_name(pipe));
1526
1527         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1528              && (val & DP_PIPEB_SELECT),
1529              "IBX PCH dp port still using transcoder B\n");
1530 }
1531
1532 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1533                                      enum pipe pipe, i915_reg_t reg)
1534 {
1535         u32 val = I915_READ(reg);
1536         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1537              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1538              i915_mmio_reg_offset(reg), pipe_name(pipe));
1539
1540         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1541              && (val & SDVO_PIPE_B_SELECT),
1542              "IBX PCH hdmi port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1546                                       enum pipe pipe)
1547 {
1548         u32 val;
1549
1550         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1551         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1552         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1553
1554         val = I915_READ(PCH_ADPA);
1555         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1556              "PCH VGA enabled on transcoder %c, should be disabled\n",
1557              pipe_name(pipe));
1558
1559         val = I915_READ(PCH_LVDS);
1560         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1561              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1562              pipe_name(pipe));
1563
1564         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1565         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1566         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1567 }
1568
1569 static void vlv_enable_pll(struct intel_crtc *crtc,
1570                            const struct intel_crtc_state *pipe_config)
1571 {
1572         struct drm_device *dev = crtc->base.dev;
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574         i915_reg_t reg = DPLL(crtc->pipe);
1575         u32 dpll = pipe_config->dpll_hw_state.dpll;
1576
1577         assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579         /* PLL is protected by panel, make sure we can write it */
1580         if (IS_MOBILE(dev_priv->dev))
1581                 assert_panel_unlocked(dev_priv, crtc->pipe);
1582
1583         I915_WRITE(reg, dpll);
1584         POSTING_READ(reg);
1585         udelay(150);
1586
1587         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1588                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1589
1590         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1591         POSTING_READ(DPLL_MD(crtc->pipe));
1592
1593         /* We do this three times for luck */
1594         I915_WRITE(reg, dpll);
1595         POSTING_READ(reg);
1596         udelay(150); /* wait for warmup */
1597         I915_WRITE(reg, dpll);
1598         POSTING_READ(reg);
1599         udelay(150); /* wait for warmup */
1600         I915_WRITE(reg, dpll);
1601         POSTING_READ(reg);
1602         udelay(150); /* wait for warmup */
1603 }
1604
1605 static void chv_enable_pll(struct intel_crtc *crtc,
1606                            const struct intel_crtc_state *pipe_config)
1607 {
1608         struct drm_device *dev = crtc->base.dev;
1609         struct drm_i915_private *dev_priv = dev->dev_private;
1610         int pipe = crtc->pipe;
1611         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1612         u32 tmp;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         mutex_lock(&dev_priv->sb_lock);
1617
1618         /* Enable back the 10bit clock to display controller */
1619         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1620         tmp |= DPIO_DCLKP_EN;
1621         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1622
1623         mutex_unlock(&dev_priv->sb_lock);
1624
1625         /*
1626          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1627          */
1628         udelay(1);
1629
1630         /* Enable PLL */
1631         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1632
1633         /* Check PLL is locked */
1634         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1636
1637         /* not sure when this should be written */
1638         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1639         POSTING_READ(DPLL_MD(pipe));
1640 }
1641
1642 static int intel_num_dvo_pipes(struct drm_device *dev)
1643 {
1644         struct intel_crtc *crtc;
1645         int count = 0;
1646
1647         for_each_intel_crtc(dev, crtc)
1648                 count += crtc->base.state->active &&
1649                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1650
1651         return count;
1652 }
1653
1654 static void i9xx_enable_pll(struct intel_crtc *crtc)
1655 {
1656         struct drm_device *dev = crtc->base.dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         i915_reg_t reg = DPLL(crtc->pipe);
1659         u32 dpll = crtc->config->dpll_hw_state.dpll;
1660
1661         assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663         /* No really, not for ILK+ */
1664         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1665
1666         /* PLL is protected by panel, make sure we can write it */
1667         if (IS_MOBILE(dev) && !IS_I830(dev))
1668                 assert_panel_unlocked(dev_priv, crtc->pipe);
1669
1670         /* Enable DVO 2x clock on both PLLs if necessary */
1671         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1672                 /*
1673                  * It appears to be important that we don't enable this
1674                  * for the current pipe before otherwise configuring the
1675                  * PLL. No idea how this should be handled if multiple
1676                  * DVO outputs are enabled simultaneosly.
1677                  */
1678                 dpll |= DPLL_DVO_2X_MODE;
1679                 I915_WRITE(DPLL(!crtc->pipe),
1680                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1681         }
1682
1683         /*
1684          * Apparently we need to have VGA mode enabled prior to changing
1685          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1686          * dividers, even though the register value does change.
1687          */
1688         I915_WRITE(reg, 0);
1689
1690         I915_WRITE(reg, dpll);
1691
1692         /* Wait for the clocks to stabilize. */
1693         POSTING_READ(reg);
1694         udelay(150);
1695
1696         if (INTEL_INFO(dev)->gen >= 4) {
1697                 I915_WRITE(DPLL_MD(crtc->pipe),
1698                            crtc->config->dpll_hw_state.dpll_md);
1699         } else {
1700                 /* The pixel multiplier can only be updated once the
1701                  * DPLL is enabled and the clocks are stable.
1702                  *
1703                  * So write it again.
1704                  */
1705                 I915_WRITE(reg, dpll);
1706         }
1707
1708         /* We do this three times for luck */
1709         I915_WRITE(reg, dpll);
1710         POSTING_READ(reg);
1711         udelay(150); /* wait for warmup */
1712         I915_WRITE(reg, dpll);
1713         POSTING_READ(reg);
1714         udelay(150); /* wait for warmup */
1715         I915_WRITE(reg, dpll);
1716         POSTING_READ(reg);
1717         udelay(150); /* wait for warmup */
1718 }
1719
1720 /**
1721  * i9xx_disable_pll - disable a PLL
1722  * @dev_priv: i915 private structure
1723  * @pipe: pipe PLL to disable
1724  *
1725  * Disable the PLL for @pipe, making sure the pipe is off first.
1726  *
1727  * Note!  This is for pre-ILK only.
1728  */
1729 static void i9xx_disable_pll(struct intel_crtc *crtc)
1730 {
1731         struct drm_device *dev = crtc->base.dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         enum pipe pipe = crtc->pipe;
1734
1735         /* Disable DVO 2x clock on both PLLs if necessary */
1736         if (IS_I830(dev) &&
1737             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1738             !intel_num_dvo_pipes(dev)) {
1739                 I915_WRITE(DPLL(PIPE_B),
1740                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1741                 I915_WRITE(DPLL(PIPE_A),
1742                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1743         }
1744
1745         /* Don't disable pipe or pipe PLLs if needed */
1746         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1747             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1748                 return;
1749
1750         /* Make sure the pipe isn't still relying on us */
1751         assert_pipe_disabled(dev_priv, pipe);
1752
1753         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1754         POSTING_READ(DPLL(pipe));
1755 }
1756
1757 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1758 {
1759         u32 val;
1760
1761         /* Make sure the pipe isn't still relying on us */
1762         assert_pipe_disabled(dev_priv, pipe);
1763
1764         /*
1765          * Leave integrated clock source and reference clock enabled for pipe B.
1766          * The latter is needed for VGA hotplug / manual detection.
1767          */
1768         val = DPLL_VGA_MODE_DIS;
1769         if (pipe == PIPE_B)
1770                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1771         I915_WRITE(DPLL(pipe), val);
1772         POSTING_READ(DPLL(pipe));
1773
1774 }
1775
1776 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1777 {
1778         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1779         u32 val;
1780
1781         /* Make sure the pipe isn't still relying on us */
1782         assert_pipe_disabled(dev_priv, pipe);
1783
1784         /* Set PLL en = 0 */
1785         val = DPLL_SSC_REF_CLK_CHV |
1786                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1787         if (pipe != PIPE_A)
1788                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1789         I915_WRITE(DPLL(pipe), val);
1790         POSTING_READ(DPLL(pipe));
1791
1792         mutex_lock(&dev_priv->sb_lock);
1793
1794         /* Disable 10bit clock to display controller */
1795         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1796         val &= ~DPIO_DCLKP_EN;
1797         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1798
1799         mutex_unlock(&dev_priv->sb_lock);
1800 }
1801
1802 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1803                          struct intel_digital_port *dport,
1804                          unsigned int expected_mask)
1805 {
1806         u32 port_mask;
1807         i915_reg_t dpll_reg;
1808
1809         switch (dport->port) {
1810         case PORT_B:
1811                 port_mask = DPLL_PORTB_READY_MASK;
1812                 dpll_reg = DPLL(0);
1813                 break;
1814         case PORT_C:
1815                 port_mask = DPLL_PORTC_READY_MASK;
1816                 dpll_reg = DPLL(0);
1817                 expected_mask <<= 4;
1818                 break;
1819         case PORT_D:
1820                 port_mask = DPLL_PORTD_READY_MASK;
1821                 dpll_reg = DPIO_PHY_STATUS;
1822                 break;
1823         default:
1824                 BUG();
1825         }
1826
1827         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1828                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1829                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1830 }
1831
1832 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1833                                            enum pipe pipe)
1834 {
1835         struct drm_device *dev = dev_priv->dev;
1836         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1838         i915_reg_t reg;
1839         uint32_t val, pipeconf_val;
1840
1841         /* PCH only available on ILK+ */
1842         BUG_ON(!HAS_PCH_SPLIT(dev));
1843
1844         /* Make sure PCH DPLL is enabled */
1845         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1846
1847         /* FDI must be feeding us bits for PCH ports */
1848         assert_fdi_tx_enabled(dev_priv, pipe);
1849         assert_fdi_rx_enabled(dev_priv, pipe);
1850
1851         if (HAS_PCH_CPT(dev)) {
1852                 /* Workaround: Set the timing override bit before enabling the
1853                  * pch transcoder. */
1854                 reg = TRANS_CHICKEN2(pipe);
1855                 val = I915_READ(reg);
1856                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857                 I915_WRITE(reg, val);
1858         }
1859
1860         reg = PCH_TRANSCONF(pipe);
1861         val = I915_READ(reg);
1862         pipeconf_val = I915_READ(PIPECONF(pipe));
1863
1864         if (HAS_PCH_IBX(dev_priv->dev)) {
1865                 /*
1866                  * Make the BPC in transcoder be consistent with
1867                  * that in pipeconf reg. For HDMI we must use 8bpc
1868                  * here for both 8bpc and 12bpc.
1869                  */
1870                 val &= ~PIPECONF_BPC_MASK;
1871                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1872                         val |= PIPECONF_8BPC;
1873                 else
1874                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1875         }
1876
1877         val &= ~TRANS_INTERLACE_MASK;
1878         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1879                 if (HAS_PCH_IBX(dev_priv->dev) &&
1880                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1881                         val |= TRANS_LEGACY_INTERLACED_ILK;
1882                 else
1883                         val |= TRANS_INTERLACED;
1884         else
1885                 val |= TRANS_PROGRESSIVE;
1886
1887         I915_WRITE(reg, val | TRANS_ENABLE);
1888         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1889                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1890 }
1891
1892 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1893                                       enum transcoder cpu_transcoder)
1894 {
1895         u32 val, pipeconf_val;
1896
1897         /* PCH only available on ILK+ */
1898         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1899
1900         /* FDI must be feeding us bits for PCH ports */
1901         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1902         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1903
1904         /* Workaround: set timing override bit. */
1905         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1906         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1907         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1908
1909         val = TRANS_ENABLE;
1910         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1911
1912         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1913             PIPECONF_INTERLACED_ILK)
1914                 val |= TRANS_INTERLACED;
1915         else
1916                 val |= TRANS_PROGRESSIVE;
1917
1918         I915_WRITE(LPT_TRANSCONF, val);
1919         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1920                 DRM_ERROR("Failed to enable PCH transcoder\n");
1921 }
1922
1923 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1924                                             enum pipe pipe)
1925 {
1926         struct drm_device *dev = dev_priv->dev;
1927         i915_reg_t reg;
1928         uint32_t val;
1929
1930         /* FDI relies on the transcoder */
1931         assert_fdi_tx_disabled(dev_priv, pipe);
1932         assert_fdi_rx_disabled(dev_priv, pipe);
1933
1934         /* Ports must be off as well */
1935         assert_pch_ports_disabled(dev_priv, pipe);
1936
1937         reg = PCH_TRANSCONF(pipe);
1938         val = I915_READ(reg);
1939         val &= ~TRANS_ENABLE;
1940         I915_WRITE(reg, val);
1941         /* wait for PCH transcoder off, transcoder state */
1942         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1943                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1944
1945         if (HAS_PCH_CPT(dev)) {
1946                 /* Workaround: Clear the timing override chicken bit again. */
1947                 reg = TRANS_CHICKEN2(pipe);
1948                 val = I915_READ(reg);
1949                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950                 I915_WRITE(reg, val);
1951         }
1952 }
1953
1954 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1955 {
1956         u32 val;
1957
1958         val = I915_READ(LPT_TRANSCONF);
1959         val &= ~TRANS_ENABLE;
1960         I915_WRITE(LPT_TRANSCONF, val);
1961         /* wait for PCH transcoder off, transcoder state */
1962         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1963                 DRM_ERROR("Failed to disable PCH transcoder\n");
1964
1965         /* Workaround: clear timing override bit. */
1966         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1967         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1968         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1969 }
1970
1971 /**
1972  * intel_enable_pipe - enable a pipe, asserting requirements
1973  * @crtc: crtc responsible for the pipe
1974  *
1975  * Enable @crtc's pipe, making sure that various hardware specific requirements
1976  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1977  */
1978 static void intel_enable_pipe(struct intel_crtc *crtc)
1979 {
1980         struct drm_device *dev = crtc->base.dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         enum pipe pipe = crtc->pipe;
1983         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1984         enum pipe pch_transcoder;
1985         i915_reg_t reg;
1986         u32 val;
1987
1988         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1989
1990         assert_planes_disabled(dev_priv, pipe);
1991         assert_cursor_disabled(dev_priv, pipe);
1992         assert_sprites_disabled(dev_priv, pipe);
1993
1994         if (HAS_PCH_LPT(dev_priv->dev))
1995                 pch_transcoder = TRANSCODER_A;
1996         else
1997                 pch_transcoder = pipe;
1998
1999         /*
2000          * A pipe without a PLL won't actually be able to drive bits from
2001          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2002          * need the check.
2003          */
2004         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2005                 if (crtc->config->has_dsi_encoder)
2006                         assert_dsi_pll_enabled(dev_priv);
2007                 else
2008                         assert_pll_enabled(dev_priv, pipe);
2009         else {
2010                 if (crtc->config->has_pch_encoder) {
2011                         /* if driving the PCH, we need FDI enabled */
2012                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2013                         assert_fdi_tx_pll_enabled(dev_priv,
2014                                                   (enum pipe) cpu_transcoder);
2015                 }
2016                 /* FIXME: assert CPU port conditions for SNB+ */
2017         }
2018
2019         reg = PIPECONF(cpu_transcoder);
2020         val = I915_READ(reg);
2021         if (val & PIPECONF_ENABLE) {
2022                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2023                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2024                 return;
2025         }
2026
2027         I915_WRITE(reg, val | PIPECONF_ENABLE);
2028         POSTING_READ(reg);
2029
2030         /*
2031          * Until the pipe starts DSL will read as 0, which would cause
2032          * an apparent vblank timestamp jump, which messes up also the
2033          * frame count when it's derived from the timestamps. So let's
2034          * wait for the pipe to start properly before we call
2035          * drm_crtc_vblank_on()
2036          */
2037         if (dev->max_vblank_count == 0 &&
2038             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2039                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2040 }
2041
2042 /**
2043  * intel_disable_pipe - disable a pipe, asserting requirements
2044  * @crtc: crtc whose pipes is to be disabled
2045  *
2046  * Disable the pipe of @crtc, making sure that various hardware
2047  * specific requirements are met, if applicable, e.g. plane
2048  * disabled, panel fitter off, etc.
2049  *
2050  * Will wait until the pipe has shut down before returning.
2051  */
2052 static void intel_disable_pipe(struct intel_crtc *crtc)
2053 {
2054         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2055         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2056         enum pipe pipe = crtc->pipe;
2057         i915_reg_t reg;
2058         u32 val;
2059
2060         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2061
2062         /*
2063          * Make sure planes won't keep trying to pump pixels to us,
2064          * or we might hang the display.
2065          */
2066         assert_planes_disabled(dev_priv, pipe);
2067         assert_cursor_disabled(dev_priv, pipe);
2068         assert_sprites_disabled(dev_priv, pipe);
2069
2070         reg = PIPECONF(cpu_transcoder);
2071         val = I915_READ(reg);
2072         if ((val & PIPECONF_ENABLE) == 0)
2073                 return;
2074
2075         /*
2076          * Double wide has implications for planes
2077          * so best keep it disabled when not needed.
2078          */
2079         if (crtc->config->double_wide)
2080                 val &= ~PIPECONF_DOUBLE_WIDE;
2081
2082         /* Don't disable pipe or pipe PLLs if needed */
2083         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2084             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2085                 val &= ~PIPECONF_ENABLE;
2086
2087         I915_WRITE(reg, val);
2088         if ((val & PIPECONF_ENABLE) == 0)
2089                 intel_wait_for_pipe_off(crtc);
2090 }
2091
2092 static bool need_vtd_wa(struct drm_device *dev)
2093 {
2094 #ifdef CONFIG_INTEL_IOMMU
2095         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2096                 return true;
2097 #endif
2098         return false;
2099 }
2100
2101 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2102 {
2103         return IS_GEN2(dev_priv) ? 2048 : 4096;
2104 }
2105
2106 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2107                                            uint64_t fb_modifier, unsigned int cpp)
2108 {
2109         switch (fb_modifier) {
2110         case DRM_FORMAT_MOD_NONE:
2111                 return cpp;
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (IS_GEN2(dev_priv))
2114                         return 128;
2115                 else
2116                         return 512;
2117         case I915_FORMAT_MOD_Y_TILED:
2118                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2119                         return 128;
2120                 else
2121                         return 512;
2122         case I915_FORMAT_MOD_Yf_TILED:
2123                 switch (cpp) {
2124                 case 1:
2125                         return 64;
2126                 case 2:
2127                 case 4:
2128                         return 128;
2129                 case 8:
2130                 case 16:
2131                         return 256;
2132                 default:
2133                         MISSING_CASE(cpp);
2134                         return cpp;
2135                 }
2136                 break;
2137         default:
2138                 MISSING_CASE(fb_modifier);
2139                 return cpp;
2140         }
2141 }
2142
2143 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2144                                uint64_t fb_modifier, unsigned int cpp)
2145 {
2146         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2147                 return 1;
2148         else
2149                 return intel_tile_size(dev_priv) /
2150                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2151 }
2152
2153 /* Return the tile dimensions in pixel units */
2154 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2155                             unsigned int *tile_width,
2156                             unsigned int *tile_height,
2157                             uint64_t fb_modifier,
2158                             unsigned int cpp)
2159 {
2160         unsigned int tile_width_bytes =
2161                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2162
2163         *tile_width = tile_width_bytes / cpp;
2164         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2165 }
2166
2167 unsigned int
2168 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2169                       uint32_t pixel_format, uint64_t fb_modifier)
2170 {
2171         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2172         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2173
2174         return ALIGN(height, tile_height);
2175 }
2176
2177 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2178 {
2179         unsigned int size = 0;
2180         int i;
2181
2182         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2183                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2184
2185         return size;
2186 }
2187
2188 static void
2189 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2190                         const struct drm_framebuffer *fb,
2191                         unsigned int rotation)
2192 {
2193         if (intel_rotation_90_or_270(rotation)) {
2194                 *view = i915_ggtt_view_rotated;
2195                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2196         } else {
2197                 *view = i915_ggtt_view_normal;
2198         }
2199 }
2200
2201 static void
2202 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2203                    struct drm_framebuffer *fb)
2204 {
2205         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2206         unsigned int tile_size, tile_width, tile_height, cpp;
2207
2208         tile_size = intel_tile_size(dev_priv);
2209
2210         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2211         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2212                         fb->modifier[0], cpp);
2213
2214         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2215         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2216
2217         if (info->pixel_format == DRM_FORMAT_NV12) {
2218                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2219                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2220                                 fb->modifier[1], cpp);
2221
2222                 info->uv_offset = fb->offsets[1];
2223                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2224                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2225         }
2226 }
2227
2228 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2229 {
2230         if (INTEL_INFO(dev_priv)->gen >= 9)
2231                 return 256 * 1024;
2232         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2233                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2234                 return 128 * 1024;
2235         else if (INTEL_INFO(dev_priv)->gen >= 4)
2236                 return 4 * 1024;
2237         else
2238                 return 0;
2239 }
2240
2241 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2242                                          uint64_t fb_modifier)
2243 {
2244         switch (fb_modifier) {
2245         case DRM_FORMAT_MOD_NONE:
2246                 return intel_linear_alignment(dev_priv);
2247         case I915_FORMAT_MOD_X_TILED:
2248                 if (INTEL_INFO(dev_priv)->gen >= 9)
2249                         return 256 * 1024;
2250                 return 0;
2251         case I915_FORMAT_MOD_Y_TILED:
2252         case I915_FORMAT_MOD_Yf_TILED:
2253                 return 1 * 1024 * 1024;
2254         default:
2255                 MISSING_CASE(fb_modifier);
2256                 return 0;
2257         }
2258 }
2259
2260 int
2261 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2262                            unsigned int rotation)
2263 {
2264         struct drm_device *dev = fb->dev;
2265         struct drm_i915_private *dev_priv = dev->dev_private;
2266         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2267         struct i915_ggtt_view view;
2268         u32 alignment;
2269         int ret;
2270
2271         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2272
2273         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2274
2275         intel_fill_fb_ggtt_view(&view, fb, rotation);
2276
2277         /* Note that the w/a also requires 64 PTE of padding following the
2278          * bo. We currently fill all unused PTE with the shadow page and so
2279          * we should always have valid PTE following the scanout preventing
2280          * the VT-d warning.
2281          */
2282         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2283                 alignment = 256 * 1024;
2284
2285         /*
2286          * Global gtt pte registers are special registers which actually forward
2287          * writes to a chunk of system memory. Which means that there is no risk
2288          * that the register values disappear as soon as we call
2289          * intel_runtime_pm_put(), so it is correct to wrap only the
2290          * pin/unpin/fence and not more.
2291          */
2292         intel_runtime_pm_get(dev_priv);
2293
2294         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2295                                                    &view);
2296         if (ret)
2297                 goto err_pm;
2298
2299         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2300          * fence, whereas 965+ only requires a fence if using
2301          * framebuffer compression.  For simplicity, we always install
2302          * a fence as the cost is not that onerous.
2303          */
2304         if (view.type == I915_GGTT_VIEW_NORMAL) {
2305                 ret = i915_gem_object_get_fence(obj);
2306                 if (ret == -EDEADLK) {
2307                         /*
2308                          * -EDEADLK means there are no free fences
2309                          * no pending flips.
2310                          *
2311                          * This is propagated to atomic, but it uses
2312                          * -EDEADLK to force a locking recovery, so
2313                          * change the returned error to -EBUSY.
2314                          */
2315                         ret = -EBUSY;
2316                         goto err_unpin;
2317                 } else if (ret)
2318                         goto err_unpin;
2319
2320                 i915_gem_object_pin_fence(obj);
2321         }
2322
2323         intel_runtime_pm_put(dev_priv);
2324         return 0;
2325
2326 err_unpin:
2327         i915_gem_object_unpin_from_display_plane(obj, &view);
2328 err_pm:
2329         intel_runtime_pm_put(dev_priv);
2330         return ret;
2331 }
2332
2333 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2334 {
2335         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336         struct i915_ggtt_view view;
2337
2338         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2339
2340         intel_fill_fb_ggtt_view(&view, fb, rotation);
2341
2342         if (view.type == I915_GGTT_VIEW_NORMAL)
2343                 i915_gem_object_unpin_fence(obj);
2344
2345         i915_gem_object_unpin_from_display_plane(obj, &view);
2346 }
2347
2348 /*
2349  * Adjust the tile offset by moving the difference into
2350  * the x/y offsets.
2351  *
2352  * Input tile dimensions and pitch must already be
2353  * rotated to match x and y, and in pixel units.
2354  */
2355 static u32 intel_adjust_tile_offset(int *x, int *y,
2356                                     unsigned int tile_width,
2357                                     unsigned int tile_height,
2358                                     unsigned int tile_size,
2359                                     unsigned int pitch_tiles,
2360                                     u32 old_offset,
2361                                     u32 new_offset)
2362 {
2363         unsigned int tiles;
2364
2365         WARN_ON(old_offset & (tile_size - 1));
2366         WARN_ON(new_offset & (tile_size - 1));
2367         WARN_ON(new_offset > old_offset);
2368
2369         tiles = (old_offset - new_offset) / tile_size;
2370
2371         *y += tiles / pitch_tiles * tile_height;
2372         *x += tiles % pitch_tiles * tile_width;
2373
2374         return new_offset;
2375 }
2376
2377 /*
2378  * Computes the linear offset to the base tile and adjusts
2379  * x, y. bytes per pixel is assumed to be a power-of-two.
2380  *
2381  * In the 90/270 rotated case, x and y are assumed
2382  * to be already rotated to match the rotated GTT view, and
2383  * pitch is the tile_height aligned framebuffer height.
2384  */
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct drm_framebuffer *fb, int plane,
2387                               unsigned int pitch,
2388                               unsigned int rotation)
2389 {
2390         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2391         uint64_t fb_modifier = fb->modifier[plane];
2392         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2393         u32 offset, offset_aligned, alignment;
2394
2395         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2396         if (alignment)
2397                 alignment--;
2398
2399         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2400                 unsigned int tile_size, tile_width, tile_height;
2401                 unsigned int tile_rows, tiles, pitch_tiles;
2402
2403                 tile_size = intel_tile_size(dev_priv);
2404                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2405                                 fb_modifier, cpp);
2406
2407                 if (intel_rotation_90_or_270(rotation)) {
2408                         pitch_tiles = pitch / tile_height;
2409                         swap(tile_width, tile_height);
2410                 } else {
2411                         pitch_tiles = pitch / (tile_width * cpp);
2412                 }
2413
2414                 tile_rows = *y / tile_height;
2415                 *y %= tile_height;
2416
2417                 tiles = *x / tile_width;
2418                 *x %= tile_width;
2419
2420                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2421                 offset_aligned = offset & ~alignment;
2422
2423                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2424                                          tile_size, pitch_tiles,
2425                                          offset, offset_aligned);
2426         } else {
2427                 offset = *y * pitch + *x * cpp;
2428                 offset_aligned = offset & ~alignment;
2429
2430                 *y = (offset & alignment) / pitch;
2431                 *x = ((offset & alignment) - *y * pitch) / cpp;
2432         }
2433
2434         return offset_aligned;
2435 }
2436
2437 static int i9xx_format_to_fourcc(int format)
2438 {
2439         switch (format) {
2440         case DISPPLANE_8BPP:
2441                 return DRM_FORMAT_C8;
2442         case DISPPLANE_BGRX555:
2443                 return DRM_FORMAT_XRGB1555;
2444         case DISPPLANE_BGRX565:
2445                 return DRM_FORMAT_RGB565;
2446         default:
2447         case DISPPLANE_BGRX888:
2448                 return DRM_FORMAT_XRGB8888;
2449         case DISPPLANE_RGBX888:
2450                 return DRM_FORMAT_XBGR8888;
2451         case DISPPLANE_BGRX101010:
2452                 return DRM_FORMAT_XRGB2101010;
2453         case DISPPLANE_RGBX101010:
2454                 return DRM_FORMAT_XBGR2101010;
2455         }
2456 }
2457
2458 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2459 {
2460         switch (format) {
2461         case PLANE_CTL_FORMAT_RGB_565:
2462                 return DRM_FORMAT_RGB565;
2463         default:
2464         case PLANE_CTL_FORMAT_XRGB_8888:
2465                 if (rgb_order) {
2466                         if (alpha)
2467                                 return DRM_FORMAT_ABGR8888;
2468                         else
2469                                 return DRM_FORMAT_XBGR8888;
2470                 } else {
2471                         if (alpha)
2472                                 return DRM_FORMAT_ARGB8888;
2473                         else
2474                                 return DRM_FORMAT_XRGB8888;
2475                 }
2476         case PLANE_CTL_FORMAT_XRGB_2101010:
2477                 if (rgb_order)
2478                         return DRM_FORMAT_XBGR2101010;
2479                 else
2480                         return DRM_FORMAT_XRGB2101010;
2481         }
2482 }
2483
2484 static bool
2485 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2486                               struct intel_initial_plane_config *plane_config)
2487 {
2488         struct drm_device *dev = crtc->base.dev;
2489         struct drm_i915_private *dev_priv = to_i915(dev);
2490         struct drm_i915_gem_object *obj = NULL;
2491         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2492         struct drm_framebuffer *fb = &plane_config->fb->base;
2493         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2494         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2495                                     PAGE_SIZE);
2496
2497         size_aligned -= base_aligned;
2498
2499         if (plane_config->size == 0)
2500                 return false;
2501
2502         /* If the FB is too big, just don't use it since fbdev is not very
2503          * important and we should probably use that space with FBC or other
2504          * features. */
2505         if (size_aligned * 2 > dev_priv->ggtt.stolen_usable_size)
2506                 return false;
2507
2508         mutex_lock(&dev->struct_mutex);
2509
2510         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2511                                                              base_aligned,
2512                                                              base_aligned,
2513                                                              size_aligned);
2514         if (!obj) {
2515                 mutex_unlock(&dev->struct_mutex);
2516                 return false;
2517         }
2518
2519         obj->tiling_mode = plane_config->tiling;
2520         if (obj->tiling_mode == I915_TILING_X)
2521                 obj->stride = fb->pitches[0];
2522
2523         mode_cmd.pixel_format = fb->pixel_format;
2524         mode_cmd.width = fb->width;
2525         mode_cmd.height = fb->height;
2526         mode_cmd.pitches[0] = fb->pitches[0];
2527         mode_cmd.modifier[0] = fb->modifier[0];
2528         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2529
2530         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2531                                    &mode_cmd, obj)) {
2532                 DRM_DEBUG_KMS("intel fb init failed\n");
2533                 goto out_unref_obj;
2534         }
2535
2536         mutex_unlock(&dev->struct_mutex);
2537
2538         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2539         return true;
2540
2541 out_unref_obj:
2542         drm_gem_object_unreference(&obj->base);
2543         mutex_unlock(&dev->struct_mutex);
2544         return false;
2545 }
2546
2547 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2548 static void
2549 update_state_fb(struct drm_plane *plane)
2550 {
2551         if (plane->fb == plane->state->fb)
2552                 return;
2553
2554         if (plane->state->fb)
2555                 drm_framebuffer_unreference(plane->state->fb);
2556         plane->state->fb = plane->fb;
2557         if (plane->state->fb)
2558                 drm_framebuffer_reference(plane->state->fb);
2559 }
2560
2561 static void
2562 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2563                              struct intel_initial_plane_config *plane_config)
2564 {
2565         struct drm_device *dev = intel_crtc->base.dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct drm_crtc *c;
2568         struct intel_crtc *i;
2569         struct drm_i915_gem_object *obj;
2570         struct drm_plane *primary = intel_crtc->base.primary;
2571         struct drm_plane_state *plane_state = primary->state;
2572         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2573         struct intel_plane *intel_plane = to_intel_plane(primary);
2574         struct intel_plane_state *intel_state =
2575                 to_intel_plane_state(plane_state);
2576         struct drm_framebuffer *fb;
2577
2578         if (!plane_config->fb)
2579                 return;
2580
2581         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2582                 fb = &plane_config->fb->base;
2583                 goto valid_fb;
2584         }
2585
2586         kfree(plane_config->fb);
2587
2588         /*
2589          * Failed to alloc the obj, check to see if we should share
2590          * an fb with another CRTC instead
2591          */
2592         for_each_crtc(dev, c) {
2593                 i = to_intel_crtc(c);
2594
2595                 if (c == &intel_crtc->base)
2596                         continue;
2597
2598                 if (!i->active)
2599                         continue;
2600
2601                 fb = c->primary->fb;
2602                 if (!fb)
2603                         continue;
2604
2605                 obj = intel_fb_obj(fb);
2606                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2607                         drm_framebuffer_reference(fb);
2608                         goto valid_fb;
2609                 }
2610         }
2611
2612         /*
2613          * We've failed to reconstruct the BIOS FB.  Current display state
2614          * indicates that the primary plane is visible, but has a NULL FB,
2615          * which will lead to problems later if we don't fix it up.  The
2616          * simplest solution is to just disable the primary plane now and
2617          * pretend the BIOS never had it enabled.
2618          */
2619         to_intel_plane_state(plane_state)->visible = false;
2620         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2621         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2622         intel_plane->disable_plane(primary, &intel_crtc->base);
2623
2624         return;
2625
2626 valid_fb:
2627         plane_state->src_x = 0;
2628         plane_state->src_y = 0;
2629         plane_state->src_w = fb->width << 16;
2630         plane_state->src_h = fb->height << 16;
2631
2632         plane_state->crtc_x = 0;
2633         plane_state->crtc_y = 0;
2634         plane_state->crtc_w = fb->width;
2635         plane_state->crtc_h = fb->height;
2636
2637         intel_state->src.x1 = plane_state->src_x;
2638         intel_state->src.y1 = plane_state->src_y;
2639         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2640         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2641         intel_state->dst.x1 = plane_state->crtc_x;
2642         intel_state->dst.y1 = plane_state->crtc_y;
2643         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2644         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2645
2646         obj = intel_fb_obj(fb);
2647         if (obj->tiling_mode != I915_TILING_NONE)
2648                 dev_priv->preserve_bios_swizzle = true;
2649
2650         drm_framebuffer_reference(fb);
2651         primary->fb = primary->state->fb = fb;
2652         primary->crtc = primary->state->crtc = &intel_crtc->base;
2653         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2654         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2655 }
2656
2657 static void i9xx_update_primary_plane(struct drm_plane *primary,
2658                                       const struct intel_crtc_state *crtc_state,
2659                                       const struct intel_plane_state *plane_state)
2660 {
2661         struct drm_device *dev = primary->dev;
2662         struct drm_i915_private *dev_priv = dev->dev_private;
2663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2664         struct drm_framebuffer *fb = plane_state->base.fb;
2665         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2666         int plane = intel_crtc->plane;
2667         u32 linear_offset;
2668         u32 dspcntr;
2669         i915_reg_t reg = DSPCNTR(plane);
2670         unsigned int rotation = plane_state->base.rotation;
2671         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2672         int x = plane_state->src.x1 >> 16;
2673         int y = plane_state->src.y1 >> 16;
2674
2675         dspcntr = DISPPLANE_GAMMA_ENABLE;
2676
2677         dspcntr |= DISPLAY_PLANE_ENABLE;
2678
2679         if (INTEL_INFO(dev)->gen < 4) {
2680                 if (intel_crtc->pipe == PIPE_B)
2681                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2682
2683                 /* pipesrc and dspsize control the size that is scaled from,
2684                  * which should always be the user's requested size.
2685                  */
2686                 I915_WRITE(DSPSIZE(plane),
2687                            ((crtc_state->pipe_src_h - 1) << 16) |
2688                            (crtc_state->pipe_src_w - 1));
2689                 I915_WRITE(DSPPOS(plane), 0);
2690         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2691                 I915_WRITE(PRIMSIZE(plane),
2692                            ((crtc_state->pipe_src_h - 1) << 16) |
2693                            (crtc_state->pipe_src_w - 1));
2694                 I915_WRITE(PRIMPOS(plane), 0);
2695                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2696         }
2697
2698         switch (fb->pixel_format) {
2699         case DRM_FORMAT_C8:
2700                 dspcntr |= DISPPLANE_8BPP;
2701                 break;
2702         case DRM_FORMAT_XRGB1555:
2703                 dspcntr |= DISPPLANE_BGRX555;
2704                 break;
2705         case DRM_FORMAT_RGB565:
2706                 dspcntr |= DISPPLANE_BGRX565;
2707                 break;
2708         case DRM_FORMAT_XRGB8888:
2709                 dspcntr |= DISPPLANE_BGRX888;
2710                 break;
2711         case DRM_FORMAT_XBGR8888:
2712                 dspcntr |= DISPPLANE_RGBX888;
2713                 break;
2714         case DRM_FORMAT_XRGB2101010:
2715                 dspcntr |= DISPPLANE_BGRX101010;
2716                 break;
2717         case DRM_FORMAT_XBGR2101010:
2718                 dspcntr |= DISPPLANE_RGBX101010;
2719                 break;
2720         default:
2721                 BUG();
2722         }
2723
2724         if (INTEL_INFO(dev)->gen >= 4 &&
2725             obj->tiling_mode != I915_TILING_NONE)
2726                 dspcntr |= DISPPLANE_TILED;
2727
2728         if (IS_G4X(dev))
2729                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2730
2731         linear_offset = y * fb->pitches[0] + x * cpp;
2732
2733         if (INTEL_INFO(dev)->gen >= 4) {
2734                 intel_crtc->dspaddr_offset =
2735                         intel_compute_tile_offset(&x, &y, fb, 0,
2736                                                   fb->pitches[0], rotation);
2737                 linear_offset -= intel_crtc->dspaddr_offset;
2738         } else {
2739                 intel_crtc->dspaddr_offset = linear_offset;
2740         }
2741
2742         if (rotation == BIT(DRM_ROTATE_180)) {
2743                 dspcntr |= DISPPLANE_ROTATE_180;
2744
2745                 x += (crtc_state->pipe_src_w - 1);
2746                 y += (crtc_state->pipe_src_h - 1);
2747
2748                 /* Finding the last pixel of the last line of the display
2749                 data and adding to linear_offset*/
2750                 linear_offset +=
2751                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2752                         (crtc_state->pipe_src_w - 1) * cpp;
2753         }
2754
2755         intel_crtc->adjusted_x = x;
2756         intel_crtc->adjusted_y = y;
2757
2758         I915_WRITE(reg, dspcntr);
2759
2760         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2761         if (INTEL_INFO(dev)->gen >= 4) {
2762                 I915_WRITE(DSPSURF(plane),
2763                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2764                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2765                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2766         } else
2767                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2768         POSTING_READ(reg);
2769 }
2770
2771 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2772                                        struct drm_crtc *crtc)
2773 {
2774         struct drm_device *dev = crtc->dev;
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777         int plane = intel_crtc->plane;
2778
2779         I915_WRITE(DSPCNTR(plane), 0);
2780         if (INTEL_INFO(dev_priv)->gen >= 4)
2781                 I915_WRITE(DSPSURF(plane), 0);
2782         else
2783                 I915_WRITE(DSPADDR(plane), 0);
2784         POSTING_READ(DSPCNTR(plane));
2785 }
2786
2787 static void ironlake_update_primary_plane(struct drm_plane *primary,
2788                                           const struct intel_crtc_state *crtc_state,
2789                                           const struct intel_plane_state *plane_state)
2790 {
2791         struct drm_device *dev = primary->dev;
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2794         struct drm_framebuffer *fb = plane_state->base.fb;
2795         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2796         int plane = intel_crtc->plane;
2797         u32 linear_offset;
2798         u32 dspcntr;
2799         i915_reg_t reg = DSPCNTR(plane);
2800         unsigned int rotation = plane_state->base.rotation;
2801         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2802         int x = plane_state->src.x1 >> 16;
2803         int y = plane_state->src.y1 >> 16;
2804
2805         dspcntr = DISPPLANE_GAMMA_ENABLE;
2806         dspcntr |= DISPLAY_PLANE_ENABLE;
2807
2808         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2810
2811         switch (fb->pixel_format) {
2812         case DRM_FORMAT_C8:
2813                 dspcntr |= DISPPLANE_8BPP;
2814                 break;
2815         case DRM_FORMAT_RGB565:
2816                 dspcntr |= DISPPLANE_BGRX565;
2817                 break;
2818         case DRM_FORMAT_XRGB8888:
2819                 dspcntr |= DISPPLANE_BGRX888;
2820                 break;
2821         case DRM_FORMAT_XBGR8888:
2822                 dspcntr |= DISPPLANE_RGBX888;
2823                 break;
2824         case DRM_FORMAT_XRGB2101010:
2825                 dspcntr |= DISPPLANE_BGRX101010;
2826                 break;
2827         case DRM_FORMAT_XBGR2101010:
2828                 dspcntr |= DISPPLANE_RGBX101010;
2829                 break;
2830         default:
2831                 BUG();
2832         }
2833
2834         if (obj->tiling_mode != I915_TILING_NONE)
2835                 dspcntr |= DISPPLANE_TILED;
2836
2837         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2838                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2839
2840         linear_offset = y * fb->pitches[0] + x * cpp;
2841         intel_crtc->dspaddr_offset =
2842                 intel_compute_tile_offset(&x, &y, fb, 0,
2843                                           fb->pitches[0], rotation);
2844         linear_offset -= intel_crtc->dspaddr_offset;
2845         if (rotation == BIT(DRM_ROTATE_180)) {
2846                 dspcntr |= DISPPLANE_ROTATE_180;
2847
2848                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2849                         x += (crtc_state->pipe_src_w - 1);
2850                         y += (crtc_state->pipe_src_h - 1);
2851
2852                         /* Finding the last pixel of the last line of the display
2853                         data and adding to linear_offset*/
2854                         linear_offset +=
2855                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2856                                 (crtc_state->pipe_src_w - 1) * cpp;
2857                 }
2858         }
2859
2860         intel_crtc->adjusted_x = x;
2861         intel_crtc->adjusted_y = y;
2862
2863         I915_WRITE(reg, dspcntr);
2864
2865         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2866         I915_WRITE(DSPSURF(plane),
2867                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2868         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2869                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2870         } else {
2871                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2872                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2873         }
2874         POSTING_READ(reg);
2875 }
2876
2877 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2878                               uint64_t fb_modifier, uint32_t pixel_format)
2879 {
2880         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2881                 return 64;
2882         } else {
2883                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2884
2885                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2886         }
2887 }
2888
2889 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2890                            struct drm_i915_gem_object *obj,
2891                            unsigned int plane)
2892 {
2893         struct i915_ggtt_view view;
2894         struct i915_vma *vma;
2895         u64 offset;
2896
2897         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2898                                 intel_plane->base.state->rotation);
2899
2900         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2901         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2902                 view.type))
2903                 return -1;
2904
2905         offset = vma->node.start;
2906
2907         if (plane == 1) {
2908                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2909                           PAGE_SIZE;
2910         }
2911
2912         WARN_ON(upper_32_bits(offset));
2913
2914         return lower_32_bits(offset);
2915 }
2916
2917 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2918 {
2919         struct drm_device *dev = intel_crtc->base.dev;
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921
2922         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2923         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2925 }
2926
2927 /*
2928  * This function detaches (aka. unbinds) unused scalers in hardware
2929  */
2930 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2931 {
2932         struct intel_crtc_scaler_state *scaler_state;
2933         int i;
2934
2935         scaler_state = &intel_crtc->config->scaler_state;
2936
2937         /* loop through and disable scalers that aren't in use */
2938         for (i = 0; i < intel_crtc->num_scalers; i++) {
2939                 if (!scaler_state->scalers[i].in_use)
2940                         skl_detach_scaler(intel_crtc, i);
2941         }
2942 }
2943
2944 u32 skl_plane_ctl_format(uint32_t pixel_format)
2945 {
2946         switch (pixel_format) {
2947         case DRM_FORMAT_C8:
2948                 return PLANE_CTL_FORMAT_INDEXED;
2949         case DRM_FORMAT_RGB565:
2950                 return PLANE_CTL_FORMAT_RGB_565;
2951         case DRM_FORMAT_XBGR8888:
2952                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2953         case DRM_FORMAT_XRGB8888:
2954                 return PLANE_CTL_FORMAT_XRGB_8888;
2955         /*
2956          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2957          * to be already pre-multiplied. We need to add a knob (or a different
2958          * DRM_FORMAT) for user-space to configure that.
2959          */
2960         case DRM_FORMAT_ABGR8888:
2961                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2962                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2963         case DRM_FORMAT_ARGB8888:
2964                 return PLANE_CTL_FORMAT_XRGB_8888 |
2965                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966         case DRM_FORMAT_XRGB2101010:
2967                 return PLANE_CTL_FORMAT_XRGB_2101010;
2968         case DRM_FORMAT_XBGR2101010:
2969                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2970         case DRM_FORMAT_YUYV:
2971                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2972         case DRM_FORMAT_YVYU:
2973                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2974         case DRM_FORMAT_UYVY:
2975                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2976         case DRM_FORMAT_VYUY:
2977                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2978         default:
2979                 MISSING_CASE(pixel_format);
2980         }
2981
2982         return 0;
2983 }
2984
2985 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2986 {
2987         switch (fb_modifier) {
2988         case DRM_FORMAT_MOD_NONE:
2989                 break;
2990         case I915_FORMAT_MOD_X_TILED:
2991                 return PLANE_CTL_TILED_X;
2992         case I915_FORMAT_MOD_Y_TILED:
2993                 return PLANE_CTL_TILED_Y;
2994         case I915_FORMAT_MOD_Yf_TILED:
2995                 return PLANE_CTL_TILED_YF;
2996         default:
2997                 MISSING_CASE(fb_modifier);
2998         }
2999
3000         return 0;
3001 }
3002
3003 u32 skl_plane_ctl_rotation(unsigned int rotation)
3004 {
3005         switch (rotation) {
3006         case BIT(DRM_ROTATE_0):
3007                 break;
3008         /*
3009          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3010          * while i915 HW rotation is clockwise, thats why this swapping.
3011          */
3012         case BIT(DRM_ROTATE_90):
3013                 return PLANE_CTL_ROTATE_270;
3014         case BIT(DRM_ROTATE_180):
3015                 return PLANE_CTL_ROTATE_180;
3016         case BIT(DRM_ROTATE_270):
3017                 return PLANE_CTL_ROTATE_90;
3018         default:
3019                 MISSING_CASE(rotation);
3020         }
3021
3022         return 0;
3023 }
3024
3025 static void skylake_update_primary_plane(struct drm_plane *plane,
3026                                          const struct intel_crtc_state *crtc_state,
3027                                          const struct intel_plane_state *plane_state)
3028 {
3029         struct drm_device *dev = plane->dev;
3030         struct drm_i915_private *dev_priv = dev->dev_private;
3031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3032         struct drm_framebuffer *fb = plane_state->base.fb;
3033         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3034         int pipe = intel_crtc->pipe;
3035         u32 plane_ctl, stride_div, stride;
3036         u32 tile_height, plane_offset, plane_size;
3037         unsigned int rotation = plane_state->base.rotation;
3038         int x_offset, y_offset;
3039         u32 surf_addr;
3040         int scaler_id = plane_state->scaler_id;
3041         int src_x = plane_state->src.x1 >> 16;
3042         int src_y = plane_state->src.y1 >> 16;
3043         int src_w = drm_rect_width(&plane_state->src) >> 16;
3044         int src_h = drm_rect_height(&plane_state->src) >> 16;
3045         int dst_x = plane_state->dst.x1;
3046         int dst_y = plane_state->dst.y1;
3047         int dst_w = drm_rect_width(&plane_state->dst);
3048         int dst_h = drm_rect_height(&plane_state->dst);
3049
3050         plane_ctl = PLANE_CTL_ENABLE |
3051                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3052                     PLANE_CTL_PIPE_CSC_ENABLE;
3053
3054         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3055         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3056         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3057         plane_ctl |= skl_plane_ctl_rotation(rotation);
3058
3059         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3060                                                fb->pixel_format);
3061         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3062
3063         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3064
3065         if (intel_rotation_90_or_270(rotation)) {
3066                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3067
3068                 /* stride = Surface height in tiles */
3069                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3070                 stride = DIV_ROUND_UP(fb->height, tile_height);
3071                 x_offset = stride * tile_height - src_y - src_h;
3072                 y_offset = src_x;
3073                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3074         } else {
3075                 stride = fb->pitches[0] / stride_div;
3076                 x_offset = src_x;
3077                 y_offset = src_y;
3078                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3079         }
3080         plane_offset = y_offset << 16 | x_offset;
3081
3082         intel_crtc->adjusted_x = x_offset;
3083         intel_crtc->adjusted_y = y_offset;
3084
3085         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3086         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3087         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3088         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3089
3090         if (scaler_id >= 0) {
3091                 uint32_t ps_ctrl = 0;
3092
3093                 WARN_ON(!dst_w || !dst_h);
3094                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3095                         crtc_state->scaler_state.scalers[scaler_id].mode;
3096                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3097                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3098                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3099                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3100                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3101         } else {
3102                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3103         }
3104
3105         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3106
3107         POSTING_READ(PLANE_SURF(pipe, 0));
3108 }
3109
3110 static void skylake_disable_primary_plane(struct drm_plane *primary,
3111                                           struct drm_crtc *crtc)
3112 {
3113         struct drm_device *dev = crtc->dev;
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         int pipe = to_intel_crtc(crtc)->pipe;
3116
3117         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3118         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3119         POSTING_READ(PLANE_SURF(pipe, 0));
3120 }
3121
3122 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3123 static int
3124 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3125                            int x, int y, enum mode_set_atomic state)
3126 {
3127         /* Support for kgdboc is disabled, this needs a major rework. */
3128         DRM_ERROR("legacy panic handler not supported any more.\n");
3129
3130         return -ENODEV;
3131 }
3132
3133 static void intel_complete_page_flips(struct drm_device *dev)
3134 {
3135         struct drm_crtc *crtc;
3136
3137         for_each_crtc(dev, crtc) {
3138                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139                 enum plane plane = intel_crtc->plane;
3140
3141                 intel_prepare_page_flip(dev, plane);
3142                 intel_finish_page_flip_plane(dev, plane);
3143         }
3144 }
3145
3146 static void intel_update_primary_planes(struct drm_device *dev)
3147 {
3148         struct drm_crtc *crtc;
3149
3150         for_each_crtc(dev, crtc) {
3151                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3152                 struct intel_plane_state *plane_state;
3153
3154                 drm_modeset_lock_crtc(crtc, &plane->base);
3155                 plane_state = to_intel_plane_state(plane->base.state);
3156
3157                 if (plane_state->visible)
3158                         plane->update_plane(&plane->base,
3159                                             to_intel_crtc_state(crtc->state),
3160                                             plane_state);
3161
3162                 drm_modeset_unlock_crtc(crtc);
3163         }
3164 }
3165
3166 void intel_prepare_reset(struct drm_device *dev)
3167 {
3168         /* no reset support for gen2 */
3169         if (IS_GEN2(dev))
3170                 return;
3171
3172         /* reset doesn't touch the display */
3173         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3174                 return;
3175
3176         drm_modeset_lock_all(dev);
3177         /*
3178          * Disabling the crtcs gracefully seems nicer. Also the
3179          * g33 docs say we should at least disable all the planes.
3180          */
3181         intel_display_suspend(dev);
3182 }
3183
3184 void intel_finish_reset(struct drm_device *dev)
3185 {
3186         struct drm_i915_private *dev_priv = to_i915(dev);
3187
3188         /*
3189          * Flips in the rings will be nuked by the reset,
3190          * so complete all pending flips so that user space
3191          * will get its events and not get stuck.
3192          */
3193         intel_complete_page_flips(dev);
3194
3195         /* no reset support for gen2 */
3196         if (IS_GEN2(dev))
3197                 return;
3198
3199         /* reset doesn't touch the display */
3200         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3201                 /*
3202                  * Flips in the rings have been nuked by the reset,
3203                  * so update the base address of all primary
3204                  * planes to the the last fb to make sure we're
3205                  * showing the correct fb after a reset.
3206                  *
3207                  * FIXME: Atomic will make this obsolete since we won't schedule
3208                  * CS-based flips (which might get lost in gpu resets) any more.
3209                  */
3210                 intel_update_primary_planes(dev);
3211                 return;
3212         }
3213
3214         /*
3215          * The display has been reset as well,
3216          * so need a full re-initialization.
3217          */
3218         intel_runtime_pm_disable_interrupts(dev_priv);
3219         intel_runtime_pm_enable_interrupts(dev_priv);
3220
3221         intel_modeset_init_hw(dev);
3222
3223         spin_lock_irq(&dev_priv->irq_lock);
3224         if (dev_priv->display.hpd_irq_setup)
3225                 dev_priv->display.hpd_irq_setup(dev);
3226         spin_unlock_irq(&dev_priv->irq_lock);
3227
3228         intel_display_resume(dev);
3229
3230         intel_hpd_init(dev_priv);
3231
3232         drm_modeset_unlock_all(dev);
3233 }
3234
3235 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3236 {
3237         struct drm_device *dev = crtc->dev;
3238         struct drm_i915_private *dev_priv = dev->dev_private;
3239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240         bool pending;
3241
3242         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3243             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3244                 return false;
3245
3246         spin_lock_irq(&dev->event_lock);
3247         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3248         spin_unlock_irq(&dev->event_lock);
3249
3250         return pending;
3251 }
3252
3253 static void intel_update_pipe_config(struct intel_crtc *crtc,
3254                                      struct intel_crtc_state *old_crtc_state)
3255 {
3256         struct drm_device *dev = crtc->base.dev;
3257         struct drm_i915_private *dev_priv = dev->dev_private;
3258         struct intel_crtc_state *pipe_config =
3259                 to_intel_crtc_state(crtc->base.state);
3260
3261         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3262         crtc->base.mode = crtc->base.state->mode;
3263
3264         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3265                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3266                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3267
3268         if (HAS_DDI(dev))
3269                 intel_color_set_csc(&crtc->base);
3270
3271         /*
3272          * Update pipe size and adjust fitter if needed: the reason for this is
3273          * that in compute_mode_changes we check the native mode (not the pfit
3274          * mode) to see if we can flip rather than do a full mode set. In the
3275          * fastboot case, we'll flip, but if we don't update the pipesrc and
3276          * pfit state, we'll end up with a big fb scanned out into the wrong
3277          * sized surface.
3278          */
3279
3280         I915_WRITE(PIPESRC(crtc->pipe),
3281                    ((pipe_config->pipe_src_w - 1) << 16) |
3282                    (pipe_config->pipe_src_h - 1));
3283
3284         /* on skylake this is done by detaching scalers */
3285         if (INTEL_INFO(dev)->gen >= 9) {
3286                 skl_detach_scalers(crtc);
3287
3288                 if (pipe_config->pch_pfit.enabled)
3289                         skylake_pfit_enable(crtc);
3290         } else if (HAS_PCH_SPLIT(dev)) {
3291                 if (pipe_config->pch_pfit.enabled)
3292                         ironlake_pfit_enable(crtc);
3293                 else if (old_crtc_state->pch_pfit.enabled)
3294                         ironlake_pfit_disable(crtc, true);
3295         }
3296 }
3297
3298 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3299 {
3300         struct drm_device *dev = crtc->dev;
3301         struct drm_i915_private *dev_priv = dev->dev_private;
3302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3303         int pipe = intel_crtc->pipe;
3304         i915_reg_t reg;
3305         u32 temp;
3306
3307         /* enable normal train */
3308         reg = FDI_TX_CTL(pipe);
3309         temp = I915_READ(reg);
3310         if (IS_IVYBRIDGE(dev)) {
3311                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3312                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3313         } else {
3314                 temp &= ~FDI_LINK_TRAIN_NONE;
3315                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3316         }
3317         I915_WRITE(reg, temp);
3318
3319         reg = FDI_RX_CTL(pipe);
3320         temp = I915_READ(reg);
3321         if (HAS_PCH_CPT(dev)) {
3322                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3323                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3324         } else {
3325                 temp &= ~FDI_LINK_TRAIN_NONE;
3326                 temp |= FDI_LINK_TRAIN_NONE;
3327         }
3328         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3329
3330         /* wait one idle pattern time */
3331         POSTING_READ(reg);
3332         udelay(1000);
3333
3334         /* IVB wants error correction enabled */
3335         if (IS_IVYBRIDGE(dev))
3336                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3337                            FDI_FE_ERRC_ENABLE);
3338 }
3339
3340 /* The FDI link training functions for ILK/Ibexpeak. */
3341 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         int pipe = intel_crtc->pipe;
3347         i915_reg_t reg;
3348         u32 temp, tries;
3349
3350         /* FDI needs bits from pipe first */
3351         assert_pipe_enabled(dev_priv, pipe);
3352
3353         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3354            for train result */
3355         reg = FDI_RX_IMR(pipe);
3356         temp = I915_READ(reg);
3357         temp &= ~FDI_RX_SYMBOL_LOCK;
3358         temp &= ~FDI_RX_BIT_LOCK;
3359         I915_WRITE(reg, temp);
3360         I915_READ(reg);
3361         udelay(150);
3362
3363         /* enable CPU FDI TX and PCH FDI RX */
3364         reg = FDI_TX_CTL(pipe);
3365         temp = I915_READ(reg);
3366         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3367         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3368         temp &= ~FDI_LINK_TRAIN_NONE;
3369         temp |= FDI_LINK_TRAIN_PATTERN_1;
3370         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3371
3372         reg = FDI_RX_CTL(pipe);
3373         temp = I915_READ(reg);
3374         temp &= ~FDI_LINK_TRAIN_NONE;
3375         temp |= FDI_LINK_TRAIN_PATTERN_1;
3376         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3377
3378         POSTING_READ(reg);
3379         udelay(150);
3380
3381         /* Ironlake workaround, enable clock pointer after FDI enable*/
3382         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3383         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3384                    FDI_RX_PHASE_SYNC_POINTER_EN);
3385
3386         reg = FDI_RX_IIR(pipe);
3387         for (tries = 0; tries < 5; tries++) {
3388                 temp = I915_READ(reg);
3389                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3390
3391                 if ((temp & FDI_RX_BIT_LOCK)) {
3392                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3393                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3394                         break;
3395                 }
3396         }
3397         if (tries == 5)
3398                 DRM_ERROR("FDI train 1 fail!\n");
3399
3400         /* Train 2 */
3401         reg = FDI_TX_CTL(pipe);
3402         temp = I915_READ(reg);
3403         temp &= ~FDI_LINK_TRAIN_NONE;
3404         temp |= FDI_LINK_TRAIN_PATTERN_2;
3405         I915_WRITE(reg, temp);
3406
3407         reg = FDI_RX_CTL(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_LINK_TRAIN_NONE;
3410         temp |= FDI_LINK_TRAIN_PATTERN_2;
3411         I915_WRITE(reg, temp);
3412
3413         POSTING_READ(reg);
3414         udelay(150);
3415
3416         reg = FDI_RX_IIR(pipe);
3417         for (tries = 0; tries < 5; tries++) {
3418                 temp = I915_READ(reg);
3419                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3420
3421                 if (temp & FDI_RX_SYMBOL_LOCK) {
3422                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3423                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3424                         break;
3425                 }
3426         }
3427         if (tries == 5)
3428                 DRM_ERROR("FDI train 2 fail!\n");
3429
3430         DRM_DEBUG_KMS("FDI train done\n");
3431
3432 }
3433
3434 static const int snb_b_fdi_train_param[] = {
3435         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3436         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3437         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3438         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3439 };
3440
3441 /* The FDI link training functions for SNB/Cougarpoint. */
3442 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3443 {
3444         struct drm_device *dev = crtc->dev;
3445         struct drm_i915_private *dev_priv = dev->dev_private;
3446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447         int pipe = intel_crtc->pipe;
3448         i915_reg_t reg;
3449         u32 temp, i, retry;
3450
3451         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3452            for train result */
3453         reg = FDI_RX_IMR(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_RX_SYMBOL_LOCK;
3456         temp &= ~FDI_RX_BIT_LOCK;
3457         I915_WRITE(reg, temp);
3458
3459         POSTING_READ(reg);
3460         udelay(150);
3461
3462         /* enable CPU FDI TX and PCH FDI RX */
3463         reg = FDI_TX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467         temp &= ~FDI_LINK_TRAIN_NONE;
3468         temp |= FDI_LINK_TRAIN_PATTERN_1;
3469         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3470         /* SNB-B */
3471         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3472         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3473
3474         I915_WRITE(FDI_RX_MISC(pipe),
3475                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3476
3477         reg = FDI_RX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         if (HAS_PCH_CPT(dev)) {
3480                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3481                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3482         } else {
3483                 temp &= ~FDI_LINK_TRAIN_NONE;
3484                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3485         }
3486         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3487
3488         POSTING_READ(reg);
3489         udelay(150);
3490
3491         for (i = 0; i < 4; i++) {
3492                 reg = FDI_TX_CTL(pipe);
3493                 temp = I915_READ(reg);
3494                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3495                 temp |= snb_b_fdi_train_param[i];
3496                 I915_WRITE(reg, temp);
3497
3498                 POSTING_READ(reg);
3499                 udelay(500);
3500
3501                 for (retry = 0; retry < 5; retry++) {
3502                         reg = FDI_RX_IIR(pipe);
3503                         temp = I915_READ(reg);
3504                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3505                         if (temp & FDI_RX_BIT_LOCK) {
3506                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3507                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3508                                 break;
3509                         }
3510                         udelay(50);
3511                 }
3512                 if (retry < 5)
3513                         break;
3514         }
3515         if (i == 4)
3516                 DRM_ERROR("FDI train 1 fail!\n");
3517
3518         /* Train 2 */
3519         reg = FDI_TX_CTL(pipe);
3520         temp = I915_READ(reg);
3521         temp &= ~FDI_LINK_TRAIN_NONE;
3522         temp |= FDI_LINK_TRAIN_PATTERN_2;
3523         if (IS_GEN6(dev)) {
3524                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3525                 /* SNB-B */
3526                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3527         }
3528         I915_WRITE(reg, temp);
3529
3530         reg = FDI_RX_CTL(pipe);
3531         temp = I915_READ(reg);
3532         if (HAS_PCH_CPT(dev)) {
3533                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3534                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3535         } else {
3536                 temp &= ~FDI_LINK_TRAIN_NONE;
3537                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3538         }
3539         I915_WRITE(reg, temp);
3540
3541         POSTING_READ(reg);
3542         udelay(150);
3543
3544         for (i = 0; i < 4; i++) {
3545                 reg = FDI_TX_CTL(pipe);
3546                 temp = I915_READ(reg);
3547                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548                 temp |= snb_b_fdi_train_param[i];
3549                 I915_WRITE(reg, temp);
3550
3551                 POSTING_READ(reg);
3552                 udelay(500);
3553
3554                 for (retry = 0; retry < 5; retry++) {
3555                         reg = FDI_RX_IIR(pipe);
3556                         temp = I915_READ(reg);
3557                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3558                         if (temp & FDI_RX_SYMBOL_LOCK) {
3559                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3560                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3561                                 break;
3562                         }
3563                         udelay(50);
3564                 }
3565                 if (retry < 5)
3566                         break;
3567         }
3568         if (i == 4)
3569                 DRM_ERROR("FDI train 2 fail!\n");
3570
3571         DRM_DEBUG_KMS("FDI train done.\n");
3572 }
3573
3574 /* Manual link training for Ivy Bridge A0 parts */
3575 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580         int pipe = intel_crtc->pipe;
3581         i915_reg_t reg;
3582         u32 temp, i, j;
3583
3584         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3585            for train result */
3586         reg = FDI_RX_IMR(pipe);
3587         temp = I915_READ(reg);
3588         temp &= ~FDI_RX_SYMBOL_LOCK;
3589         temp &= ~FDI_RX_BIT_LOCK;
3590         I915_WRITE(reg, temp);
3591
3592         POSTING_READ(reg);
3593         udelay(150);
3594
3595         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3596                       I915_READ(FDI_RX_IIR(pipe)));
3597
3598         /* Try each vswing and preemphasis setting twice before moving on */
3599         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3600                 /* disable first in case we need to retry */
3601                 reg = FDI_TX_CTL(pipe);
3602                 temp = I915_READ(reg);
3603                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3604                 temp &= ~FDI_TX_ENABLE;
3605                 I915_WRITE(reg, temp);
3606
3607                 reg = FDI_RX_CTL(pipe);
3608                 temp = I915_READ(reg);
3609                 temp &= ~FDI_LINK_TRAIN_AUTO;
3610                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3611                 temp &= ~FDI_RX_ENABLE;
3612                 I915_WRITE(reg, temp);
3613
3614                 /* enable CPU FDI TX and PCH FDI RX */
3615                 reg = FDI_TX_CTL(pipe);
3616                 temp = I915_READ(reg);
3617                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3618                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3619                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3620                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3621                 temp |= snb_b_fdi_train_param[j/2];
3622                 temp |= FDI_COMPOSITE_SYNC;
3623                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3624
3625                 I915_WRITE(FDI_RX_MISC(pipe),
3626                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3627
3628                 reg = FDI_RX_CTL(pipe);
3629                 temp = I915_READ(reg);
3630                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3631                 temp |= FDI_COMPOSITE_SYNC;
3632                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3633
3634                 POSTING_READ(reg);
3635                 udelay(1); /* should be 0.5us */
3636
3637                 for (i = 0; i < 4; i++) {
3638                         reg = FDI_RX_IIR(pipe);
3639                         temp = I915_READ(reg);
3640                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3641
3642                         if (temp & FDI_RX_BIT_LOCK ||
3643                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3644                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3645                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3646                                               i);
3647                                 break;
3648                         }
3649                         udelay(1); /* should be 0.5us */
3650                 }
3651                 if (i == 4) {
3652                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3653                         continue;
3654                 }
3655
3656                 /* Train 2 */
3657                 reg = FDI_TX_CTL(pipe);
3658                 temp = I915_READ(reg);
3659                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3660                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3661                 I915_WRITE(reg, temp);
3662
3663                 reg = FDI_RX_CTL(pipe);
3664                 temp = I915_READ(reg);
3665                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3666                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3667                 I915_WRITE(reg, temp);
3668
3669                 POSTING_READ(reg);
3670                 udelay(2); /* should be 1.5us */
3671
3672                 for (i = 0; i < 4; i++) {
3673                         reg = FDI_RX_IIR(pipe);
3674                         temp = I915_READ(reg);
3675                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3676
3677                         if (temp & FDI_RX_SYMBOL_LOCK ||
3678                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3679                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3680                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3681                                               i);
3682                                 goto train_done;
3683                         }
3684                         udelay(2); /* should be 1.5us */
3685                 }
3686                 if (i == 4)
3687                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3688         }
3689
3690 train_done:
3691         DRM_DEBUG_KMS("FDI train done.\n");
3692 }
3693
3694 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3695 {
3696         struct drm_device *dev = intel_crtc->base.dev;
3697         struct drm_i915_private *dev_priv = dev->dev_private;
3698         int pipe = intel_crtc->pipe;
3699         i915_reg_t reg;
3700         u32 temp;
3701
3702         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3703         reg = FDI_RX_CTL(pipe);
3704         temp = I915_READ(reg);
3705         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3706         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3707         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3708         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3709
3710         POSTING_READ(reg);
3711         udelay(200);
3712
3713         /* Switch from Rawclk to PCDclk */
3714         temp = I915_READ(reg);
3715         I915_WRITE(reg, temp | FDI_PCDCLK);
3716
3717         POSTING_READ(reg);
3718         udelay(200);
3719
3720         /* Enable CPU FDI TX PLL, always on for Ironlake */
3721         reg = FDI_TX_CTL(pipe);
3722         temp = I915_READ(reg);
3723         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3724                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3725
3726                 POSTING_READ(reg);
3727                 udelay(100);
3728         }
3729 }
3730
3731 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3732 {
3733         struct drm_device *dev = intel_crtc->base.dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         int pipe = intel_crtc->pipe;
3736         i915_reg_t reg;
3737         u32 temp;
3738
3739         /* Switch from PCDclk to Rawclk */
3740         reg = FDI_RX_CTL(pipe);
3741         temp = I915_READ(reg);
3742         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3743
3744         /* Disable CPU FDI TX PLL */
3745         reg = FDI_TX_CTL(pipe);
3746         temp = I915_READ(reg);
3747         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3748
3749         POSTING_READ(reg);
3750         udelay(100);
3751
3752         reg = FDI_RX_CTL(pipe);
3753         temp = I915_READ(reg);
3754         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3755
3756         /* Wait for the clocks to turn off. */
3757         POSTING_READ(reg);
3758         udelay(100);
3759 }
3760
3761 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3762 {
3763         struct drm_device *dev = crtc->dev;
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766         int pipe = intel_crtc->pipe;
3767         i915_reg_t reg;
3768         u32 temp;
3769
3770         /* disable CPU FDI tx and PCH FDI rx */
3771         reg = FDI_TX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3774         POSTING_READ(reg);
3775
3776         reg = FDI_RX_CTL(pipe);
3777         temp = I915_READ(reg);
3778         temp &= ~(0x7 << 16);
3779         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3780         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3781
3782         POSTING_READ(reg);
3783         udelay(100);
3784
3785         /* Ironlake workaround, disable clock pointer after downing FDI */
3786         if (HAS_PCH_IBX(dev))
3787                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3788
3789         /* still set train pattern 1 */
3790         reg = FDI_TX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         temp &= ~FDI_LINK_TRAIN_NONE;
3793         temp |= FDI_LINK_TRAIN_PATTERN_1;
3794         I915_WRITE(reg, temp);
3795
3796         reg = FDI_RX_CTL(pipe);
3797         temp = I915_READ(reg);
3798         if (HAS_PCH_CPT(dev)) {
3799                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3800                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3801         } else {
3802                 temp &= ~FDI_LINK_TRAIN_NONE;
3803                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3804         }
3805         /* BPC in FDI rx is consistent with that in PIPECONF */
3806         temp &= ~(0x07 << 16);
3807         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3808         I915_WRITE(reg, temp);
3809
3810         POSTING_READ(reg);
3811         udelay(100);
3812 }
3813
3814 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3815 {
3816         struct intel_crtc *crtc;
3817
3818         /* Note that we don't need to be called with mode_config.lock here
3819          * as our list of CRTC objects is static for the lifetime of the
3820          * device and so cannot disappear as we iterate. Similarly, we can
3821          * happily treat the predicates as racy, atomic checks as userspace
3822          * cannot claim and pin a new fb without at least acquring the
3823          * struct_mutex and so serialising with us.
3824          */
3825         for_each_intel_crtc(dev, crtc) {
3826                 if (atomic_read(&crtc->unpin_work_count) == 0)
3827                         continue;
3828
3829                 if (crtc->unpin_work)
3830                         intel_wait_for_vblank(dev, crtc->pipe);
3831
3832                 return true;
3833         }
3834
3835         return false;
3836 }
3837
3838 static void page_flip_completed(struct intel_crtc *intel_crtc)
3839 {
3840         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3841         struct intel_unpin_work *work = intel_crtc->unpin_work;
3842
3843         /* ensure that the unpin work is consistent wrt ->pending. */
3844         smp_rmb();
3845         intel_crtc->unpin_work = NULL;
3846
3847         if (work->event)
3848                 drm_send_vblank_event(intel_crtc->base.dev,
3849                                       intel_crtc->pipe,
3850                                       work->event);
3851
3852         drm_crtc_vblank_put(&intel_crtc->base);
3853
3854         wake_up_all(&dev_priv->pending_flip_queue);
3855         queue_work(dev_priv->wq, &work->work);
3856
3857         trace_i915_flip_complete(intel_crtc->plane,
3858                                  work->pending_flip_obj);
3859 }
3860
3861 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3862 {
3863         struct drm_device *dev = crtc->dev;
3864         struct drm_i915_private *dev_priv = dev->dev_private;
3865         long ret;
3866
3867         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3868
3869         ret = wait_event_interruptible_timeout(
3870                                         dev_priv->pending_flip_queue,
3871                                         !intel_crtc_has_pending_flip(crtc),
3872                                         60*HZ);
3873
3874         if (ret < 0)
3875                 return ret;
3876
3877         if (ret == 0) {
3878                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3879
3880                 spin_lock_irq(&dev->event_lock);
3881                 if (intel_crtc->unpin_work) {
3882                         WARN_ONCE(1, "Removing stuck page flip\n");
3883                         page_flip_completed(intel_crtc);
3884                 }
3885                 spin_unlock_irq(&dev->event_lock);
3886         }
3887
3888         return 0;
3889 }
3890
3891 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3892 {
3893         u32 temp;
3894
3895         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3896
3897         mutex_lock(&dev_priv->sb_lock);
3898
3899         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3900         temp |= SBI_SSCCTL_DISABLE;
3901         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3902
3903         mutex_unlock(&dev_priv->sb_lock);
3904 }
3905
3906 /* Program iCLKIP clock to the desired frequency */
3907 static void lpt_program_iclkip(struct drm_crtc *crtc)
3908 {
3909         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3910         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3911         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3912         u32 temp;
3913
3914         lpt_disable_iclkip(dev_priv);
3915
3916         /* The iCLK virtual clock root frequency is in MHz,
3917          * but the adjusted_mode->crtc_clock in in KHz. To get the
3918          * divisors, it is necessary to divide one by another, so we
3919          * convert the virtual clock precision to KHz here for higher
3920          * precision.
3921          */
3922         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3923                 u32 iclk_virtual_root_freq = 172800 * 1000;
3924                 u32 iclk_pi_range = 64;
3925                 u32 desired_divisor;
3926
3927                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3928                                                     clock << auxdiv);
3929                 divsel = (desired_divisor / iclk_pi_range) - 2;
3930                 phaseinc = desired_divisor % iclk_pi_range;
3931
3932                 /*
3933                  * Near 20MHz is a corner case which is
3934                  * out of range for the 7-bit divisor
3935                  */
3936                 if (divsel <= 0x7f)
3937                         break;
3938         }
3939
3940         /* This should not happen with any sane values */
3941         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3942                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3943         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3944                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3945
3946         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3947                         clock,
3948                         auxdiv,
3949                         divsel,
3950                         phasedir,
3951                         phaseinc);
3952
3953         mutex_lock(&dev_priv->sb_lock);
3954
3955         /* Program SSCDIVINTPHASE6 */
3956         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3957         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3958         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3959         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3960         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3961         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3962         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3963         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3964
3965         /* Program SSCAUXDIV */
3966         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3967         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3968         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3969         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3970
3971         /* Enable modulator and associated divider */
3972         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3973         temp &= ~SBI_SSCCTL_DISABLE;
3974         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3975
3976         mutex_unlock(&dev_priv->sb_lock);
3977
3978         /* Wait for initialization time */
3979         udelay(24);
3980
3981         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3982 }
3983
3984 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3985 {
3986         u32 divsel, phaseinc, auxdiv;
3987         u32 iclk_virtual_root_freq = 172800 * 1000;
3988         u32 iclk_pi_range = 64;
3989         u32 desired_divisor;
3990         u32 temp;
3991
3992         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3993                 return 0;
3994
3995         mutex_lock(&dev_priv->sb_lock);
3996
3997         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3998         if (temp & SBI_SSCCTL_DISABLE) {
3999                 mutex_unlock(&dev_priv->sb_lock);
4000                 return 0;
4001         }
4002
4003         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4004         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4005                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4006         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4007                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4008
4009         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4010         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4011                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4012
4013         mutex_unlock(&dev_priv->sb_lock);
4014
4015         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4016
4017         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4018                                  desired_divisor << auxdiv);
4019 }
4020
4021 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4022                                                 enum pipe pch_transcoder)
4023 {
4024         struct drm_device *dev = crtc->base.dev;
4025         struct drm_i915_private *dev_priv = dev->dev_private;
4026         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4027
4028         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4029                    I915_READ(HTOTAL(cpu_transcoder)));
4030         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4031                    I915_READ(HBLANK(cpu_transcoder)));
4032         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4033                    I915_READ(HSYNC(cpu_transcoder)));
4034
4035         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4036                    I915_READ(VTOTAL(cpu_transcoder)));
4037         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4038                    I915_READ(VBLANK(cpu_transcoder)));
4039         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4040                    I915_READ(VSYNC(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4042                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4043 }
4044
4045 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4046 {
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         uint32_t temp;
4049
4050         temp = I915_READ(SOUTH_CHICKEN1);
4051         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4052                 return;
4053
4054         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4055         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4056
4057         temp &= ~FDI_BC_BIFURCATION_SELECT;
4058         if (enable)
4059                 temp |= FDI_BC_BIFURCATION_SELECT;
4060
4061         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4062         I915_WRITE(SOUTH_CHICKEN1, temp);
4063         POSTING_READ(SOUTH_CHICKEN1);
4064 }
4065
4066 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4067 {
4068         struct drm_device *dev = intel_crtc->base.dev;
4069
4070         switch (intel_crtc->pipe) {
4071         case PIPE_A:
4072                 break;
4073         case PIPE_B:
4074                 if (intel_crtc->config->fdi_lanes > 2)
4075                         cpt_set_fdi_bc_bifurcation(dev, false);
4076                 else
4077                         cpt_set_fdi_bc_bifurcation(dev, true);
4078
4079                 break;
4080         case PIPE_C:
4081                 cpt_set_fdi_bc_bifurcation(dev, true);
4082
4083                 break;
4084         default:
4085                 BUG();
4086         }
4087 }
4088
4089 /* Return which DP Port should be selected for Transcoder DP control */
4090 static enum port
4091 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4092 {
4093         struct drm_device *dev = crtc->dev;
4094         struct intel_encoder *encoder;
4095
4096         for_each_encoder_on_crtc(dev, crtc, encoder) {
4097                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4098                     encoder->type == INTEL_OUTPUT_EDP)
4099                         return enc_to_dig_port(&encoder->base)->port;
4100         }
4101
4102         return -1;
4103 }
4104
4105 /*
4106  * Enable PCH resources required for PCH ports:
4107  *   - PCH PLLs
4108  *   - FDI training & RX/TX
4109  *   - update transcoder timings
4110  *   - DP transcoding bits
4111  *   - transcoder
4112  */
4113 static void ironlake_pch_enable(struct drm_crtc *crtc)
4114 {
4115         struct drm_device *dev = crtc->dev;
4116         struct drm_i915_private *dev_priv = dev->dev_private;
4117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4118         int pipe = intel_crtc->pipe;
4119         u32 temp;
4120
4121         assert_pch_transcoder_disabled(dev_priv, pipe);
4122
4123         if (IS_IVYBRIDGE(dev))
4124                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4125
4126         /* Write the TU size bits before fdi link training, so that error
4127          * detection works. */
4128         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4129                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4130
4131         /*
4132          * Sometimes spurious CPU pipe underruns happen during FDI
4133          * training, at least with VGA+HDMI cloning. Suppress them.
4134          */
4135         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4136
4137         /* For PCH output, training FDI link */
4138         dev_priv->display.fdi_link_train(crtc);
4139
4140         /* We need to program the right clock selection before writing the pixel
4141          * mutliplier into the DPLL. */
4142         if (HAS_PCH_CPT(dev)) {
4143                 u32 sel;
4144
4145                 temp = I915_READ(PCH_DPLL_SEL);
4146                 temp |= TRANS_DPLL_ENABLE(pipe);
4147                 sel = TRANS_DPLLB_SEL(pipe);
4148                 if (intel_crtc->config->shared_dpll ==
4149                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4150                         temp |= sel;
4151                 else
4152                         temp &= ~sel;
4153                 I915_WRITE(PCH_DPLL_SEL, temp);
4154         }
4155
4156         /* XXX: pch pll's can be enabled any time before we enable the PCH
4157          * transcoder, and we actually should do this to not upset any PCH
4158          * transcoder that already use the clock when we share it.
4159          *
4160          * Note that enable_shared_dpll tries to do the right thing, but
4161          * get_shared_dpll unconditionally resets the pll - we need that to have
4162          * the right LVDS enable sequence. */
4163         intel_enable_shared_dpll(intel_crtc);
4164
4165         /* set transcoder timing, panel must allow it */
4166         assert_panel_unlocked(dev_priv, pipe);
4167         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4168
4169         intel_fdi_normal_train(crtc);
4170
4171         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4172
4173         /* For PCH DP, enable TRANS_DP_CTL */
4174         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4175                 const struct drm_display_mode *adjusted_mode =
4176                         &intel_crtc->config->base.adjusted_mode;
4177                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4178                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4179                 temp = I915_READ(reg);
4180                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4181                           TRANS_DP_SYNC_MASK |
4182                           TRANS_DP_BPC_MASK);
4183                 temp |= TRANS_DP_OUTPUT_ENABLE;
4184                 temp |= bpc << 9; /* same format but at 11:9 */
4185
4186                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4187                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4188                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4189                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4190
4191                 switch (intel_trans_dp_port_sel(crtc)) {
4192                 case PORT_B:
4193                         temp |= TRANS_DP_PORT_SEL_B;
4194                         break;
4195                 case PORT_C:
4196                         temp |= TRANS_DP_PORT_SEL_C;
4197                         break;
4198                 case PORT_D:
4199                         temp |= TRANS_DP_PORT_SEL_D;
4200                         break;
4201                 default:
4202                         BUG();
4203                 }
4204
4205                 I915_WRITE(reg, temp);
4206         }
4207
4208         ironlake_enable_pch_transcoder(dev_priv, pipe);
4209 }
4210
4211 static void lpt_pch_enable(struct drm_crtc *crtc)
4212 {
4213         struct drm_device *dev = crtc->dev;
4214         struct drm_i915_private *dev_priv = dev->dev_private;
4215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4217
4218         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4219
4220         lpt_program_iclkip(crtc);
4221
4222         /* Set transcoder timing. */
4223         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4224
4225         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4226 }
4227
4228 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4229 {
4230         struct drm_i915_private *dev_priv = dev->dev_private;
4231         i915_reg_t dslreg = PIPEDSL(pipe);
4232         u32 temp;
4233
4234         temp = I915_READ(dslreg);
4235         udelay(500);
4236         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4237                 if (wait_for(I915_READ(dslreg) != temp, 5))
4238                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4239         }
4240 }
4241
4242 static int
4243 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4244                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4245                   int src_w, int src_h, int dst_w, int dst_h)
4246 {
4247         struct intel_crtc_scaler_state *scaler_state =
4248                 &crtc_state->scaler_state;
4249         struct intel_crtc *intel_crtc =
4250                 to_intel_crtc(crtc_state->base.crtc);
4251         int need_scaling;
4252
4253         need_scaling = intel_rotation_90_or_270(rotation) ?
4254                 (src_h != dst_w || src_w != dst_h):
4255                 (src_w != dst_w || src_h != dst_h);
4256
4257         /*
4258          * if plane is being disabled or scaler is no more required or force detach
4259          *  - free scaler binded to this plane/crtc
4260          *  - in order to do this, update crtc->scaler_usage
4261          *
4262          * Here scaler state in crtc_state is set free so that
4263          * scaler can be assigned to other user. Actual register
4264          * update to free the scaler is done in plane/panel-fit programming.
4265          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4266          */
4267         if (force_detach || !need_scaling) {
4268                 if (*scaler_id >= 0) {
4269                         scaler_state->scaler_users &= ~(1 << scaler_user);
4270                         scaler_state->scalers[*scaler_id].in_use = 0;
4271
4272                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4273                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4274                                 intel_crtc->pipe, scaler_user, *scaler_id,
4275                                 scaler_state->scaler_users);
4276                         *scaler_id = -1;
4277                 }
4278                 return 0;
4279         }
4280
4281         /* range checks */
4282         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4283                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4284
4285                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4286                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4287                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4288                         "size is out of scaler range\n",
4289                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4290                 return -EINVAL;
4291         }
4292
4293         /* mark this plane as a scaler user in crtc_state */
4294         scaler_state->scaler_users |= (1 << scaler_user);
4295         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4296                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4297                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4298                 scaler_state->scaler_users);
4299
4300         return 0;
4301 }
4302
4303 /**
4304  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4305  *
4306  * @state: crtc's scaler state
4307  *
4308  * Return
4309  *     0 - scaler_usage updated successfully
4310  *    error - requested scaling cannot be supported or other error condition
4311  */
4312 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4313 {
4314         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4315         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4316
4317         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4318                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4319
4320         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4321                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4322                 state->pipe_src_w, state->pipe_src_h,
4323                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4324 }
4325
4326 /**
4327  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4328  *
4329  * @state: crtc's scaler state
4330  * @plane_state: atomic plane state to update
4331  *
4332  * Return
4333  *     0 - scaler_usage updated successfully
4334  *    error - requested scaling cannot be supported or other error condition
4335  */
4336 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4337                                    struct intel_plane_state *plane_state)
4338 {
4339
4340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4341         struct intel_plane *intel_plane =
4342                 to_intel_plane(plane_state->base.plane);
4343         struct drm_framebuffer *fb = plane_state->base.fb;
4344         int ret;
4345
4346         bool force_detach = !fb || !plane_state->visible;
4347
4348         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4349                       intel_plane->base.base.id, intel_crtc->pipe,
4350                       drm_plane_index(&intel_plane->base));
4351
4352         ret = skl_update_scaler(crtc_state, force_detach,
4353                                 drm_plane_index(&intel_plane->base),
4354                                 &plane_state->scaler_id,
4355                                 plane_state->base.rotation,
4356                                 drm_rect_width(&plane_state->src) >> 16,
4357                                 drm_rect_height(&plane_state->src) >> 16,
4358                                 drm_rect_width(&plane_state->dst),
4359                                 drm_rect_height(&plane_state->dst));
4360
4361         if (ret || plane_state->scaler_id < 0)
4362                 return ret;
4363
4364         /* check colorkey */
4365         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4366                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4367                               intel_plane->base.base.id);
4368                 return -EINVAL;
4369         }
4370
4371         /* Check src format */
4372         switch (fb->pixel_format) {
4373         case DRM_FORMAT_RGB565:
4374         case DRM_FORMAT_XBGR8888:
4375         case DRM_FORMAT_XRGB8888:
4376         case DRM_FORMAT_ABGR8888:
4377         case DRM_FORMAT_ARGB8888:
4378         case DRM_FORMAT_XRGB2101010:
4379         case DRM_FORMAT_XBGR2101010:
4380         case DRM_FORMAT_YUYV:
4381         case DRM_FORMAT_YVYU:
4382         case DRM_FORMAT_UYVY:
4383         case DRM_FORMAT_VYUY:
4384                 break;
4385         default:
4386                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4387                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4388                 return -EINVAL;
4389         }
4390
4391         return 0;
4392 }
4393
4394 static void skylake_scaler_disable(struct intel_crtc *crtc)
4395 {
4396         int i;
4397
4398         for (i = 0; i < crtc->num_scalers; i++)
4399                 skl_detach_scaler(crtc, i);
4400 }
4401
4402 static void skylake_pfit_enable(struct intel_crtc *crtc)
4403 {
4404         struct drm_device *dev = crtc->base.dev;
4405         struct drm_i915_private *dev_priv = dev->dev_private;
4406         int pipe = crtc->pipe;
4407         struct intel_crtc_scaler_state *scaler_state =
4408                 &crtc->config->scaler_state;
4409
4410         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4411
4412         if (crtc->config->pch_pfit.enabled) {
4413                 int id;
4414
4415                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4416                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4417                         return;
4418                 }
4419
4420                 id = scaler_state->scaler_id;
4421                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4422                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4423                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4424                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4425
4426                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4427         }
4428 }
4429
4430 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4431 {
4432         struct drm_device *dev = crtc->base.dev;
4433         struct drm_i915_private *dev_priv = dev->dev_private;
4434         int pipe = crtc->pipe;
4435
4436         if (crtc->config->pch_pfit.enabled) {
4437                 /* Force use of hard-coded filter coefficients
4438                  * as some pre-programmed values are broken,
4439                  * e.g. x201.
4440                  */
4441                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4442                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4443                                                  PF_PIPE_SEL_IVB(pipe));
4444                 else
4445                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4446                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4447                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4448         }
4449 }
4450
4451 void hsw_enable_ips(struct intel_crtc *crtc)
4452 {
4453         struct drm_device *dev = crtc->base.dev;
4454         struct drm_i915_private *dev_priv = dev->dev_private;
4455
4456         if (!crtc->config->ips_enabled)
4457                 return;
4458
4459         /* We can only enable IPS after we enable a plane and wait for a vblank */
4460         intel_wait_for_vblank(dev, crtc->pipe);
4461
4462         assert_plane_enabled(dev_priv, crtc->plane);
4463         if (IS_BROADWELL(dev)) {
4464                 mutex_lock(&dev_priv->rps.hw_lock);
4465                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4466                 mutex_unlock(&dev_priv->rps.hw_lock);
4467                 /* Quoting Art Runyan: "its not safe to expect any particular
4468                  * value in IPS_CTL bit 31 after enabling IPS through the
4469                  * mailbox." Moreover, the mailbox may return a bogus state,
4470                  * so we need to just enable it and continue on.
4471                  */
4472         } else {
4473                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4474                 /* The bit only becomes 1 in the next vblank, so this wait here
4475                  * is essentially intel_wait_for_vblank. If we don't have this
4476                  * and don't wait for vblanks until the end of crtc_enable, then
4477                  * the HW state readout code will complain that the expected
4478                  * IPS_CTL value is not the one we read. */
4479                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4480                         DRM_ERROR("Timed out waiting for IPS enable\n");
4481         }
4482 }
4483
4484 void hsw_disable_ips(struct intel_crtc *crtc)
4485 {
4486         struct drm_device *dev = crtc->base.dev;
4487         struct drm_i915_private *dev_priv = dev->dev_private;
4488
4489         if (!crtc->config->ips_enabled)
4490                 return;
4491
4492         assert_plane_enabled(dev_priv, crtc->plane);
4493         if (IS_BROADWELL(dev)) {
4494                 mutex_lock(&dev_priv->rps.hw_lock);
4495                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4496                 mutex_unlock(&dev_priv->rps.hw_lock);
4497                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4498                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4499                         DRM_ERROR("Timed out waiting for IPS disable\n");
4500         } else {
4501                 I915_WRITE(IPS_CTL, 0);
4502                 POSTING_READ(IPS_CTL);
4503         }
4504
4505         /* We need to wait for a vblank before we can disable the plane. */
4506         intel_wait_for_vblank(dev, crtc->pipe);
4507 }
4508
4509 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4510 {
4511         if (intel_crtc->overlay) {
4512                 struct drm_device *dev = intel_crtc->base.dev;
4513                 struct drm_i915_private *dev_priv = dev->dev_private;
4514
4515                 mutex_lock(&dev->struct_mutex);
4516                 dev_priv->mm.interruptible = false;
4517                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4518                 dev_priv->mm.interruptible = true;
4519                 mutex_unlock(&dev->struct_mutex);
4520         }
4521
4522         /* Let userspace switch the overlay on again. In most cases userspace
4523          * has to recompute where to put it anyway.
4524          */
4525 }
4526
4527 /**
4528  * intel_post_enable_primary - Perform operations after enabling primary plane
4529  * @crtc: the CRTC whose primary plane was just enabled
4530  *
4531  * Performs potentially sleeping operations that must be done after the primary
4532  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4533  * called due to an explicit primary plane update, or due to an implicit
4534  * re-enable that is caused when a sprite plane is updated to no longer
4535  * completely hide the primary plane.
4536  */
4537 static void
4538 intel_post_enable_primary(struct drm_crtc *crtc)
4539 {
4540         struct drm_device *dev = crtc->dev;
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4543         int pipe = intel_crtc->pipe;
4544
4545         /*
4546          * FIXME IPS should be fine as long as one plane is
4547          * enabled, but in practice it seems to have problems
4548          * when going from primary only to sprite only and vice
4549          * versa.
4550          */
4551         hsw_enable_ips(intel_crtc);
4552
4553         /*
4554          * Gen2 reports pipe underruns whenever all planes are disabled.
4555          * So don't enable underrun reporting before at least some planes
4556          * are enabled.
4557          * FIXME: Need to fix the logic to work when we turn off all planes
4558          * but leave the pipe running.
4559          */
4560         if (IS_GEN2(dev))
4561                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4562
4563         /* Underruns don't always raise interrupts, so check manually. */
4564         intel_check_cpu_fifo_underruns(dev_priv);
4565         intel_check_pch_fifo_underruns(dev_priv);
4566 }
4567
4568 /* FIXME move all this to pre_plane_update() with proper state tracking */
4569 static void
4570 intel_pre_disable_primary(struct drm_crtc *crtc)
4571 {
4572         struct drm_device *dev = crtc->dev;
4573         struct drm_i915_private *dev_priv = dev->dev_private;
4574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4575         int pipe = intel_crtc->pipe;
4576
4577         /*
4578          * Gen2 reports pipe underruns whenever all planes are disabled.
4579          * So diasble underrun reporting before all the planes get disabled.
4580          * FIXME: Need to fix the logic to work when we turn off all planes
4581          * but leave the pipe running.
4582          */
4583         if (IS_GEN2(dev))
4584                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4585
4586         /*
4587          * FIXME IPS should be fine as long as one plane is
4588          * enabled, but in practice it seems to have problems
4589          * when going from primary only to sprite only and vice
4590          * versa.
4591          */
4592         hsw_disable_ips(intel_crtc);
4593 }
4594
4595 /* FIXME get rid of this and use pre_plane_update */
4596 static void
4597 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4598 {
4599         struct drm_device *dev = crtc->dev;
4600         struct drm_i915_private *dev_priv = dev->dev_private;
4601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4602         int pipe = intel_crtc->pipe;
4603
4604         intel_pre_disable_primary(crtc);
4605
4606         /*
4607          * Vblank time updates from the shadow to live plane control register
4608          * are blocked if the memory self-refresh mode is active at that
4609          * moment. So to make sure the plane gets truly disabled, disable
4610          * first the self-refresh mode. The self-refresh enable bit in turn
4611          * will be checked/applied by the HW only at the next frame start
4612          * event which is after the vblank start event, so we need to have a
4613          * wait-for-vblank between disabling the plane and the pipe.
4614          */
4615         if (HAS_GMCH_DISPLAY(dev)) {
4616                 intel_set_memory_cxsr(dev_priv, false);
4617                 dev_priv->wm.vlv.cxsr = false;
4618                 intel_wait_for_vblank(dev, pipe);
4619         }
4620 }
4621
4622 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4623 {
4624         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4625         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4626         struct intel_crtc_state *pipe_config =
4627                 to_intel_crtc_state(crtc->base.state);
4628         struct drm_device *dev = crtc->base.dev;
4629         struct drm_plane *primary = crtc->base.primary;
4630         struct drm_plane_state *old_pri_state =
4631                 drm_atomic_get_existing_plane_state(old_state, primary);
4632
4633         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4634
4635         crtc->wm.cxsr_allowed = true;
4636
4637         if (pipe_config->update_wm_post && pipe_config->base.active)
4638                 intel_update_watermarks(&crtc->base);
4639
4640         if (old_pri_state) {
4641                 struct intel_plane_state *primary_state =
4642                         to_intel_plane_state(primary->state);
4643                 struct intel_plane_state *old_primary_state =
4644                         to_intel_plane_state(old_pri_state);
4645
4646                 intel_fbc_post_update(crtc);
4647
4648                 if (primary_state->visible &&
4649                     (needs_modeset(&pipe_config->base) ||
4650                      !old_primary_state->visible))
4651                         intel_post_enable_primary(&crtc->base);
4652         }
4653 }
4654
4655 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4656 {
4657         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4658         struct drm_device *dev = crtc->base.dev;
4659         struct drm_i915_private *dev_priv = dev->dev_private;
4660         struct intel_crtc_state *pipe_config =
4661                 to_intel_crtc_state(crtc->base.state);
4662         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4663         struct drm_plane *primary = crtc->base.primary;
4664         struct drm_plane_state *old_pri_state =
4665                 drm_atomic_get_existing_plane_state(old_state, primary);
4666         bool modeset = needs_modeset(&pipe_config->base);
4667
4668         if (old_pri_state) {
4669                 struct intel_plane_state *primary_state =
4670                         to_intel_plane_state(primary->state);
4671                 struct intel_plane_state *old_primary_state =
4672                         to_intel_plane_state(old_pri_state);
4673
4674                 intel_fbc_pre_update(crtc);
4675
4676                 if (old_primary_state->visible &&
4677                     (modeset || !primary_state->visible))
4678                         intel_pre_disable_primary(&crtc->base);
4679         }
4680
4681         if (pipe_config->disable_cxsr) {
4682                 crtc->wm.cxsr_allowed = false;
4683
4684                 /*
4685                  * Vblank time updates from the shadow to live plane control register
4686                  * are blocked if the memory self-refresh mode is active at that
4687                  * moment. So to make sure the plane gets truly disabled, disable
4688                  * first the self-refresh mode. The self-refresh enable bit in turn
4689                  * will be checked/applied by the HW only at the next frame start
4690                  * event which is after the vblank start event, so we need to have a
4691                  * wait-for-vblank between disabling the plane and the pipe.
4692                  */
4693                 if (old_crtc_state->base.active) {
4694                         intel_set_memory_cxsr(dev_priv, false);
4695                         dev_priv->wm.vlv.cxsr = false;
4696                         intel_wait_for_vblank(dev, crtc->pipe);
4697                 }
4698         }
4699
4700         /*
4701          * IVB workaround: must disable low power watermarks for at least
4702          * one frame before enabling scaling.  LP watermarks can be re-enabled
4703          * when scaling is disabled.
4704          *
4705          * WaCxSRDisabledForSpriteScaling:ivb
4706          */
4707         if (pipe_config->disable_lp_wm) {
4708                 ilk_disable_lp_wm(dev);
4709                 intel_wait_for_vblank(dev, crtc->pipe);
4710         }
4711
4712         /*
4713          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4714          * watermark programming here.
4715          */
4716         if (needs_modeset(&pipe_config->base))
4717                 return;
4718
4719         /*
4720          * For platforms that support atomic watermarks, program the
4721          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4722          * will be the intermediate values that are safe for both pre- and
4723          * post- vblank; when vblank happens, the 'active' values will be set
4724          * to the final 'target' values and we'll do this again to get the
4725          * optimal watermarks.  For gen9+ platforms, the values we program here
4726          * will be the final target values which will get automatically latched
4727          * at vblank time; no further programming will be necessary.
4728          *
4729          * If a platform hasn't been transitioned to atomic watermarks yet,
4730          * we'll continue to update watermarks the old way, if flags tell
4731          * us to.
4732          */
4733         if (dev_priv->display.initial_watermarks != NULL)
4734                 dev_priv->display.initial_watermarks(pipe_config);
4735         else if (pipe_config->update_wm_pre)
4736                 intel_update_watermarks(&crtc->base);
4737 }
4738
4739 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4740 {
4741         struct drm_device *dev = crtc->dev;
4742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743         struct drm_plane *p;
4744         int pipe = intel_crtc->pipe;
4745
4746         intel_crtc_dpms_overlay_disable(intel_crtc);
4747
4748         drm_for_each_plane_mask(p, dev, plane_mask)
4749                 to_intel_plane(p)->disable_plane(p, crtc);
4750
4751         /*
4752          * FIXME: Once we grow proper nuclear flip support out of this we need
4753          * to compute the mask of flip planes precisely. For the time being
4754          * consider this a flip to a NULL plane.
4755          */
4756         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4757 }
4758
4759 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4760 {
4761         struct drm_device *dev = crtc->dev;
4762         struct drm_i915_private *dev_priv = dev->dev_private;
4763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4764         struct intel_encoder *encoder;
4765         int pipe = intel_crtc->pipe;
4766
4767         if (WARN_ON(intel_crtc->active))
4768                 return;
4769
4770         if (intel_crtc->config->has_pch_encoder)
4771                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4772
4773         if (intel_crtc->config->has_pch_encoder)
4774                 intel_prepare_shared_dpll(intel_crtc);
4775
4776         if (intel_crtc->config->has_dp_encoder)
4777                 intel_dp_set_m_n(intel_crtc, M1_N1);
4778
4779         intel_set_pipe_timings(intel_crtc);
4780         intel_set_pipe_src_size(intel_crtc);
4781
4782         if (intel_crtc->config->has_pch_encoder) {
4783                 intel_cpu_transcoder_set_m_n(intel_crtc,
4784                                      &intel_crtc->config->fdi_m_n, NULL);
4785         }
4786
4787         ironlake_set_pipeconf(crtc);
4788
4789         intel_crtc->active = true;
4790
4791         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4792
4793         for_each_encoder_on_crtc(dev, crtc, encoder)
4794                 if (encoder->pre_enable)
4795                         encoder->pre_enable(encoder);
4796
4797         if (intel_crtc->config->has_pch_encoder) {
4798                 /* Note: FDI PLL enabling _must_ be done before we enable the
4799                  * cpu pipes, hence this is separate from all the other fdi/pch
4800                  * enabling. */
4801                 ironlake_fdi_pll_enable(intel_crtc);
4802         } else {
4803                 assert_fdi_tx_disabled(dev_priv, pipe);
4804                 assert_fdi_rx_disabled(dev_priv, pipe);
4805         }
4806
4807         ironlake_pfit_enable(intel_crtc);
4808
4809         /*
4810          * On ILK+ LUT must be loaded before the pipe is running but with
4811          * clocks enabled
4812          */
4813         intel_color_load_luts(crtc);
4814
4815         if (dev_priv->display.initial_watermarks != NULL)
4816                 dev_priv->display.initial_watermarks(intel_crtc->config);
4817         intel_enable_pipe(intel_crtc);
4818
4819         if (intel_crtc->config->has_pch_encoder)
4820                 ironlake_pch_enable(crtc);
4821
4822         assert_vblank_disabled(crtc);
4823         drm_crtc_vblank_on(crtc);
4824
4825         for_each_encoder_on_crtc(dev, crtc, encoder)
4826                 encoder->enable(encoder);
4827
4828         if (HAS_PCH_CPT(dev))
4829                 cpt_verify_modeset(dev, intel_crtc->pipe);
4830
4831         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4832         if (intel_crtc->config->has_pch_encoder)
4833                 intel_wait_for_vblank(dev, pipe);
4834         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4835 }
4836
4837 /* IPS only exists on ULT machines and is tied to pipe A. */
4838 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4839 {
4840         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4841 }
4842
4843 static void haswell_crtc_enable(struct drm_crtc *crtc)
4844 {
4845         struct drm_device *dev = crtc->dev;
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848         struct intel_encoder *encoder;
4849         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4850         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4851         struct intel_crtc_state *pipe_config =
4852                 to_intel_crtc_state(crtc->state);
4853
4854         if (WARN_ON(intel_crtc->active))
4855                 return;
4856
4857         if (intel_crtc->config->has_pch_encoder)
4858                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4859                                                       false);
4860
4861         if (intel_crtc->config->shared_dpll)
4862                 intel_enable_shared_dpll(intel_crtc);
4863
4864         if (intel_crtc->config->has_dp_encoder)
4865                 intel_dp_set_m_n(intel_crtc, M1_N1);
4866
4867         if (!intel_crtc->config->has_dsi_encoder)
4868                 intel_set_pipe_timings(intel_crtc);
4869
4870         intel_set_pipe_src_size(intel_crtc);
4871
4872         if (cpu_transcoder != TRANSCODER_EDP &&
4873             !transcoder_is_dsi(cpu_transcoder)) {
4874                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4875                            intel_crtc->config->pixel_multiplier - 1);
4876         }
4877
4878         if (intel_crtc->config->has_pch_encoder) {
4879                 intel_cpu_transcoder_set_m_n(intel_crtc,
4880                                      &intel_crtc->config->fdi_m_n, NULL);
4881         }
4882
4883         if (!intel_crtc->config->has_dsi_encoder)
4884                 haswell_set_pipeconf(crtc);
4885
4886         haswell_set_pipemisc(crtc);
4887
4888         intel_color_set_csc(crtc);
4889
4890         intel_crtc->active = true;
4891
4892         if (intel_crtc->config->has_pch_encoder)
4893                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4894         else
4895                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4896
4897         for_each_encoder_on_crtc(dev, crtc, encoder) {
4898                 if (encoder->pre_enable)
4899                         encoder->pre_enable(encoder);
4900         }
4901
4902         if (intel_crtc->config->has_pch_encoder)
4903                 dev_priv->display.fdi_link_train(crtc);
4904
4905         if (!intel_crtc->config->has_dsi_encoder)
4906                 intel_ddi_enable_pipe_clock(intel_crtc);
4907
4908         if (INTEL_INFO(dev)->gen >= 9)
4909                 skylake_pfit_enable(intel_crtc);
4910         else
4911                 ironlake_pfit_enable(intel_crtc);
4912
4913         /*
4914          * On ILK+ LUT must be loaded before the pipe is running but with
4915          * clocks enabled
4916          */
4917         intel_color_load_luts(crtc);
4918
4919         intel_ddi_set_pipe_settings(crtc);
4920         if (!intel_crtc->config->has_dsi_encoder)
4921                 intel_ddi_enable_transcoder_func(crtc);
4922
4923         if (dev_priv->display.initial_watermarks != NULL)
4924                 dev_priv->display.initial_watermarks(pipe_config);
4925         else
4926                 intel_update_watermarks(crtc);
4927
4928         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4929         if (!intel_crtc->config->has_dsi_encoder)
4930                 intel_enable_pipe(intel_crtc);
4931
4932         if (intel_crtc->config->has_pch_encoder)
4933                 lpt_pch_enable(crtc);
4934
4935         if (intel_crtc->config->dp_encoder_is_mst)
4936                 intel_ddi_set_vc_payload_alloc(crtc, true);
4937
4938         assert_vblank_disabled(crtc);
4939         drm_crtc_vblank_on(crtc);
4940
4941         for_each_encoder_on_crtc(dev, crtc, encoder) {
4942                 encoder->enable(encoder);
4943                 intel_opregion_notify_encoder(encoder, true);
4944         }
4945
4946         if (intel_crtc->config->has_pch_encoder) {
4947                 intel_wait_for_vblank(dev, pipe);
4948                 intel_wait_for_vblank(dev, pipe);
4949                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4950                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4951                                                       true);
4952         }
4953
4954         /* If we change the relative order between pipe/planes enabling, we need
4955          * to change the workaround. */
4956         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4957         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4958                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4959                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4960         }
4961 }
4962
4963 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4964 {
4965         struct drm_device *dev = crtc->base.dev;
4966         struct drm_i915_private *dev_priv = dev->dev_private;
4967         int pipe = crtc->pipe;
4968
4969         /* To avoid upsetting the power well on haswell only disable the pfit if
4970          * it's in use. The hw state code will make sure we get this right. */
4971         if (force || crtc->config->pch_pfit.enabled) {
4972                 I915_WRITE(PF_CTL(pipe), 0);
4973                 I915_WRITE(PF_WIN_POS(pipe), 0);
4974                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4975         }
4976 }
4977
4978 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4979 {
4980         struct drm_device *dev = crtc->dev;
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983         struct intel_encoder *encoder;
4984         int pipe = intel_crtc->pipe;
4985
4986         if (intel_crtc->config->has_pch_encoder)
4987                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4988
4989         for_each_encoder_on_crtc(dev, crtc, encoder)
4990                 encoder->disable(encoder);
4991
4992         drm_crtc_vblank_off(crtc);
4993         assert_vblank_disabled(crtc);
4994
4995         /*
4996          * Sometimes spurious CPU pipe underruns happen when the
4997          * pipe is already disabled, but FDI RX/TX is still enabled.
4998          * Happens at least with VGA+HDMI cloning. Suppress them.
4999          */
5000         if (intel_crtc->config->has_pch_encoder)
5001                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5002
5003         intel_disable_pipe(intel_crtc);
5004
5005         ironlake_pfit_disable(intel_crtc, false);
5006
5007         if (intel_crtc->config->has_pch_encoder) {
5008                 ironlake_fdi_disable(crtc);
5009                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5010         }
5011
5012         for_each_encoder_on_crtc(dev, crtc, encoder)
5013                 if (encoder->post_disable)
5014                         encoder->post_disable(encoder);
5015
5016         if (intel_crtc->config->has_pch_encoder) {
5017                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5018
5019                 if (HAS_PCH_CPT(dev)) {
5020                         i915_reg_t reg;
5021                         u32 temp;
5022
5023                         /* disable TRANS_DP_CTL */
5024                         reg = TRANS_DP_CTL(pipe);
5025                         temp = I915_READ(reg);
5026                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5027                                   TRANS_DP_PORT_SEL_MASK);
5028                         temp |= TRANS_DP_PORT_SEL_NONE;
5029                         I915_WRITE(reg, temp);
5030
5031                         /* disable DPLL_SEL */
5032                         temp = I915_READ(PCH_DPLL_SEL);
5033                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5034                         I915_WRITE(PCH_DPLL_SEL, temp);
5035                 }
5036
5037                 ironlake_fdi_pll_disable(intel_crtc);
5038         }
5039
5040         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5041 }
5042
5043 static void haswell_crtc_disable(struct drm_crtc *crtc)
5044 {
5045         struct drm_device *dev = crtc->dev;
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048         struct intel_encoder *encoder;
5049         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5050
5051         if (intel_crtc->config->has_pch_encoder)
5052                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5053                                                       false);
5054
5055         for_each_encoder_on_crtc(dev, crtc, encoder) {
5056                 intel_opregion_notify_encoder(encoder, false);
5057                 encoder->disable(encoder);
5058         }
5059
5060         drm_crtc_vblank_off(crtc);
5061         assert_vblank_disabled(crtc);
5062
5063         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5064         if (!intel_crtc->config->has_dsi_encoder)
5065                 intel_disable_pipe(intel_crtc);
5066
5067         if (intel_crtc->config->dp_encoder_is_mst)
5068                 intel_ddi_set_vc_payload_alloc(crtc, false);
5069
5070         if (!intel_crtc->config->has_dsi_encoder)
5071                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5072
5073         if (INTEL_INFO(dev)->gen >= 9)
5074                 skylake_scaler_disable(intel_crtc);
5075         else
5076                 ironlake_pfit_disable(intel_crtc, false);
5077
5078         if (!intel_crtc->config->has_dsi_encoder)
5079                 intel_ddi_disable_pipe_clock(intel_crtc);
5080
5081         for_each_encoder_on_crtc(dev, crtc, encoder)
5082                 if (encoder->post_disable)
5083                         encoder->post_disable(encoder);
5084
5085         if (intel_crtc->config->has_pch_encoder) {
5086                 lpt_disable_pch_transcoder(dev_priv);
5087                 lpt_disable_iclkip(dev_priv);
5088                 intel_ddi_fdi_disable(crtc);
5089
5090                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5091                                                       true);
5092         }
5093 }
5094
5095 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5096 {
5097         struct drm_device *dev = crtc->base.dev;
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099         struct intel_crtc_state *pipe_config = crtc->config;
5100
5101         if (!pipe_config->gmch_pfit.control)
5102                 return;
5103
5104         /*
5105          * The panel fitter should only be adjusted whilst the pipe is disabled,
5106          * according to register description and PRM.
5107          */
5108         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5109         assert_pipe_disabled(dev_priv, crtc->pipe);
5110
5111         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5112         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5113
5114         /* Border color in case we don't scale up to the full screen. Black by
5115          * default, change to something else for debugging. */
5116         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5117 }
5118
5119 static enum intel_display_power_domain port_to_power_domain(enum port port)
5120 {
5121         switch (port) {
5122         case PORT_A:
5123                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5124         case PORT_B:
5125                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5126         case PORT_C:
5127                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5128         case PORT_D:
5129                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5130         case PORT_E:
5131                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5132         default:
5133                 MISSING_CASE(port);
5134                 return POWER_DOMAIN_PORT_OTHER;
5135         }
5136 }
5137
5138 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5139 {
5140         switch (port) {
5141         case PORT_A:
5142                 return POWER_DOMAIN_AUX_A;
5143         case PORT_B:
5144                 return POWER_DOMAIN_AUX_B;
5145         case PORT_C:
5146                 return POWER_DOMAIN_AUX_C;
5147         case PORT_D:
5148                 return POWER_DOMAIN_AUX_D;
5149         case PORT_E:
5150                 /* FIXME: Check VBT for actual wiring of PORT E */
5151                 return POWER_DOMAIN_AUX_D;
5152         default:
5153                 MISSING_CASE(port);
5154                 return POWER_DOMAIN_AUX_A;
5155         }
5156 }
5157
5158 enum intel_display_power_domain
5159 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5160 {
5161         struct drm_device *dev = intel_encoder->base.dev;
5162         struct intel_digital_port *intel_dig_port;
5163
5164         switch (intel_encoder->type) {
5165         case INTEL_OUTPUT_UNKNOWN:
5166                 /* Only DDI platforms should ever use this output type */
5167                 WARN_ON_ONCE(!HAS_DDI(dev));
5168         case INTEL_OUTPUT_DISPLAYPORT:
5169         case INTEL_OUTPUT_HDMI:
5170         case INTEL_OUTPUT_EDP:
5171                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5172                 return port_to_power_domain(intel_dig_port->port);
5173         case INTEL_OUTPUT_DP_MST:
5174                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5175                 return port_to_power_domain(intel_dig_port->port);
5176         case INTEL_OUTPUT_ANALOG:
5177                 return POWER_DOMAIN_PORT_CRT;
5178         case INTEL_OUTPUT_DSI:
5179                 return POWER_DOMAIN_PORT_DSI;
5180         default:
5181                 return POWER_DOMAIN_PORT_OTHER;
5182         }
5183 }
5184
5185 enum intel_display_power_domain
5186 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5187 {
5188         struct drm_device *dev = intel_encoder->base.dev;
5189         struct intel_digital_port *intel_dig_port;
5190
5191         switch (intel_encoder->type) {
5192         case INTEL_OUTPUT_UNKNOWN:
5193         case INTEL_OUTPUT_HDMI:
5194                 /*
5195                  * Only DDI platforms should ever use these output types.
5196                  * We can get here after the HDMI detect code has already set
5197                  * the type of the shared encoder. Since we can't be sure
5198                  * what's the status of the given connectors, play safe and
5199                  * run the DP detection too.
5200                  */
5201                 WARN_ON_ONCE(!HAS_DDI(dev));
5202         case INTEL_OUTPUT_DISPLAYPORT:
5203         case INTEL_OUTPUT_EDP:
5204                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5205                 return port_to_aux_power_domain(intel_dig_port->port);
5206         case INTEL_OUTPUT_DP_MST:
5207                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5208                 return port_to_aux_power_domain(intel_dig_port->port);
5209         default:
5210                 MISSING_CASE(intel_encoder->type);
5211                 return POWER_DOMAIN_AUX_A;
5212         }
5213 }
5214
5215 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5216                                             struct intel_crtc_state *crtc_state)
5217 {
5218         struct drm_device *dev = crtc->dev;
5219         struct drm_encoder *encoder;
5220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221         enum pipe pipe = intel_crtc->pipe;
5222         unsigned long mask;
5223         enum transcoder transcoder = crtc_state->cpu_transcoder;
5224
5225         if (!crtc_state->base.active)
5226                 return 0;
5227
5228         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5229         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5230         if (crtc_state->pch_pfit.enabled ||
5231             crtc_state->pch_pfit.force_thru)
5232                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5233
5234         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5235                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5236
5237                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5238         }
5239
5240         if (crtc_state->shared_dpll)
5241                 mask |= BIT(POWER_DOMAIN_PLLS);
5242
5243         return mask;
5244 }
5245
5246 static unsigned long
5247 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5248                                struct intel_crtc_state *crtc_state)
5249 {
5250         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5252         enum intel_display_power_domain domain;
5253         unsigned long domains, new_domains, old_domains;
5254
5255         old_domains = intel_crtc->enabled_power_domains;
5256         intel_crtc->enabled_power_domains = new_domains =
5257                 get_crtc_power_domains(crtc, crtc_state);
5258
5259         domains = new_domains & ~old_domains;
5260
5261         for_each_power_domain(domain, domains)
5262                 intel_display_power_get(dev_priv, domain);
5263
5264         return old_domains & ~new_domains;
5265 }
5266
5267 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5268                                       unsigned long domains)
5269 {
5270         enum intel_display_power_domain domain;
5271
5272         for_each_power_domain(domain, domains)
5273                 intel_display_power_put(dev_priv, domain);
5274 }
5275
5276 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5277 {
5278         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5279
5280         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5281             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5282                 return max_cdclk_freq;
5283         else if (IS_CHERRYVIEW(dev_priv))
5284                 return max_cdclk_freq*95/100;
5285         else if (INTEL_INFO(dev_priv)->gen < 4)
5286                 return 2*max_cdclk_freq*90/100;
5287         else
5288                 return max_cdclk_freq*90/100;
5289 }
5290
5291 static void intel_update_max_cdclk(struct drm_device *dev)
5292 {
5293         struct drm_i915_private *dev_priv = dev->dev_private;
5294
5295         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5296                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5297
5298                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5299                         dev_priv->max_cdclk_freq = 675000;
5300                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5301                         dev_priv->max_cdclk_freq = 540000;
5302                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5303                         dev_priv->max_cdclk_freq = 450000;
5304                 else
5305                         dev_priv->max_cdclk_freq = 337500;
5306         } else if (IS_BROADWELL(dev))  {
5307                 /*
5308                  * FIXME with extra cooling we can allow
5309                  * 540 MHz for ULX and 675 Mhz for ULT.
5310                  * How can we know if extra cooling is
5311                  * available? PCI ID, VTB, something else?
5312                  */
5313                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5314                         dev_priv->max_cdclk_freq = 450000;
5315                 else if (IS_BDW_ULX(dev))
5316                         dev_priv->max_cdclk_freq = 450000;
5317                 else if (IS_BDW_ULT(dev))
5318                         dev_priv->max_cdclk_freq = 540000;
5319                 else
5320                         dev_priv->max_cdclk_freq = 675000;
5321         } else if (IS_CHERRYVIEW(dev)) {
5322                 dev_priv->max_cdclk_freq = 320000;
5323         } else if (IS_VALLEYVIEW(dev)) {
5324                 dev_priv->max_cdclk_freq = 400000;
5325         } else {
5326                 /* otherwise assume cdclk is fixed */
5327                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5328         }
5329
5330         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5331
5332         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5333                          dev_priv->max_cdclk_freq);
5334
5335         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5336                          dev_priv->max_dotclk_freq);
5337 }
5338
5339 static void intel_update_cdclk(struct drm_device *dev)
5340 {
5341         struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5345                          dev_priv->cdclk_freq);
5346
5347         /*
5348          * Program the gmbus_freq based on the cdclk frequency.
5349          * BSpec erroneously claims we should aim for 4MHz, but
5350          * in fact 1MHz is the correct frequency.
5351          */
5352         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5353                 /*
5354                  * Program the gmbus_freq based on the cdclk frequency.
5355                  * BSpec erroneously claims we should aim for 4MHz, but
5356                  * in fact 1MHz is the correct frequency.
5357                  */
5358                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5359         }
5360
5361         if (dev_priv->max_cdclk_freq == 0)
5362                 intel_update_max_cdclk(dev);
5363 }
5364
5365 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5366 {
5367         struct drm_i915_private *dev_priv = dev->dev_private;
5368         uint32_t divider;
5369         uint32_t ratio;
5370         uint32_t current_freq;
5371         int ret;
5372
5373         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5374         switch (frequency) {
5375         case 144000:
5376                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5377                 ratio = BXT_DE_PLL_RATIO(60);
5378                 break;
5379         case 288000:
5380                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5381                 ratio = BXT_DE_PLL_RATIO(60);
5382                 break;
5383         case 384000:
5384                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5385                 ratio = BXT_DE_PLL_RATIO(60);
5386                 break;
5387         case 576000:
5388                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5389                 ratio = BXT_DE_PLL_RATIO(60);
5390                 break;
5391         case 624000:
5392                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393                 ratio = BXT_DE_PLL_RATIO(65);
5394                 break;
5395         case 19200:
5396                 /*
5397                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5398                  * to suppress GCC warning.
5399                  */
5400                 ratio = 0;
5401                 divider = 0;
5402                 break;
5403         default:
5404                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5405
5406                 return;
5407         }
5408
5409         mutex_lock(&dev_priv->rps.hw_lock);
5410         /* Inform power controller of upcoming frequency change */
5411         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5412                                       0x80000000);
5413         mutex_unlock(&dev_priv->rps.hw_lock);
5414
5415         if (ret) {
5416                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5417                           ret, frequency);
5418                 return;
5419         }
5420
5421         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5422         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5423         current_freq = current_freq * 500 + 1000;
5424
5425         /*
5426          * DE PLL has to be disabled when
5427          * - setting to 19.2MHz (bypass, PLL isn't used)
5428          * - before setting to 624MHz (PLL needs toggling)
5429          * - before setting to any frequency from 624MHz (PLL needs toggling)
5430          */
5431         if (frequency == 19200 || frequency == 624000 ||
5432             current_freq == 624000) {
5433                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5434                 /* Timeout 200us */
5435                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5436                              1))
5437                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5438         }
5439
5440         if (frequency != 19200) {
5441                 uint32_t val;
5442
5443                 val = I915_READ(BXT_DE_PLL_CTL);
5444                 val &= ~BXT_DE_PLL_RATIO_MASK;
5445                 val |= ratio;
5446                 I915_WRITE(BXT_DE_PLL_CTL, val);
5447
5448                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5449                 /* Timeout 200us */
5450                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5451                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5452
5453                 val = I915_READ(CDCLK_CTL);
5454                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5455                 val |= divider;
5456                 /*
5457                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5458                  * enable otherwise.
5459                  */
5460                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461                 if (frequency >= 500000)
5462                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463
5464                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5465                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5466                 val |= (frequency - 1000) / 500;
5467                 I915_WRITE(CDCLK_CTL, val);
5468         }
5469
5470         mutex_lock(&dev_priv->rps.hw_lock);
5471         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5472                                       DIV_ROUND_UP(frequency, 25000));
5473         mutex_unlock(&dev_priv->rps.hw_lock);
5474
5475         if (ret) {
5476                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5477                           ret, frequency);
5478                 return;
5479         }
5480
5481         intel_update_cdclk(dev);
5482 }
5483
5484 void broxton_init_cdclk(struct drm_device *dev)
5485 {
5486         struct drm_i915_private *dev_priv = dev->dev_private;
5487         uint32_t val;
5488
5489         /*
5490          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5491          * or else the reset will hang because there is no PCH to respond.
5492          * Move the handshake programming to initialization sequence.
5493          * Previously was left up to BIOS.
5494          */
5495         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5496         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5497         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5498
5499         /* Enable PG1 for cdclk */
5500         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5501
5502         /* check if cd clock is enabled */
5503         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5504                 DRM_DEBUG_KMS("Display already initialized\n");
5505                 return;
5506         }
5507
5508         /*
5509          * FIXME:
5510          * - The initial CDCLK needs to be read from VBT.
5511          *   Need to make this change after VBT has changes for BXT.
5512          * - check if setting the max (or any) cdclk freq is really necessary
5513          *   here, it belongs to modeset time
5514          */
5515         broxton_set_cdclk(dev, 624000);
5516
5517         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5518         POSTING_READ(DBUF_CTL);
5519
5520         udelay(10);
5521
5522         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5523                 DRM_ERROR("DBuf power enable timeout!\n");
5524 }
5525
5526 void broxton_uninit_cdclk(struct drm_device *dev)
5527 {
5528         struct drm_i915_private *dev_priv = dev->dev_private;
5529
5530         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5531         POSTING_READ(DBUF_CTL);
5532
5533         udelay(10);
5534
5535         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5536                 DRM_ERROR("DBuf power disable timeout!\n");
5537
5538         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5539         broxton_set_cdclk(dev, 19200);
5540
5541         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5542 }
5543
5544 static const struct skl_cdclk_entry {
5545         unsigned int freq;
5546         unsigned int vco;
5547 } skl_cdclk_frequencies[] = {
5548         { .freq = 308570, .vco = 8640 },
5549         { .freq = 337500, .vco = 8100 },
5550         { .freq = 432000, .vco = 8640 },
5551         { .freq = 450000, .vco = 8100 },
5552         { .freq = 540000, .vco = 8100 },
5553         { .freq = 617140, .vco = 8640 },
5554         { .freq = 675000, .vco = 8100 },
5555 };
5556
5557 static unsigned int skl_cdclk_decimal(unsigned int freq)
5558 {
5559         return (freq - 1000) / 500;
5560 }
5561
5562 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5563 {
5564         unsigned int i;
5565
5566         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5567                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5568
5569                 if (e->freq == freq)
5570                         return e->vco;
5571         }
5572
5573         return 8100;
5574 }
5575
5576 static void
5577 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5578 {
5579         unsigned int min_freq;
5580         u32 val;
5581
5582         /* select the minimum CDCLK before enabling DPLL 0 */
5583         val = I915_READ(CDCLK_CTL);
5584         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5585         val |= CDCLK_FREQ_337_308;
5586
5587         if (required_vco == 8640)
5588                 min_freq = 308570;
5589         else
5590                 min_freq = 337500;
5591
5592         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5593
5594         I915_WRITE(CDCLK_CTL, val);
5595         POSTING_READ(CDCLK_CTL);
5596
5597         /*
5598          * We always enable DPLL0 with the lowest link rate possible, but still
5599          * taking into account the VCO required to operate the eDP panel at the
5600          * desired frequency. The usual DP link rates operate with a VCO of
5601          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5602          * The modeset code is responsible for the selection of the exact link
5603          * rate later on, with the constraint of choosing a frequency that
5604          * works with required_vco.
5605          */
5606         val = I915_READ(DPLL_CTRL1);
5607
5608         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5609                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5610         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5611         if (required_vco == 8640)
5612                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5613                                             SKL_DPLL0);
5614         else
5615                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5616                                             SKL_DPLL0);
5617
5618         I915_WRITE(DPLL_CTRL1, val);
5619         POSTING_READ(DPLL_CTRL1);
5620
5621         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5622
5623         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5624                 DRM_ERROR("DPLL0 not locked\n");
5625 }
5626
5627 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5628 {
5629         int ret;
5630         u32 val;
5631
5632         /* inform PCU we want to change CDCLK */
5633         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5634         mutex_lock(&dev_priv->rps.hw_lock);
5635         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5636         mutex_unlock(&dev_priv->rps.hw_lock);
5637
5638         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5639 }
5640
5641 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5642 {
5643         unsigned int i;
5644
5645         for (i = 0; i < 15; i++) {
5646                 if (skl_cdclk_pcu_ready(dev_priv))
5647                         return true;
5648                 udelay(10);
5649         }
5650
5651         return false;
5652 }
5653
5654 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5655 {
5656         struct drm_device *dev = dev_priv->dev;
5657         u32 freq_select, pcu_ack;
5658
5659         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5660
5661         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5662                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5663                 return;
5664         }
5665
5666         /* set CDCLK_CTL */
5667         switch(freq) {
5668         case 450000:
5669         case 432000:
5670                 freq_select = CDCLK_FREQ_450_432;
5671                 pcu_ack = 1;
5672                 break;
5673         case 540000:
5674                 freq_select = CDCLK_FREQ_540;
5675                 pcu_ack = 2;
5676                 break;
5677         case 308570:
5678         case 337500:
5679         default:
5680                 freq_select = CDCLK_FREQ_337_308;
5681                 pcu_ack = 0;
5682                 break;
5683         case 617140:
5684         case 675000:
5685                 freq_select = CDCLK_FREQ_675_617;
5686                 pcu_ack = 3;
5687                 break;
5688         }
5689
5690         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5691         POSTING_READ(CDCLK_CTL);
5692
5693         /* inform PCU of the change */
5694         mutex_lock(&dev_priv->rps.hw_lock);
5695         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5696         mutex_unlock(&dev_priv->rps.hw_lock);
5697
5698         intel_update_cdclk(dev);
5699 }
5700
5701 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5702 {
5703         /* disable DBUF power */
5704         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5705         POSTING_READ(DBUF_CTL);
5706
5707         udelay(10);
5708
5709         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5710                 DRM_ERROR("DBuf power disable timeout\n");
5711
5712         /* disable DPLL0 */
5713         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5714         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5715                 DRM_ERROR("Couldn't disable DPLL0\n");
5716 }
5717
5718 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5719 {
5720         unsigned int required_vco;
5721
5722         /* DPLL0 not enabled (happens on early BIOS versions) */
5723         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5724                 /* enable DPLL0 */
5725                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5726                 skl_dpll0_enable(dev_priv, required_vco);
5727         }
5728
5729         /* set CDCLK to the frequency the BIOS chose */
5730         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5731
5732         /* enable DBUF power */
5733         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5734         POSTING_READ(DBUF_CTL);
5735
5736         udelay(10);
5737
5738         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5739                 DRM_ERROR("DBuf power enable timeout\n");
5740 }
5741
5742 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5743 {
5744         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5745         uint32_t cdctl = I915_READ(CDCLK_CTL);
5746         int freq = dev_priv->skl_boot_cdclk;
5747
5748         /*
5749          * check if the pre-os intialized the display
5750          * There is SWF18 scratchpad register defined which is set by the
5751          * pre-os which can be used by the OS drivers to check the status
5752          */
5753         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5754                 goto sanitize;
5755
5756         /* Is PLL enabled and locked ? */
5757         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5758                 goto sanitize;
5759
5760         /* DPLL okay; verify the cdclock
5761          *
5762          * Noticed in some instances that the freq selection is correct but
5763          * decimal part is programmed wrong from BIOS where pre-os does not
5764          * enable display. Verify the same as well.
5765          */
5766         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5767                 /* All well; nothing to sanitize */
5768                 return false;
5769 sanitize:
5770         /*
5771          * As of now initialize with max cdclk till
5772          * we get dynamic cdclk support
5773          * */
5774         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5775         skl_init_cdclk(dev_priv);
5776
5777         /* we did have to sanitize */
5778         return true;
5779 }
5780
5781 /* Adjust CDclk dividers to allow high res or save power if possible */
5782 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5783 {
5784         struct drm_i915_private *dev_priv = dev->dev_private;
5785         u32 val, cmd;
5786
5787         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5788                                         != dev_priv->cdclk_freq);
5789
5790         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5791                 cmd = 2;
5792         else if (cdclk == 266667)
5793                 cmd = 1;
5794         else
5795                 cmd = 0;
5796
5797         mutex_lock(&dev_priv->rps.hw_lock);
5798         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5799         val &= ~DSPFREQGUAR_MASK;
5800         val |= (cmd << DSPFREQGUAR_SHIFT);
5801         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5802         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5803                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5804                      50)) {
5805                 DRM_ERROR("timed out waiting for CDclk change\n");
5806         }
5807         mutex_unlock(&dev_priv->rps.hw_lock);
5808
5809         mutex_lock(&dev_priv->sb_lock);
5810
5811         if (cdclk == 400000) {
5812                 u32 divider;
5813
5814                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5815
5816                 /* adjust cdclk divider */
5817                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5818                 val &= ~CCK_FREQUENCY_VALUES;
5819                 val |= divider;
5820                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5821
5822                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5823                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5824                              50))
5825                         DRM_ERROR("timed out waiting for CDclk change\n");
5826         }
5827
5828         /* adjust self-refresh exit latency value */
5829         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5830         val &= ~0x7f;
5831
5832         /*
5833          * For high bandwidth configs, we set a higher latency in the bunit
5834          * so that the core display fetch happens in time to avoid underruns.
5835          */
5836         if (cdclk == 400000)
5837                 val |= 4500 / 250; /* 4.5 usec */
5838         else
5839                 val |= 3000 / 250; /* 3.0 usec */
5840         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5841
5842         mutex_unlock(&dev_priv->sb_lock);
5843
5844         intel_update_cdclk(dev);
5845 }
5846
5847 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5848 {
5849         struct drm_i915_private *dev_priv = dev->dev_private;
5850         u32 val, cmd;
5851
5852         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5853                                                 != dev_priv->cdclk_freq);
5854
5855         switch (cdclk) {
5856         case 333333:
5857         case 320000:
5858         case 266667:
5859         case 200000:
5860                 break;
5861         default:
5862                 MISSING_CASE(cdclk);
5863                 return;
5864         }
5865
5866         /*
5867          * Specs are full of misinformation, but testing on actual
5868          * hardware has shown that we just need to write the desired
5869          * CCK divider into the Punit register.
5870          */
5871         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5872
5873         mutex_lock(&dev_priv->rps.hw_lock);
5874         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5875         val &= ~DSPFREQGUAR_MASK_CHV;
5876         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5877         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5878         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5879                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5880                      50)) {
5881                 DRM_ERROR("timed out waiting for CDclk change\n");
5882         }
5883         mutex_unlock(&dev_priv->rps.hw_lock);
5884
5885         intel_update_cdclk(dev);
5886 }
5887
5888 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5889                                  int max_pixclk)
5890 {
5891         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5892         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5893
5894         /*
5895          * Really only a few cases to deal with, as only 4 CDclks are supported:
5896          *   200MHz
5897          *   267MHz
5898          *   320/333MHz (depends on HPLL freq)
5899          *   400MHz (VLV only)
5900          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5901          * of the lower bin and adjust if needed.
5902          *
5903          * We seem to get an unstable or solid color picture at 200MHz.
5904          * Not sure what's wrong. For now use 200MHz only when all pipes
5905          * are off.
5906          */
5907         if (!IS_CHERRYVIEW(dev_priv) &&
5908             max_pixclk > freq_320*limit/100)
5909                 return 400000;
5910         else if (max_pixclk > 266667*limit/100)
5911                 return freq_320;
5912         else if (max_pixclk > 0)
5913                 return 266667;
5914         else
5915                 return 200000;
5916 }
5917
5918 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5919                               int max_pixclk)
5920 {
5921         /*
5922          * FIXME:
5923          * - remove the guardband, it's not needed on BXT
5924          * - set 19.2MHz bypass frequency if there are no active pipes
5925          */
5926         if (max_pixclk > 576000*9/10)
5927                 return 624000;
5928         else if (max_pixclk > 384000*9/10)
5929                 return 576000;
5930         else if (max_pixclk > 288000*9/10)
5931                 return 384000;
5932         else if (max_pixclk > 144000*9/10)
5933                 return 288000;
5934         else
5935                 return 144000;
5936 }
5937
5938 /* Compute the max pixel clock for new configuration. */
5939 static int intel_mode_max_pixclk(struct drm_device *dev,
5940                                  struct drm_atomic_state *state)
5941 {
5942         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5943         struct drm_i915_private *dev_priv = dev->dev_private;
5944         struct drm_crtc *crtc;
5945         struct drm_crtc_state *crtc_state;
5946         unsigned max_pixclk = 0, i;
5947         enum pipe pipe;
5948
5949         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5950                sizeof(intel_state->min_pixclk));
5951
5952         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5953                 int pixclk = 0;
5954
5955                 if (crtc_state->enable)
5956                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5957
5958                 intel_state->min_pixclk[i] = pixclk;
5959         }
5960
5961         for_each_pipe(dev_priv, pipe)
5962                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5963
5964         return max_pixclk;
5965 }
5966
5967 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5968 {
5969         struct drm_device *dev = state->dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971         int max_pixclk = intel_mode_max_pixclk(dev, state);
5972         struct intel_atomic_state *intel_state =
5973                 to_intel_atomic_state(state);
5974
5975         if (max_pixclk < 0)
5976                 return max_pixclk;
5977
5978         intel_state->cdclk = intel_state->dev_cdclk =
5979                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5980
5981         if (!intel_state->active_crtcs)
5982                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5983
5984         return 0;
5985 }
5986
5987 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5988 {
5989         struct drm_device *dev = state->dev;
5990         struct drm_i915_private *dev_priv = dev->dev_private;
5991         int max_pixclk = intel_mode_max_pixclk(dev, state);
5992         struct intel_atomic_state *intel_state =
5993                 to_intel_atomic_state(state);
5994
5995         if (max_pixclk < 0)
5996                 return max_pixclk;
5997
5998         intel_state->cdclk = intel_state->dev_cdclk =
5999                 broxton_calc_cdclk(dev_priv, max_pixclk);
6000
6001         if (!intel_state->active_crtcs)
6002                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6003
6004         return 0;
6005 }
6006
6007 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6008 {
6009         unsigned int credits, default_credits;
6010
6011         if (IS_CHERRYVIEW(dev_priv))
6012                 default_credits = PFI_CREDIT(12);
6013         else
6014                 default_credits = PFI_CREDIT(8);
6015
6016         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6017                 /* CHV suggested value is 31 or 63 */
6018                 if (IS_CHERRYVIEW(dev_priv))
6019                         credits = PFI_CREDIT_63;
6020                 else
6021                         credits = PFI_CREDIT(15);
6022         } else {
6023                 credits = default_credits;
6024         }
6025
6026         /*
6027          * WA - write default credits before re-programming
6028          * FIXME: should we also set the resend bit here?
6029          */
6030         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6031                    default_credits);
6032
6033         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6034                    credits | PFI_CREDIT_RESEND);
6035
6036         /*
6037          * FIXME is this guaranteed to clear
6038          * immediately or should we poll for it?
6039          */
6040         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6041 }
6042
6043 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6044 {
6045         struct drm_device *dev = old_state->dev;
6046         struct drm_i915_private *dev_priv = dev->dev_private;
6047         struct intel_atomic_state *old_intel_state =
6048                 to_intel_atomic_state(old_state);
6049         unsigned req_cdclk = old_intel_state->dev_cdclk;
6050
6051         /*
6052          * FIXME: We can end up here with all power domains off, yet
6053          * with a CDCLK frequency other than the minimum. To account
6054          * for this take the PIPE-A power domain, which covers the HW
6055          * blocks needed for the following programming. This can be
6056          * removed once it's guaranteed that we get here either with
6057          * the minimum CDCLK set, or the required power domains
6058          * enabled.
6059          */
6060         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6061
6062         if (IS_CHERRYVIEW(dev))
6063                 cherryview_set_cdclk(dev, req_cdclk);
6064         else
6065                 valleyview_set_cdclk(dev, req_cdclk);
6066
6067         vlv_program_pfi_credits(dev_priv);
6068
6069         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6070 }
6071
6072 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6073 {
6074         struct drm_device *dev = crtc->dev;
6075         struct drm_i915_private *dev_priv = to_i915(dev);
6076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6077         struct intel_encoder *encoder;
6078         int pipe = intel_crtc->pipe;
6079
6080         if (WARN_ON(intel_crtc->active))
6081                 return;
6082
6083         if (intel_crtc->config->has_dp_encoder)
6084                 intel_dp_set_m_n(intel_crtc, M1_N1);
6085
6086         intel_set_pipe_timings(intel_crtc);
6087         intel_set_pipe_src_size(intel_crtc);
6088
6089         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6090                 struct drm_i915_private *dev_priv = dev->dev_private;
6091
6092                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6093                 I915_WRITE(CHV_CANVAS(pipe), 0);
6094         }
6095
6096         i9xx_set_pipeconf(intel_crtc);
6097
6098         intel_crtc->active = true;
6099
6100         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6101
6102         for_each_encoder_on_crtc(dev, crtc, encoder)
6103                 if (encoder->pre_pll_enable)
6104                         encoder->pre_pll_enable(encoder);
6105
6106         if (!intel_crtc->config->has_dsi_encoder) {
6107                 if (IS_CHERRYVIEW(dev)) {
6108                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6109                         chv_enable_pll(intel_crtc, intel_crtc->config);
6110                 } else {
6111                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6112                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6113                 }
6114         }
6115
6116         for_each_encoder_on_crtc(dev, crtc, encoder)
6117                 if (encoder->pre_enable)
6118                         encoder->pre_enable(encoder);
6119
6120         i9xx_pfit_enable(intel_crtc);
6121
6122         intel_color_load_luts(crtc);
6123
6124         intel_update_watermarks(crtc);
6125         intel_enable_pipe(intel_crtc);
6126
6127         assert_vblank_disabled(crtc);
6128         drm_crtc_vblank_on(crtc);
6129
6130         for_each_encoder_on_crtc(dev, crtc, encoder)
6131                 encoder->enable(encoder);
6132 }
6133
6134 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6135 {
6136         struct drm_device *dev = crtc->base.dev;
6137         struct drm_i915_private *dev_priv = dev->dev_private;
6138
6139         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6140         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6141 }
6142
6143 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6144 {
6145         struct drm_device *dev = crtc->dev;
6146         struct drm_i915_private *dev_priv = to_i915(dev);
6147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148         struct intel_encoder *encoder;
6149         int pipe = intel_crtc->pipe;
6150
6151         if (WARN_ON(intel_crtc->active))
6152                 return;
6153
6154         i9xx_set_pll_dividers(intel_crtc);
6155
6156         if (intel_crtc->config->has_dp_encoder)
6157                 intel_dp_set_m_n(intel_crtc, M1_N1);
6158
6159         intel_set_pipe_timings(intel_crtc);
6160         intel_set_pipe_src_size(intel_crtc);
6161
6162         i9xx_set_pipeconf(intel_crtc);
6163
6164         intel_crtc->active = true;
6165
6166         if (!IS_GEN2(dev))
6167                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6168
6169         for_each_encoder_on_crtc(dev, crtc, encoder)
6170                 if (encoder->pre_enable)
6171                         encoder->pre_enable(encoder);
6172
6173         i9xx_enable_pll(intel_crtc);
6174
6175         i9xx_pfit_enable(intel_crtc);
6176
6177         intel_color_load_luts(crtc);
6178
6179         intel_update_watermarks(crtc);
6180         intel_enable_pipe(intel_crtc);
6181
6182         assert_vblank_disabled(crtc);
6183         drm_crtc_vblank_on(crtc);
6184
6185         for_each_encoder_on_crtc(dev, crtc, encoder)
6186                 encoder->enable(encoder);
6187 }
6188
6189 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6190 {
6191         struct drm_device *dev = crtc->base.dev;
6192         struct drm_i915_private *dev_priv = dev->dev_private;
6193
6194         if (!crtc->config->gmch_pfit.control)
6195                 return;
6196
6197         assert_pipe_disabled(dev_priv, crtc->pipe);
6198
6199         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6200                          I915_READ(PFIT_CONTROL));
6201         I915_WRITE(PFIT_CONTROL, 0);
6202 }
6203
6204 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6205 {
6206         struct drm_device *dev = crtc->dev;
6207         struct drm_i915_private *dev_priv = dev->dev_private;
6208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209         struct intel_encoder *encoder;
6210         int pipe = intel_crtc->pipe;
6211
6212         /*
6213          * On gen2 planes are double buffered but the pipe isn't, so we must
6214          * wait for planes to fully turn off before disabling the pipe.
6215          * We also need to wait on all gmch platforms because of the
6216          * self-refresh mode constraint explained above.
6217          */
6218         intel_wait_for_vblank(dev, pipe);
6219
6220         for_each_encoder_on_crtc(dev, crtc, encoder)
6221                 encoder->disable(encoder);
6222
6223         drm_crtc_vblank_off(crtc);
6224         assert_vblank_disabled(crtc);
6225
6226         intel_disable_pipe(intel_crtc);
6227
6228         i9xx_pfit_disable(intel_crtc);
6229
6230         for_each_encoder_on_crtc(dev, crtc, encoder)
6231                 if (encoder->post_disable)
6232                         encoder->post_disable(encoder);
6233
6234         if (!intel_crtc->config->has_dsi_encoder) {
6235                 if (IS_CHERRYVIEW(dev))
6236                         chv_disable_pll(dev_priv, pipe);
6237                 else if (IS_VALLEYVIEW(dev))
6238                         vlv_disable_pll(dev_priv, pipe);
6239                 else
6240                         i9xx_disable_pll(intel_crtc);
6241         }
6242
6243         for_each_encoder_on_crtc(dev, crtc, encoder)
6244                 if (encoder->post_pll_disable)
6245                         encoder->post_pll_disable(encoder);
6246
6247         if (!IS_GEN2(dev))
6248                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6249 }
6250
6251 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6252 {
6253         struct intel_encoder *encoder;
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6256         enum intel_display_power_domain domain;
6257         unsigned long domains;
6258
6259         if (!intel_crtc->active)
6260                 return;
6261
6262         if (to_intel_plane_state(crtc->primary->state)->visible) {
6263                 WARN_ON(intel_crtc->unpin_work);
6264
6265                 intel_pre_disable_primary_noatomic(crtc);
6266
6267                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6268                 to_intel_plane_state(crtc->primary->state)->visible = false;
6269         }
6270
6271         dev_priv->display.crtc_disable(crtc);
6272
6273         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6274                       crtc->base.id);
6275
6276         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6277         crtc->state->active = false;
6278         intel_crtc->active = false;
6279         crtc->enabled = false;
6280         crtc->state->connector_mask = 0;
6281         crtc->state->encoder_mask = 0;
6282
6283         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6284                 encoder->base.crtc = NULL;
6285
6286         intel_fbc_disable(intel_crtc);
6287         intel_update_watermarks(crtc);
6288         intel_disable_shared_dpll(intel_crtc);
6289
6290         domains = intel_crtc->enabled_power_domains;
6291         for_each_power_domain(domain, domains)
6292                 intel_display_power_put(dev_priv, domain);
6293         intel_crtc->enabled_power_domains = 0;
6294
6295         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6296         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6297 }
6298
6299 /*
6300  * turn all crtc's off, but do not adjust state
6301  * This has to be paired with a call to intel_modeset_setup_hw_state.
6302  */
6303 int intel_display_suspend(struct drm_device *dev)
6304 {
6305         struct drm_i915_private *dev_priv = to_i915(dev);
6306         struct drm_atomic_state *state;
6307         int ret;
6308
6309         state = drm_atomic_helper_suspend(dev);
6310         ret = PTR_ERR_OR_ZERO(state);
6311         if (ret)
6312                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6313         else
6314                 dev_priv->modeset_restore_state = state;
6315         return ret;
6316 }
6317
6318 void intel_encoder_destroy(struct drm_encoder *encoder)
6319 {
6320         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6321
6322         drm_encoder_cleanup(encoder);
6323         kfree(intel_encoder);
6324 }
6325
6326 /* Cross check the actual hw state with our own modeset state tracking (and it's
6327  * internal consistency). */
6328 static void intel_connector_check_state(struct intel_connector *connector)
6329 {
6330         struct drm_crtc *crtc = connector->base.state->crtc;
6331
6332         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6333                       connector->base.base.id,
6334                       connector->base.name);
6335
6336         if (connector->get_hw_state(connector)) {
6337                 struct intel_encoder *encoder = connector->encoder;
6338                 struct drm_connector_state *conn_state = connector->base.state;
6339
6340                 I915_STATE_WARN(!crtc,
6341                          "connector enabled without attached crtc\n");
6342
6343                 if (!crtc)
6344                         return;
6345
6346                 I915_STATE_WARN(!crtc->state->active,
6347                       "connector is active, but attached crtc isn't\n");
6348
6349                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6350                         return;
6351
6352                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6353                         "atomic encoder doesn't match attached encoder\n");
6354
6355                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6356                         "attached encoder crtc differs from connector crtc\n");
6357         } else {
6358                 I915_STATE_WARN(crtc && crtc->state->active,
6359                         "attached crtc is active, but connector isn't\n");
6360                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6361                         "best encoder set without crtc!\n");
6362         }
6363 }
6364
6365 int intel_connector_init(struct intel_connector *connector)
6366 {
6367         drm_atomic_helper_connector_reset(&connector->base);
6368
6369         if (!connector->base.state)
6370                 return -ENOMEM;
6371
6372         return 0;
6373 }
6374
6375 struct intel_connector *intel_connector_alloc(void)
6376 {
6377         struct intel_connector *connector;
6378
6379         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6380         if (!connector)
6381                 return NULL;
6382
6383         if (intel_connector_init(connector) < 0) {
6384                 kfree(connector);
6385                 return NULL;
6386         }
6387
6388         return connector;
6389 }
6390
6391 /* Simple connector->get_hw_state implementation for encoders that support only
6392  * one connector and no cloning and hence the encoder state determines the state
6393  * of the connector. */
6394 bool intel_connector_get_hw_state(struct intel_connector *connector)
6395 {
6396         enum pipe pipe = 0;
6397         struct intel_encoder *encoder = connector->encoder;
6398
6399         return encoder->get_hw_state(encoder, &pipe);
6400 }
6401
6402 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6403 {
6404         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6405                 return crtc_state->fdi_lanes;
6406
6407         return 0;
6408 }
6409
6410 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6411                                      struct intel_crtc_state *pipe_config)
6412 {
6413         struct drm_atomic_state *state = pipe_config->base.state;
6414         struct intel_crtc *other_crtc;
6415         struct intel_crtc_state *other_crtc_state;
6416
6417         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6418                       pipe_name(pipe), pipe_config->fdi_lanes);
6419         if (pipe_config->fdi_lanes > 4) {
6420                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6421                               pipe_name(pipe), pipe_config->fdi_lanes);
6422                 return -EINVAL;
6423         }
6424
6425         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6426                 if (pipe_config->fdi_lanes > 2) {
6427                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6428                                       pipe_config->fdi_lanes);
6429                         return -EINVAL;
6430                 } else {
6431                         return 0;
6432                 }
6433         }
6434
6435         if (INTEL_INFO(dev)->num_pipes == 2)
6436                 return 0;
6437
6438         /* Ivybridge 3 pipe is really complicated */
6439         switch (pipe) {
6440         case PIPE_A:
6441                 return 0;
6442         case PIPE_B:
6443                 if (pipe_config->fdi_lanes <= 2)
6444                         return 0;
6445
6446                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6447                 other_crtc_state =
6448                         intel_atomic_get_crtc_state(state, other_crtc);
6449                 if (IS_ERR(other_crtc_state))
6450                         return PTR_ERR(other_crtc_state);
6451
6452                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6453                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6454                                       pipe_name(pipe), pipe_config->fdi_lanes);
6455                         return -EINVAL;
6456                 }
6457                 return 0;
6458         case PIPE_C:
6459                 if (pipe_config->fdi_lanes > 2) {
6460                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6461                                       pipe_name(pipe), pipe_config->fdi_lanes);
6462                         return -EINVAL;
6463                 }
6464
6465                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6466                 other_crtc_state =
6467                         intel_atomic_get_crtc_state(state, other_crtc);
6468                 if (IS_ERR(other_crtc_state))
6469                         return PTR_ERR(other_crtc_state);
6470
6471                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6472                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6473                         return -EINVAL;
6474                 }
6475                 return 0;
6476         default:
6477                 BUG();
6478         }
6479 }
6480
6481 #define RETRY 1
6482 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6483                                        struct intel_crtc_state *pipe_config)
6484 {
6485         struct drm_device *dev = intel_crtc->base.dev;
6486         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6487         int lane, link_bw, fdi_dotclock, ret;
6488         bool needs_recompute = false;
6489
6490 retry:
6491         /* FDI is a binary signal running at ~2.7GHz, encoding
6492          * each output octet as 10 bits. The actual frequency
6493          * is stored as a divider into a 100MHz clock, and the
6494          * mode pixel clock is stored in units of 1KHz.
6495          * Hence the bw of each lane in terms of the mode signal
6496          * is:
6497          */
6498         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6499
6500         fdi_dotclock = adjusted_mode->crtc_clock;
6501
6502         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6503                                            pipe_config->pipe_bpp);
6504
6505         pipe_config->fdi_lanes = lane;
6506
6507         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6508                                link_bw, &pipe_config->fdi_m_n);
6509
6510         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6511         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6512                 pipe_config->pipe_bpp -= 2*3;
6513                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6514                               pipe_config->pipe_bpp);
6515                 needs_recompute = true;
6516                 pipe_config->bw_constrained = true;
6517
6518                 goto retry;
6519         }
6520
6521         if (needs_recompute)
6522                 return RETRY;
6523
6524         return ret;
6525 }
6526
6527 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6528                                      struct intel_crtc_state *pipe_config)
6529 {
6530         if (pipe_config->pipe_bpp > 24)
6531                 return false;
6532
6533         /* HSW can handle pixel rate up to cdclk? */
6534         if (IS_HASWELL(dev_priv->dev))
6535                 return true;
6536
6537         /*
6538          * We compare against max which means we must take
6539          * the increased cdclk requirement into account when
6540          * calculating the new cdclk.
6541          *
6542          * Should measure whether using a lower cdclk w/o IPS
6543          */
6544         return ilk_pipe_pixel_rate(pipe_config) <=
6545                 dev_priv->max_cdclk_freq * 95 / 100;
6546 }
6547
6548 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6549                                    struct intel_crtc_state *pipe_config)
6550 {
6551         struct drm_device *dev = crtc->base.dev;
6552         struct drm_i915_private *dev_priv = dev->dev_private;
6553
6554         pipe_config->ips_enabled = i915.enable_ips &&
6555                 hsw_crtc_supports_ips(crtc) &&
6556                 pipe_config_supports_ips(dev_priv, pipe_config);
6557 }
6558
6559 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6560 {
6561         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6562
6563         /* GDG double wide on either pipe, otherwise pipe A only */
6564         return INTEL_INFO(dev_priv)->gen < 4 &&
6565                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6566 }
6567
6568 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6569                                      struct intel_crtc_state *pipe_config)
6570 {
6571         struct drm_device *dev = crtc->base.dev;
6572         struct drm_i915_private *dev_priv = dev->dev_private;
6573         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6574
6575         /* FIXME should check pixel clock limits on all platforms */
6576         if (INTEL_INFO(dev)->gen < 4) {
6577                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6578
6579                 /*
6580                  * Enable double wide mode when the dot clock
6581                  * is > 90% of the (display) core speed.
6582                  */
6583                 if (intel_crtc_supports_double_wide(crtc) &&
6584                     adjusted_mode->crtc_clock > clock_limit) {
6585                         clock_limit *= 2;
6586                         pipe_config->double_wide = true;
6587                 }
6588
6589                 if (adjusted_mode->crtc_clock > clock_limit) {
6590                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6591                                       adjusted_mode->crtc_clock, clock_limit,
6592                                       yesno(pipe_config->double_wide));
6593                         return -EINVAL;
6594                 }
6595         }
6596
6597         /*
6598          * Pipe horizontal size must be even in:
6599          * - DVO ganged mode
6600          * - LVDS dual channel mode
6601          * - Double wide pipe
6602          */
6603         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6604              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6605                 pipe_config->pipe_src_w &= ~1;
6606
6607         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6608          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6609          */
6610         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6611                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6612                 return -EINVAL;
6613
6614         if (HAS_IPS(dev))
6615                 hsw_compute_ips_config(crtc, pipe_config);
6616
6617         if (pipe_config->has_pch_encoder)
6618                 return ironlake_fdi_compute_config(crtc, pipe_config);
6619
6620         return 0;
6621 }
6622
6623 static int skylake_get_display_clock_speed(struct drm_device *dev)
6624 {
6625         struct drm_i915_private *dev_priv = to_i915(dev);
6626         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6627         uint32_t cdctl = I915_READ(CDCLK_CTL);
6628         uint32_t linkrate;
6629
6630         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6631                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6632
6633         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6634                 return 540000;
6635
6636         linkrate = (I915_READ(DPLL_CTRL1) &
6637                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6638
6639         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6640             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6641                 /* vco 8640 */
6642                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6643                 case CDCLK_FREQ_450_432:
6644                         return 432000;
6645                 case CDCLK_FREQ_337_308:
6646                         return 308570;
6647                 case CDCLK_FREQ_675_617:
6648                         return 617140;
6649                 default:
6650                         WARN(1, "Unknown cd freq selection\n");
6651                 }
6652         } else {
6653                 /* vco 8100 */
6654                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6655                 case CDCLK_FREQ_450_432:
6656                         return 450000;
6657                 case CDCLK_FREQ_337_308:
6658                         return 337500;
6659                 case CDCLK_FREQ_675_617:
6660                         return 675000;
6661                 default:
6662                         WARN(1, "Unknown cd freq selection\n");
6663                 }
6664         }
6665
6666         /* error case, do as if DPLL0 isn't enabled */
6667         return 24000;
6668 }
6669
6670 static int broxton_get_display_clock_speed(struct drm_device *dev)
6671 {
6672         struct drm_i915_private *dev_priv = to_i915(dev);
6673         uint32_t cdctl = I915_READ(CDCLK_CTL);
6674         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6675         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6676         int cdclk;
6677
6678         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6679                 return 19200;
6680
6681         cdclk = 19200 * pll_ratio / 2;
6682
6683         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6684         case BXT_CDCLK_CD2X_DIV_SEL_1:
6685                 return cdclk;  /* 576MHz or 624MHz */
6686         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6687                 return cdclk * 2 / 3; /* 384MHz */
6688         case BXT_CDCLK_CD2X_DIV_SEL_2:
6689                 return cdclk / 2; /* 288MHz */
6690         case BXT_CDCLK_CD2X_DIV_SEL_4:
6691                 return cdclk / 4; /* 144MHz */
6692         }
6693
6694         /* error case, do as if DE PLL isn't enabled */
6695         return 19200;
6696 }
6697
6698 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6699 {
6700         struct drm_i915_private *dev_priv = dev->dev_private;
6701         uint32_t lcpll = I915_READ(LCPLL_CTL);
6702         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6703
6704         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6705                 return 800000;
6706         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6707                 return 450000;
6708         else if (freq == LCPLL_CLK_FREQ_450)
6709                 return 450000;
6710         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6711                 return 540000;
6712         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6713                 return 337500;
6714         else
6715                 return 675000;
6716 }
6717
6718 static int haswell_get_display_clock_speed(struct drm_device *dev)
6719 {
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         uint32_t lcpll = I915_READ(LCPLL_CTL);
6722         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6723
6724         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6725                 return 800000;
6726         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6727                 return 450000;
6728         else if (freq == LCPLL_CLK_FREQ_450)
6729                 return 450000;
6730         else if (IS_HSW_ULT(dev))
6731                 return 337500;
6732         else
6733                 return 540000;
6734 }
6735
6736 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6737 {
6738         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6739                                       CCK_DISPLAY_CLOCK_CONTROL);
6740 }
6741
6742 static int ilk_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         return 450000;
6745 }
6746
6747 static int i945_get_display_clock_speed(struct drm_device *dev)
6748 {
6749         return 400000;
6750 }
6751
6752 static int i915_get_display_clock_speed(struct drm_device *dev)
6753 {
6754         return 333333;
6755 }
6756
6757 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6758 {
6759         return 200000;
6760 }
6761
6762 static int pnv_get_display_clock_speed(struct drm_device *dev)
6763 {
6764         u16 gcfgc = 0;
6765
6766         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6767
6768         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6769         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6770                 return 266667;
6771         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6772                 return 333333;
6773         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6774                 return 444444;
6775         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6776                 return 200000;
6777         default:
6778                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6779         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6780                 return 133333;
6781         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6782                 return 166667;
6783         }
6784 }
6785
6786 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6787 {
6788         u16 gcfgc = 0;
6789
6790         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6791
6792         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6793                 return 133333;
6794         else {
6795                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796                 case GC_DISPLAY_CLOCK_333_MHZ:
6797                         return 333333;
6798                 default:
6799                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6800                         return 190000;
6801                 }
6802         }
6803 }
6804
6805 static int i865_get_display_clock_speed(struct drm_device *dev)
6806 {
6807         return 266667;
6808 }
6809
6810 static int i85x_get_display_clock_speed(struct drm_device *dev)
6811 {
6812         u16 hpllcc = 0;
6813
6814         /*
6815          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6816          * encoding is different :(
6817          * FIXME is this the right way to detect 852GM/852GMV?
6818          */
6819         if (dev->pdev->revision == 0x1)
6820                 return 133333;
6821
6822         pci_bus_read_config_word(dev->pdev->bus,
6823                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6824
6825         /* Assume that the hardware is in the high speed state.  This
6826          * should be the default.
6827          */
6828         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6829         case GC_CLOCK_133_200:
6830         case GC_CLOCK_133_200_2:
6831         case GC_CLOCK_100_200:
6832                 return 200000;
6833         case GC_CLOCK_166_250:
6834                 return 250000;
6835         case GC_CLOCK_100_133:
6836                 return 133333;
6837         case GC_CLOCK_133_266:
6838         case GC_CLOCK_133_266_2:
6839         case GC_CLOCK_166_266:
6840                 return 266667;
6841         }
6842
6843         /* Shouldn't happen */
6844         return 0;
6845 }
6846
6847 static int i830_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         return 133333;
6850 }
6851
6852 static unsigned int intel_hpll_vco(struct drm_device *dev)
6853 {
6854         struct drm_i915_private *dev_priv = dev->dev_private;
6855         static const unsigned int blb_vco[8] = {
6856                 [0] = 3200000,
6857                 [1] = 4000000,
6858                 [2] = 5333333,
6859                 [3] = 4800000,
6860                 [4] = 6400000,
6861         };
6862         static const unsigned int pnv_vco[8] = {
6863                 [0] = 3200000,
6864                 [1] = 4000000,
6865                 [2] = 5333333,
6866                 [3] = 4800000,
6867                 [4] = 2666667,
6868         };
6869         static const unsigned int cl_vco[8] = {
6870                 [0] = 3200000,
6871                 [1] = 4000000,
6872                 [2] = 5333333,
6873                 [3] = 6400000,
6874                 [4] = 3333333,
6875                 [5] = 3566667,
6876                 [6] = 4266667,
6877         };
6878         static const unsigned int elk_vco[8] = {
6879                 [0] = 3200000,
6880                 [1] = 4000000,
6881                 [2] = 5333333,
6882                 [3] = 4800000,
6883         };
6884         static const unsigned int ctg_vco[8] = {
6885                 [0] = 3200000,
6886                 [1] = 4000000,
6887                 [2] = 5333333,
6888                 [3] = 6400000,
6889                 [4] = 2666667,
6890                 [5] = 4266667,
6891         };
6892         const unsigned int *vco_table;
6893         unsigned int vco;
6894         uint8_t tmp = 0;
6895
6896         /* FIXME other chipsets? */
6897         if (IS_GM45(dev))
6898                 vco_table = ctg_vco;
6899         else if (IS_G4X(dev))
6900                 vco_table = elk_vco;
6901         else if (IS_CRESTLINE(dev))
6902                 vco_table = cl_vco;
6903         else if (IS_PINEVIEW(dev))
6904                 vco_table = pnv_vco;
6905         else if (IS_G33(dev))
6906                 vco_table = blb_vco;
6907         else
6908                 return 0;
6909
6910         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6911
6912         vco = vco_table[tmp & 0x7];
6913         if (vco == 0)
6914                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6915         else
6916                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6917
6918         return vco;
6919 }
6920
6921 static int gm45_get_display_clock_speed(struct drm_device *dev)
6922 {
6923         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6924         uint16_t tmp = 0;
6925
6926         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6927
6928         cdclk_sel = (tmp >> 12) & 0x1;
6929
6930         switch (vco) {
6931         case 2666667:
6932         case 4000000:
6933         case 5333333:
6934                 return cdclk_sel ? 333333 : 222222;
6935         case 3200000:
6936                 return cdclk_sel ? 320000 : 228571;
6937         default:
6938                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6939                 return 222222;
6940         }
6941 }
6942
6943 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6944 {
6945         static const uint8_t div_3200[] = { 16, 10,  8 };
6946         static const uint8_t div_4000[] = { 20, 12, 10 };
6947         static const uint8_t div_5333[] = { 24, 16, 14 };
6948         const uint8_t *div_table;
6949         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6950         uint16_t tmp = 0;
6951
6952         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6953
6954         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6955
6956         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6957                 goto fail;
6958
6959         switch (vco) {
6960         case 3200000:
6961                 div_table = div_3200;
6962                 break;
6963         case 4000000:
6964                 div_table = div_4000;
6965                 break;
6966         case 5333333:
6967                 div_table = div_5333;
6968                 break;
6969         default:
6970                 goto fail;
6971         }
6972
6973         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6974
6975 fail:
6976         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6977         return 200000;
6978 }
6979
6980 static int g33_get_display_clock_speed(struct drm_device *dev)
6981 {
6982         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6983         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6984         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6985         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6986         const uint8_t *div_table;
6987         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6988         uint16_t tmp = 0;
6989
6990         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6991
6992         cdclk_sel = (tmp >> 4) & 0x7;
6993
6994         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6995                 goto fail;
6996
6997         switch (vco) {
6998         case 3200000:
6999                 div_table = div_3200;
7000                 break;
7001         case 4000000:
7002                 div_table = div_4000;
7003                 break;
7004         case 4800000:
7005                 div_table = div_4800;
7006                 break;
7007         case 5333333:
7008                 div_table = div_5333;
7009                 break;
7010         default:
7011                 goto fail;
7012         }
7013
7014         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7015
7016 fail:
7017         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7018         return 190476;
7019 }
7020
7021 static void
7022 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7023 {
7024         while (*num > DATA_LINK_M_N_MASK ||
7025                *den > DATA_LINK_M_N_MASK) {
7026                 *num >>= 1;
7027                 *den >>= 1;
7028         }
7029 }
7030
7031 static void compute_m_n(unsigned int m, unsigned int n,
7032                         uint32_t *ret_m, uint32_t *ret_n)
7033 {
7034         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7035         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7036         intel_reduce_m_n_ratio(ret_m, ret_n);
7037 }
7038
7039 void
7040 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7041                        int pixel_clock, int link_clock,
7042                        struct intel_link_m_n *m_n)
7043 {
7044         m_n->tu = 64;
7045
7046         compute_m_n(bits_per_pixel * pixel_clock,
7047                     link_clock * nlanes * 8,
7048                     &m_n->gmch_m, &m_n->gmch_n);
7049
7050         compute_m_n(pixel_clock, link_clock,
7051                     &m_n->link_m, &m_n->link_n);
7052 }
7053
7054 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7055 {
7056         if (i915.panel_use_ssc >= 0)
7057                 return i915.panel_use_ssc != 0;
7058         return dev_priv->vbt.lvds_use_ssc
7059                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7060 }
7061
7062 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7063                            int num_connectors)
7064 {
7065         struct drm_device *dev = crtc_state->base.crtc->dev;
7066         struct drm_i915_private *dev_priv = dev->dev_private;
7067         int refclk;
7068
7069         WARN_ON(!crtc_state->base.state);
7070
7071         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7072                 refclk = 100000;
7073         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7074             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7075                 refclk = dev_priv->vbt.lvds_ssc_freq;
7076                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7077         } else if (!IS_GEN2(dev)) {
7078                 refclk = 96000;
7079         } else {
7080                 refclk = 48000;
7081         }
7082
7083         return refclk;
7084 }
7085
7086 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7087 {
7088         return (1 << dpll->n) << 16 | dpll->m2;
7089 }
7090
7091 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7092 {
7093         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7094 }
7095
7096 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7097                                      struct intel_crtc_state *crtc_state,
7098                                      intel_clock_t *reduced_clock)
7099 {
7100         struct drm_device *dev = crtc->base.dev;
7101         u32 fp, fp2 = 0;
7102
7103         if (IS_PINEVIEW(dev)) {
7104                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7105                 if (reduced_clock)
7106                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7107         } else {
7108                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7109                 if (reduced_clock)
7110                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7111         }
7112
7113         crtc_state->dpll_hw_state.fp0 = fp;
7114
7115         crtc->lowfreq_avail = false;
7116         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7117             reduced_clock) {
7118                 crtc_state->dpll_hw_state.fp1 = fp2;
7119                 crtc->lowfreq_avail = true;
7120         } else {
7121                 crtc_state->dpll_hw_state.fp1 = fp;
7122         }
7123 }
7124
7125 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7126                 pipe)
7127 {
7128         u32 reg_val;
7129
7130         /*
7131          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7132          * and set it to a reasonable value instead.
7133          */
7134         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7135         reg_val &= 0xffffff00;
7136         reg_val |= 0x00000030;
7137         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7138
7139         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7140         reg_val &= 0x8cffffff;
7141         reg_val = 0x8c000000;
7142         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7143
7144         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7145         reg_val &= 0xffffff00;
7146         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7147
7148         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7149         reg_val &= 0x00ffffff;
7150         reg_val |= 0xb0000000;
7151         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7152 }
7153
7154 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7155                                          struct intel_link_m_n *m_n)
7156 {
7157         struct drm_device *dev = crtc->base.dev;
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159         int pipe = crtc->pipe;
7160
7161         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7162         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7163         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7164         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7165 }
7166
7167 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7168                                          struct intel_link_m_n *m_n,
7169                                          struct intel_link_m_n *m2_n2)
7170 {
7171         struct drm_device *dev = crtc->base.dev;
7172         struct drm_i915_private *dev_priv = dev->dev_private;
7173         int pipe = crtc->pipe;
7174         enum transcoder transcoder = crtc->config->cpu_transcoder;
7175
7176         if (INTEL_INFO(dev)->gen >= 5) {
7177                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7178                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7179                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7180                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7181                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7182                  * for gen < 8) and if DRRS is supported (to make sure the
7183                  * registers are not unnecessarily accessed).
7184                  */
7185                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7186                         crtc->config->has_drrs) {
7187                         I915_WRITE(PIPE_DATA_M2(transcoder),
7188                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7189                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7190                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7191                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7192                 }
7193         } else {
7194                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7195                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7196                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7197                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7198         }
7199 }
7200
7201 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7202 {
7203         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7204
7205         if (m_n == M1_N1) {
7206                 dp_m_n = &crtc->config->dp_m_n;
7207                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7208         } else if (m_n == M2_N2) {
7209
7210                 /*
7211                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7212                  * needs to be programmed into M1_N1.
7213                  */
7214                 dp_m_n = &crtc->config->dp_m2_n2;
7215         } else {
7216                 DRM_ERROR("Unsupported divider value\n");
7217                 return;
7218         }
7219
7220         if (crtc->config->has_pch_encoder)
7221                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7222         else
7223                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7224 }
7225
7226 static void vlv_compute_dpll(struct intel_crtc *crtc,
7227                              struct intel_crtc_state *pipe_config)
7228 {
7229         u32 dpll, dpll_md;
7230
7231         /*
7232          * Enable DPIO clock input. We should never disable the reference
7233          * clock for pipe B, since VGA hotplug / manual detection depends
7234          * on it.
7235          */
7236         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7237                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7238         /* We should never disable this, set it here for state tracking */
7239         if (crtc->pipe == PIPE_B)
7240                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7241         dpll |= DPLL_VCO_ENABLE;
7242         pipe_config->dpll_hw_state.dpll = dpll;
7243
7244         dpll_md = (pipe_config->pixel_multiplier - 1)
7245                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7246         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7247 }
7248
7249 static void vlv_prepare_pll(struct intel_crtc *crtc,
7250                             const struct intel_crtc_state *pipe_config)
7251 {
7252         struct drm_device *dev = crtc->base.dev;
7253         struct drm_i915_private *dev_priv = dev->dev_private;
7254         int pipe = crtc->pipe;
7255         u32 mdiv;
7256         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7257         u32 coreclk, reg_val;
7258
7259         mutex_lock(&dev_priv->sb_lock);
7260
7261         bestn = pipe_config->dpll.n;
7262         bestm1 = pipe_config->dpll.m1;
7263         bestm2 = pipe_config->dpll.m2;
7264         bestp1 = pipe_config->dpll.p1;
7265         bestp2 = pipe_config->dpll.p2;
7266
7267         /* See eDP HDMI DPIO driver vbios notes doc */
7268
7269         /* PLL B needs special handling */
7270         if (pipe == PIPE_B)
7271                 vlv_pllb_recal_opamp(dev_priv, pipe);
7272
7273         /* Set up Tx target for periodic Rcomp update */
7274         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7275
7276         /* Disable target IRef on PLL */
7277         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7278         reg_val &= 0x00ffffff;
7279         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7280
7281         /* Disable fast lock */
7282         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7283
7284         /* Set idtafcrecal before PLL is enabled */
7285         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7286         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7287         mdiv |= ((bestn << DPIO_N_SHIFT));
7288         mdiv |= (1 << DPIO_K_SHIFT);
7289
7290         /*
7291          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7292          * but we don't support that).
7293          * Note: don't use the DAC post divider as it seems unstable.
7294          */
7295         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7296         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7297
7298         mdiv |= DPIO_ENABLE_CALIBRATION;
7299         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7300
7301         /* Set HBR and RBR LPF coefficients */
7302         if (pipe_config->port_clock == 162000 ||
7303             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7304             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7305                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7306                                  0x009f0003);
7307         else
7308                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7309                                  0x00d0000f);
7310
7311         if (pipe_config->has_dp_encoder) {
7312                 /* Use SSC source */
7313                 if (pipe == PIPE_A)
7314                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7315                                          0x0df40000);
7316                 else
7317                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7318                                          0x0df70000);
7319         } else { /* HDMI or VGA */
7320                 /* Use bend source */
7321                 if (pipe == PIPE_A)
7322                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7323                                          0x0df70000);
7324                 else
7325                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7326                                          0x0df40000);
7327         }
7328
7329         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7330         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7331         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7332             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7333                 coreclk |= 0x01000000;
7334         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7335
7336         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7337         mutex_unlock(&dev_priv->sb_lock);
7338 }
7339
7340 static void chv_compute_dpll(struct intel_crtc *crtc,
7341                              struct intel_crtc_state *pipe_config)
7342 {
7343         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7344                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7345                 DPLL_VCO_ENABLE;
7346         if (crtc->pipe != PIPE_A)
7347                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7348
7349         pipe_config->dpll_hw_state.dpll_md =
7350                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7351 }
7352
7353 static void chv_prepare_pll(struct intel_crtc *crtc,
7354                             const struct intel_crtc_state *pipe_config)
7355 {
7356         struct drm_device *dev = crtc->base.dev;
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         int pipe = crtc->pipe;
7359         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7360         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7361         u32 loopfilter, tribuf_calcntr;
7362         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7363         u32 dpio_val;
7364         int vco;
7365
7366         bestn = pipe_config->dpll.n;
7367         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7368         bestm1 = pipe_config->dpll.m1;
7369         bestm2 = pipe_config->dpll.m2 >> 22;
7370         bestp1 = pipe_config->dpll.p1;
7371         bestp2 = pipe_config->dpll.p2;
7372         vco = pipe_config->dpll.vco;
7373         dpio_val = 0;
7374         loopfilter = 0;
7375
7376         /*
7377          * Enable Refclk and SSC
7378          */
7379         I915_WRITE(dpll_reg,
7380                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7381
7382         mutex_lock(&dev_priv->sb_lock);
7383
7384         /* p1 and p2 divider */
7385         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7386                         5 << DPIO_CHV_S1_DIV_SHIFT |
7387                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7388                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7389                         1 << DPIO_CHV_K_DIV_SHIFT);
7390
7391         /* Feedback post-divider - m2 */
7392         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7393
7394         /* Feedback refclk divider - n and m1 */
7395         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7396                         DPIO_CHV_M1_DIV_BY_2 |
7397                         1 << DPIO_CHV_N_DIV_SHIFT);
7398
7399         /* M2 fraction division */
7400         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7401
7402         /* M2 fraction division enable */
7403         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7404         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7405         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7406         if (bestm2_frac)
7407                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7408         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7409
7410         /* Program digital lock detect threshold */
7411         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7412         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7413                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7414         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7415         if (!bestm2_frac)
7416                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7417         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7418
7419         /* Loop filter */
7420         if (vco == 5400000) {
7421                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7422                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7423                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424                 tribuf_calcntr = 0x9;
7425         } else if (vco <= 6200000) {
7426                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7427                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7428                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7429                 tribuf_calcntr = 0x9;
7430         } else if (vco <= 6480000) {
7431                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7432                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7433                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7434                 tribuf_calcntr = 0x8;
7435         } else {
7436                 /* Not supported. Apply the same limits as in the max case */
7437                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7438                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7439                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440                 tribuf_calcntr = 0;
7441         }
7442         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7443
7444         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7445         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7446         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7447         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7448
7449         /* AFC Recal */
7450         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7451                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7452                         DPIO_AFC_RECAL);
7453
7454         mutex_unlock(&dev_priv->sb_lock);
7455 }
7456
7457 /**
7458  * vlv_force_pll_on - forcibly enable just the PLL
7459  * @dev_priv: i915 private structure
7460  * @pipe: pipe PLL to enable
7461  * @dpll: PLL configuration
7462  *
7463  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7464  * in cases where we need the PLL enabled even when @pipe is not going to
7465  * be enabled.
7466  */
7467 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7468                      const struct dpll *dpll)
7469 {
7470         struct intel_crtc *crtc =
7471                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7472         struct intel_crtc_state *pipe_config;
7473
7474         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7475         if (!pipe_config)
7476                 return -ENOMEM;
7477
7478         pipe_config->base.crtc = &crtc->base;
7479         pipe_config->pixel_multiplier = 1;
7480         pipe_config->dpll = *dpll;
7481
7482         if (IS_CHERRYVIEW(dev)) {
7483                 chv_compute_dpll(crtc, pipe_config);
7484                 chv_prepare_pll(crtc, pipe_config);
7485                 chv_enable_pll(crtc, pipe_config);
7486         } else {
7487                 vlv_compute_dpll(crtc, pipe_config);
7488                 vlv_prepare_pll(crtc, pipe_config);
7489                 vlv_enable_pll(crtc, pipe_config);
7490         }
7491
7492         kfree(pipe_config);
7493
7494         return 0;
7495 }
7496
7497 /**
7498  * vlv_force_pll_off - forcibly disable just the PLL
7499  * @dev_priv: i915 private structure
7500  * @pipe: pipe PLL to disable
7501  *
7502  * Disable the PLL for @pipe. To be used in cases where we need
7503  * the PLL enabled even when @pipe is not going to be enabled.
7504  */
7505 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7506 {
7507         if (IS_CHERRYVIEW(dev))
7508                 chv_disable_pll(to_i915(dev), pipe);
7509         else
7510                 vlv_disable_pll(to_i915(dev), pipe);
7511 }
7512
7513 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7514                               struct intel_crtc_state *crtc_state,
7515                               intel_clock_t *reduced_clock,
7516                               int num_connectors)
7517 {
7518         struct drm_device *dev = crtc->base.dev;
7519         struct drm_i915_private *dev_priv = dev->dev_private;
7520         u32 dpll;
7521         bool is_sdvo;
7522         struct dpll *clock = &crtc_state->dpll;
7523
7524         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7525
7526         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7527                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7528
7529         dpll = DPLL_VGA_MODE_DIS;
7530
7531         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7532                 dpll |= DPLLB_MODE_LVDS;
7533         else
7534                 dpll |= DPLLB_MODE_DAC_SERIAL;
7535
7536         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7537                 dpll |= (crtc_state->pixel_multiplier - 1)
7538                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7539         }
7540
7541         if (is_sdvo)
7542                 dpll |= DPLL_SDVO_HIGH_SPEED;
7543
7544         if (crtc_state->has_dp_encoder)
7545                 dpll |= DPLL_SDVO_HIGH_SPEED;
7546
7547         /* compute bitmask from p1 value */
7548         if (IS_PINEVIEW(dev))
7549                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7550         else {
7551                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7552                 if (IS_G4X(dev) && reduced_clock)
7553                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7554         }
7555         switch (clock->p2) {
7556         case 5:
7557                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7558                 break;
7559         case 7:
7560                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7561                 break;
7562         case 10:
7563                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7564                 break;
7565         case 14:
7566                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7567                 break;
7568         }
7569         if (INTEL_INFO(dev)->gen >= 4)
7570                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7571
7572         if (crtc_state->sdvo_tv_clock)
7573                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7574         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7575                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7576                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7577         else
7578                 dpll |= PLL_REF_INPUT_DREFCLK;
7579
7580         dpll |= DPLL_VCO_ENABLE;
7581         crtc_state->dpll_hw_state.dpll = dpll;
7582
7583         if (INTEL_INFO(dev)->gen >= 4) {
7584                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7585                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7586                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7587         }
7588 }
7589
7590 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7591                               struct intel_crtc_state *crtc_state,
7592                               intel_clock_t *reduced_clock,
7593                               int num_connectors)
7594 {
7595         struct drm_device *dev = crtc->base.dev;
7596         struct drm_i915_private *dev_priv = dev->dev_private;
7597         u32 dpll;
7598         struct dpll *clock = &crtc_state->dpll;
7599
7600         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7601
7602         dpll = DPLL_VGA_MODE_DIS;
7603
7604         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7605                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7606         } else {
7607                 if (clock->p1 == 2)
7608                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7609                 else
7610                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611                 if (clock->p2 == 4)
7612                         dpll |= PLL_P2_DIVIDE_BY_4;
7613         }
7614
7615         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7616                 dpll |= DPLL_DVO_2X_MODE;
7617
7618         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7619                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7620                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7621         else
7622                 dpll |= PLL_REF_INPUT_DREFCLK;
7623
7624         dpll |= DPLL_VCO_ENABLE;
7625         crtc_state->dpll_hw_state.dpll = dpll;
7626 }
7627
7628 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7629 {
7630         struct drm_device *dev = intel_crtc->base.dev;
7631         struct drm_i915_private *dev_priv = dev->dev_private;
7632         enum pipe pipe = intel_crtc->pipe;
7633         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7634         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7635         uint32_t crtc_vtotal, crtc_vblank_end;
7636         int vsyncshift = 0;
7637
7638         /* We need to be careful not to changed the adjusted mode, for otherwise
7639          * the hw state checker will get angry at the mismatch. */
7640         crtc_vtotal = adjusted_mode->crtc_vtotal;
7641         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7642
7643         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7644                 /* the chip adds 2 halflines automatically */
7645                 crtc_vtotal -= 1;
7646                 crtc_vblank_end -= 1;
7647
7648                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7649                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7650                 else
7651                         vsyncshift = adjusted_mode->crtc_hsync_start -
7652                                 adjusted_mode->crtc_htotal / 2;
7653                 if (vsyncshift < 0)
7654                         vsyncshift += adjusted_mode->crtc_htotal;
7655         }
7656
7657         if (INTEL_INFO(dev)->gen > 3)
7658                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7659
7660         I915_WRITE(HTOTAL(cpu_transcoder),
7661                    (adjusted_mode->crtc_hdisplay - 1) |
7662                    ((adjusted_mode->crtc_htotal - 1) << 16));
7663         I915_WRITE(HBLANK(cpu_transcoder),
7664                    (adjusted_mode->crtc_hblank_start - 1) |
7665                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7666         I915_WRITE(HSYNC(cpu_transcoder),
7667                    (adjusted_mode->crtc_hsync_start - 1) |
7668                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7669
7670         I915_WRITE(VTOTAL(cpu_transcoder),
7671                    (adjusted_mode->crtc_vdisplay - 1) |
7672                    ((crtc_vtotal - 1) << 16));
7673         I915_WRITE(VBLANK(cpu_transcoder),
7674                    (adjusted_mode->crtc_vblank_start - 1) |
7675                    ((crtc_vblank_end - 1) << 16));
7676         I915_WRITE(VSYNC(cpu_transcoder),
7677                    (adjusted_mode->crtc_vsync_start - 1) |
7678                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7679
7680         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7681          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7682          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7683          * bits. */
7684         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7685             (pipe == PIPE_B || pipe == PIPE_C))
7686                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7687
7688 }
7689
7690 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7691 {
7692         struct drm_device *dev = intel_crtc->base.dev;
7693         struct drm_i915_private *dev_priv = dev->dev_private;
7694         enum pipe pipe = intel_crtc->pipe;
7695
7696         /* pipesrc controls the size that is scaled from, which should
7697          * always be the user's requested size.
7698          */
7699         I915_WRITE(PIPESRC(pipe),
7700                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7701                    (intel_crtc->config->pipe_src_h - 1));
7702 }
7703
7704 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7705                                    struct intel_crtc_state *pipe_config)
7706 {
7707         struct drm_device *dev = crtc->base.dev;
7708         struct drm_i915_private *dev_priv = dev->dev_private;
7709         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7710         uint32_t tmp;
7711
7712         tmp = I915_READ(HTOTAL(cpu_transcoder));
7713         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7714         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7715         tmp = I915_READ(HBLANK(cpu_transcoder));
7716         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7717         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7718         tmp = I915_READ(HSYNC(cpu_transcoder));
7719         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7720         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7721
7722         tmp = I915_READ(VTOTAL(cpu_transcoder));
7723         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7724         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7725         tmp = I915_READ(VBLANK(cpu_transcoder));
7726         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7727         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7728         tmp = I915_READ(VSYNC(cpu_transcoder));
7729         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7730         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7731
7732         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7733                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7734                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7735                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7736         }
7737 }
7738
7739 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7740                                     struct intel_crtc_state *pipe_config)
7741 {
7742         struct drm_device *dev = crtc->base.dev;
7743         struct drm_i915_private *dev_priv = dev->dev_private;
7744         u32 tmp;
7745
7746         tmp = I915_READ(PIPESRC(crtc->pipe));
7747         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7748         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7749
7750         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7751         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7752 }
7753
7754 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7755                                  struct intel_crtc_state *pipe_config)
7756 {
7757         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7758         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7759         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7760         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7761
7762         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7763         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7764         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7765         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7766
7767         mode->flags = pipe_config->base.adjusted_mode.flags;
7768         mode->type = DRM_MODE_TYPE_DRIVER;
7769
7770         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7771         mode->flags |= pipe_config->base.adjusted_mode.flags;
7772
7773         mode->hsync = drm_mode_hsync(mode);
7774         mode->vrefresh = drm_mode_vrefresh(mode);
7775         drm_mode_set_name(mode);
7776 }
7777
7778 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7779 {
7780         struct drm_device *dev = intel_crtc->base.dev;
7781         struct drm_i915_private *dev_priv = dev->dev_private;
7782         uint32_t pipeconf;
7783
7784         pipeconf = 0;
7785
7786         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7787             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7788                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7789
7790         if (intel_crtc->config->double_wide)
7791                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7792
7793         /* only g4x and later have fancy bpc/dither controls */
7794         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7795                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7796                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7797                         pipeconf |= PIPECONF_DITHER_EN |
7798                                     PIPECONF_DITHER_TYPE_SP;
7799
7800                 switch (intel_crtc->config->pipe_bpp) {
7801                 case 18:
7802                         pipeconf |= PIPECONF_6BPC;
7803                         break;
7804                 case 24:
7805                         pipeconf |= PIPECONF_8BPC;
7806                         break;
7807                 case 30:
7808                         pipeconf |= PIPECONF_10BPC;
7809                         break;
7810                 default:
7811                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7812                         BUG();
7813                 }
7814         }
7815
7816         if (HAS_PIPE_CXSR(dev)) {
7817                 if (intel_crtc->lowfreq_avail) {
7818                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7819                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7820                 } else {
7821                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7822                 }
7823         }
7824
7825         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7826                 if (INTEL_INFO(dev)->gen < 4 ||
7827                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7828                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7829                 else
7830                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7831         } else
7832                 pipeconf |= PIPECONF_PROGRESSIVE;
7833
7834         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7835              intel_crtc->config->limited_color_range)
7836                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7837
7838         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7839         POSTING_READ(PIPECONF(intel_crtc->pipe));
7840 }
7841
7842 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7843                                    struct intel_crtc_state *crtc_state)
7844 {
7845         struct drm_device *dev = crtc->base.dev;
7846         struct drm_i915_private *dev_priv = dev->dev_private;
7847         int refclk, num_connectors = 0;
7848         intel_clock_t clock;
7849         bool ok;
7850         const intel_limit_t *limit;
7851         struct drm_atomic_state *state = crtc_state->base.state;
7852         struct drm_connector *connector;
7853         struct drm_connector_state *connector_state;
7854         int i;
7855
7856         memset(&crtc_state->dpll_hw_state, 0,
7857                sizeof(crtc_state->dpll_hw_state));
7858
7859         if (crtc_state->has_dsi_encoder)
7860                 return 0;
7861
7862         for_each_connector_in_state(state, connector, connector_state, i) {
7863                 if (connector_state->crtc == &crtc->base)
7864                         num_connectors++;
7865         }
7866
7867         if (!crtc_state->clock_set) {
7868                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7869
7870                 /*
7871                  * Returns a set of divisors for the desired target clock with
7872                  * the given refclk, or FALSE.  The returned values represent
7873                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7874                  * 2) / p1 / p2.
7875                  */
7876                 limit = intel_limit(crtc_state, refclk);
7877                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7878                                                  crtc_state->port_clock,
7879                                                  refclk, NULL, &clock);
7880                 if (!ok) {
7881                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7882                         return -EINVAL;
7883                 }
7884
7885                 /* Compat-code for transition, will disappear. */
7886                 crtc_state->dpll.n = clock.n;
7887                 crtc_state->dpll.m1 = clock.m1;
7888                 crtc_state->dpll.m2 = clock.m2;
7889                 crtc_state->dpll.p1 = clock.p1;
7890                 crtc_state->dpll.p2 = clock.p2;
7891         }
7892
7893         if (IS_GEN2(dev)) {
7894                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7895                                   num_connectors);
7896         } else if (IS_CHERRYVIEW(dev)) {
7897                 chv_compute_dpll(crtc, crtc_state);
7898         } else if (IS_VALLEYVIEW(dev)) {
7899                 vlv_compute_dpll(crtc, crtc_state);
7900         } else {
7901                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7902                                   num_connectors);
7903         }
7904
7905         return 0;
7906 }
7907
7908 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7909                                  struct intel_crtc_state *pipe_config)
7910 {
7911         struct drm_device *dev = crtc->base.dev;
7912         struct drm_i915_private *dev_priv = dev->dev_private;
7913         uint32_t tmp;
7914
7915         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7916                 return;
7917
7918         tmp = I915_READ(PFIT_CONTROL);
7919         if (!(tmp & PFIT_ENABLE))
7920                 return;
7921
7922         /* Check whether the pfit is attached to our pipe. */
7923         if (INTEL_INFO(dev)->gen < 4) {
7924                 if (crtc->pipe != PIPE_B)
7925                         return;
7926         } else {
7927                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7928                         return;
7929         }
7930
7931         pipe_config->gmch_pfit.control = tmp;
7932         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7933         if (INTEL_INFO(dev)->gen < 5)
7934                 pipe_config->gmch_pfit.lvds_border_bits =
7935                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7936 }
7937
7938 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7939                                struct intel_crtc_state *pipe_config)
7940 {
7941         struct drm_device *dev = crtc->base.dev;
7942         struct drm_i915_private *dev_priv = dev->dev_private;
7943         int pipe = pipe_config->cpu_transcoder;
7944         intel_clock_t clock;
7945         u32 mdiv;
7946         int refclk = 100000;
7947
7948         /* In case of MIPI DPLL will not even be used */
7949         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7950                 return;
7951
7952         mutex_lock(&dev_priv->sb_lock);
7953         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7954         mutex_unlock(&dev_priv->sb_lock);
7955
7956         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7957         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7958         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7959         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7960         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7961
7962         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7963 }
7964
7965 static void
7966 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7967                               struct intel_initial_plane_config *plane_config)
7968 {
7969         struct drm_device *dev = crtc->base.dev;
7970         struct drm_i915_private *dev_priv = dev->dev_private;
7971         u32 val, base, offset;
7972         int pipe = crtc->pipe, plane = crtc->plane;
7973         int fourcc, pixel_format;
7974         unsigned int aligned_height;
7975         struct drm_framebuffer *fb;
7976         struct intel_framebuffer *intel_fb;
7977
7978         val = I915_READ(DSPCNTR(plane));
7979         if (!(val & DISPLAY_PLANE_ENABLE))
7980                 return;
7981
7982         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7983         if (!intel_fb) {
7984                 DRM_DEBUG_KMS("failed to alloc fb\n");
7985                 return;
7986         }
7987
7988         fb = &intel_fb->base;
7989
7990         if (INTEL_INFO(dev)->gen >= 4) {
7991                 if (val & DISPPLANE_TILED) {
7992                         plane_config->tiling = I915_TILING_X;
7993                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7994                 }
7995         }
7996
7997         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7998         fourcc = i9xx_format_to_fourcc(pixel_format);
7999         fb->pixel_format = fourcc;
8000         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8001
8002         if (INTEL_INFO(dev)->gen >= 4) {
8003                 if (plane_config->tiling)
8004                         offset = I915_READ(DSPTILEOFF(plane));
8005                 else
8006                         offset = I915_READ(DSPLINOFF(plane));
8007                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8008         } else {
8009                 base = I915_READ(DSPADDR(plane));
8010         }
8011         plane_config->base = base;
8012
8013         val = I915_READ(PIPESRC(pipe));
8014         fb->width = ((val >> 16) & 0xfff) + 1;
8015         fb->height = ((val >> 0) & 0xfff) + 1;
8016
8017         val = I915_READ(DSPSTRIDE(pipe));
8018         fb->pitches[0] = val & 0xffffffc0;
8019
8020         aligned_height = intel_fb_align_height(dev, fb->height,
8021                                                fb->pixel_format,
8022                                                fb->modifier[0]);
8023
8024         plane_config->size = fb->pitches[0] * aligned_height;
8025
8026         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8027                       pipe_name(pipe), plane, fb->width, fb->height,
8028                       fb->bits_per_pixel, base, fb->pitches[0],
8029                       plane_config->size);
8030
8031         plane_config->fb = intel_fb;
8032 }
8033
8034 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8035                                struct intel_crtc_state *pipe_config)
8036 {
8037         struct drm_device *dev = crtc->base.dev;
8038         struct drm_i915_private *dev_priv = dev->dev_private;
8039         int pipe = pipe_config->cpu_transcoder;
8040         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8041         intel_clock_t clock;
8042         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8043         int refclk = 100000;
8044
8045         mutex_lock(&dev_priv->sb_lock);
8046         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8047         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8048         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8049         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8050         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8051         mutex_unlock(&dev_priv->sb_lock);
8052
8053         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8054         clock.m2 = (pll_dw0 & 0xff) << 22;
8055         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8056                 clock.m2 |= pll_dw2 & 0x3fffff;
8057         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8058         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8059         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8060
8061         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8062 }
8063
8064 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8065                                  struct intel_crtc_state *pipe_config)
8066 {
8067         struct drm_device *dev = crtc->base.dev;
8068         struct drm_i915_private *dev_priv = dev->dev_private;
8069         enum intel_display_power_domain power_domain;
8070         uint32_t tmp;
8071         bool ret;
8072
8073         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8074         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8075                 return false;
8076
8077         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8078         pipe_config->shared_dpll = NULL;
8079
8080         ret = false;
8081
8082         tmp = I915_READ(PIPECONF(crtc->pipe));
8083         if (!(tmp & PIPECONF_ENABLE))
8084                 goto out;
8085
8086         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8087                 switch (tmp & PIPECONF_BPC_MASK) {
8088                 case PIPECONF_6BPC:
8089                         pipe_config->pipe_bpp = 18;
8090                         break;
8091                 case PIPECONF_8BPC:
8092                         pipe_config->pipe_bpp = 24;
8093                         break;
8094                 case PIPECONF_10BPC:
8095                         pipe_config->pipe_bpp = 30;
8096                         break;
8097                 default:
8098                         break;
8099                 }
8100         }
8101
8102         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8103             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8104                 pipe_config->limited_color_range = true;
8105
8106         if (INTEL_INFO(dev)->gen < 4)
8107                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8108
8109         intel_get_pipe_timings(crtc, pipe_config);
8110         intel_get_pipe_src_size(crtc, pipe_config);
8111
8112         i9xx_get_pfit_config(crtc, pipe_config);
8113
8114         if (INTEL_INFO(dev)->gen >= 4) {
8115                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8116                 pipe_config->pixel_multiplier =
8117                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8118                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8119                 pipe_config->dpll_hw_state.dpll_md = tmp;
8120         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8121                 tmp = I915_READ(DPLL(crtc->pipe));
8122                 pipe_config->pixel_multiplier =
8123                         ((tmp & SDVO_MULTIPLIER_MASK)
8124                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8125         } else {
8126                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8127                  * port and will be fixed up in the encoder->get_config
8128                  * function. */
8129                 pipe_config->pixel_multiplier = 1;
8130         }
8131         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8132         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8133                 /*
8134                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8135                  * on 830. Filter it out here so that we don't
8136                  * report errors due to that.
8137                  */
8138                 if (IS_I830(dev))
8139                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8140
8141                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8142                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8143         } else {
8144                 /* Mask out read-only status bits. */
8145                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8146                                                      DPLL_PORTC_READY_MASK |
8147                                                      DPLL_PORTB_READY_MASK);
8148         }
8149
8150         if (IS_CHERRYVIEW(dev))
8151                 chv_crtc_clock_get(crtc, pipe_config);
8152         else if (IS_VALLEYVIEW(dev))
8153                 vlv_crtc_clock_get(crtc, pipe_config);
8154         else
8155                 i9xx_crtc_clock_get(crtc, pipe_config);
8156
8157         /*
8158          * Normally the dotclock is filled in by the encoder .get_config()
8159          * but in case the pipe is enabled w/o any ports we need a sane
8160          * default.
8161          */
8162         pipe_config->base.adjusted_mode.crtc_clock =
8163                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8164
8165         ret = true;
8166
8167 out:
8168         intel_display_power_put(dev_priv, power_domain);
8169
8170         return ret;
8171 }
8172
8173 static void ironlake_init_pch_refclk(struct drm_device *dev)
8174 {
8175         struct drm_i915_private *dev_priv = dev->dev_private;
8176         struct intel_encoder *encoder;
8177         u32 val, final;
8178         bool has_lvds = false;
8179         bool has_cpu_edp = false;
8180         bool has_panel = false;
8181         bool has_ck505 = false;
8182         bool can_ssc = false;
8183
8184         /* We need to take the global config into account */
8185         for_each_intel_encoder(dev, encoder) {
8186                 switch (encoder->type) {
8187                 case INTEL_OUTPUT_LVDS:
8188                         has_panel = true;
8189                         has_lvds = true;
8190                         break;
8191                 case INTEL_OUTPUT_EDP:
8192                         has_panel = true;
8193                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8194                                 has_cpu_edp = true;
8195                         break;
8196                 default:
8197                         break;
8198                 }
8199         }
8200
8201         if (HAS_PCH_IBX(dev)) {
8202                 has_ck505 = dev_priv->vbt.display_clock_mode;
8203                 can_ssc = has_ck505;
8204         } else {
8205                 has_ck505 = false;
8206                 can_ssc = true;
8207         }
8208
8209         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8210                       has_panel, has_lvds, has_ck505);
8211
8212         /* Ironlake: try to setup display ref clock before DPLL
8213          * enabling. This is only under driver's control after
8214          * PCH B stepping, previous chipset stepping should be
8215          * ignoring this setting.
8216          */
8217         val = I915_READ(PCH_DREF_CONTROL);
8218
8219         /* As we must carefully and slowly disable/enable each source in turn,
8220          * compute the final state we want first and check if we need to
8221          * make any changes at all.
8222          */
8223         final = val;
8224         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8225         if (has_ck505)
8226                 final |= DREF_NONSPREAD_CK505_ENABLE;
8227         else
8228                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8229
8230         final &= ~DREF_SSC_SOURCE_MASK;
8231         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8232         final &= ~DREF_SSC1_ENABLE;
8233
8234         if (has_panel) {
8235                 final |= DREF_SSC_SOURCE_ENABLE;
8236
8237                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8238                         final |= DREF_SSC1_ENABLE;
8239
8240                 if (has_cpu_edp) {
8241                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8242                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8243                         else
8244                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8245                 } else
8246                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8247         } else {
8248                 final |= DREF_SSC_SOURCE_DISABLE;
8249                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8250         }
8251
8252         if (final == val)
8253                 return;
8254
8255         /* Always enable nonspread source */
8256         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8257
8258         if (has_ck505)
8259                 val |= DREF_NONSPREAD_CK505_ENABLE;
8260         else
8261                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8262
8263         if (has_panel) {
8264                 val &= ~DREF_SSC_SOURCE_MASK;
8265                 val |= DREF_SSC_SOURCE_ENABLE;
8266
8267                 /* SSC must be turned on before enabling the CPU output  */
8268                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8269                         DRM_DEBUG_KMS("Using SSC on panel\n");
8270                         val |= DREF_SSC1_ENABLE;
8271                 } else
8272                         val &= ~DREF_SSC1_ENABLE;
8273
8274                 /* Get SSC going before enabling the outputs */
8275                 I915_WRITE(PCH_DREF_CONTROL, val);
8276                 POSTING_READ(PCH_DREF_CONTROL);
8277                 udelay(200);
8278
8279                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8280
8281                 /* Enable CPU source on CPU attached eDP */
8282                 if (has_cpu_edp) {
8283                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8284                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8285                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8286                         } else
8287                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8288                 } else
8289                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8290
8291                 I915_WRITE(PCH_DREF_CONTROL, val);
8292                 POSTING_READ(PCH_DREF_CONTROL);
8293                 udelay(200);
8294         } else {
8295                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8296
8297                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8298
8299                 /* Turn off CPU output */
8300                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8301
8302                 I915_WRITE(PCH_DREF_CONTROL, val);
8303                 POSTING_READ(PCH_DREF_CONTROL);
8304                 udelay(200);
8305
8306                 /* Turn off the SSC source */
8307                 val &= ~DREF_SSC_SOURCE_MASK;
8308                 val |= DREF_SSC_SOURCE_DISABLE;
8309
8310                 /* Turn off SSC1 */
8311                 val &= ~DREF_SSC1_ENABLE;
8312
8313                 I915_WRITE(PCH_DREF_CONTROL, val);
8314                 POSTING_READ(PCH_DREF_CONTROL);
8315                 udelay(200);
8316         }
8317
8318         BUG_ON(val != final);
8319 }
8320
8321 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8322 {
8323         uint32_t tmp;
8324
8325         tmp = I915_READ(SOUTH_CHICKEN2);
8326         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8327         I915_WRITE(SOUTH_CHICKEN2, tmp);
8328
8329         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8330                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8331                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8332
8333         tmp = I915_READ(SOUTH_CHICKEN2);
8334         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8335         I915_WRITE(SOUTH_CHICKEN2, tmp);
8336
8337         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8338                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8339                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8340 }
8341
8342 /* WaMPhyProgramming:hsw */
8343 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8344 {
8345         uint32_t tmp;
8346
8347         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8348         tmp &= ~(0xFF << 24);
8349         tmp |= (0x12 << 24);
8350         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8351
8352         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8353         tmp |= (1 << 11);
8354         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8355
8356         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8357         tmp |= (1 << 11);
8358         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8359
8360         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8361         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8362         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8363
8364         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8365         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8366         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8367
8368         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8369         tmp &= ~(7 << 13);
8370         tmp |= (5 << 13);
8371         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8372
8373         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8374         tmp &= ~(7 << 13);
8375         tmp |= (5 << 13);
8376         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8377
8378         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8379         tmp &= ~0xFF;
8380         tmp |= 0x1C;
8381         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8382
8383         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8384         tmp &= ~0xFF;
8385         tmp |= 0x1C;
8386         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8387
8388         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8389         tmp &= ~(0xFF << 16);
8390         tmp |= (0x1C << 16);
8391         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8392
8393         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8394         tmp &= ~(0xFF << 16);
8395         tmp |= (0x1C << 16);
8396         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8397
8398         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8399         tmp |= (1 << 27);
8400         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8401
8402         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8403         tmp |= (1 << 27);
8404         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8405
8406         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8407         tmp &= ~(0xF << 28);
8408         tmp |= (4 << 28);
8409         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8410
8411         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8412         tmp &= ~(0xF << 28);
8413         tmp |= (4 << 28);
8414         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8415 }
8416
8417 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8418  * Programming" based on the parameters passed:
8419  * - Sequence to enable CLKOUT_DP
8420  * - Sequence to enable CLKOUT_DP without spread
8421  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8422  */
8423 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8424                                  bool with_fdi)
8425 {
8426         struct drm_i915_private *dev_priv = dev->dev_private;
8427         uint32_t reg, tmp;
8428
8429         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8430                 with_spread = true;
8431         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8432                 with_fdi = false;
8433
8434         mutex_lock(&dev_priv->sb_lock);
8435
8436         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8437         tmp &= ~SBI_SSCCTL_DISABLE;
8438         tmp |= SBI_SSCCTL_PATHALT;
8439         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8440
8441         udelay(24);
8442
8443         if (with_spread) {
8444                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8445                 tmp &= ~SBI_SSCCTL_PATHALT;
8446                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8447
8448                 if (with_fdi) {
8449                         lpt_reset_fdi_mphy(dev_priv);
8450                         lpt_program_fdi_mphy(dev_priv);
8451                 }
8452         }
8453
8454         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8455         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8456         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8457         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8458
8459         mutex_unlock(&dev_priv->sb_lock);
8460 }
8461
8462 /* Sequence to disable CLKOUT_DP */
8463 static void lpt_disable_clkout_dp(struct drm_device *dev)
8464 {
8465         struct drm_i915_private *dev_priv = dev->dev_private;
8466         uint32_t reg, tmp;
8467
8468         mutex_lock(&dev_priv->sb_lock);
8469
8470         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8471         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8472         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8473         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8474
8475         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8476         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8477                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8478                         tmp |= SBI_SSCCTL_PATHALT;
8479                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8480                         udelay(32);
8481                 }
8482                 tmp |= SBI_SSCCTL_DISABLE;
8483                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8484         }
8485
8486         mutex_unlock(&dev_priv->sb_lock);
8487 }
8488
8489 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8490
8491 static const uint16_t sscdivintphase[] = {
8492         [BEND_IDX( 50)] = 0x3B23,
8493         [BEND_IDX( 45)] = 0x3B23,
8494         [BEND_IDX( 40)] = 0x3C23,
8495         [BEND_IDX( 35)] = 0x3C23,
8496         [BEND_IDX( 30)] = 0x3D23,
8497         [BEND_IDX( 25)] = 0x3D23,
8498         [BEND_IDX( 20)] = 0x3E23,
8499         [BEND_IDX( 15)] = 0x3E23,
8500         [BEND_IDX( 10)] = 0x3F23,
8501         [BEND_IDX(  5)] = 0x3F23,
8502         [BEND_IDX(  0)] = 0x0025,
8503         [BEND_IDX( -5)] = 0x0025,
8504         [BEND_IDX(-10)] = 0x0125,
8505         [BEND_IDX(-15)] = 0x0125,
8506         [BEND_IDX(-20)] = 0x0225,
8507         [BEND_IDX(-25)] = 0x0225,
8508         [BEND_IDX(-30)] = 0x0325,
8509         [BEND_IDX(-35)] = 0x0325,
8510         [BEND_IDX(-40)] = 0x0425,
8511         [BEND_IDX(-45)] = 0x0425,
8512         [BEND_IDX(-50)] = 0x0525,
8513 };
8514
8515 /*
8516  * Bend CLKOUT_DP
8517  * steps -50 to 50 inclusive, in steps of 5
8518  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8519  * change in clock period = -(steps / 10) * 5.787 ps
8520  */
8521 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8522 {
8523         uint32_t tmp;
8524         int idx = BEND_IDX(steps);
8525
8526         if (WARN_ON(steps % 5 != 0))
8527                 return;
8528
8529         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8530                 return;
8531
8532         mutex_lock(&dev_priv->sb_lock);
8533
8534         if (steps % 10 != 0)
8535                 tmp = 0xAAAAAAAB;
8536         else
8537                 tmp = 0x00000000;
8538         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8539
8540         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8541         tmp &= 0xffff0000;
8542         tmp |= sscdivintphase[idx];
8543         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8544
8545         mutex_unlock(&dev_priv->sb_lock);
8546 }
8547
8548 #undef BEND_IDX
8549
8550 static void lpt_init_pch_refclk(struct drm_device *dev)
8551 {
8552         struct intel_encoder *encoder;
8553         bool has_vga = false;
8554
8555         for_each_intel_encoder(dev, encoder) {
8556                 switch (encoder->type) {
8557                 case INTEL_OUTPUT_ANALOG:
8558                         has_vga = true;
8559                         break;
8560                 default:
8561                         break;
8562                 }
8563         }
8564
8565         if (has_vga) {
8566                 lpt_bend_clkout_dp(to_i915(dev), 0);
8567                 lpt_enable_clkout_dp(dev, true, true);
8568         } else {
8569                 lpt_disable_clkout_dp(dev);
8570         }
8571 }
8572
8573 /*
8574  * Initialize reference clocks when the driver loads
8575  */
8576 void intel_init_pch_refclk(struct drm_device *dev)
8577 {
8578         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8579                 ironlake_init_pch_refclk(dev);
8580         else if (HAS_PCH_LPT(dev))
8581                 lpt_init_pch_refclk(dev);
8582 }
8583
8584 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8585 {
8586         struct drm_device *dev = crtc_state->base.crtc->dev;
8587         struct drm_i915_private *dev_priv = dev->dev_private;
8588         struct drm_atomic_state *state = crtc_state->base.state;
8589         struct drm_connector *connector;
8590         struct drm_connector_state *connector_state;
8591         struct intel_encoder *encoder;
8592         int num_connectors = 0, i;
8593         bool is_lvds = false;
8594
8595         for_each_connector_in_state(state, connector, connector_state, i) {
8596                 if (connector_state->crtc != crtc_state->base.crtc)
8597                         continue;
8598
8599                 encoder = to_intel_encoder(connector_state->best_encoder);
8600
8601                 switch (encoder->type) {
8602                 case INTEL_OUTPUT_LVDS:
8603                         is_lvds = true;
8604                         break;
8605                 default:
8606                         break;
8607                 }
8608                 num_connectors++;
8609         }
8610
8611         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8612                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8613                               dev_priv->vbt.lvds_ssc_freq);
8614                 return dev_priv->vbt.lvds_ssc_freq;
8615         }
8616
8617         return 120000;
8618 }
8619
8620 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8621 {
8622         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8624         int pipe = intel_crtc->pipe;
8625         uint32_t val;
8626
8627         val = 0;
8628
8629         switch (intel_crtc->config->pipe_bpp) {
8630         case 18:
8631                 val |= PIPECONF_6BPC;
8632                 break;
8633         case 24:
8634                 val |= PIPECONF_8BPC;
8635                 break;
8636         case 30:
8637                 val |= PIPECONF_10BPC;
8638                 break;
8639         case 36:
8640                 val |= PIPECONF_12BPC;
8641                 break;
8642         default:
8643                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8644                 BUG();
8645         }
8646
8647         if (intel_crtc->config->dither)
8648                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8649
8650         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8651                 val |= PIPECONF_INTERLACED_ILK;
8652         else
8653                 val |= PIPECONF_PROGRESSIVE;
8654
8655         if (intel_crtc->config->limited_color_range)
8656                 val |= PIPECONF_COLOR_RANGE_SELECT;
8657
8658         I915_WRITE(PIPECONF(pipe), val);
8659         POSTING_READ(PIPECONF(pipe));
8660 }
8661
8662 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8663 {
8664         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8667         u32 val = 0;
8668
8669         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8670                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8671
8672         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8673                 val |= PIPECONF_INTERLACED_ILK;
8674         else
8675                 val |= PIPECONF_PROGRESSIVE;
8676
8677         I915_WRITE(PIPECONF(cpu_transcoder), val);
8678         POSTING_READ(PIPECONF(cpu_transcoder));
8679 }
8680
8681 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8682 {
8683         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8685
8686         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8687                 u32 val = 0;
8688
8689                 switch (intel_crtc->config->pipe_bpp) {
8690                 case 18:
8691                         val |= PIPEMISC_DITHER_6_BPC;
8692                         break;
8693                 case 24:
8694                         val |= PIPEMISC_DITHER_8_BPC;
8695                         break;
8696                 case 30:
8697                         val |= PIPEMISC_DITHER_10_BPC;
8698                         break;
8699                 case 36:
8700                         val |= PIPEMISC_DITHER_12_BPC;
8701                         break;
8702                 default:
8703                         /* Case prevented by pipe_config_set_bpp. */
8704                         BUG();
8705                 }
8706
8707                 if (intel_crtc->config->dither)
8708                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8709
8710                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8711         }
8712 }
8713
8714 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8715                                     struct intel_crtc_state *crtc_state,
8716                                     intel_clock_t *clock,
8717                                     bool *has_reduced_clock,
8718                                     intel_clock_t *reduced_clock)
8719 {
8720         struct drm_device *dev = crtc->dev;
8721         struct drm_i915_private *dev_priv = dev->dev_private;
8722         int refclk;
8723         const intel_limit_t *limit;
8724         bool ret;
8725
8726         refclk = ironlake_get_refclk(crtc_state);
8727
8728         /*
8729          * Returns a set of divisors for the desired target clock with the given
8730          * refclk, or FALSE.  The returned values represent the clock equation:
8731          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8732          */
8733         limit = intel_limit(crtc_state, refclk);
8734         ret = dev_priv->display.find_dpll(limit, crtc_state,
8735                                           crtc_state->port_clock,
8736                                           refclk, NULL, clock);
8737         if (!ret)
8738                 return false;
8739
8740         return true;
8741 }
8742
8743 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8744 {
8745         /*
8746          * Account for spread spectrum to avoid
8747          * oversubscribing the link. Max center spread
8748          * is 2.5%; use 5% for safety's sake.
8749          */
8750         u32 bps = target_clock * bpp * 21 / 20;
8751         return DIV_ROUND_UP(bps, link_bw * 8);
8752 }
8753
8754 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8755 {
8756         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8757 }
8758
8759 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8760                                       struct intel_crtc_state *crtc_state,
8761                                       u32 *fp,
8762                                       intel_clock_t *reduced_clock, u32 *fp2)
8763 {
8764         struct drm_crtc *crtc = &intel_crtc->base;
8765         struct drm_device *dev = crtc->dev;
8766         struct drm_i915_private *dev_priv = dev->dev_private;
8767         struct drm_atomic_state *state = crtc_state->base.state;
8768         struct drm_connector *connector;
8769         struct drm_connector_state *connector_state;
8770         struct intel_encoder *encoder;
8771         uint32_t dpll;
8772         int factor, num_connectors = 0, i;
8773         bool is_lvds = false, is_sdvo = false;
8774
8775         for_each_connector_in_state(state, connector, connector_state, i) {
8776                 if (connector_state->crtc != crtc_state->base.crtc)
8777                         continue;
8778
8779                 encoder = to_intel_encoder(connector_state->best_encoder);
8780
8781                 switch (encoder->type) {
8782                 case INTEL_OUTPUT_LVDS:
8783                         is_lvds = true;
8784                         break;
8785                 case INTEL_OUTPUT_SDVO:
8786                 case INTEL_OUTPUT_HDMI:
8787                         is_sdvo = true;
8788                         break;
8789                 default:
8790                         break;
8791                 }
8792
8793                 num_connectors++;
8794         }
8795
8796         /* Enable autotuning of the PLL clock (if permissible) */
8797         factor = 21;
8798         if (is_lvds) {
8799                 if ((intel_panel_use_ssc(dev_priv) &&
8800                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8801                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8802                         factor = 25;
8803         } else if (crtc_state->sdvo_tv_clock)
8804                 factor = 20;
8805
8806         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8807                 *fp |= FP_CB_TUNE;
8808
8809         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8810                 *fp2 |= FP_CB_TUNE;
8811
8812         dpll = 0;
8813
8814         if (is_lvds)
8815                 dpll |= DPLLB_MODE_LVDS;
8816         else
8817                 dpll |= DPLLB_MODE_DAC_SERIAL;
8818
8819         dpll |= (crtc_state->pixel_multiplier - 1)
8820                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8821
8822         if (is_sdvo)
8823                 dpll |= DPLL_SDVO_HIGH_SPEED;
8824         if (crtc_state->has_dp_encoder)
8825                 dpll |= DPLL_SDVO_HIGH_SPEED;
8826
8827         /* compute bitmask from p1 value */
8828         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8829         /* also FPA1 */
8830         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8831
8832         switch (crtc_state->dpll.p2) {
8833         case 5:
8834                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8835                 break;
8836         case 7:
8837                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8838                 break;
8839         case 10:
8840                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8841                 break;
8842         case 14:
8843                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8844                 break;
8845         }
8846
8847         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8848                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8849         else
8850                 dpll |= PLL_REF_INPUT_DREFCLK;
8851
8852         return dpll | DPLL_VCO_ENABLE;
8853 }
8854
8855 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8856                                        struct intel_crtc_state *crtc_state)
8857 {
8858         struct drm_device *dev = crtc->base.dev;
8859         intel_clock_t clock, reduced_clock;
8860         u32 dpll = 0, fp = 0, fp2 = 0;
8861         bool ok, has_reduced_clock = false;
8862         bool is_lvds = false;
8863         struct intel_shared_dpll *pll;
8864
8865         memset(&crtc_state->dpll_hw_state, 0,
8866                sizeof(crtc_state->dpll_hw_state));
8867
8868         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8869
8870         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8871              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8872
8873         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8874                                      &has_reduced_clock, &reduced_clock);
8875         if (!ok && !crtc_state->clock_set) {
8876                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8877                 return -EINVAL;
8878         }
8879         /* Compat-code for transition, will disappear. */
8880         if (!crtc_state->clock_set) {
8881                 crtc_state->dpll.n = clock.n;
8882                 crtc_state->dpll.m1 = clock.m1;
8883                 crtc_state->dpll.m2 = clock.m2;
8884                 crtc_state->dpll.p1 = clock.p1;
8885                 crtc_state->dpll.p2 = clock.p2;
8886         }
8887
8888         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8889         if (crtc_state->has_pch_encoder) {
8890                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8891                 if (has_reduced_clock)
8892                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8893
8894                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8895                                              &fp, &reduced_clock,
8896                                              has_reduced_clock ? &fp2 : NULL);
8897
8898                 crtc_state->dpll_hw_state.dpll = dpll;
8899                 crtc_state->dpll_hw_state.fp0 = fp;
8900                 if (has_reduced_clock)
8901                         crtc_state->dpll_hw_state.fp1 = fp2;
8902                 else
8903                         crtc_state->dpll_hw_state.fp1 = fp;
8904
8905                 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8906                 if (pll == NULL) {
8907                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8908                                          pipe_name(crtc->pipe));
8909                         return -EINVAL;
8910                 }
8911         }
8912
8913         if (is_lvds && has_reduced_clock)
8914                 crtc->lowfreq_avail = true;
8915         else
8916                 crtc->lowfreq_avail = false;
8917
8918         return 0;
8919 }
8920
8921 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8922                                          struct intel_link_m_n *m_n)
8923 {
8924         struct drm_device *dev = crtc->base.dev;
8925         struct drm_i915_private *dev_priv = dev->dev_private;
8926         enum pipe pipe = crtc->pipe;
8927
8928         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8929         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8930         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8931                 & ~TU_SIZE_MASK;
8932         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8933         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8934                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8935 }
8936
8937 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8938                                          enum transcoder transcoder,
8939                                          struct intel_link_m_n *m_n,
8940                                          struct intel_link_m_n *m2_n2)
8941 {
8942         struct drm_device *dev = crtc->base.dev;
8943         struct drm_i915_private *dev_priv = dev->dev_private;
8944         enum pipe pipe = crtc->pipe;
8945
8946         if (INTEL_INFO(dev)->gen >= 5) {
8947                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8948                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8949                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8950                         & ~TU_SIZE_MASK;
8951                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8952                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8953                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8955                  * gen < 8) and if DRRS is supported (to make sure the
8956                  * registers are not unnecessarily read).
8957                  */
8958                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8959                         crtc->config->has_drrs) {
8960                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8961                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8962                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8963                                         & ~TU_SIZE_MASK;
8964                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8965                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8966                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8967                 }
8968         } else {
8969                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8970                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8971                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8972                         & ~TU_SIZE_MASK;
8973                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8974                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8975                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976         }
8977 }
8978
8979 void intel_dp_get_m_n(struct intel_crtc *crtc,
8980                       struct intel_crtc_state *pipe_config)
8981 {
8982         if (pipe_config->has_pch_encoder)
8983                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8984         else
8985                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8986                                              &pipe_config->dp_m_n,
8987                                              &pipe_config->dp_m2_n2);
8988 }
8989
8990 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8991                                         struct intel_crtc_state *pipe_config)
8992 {
8993         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8994                                      &pipe_config->fdi_m_n, NULL);
8995 }
8996
8997 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8998                                     struct intel_crtc_state *pipe_config)
8999 {
9000         struct drm_device *dev = crtc->base.dev;
9001         struct drm_i915_private *dev_priv = dev->dev_private;
9002         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9003         uint32_t ps_ctrl = 0;
9004         int id = -1;
9005         int i;
9006
9007         /* find scaler attached to this pipe */
9008         for (i = 0; i < crtc->num_scalers; i++) {
9009                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9010                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9011                         id = i;
9012                         pipe_config->pch_pfit.enabled = true;
9013                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9014                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9015                         break;
9016                 }
9017         }
9018
9019         scaler_state->scaler_id = id;
9020         if (id >= 0) {
9021                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9022         } else {
9023                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9024         }
9025 }
9026
9027 static void
9028 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9029                                  struct intel_initial_plane_config *plane_config)
9030 {
9031         struct drm_device *dev = crtc->base.dev;
9032         struct drm_i915_private *dev_priv = dev->dev_private;
9033         u32 val, base, offset, stride_mult, tiling;
9034         int pipe = crtc->pipe;
9035         int fourcc, pixel_format;
9036         unsigned int aligned_height;
9037         struct drm_framebuffer *fb;
9038         struct intel_framebuffer *intel_fb;
9039
9040         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9041         if (!intel_fb) {
9042                 DRM_DEBUG_KMS("failed to alloc fb\n");
9043                 return;
9044         }
9045
9046         fb = &intel_fb->base;
9047
9048         val = I915_READ(PLANE_CTL(pipe, 0));
9049         if (!(val & PLANE_CTL_ENABLE))
9050                 goto error;
9051
9052         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9053         fourcc = skl_format_to_fourcc(pixel_format,
9054                                       val & PLANE_CTL_ORDER_RGBX,
9055                                       val & PLANE_CTL_ALPHA_MASK);
9056         fb->pixel_format = fourcc;
9057         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9058
9059         tiling = val & PLANE_CTL_TILED_MASK;
9060         switch (tiling) {
9061         case PLANE_CTL_TILED_LINEAR:
9062                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9063                 break;
9064         case PLANE_CTL_TILED_X:
9065                 plane_config->tiling = I915_TILING_X;
9066                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9067                 break;
9068         case PLANE_CTL_TILED_Y:
9069                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9070                 break;
9071         case PLANE_CTL_TILED_YF:
9072                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9073                 break;
9074         default:
9075                 MISSING_CASE(tiling);
9076                 goto error;
9077         }
9078
9079         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9080         plane_config->base = base;
9081
9082         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9083
9084         val = I915_READ(PLANE_SIZE(pipe, 0));
9085         fb->height = ((val >> 16) & 0xfff) + 1;
9086         fb->width = ((val >> 0) & 0x1fff) + 1;
9087
9088         val = I915_READ(PLANE_STRIDE(pipe, 0));
9089         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9090                                                 fb->pixel_format);
9091         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9092
9093         aligned_height = intel_fb_align_height(dev, fb->height,
9094                                                fb->pixel_format,
9095                                                fb->modifier[0]);
9096
9097         plane_config->size = fb->pitches[0] * aligned_height;
9098
9099         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9100                       pipe_name(pipe), fb->width, fb->height,
9101                       fb->bits_per_pixel, base, fb->pitches[0],
9102                       plane_config->size);
9103
9104         plane_config->fb = intel_fb;
9105         return;
9106
9107 error:
9108         kfree(fb);
9109 }
9110
9111 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9112                                      struct intel_crtc_state *pipe_config)
9113 {
9114         struct drm_device *dev = crtc->base.dev;
9115         struct drm_i915_private *dev_priv = dev->dev_private;
9116         uint32_t tmp;
9117
9118         tmp = I915_READ(PF_CTL(crtc->pipe));
9119
9120         if (tmp & PF_ENABLE) {
9121                 pipe_config->pch_pfit.enabled = true;
9122                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9123                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9124
9125                 /* We currently do not free assignements of panel fitters on
9126                  * ivb/hsw (since we don't use the higher upscaling modes which
9127                  * differentiates them) so just WARN about this case for now. */
9128                 if (IS_GEN7(dev)) {
9129                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9130                                 PF_PIPE_SEL_IVB(crtc->pipe));
9131                 }
9132         }
9133 }
9134
9135 static void
9136 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9137                                   struct intel_initial_plane_config *plane_config)
9138 {
9139         struct drm_device *dev = crtc->base.dev;
9140         struct drm_i915_private *dev_priv = dev->dev_private;
9141         u32 val, base, offset;
9142         int pipe = crtc->pipe;
9143         int fourcc, pixel_format;
9144         unsigned int aligned_height;
9145         struct drm_framebuffer *fb;
9146         struct intel_framebuffer *intel_fb;
9147
9148         val = I915_READ(DSPCNTR(pipe));
9149         if (!(val & DISPLAY_PLANE_ENABLE))
9150                 return;
9151
9152         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9153         if (!intel_fb) {
9154                 DRM_DEBUG_KMS("failed to alloc fb\n");
9155                 return;
9156         }
9157
9158         fb = &intel_fb->base;
9159
9160         if (INTEL_INFO(dev)->gen >= 4) {
9161                 if (val & DISPPLANE_TILED) {
9162                         plane_config->tiling = I915_TILING_X;
9163                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9164                 }
9165         }
9166
9167         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9168         fourcc = i9xx_format_to_fourcc(pixel_format);
9169         fb->pixel_format = fourcc;
9170         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9171
9172         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9173         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9174                 offset = I915_READ(DSPOFFSET(pipe));
9175         } else {
9176                 if (plane_config->tiling)
9177                         offset = I915_READ(DSPTILEOFF(pipe));
9178                 else
9179                         offset = I915_READ(DSPLINOFF(pipe));
9180         }
9181         plane_config->base = base;
9182
9183         val = I915_READ(PIPESRC(pipe));
9184         fb->width = ((val >> 16) & 0xfff) + 1;
9185         fb->height = ((val >> 0) & 0xfff) + 1;
9186
9187         val = I915_READ(DSPSTRIDE(pipe));
9188         fb->pitches[0] = val & 0xffffffc0;
9189
9190         aligned_height = intel_fb_align_height(dev, fb->height,
9191                                                fb->pixel_format,
9192                                                fb->modifier[0]);
9193
9194         plane_config->size = fb->pitches[0] * aligned_height;
9195
9196         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9197                       pipe_name(pipe), fb->width, fb->height,
9198                       fb->bits_per_pixel, base, fb->pitches[0],
9199                       plane_config->size);
9200
9201         plane_config->fb = intel_fb;
9202 }
9203
9204 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9205                                      struct intel_crtc_state *pipe_config)
9206 {
9207         struct drm_device *dev = crtc->base.dev;
9208         struct drm_i915_private *dev_priv = dev->dev_private;
9209         enum intel_display_power_domain power_domain;
9210         uint32_t tmp;
9211         bool ret;
9212
9213         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9214         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9215                 return false;
9216
9217         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9218         pipe_config->shared_dpll = NULL;
9219
9220         ret = false;
9221         tmp = I915_READ(PIPECONF(crtc->pipe));
9222         if (!(tmp & PIPECONF_ENABLE))
9223                 goto out;
9224
9225         switch (tmp & PIPECONF_BPC_MASK) {
9226         case PIPECONF_6BPC:
9227                 pipe_config->pipe_bpp = 18;
9228                 break;
9229         case PIPECONF_8BPC:
9230                 pipe_config->pipe_bpp = 24;
9231                 break;
9232         case PIPECONF_10BPC:
9233                 pipe_config->pipe_bpp = 30;
9234                 break;
9235         case PIPECONF_12BPC:
9236                 pipe_config->pipe_bpp = 36;
9237                 break;
9238         default:
9239                 break;
9240         }
9241
9242         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9243                 pipe_config->limited_color_range = true;
9244
9245         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9246                 struct intel_shared_dpll *pll;
9247                 enum intel_dpll_id pll_id;
9248
9249                 pipe_config->has_pch_encoder = true;
9250
9251                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9252                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9253                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9254
9255                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9256
9257                 if (HAS_PCH_IBX(dev_priv->dev)) {
9258                         pll_id = (enum intel_dpll_id) crtc->pipe;
9259                 } else {
9260                         tmp = I915_READ(PCH_DPLL_SEL);
9261                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9262                                 pll_id = DPLL_ID_PCH_PLL_B;
9263                         else
9264                                 pll_id= DPLL_ID_PCH_PLL_A;
9265                 }
9266
9267                 pipe_config->shared_dpll =
9268                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9269                 pll = pipe_config->shared_dpll;
9270
9271                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9272                                                  &pipe_config->dpll_hw_state));
9273
9274                 tmp = pipe_config->dpll_hw_state.dpll;
9275                 pipe_config->pixel_multiplier =
9276                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9277                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9278
9279                 ironlake_pch_clock_get(crtc, pipe_config);
9280         } else {
9281                 pipe_config->pixel_multiplier = 1;
9282         }
9283
9284         intel_get_pipe_timings(crtc, pipe_config);
9285         intel_get_pipe_src_size(crtc, pipe_config);
9286
9287         ironlake_get_pfit_config(crtc, pipe_config);
9288
9289         ret = true;
9290
9291 out:
9292         intel_display_power_put(dev_priv, power_domain);
9293
9294         return ret;
9295 }
9296
9297 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9298 {
9299         struct drm_device *dev = dev_priv->dev;
9300         struct intel_crtc *crtc;
9301
9302         for_each_intel_crtc(dev, crtc)
9303                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9304                      pipe_name(crtc->pipe));
9305
9306         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9307         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9308         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9309         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9310         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9311         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9312              "CPU PWM1 enabled\n");
9313         if (IS_HASWELL(dev))
9314                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9315                      "CPU PWM2 enabled\n");
9316         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9317              "PCH PWM1 enabled\n");
9318         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9319              "Utility pin enabled\n");
9320         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9321
9322         /*
9323          * In theory we can still leave IRQs enabled, as long as only the HPD
9324          * interrupts remain enabled. We used to check for that, but since it's
9325          * gen-specific and since we only disable LCPLL after we fully disable
9326          * the interrupts, the check below should be enough.
9327          */
9328         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9329 }
9330
9331 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9332 {
9333         struct drm_device *dev = dev_priv->dev;
9334
9335         if (IS_HASWELL(dev))
9336                 return I915_READ(D_COMP_HSW);
9337         else
9338                 return I915_READ(D_COMP_BDW);
9339 }
9340
9341 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9342 {
9343         struct drm_device *dev = dev_priv->dev;
9344
9345         if (IS_HASWELL(dev)) {
9346                 mutex_lock(&dev_priv->rps.hw_lock);
9347                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9348                                             val))
9349                         DRM_ERROR("Failed to write to D_COMP\n");
9350                 mutex_unlock(&dev_priv->rps.hw_lock);
9351         } else {
9352                 I915_WRITE(D_COMP_BDW, val);
9353                 POSTING_READ(D_COMP_BDW);
9354         }
9355 }
9356
9357 /*
9358  * This function implements pieces of two sequences from BSpec:
9359  * - Sequence for display software to disable LCPLL
9360  * - Sequence for display software to allow package C8+
9361  * The steps implemented here are just the steps that actually touch the LCPLL
9362  * register. Callers should take care of disabling all the display engine
9363  * functions, doing the mode unset, fixing interrupts, etc.
9364  */
9365 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9366                               bool switch_to_fclk, bool allow_power_down)
9367 {
9368         uint32_t val;
9369
9370         assert_can_disable_lcpll(dev_priv);
9371
9372         val = I915_READ(LCPLL_CTL);
9373
9374         if (switch_to_fclk) {
9375                 val |= LCPLL_CD_SOURCE_FCLK;
9376                 I915_WRITE(LCPLL_CTL, val);
9377
9378                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9379                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9380                         DRM_ERROR("Switching to FCLK failed\n");
9381
9382                 val = I915_READ(LCPLL_CTL);
9383         }
9384
9385         val |= LCPLL_PLL_DISABLE;
9386         I915_WRITE(LCPLL_CTL, val);
9387         POSTING_READ(LCPLL_CTL);
9388
9389         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9390                 DRM_ERROR("LCPLL still locked\n");
9391
9392         val = hsw_read_dcomp(dev_priv);
9393         val |= D_COMP_COMP_DISABLE;
9394         hsw_write_dcomp(dev_priv, val);
9395         ndelay(100);
9396
9397         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9398                      1))
9399                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9400
9401         if (allow_power_down) {
9402                 val = I915_READ(LCPLL_CTL);
9403                 val |= LCPLL_POWER_DOWN_ALLOW;
9404                 I915_WRITE(LCPLL_CTL, val);
9405                 POSTING_READ(LCPLL_CTL);
9406         }
9407 }
9408
9409 /*
9410  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9411  * source.
9412  */
9413 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9414 {
9415         uint32_t val;
9416
9417         val = I915_READ(LCPLL_CTL);
9418
9419         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9420                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9421                 return;
9422
9423         /*
9424          * Make sure we're not on PC8 state before disabling PC8, otherwise
9425          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9426          */
9427         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9428
9429         if (val & LCPLL_POWER_DOWN_ALLOW) {
9430                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9431                 I915_WRITE(LCPLL_CTL, val);
9432                 POSTING_READ(LCPLL_CTL);
9433         }
9434
9435         val = hsw_read_dcomp(dev_priv);
9436         val |= D_COMP_COMP_FORCE;
9437         val &= ~D_COMP_COMP_DISABLE;
9438         hsw_write_dcomp(dev_priv, val);
9439
9440         val = I915_READ(LCPLL_CTL);
9441         val &= ~LCPLL_PLL_DISABLE;
9442         I915_WRITE(LCPLL_CTL, val);
9443
9444         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9445                 DRM_ERROR("LCPLL not locked yet\n");
9446
9447         if (val & LCPLL_CD_SOURCE_FCLK) {
9448                 val = I915_READ(LCPLL_CTL);
9449                 val &= ~LCPLL_CD_SOURCE_FCLK;
9450                 I915_WRITE(LCPLL_CTL, val);
9451
9452                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9453                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9454                         DRM_ERROR("Switching back to LCPLL failed\n");
9455         }
9456
9457         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9458         intel_update_cdclk(dev_priv->dev);
9459 }
9460
9461 /*
9462  * Package states C8 and deeper are really deep PC states that can only be
9463  * reached when all the devices on the system allow it, so even if the graphics
9464  * device allows PC8+, it doesn't mean the system will actually get to these
9465  * states. Our driver only allows PC8+ when going into runtime PM.
9466  *
9467  * The requirements for PC8+ are that all the outputs are disabled, the power
9468  * well is disabled and most interrupts are disabled, and these are also
9469  * requirements for runtime PM. When these conditions are met, we manually do
9470  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9471  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9472  * hang the machine.
9473  *
9474  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9475  * the state of some registers, so when we come back from PC8+ we need to
9476  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9477  * need to take care of the registers kept by RC6. Notice that this happens even
9478  * if we don't put the device in PCI D3 state (which is what currently happens
9479  * because of the runtime PM support).
9480  *
9481  * For more, read "Display Sequences for Package C8" on the hardware
9482  * documentation.
9483  */
9484 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9485 {
9486         struct drm_device *dev = dev_priv->dev;
9487         uint32_t val;
9488
9489         DRM_DEBUG_KMS("Enabling package C8+\n");
9490
9491         if (HAS_PCH_LPT_LP(dev)) {
9492                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9493                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9494                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9495         }
9496
9497         lpt_disable_clkout_dp(dev);
9498         hsw_disable_lcpll(dev_priv, true, true);
9499 }
9500
9501 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9502 {
9503         struct drm_device *dev = dev_priv->dev;
9504         uint32_t val;
9505
9506         DRM_DEBUG_KMS("Disabling package C8+\n");
9507
9508         hsw_restore_lcpll(dev_priv);
9509         lpt_init_pch_refclk(dev);
9510
9511         if (HAS_PCH_LPT_LP(dev)) {
9512                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9513                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9514                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9515         }
9516 }
9517
9518 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9519 {
9520         struct drm_device *dev = old_state->dev;
9521         struct intel_atomic_state *old_intel_state =
9522                 to_intel_atomic_state(old_state);
9523         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9524
9525         broxton_set_cdclk(dev, req_cdclk);
9526 }
9527
9528 /* compute the max rate for new configuration */
9529 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9530 {
9531         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9532         struct drm_i915_private *dev_priv = state->dev->dev_private;
9533         struct drm_crtc *crtc;
9534         struct drm_crtc_state *cstate;
9535         struct intel_crtc_state *crtc_state;
9536         unsigned max_pixel_rate = 0, i;
9537         enum pipe pipe;
9538
9539         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9540                sizeof(intel_state->min_pixclk));
9541
9542         for_each_crtc_in_state(state, crtc, cstate, i) {
9543                 int pixel_rate;
9544
9545                 crtc_state = to_intel_crtc_state(cstate);
9546                 if (!crtc_state->base.enable) {
9547                         intel_state->min_pixclk[i] = 0;
9548                         continue;
9549                 }
9550
9551                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9552
9553                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9554                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9555                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9556
9557                 intel_state->min_pixclk[i] = pixel_rate;
9558         }
9559
9560         for_each_pipe(dev_priv, pipe)
9561                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9562
9563         return max_pixel_rate;
9564 }
9565
9566 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9567 {
9568         struct drm_i915_private *dev_priv = dev->dev_private;
9569         uint32_t val, data;
9570         int ret;
9571
9572         if (WARN((I915_READ(LCPLL_CTL) &
9573                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9574                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9575                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9576                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9577                  "trying to change cdclk frequency with cdclk not enabled\n"))
9578                 return;
9579
9580         mutex_lock(&dev_priv->rps.hw_lock);
9581         ret = sandybridge_pcode_write(dev_priv,
9582                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9583         mutex_unlock(&dev_priv->rps.hw_lock);
9584         if (ret) {
9585                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9586                 return;
9587         }
9588
9589         val = I915_READ(LCPLL_CTL);
9590         val |= LCPLL_CD_SOURCE_FCLK;
9591         I915_WRITE(LCPLL_CTL, val);
9592
9593         if (wait_for_us(I915_READ(LCPLL_CTL) &
9594                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9595                 DRM_ERROR("Switching to FCLK failed\n");
9596
9597         val = I915_READ(LCPLL_CTL);
9598         val &= ~LCPLL_CLK_FREQ_MASK;
9599
9600         switch (cdclk) {
9601         case 450000:
9602                 val |= LCPLL_CLK_FREQ_450;
9603                 data = 0;
9604                 break;
9605         case 540000:
9606                 val |= LCPLL_CLK_FREQ_54O_BDW;
9607                 data = 1;
9608                 break;
9609         case 337500:
9610                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9611                 data = 2;
9612                 break;
9613         case 675000:
9614                 val |= LCPLL_CLK_FREQ_675_BDW;
9615                 data = 3;
9616                 break;
9617         default:
9618                 WARN(1, "invalid cdclk frequency\n");
9619                 return;
9620         }
9621
9622         I915_WRITE(LCPLL_CTL, val);
9623
9624         val = I915_READ(LCPLL_CTL);
9625         val &= ~LCPLL_CD_SOURCE_FCLK;
9626         I915_WRITE(LCPLL_CTL, val);
9627
9628         if (wait_for_us((I915_READ(LCPLL_CTL) &
9629                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9630                 DRM_ERROR("Switching back to LCPLL failed\n");
9631
9632         mutex_lock(&dev_priv->rps.hw_lock);
9633         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9634         mutex_unlock(&dev_priv->rps.hw_lock);
9635
9636         intel_update_cdclk(dev);
9637
9638         WARN(cdclk != dev_priv->cdclk_freq,
9639              "cdclk requested %d kHz but got %d kHz\n",
9640              cdclk, dev_priv->cdclk_freq);
9641 }
9642
9643 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9644 {
9645         struct drm_i915_private *dev_priv = to_i915(state->dev);
9646         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9647         int max_pixclk = ilk_max_pixel_rate(state);
9648         int cdclk;
9649
9650         /*
9651          * FIXME should also account for plane ratio
9652          * once 64bpp pixel formats are supported.
9653          */
9654         if (max_pixclk > 540000)
9655                 cdclk = 675000;
9656         else if (max_pixclk > 450000)
9657                 cdclk = 540000;
9658         else if (max_pixclk > 337500)
9659                 cdclk = 450000;
9660         else
9661                 cdclk = 337500;
9662
9663         if (cdclk > dev_priv->max_cdclk_freq) {
9664                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9665                               cdclk, dev_priv->max_cdclk_freq);
9666                 return -EINVAL;
9667         }
9668
9669         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9670         if (!intel_state->active_crtcs)
9671                 intel_state->dev_cdclk = 337500;
9672
9673         return 0;
9674 }
9675
9676 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9677 {
9678         struct drm_device *dev = old_state->dev;
9679         struct intel_atomic_state *old_intel_state =
9680                 to_intel_atomic_state(old_state);
9681         unsigned req_cdclk = old_intel_state->dev_cdclk;
9682
9683         broadwell_set_cdclk(dev, req_cdclk);
9684 }
9685
9686 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9687                                       struct intel_crtc_state *crtc_state)
9688 {
9689         struct intel_encoder *intel_encoder =
9690                 intel_ddi_get_crtc_new_encoder(crtc_state);
9691
9692         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9693                 if (!intel_ddi_pll_select(crtc, crtc_state))
9694                         return -EINVAL;
9695         }
9696
9697         crtc->lowfreq_avail = false;
9698
9699         return 0;
9700 }
9701
9702 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9703                                 enum port port,
9704                                 struct intel_crtc_state *pipe_config)
9705 {
9706         enum intel_dpll_id id;
9707
9708         switch (port) {
9709         case PORT_A:
9710                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9711                 id = DPLL_ID_SKL_DPLL0;
9712                 break;
9713         case PORT_B:
9714                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9715                 id = DPLL_ID_SKL_DPLL1;
9716                 break;
9717         case PORT_C:
9718                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9719                 id = DPLL_ID_SKL_DPLL2;
9720                 break;
9721         default:
9722                 DRM_ERROR("Incorrect port type\n");
9723                 return;
9724         }
9725
9726         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9727 }
9728
9729 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9730                                 enum port port,
9731                                 struct intel_crtc_state *pipe_config)
9732 {
9733         enum intel_dpll_id id;
9734         u32 temp;
9735
9736         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9737         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9738
9739         switch (pipe_config->ddi_pll_sel) {
9740         case SKL_DPLL0:
9741                 id = DPLL_ID_SKL_DPLL0;
9742                 break;
9743         case SKL_DPLL1:
9744                 id = DPLL_ID_SKL_DPLL1;
9745                 break;
9746         case SKL_DPLL2:
9747                 id = DPLL_ID_SKL_DPLL2;
9748                 break;
9749         case SKL_DPLL3:
9750                 id = DPLL_ID_SKL_DPLL3;
9751                 break;
9752         default:
9753                 MISSING_CASE(pipe_config->ddi_pll_sel);
9754                 return;
9755         }
9756
9757         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9758 }
9759
9760 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9761                                 enum port port,
9762                                 struct intel_crtc_state *pipe_config)
9763 {
9764         enum intel_dpll_id id;
9765
9766         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9767
9768         switch (pipe_config->ddi_pll_sel) {
9769         case PORT_CLK_SEL_WRPLL1:
9770                 id = DPLL_ID_WRPLL1;
9771                 break;
9772         case PORT_CLK_SEL_WRPLL2:
9773                 id = DPLL_ID_WRPLL2;
9774                 break;
9775         case PORT_CLK_SEL_SPLL:
9776                 id = DPLL_ID_SPLL;
9777                 break;
9778         case PORT_CLK_SEL_LCPLL_810:
9779                 id = DPLL_ID_LCPLL_810;
9780                 break;
9781         case PORT_CLK_SEL_LCPLL_1350:
9782                 id = DPLL_ID_LCPLL_1350;
9783                 break;
9784         case PORT_CLK_SEL_LCPLL_2700:
9785                 id = DPLL_ID_LCPLL_2700;
9786                 break;
9787         default:
9788                 MISSING_CASE(pipe_config->ddi_pll_sel);
9789                 /* fall through */
9790         case PORT_CLK_SEL_NONE:
9791                 return;
9792         }
9793
9794         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9795 }
9796
9797 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9798                                      struct intel_crtc_state *pipe_config,
9799                                      unsigned long *power_domain_mask)
9800 {
9801         struct drm_device *dev = crtc->base.dev;
9802         struct drm_i915_private *dev_priv = dev->dev_private;
9803         enum intel_display_power_domain power_domain;
9804         u32 tmp;
9805
9806         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9807
9808         /*
9809          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9810          * consistency and less surprising code; it's in always on power).
9811          */
9812         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9813         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9814                 enum pipe trans_edp_pipe;
9815                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9816                 default:
9817                         WARN(1, "unknown pipe linked to edp transcoder\n");
9818                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9819                 case TRANS_DDI_EDP_INPUT_A_ON:
9820                         trans_edp_pipe = PIPE_A;
9821                         break;
9822                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9823                         trans_edp_pipe = PIPE_B;
9824                         break;
9825                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9826                         trans_edp_pipe = PIPE_C;
9827                         break;
9828                 }
9829
9830                 if (trans_edp_pipe == crtc->pipe)
9831                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9832         }
9833
9834         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9835         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9836                 return false;
9837         *power_domain_mask |= BIT(power_domain);
9838
9839         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9840
9841         return tmp & PIPECONF_ENABLE;
9842 }
9843
9844 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9845                                          struct intel_crtc_state *pipe_config,
9846                                          unsigned long *power_domain_mask)
9847 {
9848         struct drm_device *dev = crtc->base.dev;
9849         struct drm_i915_private *dev_priv = dev->dev_private;
9850         enum intel_display_power_domain power_domain;
9851         enum port port;
9852         enum transcoder cpu_transcoder;
9853         u32 tmp;
9854
9855         pipe_config->has_dsi_encoder = false;
9856
9857         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9858                 if (port == PORT_A)
9859                         cpu_transcoder = TRANSCODER_DSI_A;
9860                 else
9861                         cpu_transcoder = TRANSCODER_DSI_C;
9862
9863                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9864                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9865                         continue;
9866                 *power_domain_mask |= BIT(power_domain);
9867
9868                 /* XXX: this works for video mode only */
9869                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9870                 if (!(tmp & DPI_ENABLE))
9871                         continue;
9872
9873                 tmp = I915_READ(MIPI_CTRL(port));
9874                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9875                         continue;
9876
9877                 pipe_config->cpu_transcoder = cpu_transcoder;
9878                 pipe_config->has_dsi_encoder = true;
9879                 break;
9880         }
9881
9882         return pipe_config->has_dsi_encoder;
9883 }
9884
9885 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9886                                        struct intel_crtc_state *pipe_config)
9887 {
9888         struct drm_device *dev = crtc->base.dev;
9889         struct drm_i915_private *dev_priv = dev->dev_private;
9890         struct intel_shared_dpll *pll;
9891         enum port port;
9892         uint32_t tmp;
9893
9894         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9895
9896         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9897
9898         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9899                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9900         else if (IS_BROXTON(dev))
9901                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9902         else
9903                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9904
9905         pll = pipe_config->shared_dpll;
9906         if (pll) {
9907                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9908                                                  &pipe_config->dpll_hw_state));
9909         }
9910
9911         /*
9912          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9913          * DDI E. So just check whether this pipe is wired to DDI E and whether
9914          * the PCH transcoder is on.
9915          */
9916         if (INTEL_INFO(dev)->gen < 9 &&
9917             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9918                 pipe_config->has_pch_encoder = true;
9919
9920                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9921                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9922                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9923
9924                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9925         }
9926 }
9927
9928 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9929                                     struct intel_crtc_state *pipe_config)
9930 {
9931         struct drm_device *dev = crtc->base.dev;
9932         struct drm_i915_private *dev_priv = dev->dev_private;
9933         enum intel_display_power_domain power_domain;
9934         unsigned long power_domain_mask;
9935         bool active;
9936
9937         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9938         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9939                 return false;
9940         power_domain_mask = BIT(power_domain);
9941
9942         pipe_config->shared_dpll = NULL;
9943
9944         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9945
9946         if (IS_BROXTON(dev_priv)) {
9947                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9948                                              &power_domain_mask);
9949                 WARN_ON(active && pipe_config->has_dsi_encoder);
9950                 if (pipe_config->has_dsi_encoder)
9951                         active = true;
9952         }
9953
9954         if (!active)
9955                 goto out;
9956
9957         if (!pipe_config->has_dsi_encoder) {
9958                 haswell_get_ddi_port_state(crtc, pipe_config);
9959                 intel_get_pipe_timings(crtc, pipe_config);
9960         }
9961
9962         intel_get_pipe_src_size(crtc, pipe_config);
9963
9964         if (INTEL_INFO(dev)->gen >= 9) {
9965                 skl_init_scalers(dev, crtc, pipe_config);
9966         }
9967
9968         if (INTEL_INFO(dev)->gen >= 9) {
9969                 pipe_config->scaler_state.scaler_id = -1;
9970                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9971         }
9972
9973         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9974         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9975                 power_domain_mask |= BIT(power_domain);
9976                 if (INTEL_INFO(dev)->gen >= 9)
9977                         skylake_get_pfit_config(crtc, pipe_config);
9978                 else
9979                         ironlake_get_pfit_config(crtc, pipe_config);
9980         }
9981
9982         if (IS_HASWELL(dev))
9983                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9984                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9985
9986         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9987             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9988                 pipe_config->pixel_multiplier =
9989                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9990         } else {
9991                 pipe_config->pixel_multiplier = 1;
9992         }
9993
9994 out:
9995         for_each_power_domain(power_domain, power_domain_mask)
9996                 intel_display_power_put(dev_priv, power_domain);
9997
9998         return active;
9999 }
10000
10001 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10002                                const struct intel_plane_state *plane_state)
10003 {
10004         struct drm_device *dev = crtc->dev;
10005         struct drm_i915_private *dev_priv = dev->dev_private;
10006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10007         uint32_t cntl = 0, size = 0;
10008
10009         if (plane_state && plane_state->visible) {
10010                 unsigned int width = plane_state->base.crtc_w;
10011                 unsigned int height = plane_state->base.crtc_h;
10012                 unsigned int stride = roundup_pow_of_two(width) * 4;
10013
10014                 switch (stride) {
10015                 default:
10016                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10017                                   width, stride);
10018                         stride = 256;
10019                         /* fallthrough */
10020                 case 256:
10021                 case 512:
10022                 case 1024:
10023                 case 2048:
10024                         break;
10025                 }
10026
10027                 cntl |= CURSOR_ENABLE |
10028                         CURSOR_GAMMA_ENABLE |
10029                         CURSOR_FORMAT_ARGB |
10030                         CURSOR_STRIDE(stride);
10031
10032                 size = (height << 12) | width;
10033         }
10034
10035         if (intel_crtc->cursor_cntl != 0 &&
10036             (intel_crtc->cursor_base != base ||
10037              intel_crtc->cursor_size != size ||
10038              intel_crtc->cursor_cntl != cntl)) {
10039                 /* On these chipsets we can only modify the base/size/stride
10040                  * whilst the cursor is disabled.
10041                  */
10042                 I915_WRITE(CURCNTR(PIPE_A), 0);
10043                 POSTING_READ(CURCNTR(PIPE_A));
10044                 intel_crtc->cursor_cntl = 0;
10045         }
10046
10047         if (intel_crtc->cursor_base != base) {
10048                 I915_WRITE(CURBASE(PIPE_A), base);
10049                 intel_crtc->cursor_base = base;
10050         }
10051
10052         if (intel_crtc->cursor_size != size) {
10053                 I915_WRITE(CURSIZE, size);
10054                 intel_crtc->cursor_size = size;
10055         }
10056
10057         if (intel_crtc->cursor_cntl != cntl) {
10058                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10059                 POSTING_READ(CURCNTR(PIPE_A));
10060                 intel_crtc->cursor_cntl = cntl;
10061         }
10062 }
10063
10064 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10065                                const struct intel_plane_state *plane_state)
10066 {
10067         struct drm_device *dev = crtc->dev;
10068         struct drm_i915_private *dev_priv = dev->dev_private;
10069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10070         int pipe = intel_crtc->pipe;
10071         uint32_t cntl = 0;
10072
10073         if (plane_state && plane_state->visible) {
10074                 cntl = MCURSOR_GAMMA_ENABLE;
10075                 switch (plane_state->base.crtc_w) {
10076                         case 64:
10077                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10078                                 break;
10079                         case 128:
10080                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10081                                 break;
10082                         case 256:
10083                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10084                                 break;
10085                         default:
10086                                 MISSING_CASE(plane_state->base.crtc_w);
10087                                 return;
10088                 }
10089                 cntl |= pipe << 28; /* Connect to correct pipe */
10090
10091                 if (HAS_DDI(dev))
10092                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10093
10094                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10095                         cntl |= CURSOR_ROTATE_180;
10096         }
10097
10098         if (intel_crtc->cursor_cntl != cntl) {
10099                 I915_WRITE(CURCNTR(pipe), cntl);
10100                 POSTING_READ(CURCNTR(pipe));
10101                 intel_crtc->cursor_cntl = cntl;
10102         }
10103
10104         /* and commit changes on next vblank */
10105         I915_WRITE(CURBASE(pipe), base);
10106         POSTING_READ(CURBASE(pipe));
10107
10108         intel_crtc->cursor_base = base;
10109 }
10110
10111 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10112 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10113                                      const struct intel_plane_state *plane_state)
10114 {
10115         struct drm_device *dev = crtc->dev;
10116         struct drm_i915_private *dev_priv = dev->dev_private;
10117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10118         int pipe = intel_crtc->pipe;
10119         u32 base = intel_crtc->cursor_addr;
10120         u32 pos = 0;
10121
10122         if (plane_state) {
10123                 int x = plane_state->base.crtc_x;
10124                 int y = plane_state->base.crtc_y;
10125
10126                 if (x < 0) {
10127                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10128                         x = -x;
10129                 }
10130                 pos |= x << CURSOR_X_SHIFT;
10131
10132                 if (y < 0) {
10133                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10134                         y = -y;
10135                 }
10136                 pos |= y << CURSOR_Y_SHIFT;
10137
10138                 /* ILK+ do this automagically */
10139                 if (HAS_GMCH_DISPLAY(dev) &&
10140                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10141                         base += (plane_state->base.crtc_h *
10142                                  plane_state->base.crtc_w - 1) * 4;
10143                 }
10144         }
10145
10146         I915_WRITE(CURPOS(pipe), pos);
10147
10148         if (IS_845G(dev) || IS_I865G(dev))
10149                 i845_update_cursor(crtc, base, plane_state);
10150         else
10151                 i9xx_update_cursor(crtc, base, plane_state);
10152 }
10153
10154 static bool cursor_size_ok(struct drm_device *dev,
10155                            uint32_t width, uint32_t height)
10156 {
10157         if (width == 0 || height == 0)
10158                 return false;
10159
10160         /*
10161          * 845g/865g are special in that they are only limited by
10162          * the width of their cursors, the height is arbitrary up to
10163          * the precision of the register. Everything else requires
10164          * square cursors, limited to a few power-of-two sizes.
10165          */
10166         if (IS_845G(dev) || IS_I865G(dev)) {
10167                 if ((width & 63) != 0)
10168                         return false;
10169
10170                 if (width > (IS_845G(dev) ? 64 : 512))
10171                         return false;
10172
10173                 if (height > 1023)
10174                         return false;
10175         } else {
10176                 switch (width | height) {
10177                 case 256:
10178                 case 128:
10179                         if (IS_GEN2(dev))
10180                                 return false;
10181                 case 64:
10182                         break;
10183                 default:
10184                         return false;
10185                 }
10186         }
10187
10188         return true;
10189 }
10190
10191 /* VESA 640x480x72Hz mode to set on the pipe */
10192 static struct drm_display_mode load_detect_mode = {
10193         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10194                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10195 };
10196
10197 struct drm_framebuffer *
10198 __intel_framebuffer_create(struct drm_device *dev,
10199                            struct drm_mode_fb_cmd2 *mode_cmd,
10200                            struct drm_i915_gem_object *obj)
10201 {
10202         struct intel_framebuffer *intel_fb;
10203         int ret;
10204
10205         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10206         if (!intel_fb)
10207                 return ERR_PTR(-ENOMEM);
10208
10209         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10210         if (ret)
10211                 goto err;
10212
10213         return &intel_fb->base;
10214
10215 err:
10216         kfree(intel_fb);
10217         return ERR_PTR(ret);
10218 }
10219
10220 static struct drm_framebuffer *
10221 intel_framebuffer_create(struct drm_device *dev,
10222                          struct drm_mode_fb_cmd2 *mode_cmd,
10223                          struct drm_i915_gem_object *obj)
10224 {
10225         struct drm_framebuffer *fb;
10226         int ret;
10227
10228         ret = i915_mutex_lock_interruptible(dev);
10229         if (ret)
10230                 return ERR_PTR(ret);
10231         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10232         mutex_unlock(&dev->struct_mutex);
10233
10234         return fb;
10235 }
10236
10237 static u32
10238 intel_framebuffer_pitch_for_width(int width, int bpp)
10239 {
10240         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10241         return ALIGN(pitch, 64);
10242 }
10243
10244 static u32
10245 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10246 {
10247         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10248         return PAGE_ALIGN(pitch * mode->vdisplay);
10249 }
10250
10251 static struct drm_framebuffer *
10252 intel_framebuffer_create_for_mode(struct drm_device *dev,
10253                                   struct drm_display_mode *mode,
10254                                   int depth, int bpp)
10255 {
10256         struct drm_framebuffer *fb;
10257         struct drm_i915_gem_object *obj;
10258         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10259
10260         obj = i915_gem_alloc_object(dev,
10261                                     intel_framebuffer_size_for_mode(mode, bpp));
10262         if (obj == NULL)
10263                 return ERR_PTR(-ENOMEM);
10264
10265         mode_cmd.width = mode->hdisplay;
10266         mode_cmd.height = mode->vdisplay;
10267         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10268                                                                 bpp);
10269         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10270
10271         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10272         if (IS_ERR(fb))
10273                 drm_gem_object_unreference_unlocked(&obj->base);
10274
10275         return fb;
10276 }
10277
10278 static struct drm_framebuffer *
10279 mode_fits_in_fbdev(struct drm_device *dev,
10280                    struct drm_display_mode *mode)
10281 {
10282 #ifdef CONFIG_DRM_FBDEV_EMULATION
10283         struct drm_i915_private *dev_priv = dev->dev_private;
10284         struct drm_i915_gem_object *obj;
10285         struct drm_framebuffer *fb;
10286
10287         if (!dev_priv->fbdev)
10288                 return NULL;
10289
10290         if (!dev_priv->fbdev->fb)
10291                 return NULL;
10292
10293         obj = dev_priv->fbdev->fb->obj;
10294         BUG_ON(!obj);
10295
10296         fb = &dev_priv->fbdev->fb->base;
10297         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10298                                                                fb->bits_per_pixel))
10299                 return NULL;
10300
10301         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10302                 return NULL;
10303
10304         drm_framebuffer_reference(fb);
10305         return fb;
10306 #else
10307         return NULL;
10308 #endif
10309 }
10310
10311 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10312                                            struct drm_crtc *crtc,
10313                                            struct drm_display_mode *mode,
10314                                            struct drm_framebuffer *fb,
10315                                            int x, int y)
10316 {
10317         struct drm_plane_state *plane_state;
10318         int hdisplay, vdisplay;
10319         int ret;
10320
10321         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10322         if (IS_ERR(plane_state))
10323                 return PTR_ERR(plane_state);
10324
10325         if (mode)
10326                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10327         else
10328                 hdisplay = vdisplay = 0;
10329
10330         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10331         if (ret)
10332                 return ret;
10333         drm_atomic_set_fb_for_plane(plane_state, fb);
10334         plane_state->crtc_x = 0;
10335         plane_state->crtc_y = 0;
10336         plane_state->crtc_w = hdisplay;
10337         plane_state->crtc_h = vdisplay;
10338         plane_state->src_x = x << 16;
10339         plane_state->src_y = y << 16;
10340         plane_state->src_w = hdisplay << 16;
10341         plane_state->src_h = vdisplay << 16;
10342
10343         return 0;
10344 }
10345
10346 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10347                                 struct drm_display_mode *mode,
10348                                 struct intel_load_detect_pipe *old,
10349                                 struct drm_modeset_acquire_ctx *ctx)
10350 {
10351         struct intel_crtc *intel_crtc;
10352         struct intel_encoder *intel_encoder =
10353                 intel_attached_encoder(connector);
10354         struct drm_crtc *possible_crtc;
10355         struct drm_encoder *encoder = &intel_encoder->base;
10356         struct drm_crtc *crtc = NULL;
10357         struct drm_device *dev = encoder->dev;
10358         struct drm_framebuffer *fb;
10359         struct drm_mode_config *config = &dev->mode_config;
10360         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10361         struct drm_connector_state *connector_state;
10362         struct intel_crtc_state *crtc_state;
10363         int ret, i = -1;
10364
10365         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10366                       connector->base.id, connector->name,
10367                       encoder->base.id, encoder->name);
10368
10369         old->restore_state = NULL;
10370
10371 retry:
10372         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10373         if (ret)
10374                 goto fail;
10375
10376         /*
10377          * Algorithm gets a little messy:
10378          *
10379          *   - if the connector already has an assigned crtc, use it (but make
10380          *     sure it's on first)
10381          *
10382          *   - try to find the first unused crtc that can drive this connector,
10383          *     and use that if we find one
10384          */
10385
10386         /* See if we already have a CRTC for this connector */
10387         if (connector->state->crtc) {
10388                 crtc = connector->state->crtc;
10389
10390                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10391                 if (ret)
10392                         goto fail;
10393
10394                 /* Make sure the crtc and connector are running */
10395                 goto found;
10396         }
10397
10398         /* Find an unused one (if possible) */
10399         for_each_crtc(dev, possible_crtc) {
10400                 i++;
10401                 if (!(encoder->possible_crtcs & (1 << i)))
10402                         continue;
10403
10404                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10405                 if (ret)
10406                         goto fail;
10407
10408                 if (possible_crtc->state->enable) {
10409                         drm_modeset_unlock(&possible_crtc->mutex);
10410                         continue;
10411                 }
10412
10413                 crtc = possible_crtc;
10414                 break;
10415         }
10416
10417         /*
10418          * If we didn't find an unused CRTC, don't use any.
10419          */
10420         if (!crtc) {
10421                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10422                 goto fail;
10423         }
10424
10425 found:
10426         intel_crtc = to_intel_crtc(crtc);
10427
10428         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10429         if (ret)
10430                 goto fail;
10431
10432         state = drm_atomic_state_alloc(dev);
10433         restore_state = drm_atomic_state_alloc(dev);
10434         if (!state || !restore_state) {
10435                 ret = -ENOMEM;
10436                 goto fail;
10437         }
10438
10439         state->acquire_ctx = ctx;
10440         restore_state->acquire_ctx = ctx;
10441
10442         connector_state = drm_atomic_get_connector_state(state, connector);
10443         if (IS_ERR(connector_state)) {
10444                 ret = PTR_ERR(connector_state);
10445                 goto fail;
10446         }
10447
10448         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10449         if (ret)
10450                 goto fail;
10451
10452         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10453         if (IS_ERR(crtc_state)) {
10454                 ret = PTR_ERR(crtc_state);
10455                 goto fail;
10456         }
10457
10458         crtc_state->base.active = crtc_state->base.enable = true;
10459
10460         if (!mode)
10461                 mode = &load_detect_mode;
10462
10463         /* We need a framebuffer large enough to accommodate all accesses
10464          * that the plane may generate whilst we perform load detection.
10465          * We can not rely on the fbcon either being present (we get called
10466          * during its initialisation to detect all boot displays, or it may
10467          * not even exist) or that it is large enough to satisfy the
10468          * requested mode.
10469          */
10470         fb = mode_fits_in_fbdev(dev, mode);
10471         if (fb == NULL) {
10472                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10473                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10474         } else
10475                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10476         if (IS_ERR(fb)) {
10477                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10478                 goto fail;
10479         }
10480
10481         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10482         if (ret)
10483                 goto fail;
10484
10485         drm_framebuffer_unreference(fb);
10486
10487         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10488         if (ret)
10489                 goto fail;
10490
10491         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10492         if (!ret)
10493                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10494         if (!ret)
10495                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10496         if (ret) {
10497                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10498                 goto fail;
10499         }
10500
10501         ret = drm_atomic_commit(state);
10502         if (ret) {
10503                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10504                 goto fail;
10505         }
10506
10507         old->restore_state = restore_state;
10508
10509         /* let the connector get through one full cycle before testing */
10510         intel_wait_for_vblank(dev, intel_crtc->pipe);
10511         return true;
10512
10513 fail:
10514         drm_atomic_state_free(state);
10515         drm_atomic_state_free(restore_state);
10516         restore_state = state = NULL;
10517
10518         if (ret == -EDEADLK) {
10519                 drm_modeset_backoff(ctx);
10520                 goto retry;
10521         }
10522
10523         return false;
10524 }
10525
10526 void intel_release_load_detect_pipe(struct drm_connector *connector,
10527                                     struct intel_load_detect_pipe *old,
10528                                     struct drm_modeset_acquire_ctx *ctx)
10529 {
10530         struct intel_encoder *intel_encoder =
10531                 intel_attached_encoder(connector);
10532         struct drm_encoder *encoder = &intel_encoder->base;
10533         struct drm_atomic_state *state = old->restore_state;
10534         int ret;
10535
10536         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10537                       connector->base.id, connector->name,
10538                       encoder->base.id, encoder->name);
10539
10540         if (!state)
10541                 return;
10542
10543         ret = drm_atomic_commit(state);
10544         if (ret) {
10545                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10546                 drm_atomic_state_free(state);
10547         }
10548 }
10549
10550 static int i9xx_pll_refclk(struct drm_device *dev,
10551                            const struct intel_crtc_state *pipe_config)
10552 {
10553         struct drm_i915_private *dev_priv = dev->dev_private;
10554         u32 dpll = pipe_config->dpll_hw_state.dpll;
10555
10556         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10557                 return dev_priv->vbt.lvds_ssc_freq;
10558         else if (HAS_PCH_SPLIT(dev))
10559                 return 120000;
10560         else if (!IS_GEN2(dev))
10561                 return 96000;
10562         else
10563                 return 48000;
10564 }
10565
10566 /* Returns the clock of the currently programmed mode of the given pipe. */
10567 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10568                                 struct intel_crtc_state *pipe_config)
10569 {
10570         struct drm_device *dev = crtc->base.dev;
10571         struct drm_i915_private *dev_priv = dev->dev_private;
10572         int pipe = pipe_config->cpu_transcoder;
10573         u32 dpll = pipe_config->dpll_hw_state.dpll;
10574         u32 fp;
10575         intel_clock_t clock;
10576         int port_clock;
10577         int refclk = i9xx_pll_refclk(dev, pipe_config);
10578
10579         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10580                 fp = pipe_config->dpll_hw_state.fp0;
10581         else
10582                 fp = pipe_config->dpll_hw_state.fp1;
10583
10584         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10585         if (IS_PINEVIEW(dev)) {
10586                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10587                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10588         } else {
10589                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10590                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10591         }
10592
10593         if (!IS_GEN2(dev)) {
10594                 if (IS_PINEVIEW(dev))
10595                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10596                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10597                 else
10598                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10599                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10600
10601                 switch (dpll & DPLL_MODE_MASK) {
10602                 case DPLLB_MODE_DAC_SERIAL:
10603                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10604                                 5 : 10;
10605                         break;
10606                 case DPLLB_MODE_LVDS:
10607                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10608                                 7 : 14;
10609                         break;
10610                 default:
10611                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10612                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10613                         return;
10614                 }
10615
10616                 if (IS_PINEVIEW(dev))
10617                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10618                 else
10619                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10620         } else {
10621                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10622                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10623
10624                 if (is_lvds) {
10625                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10626                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10627
10628                         if (lvds & LVDS_CLKB_POWER_UP)
10629                                 clock.p2 = 7;
10630                         else
10631                                 clock.p2 = 14;
10632                 } else {
10633                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10634                                 clock.p1 = 2;
10635                         else {
10636                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10637                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10638                         }
10639                         if (dpll & PLL_P2_DIVIDE_BY_4)
10640                                 clock.p2 = 4;
10641                         else
10642                                 clock.p2 = 2;
10643                 }
10644
10645                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10646         }
10647
10648         /*
10649          * This value includes pixel_multiplier. We will use
10650          * port_clock to compute adjusted_mode.crtc_clock in the
10651          * encoder's get_config() function.
10652          */
10653         pipe_config->port_clock = port_clock;
10654 }
10655
10656 int intel_dotclock_calculate(int link_freq,
10657                              const struct intel_link_m_n *m_n)
10658 {
10659         /*
10660          * The calculation for the data clock is:
10661          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10662          * But we want to avoid losing precison if possible, so:
10663          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10664          *
10665          * and the link clock is simpler:
10666          * link_clock = (m * link_clock) / n
10667          */
10668
10669         if (!m_n->link_n)
10670                 return 0;
10671
10672         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10673 }
10674
10675 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10676                                    struct intel_crtc_state *pipe_config)
10677 {
10678         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10679
10680         /* read out port_clock from the DPLL */
10681         i9xx_crtc_clock_get(crtc, pipe_config);
10682
10683         /*
10684          * In case there is an active pipe without active ports,
10685          * we may need some idea for the dotclock anyway.
10686          * Calculate one based on the FDI configuration.
10687          */
10688         pipe_config->base.adjusted_mode.crtc_clock =
10689                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10690                                          &pipe_config->fdi_m_n);
10691 }
10692
10693 /** Returns the currently programmed mode of the given pipe. */
10694 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10695                                              struct drm_crtc *crtc)
10696 {
10697         struct drm_i915_private *dev_priv = dev->dev_private;
10698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10699         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10700         struct drm_display_mode *mode;
10701         struct intel_crtc_state *pipe_config;
10702         int htot = I915_READ(HTOTAL(cpu_transcoder));
10703         int hsync = I915_READ(HSYNC(cpu_transcoder));
10704         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10705         int vsync = I915_READ(VSYNC(cpu_transcoder));
10706         enum pipe pipe = intel_crtc->pipe;
10707
10708         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10709         if (!mode)
10710                 return NULL;
10711
10712         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10713         if (!pipe_config) {
10714                 kfree(mode);
10715                 return NULL;
10716         }
10717
10718         /*
10719          * Construct a pipe_config sufficient for getting the clock info
10720          * back out of crtc_clock_get.
10721          *
10722          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10723          * to use a real value here instead.
10724          */
10725         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10726         pipe_config->pixel_multiplier = 1;
10727         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10728         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10729         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10730         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10731
10732         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10733         mode->hdisplay = (htot & 0xffff) + 1;
10734         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10735         mode->hsync_start = (hsync & 0xffff) + 1;
10736         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10737         mode->vdisplay = (vtot & 0xffff) + 1;
10738         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10739         mode->vsync_start = (vsync & 0xffff) + 1;
10740         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10741
10742         drm_mode_set_name(mode);
10743
10744         kfree(pipe_config);
10745
10746         return mode;
10747 }
10748
10749 void intel_mark_busy(struct drm_device *dev)
10750 {
10751         struct drm_i915_private *dev_priv = dev->dev_private;
10752
10753         if (dev_priv->mm.busy)
10754                 return;
10755
10756         intel_runtime_pm_get(dev_priv);
10757         i915_update_gfx_val(dev_priv);
10758         if (INTEL_INFO(dev)->gen >= 6)
10759                 gen6_rps_busy(dev_priv);
10760         dev_priv->mm.busy = true;
10761 }
10762
10763 void intel_mark_idle(struct drm_device *dev)
10764 {
10765         struct drm_i915_private *dev_priv = dev->dev_private;
10766
10767         if (!dev_priv->mm.busy)
10768                 return;
10769
10770         dev_priv->mm.busy = false;
10771
10772         if (INTEL_INFO(dev)->gen >= 6)
10773                 gen6_rps_idle(dev->dev_private);
10774
10775         intel_runtime_pm_put(dev_priv);
10776 }
10777
10778 static void intel_crtc_destroy(struct drm_crtc *crtc)
10779 {
10780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10781         struct drm_device *dev = crtc->dev;
10782         struct intel_unpin_work *work;
10783
10784         spin_lock_irq(&dev->event_lock);
10785         work = intel_crtc->unpin_work;
10786         intel_crtc->unpin_work = NULL;
10787         spin_unlock_irq(&dev->event_lock);
10788
10789         if (work) {
10790                 cancel_work_sync(&work->work);
10791                 kfree(work);
10792         }
10793
10794         drm_crtc_cleanup(crtc);
10795
10796         kfree(intel_crtc);
10797 }
10798
10799 static void intel_unpin_work_fn(struct work_struct *__work)
10800 {
10801         struct intel_unpin_work *work =
10802                 container_of(__work, struct intel_unpin_work, work);
10803         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10804         struct drm_device *dev = crtc->base.dev;
10805         struct drm_plane *primary = crtc->base.primary;
10806
10807         mutex_lock(&dev->struct_mutex);
10808         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10809         drm_gem_object_unreference(&work->pending_flip_obj->base);
10810
10811         if (work->flip_queued_req)
10812                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10813         mutex_unlock(&dev->struct_mutex);
10814
10815         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10816         intel_fbc_post_update(crtc);
10817         drm_framebuffer_unreference(work->old_fb);
10818
10819         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10820         atomic_dec(&crtc->unpin_work_count);
10821
10822         kfree(work);
10823 }
10824
10825 static void do_intel_finish_page_flip(struct drm_device *dev,
10826                                       struct drm_crtc *crtc)
10827 {
10828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10829         struct intel_unpin_work *work;
10830         unsigned long flags;
10831
10832         /* Ignore early vblank irqs */
10833         if (intel_crtc == NULL)
10834                 return;
10835
10836         /*
10837          * This is called both by irq handlers and the reset code (to complete
10838          * lost pageflips) so needs the full irqsave spinlocks.
10839          */
10840         spin_lock_irqsave(&dev->event_lock, flags);
10841         work = intel_crtc->unpin_work;
10842
10843         /* Ensure we don't miss a work->pending update ... */
10844         smp_rmb();
10845
10846         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10847                 spin_unlock_irqrestore(&dev->event_lock, flags);
10848                 return;
10849         }
10850
10851         page_flip_completed(intel_crtc);
10852
10853         spin_unlock_irqrestore(&dev->event_lock, flags);
10854 }
10855
10856 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10857 {
10858         struct drm_i915_private *dev_priv = dev->dev_private;
10859         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10860
10861         do_intel_finish_page_flip(dev, crtc);
10862 }
10863
10864 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10865 {
10866         struct drm_i915_private *dev_priv = dev->dev_private;
10867         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10868
10869         do_intel_finish_page_flip(dev, crtc);
10870 }
10871
10872 /* Is 'a' after or equal to 'b'? */
10873 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10874 {
10875         return !((a - b) & 0x80000000);
10876 }
10877
10878 static bool page_flip_finished(struct intel_crtc *crtc)
10879 {
10880         struct drm_device *dev = crtc->base.dev;
10881         struct drm_i915_private *dev_priv = dev->dev_private;
10882
10883         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10884             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10885                 return true;
10886
10887         /*
10888          * The relevant registers doen't exist on pre-ctg.
10889          * As the flip done interrupt doesn't trigger for mmio
10890          * flips on gmch platforms, a flip count check isn't
10891          * really needed there. But since ctg has the registers,
10892          * include it in the check anyway.
10893          */
10894         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10895                 return true;
10896
10897         /*
10898          * BDW signals flip done immediately if the plane
10899          * is disabled, even if the plane enable is already
10900          * armed to occur at the next vblank :(
10901          */
10902
10903         /*
10904          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10905          * used the same base address. In that case the mmio flip might
10906          * have completed, but the CS hasn't even executed the flip yet.
10907          *
10908          * A flip count check isn't enough as the CS might have updated
10909          * the base address just after start of vblank, but before we
10910          * managed to process the interrupt. This means we'd complete the
10911          * CS flip too soon.
10912          *
10913          * Combining both checks should get us a good enough result. It may
10914          * still happen that the CS flip has been executed, but has not
10915          * yet actually completed. But in case the base address is the same
10916          * anyway, we don't really care.
10917          */
10918         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10919                 crtc->unpin_work->gtt_offset &&
10920                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10921                                     crtc->unpin_work->flip_count);
10922 }
10923
10924 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10925 {
10926         struct drm_i915_private *dev_priv = dev->dev_private;
10927         struct intel_crtc *intel_crtc =
10928                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10929         unsigned long flags;
10930
10931
10932         /*
10933          * This is called both by irq handlers and the reset code (to complete
10934          * lost pageflips) so needs the full irqsave spinlocks.
10935          *
10936          * NB: An MMIO update of the plane base pointer will also
10937          * generate a page-flip completion irq, i.e. every modeset
10938          * is also accompanied by a spurious intel_prepare_page_flip().
10939          */
10940         spin_lock_irqsave(&dev->event_lock, flags);
10941         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10942                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10943         spin_unlock_irqrestore(&dev->event_lock, flags);
10944 }
10945
10946 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10947 {
10948         /* Ensure that the work item is consistent when activating it ... */
10949         smp_wmb();
10950         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10951         /* and that it is marked active as soon as the irq could fire. */
10952         smp_wmb();
10953 }
10954
10955 static int intel_gen2_queue_flip(struct drm_device *dev,
10956                                  struct drm_crtc *crtc,
10957                                  struct drm_framebuffer *fb,
10958                                  struct drm_i915_gem_object *obj,
10959                                  struct drm_i915_gem_request *req,
10960                                  uint32_t flags)
10961 {
10962         struct intel_engine_cs *engine = req->engine;
10963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10964         u32 flip_mask;
10965         int ret;
10966
10967         ret = intel_ring_begin(req, 6);
10968         if (ret)
10969                 return ret;
10970
10971         /* Can't queue multiple flips, so wait for the previous
10972          * one to finish before executing the next.
10973          */
10974         if (intel_crtc->plane)
10975                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10976         else
10977                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10978         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
10979         intel_ring_emit(engine, MI_NOOP);
10980         intel_ring_emit(engine, MI_DISPLAY_FLIP |
10981                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10982         intel_ring_emit(engine, fb->pitches[0]);
10983         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
10984         intel_ring_emit(engine, 0); /* aux display base address, unused */
10985
10986         intel_mark_page_flip_active(intel_crtc->unpin_work);
10987         return 0;
10988 }
10989
10990 static int intel_gen3_queue_flip(struct drm_device *dev,
10991                                  struct drm_crtc *crtc,
10992                                  struct drm_framebuffer *fb,
10993                                  struct drm_i915_gem_object *obj,
10994                                  struct drm_i915_gem_request *req,
10995                                  uint32_t flags)
10996 {
10997         struct intel_engine_cs *engine = req->engine;
10998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10999         u32 flip_mask;
11000         int ret;
11001
11002         ret = intel_ring_begin(req, 6);
11003         if (ret)
11004                 return ret;
11005
11006         if (intel_crtc->plane)
11007                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11008         else
11009                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11010         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11011         intel_ring_emit(engine, MI_NOOP);
11012         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11013                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11014         intel_ring_emit(engine, fb->pitches[0]);
11015         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11016         intel_ring_emit(engine, MI_NOOP);
11017
11018         intel_mark_page_flip_active(intel_crtc->unpin_work);
11019         return 0;
11020 }
11021
11022 static int intel_gen4_queue_flip(struct drm_device *dev,
11023                                  struct drm_crtc *crtc,
11024                                  struct drm_framebuffer *fb,
11025                                  struct drm_i915_gem_object *obj,
11026                                  struct drm_i915_gem_request *req,
11027                                  uint32_t flags)
11028 {
11029         struct intel_engine_cs *engine = req->engine;
11030         struct drm_i915_private *dev_priv = dev->dev_private;
11031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11032         uint32_t pf, pipesrc;
11033         int ret;
11034
11035         ret = intel_ring_begin(req, 4);
11036         if (ret)
11037                 return ret;
11038
11039         /* i965+ uses the linear or tiled offsets from the
11040          * Display Registers (which do not change across a page-flip)
11041          * so we need only reprogram the base address.
11042          */
11043         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11044                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11045         intel_ring_emit(engine, fb->pitches[0]);
11046         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11047                         obj->tiling_mode);
11048
11049         /* XXX Enabling the panel-fitter across page-flip is so far
11050          * untested on non-native modes, so ignore it for now.
11051          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11052          */
11053         pf = 0;
11054         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11055         intel_ring_emit(engine, pf | pipesrc);
11056
11057         intel_mark_page_flip_active(intel_crtc->unpin_work);
11058         return 0;
11059 }
11060
11061 static int intel_gen6_queue_flip(struct drm_device *dev,
11062                                  struct drm_crtc *crtc,
11063                                  struct drm_framebuffer *fb,
11064                                  struct drm_i915_gem_object *obj,
11065                                  struct drm_i915_gem_request *req,
11066                                  uint32_t flags)
11067 {
11068         struct intel_engine_cs *engine = req->engine;
11069         struct drm_i915_private *dev_priv = dev->dev_private;
11070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11071         uint32_t pf, pipesrc;
11072         int ret;
11073
11074         ret = intel_ring_begin(req, 4);
11075         if (ret)
11076                 return ret;
11077
11078         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11079                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11080         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11081         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11082
11083         /* Contrary to the suggestions in the documentation,
11084          * "Enable Panel Fitter" does not seem to be required when page
11085          * flipping with a non-native mode, and worse causes a normal
11086          * modeset to fail.
11087          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11088          */
11089         pf = 0;
11090         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11091         intel_ring_emit(engine, pf | pipesrc);
11092
11093         intel_mark_page_flip_active(intel_crtc->unpin_work);
11094         return 0;
11095 }
11096
11097 static int intel_gen7_queue_flip(struct drm_device *dev,
11098                                  struct drm_crtc *crtc,
11099                                  struct drm_framebuffer *fb,
11100                                  struct drm_i915_gem_object *obj,
11101                                  struct drm_i915_gem_request *req,
11102                                  uint32_t flags)
11103 {
11104         struct intel_engine_cs *engine = req->engine;
11105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11106         uint32_t plane_bit = 0;
11107         int len, ret;
11108
11109         switch (intel_crtc->plane) {
11110         case PLANE_A:
11111                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11112                 break;
11113         case PLANE_B:
11114                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11115                 break;
11116         case PLANE_C:
11117                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11118                 break;
11119         default:
11120                 WARN_ONCE(1, "unknown plane in flip command\n");
11121                 return -ENODEV;
11122         }
11123
11124         len = 4;
11125         if (engine->id == RCS) {
11126                 len += 6;
11127                 /*
11128                  * On Gen 8, SRM is now taking an extra dword to accommodate
11129                  * 48bits addresses, and we need a NOOP for the batch size to
11130                  * stay even.
11131                  */
11132                 if (IS_GEN8(dev))
11133                         len += 2;
11134         }
11135
11136         /*
11137          * BSpec MI_DISPLAY_FLIP for IVB:
11138          * "The full packet must be contained within the same cache line."
11139          *
11140          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11141          * cacheline, if we ever start emitting more commands before
11142          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11143          * then do the cacheline alignment, and finally emit the
11144          * MI_DISPLAY_FLIP.
11145          */
11146         ret = intel_ring_cacheline_align(req);
11147         if (ret)
11148                 return ret;
11149
11150         ret = intel_ring_begin(req, len);
11151         if (ret)
11152                 return ret;
11153
11154         /* Unmask the flip-done completion message. Note that the bspec says that
11155          * we should do this for both the BCS and RCS, and that we must not unmask
11156          * more than one flip event at any time (or ensure that one flip message
11157          * can be sent by waiting for flip-done prior to queueing new flips).
11158          * Experimentation says that BCS works despite DERRMR masking all
11159          * flip-done completion events and that unmasking all planes at once
11160          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11161          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11162          */
11163         if (engine->id == RCS) {
11164                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11165                 intel_ring_emit_reg(engine, DERRMR);
11166                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11167                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11168                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11169                 if (IS_GEN8(dev))
11170                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11171                                               MI_SRM_LRM_GLOBAL_GTT);
11172                 else
11173                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11174                                               MI_SRM_LRM_GLOBAL_GTT);
11175                 intel_ring_emit_reg(engine, DERRMR);
11176                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11177                 if (IS_GEN8(dev)) {
11178                         intel_ring_emit(engine, 0);
11179                         intel_ring_emit(engine, MI_NOOP);
11180                 }
11181         }
11182
11183         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11184         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11185         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11186         intel_ring_emit(engine, (MI_NOOP));
11187
11188         intel_mark_page_flip_active(intel_crtc->unpin_work);
11189         return 0;
11190 }
11191
11192 static bool use_mmio_flip(struct intel_engine_cs *engine,
11193                           struct drm_i915_gem_object *obj)
11194 {
11195         /*
11196          * This is not being used for older platforms, because
11197          * non-availability of flip done interrupt forces us to use
11198          * CS flips. Older platforms derive flip done using some clever
11199          * tricks involving the flip_pending status bits and vblank irqs.
11200          * So using MMIO flips there would disrupt this mechanism.
11201          */
11202
11203         if (engine == NULL)
11204                 return true;
11205
11206         if (INTEL_INFO(engine->dev)->gen < 5)
11207                 return false;
11208
11209         if (i915.use_mmio_flip < 0)
11210                 return false;
11211         else if (i915.use_mmio_flip > 0)
11212                 return true;
11213         else if (i915.enable_execlists)
11214                 return true;
11215         else if (obj->base.dma_buf &&
11216                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11217                                                        false))
11218                 return true;
11219         else
11220                 return engine != i915_gem_request_get_engine(obj->last_write_req);
11221 }
11222
11223 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11224                              unsigned int rotation,
11225                              struct intel_unpin_work *work)
11226 {
11227         struct drm_device *dev = intel_crtc->base.dev;
11228         struct drm_i915_private *dev_priv = dev->dev_private;
11229         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11230         const enum pipe pipe = intel_crtc->pipe;
11231         u32 ctl, stride, tile_height;
11232
11233         ctl = I915_READ(PLANE_CTL(pipe, 0));
11234         ctl &= ~PLANE_CTL_TILED_MASK;
11235         switch (fb->modifier[0]) {
11236         case DRM_FORMAT_MOD_NONE:
11237                 break;
11238         case I915_FORMAT_MOD_X_TILED:
11239                 ctl |= PLANE_CTL_TILED_X;
11240                 break;
11241         case I915_FORMAT_MOD_Y_TILED:
11242                 ctl |= PLANE_CTL_TILED_Y;
11243                 break;
11244         case I915_FORMAT_MOD_Yf_TILED:
11245                 ctl |= PLANE_CTL_TILED_YF;
11246                 break;
11247         default:
11248                 MISSING_CASE(fb->modifier[0]);
11249         }
11250
11251         /*
11252          * The stride is either expressed as a multiple of 64 bytes chunks for
11253          * linear buffers or in number of tiles for tiled buffers.
11254          */
11255         if (intel_rotation_90_or_270(rotation)) {
11256                 /* stride = Surface height in tiles */
11257                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11258                 stride = DIV_ROUND_UP(fb->height, tile_height);
11259         } else {
11260                 stride = fb->pitches[0] /
11261                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11262                                                   fb->pixel_format);
11263         }
11264
11265         /*
11266          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11267          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11268          */
11269         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11270         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11271
11272         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11273         POSTING_READ(PLANE_SURF(pipe, 0));
11274 }
11275
11276 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11277                              struct intel_unpin_work *work)
11278 {
11279         struct drm_device *dev = intel_crtc->base.dev;
11280         struct drm_i915_private *dev_priv = dev->dev_private;
11281         struct intel_framebuffer *intel_fb =
11282                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11283         struct drm_i915_gem_object *obj = intel_fb->obj;
11284         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11285         u32 dspcntr;
11286
11287         dspcntr = I915_READ(reg);
11288
11289         if (obj->tiling_mode != I915_TILING_NONE)
11290                 dspcntr |= DISPPLANE_TILED;
11291         else
11292                 dspcntr &= ~DISPPLANE_TILED;
11293
11294         I915_WRITE(reg, dspcntr);
11295
11296         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11297         POSTING_READ(DSPSURF(intel_crtc->plane));
11298 }
11299
11300 /*
11301  * XXX: This is the temporary way to update the plane registers until we get
11302  * around to using the usual plane update functions for MMIO flips
11303  */
11304 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11305 {
11306         struct intel_crtc *crtc = mmio_flip->crtc;
11307         struct intel_unpin_work *work;
11308
11309         spin_lock_irq(&crtc->base.dev->event_lock);
11310         work = crtc->unpin_work;
11311         spin_unlock_irq(&crtc->base.dev->event_lock);
11312         if (work == NULL)
11313                 return;
11314
11315         intel_mark_page_flip_active(work);
11316
11317         intel_pipe_update_start(crtc);
11318
11319         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11320                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11321         else
11322                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11323                 ilk_do_mmio_flip(crtc, work);
11324
11325         intel_pipe_update_end(crtc);
11326 }
11327
11328 static void intel_mmio_flip_work_func(struct work_struct *work)
11329 {
11330         struct intel_mmio_flip *mmio_flip =
11331                 container_of(work, struct intel_mmio_flip, work);
11332         struct intel_framebuffer *intel_fb =
11333                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11334         struct drm_i915_gem_object *obj = intel_fb->obj;
11335
11336         if (mmio_flip->req) {
11337                 WARN_ON(__i915_wait_request(mmio_flip->req,
11338                                             mmio_flip->crtc->reset_counter,
11339                                             false, NULL,
11340                                             &mmio_flip->i915->rps.mmioflips));
11341                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11342         }
11343
11344         /* For framebuffer backed by dmabuf, wait for fence */
11345         if (obj->base.dma_buf)
11346                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11347                                                             false, false,
11348                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11349
11350         intel_do_mmio_flip(mmio_flip);
11351         kfree(mmio_flip);
11352 }
11353
11354 static int intel_queue_mmio_flip(struct drm_device *dev,
11355                                  struct drm_crtc *crtc,
11356                                  struct drm_i915_gem_object *obj)
11357 {
11358         struct intel_mmio_flip *mmio_flip;
11359
11360         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11361         if (mmio_flip == NULL)
11362                 return -ENOMEM;
11363
11364         mmio_flip->i915 = to_i915(dev);
11365         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11366         mmio_flip->crtc = to_intel_crtc(crtc);
11367         mmio_flip->rotation = crtc->primary->state->rotation;
11368
11369         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11370         schedule_work(&mmio_flip->work);
11371
11372         return 0;
11373 }
11374
11375 static int intel_default_queue_flip(struct drm_device *dev,
11376                                     struct drm_crtc *crtc,
11377                                     struct drm_framebuffer *fb,
11378                                     struct drm_i915_gem_object *obj,
11379                                     struct drm_i915_gem_request *req,
11380                                     uint32_t flags)
11381 {
11382         return -ENODEV;
11383 }
11384
11385 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11386                                          struct drm_crtc *crtc)
11387 {
11388         struct drm_i915_private *dev_priv = dev->dev_private;
11389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11390         struct intel_unpin_work *work = intel_crtc->unpin_work;
11391         u32 addr;
11392
11393         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11394                 return true;
11395
11396         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11397                 return false;
11398
11399         if (!work->enable_stall_check)
11400                 return false;
11401
11402         if (work->flip_ready_vblank == 0) {
11403                 if (work->flip_queued_req &&
11404                     !i915_gem_request_completed(work->flip_queued_req, true))
11405                         return false;
11406
11407                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11408         }
11409
11410         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11411                 return false;
11412
11413         /* Potential stall - if we see that the flip has happened,
11414          * assume a missed interrupt. */
11415         if (INTEL_INFO(dev)->gen >= 4)
11416                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11417         else
11418                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11419
11420         /* There is a potential issue here with a false positive after a flip
11421          * to the same address. We could address this by checking for a
11422          * non-incrementing frame counter.
11423          */
11424         return addr == work->gtt_offset;
11425 }
11426
11427 void intel_check_page_flip(struct drm_device *dev, int pipe)
11428 {
11429         struct drm_i915_private *dev_priv = dev->dev_private;
11430         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11432         struct intel_unpin_work *work;
11433
11434         WARN_ON(!in_interrupt());
11435
11436         if (crtc == NULL)
11437                 return;
11438
11439         spin_lock(&dev->event_lock);
11440         work = intel_crtc->unpin_work;
11441         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11442                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11443                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11444                 page_flip_completed(intel_crtc);
11445                 work = NULL;
11446         }
11447         if (work != NULL &&
11448             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11449                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11450         spin_unlock(&dev->event_lock);
11451 }
11452
11453 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11454                                 struct drm_framebuffer *fb,
11455                                 struct drm_pending_vblank_event *event,
11456                                 uint32_t page_flip_flags)
11457 {
11458         struct drm_device *dev = crtc->dev;
11459         struct drm_i915_private *dev_priv = dev->dev_private;
11460         struct drm_framebuffer *old_fb = crtc->primary->fb;
11461         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11463         struct drm_plane *primary = crtc->primary;
11464         enum pipe pipe = intel_crtc->pipe;
11465         struct intel_unpin_work *work;
11466         struct intel_engine_cs *engine;
11467         bool mmio_flip;
11468         struct drm_i915_gem_request *request = NULL;
11469         int ret;
11470
11471         /*
11472          * drm_mode_page_flip_ioctl() should already catch this, but double
11473          * check to be safe.  In the future we may enable pageflipping from
11474          * a disabled primary plane.
11475          */
11476         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11477                 return -EBUSY;
11478
11479         /* Can't change pixel format via MI display flips. */
11480         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11481                 return -EINVAL;
11482
11483         /*
11484          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11485          * Note that pitch changes could also affect these register.
11486          */
11487         if (INTEL_INFO(dev)->gen > 3 &&
11488             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11489              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11490                 return -EINVAL;
11491
11492         if (i915_terminally_wedged(&dev_priv->gpu_error))
11493                 goto out_hang;
11494
11495         work = kzalloc(sizeof(*work), GFP_KERNEL);
11496         if (work == NULL)
11497                 return -ENOMEM;
11498
11499         work->event = event;
11500         work->crtc = crtc;
11501         work->old_fb = old_fb;
11502         INIT_WORK(&work->work, intel_unpin_work_fn);
11503
11504         ret = drm_crtc_vblank_get(crtc);
11505         if (ret)
11506                 goto free_work;
11507
11508         /* We borrow the event spin lock for protecting unpin_work */
11509         spin_lock_irq(&dev->event_lock);
11510         if (intel_crtc->unpin_work) {
11511                 /* Before declaring the flip queue wedged, check if
11512                  * the hardware completed the operation behind our backs.
11513                  */
11514                 if (__intel_pageflip_stall_check(dev, crtc)) {
11515                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11516                         page_flip_completed(intel_crtc);
11517                 } else {
11518                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11519                         spin_unlock_irq(&dev->event_lock);
11520
11521                         drm_crtc_vblank_put(crtc);
11522                         kfree(work);
11523                         return -EBUSY;
11524                 }
11525         }
11526         intel_crtc->unpin_work = work;
11527         spin_unlock_irq(&dev->event_lock);
11528
11529         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11530                 flush_workqueue(dev_priv->wq);
11531
11532         /* Reference the objects for the scheduled work. */
11533         drm_framebuffer_reference(work->old_fb);
11534         drm_gem_object_reference(&obj->base);
11535
11536         crtc->primary->fb = fb;
11537         update_state_fb(crtc->primary);
11538         intel_fbc_pre_update(intel_crtc);
11539
11540         work->pending_flip_obj = obj;
11541
11542         ret = i915_mutex_lock_interruptible(dev);
11543         if (ret)
11544                 goto cleanup;
11545
11546         atomic_inc(&intel_crtc->unpin_work_count);
11547         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11548
11549         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11550                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11551
11552         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11553                 engine = &dev_priv->engine[BCS];
11554                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11555                         /* vlv: DISPLAY_FLIP fails to change tiling */
11556                         engine = NULL;
11557         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11558                 engine = &dev_priv->engine[BCS];
11559         } else if (INTEL_INFO(dev)->gen >= 7) {
11560                 engine = i915_gem_request_get_engine(obj->last_write_req);
11561                 if (engine == NULL || engine->id != RCS)
11562                         engine = &dev_priv->engine[BCS];
11563         } else {
11564                 engine = &dev_priv->engine[RCS];
11565         }
11566
11567         mmio_flip = use_mmio_flip(engine, obj);
11568
11569         /* When using CS flips, we want to emit semaphores between rings.
11570          * However, when using mmio flips we will create a task to do the
11571          * synchronisation, so all we want here is to pin the framebuffer
11572          * into the display plane and skip any waits.
11573          */
11574         if (!mmio_flip) {
11575                 ret = i915_gem_object_sync(obj, engine, &request);
11576                 if (ret)
11577                         goto cleanup_pending;
11578         }
11579
11580         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11581         if (ret)
11582                 goto cleanup_pending;
11583
11584         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11585                                                   obj, 0);
11586         work->gtt_offset += intel_crtc->dspaddr_offset;
11587
11588         if (mmio_flip) {
11589                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11590                 if (ret)
11591                         goto cleanup_unpin;
11592
11593                 i915_gem_request_assign(&work->flip_queued_req,
11594                                         obj->last_write_req);
11595         } else {
11596                 if (!request) {
11597                         request = i915_gem_request_alloc(engine, NULL);
11598                         if (IS_ERR(request)) {
11599                                 ret = PTR_ERR(request);
11600                                 goto cleanup_unpin;
11601                         }
11602                 }
11603
11604                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11605                                                    page_flip_flags);
11606                 if (ret)
11607                         goto cleanup_unpin;
11608
11609                 i915_gem_request_assign(&work->flip_queued_req, request);
11610         }
11611
11612         if (request)
11613                 i915_add_request_no_flush(request);
11614
11615         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11616         work->enable_stall_check = true;
11617
11618         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11619                           to_intel_plane(primary)->frontbuffer_bit);
11620         mutex_unlock(&dev->struct_mutex);
11621
11622         intel_frontbuffer_flip_prepare(dev,
11623                                        to_intel_plane(primary)->frontbuffer_bit);
11624
11625         trace_i915_flip_request(intel_crtc->plane, obj);
11626
11627         return 0;
11628
11629 cleanup_unpin:
11630         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11631 cleanup_pending:
11632         if (!IS_ERR_OR_NULL(request))
11633                 i915_gem_request_cancel(request);
11634         atomic_dec(&intel_crtc->unpin_work_count);
11635         mutex_unlock(&dev->struct_mutex);
11636 cleanup:
11637         crtc->primary->fb = old_fb;
11638         update_state_fb(crtc->primary);
11639
11640         drm_gem_object_unreference_unlocked(&obj->base);
11641         drm_framebuffer_unreference(work->old_fb);
11642
11643         spin_lock_irq(&dev->event_lock);
11644         intel_crtc->unpin_work = NULL;
11645         spin_unlock_irq(&dev->event_lock);
11646
11647         drm_crtc_vblank_put(crtc);
11648 free_work:
11649         kfree(work);
11650
11651         if (ret == -EIO) {
11652                 struct drm_atomic_state *state;
11653                 struct drm_plane_state *plane_state;
11654
11655 out_hang:
11656                 state = drm_atomic_state_alloc(dev);
11657                 if (!state)
11658                         return -ENOMEM;
11659                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11660
11661 retry:
11662                 plane_state = drm_atomic_get_plane_state(state, primary);
11663                 ret = PTR_ERR_OR_ZERO(plane_state);
11664                 if (!ret) {
11665                         drm_atomic_set_fb_for_plane(plane_state, fb);
11666
11667                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11668                         if (!ret)
11669                                 ret = drm_atomic_commit(state);
11670                 }
11671
11672                 if (ret == -EDEADLK) {
11673                         drm_modeset_backoff(state->acquire_ctx);
11674                         drm_atomic_state_clear(state);
11675                         goto retry;
11676                 }
11677
11678                 if (ret)
11679                         drm_atomic_state_free(state);
11680
11681                 if (ret == 0 && event) {
11682                         spin_lock_irq(&dev->event_lock);
11683                         drm_send_vblank_event(dev, pipe, event);
11684                         spin_unlock_irq(&dev->event_lock);
11685                 }
11686         }
11687         return ret;
11688 }
11689
11690
11691 /**
11692  * intel_wm_need_update - Check whether watermarks need updating
11693  * @plane: drm plane
11694  * @state: new plane state
11695  *
11696  * Check current plane state versus the new one to determine whether
11697  * watermarks need to be recalculated.
11698  *
11699  * Returns true or false.
11700  */
11701 static bool intel_wm_need_update(struct drm_plane *plane,
11702                                  struct drm_plane_state *state)
11703 {
11704         struct intel_plane_state *new = to_intel_plane_state(state);
11705         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11706
11707         /* Update watermarks on tiling or size changes. */
11708         if (new->visible != cur->visible)
11709                 return true;
11710
11711         if (!cur->base.fb || !new->base.fb)
11712                 return false;
11713
11714         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11715             cur->base.rotation != new->base.rotation ||
11716             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11717             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11718             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11719             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11720                 return true;
11721
11722         return false;
11723 }
11724
11725 static bool needs_scaling(struct intel_plane_state *state)
11726 {
11727         int src_w = drm_rect_width(&state->src) >> 16;
11728         int src_h = drm_rect_height(&state->src) >> 16;
11729         int dst_w = drm_rect_width(&state->dst);
11730         int dst_h = drm_rect_height(&state->dst);
11731
11732         return (src_w != dst_w || src_h != dst_h);
11733 }
11734
11735 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11736                                     struct drm_plane_state *plane_state)
11737 {
11738         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11739         struct drm_crtc *crtc = crtc_state->crtc;
11740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11741         struct drm_plane *plane = plane_state->plane;
11742         struct drm_device *dev = crtc->dev;
11743         struct drm_i915_private *dev_priv = to_i915(dev);
11744         struct intel_plane_state *old_plane_state =
11745                 to_intel_plane_state(plane->state);
11746         int idx = intel_crtc->base.base.id, ret;
11747         bool mode_changed = needs_modeset(crtc_state);
11748         bool was_crtc_enabled = crtc->state->active;
11749         bool is_crtc_enabled = crtc_state->active;
11750         bool turn_off, turn_on, visible, was_visible;
11751         struct drm_framebuffer *fb = plane_state->fb;
11752
11753         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11754             plane->type != DRM_PLANE_TYPE_CURSOR) {
11755                 ret = skl_update_scaler_plane(
11756                         to_intel_crtc_state(crtc_state),
11757                         to_intel_plane_state(plane_state));
11758                 if (ret)
11759                         return ret;
11760         }
11761
11762         was_visible = old_plane_state->visible;
11763         visible = to_intel_plane_state(plane_state)->visible;
11764
11765         if (!was_crtc_enabled && WARN_ON(was_visible))
11766                 was_visible = false;
11767
11768         /*
11769          * Visibility is calculated as if the crtc was on, but
11770          * after scaler setup everything depends on it being off
11771          * when the crtc isn't active.
11772          */
11773         if (!is_crtc_enabled)
11774                 to_intel_plane_state(plane_state)->visible = visible = false;
11775
11776         if (!was_visible && !visible)
11777                 return 0;
11778
11779         if (fb != old_plane_state->base.fb)
11780                 pipe_config->fb_changed = true;
11781
11782         turn_off = was_visible && (!visible || mode_changed);
11783         turn_on = visible && (!was_visible || mode_changed);
11784
11785         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11786                          plane->base.id, fb ? fb->base.id : -1);
11787
11788         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11789                          plane->base.id, was_visible, visible,
11790                          turn_off, turn_on, mode_changed);
11791
11792         if (turn_on) {
11793                 pipe_config->update_wm_pre = true;
11794
11795                 /* must disable cxsr around plane enable/disable */
11796                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11797                         pipe_config->disable_cxsr = true;
11798         } else if (turn_off) {
11799                 pipe_config->update_wm_post = true;
11800
11801                 /* must disable cxsr around plane enable/disable */
11802                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11803                         pipe_config->disable_cxsr = true;
11804         } else if (intel_wm_need_update(plane, plane_state)) {
11805                 /* FIXME bollocks */
11806                 pipe_config->update_wm_pre = true;
11807                 pipe_config->update_wm_post = true;
11808         }
11809
11810         /* Pre-gen9 platforms need two-step watermark updates */
11811         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11812             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11813                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11814
11815         if (visible || was_visible)
11816                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11817
11818         /*
11819          * WaCxSRDisabledForSpriteScaling:ivb
11820          *
11821          * cstate->update_wm was already set above, so this flag will
11822          * take effect when we commit and program watermarks.
11823          */
11824         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11825             needs_scaling(to_intel_plane_state(plane_state)) &&
11826             !needs_scaling(old_plane_state))
11827                 pipe_config->disable_lp_wm = true;
11828
11829         return 0;
11830 }
11831
11832 static bool encoders_cloneable(const struct intel_encoder *a,
11833                                const struct intel_encoder *b)
11834 {
11835         /* masks could be asymmetric, so check both ways */
11836         return a == b || (a->cloneable & (1 << b->type) &&
11837                           b->cloneable & (1 << a->type));
11838 }
11839
11840 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11841                                          struct intel_crtc *crtc,
11842                                          struct intel_encoder *encoder)
11843 {
11844         struct intel_encoder *source_encoder;
11845         struct drm_connector *connector;
11846         struct drm_connector_state *connector_state;
11847         int i;
11848
11849         for_each_connector_in_state(state, connector, connector_state, i) {
11850                 if (connector_state->crtc != &crtc->base)
11851                         continue;
11852
11853                 source_encoder =
11854                         to_intel_encoder(connector_state->best_encoder);
11855                 if (!encoders_cloneable(encoder, source_encoder))
11856                         return false;
11857         }
11858
11859         return true;
11860 }
11861
11862 static bool check_encoder_cloning(struct drm_atomic_state *state,
11863                                   struct intel_crtc *crtc)
11864 {
11865         struct intel_encoder *encoder;
11866         struct drm_connector *connector;
11867         struct drm_connector_state *connector_state;
11868         int i;
11869
11870         for_each_connector_in_state(state, connector, connector_state, i) {
11871                 if (connector_state->crtc != &crtc->base)
11872                         continue;
11873
11874                 encoder = to_intel_encoder(connector_state->best_encoder);
11875                 if (!check_single_encoder_cloning(state, crtc, encoder))
11876                         return false;
11877         }
11878
11879         return true;
11880 }
11881
11882 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11883                                    struct drm_crtc_state *crtc_state)
11884 {
11885         struct drm_device *dev = crtc->dev;
11886         struct drm_i915_private *dev_priv = dev->dev_private;
11887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11888         struct intel_crtc_state *pipe_config =
11889                 to_intel_crtc_state(crtc_state);
11890         struct drm_atomic_state *state = crtc_state->state;
11891         int ret;
11892         bool mode_changed = needs_modeset(crtc_state);
11893
11894         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11895                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11896                 return -EINVAL;
11897         }
11898
11899         if (mode_changed && !crtc_state->active)
11900                 pipe_config->update_wm_post = true;
11901
11902         if (mode_changed && crtc_state->enable &&
11903             dev_priv->display.crtc_compute_clock &&
11904             !WARN_ON(pipe_config->shared_dpll)) {
11905                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11906                                                            pipe_config);
11907                 if (ret)
11908                         return ret;
11909         }
11910
11911         ret = 0;
11912         if (dev_priv->display.compute_pipe_wm) {
11913                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11914                 if (ret) {
11915                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11916                         return ret;
11917                 }
11918         }
11919
11920         if (dev_priv->display.compute_intermediate_wm &&
11921             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11922                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11923                         return 0;
11924
11925                 /*
11926                  * Calculate 'intermediate' watermarks that satisfy both the
11927                  * old state and the new state.  We can program these
11928                  * immediately.
11929                  */
11930                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11931                                                                 intel_crtc,
11932                                                                 pipe_config);
11933                 if (ret) {
11934                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11935                         return ret;
11936                 }
11937         }
11938
11939         if (INTEL_INFO(dev)->gen >= 9) {
11940                 if (mode_changed)
11941                         ret = skl_update_scaler_crtc(pipe_config);
11942
11943                 if (!ret)
11944                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11945                                                          pipe_config);
11946         }
11947
11948         return ret;
11949 }
11950
11951 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11952         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11953         .load_lut = intel_color_load_luts,
11954         .atomic_begin = intel_begin_crtc_commit,
11955         .atomic_flush = intel_finish_crtc_commit,
11956         .atomic_check = intel_crtc_atomic_check,
11957 };
11958
11959 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11960 {
11961         struct intel_connector *connector;
11962
11963         for_each_intel_connector(dev, connector) {
11964                 if (connector->base.encoder) {
11965                         connector->base.state->best_encoder =
11966                                 connector->base.encoder;
11967                         connector->base.state->crtc =
11968                                 connector->base.encoder->crtc;
11969                 } else {
11970                         connector->base.state->best_encoder = NULL;
11971                         connector->base.state->crtc = NULL;
11972                 }
11973         }
11974 }
11975
11976 static void
11977 connected_sink_compute_bpp(struct intel_connector *connector,
11978                            struct intel_crtc_state *pipe_config)
11979 {
11980         int bpp = pipe_config->pipe_bpp;
11981
11982         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11983                 connector->base.base.id,
11984                 connector->base.name);
11985
11986         /* Don't use an invalid EDID bpc value */
11987         if (connector->base.display_info.bpc &&
11988             connector->base.display_info.bpc * 3 < bpp) {
11989                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11990                               bpp, connector->base.display_info.bpc*3);
11991                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11992         }
11993
11994         /* Clamp bpp to default limit on screens without EDID 1.4 */
11995         if (connector->base.display_info.bpc == 0) {
11996                 int type = connector->base.connector_type;
11997                 int clamp_bpp = 24;
11998
11999                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12000                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12001                     type == DRM_MODE_CONNECTOR_eDP)
12002                         clamp_bpp = 18;
12003
12004                 if (bpp > clamp_bpp) {
12005                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12006                                       bpp, clamp_bpp);
12007                         pipe_config->pipe_bpp = clamp_bpp;
12008                 }
12009         }
12010 }
12011
12012 static int
12013 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12014                           struct intel_crtc_state *pipe_config)
12015 {
12016         struct drm_device *dev = crtc->base.dev;
12017         struct drm_atomic_state *state;
12018         struct drm_connector *connector;
12019         struct drm_connector_state *connector_state;
12020         int bpp, i;
12021
12022         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12023                 bpp = 10*3;
12024         else if (INTEL_INFO(dev)->gen >= 5)
12025                 bpp = 12*3;
12026         else
12027                 bpp = 8*3;
12028
12029
12030         pipe_config->pipe_bpp = bpp;
12031
12032         state = pipe_config->base.state;
12033
12034         /* Clamp display bpp to EDID value */
12035         for_each_connector_in_state(state, connector, connector_state, i) {
12036                 if (connector_state->crtc != &crtc->base)
12037                         continue;
12038
12039                 connected_sink_compute_bpp(to_intel_connector(connector),
12040                                            pipe_config);
12041         }
12042
12043         return bpp;
12044 }
12045
12046 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12047 {
12048         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12049                         "type: 0x%x flags: 0x%x\n",
12050                 mode->crtc_clock,
12051                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12052                 mode->crtc_hsync_end, mode->crtc_htotal,
12053                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12054                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12055 }
12056
12057 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12058                                    struct intel_crtc_state *pipe_config,
12059                                    const char *context)
12060 {
12061         struct drm_device *dev = crtc->base.dev;
12062         struct drm_plane *plane;
12063         struct intel_plane *intel_plane;
12064         struct intel_plane_state *state;
12065         struct drm_framebuffer *fb;
12066
12067         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12068                       context, pipe_config, pipe_name(crtc->pipe));
12069
12070         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12071         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12072                       pipe_config->pipe_bpp, pipe_config->dither);
12073         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12074                       pipe_config->has_pch_encoder,
12075                       pipe_config->fdi_lanes,
12076                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12077                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12078                       pipe_config->fdi_m_n.tu);
12079         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12080                       pipe_config->has_dp_encoder,
12081                       pipe_config->lane_count,
12082                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12083                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12084                       pipe_config->dp_m_n.tu);
12085
12086         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12087                       pipe_config->has_dp_encoder,
12088                       pipe_config->lane_count,
12089                       pipe_config->dp_m2_n2.gmch_m,
12090                       pipe_config->dp_m2_n2.gmch_n,
12091                       pipe_config->dp_m2_n2.link_m,
12092                       pipe_config->dp_m2_n2.link_n,
12093                       pipe_config->dp_m2_n2.tu);
12094
12095         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12096                       pipe_config->has_audio,
12097                       pipe_config->has_infoframe);
12098
12099         DRM_DEBUG_KMS("requested mode:\n");
12100         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12101         DRM_DEBUG_KMS("adjusted mode:\n");
12102         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12103         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12104         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12105         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12106                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12107         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12108                       crtc->num_scalers,
12109                       pipe_config->scaler_state.scaler_users,
12110                       pipe_config->scaler_state.scaler_id);
12111         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12112                       pipe_config->gmch_pfit.control,
12113                       pipe_config->gmch_pfit.pgm_ratios,
12114                       pipe_config->gmch_pfit.lvds_border_bits);
12115         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12116                       pipe_config->pch_pfit.pos,
12117                       pipe_config->pch_pfit.size,
12118                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12119         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12120         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12121
12122         if (IS_BROXTON(dev)) {
12123                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12124                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12125                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12126                               pipe_config->ddi_pll_sel,
12127                               pipe_config->dpll_hw_state.ebb0,
12128                               pipe_config->dpll_hw_state.ebb4,
12129                               pipe_config->dpll_hw_state.pll0,
12130                               pipe_config->dpll_hw_state.pll1,
12131                               pipe_config->dpll_hw_state.pll2,
12132                               pipe_config->dpll_hw_state.pll3,
12133                               pipe_config->dpll_hw_state.pll6,
12134                               pipe_config->dpll_hw_state.pll8,
12135                               pipe_config->dpll_hw_state.pll9,
12136                               pipe_config->dpll_hw_state.pll10,
12137                               pipe_config->dpll_hw_state.pcsdw12);
12138         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12139                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12140                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12141                               pipe_config->ddi_pll_sel,
12142                               pipe_config->dpll_hw_state.ctrl1,
12143                               pipe_config->dpll_hw_state.cfgcr1,
12144                               pipe_config->dpll_hw_state.cfgcr2);
12145         } else if (HAS_DDI(dev)) {
12146                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12147                               pipe_config->ddi_pll_sel,
12148                               pipe_config->dpll_hw_state.wrpll,
12149                               pipe_config->dpll_hw_state.spll);
12150         } else {
12151                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12152                               "fp0: 0x%x, fp1: 0x%x\n",
12153                               pipe_config->dpll_hw_state.dpll,
12154                               pipe_config->dpll_hw_state.dpll_md,
12155                               pipe_config->dpll_hw_state.fp0,
12156                               pipe_config->dpll_hw_state.fp1);
12157         }
12158
12159         DRM_DEBUG_KMS("planes on this crtc\n");
12160         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12161                 intel_plane = to_intel_plane(plane);
12162                 if (intel_plane->pipe != crtc->pipe)
12163                         continue;
12164
12165                 state = to_intel_plane_state(plane->state);
12166                 fb = state->base.fb;
12167                 if (!fb) {
12168                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12169                                 "disabled, scaler_id = %d\n",
12170                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12171                                 plane->base.id, intel_plane->pipe,
12172                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12173                                 drm_plane_index(plane), state->scaler_id);
12174                         continue;
12175                 }
12176
12177                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12178                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12179                         plane->base.id, intel_plane->pipe,
12180                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12181                         drm_plane_index(plane));
12182                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12183                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12184                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12185                         state->scaler_id,
12186                         state->src.x1 >> 16, state->src.y1 >> 16,
12187                         drm_rect_width(&state->src) >> 16,
12188                         drm_rect_height(&state->src) >> 16,
12189                         state->dst.x1, state->dst.y1,
12190                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12191         }
12192 }
12193
12194 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12195 {
12196         struct drm_device *dev = state->dev;
12197         struct drm_connector *connector;
12198         unsigned int used_ports = 0;
12199
12200         /*
12201          * Walk the connector list instead of the encoder
12202          * list to detect the problem on ddi platforms
12203          * where there's just one encoder per digital port.
12204          */
12205         drm_for_each_connector(connector, dev) {
12206                 struct drm_connector_state *connector_state;
12207                 struct intel_encoder *encoder;
12208
12209                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12210                 if (!connector_state)
12211                         connector_state = connector->state;
12212
12213                 if (!connector_state->best_encoder)
12214                         continue;
12215
12216                 encoder = to_intel_encoder(connector_state->best_encoder);
12217
12218                 WARN_ON(!connector_state->crtc);
12219
12220                 switch (encoder->type) {
12221                         unsigned int port_mask;
12222                 case INTEL_OUTPUT_UNKNOWN:
12223                         if (WARN_ON(!HAS_DDI(dev)))
12224                                 break;
12225                 case INTEL_OUTPUT_DISPLAYPORT:
12226                 case INTEL_OUTPUT_HDMI:
12227                 case INTEL_OUTPUT_EDP:
12228                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12229
12230                         /* the same port mustn't appear more than once */
12231                         if (used_ports & port_mask)
12232                                 return false;
12233
12234                         used_ports |= port_mask;
12235                 default:
12236                         break;
12237                 }
12238         }
12239
12240         return true;
12241 }
12242
12243 static void
12244 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12245 {
12246         struct drm_crtc_state tmp_state;
12247         struct intel_crtc_scaler_state scaler_state;
12248         struct intel_dpll_hw_state dpll_hw_state;
12249         struct intel_shared_dpll *shared_dpll;
12250         uint32_t ddi_pll_sel;
12251         bool force_thru;
12252
12253         /* FIXME: before the switch to atomic started, a new pipe_config was
12254          * kzalloc'd. Code that depends on any field being zero should be
12255          * fixed, so that the crtc_state can be safely duplicated. For now,
12256          * only fields that are know to not cause problems are preserved. */
12257
12258         tmp_state = crtc_state->base;
12259         scaler_state = crtc_state->scaler_state;
12260         shared_dpll = crtc_state->shared_dpll;
12261         dpll_hw_state = crtc_state->dpll_hw_state;
12262         ddi_pll_sel = crtc_state->ddi_pll_sel;
12263         force_thru = crtc_state->pch_pfit.force_thru;
12264
12265         memset(crtc_state, 0, sizeof *crtc_state);
12266
12267         crtc_state->base = tmp_state;
12268         crtc_state->scaler_state = scaler_state;
12269         crtc_state->shared_dpll = shared_dpll;
12270         crtc_state->dpll_hw_state = dpll_hw_state;
12271         crtc_state->ddi_pll_sel = ddi_pll_sel;
12272         crtc_state->pch_pfit.force_thru = force_thru;
12273 }
12274
12275 static int
12276 intel_modeset_pipe_config(struct drm_crtc *crtc,
12277                           struct intel_crtc_state *pipe_config)
12278 {
12279         struct drm_atomic_state *state = pipe_config->base.state;
12280         struct intel_encoder *encoder;
12281         struct drm_connector *connector;
12282         struct drm_connector_state *connector_state;
12283         int base_bpp, ret = -EINVAL;
12284         int i;
12285         bool retry = true;
12286
12287         clear_intel_crtc_state(pipe_config);
12288
12289         pipe_config->cpu_transcoder =
12290                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12291
12292         /*
12293          * Sanitize sync polarity flags based on requested ones. If neither
12294          * positive or negative polarity is requested, treat this as meaning
12295          * negative polarity.
12296          */
12297         if (!(pipe_config->base.adjusted_mode.flags &
12298               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12299                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12300
12301         if (!(pipe_config->base.adjusted_mode.flags &
12302               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12303                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12304
12305         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12306                                              pipe_config);
12307         if (base_bpp < 0)
12308                 goto fail;
12309
12310         /*
12311          * Determine the real pipe dimensions. Note that stereo modes can
12312          * increase the actual pipe size due to the frame doubling and
12313          * insertion of additional space for blanks between the frame. This
12314          * is stored in the crtc timings. We use the requested mode to do this
12315          * computation to clearly distinguish it from the adjusted mode, which
12316          * can be changed by the connectors in the below retry loop.
12317          */
12318         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12319                                &pipe_config->pipe_src_w,
12320                                &pipe_config->pipe_src_h);
12321
12322 encoder_retry:
12323         /* Ensure the port clock defaults are reset when retrying. */
12324         pipe_config->port_clock = 0;
12325         pipe_config->pixel_multiplier = 1;
12326
12327         /* Fill in default crtc timings, allow encoders to overwrite them. */
12328         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12329                               CRTC_STEREO_DOUBLE);
12330
12331         /* Pass our mode to the connectors and the CRTC to give them a chance to
12332          * adjust it according to limitations or connector properties, and also
12333          * a chance to reject the mode entirely.
12334          */
12335         for_each_connector_in_state(state, connector, connector_state, i) {
12336                 if (connector_state->crtc != crtc)
12337                         continue;
12338
12339                 encoder = to_intel_encoder(connector_state->best_encoder);
12340
12341                 if (!(encoder->compute_config(encoder, pipe_config))) {
12342                         DRM_DEBUG_KMS("Encoder config failure\n");
12343                         goto fail;
12344                 }
12345         }
12346
12347         /* Set default port clock if not overwritten by the encoder. Needs to be
12348          * done afterwards in case the encoder adjusts the mode. */
12349         if (!pipe_config->port_clock)
12350                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12351                         * pipe_config->pixel_multiplier;
12352
12353         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12354         if (ret < 0) {
12355                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12356                 goto fail;
12357         }
12358
12359         if (ret == RETRY) {
12360                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12361                         ret = -EINVAL;
12362                         goto fail;
12363                 }
12364
12365                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12366                 retry = false;
12367                 goto encoder_retry;
12368         }
12369
12370         /* Dithering seems to not pass-through bits correctly when it should, so
12371          * only enable it on 6bpc panels. */
12372         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12373         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12374                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12375
12376 fail:
12377         return ret;
12378 }
12379
12380 static void
12381 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12382 {
12383         struct drm_crtc *crtc;
12384         struct drm_crtc_state *crtc_state;
12385         int i;
12386
12387         /* Double check state. */
12388         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12389                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12390
12391                 /* Update hwmode for vblank functions */
12392                 if (crtc->state->active)
12393                         crtc->hwmode = crtc->state->adjusted_mode;
12394                 else
12395                         crtc->hwmode.crtc_clock = 0;
12396
12397                 /*
12398                  * Update legacy state to satisfy fbc code. This can
12399                  * be removed when fbc uses the atomic state.
12400                  */
12401                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12402                         struct drm_plane_state *plane_state = crtc->primary->state;
12403
12404                         crtc->primary->fb = plane_state->fb;
12405                         crtc->x = plane_state->src_x >> 16;
12406                         crtc->y = plane_state->src_y >> 16;
12407                 }
12408         }
12409 }
12410
12411 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12412 {
12413         int diff;
12414
12415         if (clock1 == clock2)
12416                 return true;
12417
12418         if (!clock1 || !clock2)
12419                 return false;
12420
12421         diff = abs(clock1 - clock2);
12422
12423         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12424                 return true;
12425
12426         return false;
12427 }
12428
12429 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12430         list_for_each_entry((intel_crtc), \
12431                             &(dev)->mode_config.crtc_list, \
12432                             base.head) \
12433                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12434
12435 static bool
12436 intel_compare_m_n(unsigned int m, unsigned int n,
12437                   unsigned int m2, unsigned int n2,
12438                   bool exact)
12439 {
12440         if (m == m2 && n == n2)
12441                 return true;
12442
12443         if (exact || !m || !n || !m2 || !n2)
12444                 return false;
12445
12446         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12447
12448         if (n > n2) {
12449                 while (n > n2) {
12450                         m2 <<= 1;
12451                         n2 <<= 1;
12452                 }
12453         } else if (n < n2) {
12454                 while (n < n2) {
12455                         m <<= 1;
12456                         n <<= 1;
12457                 }
12458         }
12459
12460         if (n != n2)
12461                 return false;
12462
12463         return intel_fuzzy_clock_check(m, m2);
12464 }
12465
12466 static bool
12467 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12468                        struct intel_link_m_n *m2_n2,
12469                        bool adjust)
12470 {
12471         if (m_n->tu == m2_n2->tu &&
12472             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12473                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12474             intel_compare_m_n(m_n->link_m, m_n->link_n,
12475                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12476                 if (adjust)
12477                         *m2_n2 = *m_n;
12478
12479                 return true;
12480         }
12481
12482         return false;
12483 }
12484
12485 static bool
12486 intel_pipe_config_compare(struct drm_device *dev,
12487                           struct intel_crtc_state *current_config,
12488                           struct intel_crtc_state *pipe_config,
12489                           bool adjust)
12490 {
12491         bool ret = true;
12492
12493 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12494         do { \
12495                 if (!adjust) \
12496                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12497                 else \
12498                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12499         } while (0)
12500
12501 #define PIPE_CONF_CHECK_X(name) \
12502         if (current_config->name != pipe_config->name) { \
12503                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12504                           "(expected 0x%08x, found 0x%08x)\n", \
12505                           current_config->name, \
12506                           pipe_config->name); \
12507                 ret = false; \
12508         }
12509
12510 #define PIPE_CONF_CHECK_I(name) \
12511         if (current_config->name != pipe_config->name) { \
12512                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12513                           "(expected %i, found %i)\n", \
12514                           current_config->name, \
12515                           pipe_config->name); \
12516                 ret = false; \
12517         }
12518
12519 #define PIPE_CONF_CHECK_P(name) \
12520         if (current_config->name != pipe_config->name) { \
12521                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12522                           "(expected %p, found %p)\n", \
12523                           current_config->name, \
12524                           pipe_config->name); \
12525                 ret = false; \
12526         }
12527
12528 #define PIPE_CONF_CHECK_M_N(name) \
12529         if (!intel_compare_link_m_n(&current_config->name, \
12530                                     &pipe_config->name,\
12531                                     adjust)) { \
12532                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12533                           "(expected tu %i gmch %i/%i link %i/%i, " \
12534                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12535                           current_config->name.tu, \
12536                           current_config->name.gmch_m, \
12537                           current_config->name.gmch_n, \
12538                           current_config->name.link_m, \
12539                           current_config->name.link_n, \
12540                           pipe_config->name.tu, \
12541                           pipe_config->name.gmch_m, \
12542                           pipe_config->name.gmch_n, \
12543                           pipe_config->name.link_m, \
12544                           pipe_config->name.link_n); \
12545                 ret = false; \
12546         }
12547
12548 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12549         if (!intel_compare_link_m_n(&current_config->name, \
12550                                     &pipe_config->name, adjust) && \
12551             !intel_compare_link_m_n(&current_config->alt_name, \
12552                                     &pipe_config->name, adjust)) { \
12553                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12554                           "(expected tu %i gmch %i/%i link %i/%i, " \
12555                           "or tu %i gmch %i/%i link %i/%i, " \
12556                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12557                           current_config->name.tu, \
12558                           current_config->name.gmch_m, \
12559                           current_config->name.gmch_n, \
12560                           current_config->name.link_m, \
12561                           current_config->name.link_n, \
12562                           current_config->alt_name.tu, \
12563                           current_config->alt_name.gmch_m, \
12564                           current_config->alt_name.gmch_n, \
12565                           current_config->alt_name.link_m, \
12566                           current_config->alt_name.link_n, \
12567                           pipe_config->name.tu, \
12568                           pipe_config->name.gmch_m, \
12569                           pipe_config->name.gmch_n, \
12570                           pipe_config->name.link_m, \
12571                           pipe_config->name.link_n); \
12572                 ret = false; \
12573         }
12574
12575 /* This is required for BDW+ where there is only one set of registers for
12576  * switching between high and low RR.
12577  * This macro can be used whenever a comparison has to be made between one
12578  * hw state and multiple sw state variables.
12579  */
12580 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12581         if ((current_config->name != pipe_config->name) && \
12582                 (current_config->alt_name != pipe_config->name)) { \
12583                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12584                                   "(expected %i or %i, found %i)\n", \
12585                                   current_config->name, \
12586                                   current_config->alt_name, \
12587                                   pipe_config->name); \
12588                         ret = false; \
12589         }
12590
12591 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12592         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12593                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12594                           "(expected %i, found %i)\n", \
12595                           current_config->name & (mask), \
12596                           pipe_config->name & (mask)); \
12597                 ret = false; \
12598         }
12599
12600 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12601         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12602                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12603                           "(expected %i, found %i)\n", \
12604                           current_config->name, \
12605                           pipe_config->name); \
12606                 ret = false; \
12607         }
12608
12609 #define PIPE_CONF_QUIRK(quirk)  \
12610         ((current_config->quirks | pipe_config->quirks) & (quirk))
12611
12612         PIPE_CONF_CHECK_I(cpu_transcoder);
12613
12614         PIPE_CONF_CHECK_I(has_pch_encoder);
12615         PIPE_CONF_CHECK_I(fdi_lanes);
12616         PIPE_CONF_CHECK_M_N(fdi_m_n);
12617
12618         PIPE_CONF_CHECK_I(has_dp_encoder);
12619         PIPE_CONF_CHECK_I(lane_count);
12620
12621         if (INTEL_INFO(dev)->gen < 8) {
12622                 PIPE_CONF_CHECK_M_N(dp_m_n);
12623
12624                 if (current_config->has_drrs)
12625                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12626         } else
12627                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12628
12629         PIPE_CONF_CHECK_I(has_dsi_encoder);
12630
12631         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12632         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12633         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12634         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12635         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12636         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12637
12638         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12639         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12640         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12641         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12642         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12643         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12644
12645         PIPE_CONF_CHECK_I(pixel_multiplier);
12646         PIPE_CONF_CHECK_I(has_hdmi_sink);
12647         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12648             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12649                 PIPE_CONF_CHECK_I(limited_color_range);
12650         PIPE_CONF_CHECK_I(has_infoframe);
12651
12652         PIPE_CONF_CHECK_I(has_audio);
12653
12654         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12655                               DRM_MODE_FLAG_INTERLACE);
12656
12657         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12658                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12659                                       DRM_MODE_FLAG_PHSYNC);
12660                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12661                                       DRM_MODE_FLAG_NHSYNC);
12662                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12663                                       DRM_MODE_FLAG_PVSYNC);
12664                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12665                                       DRM_MODE_FLAG_NVSYNC);
12666         }
12667
12668         PIPE_CONF_CHECK_X(gmch_pfit.control);
12669         /* pfit ratios are autocomputed by the hw on gen4+ */
12670         if (INTEL_INFO(dev)->gen < 4)
12671                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12672         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12673
12674         if (!adjust) {
12675                 PIPE_CONF_CHECK_I(pipe_src_w);
12676                 PIPE_CONF_CHECK_I(pipe_src_h);
12677
12678                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12679                 if (current_config->pch_pfit.enabled) {
12680                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12681                         PIPE_CONF_CHECK_X(pch_pfit.size);
12682                 }
12683
12684                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12685         }
12686
12687         /* BDW+ don't expose a synchronous way to read the state */
12688         if (IS_HASWELL(dev))
12689                 PIPE_CONF_CHECK_I(ips_enabled);
12690
12691         PIPE_CONF_CHECK_I(double_wide);
12692
12693         PIPE_CONF_CHECK_X(ddi_pll_sel);
12694
12695         PIPE_CONF_CHECK_P(shared_dpll);
12696         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12697         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12698         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12699         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12700         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12701         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12702         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12703         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12704         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12705
12706         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12707                 PIPE_CONF_CHECK_I(pipe_bpp);
12708
12709         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12710         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12711
12712 #undef PIPE_CONF_CHECK_X
12713 #undef PIPE_CONF_CHECK_I
12714 #undef PIPE_CONF_CHECK_P
12715 #undef PIPE_CONF_CHECK_I_ALT
12716 #undef PIPE_CONF_CHECK_FLAGS
12717 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12718 #undef PIPE_CONF_QUIRK
12719 #undef INTEL_ERR_OR_DBG_KMS
12720
12721         return ret;
12722 }
12723
12724 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12725                                            const struct intel_crtc_state *pipe_config)
12726 {
12727         if (pipe_config->has_pch_encoder) {
12728                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12729                                                             &pipe_config->fdi_m_n);
12730                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12731
12732                 /*
12733                  * FDI already provided one idea for the dotclock.
12734                  * Yell if the encoder disagrees.
12735                  */
12736                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12737                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12738                      fdi_dotclock, dotclock);
12739         }
12740 }
12741
12742 static void check_wm_state(struct drm_device *dev)
12743 {
12744         struct drm_i915_private *dev_priv = dev->dev_private;
12745         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12746         struct intel_crtc *intel_crtc;
12747         int plane;
12748
12749         if (INTEL_INFO(dev)->gen < 9)
12750                 return;
12751
12752         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12753         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12754
12755         for_each_intel_crtc(dev, intel_crtc) {
12756                 struct skl_ddb_entry *hw_entry, *sw_entry;
12757                 const enum pipe pipe = intel_crtc->pipe;
12758
12759                 if (!intel_crtc->active)
12760                         continue;
12761
12762                 /* planes */
12763                 for_each_plane(dev_priv, pipe, plane) {
12764                         hw_entry = &hw_ddb.plane[pipe][plane];
12765                         sw_entry = &sw_ddb->plane[pipe][plane];
12766
12767                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12768                                 continue;
12769
12770                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12771                                   "(expected (%u,%u), found (%u,%u))\n",
12772                                   pipe_name(pipe), plane + 1,
12773                                   sw_entry->start, sw_entry->end,
12774                                   hw_entry->start, hw_entry->end);
12775                 }
12776
12777                 /* cursor */
12778                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12779                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12780
12781                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12782                         continue;
12783
12784                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12785                           "(expected (%u,%u), found (%u,%u))\n",
12786                           pipe_name(pipe),
12787                           sw_entry->start, sw_entry->end,
12788                           hw_entry->start, hw_entry->end);
12789         }
12790 }
12791
12792 static void
12793 check_connector_state(struct drm_device *dev,
12794                       struct drm_atomic_state *old_state)
12795 {
12796         struct drm_connector_state *old_conn_state;
12797         struct drm_connector *connector;
12798         int i;
12799
12800         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12801                 struct drm_encoder *encoder = connector->encoder;
12802                 struct drm_connector_state *state = connector->state;
12803
12804                 /* This also checks the encoder/connector hw state with the
12805                  * ->get_hw_state callbacks. */
12806                 intel_connector_check_state(to_intel_connector(connector));
12807
12808                 I915_STATE_WARN(state->best_encoder != encoder,
12809                      "connector's atomic encoder doesn't match legacy encoder\n");
12810         }
12811 }
12812
12813 static void
12814 check_encoder_state(struct drm_device *dev)
12815 {
12816         struct intel_encoder *encoder;
12817         struct intel_connector *connector;
12818
12819         for_each_intel_encoder(dev, encoder) {
12820                 bool enabled = false;
12821                 enum pipe pipe;
12822
12823                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12824                               encoder->base.base.id,
12825                               encoder->base.name);
12826
12827                 for_each_intel_connector(dev, connector) {
12828                         if (connector->base.state->best_encoder != &encoder->base)
12829                                 continue;
12830                         enabled = true;
12831
12832                         I915_STATE_WARN(connector->base.state->crtc !=
12833                                         encoder->base.crtc,
12834                              "connector's crtc doesn't match encoder crtc\n");
12835                 }
12836
12837                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12838                      "encoder's enabled state mismatch "
12839                      "(expected %i, found %i)\n",
12840                      !!encoder->base.crtc, enabled);
12841
12842                 if (!encoder->base.crtc) {
12843                         bool active;
12844
12845                         active = encoder->get_hw_state(encoder, &pipe);
12846                         I915_STATE_WARN(active,
12847                              "encoder detached but still enabled on pipe %c.\n",
12848                              pipe_name(pipe));
12849                 }
12850         }
12851 }
12852
12853 static void
12854 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12855 {
12856         struct drm_i915_private *dev_priv = dev->dev_private;
12857         struct intel_encoder *encoder;
12858         struct drm_crtc_state *old_crtc_state;
12859         struct drm_crtc *crtc;
12860         int i;
12861
12862         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12863                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12864                 struct intel_crtc_state *pipe_config, *sw_config;
12865                 bool active;
12866
12867                 if (!needs_modeset(crtc->state) &&
12868                     !to_intel_crtc_state(crtc->state)->update_pipe)
12869                         continue;
12870
12871                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12872                 pipe_config = to_intel_crtc_state(old_crtc_state);
12873                 memset(pipe_config, 0, sizeof(*pipe_config));
12874                 pipe_config->base.crtc = crtc;
12875                 pipe_config->base.state = old_state;
12876
12877                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12878                               crtc->base.id);
12879
12880                 active = dev_priv->display.get_pipe_config(intel_crtc,
12881                                                            pipe_config);
12882
12883                 /* hw state is inconsistent with the pipe quirk */
12884                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12885                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12886                         active = crtc->state->active;
12887
12888                 I915_STATE_WARN(crtc->state->active != active,
12889                      "crtc active state doesn't match with hw state "
12890                      "(expected %i, found %i)\n", crtc->state->active, active);
12891
12892                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12893                      "transitional active state does not match atomic hw state "
12894                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12895
12896                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12897                         enum pipe pipe;
12898
12899                         active = encoder->get_hw_state(encoder, &pipe);
12900                         I915_STATE_WARN(active != crtc->state->active,
12901                                 "[ENCODER:%i] active %i with crtc active %i\n",
12902                                 encoder->base.base.id, active, crtc->state->active);
12903
12904                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12905                                         "Encoder connected to wrong pipe %c\n",
12906                                         pipe_name(pipe));
12907
12908                         if (active)
12909                                 encoder->get_config(encoder, pipe_config);
12910                 }
12911
12912                 if (!crtc->state->active)
12913                         continue;
12914
12915                 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12916
12917                 sw_config = to_intel_crtc_state(crtc->state);
12918                 if (!intel_pipe_config_compare(dev, sw_config,
12919                                                pipe_config, false)) {
12920                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12921                         intel_dump_pipe_config(intel_crtc, pipe_config,
12922                                                "[hw state]");
12923                         intel_dump_pipe_config(intel_crtc, sw_config,
12924                                                "[sw state]");
12925                 }
12926         }
12927 }
12928
12929 static void
12930 check_shared_dpll_state(struct drm_device *dev)
12931 {
12932         struct drm_i915_private *dev_priv = dev->dev_private;
12933         struct intel_crtc *crtc;
12934         struct intel_dpll_hw_state dpll_hw_state;
12935         int i;
12936
12937         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12938                 struct intel_shared_dpll *pll =
12939                         intel_get_shared_dpll_by_id(dev_priv, i);
12940                 unsigned enabled_crtcs = 0, active_crtcs = 0;
12941                 bool active;
12942
12943                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12944
12945                 DRM_DEBUG_KMS("%s\n", pll->name);
12946
12947                 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12948
12949                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12950                      "more active pll users than references: %x vs %x\n",
12951                      pll->active_mask, pll->config.crtc_mask);
12952
12953                 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12954                         I915_STATE_WARN(!pll->on && pll->active_mask,
12955                              "pll in active use but not on in sw tracking\n");
12956                         I915_STATE_WARN(pll->on && !pll->active_mask,
12957                              "pll is on but not used by any active crtc\n");
12958                         I915_STATE_WARN(pll->on != active,
12959                              "pll on state mismatch (expected %i, found %i)\n",
12960                              pll->on, active);
12961                 }
12962
12963                 for_each_intel_crtc(dev, crtc) {
12964                         if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12965                                 enabled_crtcs |= 1 << drm_crtc_index(&crtc->base);
12966                         if (crtc->base.state->active && crtc->config->shared_dpll == pll)
12967                                 active_crtcs |= 1 << drm_crtc_index(&crtc->base);
12968                 }
12969
12970                 I915_STATE_WARN(pll->active_mask != active_crtcs,
12971                      "pll active crtcs mismatch (expected %x, found %x)\n",
12972                      pll->active_mask, active_crtcs);
12973                 I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs,
12974                      "pll enabled crtcs mismatch (expected %x, found %x)\n",
12975                      pll->config.crtc_mask, enabled_crtcs);
12976
12977                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12978                                        sizeof(dpll_hw_state)),
12979                      "pll hw state mismatch\n");
12980         }
12981 }
12982
12983 static void
12984 intel_modeset_check_state(struct drm_device *dev,
12985                           struct drm_atomic_state *old_state)
12986 {
12987         check_wm_state(dev);
12988         check_connector_state(dev, old_state);
12989         check_encoder_state(dev);
12990         check_crtc_state(dev, old_state);
12991         check_shared_dpll_state(dev);
12992 }
12993
12994 static void update_scanline_offset(struct intel_crtc *crtc)
12995 {
12996         struct drm_device *dev = crtc->base.dev;
12997
12998         /*
12999          * The scanline counter increments at the leading edge of hsync.
13000          *
13001          * On most platforms it starts counting from vtotal-1 on the
13002          * first active line. That means the scanline counter value is
13003          * always one less than what we would expect. Ie. just after
13004          * start of vblank, which also occurs at start of hsync (on the
13005          * last active line), the scanline counter will read vblank_start-1.
13006          *
13007          * On gen2 the scanline counter starts counting from 1 instead
13008          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13009          * to keep the value positive), instead of adding one.
13010          *
13011          * On HSW+ the behaviour of the scanline counter depends on the output
13012          * type. For DP ports it behaves like most other platforms, but on HDMI
13013          * there's an extra 1 line difference. So we need to add two instead of
13014          * one to the value.
13015          */
13016         if (IS_GEN2(dev)) {
13017                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13018                 int vtotal;
13019
13020                 vtotal = adjusted_mode->crtc_vtotal;
13021                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13022                         vtotal /= 2;
13023
13024                 crtc->scanline_offset = vtotal - 1;
13025         } else if (HAS_DDI(dev) &&
13026                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13027                 crtc->scanline_offset = 2;
13028         } else
13029                 crtc->scanline_offset = 1;
13030 }
13031
13032 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13033 {
13034         struct drm_device *dev = state->dev;
13035         struct drm_i915_private *dev_priv = to_i915(dev);
13036         struct intel_shared_dpll_config *shared_dpll = NULL;
13037         struct drm_crtc *crtc;
13038         struct drm_crtc_state *crtc_state;
13039         int i;
13040
13041         if (!dev_priv->display.crtc_compute_clock)
13042                 return;
13043
13044         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13045                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13046                 struct intel_shared_dpll *old_dpll =
13047                         to_intel_crtc_state(crtc->state)->shared_dpll;
13048
13049                 if (!needs_modeset(crtc_state))
13050                         continue;
13051
13052                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13053
13054                 if (!old_dpll)
13055                         continue;
13056
13057                 if (!shared_dpll)
13058                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13059
13060                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13061         }
13062 }
13063
13064 /*
13065  * This implements the workaround described in the "notes" section of the mode
13066  * set sequence documentation. When going from no pipes or single pipe to
13067  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13068  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13069  */
13070 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13071 {
13072         struct drm_crtc_state *crtc_state;
13073         struct intel_crtc *intel_crtc;
13074         struct drm_crtc *crtc;
13075         struct intel_crtc_state *first_crtc_state = NULL;
13076         struct intel_crtc_state *other_crtc_state = NULL;
13077         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13078         int i;
13079
13080         /* look at all crtc's that are going to be enabled in during modeset */
13081         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13082                 intel_crtc = to_intel_crtc(crtc);
13083
13084                 if (!crtc_state->active || !needs_modeset(crtc_state))
13085                         continue;
13086
13087                 if (first_crtc_state) {
13088                         other_crtc_state = to_intel_crtc_state(crtc_state);
13089                         break;
13090                 } else {
13091                         first_crtc_state = to_intel_crtc_state(crtc_state);
13092                         first_pipe = intel_crtc->pipe;
13093                 }
13094         }
13095
13096         /* No workaround needed? */
13097         if (!first_crtc_state)
13098                 return 0;
13099
13100         /* w/a possibly needed, check how many crtc's are already enabled. */
13101         for_each_intel_crtc(state->dev, intel_crtc) {
13102                 struct intel_crtc_state *pipe_config;
13103
13104                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13105                 if (IS_ERR(pipe_config))
13106                         return PTR_ERR(pipe_config);
13107
13108                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13109
13110                 if (!pipe_config->base.active ||
13111                     needs_modeset(&pipe_config->base))
13112                         continue;
13113
13114                 /* 2 or more enabled crtcs means no need for w/a */
13115                 if (enabled_pipe != INVALID_PIPE)
13116                         return 0;
13117
13118                 enabled_pipe = intel_crtc->pipe;
13119         }
13120
13121         if (enabled_pipe != INVALID_PIPE)
13122                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13123         else if (other_crtc_state)
13124                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13125
13126         return 0;
13127 }
13128
13129 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13130 {
13131         struct drm_crtc *crtc;
13132         struct drm_crtc_state *crtc_state;
13133         int ret = 0;
13134
13135         /* add all active pipes to the state */
13136         for_each_crtc(state->dev, crtc) {
13137                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13138                 if (IS_ERR(crtc_state))
13139                         return PTR_ERR(crtc_state);
13140
13141                 if (!crtc_state->active || needs_modeset(crtc_state))
13142                         continue;
13143
13144                 crtc_state->mode_changed = true;
13145
13146                 ret = drm_atomic_add_affected_connectors(state, crtc);
13147                 if (ret)
13148                         break;
13149
13150                 ret = drm_atomic_add_affected_planes(state, crtc);
13151                 if (ret)
13152                         break;
13153         }
13154
13155         return ret;
13156 }
13157
13158 static int intel_modeset_checks(struct drm_atomic_state *state)
13159 {
13160         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13161         struct drm_i915_private *dev_priv = state->dev->dev_private;
13162         struct drm_crtc *crtc;
13163         struct drm_crtc_state *crtc_state;
13164         int ret = 0, i;
13165
13166         if (!check_digital_port_conflicts(state)) {
13167                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13168                 return -EINVAL;
13169         }
13170
13171         intel_state->modeset = true;
13172         intel_state->active_crtcs = dev_priv->active_crtcs;
13173
13174         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13175                 if (crtc_state->active)
13176                         intel_state->active_crtcs |= 1 << i;
13177                 else
13178                         intel_state->active_crtcs &= ~(1 << i);
13179         }
13180
13181         /*
13182          * See if the config requires any additional preparation, e.g.
13183          * to adjust global state with pipes off.  We need to do this
13184          * here so we can get the modeset_pipe updated config for the new
13185          * mode set on this crtc.  For other crtcs we need to use the
13186          * adjusted_mode bits in the crtc directly.
13187          */
13188         if (dev_priv->display.modeset_calc_cdclk) {
13189                 ret = dev_priv->display.modeset_calc_cdclk(state);
13190
13191                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13192                         ret = intel_modeset_all_pipes(state);
13193
13194                 if (ret < 0)
13195                         return ret;
13196
13197                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13198                               intel_state->cdclk, intel_state->dev_cdclk);
13199         } else
13200                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13201
13202         intel_modeset_clear_plls(state);
13203
13204         if (IS_HASWELL(dev_priv))
13205                 return haswell_mode_set_planes_workaround(state);
13206
13207         return 0;
13208 }
13209
13210 /*
13211  * Handle calculation of various watermark data at the end of the atomic check
13212  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13213  * handlers to ensure that all derived state has been updated.
13214  */
13215 static void calc_watermark_data(struct drm_atomic_state *state)
13216 {
13217         struct drm_device *dev = state->dev;
13218         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13219         struct drm_crtc *crtc;
13220         struct drm_crtc_state *cstate;
13221         struct drm_plane *plane;
13222         struct drm_plane_state *pstate;
13223
13224         /*
13225          * Calculate watermark configuration details now that derived
13226          * plane/crtc state is all properly updated.
13227          */
13228         drm_for_each_crtc(crtc, dev) {
13229                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13230                         crtc->state;
13231
13232                 if (cstate->active)
13233                         intel_state->wm_config.num_pipes_active++;
13234         }
13235         drm_for_each_legacy_plane(plane, dev) {
13236                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13237                         plane->state;
13238
13239                 if (!to_intel_plane_state(pstate)->visible)
13240                         continue;
13241
13242                 intel_state->wm_config.sprites_enabled = true;
13243                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13244                     pstate->crtc_h != pstate->src_h >> 16)
13245                         intel_state->wm_config.sprites_scaled = true;
13246         }
13247 }
13248
13249 /**
13250  * intel_atomic_check - validate state object
13251  * @dev: drm device
13252  * @state: state to validate
13253  */
13254 static int intel_atomic_check(struct drm_device *dev,
13255                               struct drm_atomic_state *state)
13256 {
13257         struct drm_i915_private *dev_priv = to_i915(dev);
13258         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13259         struct drm_crtc *crtc;
13260         struct drm_crtc_state *crtc_state;
13261         int ret, i;
13262         bool any_ms = false;
13263
13264         ret = drm_atomic_helper_check_modeset(dev, state);
13265         if (ret)
13266                 return ret;
13267
13268         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13269                 struct intel_crtc_state *pipe_config =
13270                         to_intel_crtc_state(crtc_state);
13271
13272                 /* Catch I915_MODE_FLAG_INHERITED */
13273                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13274                         crtc_state->mode_changed = true;
13275
13276                 if (!crtc_state->enable) {
13277                         if (needs_modeset(crtc_state))
13278                                 any_ms = true;
13279                         continue;
13280                 }
13281
13282                 if (!needs_modeset(crtc_state))
13283                         continue;
13284
13285                 /* FIXME: For only active_changed we shouldn't need to do any
13286                  * state recomputation at all. */
13287
13288                 ret = drm_atomic_add_affected_connectors(state, crtc);
13289                 if (ret)
13290                         return ret;
13291
13292                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13293                 if (ret)
13294                         return ret;
13295
13296                 if (i915.fastboot &&
13297                     intel_pipe_config_compare(dev,
13298                                         to_intel_crtc_state(crtc->state),
13299                                         pipe_config, true)) {
13300                         crtc_state->mode_changed = false;
13301                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13302                 }
13303
13304                 if (needs_modeset(crtc_state)) {
13305                         any_ms = true;
13306
13307                         ret = drm_atomic_add_affected_planes(state, crtc);
13308                         if (ret)
13309                                 return ret;
13310                 }
13311
13312                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13313                                        needs_modeset(crtc_state) ?
13314                                        "[modeset]" : "[fastset]");
13315         }
13316
13317         if (any_ms) {
13318                 ret = intel_modeset_checks(state);
13319
13320                 if (ret)
13321                         return ret;
13322         } else
13323                 intel_state->cdclk = dev_priv->cdclk_freq;
13324
13325         ret = drm_atomic_helper_check_planes(dev, state);
13326         if (ret)
13327                 return ret;
13328
13329         intel_fbc_choose_crtc(dev_priv, state);
13330         calc_watermark_data(state);
13331
13332         return 0;
13333 }
13334
13335 static int intel_atomic_prepare_commit(struct drm_device *dev,
13336                                        struct drm_atomic_state *state,
13337                                        bool async)
13338 {
13339         struct drm_i915_private *dev_priv = dev->dev_private;
13340         struct drm_plane_state *plane_state;
13341         struct drm_crtc_state *crtc_state;
13342         struct drm_plane *plane;
13343         struct drm_crtc *crtc;
13344         int i, ret;
13345
13346         if (async) {
13347                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13348                 return -EINVAL;
13349         }
13350
13351         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13352                 ret = intel_crtc_wait_for_pending_flips(crtc);
13353                 if (ret)
13354                         return ret;
13355
13356                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13357                         flush_workqueue(dev_priv->wq);
13358         }
13359
13360         ret = mutex_lock_interruptible(&dev->struct_mutex);
13361         if (ret)
13362                 return ret;
13363
13364         ret = drm_atomic_helper_prepare_planes(dev, state);
13365         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13366                 u32 reset_counter;
13367
13368                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13369                 mutex_unlock(&dev->struct_mutex);
13370
13371                 for_each_plane_in_state(state, plane, plane_state, i) {
13372                         struct intel_plane_state *intel_plane_state =
13373                                 to_intel_plane_state(plane_state);
13374
13375                         if (!intel_plane_state->wait_req)
13376                                 continue;
13377
13378                         ret = __i915_wait_request(intel_plane_state->wait_req,
13379                                                   reset_counter, true,
13380                                                   NULL, NULL);
13381
13382                         /* Swallow -EIO errors to allow updates during hw lockup. */
13383                         if (ret == -EIO)
13384                                 ret = 0;
13385
13386                         if (ret)
13387                                 break;
13388                 }
13389
13390                 if (!ret)
13391                         return 0;
13392
13393                 mutex_lock(&dev->struct_mutex);
13394                 drm_atomic_helper_cleanup_planes(dev, state);
13395         }
13396
13397         mutex_unlock(&dev->struct_mutex);
13398         return ret;
13399 }
13400
13401 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13402                                           struct drm_i915_private *dev_priv,
13403                                           unsigned crtc_mask)
13404 {
13405         unsigned last_vblank_count[I915_MAX_PIPES];
13406         enum pipe pipe;
13407         int ret;
13408
13409         if (!crtc_mask)
13410                 return;
13411
13412         for_each_pipe(dev_priv, pipe) {
13413                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13414
13415                 if (!((1 << pipe) & crtc_mask))
13416                         continue;
13417
13418                 ret = drm_crtc_vblank_get(crtc);
13419                 if (WARN_ON(ret != 0)) {
13420                         crtc_mask &= ~(1 << pipe);
13421                         continue;
13422                 }
13423
13424                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13425         }
13426
13427         for_each_pipe(dev_priv, pipe) {
13428                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13429                 long lret;
13430
13431                 if (!((1 << pipe) & crtc_mask))
13432                         continue;
13433
13434                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13435                                 last_vblank_count[pipe] !=
13436                                         drm_crtc_vblank_count(crtc),
13437                                 msecs_to_jiffies(50));
13438
13439                 WARN_ON(!lret);
13440
13441                 drm_crtc_vblank_put(crtc);
13442         }
13443 }
13444
13445 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13446 {
13447         /* fb updated, need to unpin old fb */
13448         if (crtc_state->fb_changed)
13449                 return true;
13450
13451         /* wm changes, need vblank before final wm's */
13452         if (crtc_state->update_wm_post)
13453                 return true;
13454
13455         /*
13456          * cxsr is re-enabled after vblank.
13457          * This is already handled by crtc_state->update_wm_post,
13458          * but added for clarity.
13459          */
13460         if (crtc_state->disable_cxsr)
13461                 return true;
13462
13463         return false;
13464 }
13465
13466 /**
13467  * intel_atomic_commit - commit validated state object
13468  * @dev: DRM device
13469  * @state: the top-level driver state object
13470  * @async: asynchronous commit
13471  *
13472  * This function commits a top-level state object that has been validated
13473  * with drm_atomic_helper_check().
13474  *
13475  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13476  * we can only handle plane-related operations and do not yet support
13477  * asynchronous commit.
13478  *
13479  * RETURNS
13480  * Zero for success or -errno.
13481  */
13482 static int intel_atomic_commit(struct drm_device *dev,
13483                                struct drm_atomic_state *state,
13484                                bool async)
13485 {
13486         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13487         struct drm_i915_private *dev_priv = dev->dev_private;
13488         struct drm_crtc_state *old_crtc_state;
13489         struct drm_crtc *crtc;
13490         struct intel_crtc_state *intel_cstate;
13491         int ret = 0, i;
13492         bool hw_check = intel_state->modeset;
13493         unsigned long put_domains[I915_MAX_PIPES] = {};
13494         unsigned crtc_vblank_mask = 0;
13495
13496         ret = intel_atomic_prepare_commit(dev, state, async);
13497         if (ret) {
13498                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13499                 return ret;
13500         }
13501
13502         drm_atomic_helper_swap_state(dev, state);
13503         dev_priv->wm.config = intel_state->wm_config;
13504         intel_shared_dpll_commit(state);
13505
13506         if (intel_state->modeset) {
13507                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13508                        sizeof(intel_state->min_pixclk));
13509                 dev_priv->active_crtcs = intel_state->active_crtcs;
13510                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13511
13512                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13513         }
13514
13515         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13516                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13517
13518                 if (needs_modeset(crtc->state) ||
13519                     to_intel_crtc_state(crtc->state)->update_pipe) {
13520                         hw_check = true;
13521
13522                         put_domains[to_intel_crtc(crtc)->pipe] =
13523                                 modeset_get_crtc_power_domains(crtc,
13524                                         to_intel_crtc_state(crtc->state));
13525                 }
13526
13527                 if (!needs_modeset(crtc->state))
13528                         continue;
13529
13530                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13531
13532                 if (old_crtc_state->active) {
13533                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13534                         dev_priv->display.crtc_disable(crtc);
13535                         intel_crtc->active = false;
13536                         intel_fbc_disable(intel_crtc);
13537                         intel_disable_shared_dpll(intel_crtc);
13538
13539                         /*
13540                          * Underruns don't always raise
13541                          * interrupts, so check manually.
13542                          */
13543                         intel_check_cpu_fifo_underruns(dev_priv);
13544                         intel_check_pch_fifo_underruns(dev_priv);
13545
13546                         if (!crtc->state->active)
13547                                 intel_update_watermarks(crtc);
13548                 }
13549         }
13550
13551         /* Only after disabling all output pipelines that will be changed can we
13552          * update the the output configuration. */
13553         intel_modeset_update_crtc_state(state);
13554
13555         if (intel_state->modeset) {
13556                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13557
13558                 if (dev_priv->display.modeset_commit_cdclk &&
13559                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13560                         dev_priv->display.modeset_commit_cdclk(state);
13561         }
13562
13563         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13564         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13565                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13566                 bool modeset = needs_modeset(crtc->state);
13567                 struct intel_crtc_state *pipe_config =
13568                         to_intel_crtc_state(crtc->state);
13569                 bool update_pipe = !modeset && pipe_config->update_pipe;
13570
13571                 if (modeset && crtc->state->active) {
13572                         update_scanline_offset(to_intel_crtc(crtc));
13573                         dev_priv->display.crtc_enable(crtc);
13574                 }
13575
13576                 if (!modeset)
13577                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13578
13579                 if (crtc->state->active &&
13580                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13581                         intel_fbc_enable(intel_crtc);
13582
13583                 if (crtc->state->active &&
13584                     (crtc->state->planes_changed || update_pipe))
13585                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13586
13587                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13588                         crtc_vblank_mask |= 1 << i;
13589         }
13590
13591         /* FIXME: add subpixel order */
13592
13593         if (!state->legacy_cursor_update)
13594                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13595
13596         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13597                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13598
13599                 if (put_domains[i])
13600                         modeset_put_power_domains(dev_priv, put_domains[i]);
13601         }
13602
13603         if (intel_state->modeset)
13604                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13605
13606         /*
13607          * Now that the vblank has passed, we can go ahead and program the
13608          * optimal watermarks on platforms that need two-step watermark
13609          * programming.
13610          *
13611          * TODO: Move this (and other cleanup) to an async worker eventually.
13612          */
13613         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13614                 intel_cstate = to_intel_crtc_state(crtc->state);
13615
13616                 if (dev_priv->display.optimize_watermarks)
13617                         dev_priv->display.optimize_watermarks(intel_cstate);
13618         }
13619
13620         mutex_lock(&dev->struct_mutex);
13621         drm_atomic_helper_cleanup_planes(dev, state);
13622         mutex_unlock(&dev->struct_mutex);
13623
13624         if (hw_check)
13625                 intel_modeset_check_state(dev, state);
13626
13627         drm_atomic_state_free(state);
13628
13629         /* As one of the primary mmio accessors, KMS has a high likelihood
13630          * of triggering bugs in unclaimed access. After we finish
13631          * modesetting, see if an error has been flagged, and if so
13632          * enable debugging for the next modeset - and hope we catch
13633          * the culprit.
13634          *
13635          * XXX note that we assume display power is on at this point.
13636          * This might hold true now but we need to add pm helper to check
13637          * unclaimed only when the hardware is on, as atomic commits
13638          * can happen also when the device is completely off.
13639          */
13640         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13641
13642         return 0;
13643 }
13644
13645 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13646 {
13647         struct drm_device *dev = crtc->dev;
13648         struct drm_atomic_state *state;
13649         struct drm_crtc_state *crtc_state;
13650         int ret;
13651
13652         state = drm_atomic_state_alloc(dev);
13653         if (!state) {
13654                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13655                               crtc->base.id);
13656                 return;
13657         }
13658
13659         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13660
13661 retry:
13662         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13663         ret = PTR_ERR_OR_ZERO(crtc_state);
13664         if (!ret) {
13665                 if (!crtc_state->active)
13666                         goto out;
13667
13668                 crtc_state->mode_changed = true;
13669                 ret = drm_atomic_commit(state);
13670         }
13671
13672         if (ret == -EDEADLK) {
13673                 drm_atomic_state_clear(state);
13674                 drm_modeset_backoff(state->acquire_ctx);
13675                 goto retry;
13676         }
13677
13678         if (ret)
13679 out:
13680                 drm_atomic_state_free(state);
13681 }
13682
13683 #undef for_each_intel_crtc_masked
13684
13685 static const struct drm_crtc_funcs intel_crtc_funcs = {
13686         .gamma_set = intel_color_legacy_gamma_set,
13687         .set_config = drm_atomic_helper_set_config,
13688         .destroy = intel_crtc_destroy,
13689         .page_flip = intel_crtc_page_flip,
13690         .atomic_duplicate_state = intel_crtc_duplicate_state,
13691         .atomic_destroy_state = intel_crtc_destroy_state,
13692 };
13693
13694 /**
13695  * intel_prepare_plane_fb - Prepare fb for usage on plane
13696  * @plane: drm plane to prepare for
13697  * @fb: framebuffer to prepare for presentation
13698  *
13699  * Prepares a framebuffer for usage on a display plane.  Generally this
13700  * involves pinning the underlying object and updating the frontbuffer tracking
13701  * bits.  Some older platforms need special physical address handling for
13702  * cursor planes.
13703  *
13704  * Must be called with struct_mutex held.
13705  *
13706  * Returns 0 on success, negative error code on failure.
13707  */
13708 int
13709 intel_prepare_plane_fb(struct drm_plane *plane,
13710                        const struct drm_plane_state *new_state)
13711 {
13712         struct drm_device *dev = plane->dev;
13713         struct drm_framebuffer *fb = new_state->fb;
13714         struct intel_plane *intel_plane = to_intel_plane(plane);
13715         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13716         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13717         int ret = 0;
13718
13719         if (!obj && !old_obj)
13720                 return 0;
13721
13722         if (old_obj) {
13723                 struct drm_crtc_state *crtc_state =
13724                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13725
13726                 /* Big Hammer, we also need to ensure that any pending
13727                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13728                  * current scanout is retired before unpinning the old
13729                  * framebuffer. Note that we rely on userspace rendering
13730                  * into the buffer attached to the pipe they are waiting
13731                  * on. If not, userspace generates a GPU hang with IPEHR
13732                  * point to the MI_WAIT_FOR_EVENT.
13733                  *
13734                  * This should only fail upon a hung GPU, in which case we
13735                  * can safely continue.
13736                  */
13737                 if (needs_modeset(crtc_state))
13738                         ret = i915_gem_object_wait_rendering(old_obj, true);
13739
13740                 /* Swallow -EIO errors to allow updates during hw lockup. */
13741                 if (ret && ret != -EIO)
13742                         return ret;
13743         }
13744
13745         /* For framebuffer backed by dmabuf, wait for fence */
13746         if (obj && obj->base.dma_buf) {
13747                 long lret;
13748
13749                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13750                                                            false, true,
13751                                                            MAX_SCHEDULE_TIMEOUT);
13752                 if (lret == -ERESTARTSYS)
13753                         return lret;
13754
13755                 WARN(lret < 0, "waiting returns %li\n", lret);
13756         }
13757
13758         if (!obj) {
13759                 ret = 0;
13760         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13761             INTEL_INFO(dev)->cursor_needs_physical) {
13762                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13763                 ret = i915_gem_object_attach_phys(obj, align);
13764                 if (ret)
13765                         DRM_DEBUG_KMS("failed to attach phys object\n");
13766         } else {
13767                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13768         }
13769
13770         if (ret == 0) {
13771                 if (obj) {
13772                         struct intel_plane_state *plane_state =
13773                                 to_intel_plane_state(new_state);
13774
13775                         i915_gem_request_assign(&plane_state->wait_req,
13776                                                 obj->last_write_req);
13777                 }
13778
13779                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13780         }
13781
13782         return ret;
13783 }
13784
13785 /**
13786  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13787  * @plane: drm plane to clean up for
13788  * @fb: old framebuffer that was on plane
13789  *
13790  * Cleans up a framebuffer that has just been removed from a plane.
13791  *
13792  * Must be called with struct_mutex held.
13793  */
13794 void
13795 intel_cleanup_plane_fb(struct drm_plane *plane,
13796                        const struct drm_plane_state *old_state)
13797 {
13798         struct drm_device *dev = plane->dev;
13799         struct intel_plane *intel_plane = to_intel_plane(plane);
13800         struct intel_plane_state *old_intel_state;
13801         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13802         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13803
13804         old_intel_state = to_intel_plane_state(old_state);
13805
13806         if (!obj && !old_obj)
13807                 return;
13808
13809         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13810             !INTEL_INFO(dev)->cursor_needs_physical))
13811                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13812
13813         /* prepare_fb aborted? */
13814         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13815             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13816                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13817
13818         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13819 }
13820
13821 int
13822 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13823 {
13824         int max_scale;
13825         struct drm_device *dev;
13826         struct drm_i915_private *dev_priv;
13827         int crtc_clock, cdclk;
13828
13829         if (!intel_crtc || !crtc_state->base.enable)
13830                 return DRM_PLANE_HELPER_NO_SCALING;
13831
13832         dev = intel_crtc->base.dev;
13833         dev_priv = dev->dev_private;
13834         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13835         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13836
13837         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13838                 return DRM_PLANE_HELPER_NO_SCALING;
13839
13840         /*
13841          * skl max scale is lower of:
13842          *    close to 3 but not 3, -1 is for that purpose
13843          *            or
13844          *    cdclk/crtc_clock
13845          */
13846         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13847
13848         return max_scale;
13849 }
13850
13851 static int
13852 intel_check_primary_plane(struct drm_plane *plane,
13853                           struct intel_crtc_state *crtc_state,
13854                           struct intel_plane_state *state)
13855 {
13856         struct drm_crtc *crtc = state->base.crtc;
13857         struct drm_framebuffer *fb = state->base.fb;
13858         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13859         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13860         bool can_position = false;
13861
13862         if (INTEL_INFO(plane->dev)->gen >= 9) {
13863                 /* use scaler when colorkey is not required */
13864                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13865                         min_scale = 1;
13866                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13867                 }
13868                 can_position = true;
13869         }
13870
13871         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13872                                              &state->dst, &state->clip,
13873                                              min_scale, max_scale,
13874                                              can_position, true,
13875                                              &state->visible);
13876 }
13877
13878 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13879                                     struct drm_crtc_state *old_crtc_state)
13880 {
13881         struct drm_device *dev = crtc->dev;
13882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13883         struct intel_crtc_state *old_intel_state =
13884                 to_intel_crtc_state(old_crtc_state);
13885         bool modeset = needs_modeset(crtc->state);
13886
13887         /* Perform vblank evasion around commit operation */
13888         intel_pipe_update_start(intel_crtc);
13889
13890         if (modeset)
13891                 return;
13892
13893         if (to_intel_crtc_state(crtc->state)->update_pipe)
13894                 intel_update_pipe_config(intel_crtc, old_intel_state);
13895         else if (INTEL_INFO(dev)->gen >= 9)
13896                 skl_detach_scalers(intel_crtc);
13897 }
13898
13899 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13900                                      struct drm_crtc_state *old_crtc_state)
13901 {
13902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13903
13904         intel_pipe_update_end(intel_crtc);
13905 }
13906
13907 /**
13908  * intel_plane_destroy - destroy a plane
13909  * @plane: plane to destroy
13910  *
13911  * Common destruction function for all types of planes (primary, cursor,
13912  * sprite).
13913  */
13914 void intel_plane_destroy(struct drm_plane *plane)
13915 {
13916         struct intel_plane *intel_plane = to_intel_plane(plane);
13917         drm_plane_cleanup(plane);
13918         kfree(intel_plane);
13919 }
13920
13921 const struct drm_plane_funcs intel_plane_funcs = {
13922         .update_plane = drm_atomic_helper_update_plane,
13923         .disable_plane = drm_atomic_helper_disable_plane,
13924         .destroy = intel_plane_destroy,
13925         .set_property = drm_atomic_helper_plane_set_property,
13926         .atomic_get_property = intel_plane_atomic_get_property,
13927         .atomic_set_property = intel_plane_atomic_set_property,
13928         .atomic_duplicate_state = intel_plane_duplicate_state,
13929         .atomic_destroy_state = intel_plane_destroy_state,
13930
13931 };
13932
13933 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13934                                                     int pipe)
13935 {
13936         struct intel_plane *primary;
13937         struct intel_plane_state *state;
13938         const uint32_t *intel_primary_formats;
13939         unsigned int num_formats;
13940
13941         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13942         if (primary == NULL)
13943                 return NULL;
13944
13945         state = intel_create_plane_state(&primary->base);
13946         if (!state) {
13947                 kfree(primary);
13948                 return NULL;
13949         }
13950         primary->base.state = &state->base;
13951
13952         primary->can_scale = false;
13953         primary->max_downscale = 1;
13954         if (INTEL_INFO(dev)->gen >= 9) {
13955                 primary->can_scale = true;
13956                 state->scaler_id = -1;
13957         }
13958         primary->pipe = pipe;
13959         primary->plane = pipe;
13960         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13961         primary->check_plane = intel_check_primary_plane;
13962         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13963                 primary->plane = !pipe;
13964
13965         if (INTEL_INFO(dev)->gen >= 9) {
13966                 intel_primary_formats = skl_primary_formats;
13967                 num_formats = ARRAY_SIZE(skl_primary_formats);
13968
13969                 primary->update_plane = skylake_update_primary_plane;
13970                 primary->disable_plane = skylake_disable_primary_plane;
13971         } else if (HAS_PCH_SPLIT(dev)) {
13972                 intel_primary_formats = i965_primary_formats;
13973                 num_formats = ARRAY_SIZE(i965_primary_formats);
13974
13975                 primary->update_plane = ironlake_update_primary_plane;
13976                 primary->disable_plane = i9xx_disable_primary_plane;
13977         } else if (INTEL_INFO(dev)->gen >= 4) {
13978                 intel_primary_formats = i965_primary_formats;
13979                 num_formats = ARRAY_SIZE(i965_primary_formats);
13980
13981                 primary->update_plane = i9xx_update_primary_plane;
13982                 primary->disable_plane = i9xx_disable_primary_plane;
13983         } else {
13984                 intel_primary_formats = i8xx_primary_formats;
13985                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13986
13987                 primary->update_plane = i9xx_update_primary_plane;
13988                 primary->disable_plane = i9xx_disable_primary_plane;
13989         }
13990
13991         drm_universal_plane_init(dev, &primary->base, 0,
13992                                  &intel_plane_funcs,
13993                                  intel_primary_formats, num_formats,
13994                                  DRM_PLANE_TYPE_PRIMARY, NULL);
13995
13996         if (INTEL_INFO(dev)->gen >= 4)
13997                 intel_create_rotation_property(dev, primary);
13998
13999         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14000
14001         return &primary->base;
14002 }
14003
14004 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14005 {
14006         if (!dev->mode_config.rotation_property) {
14007                 unsigned long flags = BIT(DRM_ROTATE_0) |
14008                         BIT(DRM_ROTATE_180);
14009
14010                 if (INTEL_INFO(dev)->gen >= 9)
14011                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14012
14013                 dev->mode_config.rotation_property =
14014                         drm_mode_create_rotation_property(dev, flags);
14015         }
14016         if (dev->mode_config.rotation_property)
14017                 drm_object_attach_property(&plane->base.base,
14018                                 dev->mode_config.rotation_property,
14019                                 plane->base.state->rotation);
14020 }
14021
14022 static int
14023 intel_check_cursor_plane(struct drm_plane *plane,
14024                          struct intel_crtc_state *crtc_state,
14025                          struct intel_plane_state *state)
14026 {
14027         struct drm_crtc *crtc = crtc_state->base.crtc;
14028         struct drm_framebuffer *fb = state->base.fb;
14029         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14030         enum pipe pipe = to_intel_plane(plane)->pipe;
14031         unsigned stride;
14032         int ret;
14033
14034         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14035                                             &state->dst, &state->clip,
14036                                             DRM_PLANE_HELPER_NO_SCALING,
14037                                             DRM_PLANE_HELPER_NO_SCALING,
14038                                             true, true, &state->visible);
14039         if (ret)
14040                 return ret;
14041
14042         /* if we want to turn off the cursor ignore width and height */
14043         if (!obj)
14044                 return 0;
14045
14046         /* Check for which cursor types we support */
14047         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14048                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14049                           state->base.crtc_w, state->base.crtc_h);
14050                 return -EINVAL;
14051         }
14052
14053         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14054         if (obj->base.size < stride * state->base.crtc_h) {
14055                 DRM_DEBUG_KMS("buffer is too small\n");
14056                 return -ENOMEM;
14057         }
14058
14059         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14060                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14061                 return -EINVAL;
14062         }
14063
14064         /*
14065          * There's something wrong with the cursor on CHV pipe C.
14066          * If it straddles the left edge of the screen then
14067          * moving it away from the edge or disabling it often
14068          * results in a pipe underrun, and often that can lead to
14069          * dead pipe (constant underrun reported, and it scans
14070          * out just a solid color). To recover from that, the
14071          * display power well must be turned off and on again.
14072          * Refuse the put the cursor into that compromised position.
14073          */
14074         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14075             state->visible && state->base.crtc_x < 0) {
14076                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14077                 return -EINVAL;
14078         }
14079
14080         return 0;
14081 }
14082
14083 static void
14084 intel_disable_cursor_plane(struct drm_plane *plane,
14085                            struct drm_crtc *crtc)
14086 {
14087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14088
14089         intel_crtc->cursor_addr = 0;
14090         intel_crtc_update_cursor(crtc, NULL);
14091 }
14092
14093 static void
14094 intel_update_cursor_plane(struct drm_plane *plane,
14095                           const struct intel_crtc_state *crtc_state,
14096                           const struct intel_plane_state *state)
14097 {
14098         struct drm_crtc *crtc = crtc_state->base.crtc;
14099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14100         struct drm_device *dev = plane->dev;
14101         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14102         uint32_t addr;
14103
14104         if (!obj)
14105                 addr = 0;
14106         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14107                 addr = i915_gem_obj_ggtt_offset(obj);
14108         else
14109                 addr = obj->phys_handle->busaddr;
14110
14111         intel_crtc->cursor_addr = addr;
14112         intel_crtc_update_cursor(crtc, state);
14113 }
14114
14115 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14116                                                    int pipe)
14117 {
14118         struct intel_plane *cursor;
14119         struct intel_plane_state *state;
14120
14121         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14122         if (cursor == NULL)
14123                 return NULL;
14124
14125         state = intel_create_plane_state(&cursor->base);
14126         if (!state) {
14127                 kfree(cursor);
14128                 return NULL;
14129         }
14130         cursor->base.state = &state->base;
14131
14132         cursor->can_scale = false;
14133         cursor->max_downscale = 1;
14134         cursor->pipe = pipe;
14135         cursor->plane = pipe;
14136         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14137         cursor->check_plane = intel_check_cursor_plane;
14138         cursor->update_plane = intel_update_cursor_plane;
14139         cursor->disable_plane = intel_disable_cursor_plane;
14140
14141         drm_universal_plane_init(dev, &cursor->base, 0,
14142                                  &intel_plane_funcs,
14143                                  intel_cursor_formats,
14144                                  ARRAY_SIZE(intel_cursor_formats),
14145                                  DRM_PLANE_TYPE_CURSOR, NULL);
14146
14147         if (INTEL_INFO(dev)->gen >= 4) {
14148                 if (!dev->mode_config.rotation_property)
14149                         dev->mode_config.rotation_property =
14150                                 drm_mode_create_rotation_property(dev,
14151                                                         BIT(DRM_ROTATE_0) |
14152                                                         BIT(DRM_ROTATE_180));
14153                 if (dev->mode_config.rotation_property)
14154                         drm_object_attach_property(&cursor->base.base,
14155                                 dev->mode_config.rotation_property,
14156                                 state->base.rotation);
14157         }
14158
14159         if (INTEL_INFO(dev)->gen >=9)
14160                 state->scaler_id = -1;
14161
14162         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14163
14164         return &cursor->base;
14165 }
14166
14167 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14168         struct intel_crtc_state *crtc_state)
14169 {
14170         int i;
14171         struct intel_scaler *intel_scaler;
14172         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14173
14174         for (i = 0; i < intel_crtc->num_scalers; i++) {
14175                 intel_scaler = &scaler_state->scalers[i];
14176                 intel_scaler->in_use = 0;
14177                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14178         }
14179
14180         scaler_state->scaler_id = -1;
14181 }
14182
14183 static void intel_crtc_init(struct drm_device *dev, int pipe)
14184 {
14185         struct drm_i915_private *dev_priv = dev->dev_private;
14186         struct intel_crtc *intel_crtc;
14187         struct intel_crtc_state *crtc_state = NULL;
14188         struct drm_plane *primary = NULL;
14189         struct drm_plane *cursor = NULL;
14190         int ret;
14191
14192         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14193         if (intel_crtc == NULL)
14194                 return;
14195
14196         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14197         if (!crtc_state)
14198                 goto fail;
14199         intel_crtc->config = crtc_state;
14200         intel_crtc->base.state = &crtc_state->base;
14201         crtc_state->base.crtc = &intel_crtc->base;
14202
14203         /* initialize shared scalers */
14204         if (INTEL_INFO(dev)->gen >= 9) {
14205                 if (pipe == PIPE_C)
14206                         intel_crtc->num_scalers = 1;
14207                 else
14208                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14209
14210                 skl_init_scalers(dev, intel_crtc, crtc_state);
14211         }
14212
14213         primary = intel_primary_plane_create(dev, pipe);
14214         if (!primary)
14215                 goto fail;
14216
14217         cursor = intel_cursor_plane_create(dev, pipe);
14218         if (!cursor)
14219                 goto fail;
14220
14221         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14222                                         cursor, &intel_crtc_funcs, NULL);
14223         if (ret)
14224                 goto fail;
14225
14226         /*
14227          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14228          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14229          */
14230         intel_crtc->pipe = pipe;
14231         intel_crtc->plane = pipe;
14232         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14233                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14234                 intel_crtc->plane = !pipe;
14235         }
14236
14237         intel_crtc->cursor_base = ~0;
14238         intel_crtc->cursor_cntl = ~0;
14239         intel_crtc->cursor_size = ~0;
14240
14241         intel_crtc->wm.cxsr_allowed = true;
14242
14243         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14244                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14245         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14246         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14247
14248         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14249
14250         intel_color_init(&intel_crtc->base);
14251
14252         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14253         return;
14254
14255 fail:
14256         if (primary)
14257                 drm_plane_cleanup(primary);
14258         if (cursor)
14259                 drm_plane_cleanup(cursor);
14260         kfree(crtc_state);
14261         kfree(intel_crtc);
14262 }
14263
14264 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14265 {
14266         struct drm_encoder *encoder = connector->base.encoder;
14267         struct drm_device *dev = connector->base.dev;
14268
14269         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14270
14271         if (!encoder || WARN_ON(!encoder->crtc))
14272                 return INVALID_PIPE;
14273
14274         return to_intel_crtc(encoder->crtc)->pipe;
14275 }
14276
14277 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14278                                 struct drm_file *file)
14279 {
14280         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14281         struct drm_crtc *drmmode_crtc;
14282         struct intel_crtc *crtc;
14283
14284         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14285
14286         if (!drmmode_crtc) {
14287                 DRM_ERROR("no such CRTC id\n");
14288                 return -ENOENT;
14289         }
14290
14291         crtc = to_intel_crtc(drmmode_crtc);
14292         pipe_from_crtc_id->pipe = crtc->pipe;
14293
14294         return 0;
14295 }
14296
14297 static int intel_encoder_clones(struct intel_encoder *encoder)
14298 {
14299         struct drm_device *dev = encoder->base.dev;
14300         struct intel_encoder *source_encoder;
14301         int index_mask = 0;
14302         int entry = 0;
14303
14304         for_each_intel_encoder(dev, source_encoder) {
14305                 if (encoders_cloneable(encoder, source_encoder))
14306                         index_mask |= (1 << entry);
14307
14308                 entry++;
14309         }
14310
14311         return index_mask;
14312 }
14313
14314 static bool has_edp_a(struct drm_device *dev)
14315 {
14316         struct drm_i915_private *dev_priv = dev->dev_private;
14317
14318         if (!IS_MOBILE(dev))
14319                 return false;
14320
14321         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14322                 return false;
14323
14324         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14325                 return false;
14326
14327         return true;
14328 }
14329
14330 static bool intel_crt_present(struct drm_device *dev)
14331 {
14332         struct drm_i915_private *dev_priv = dev->dev_private;
14333
14334         if (INTEL_INFO(dev)->gen >= 9)
14335                 return false;
14336
14337         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14338                 return false;
14339
14340         if (IS_CHERRYVIEW(dev))
14341                 return false;
14342
14343         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14344                 return false;
14345
14346         /* DDI E can't be used if DDI A requires 4 lanes */
14347         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14348                 return false;
14349
14350         if (!dev_priv->vbt.int_crt_support)
14351                 return false;
14352
14353         return true;
14354 }
14355
14356 static void intel_setup_outputs(struct drm_device *dev)
14357 {
14358         struct drm_i915_private *dev_priv = dev->dev_private;
14359         struct intel_encoder *encoder;
14360         bool dpd_is_edp = false;
14361
14362         intel_lvds_init(dev);
14363
14364         if (intel_crt_present(dev))
14365                 intel_crt_init(dev);
14366
14367         if (IS_BROXTON(dev)) {
14368                 /*
14369                  * FIXME: Broxton doesn't support port detection via the
14370                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14371                  * detect the ports.
14372                  */
14373                 intel_ddi_init(dev, PORT_A);
14374                 intel_ddi_init(dev, PORT_B);
14375                 intel_ddi_init(dev, PORT_C);
14376         } else if (HAS_DDI(dev)) {
14377                 int found;
14378
14379                 /*
14380                  * Haswell uses DDI functions to detect digital outputs.
14381                  * On SKL pre-D0 the strap isn't connected, so we assume
14382                  * it's there.
14383                  */
14384                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14385                 /* WaIgnoreDDIAStrap: skl */
14386                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14387                         intel_ddi_init(dev, PORT_A);
14388
14389                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14390                  * register */
14391                 found = I915_READ(SFUSE_STRAP);
14392
14393                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14394                         intel_ddi_init(dev, PORT_B);
14395                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14396                         intel_ddi_init(dev, PORT_C);
14397                 if (found & SFUSE_STRAP_DDID_DETECTED)
14398                         intel_ddi_init(dev, PORT_D);
14399                 /*
14400                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14401                  */
14402                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14403                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14404                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14405                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14406                         intel_ddi_init(dev, PORT_E);
14407
14408         } else if (HAS_PCH_SPLIT(dev)) {
14409                 int found;
14410                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14411
14412                 if (has_edp_a(dev))
14413                         intel_dp_init(dev, DP_A, PORT_A);
14414
14415                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14416                         /* PCH SDVOB multiplex with HDMIB */
14417                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14418                         if (!found)
14419                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14420                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14421                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14422                 }
14423
14424                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14425                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14426
14427                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14428                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14429
14430                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14431                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14432
14433                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14434                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14435         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14436                 /*
14437                  * The DP_DETECTED bit is the latched state of the DDC
14438                  * SDA pin at boot. However since eDP doesn't require DDC
14439                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14440                  * eDP ports may have been muxed to an alternate function.
14441                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14442                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14443                  * detect eDP ports.
14444                  */
14445                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14446                     !intel_dp_is_edp(dev, PORT_B))
14447                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14448                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14449                     intel_dp_is_edp(dev, PORT_B))
14450                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14451
14452                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14453                     !intel_dp_is_edp(dev, PORT_C))
14454                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14455                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14456                     intel_dp_is_edp(dev, PORT_C))
14457                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14458
14459                 if (IS_CHERRYVIEW(dev)) {
14460                         /* eDP not supported on port D, so don't check VBT */
14461                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14462                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14463                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14464                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14465                 }
14466
14467                 intel_dsi_init(dev);
14468         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14469                 bool found = false;
14470
14471                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14472                         DRM_DEBUG_KMS("probing SDVOB\n");
14473                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14474                         if (!found && IS_G4X(dev)) {
14475                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14476                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14477                         }
14478
14479                         if (!found && IS_G4X(dev))
14480                                 intel_dp_init(dev, DP_B, PORT_B);
14481                 }
14482
14483                 /* Before G4X SDVOC doesn't have its own detect register */
14484
14485                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14486                         DRM_DEBUG_KMS("probing SDVOC\n");
14487                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14488                 }
14489
14490                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14491
14492                         if (IS_G4X(dev)) {
14493                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14494                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14495                         }
14496                         if (IS_G4X(dev))
14497                                 intel_dp_init(dev, DP_C, PORT_C);
14498                 }
14499
14500                 if (IS_G4X(dev) &&
14501                     (I915_READ(DP_D) & DP_DETECTED))
14502                         intel_dp_init(dev, DP_D, PORT_D);
14503         } else if (IS_GEN2(dev))
14504                 intel_dvo_init(dev);
14505
14506         if (SUPPORTS_TV(dev))
14507                 intel_tv_init(dev);
14508
14509         intel_psr_init(dev);
14510
14511         for_each_intel_encoder(dev, encoder) {
14512                 encoder->base.possible_crtcs = encoder->crtc_mask;
14513                 encoder->base.possible_clones =
14514                         intel_encoder_clones(encoder);
14515         }
14516
14517         intel_init_pch_refclk(dev);
14518
14519         drm_helper_move_panel_connectors_to_head(dev);
14520 }
14521
14522 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14523 {
14524         struct drm_device *dev = fb->dev;
14525         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14526
14527         drm_framebuffer_cleanup(fb);
14528         mutex_lock(&dev->struct_mutex);
14529         WARN_ON(!intel_fb->obj->framebuffer_references--);
14530         drm_gem_object_unreference(&intel_fb->obj->base);
14531         mutex_unlock(&dev->struct_mutex);
14532         kfree(intel_fb);
14533 }
14534
14535 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14536                                                 struct drm_file *file,
14537                                                 unsigned int *handle)
14538 {
14539         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14540         struct drm_i915_gem_object *obj = intel_fb->obj;
14541
14542         if (obj->userptr.mm) {
14543                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14544                 return -EINVAL;
14545         }
14546
14547         return drm_gem_handle_create(file, &obj->base, handle);
14548 }
14549
14550 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14551                                         struct drm_file *file,
14552                                         unsigned flags, unsigned color,
14553                                         struct drm_clip_rect *clips,
14554                                         unsigned num_clips)
14555 {
14556         struct drm_device *dev = fb->dev;
14557         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14558         struct drm_i915_gem_object *obj = intel_fb->obj;
14559
14560         mutex_lock(&dev->struct_mutex);
14561         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14562         mutex_unlock(&dev->struct_mutex);
14563
14564         return 0;
14565 }
14566
14567 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14568         .destroy = intel_user_framebuffer_destroy,
14569         .create_handle = intel_user_framebuffer_create_handle,
14570         .dirty = intel_user_framebuffer_dirty,
14571 };
14572
14573 static
14574 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14575                          uint32_t pixel_format)
14576 {
14577         u32 gen = INTEL_INFO(dev)->gen;
14578
14579         if (gen >= 9) {
14580                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14581
14582                 /* "The stride in bytes must not exceed the of the size of 8K
14583                  *  pixels and 32K bytes."
14584                  */
14585                 return min(8192 * cpp, 32768);
14586         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14587                 return 32*1024;
14588         } else if (gen >= 4) {
14589                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14590                         return 16*1024;
14591                 else
14592                         return 32*1024;
14593         } else if (gen >= 3) {
14594                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14595                         return 8*1024;
14596                 else
14597                         return 16*1024;
14598         } else {
14599                 /* XXX DSPC is limited to 4k tiled */
14600                 return 8*1024;
14601         }
14602 }
14603
14604 static int intel_framebuffer_init(struct drm_device *dev,
14605                                   struct intel_framebuffer *intel_fb,
14606                                   struct drm_mode_fb_cmd2 *mode_cmd,
14607                                   struct drm_i915_gem_object *obj)
14608 {
14609         struct drm_i915_private *dev_priv = to_i915(dev);
14610         unsigned int aligned_height;
14611         int ret;
14612         u32 pitch_limit, stride_alignment;
14613
14614         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14615
14616         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14617                 /* Enforce that fb modifier and tiling mode match, but only for
14618                  * X-tiled. This is needed for FBC. */
14619                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14620                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14621                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14622                         return -EINVAL;
14623                 }
14624         } else {
14625                 if (obj->tiling_mode == I915_TILING_X)
14626                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14627                 else if (obj->tiling_mode == I915_TILING_Y) {
14628                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14629                         return -EINVAL;
14630                 }
14631         }
14632
14633         /* Passed in modifier sanity checking. */
14634         switch (mode_cmd->modifier[0]) {
14635         case I915_FORMAT_MOD_Y_TILED:
14636         case I915_FORMAT_MOD_Yf_TILED:
14637                 if (INTEL_INFO(dev)->gen < 9) {
14638                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14639                                   mode_cmd->modifier[0]);
14640                         return -EINVAL;
14641                 }
14642         case DRM_FORMAT_MOD_NONE:
14643         case I915_FORMAT_MOD_X_TILED:
14644                 break;
14645         default:
14646                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14647                           mode_cmd->modifier[0]);
14648                 return -EINVAL;
14649         }
14650
14651         stride_alignment = intel_fb_stride_alignment(dev_priv,
14652                                                      mode_cmd->modifier[0],
14653                                                      mode_cmd->pixel_format);
14654         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14655                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14656                           mode_cmd->pitches[0], stride_alignment);
14657                 return -EINVAL;
14658         }
14659
14660         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14661                                            mode_cmd->pixel_format);
14662         if (mode_cmd->pitches[0] > pitch_limit) {
14663                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14664                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14665                           "tiled" : "linear",
14666                           mode_cmd->pitches[0], pitch_limit);
14667                 return -EINVAL;
14668         }
14669
14670         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14671             mode_cmd->pitches[0] != obj->stride) {
14672                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14673                           mode_cmd->pitches[0], obj->stride);
14674                 return -EINVAL;
14675         }
14676
14677         /* Reject formats not supported by any plane early. */
14678         switch (mode_cmd->pixel_format) {
14679         case DRM_FORMAT_C8:
14680         case DRM_FORMAT_RGB565:
14681         case DRM_FORMAT_XRGB8888:
14682         case DRM_FORMAT_ARGB8888:
14683                 break;
14684         case DRM_FORMAT_XRGB1555:
14685                 if (INTEL_INFO(dev)->gen > 3) {
14686                         DRM_DEBUG("unsupported pixel format: %s\n",
14687                                   drm_get_format_name(mode_cmd->pixel_format));
14688                         return -EINVAL;
14689                 }
14690                 break;
14691         case DRM_FORMAT_ABGR8888:
14692                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14693                     INTEL_INFO(dev)->gen < 9) {
14694                         DRM_DEBUG("unsupported pixel format: %s\n",
14695                                   drm_get_format_name(mode_cmd->pixel_format));
14696                         return -EINVAL;
14697                 }
14698                 break;
14699         case DRM_FORMAT_XBGR8888:
14700         case DRM_FORMAT_XRGB2101010:
14701         case DRM_FORMAT_XBGR2101010:
14702                 if (INTEL_INFO(dev)->gen < 4) {
14703                         DRM_DEBUG("unsupported pixel format: %s\n",
14704                                   drm_get_format_name(mode_cmd->pixel_format));
14705                         return -EINVAL;
14706                 }
14707                 break;
14708         case DRM_FORMAT_ABGR2101010:
14709                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14710                         DRM_DEBUG("unsupported pixel format: %s\n",
14711                                   drm_get_format_name(mode_cmd->pixel_format));
14712                         return -EINVAL;
14713                 }
14714                 break;
14715         case DRM_FORMAT_YUYV:
14716         case DRM_FORMAT_UYVY:
14717         case DRM_FORMAT_YVYU:
14718         case DRM_FORMAT_VYUY:
14719                 if (INTEL_INFO(dev)->gen < 5) {
14720                         DRM_DEBUG("unsupported pixel format: %s\n",
14721                                   drm_get_format_name(mode_cmd->pixel_format));
14722                         return -EINVAL;
14723                 }
14724                 break;
14725         default:
14726                 DRM_DEBUG("unsupported pixel format: %s\n",
14727                           drm_get_format_name(mode_cmd->pixel_format));
14728                 return -EINVAL;
14729         }
14730
14731         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14732         if (mode_cmd->offsets[0] != 0)
14733                 return -EINVAL;
14734
14735         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14736                                                mode_cmd->pixel_format,
14737                                                mode_cmd->modifier[0]);
14738         /* FIXME drm helper for size checks (especially planar formats)? */
14739         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14740                 return -EINVAL;
14741
14742         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14743         intel_fb->obj = obj;
14744
14745         intel_fill_fb_info(dev_priv, &intel_fb->base);
14746
14747         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14748         if (ret) {
14749                 DRM_ERROR("framebuffer init failed %d\n", ret);
14750                 return ret;
14751         }
14752
14753         intel_fb->obj->framebuffer_references++;
14754
14755         return 0;
14756 }
14757
14758 static struct drm_framebuffer *
14759 intel_user_framebuffer_create(struct drm_device *dev,
14760                               struct drm_file *filp,
14761                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14762 {
14763         struct drm_framebuffer *fb;
14764         struct drm_i915_gem_object *obj;
14765         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14766
14767         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14768                                                 mode_cmd.handles[0]));
14769         if (&obj->base == NULL)
14770                 return ERR_PTR(-ENOENT);
14771
14772         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14773         if (IS_ERR(fb))
14774                 drm_gem_object_unreference_unlocked(&obj->base);
14775
14776         return fb;
14777 }
14778
14779 #ifndef CONFIG_DRM_FBDEV_EMULATION
14780 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14781 {
14782 }
14783 #endif
14784
14785 static const struct drm_mode_config_funcs intel_mode_funcs = {
14786         .fb_create = intel_user_framebuffer_create,
14787         .output_poll_changed = intel_fbdev_output_poll_changed,
14788         .atomic_check = intel_atomic_check,
14789         .atomic_commit = intel_atomic_commit,
14790         .atomic_state_alloc = intel_atomic_state_alloc,
14791         .atomic_state_clear = intel_atomic_state_clear,
14792 };
14793
14794 /**
14795  * intel_init_display_hooks - initialize the display modesetting hooks
14796  * @dev_priv: device private
14797  */
14798 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14799 {
14800         if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
14801                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14802         else if (IS_CHERRYVIEW(dev_priv))
14803                 dev_priv->display.find_dpll = chv_find_best_dpll;
14804         else if (IS_VALLEYVIEW(dev_priv))
14805                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14806         else if (IS_PINEVIEW(dev_priv))
14807                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14808         else
14809                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14810
14811         if (INTEL_INFO(dev_priv)->gen >= 9) {
14812                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14813                 dev_priv->display.get_initial_plane_config =
14814                         skylake_get_initial_plane_config;
14815                 dev_priv->display.crtc_compute_clock =
14816                         haswell_crtc_compute_clock;
14817                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14818                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14819         } else if (HAS_DDI(dev_priv)) {
14820                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14821                 dev_priv->display.get_initial_plane_config =
14822                         ironlake_get_initial_plane_config;
14823                 dev_priv->display.crtc_compute_clock =
14824                         haswell_crtc_compute_clock;
14825                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14826                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14827         } else if (HAS_PCH_SPLIT(dev_priv)) {
14828                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14829                 dev_priv->display.get_initial_plane_config =
14830                         ironlake_get_initial_plane_config;
14831                 dev_priv->display.crtc_compute_clock =
14832                         ironlake_crtc_compute_clock;
14833                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14834                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14835         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14836                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14837                 dev_priv->display.get_initial_plane_config =
14838                         i9xx_get_initial_plane_config;
14839                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14840                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14841                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14842         } else {
14843                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14844                 dev_priv->display.get_initial_plane_config =
14845                         i9xx_get_initial_plane_config;
14846                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14847                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14848                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14849         }
14850
14851         /* Returns the core display clock speed */
14852         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14853                 dev_priv->display.get_display_clock_speed =
14854                         skylake_get_display_clock_speed;
14855         else if (IS_BROXTON(dev_priv))
14856                 dev_priv->display.get_display_clock_speed =
14857                         broxton_get_display_clock_speed;
14858         else if (IS_BROADWELL(dev_priv))
14859                 dev_priv->display.get_display_clock_speed =
14860                         broadwell_get_display_clock_speed;
14861         else if (IS_HASWELL(dev_priv))
14862                 dev_priv->display.get_display_clock_speed =
14863                         haswell_get_display_clock_speed;
14864         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14865                 dev_priv->display.get_display_clock_speed =
14866                         valleyview_get_display_clock_speed;
14867         else if (IS_GEN5(dev_priv))
14868                 dev_priv->display.get_display_clock_speed =
14869                         ilk_get_display_clock_speed;
14870         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14871                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14872                 dev_priv->display.get_display_clock_speed =
14873                         i945_get_display_clock_speed;
14874         else if (IS_GM45(dev_priv))
14875                 dev_priv->display.get_display_clock_speed =
14876                         gm45_get_display_clock_speed;
14877         else if (IS_CRESTLINE(dev_priv))
14878                 dev_priv->display.get_display_clock_speed =
14879                         i965gm_get_display_clock_speed;
14880         else if (IS_PINEVIEW(dev_priv))
14881                 dev_priv->display.get_display_clock_speed =
14882                         pnv_get_display_clock_speed;
14883         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14884                 dev_priv->display.get_display_clock_speed =
14885                         g33_get_display_clock_speed;
14886         else if (IS_I915G(dev_priv))
14887                 dev_priv->display.get_display_clock_speed =
14888                         i915_get_display_clock_speed;
14889         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14890                 dev_priv->display.get_display_clock_speed =
14891                         i9xx_misc_get_display_clock_speed;
14892         else if (IS_I915GM(dev_priv))
14893                 dev_priv->display.get_display_clock_speed =
14894                         i915gm_get_display_clock_speed;
14895         else if (IS_I865G(dev_priv))
14896                 dev_priv->display.get_display_clock_speed =
14897                         i865_get_display_clock_speed;
14898         else if (IS_I85X(dev_priv))
14899                 dev_priv->display.get_display_clock_speed =
14900                         i85x_get_display_clock_speed;
14901         else { /* 830 */
14902                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14903                 dev_priv->display.get_display_clock_speed =
14904                         i830_get_display_clock_speed;
14905         }
14906
14907         if (IS_GEN5(dev_priv)) {
14908                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14909         } else if (IS_GEN6(dev_priv)) {
14910                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14911         } else if (IS_IVYBRIDGE(dev_priv)) {
14912                 /* FIXME: detect B0+ stepping and use auto training */
14913                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14914         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14915                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14916                 if (IS_BROADWELL(dev_priv)) {
14917                         dev_priv->display.modeset_commit_cdclk =
14918                                 broadwell_modeset_commit_cdclk;
14919                         dev_priv->display.modeset_calc_cdclk =
14920                                 broadwell_modeset_calc_cdclk;
14921                 }
14922         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14923                 dev_priv->display.modeset_commit_cdclk =
14924                         valleyview_modeset_commit_cdclk;
14925                 dev_priv->display.modeset_calc_cdclk =
14926                         valleyview_modeset_calc_cdclk;
14927         } else if (IS_BROXTON(dev_priv)) {
14928                 dev_priv->display.modeset_commit_cdclk =
14929                         broxton_modeset_commit_cdclk;
14930                 dev_priv->display.modeset_calc_cdclk =
14931                         broxton_modeset_calc_cdclk;
14932         }
14933
14934         switch (INTEL_INFO(dev_priv)->gen) {
14935         case 2:
14936                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14937                 break;
14938
14939         case 3:
14940                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14941                 break;
14942
14943         case 4:
14944         case 5:
14945                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14946                 break;
14947
14948         case 6:
14949                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14950                 break;
14951         case 7:
14952         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14953                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14954                 break;
14955         case 9:
14956                 /* Drop through - unsupported since execlist only. */
14957         default:
14958                 /* Default just returns -ENODEV to indicate unsupported */
14959                 dev_priv->display.queue_flip = intel_default_queue_flip;
14960         }
14961 }
14962
14963 /*
14964  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14965  * resume, or other times.  This quirk makes sure that's the case for
14966  * affected systems.
14967  */
14968 static void quirk_pipea_force(struct drm_device *dev)
14969 {
14970         struct drm_i915_private *dev_priv = dev->dev_private;
14971
14972         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14973         DRM_INFO("applying pipe a force quirk\n");
14974 }
14975
14976 static void quirk_pipeb_force(struct drm_device *dev)
14977 {
14978         struct drm_i915_private *dev_priv = dev->dev_private;
14979
14980         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14981         DRM_INFO("applying pipe b force quirk\n");
14982 }
14983
14984 /*
14985  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14986  */
14987 static void quirk_ssc_force_disable(struct drm_device *dev)
14988 {
14989         struct drm_i915_private *dev_priv = dev->dev_private;
14990         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14991         DRM_INFO("applying lvds SSC disable quirk\n");
14992 }
14993
14994 /*
14995  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14996  * brightness value
14997  */
14998 static void quirk_invert_brightness(struct drm_device *dev)
14999 {
15000         struct drm_i915_private *dev_priv = dev->dev_private;
15001         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15002         DRM_INFO("applying inverted panel brightness quirk\n");
15003 }
15004
15005 /* Some VBT's incorrectly indicate no backlight is present */
15006 static void quirk_backlight_present(struct drm_device *dev)
15007 {
15008         struct drm_i915_private *dev_priv = dev->dev_private;
15009         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15010         DRM_INFO("applying backlight present quirk\n");
15011 }
15012
15013 struct intel_quirk {
15014         int device;
15015         int subsystem_vendor;
15016         int subsystem_device;
15017         void (*hook)(struct drm_device *dev);
15018 };
15019
15020 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15021 struct intel_dmi_quirk {
15022         void (*hook)(struct drm_device *dev);
15023         const struct dmi_system_id (*dmi_id_list)[];
15024 };
15025
15026 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15027 {
15028         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15029         return 1;
15030 }
15031
15032 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15033         {
15034                 .dmi_id_list = &(const struct dmi_system_id[]) {
15035                         {
15036                                 .callback = intel_dmi_reverse_brightness,
15037                                 .ident = "NCR Corporation",
15038                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15039                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15040                                 },
15041                         },
15042                         { }  /* terminating entry */
15043                 },
15044                 .hook = quirk_invert_brightness,
15045         },
15046 };
15047
15048 static struct intel_quirk intel_quirks[] = {
15049         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15050         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15051
15052         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15053         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15054
15055         /* 830 needs to leave pipe A & dpll A up */
15056         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15057
15058         /* 830 needs to leave pipe B & dpll B up */
15059         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15060
15061         /* Lenovo U160 cannot use SSC on LVDS */
15062         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15063
15064         /* Sony Vaio Y cannot use SSC on LVDS */
15065         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15066
15067         /* Acer Aspire 5734Z must invert backlight brightness */
15068         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15069
15070         /* Acer/eMachines G725 */
15071         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15072
15073         /* Acer/eMachines e725 */
15074         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15075
15076         /* Acer/Packard Bell NCL20 */
15077         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15078
15079         /* Acer Aspire 4736Z */
15080         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15081
15082         /* Acer Aspire 5336 */
15083         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15084
15085         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15086         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15087
15088         /* Acer C720 Chromebook (Core i3 4005U) */
15089         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15090
15091         /* Apple Macbook 2,1 (Core 2 T7400) */
15092         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15093
15094         /* Apple Macbook 4,1 */
15095         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15096
15097         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15098         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15099
15100         /* HP Chromebook 14 (Celeron 2955U) */
15101         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15102
15103         /* Dell Chromebook 11 */
15104         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15105
15106         /* Dell Chromebook 11 (2015 version) */
15107         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15108 };
15109
15110 static void intel_init_quirks(struct drm_device *dev)
15111 {
15112         struct pci_dev *d = dev->pdev;
15113         int i;
15114
15115         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15116                 struct intel_quirk *q = &intel_quirks[i];
15117
15118                 if (d->device == q->device &&
15119                     (d->subsystem_vendor == q->subsystem_vendor ||
15120                      q->subsystem_vendor == PCI_ANY_ID) &&
15121                     (d->subsystem_device == q->subsystem_device ||
15122                      q->subsystem_device == PCI_ANY_ID))
15123                         q->hook(dev);
15124         }
15125         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15126                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15127                         intel_dmi_quirks[i].hook(dev);
15128         }
15129 }
15130
15131 /* Disable the VGA plane that we never use */
15132 static void i915_disable_vga(struct drm_device *dev)
15133 {
15134         struct drm_i915_private *dev_priv = dev->dev_private;
15135         u8 sr1;
15136         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15137
15138         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15139         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15140         outb(SR01, VGA_SR_INDEX);
15141         sr1 = inb(VGA_SR_DATA);
15142         outb(sr1 | 1<<5, VGA_SR_DATA);
15143         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15144         udelay(300);
15145
15146         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15147         POSTING_READ(vga_reg);
15148 }
15149
15150 void intel_modeset_init_hw(struct drm_device *dev)
15151 {
15152         struct drm_i915_private *dev_priv = dev->dev_private;
15153
15154         intel_update_cdclk(dev);
15155
15156         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15157
15158         intel_init_clock_gating(dev);
15159         intel_enable_gt_powersave(dev);
15160 }
15161
15162 /*
15163  * Calculate what we think the watermarks should be for the state we've read
15164  * out of the hardware and then immediately program those watermarks so that
15165  * we ensure the hardware settings match our internal state.
15166  *
15167  * We can calculate what we think WM's should be by creating a duplicate of the
15168  * current state (which was constructed during hardware readout) and running it
15169  * through the atomic check code to calculate new watermark values in the
15170  * state object.
15171  */
15172 static void sanitize_watermarks(struct drm_device *dev)
15173 {
15174         struct drm_i915_private *dev_priv = to_i915(dev);
15175         struct drm_atomic_state *state;
15176         struct drm_crtc *crtc;
15177         struct drm_crtc_state *cstate;
15178         struct drm_modeset_acquire_ctx ctx;
15179         int ret;
15180         int i;
15181
15182         /* Only supported on platforms that use atomic watermark design */
15183         if (!dev_priv->display.optimize_watermarks)
15184                 return;
15185
15186         /*
15187          * We need to hold connection_mutex before calling duplicate_state so
15188          * that the connector loop is protected.
15189          */
15190         drm_modeset_acquire_init(&ctx, 0);
15191 retry:
15192         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15193         if (ret == -EDEADLK) {
15194                 drm_modeset_backoff(&ctx);
15195                 goto retry;
15196         } else if (WARN_ON(ret)) {
15197                 goto fail;
15198         }
15199
15200         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15201         if (WARN_ON(IS_ERR(state)))
15202                 goto fail;
15203
15204         /*
15205          * Hardware readout is the only time we don't want to calculate
15206          * intermediate watermarks (since we don't trust the current
15207          * watermarks).
15208          */
15209         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15210
15211         ret = intel_atomic_check(dev, state);
15212         if (ret) {
15213                 /*
15214                  * If we fail here, it means that the hardware appears to be
15215                  * programmed in a way that shouldn't be possible, given our
15216                  * understanding of watermark requirements.  This might mean a
15217                  * mistake in the hardware readout code or a mistake in the
15218                  * watermark calculations for a given platform.  Raise a WARN
15219                  * so that this is noticeable.
15220                  *
15221                  * If this actually happens, we'll have to just leave the
15222                  * BIOS-programmed watermarks untouched and hope for the best.
15223                  */
15224                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15225                 goto fail;
15226         }
15227
15228         /* Write calculated watermark values back */
15229         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15230         for_each_crtc_in_state(state, crtc, cstate, i) {
15231                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15232
15233                 cs->wm.need_postvbl_update = true;
15234                 dev_priv->display.optimize_watermarks(cs);
15235         }
15236
15237         drm_atomic_state_free(state);
15238 fail:
15239         drm_modeset_drop_locks(&ctx);
15240         drm_modeset_acquire_fini(&ctx);
15241 }
15242
15243 void intel_modeset_init(struct drm_device *dev)
15244 {
15245         struct drm_i915_private *dev_priv = dev->dev_private;
15246         int sprite, ret;
15247         enum pipe pipe;
15248         struct intel_crtc *crtc;
15249
15250         drm_mode_config_init(dev);
15251
15252         dev->mode_config.min_width = 0;
15253         dev->mode_config.min_height = 0;
15254
15255         dev->mode_config.preferred_depth = 24;
15256         dev->mode_config.prefer_shadow = 1;
15257
15258         dev->mode_config.allow_fb_modifiers = true;
15259
15260         dev->mode_config.funcs = &intel_mode_funcs;
15261
15262         intel_init_quirks(dev);
15263
15264         intel_init_pm(dev);
15265
15266         if (INTEL_INFO(dev)->num_pipes == 0)
15267                 return;
15268
15269         /*
15270          * There may be no VBT; and if the BIOS enabled SSC we can
15271          * just keep using it to avoid unnecessary flicker.  Whereas if the
15272          * BIOS isn't using it, don't assume it will work even if the VBT
15273          * indicates as much.
15274          */
15275         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15276                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15277                                             DREF_SSC1_ENABLE);
15278
15279                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15280                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15281                                      bios_lvds_use_ssc ? "en" : "dis",
15282                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15283                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15284                 }
15285         }
15286
15287         if (IS_GEN2(dev)) {
15288                 dev->mode_config.max_width = 2048;
15289                 dev->mode_config.max_height = 2048;
15290         } else if (IS_GEN3(dev)) {
15291                 dev->mode_config.max_width = 4096;
15292                 dev->mode_config.max_height = 4096;
15293         } else {
15294                 dev->mode_config.max_width = 8192;
15295                 dev->mode_config.max_height = 8192;
15296         }
15297
15298         if (IS_845G(dev) || IS_I865G(dev)) {
15299                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15300                 dev->mode_config.cursor_height = 1023;
15301         } else if (IS_GEN2(dev)) {
15302                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15303                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15304         } else {
15305                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15306                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15307         }
15308
15309         dev->mode_config.fb_base = dev_priv->ggtt.mappable_base;
15310
15311         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15312                       INTEL_INFO(dev)->num_pipes,
15313                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15314
15315         for_each_pipe(dev_priv, pipe) {
15316                 intel_crtc_init(dev, pipe);
15317                 for_each_sprite(dev_priv, pipe, sprite) {
15318                         ret = intel_plane_init(dev, pipe, sprite);
15319                         if (ret)
15320                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15321                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15322                 }
15323         }
15324
15325         intel_update_czclk(dev_priv);
15326         intel_update_rawclk(dev_priv);
15327         intel_update_cdclk(dev);
15328
15329         intel_shared_dpll_init(dev);
15330
15331         /* Just disable it once at startup */
15332         i915_disable_vga(dev);
15333         intel_setup_outputs(dev);
15334
15335         drm_modeset_lock_all(dev);
15336         intel_modeset_setup_hw_state(dev);
15337         drm_modeset_unlock_all(dev);
15338
15339         for_each_intel_crtc(dev, crtc) {
15340                 struct intel_initial_plane_config plane_config = {};
15341
15342                 if (!crtc->active)
15343                         continue;
15344
15345                 /*
15346                  * Note that reserving the BIOS fb up front prevents us
15347                  * from stuffing other stolen allocations like the ring
15348                  * on top.  This prevents some ugliness at boot time, and
15349                  * can even allow for smooth boot transitions if the BIOS
15350                  * fb is large enough for the active pipe configuration.
15351                  */
15352                 dev_priv->display.get_initial_plane_config(crtc,
15353                                                            &plane_config);
15354
15355                 /*
15356                  * If the fb is shared between multiple heads, we'll
15357                  * just get the first one.
15358                  */
15359                 intel_find_initial_plane_obj(crtc, &plane_config);
15360         }
15361
15362         /*
15363          * Make sure hardware watermarks really match the state we read out.
15364          * Note that we need to do this after reconstructing the BIOS fb's
15365          * since the watermark calculation done here will use pstate->fb.
15366          */
15367         sanitize_watermarks(dev);
15368 }
15369
15370 static void intel_enable_pipe_a(struct drm_device *dev)
15371 {
15372         struct intel_connector *connector;
15373         struct drm_connector *crt = NULL;
15374         struct intel_load_detect_pipe load_detect_temp;
15375         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15376
15377         /* We can't just switch on the pipe A, we need to set things up with a
15378          * proper mode and output configuration. As a gross hack, enable pipe A
15379          * by enabling the load detect pipe once. */
15380         for_each_intel_connector(dev, connector) {
15381                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15382                         crt = &connector->base;
15383                         break;
15384                 }
15385         }
15386
15387         if (!crt)
15388                 return;
15389
15390         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15391                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15392 }
15393
15394 static bool
15395 intel_check_plane_mapping(struct intel_crtc *crtc)
15396 {
15397         struct drm_device *dev = crtc->base.dev;
15398         struct drm_i915_private *dev_priv = dev->dev_private;
15399         u32 val;
15400
15401         if (INTEL_INFO(dev)->num_pipes == 1)
15402                 return true;
15403
15404         val = I915_READ(DSPCNTR(!crtc->plane));
15405
15406         if ((val & DISPLAY_PLANE_ENABLE) &&
15407             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15408                 return false;
15409
15410         return true;
15411 }
15412
15413 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15414 {
15415         struct drm_device *dev = crtc->base.dev;
15416         struct intel_encoder *encoder;
15417
15418         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15419                 return true;
15420
15421         return false;
15422 }
15423
15424 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15425 {
15426         struct drm_device *dev = encoder->base.dev;
15427         struct intel_connector *connector;
15428
15429         for_each_connector_on_encoder(dev, &encoder->base, connector)
15430                 return true;
15431
15432         return false;
15433 }
15434
15435 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15436 {
15437         struct drm_device *dev = crtc->base.dev;
15438         struct drm_i915_private *dev_priv = dev->dev_private;
15439         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15440
15441         /* Clear any frame start delays used for debugging left by the BIOS */
15442         if (!transcoder_is_dsi(cpu_transcoder)) {
15443                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15444
15445                 I915_WRITE(reg,
15446                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15447         }
15448
15449         /* restore vblank interrupts to correct state */
15450         drm_crtc_vblank_reset(&crtc->base);
15451         if (crtc->active) {
15452                 struct intel_plane *plane;
15453
15454                 drm_crtc_vblank_on(&crtc->base);
15455
15456                 /* Disable everything but the primary plane */
15457                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15458                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15459                                 continue;
15460
15461                         plane->disable_plane(&plane->base, &crtc->base);
15462                 }
15463         }
15464
15465         /* We need to sanitize the plane -> pipe mapping first because this will
15466          * disable the crtc (and hence change the state) if it is wrong. Note
15467          * that gen4+ has a fixed plane -> pipe mapping.  */
15468         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15469                 bool plane;
15470
15471                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15472                               crtc->base.base.id);
15473
15474                 /* Pipe has the wrong plane attached and the plane is active.
15475                  * Temporarily change the plane mapping and disable everything
15476                  * ...  */
15477                 plane = crtc->plane;
15478                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15479                 crtc->plane = !plane;
15480                 intel_crtc_disable_noatomic(&crtc->base);
15481                 crtc->plane = plane;
15482         }
15483
15484         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15485             crtc->pipe == PIPE_A && !crtc->active) {
15486                 /* BIOS forgot to enable pipe A, this mostly happens after
15487                  * resume. Force-enable the pipe to fix this, the update_dpms
15488                  * call below we restore the pipe to the right state, but leave
15489                  * the required bits on. */
15490                 intel_enable_pipe_a(dev);
15491         }
15492
15493         /* Adjust the state of the output pipe according to whether we
15494          * have active connectors/encoders. */
15495         if (crtc->active && !intel_crtc_has_encoders(crtc))
15496                 intel_crtc_disable_noatomic(&crtc->base);
15497
15498         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15499                 /*
15500                  * We start out with underrun reporting disabled to avoid races.
15501                  * For correct bookkeeping mark this on active crtcs.
15502                  *
15503                  * Also on gmch platforms we dont have any hardware bits to
15504                  * disable the underrun reporting. Which means we need to start
15505                  * out with underrun reporting disabled also on inactive pipes,
15506                  * since otherwise we'll complain about the garbage we read when
15507                  * e.g. coming up after runtime pm.
15508                  *
15509                  * No protection against concurrent access is required - at
15510                  * worst a fifo underrun happens which also sets this to false.
15511                  */
15512                 crtc->cpu_fifo_underrun_disabled = true;
15513                 crtc->pch_fifo_underrun_disabled = true;
15514         }
15515 }
15516
15517 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15518 {
15519         struct intel_connector *connector;
15520         struct drm_device *dev = encoder->base.dev;
15521
15522         /* We need to check both for a crtc link (meaning that the
15523          * encoder is active and trying to read from a pipe) and the
15524          * pipe itself being active. */
15525         bool has_active_crtc = encoder->base.crtc &&
15526                 to_intel_crtc(encoder->base.crtc)->active;
15527
15528         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15529                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15530                               encoder->base.base.id,
15531                               encoder->base.name);
15532
15533                 /* Connector is active, but has no active pipe. This is
15534                  * fallout from our resume register restoring. Disable
15535                  * the encoder manually again. */
15536                 if (encoder->base.crtc) {
15537                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15538                                       encoder->base.base.id,
15539                                       encoder->base.name);
15540                         encoder->disable(encoder);
15541                         if (encoder->post_disable)
15542                                 encoder->post_disable(encoder);
15543                 }
15544                 encoder->base.crtc = NULL;
15545
15546                 /* Inconsistent output/port/pipe state happens presumably due to
15547                  * a bug in one of the get_hw_state functions. Or someplace else
15548                  * in our code, like the register restore mess on resume. Clamp
15549                  * things to off as a safer default. */
15550                 for_each_intel_connector(dev, connector) {
15551                         if (connector->encoder != encoder)
15552                                 continue;
15553                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15554                         connector->base.encoder = NULL;
15555                 }
15556         }
15557         /* Enabled encoders without active connectors will be fixed in
15558          * the crtc fixup. */
15559 }
15560
15561 void i915_redisable_vga_power_on(struct drm_device *dev)
15562 {
15563         struct drm_i915_private *dev_priv = dev->dev_private;
15564         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15565
15566         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15567                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15568                 i915_disable_vga(dev);
15569         }
15570 }
15571
15572 void i915_redisable_vga(struct drm_device *dev)
15573 {
15574         struct drm_i915_private *dev_priv = dev->dev_private;
15575
15576         /* This function can be called both from intel_modeset_setup_hw_state or
15577          * at a very early point in our resume sequence, where the power well
15578          * structures are not yet restored. Since this function is at a very
15579          * paranoid "someone might have enabled VGA while we were not looking"
15580          * level, just check if the power well is enabled instead of trying to
15581          * follow the "don't touch the power well if we don't need it" policy
15582          * the rest of the driver uses. */
15583         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15584                 return;
15585
15586         i915_redisable_vga_power_on(dev);
15587
15588         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15589 }
15590
15591 static bool primary_get_hw_state(struct intel_plane *plane)
15592 {
15593         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15594
15595         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15596 }
15597
15598 /* FIXME read out full plane state for all planes */
15599 static void readout_plane_state(struct intel_crtc *crtc)
15600 {
15601         struct drm_plane *primary = crtc->base.primary;
15602         struct intel_plane_state *plane_state =
15603                 to_intel_plane_state(primary->state);
15604
15605         plane_state->visible = crtc->active &&
15606                 primary_get_hw_state(to_intel_plane(primary));
15607
15608         if (plane_state->visible)
15609                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15610 }
15611
15612 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15613 {
15614         struct drm_i915_private *dev_priv = dev->dev_private;
15615         enum pipe pipe;
15616         struct intel_crtc *crtc;
15617         struct intel_encoder *encoder;
15618         struct intel_connector *connector;
15619         int i;
15620
15621         dev_priv->active_crtcs = 0;
15622
15623         for_each_intel_crtc(dev, crtc) {
15624                 struct intel_crtc_state *crtc_state = crtc->config;
15625                 int pixclk = 0;
15626
15627                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15628                 memset(crtc_state, 0, sizeof(*crtc_state));
15629                 crtc_state->base.crtc = &crtc->base;
15630
15631                 crtc_state->base.active = crtc_state->base.enable =
15632                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15633
15634                 crtc->base.enabled = crtc_state->base.enable;
15635                 crtc->active = crtc_state->base.active;
15636
15637                 if (crtc_state->base.active) {
15638                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15639
15640                         if (IS_BROADWELL(dev_priv)) {
15641                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15642
15643                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15644                                 if (crtc_state->ips_enabled)
15645                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15646                         } else if (IS_VALLEYVIEW(dev_priv) ||
15647                                    IS_CHERRYVIEW(dev_priv) ||
15648                                    IS_BROXTON(dev_priv))
15649                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15650                         else
15651                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15652                 }
15653
15654                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15655
15656                 readout_plane_state(crtc);
15657
15658                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15659                               crtc->base.base.id,
15660                               crtc->active ? "enabled" : "disabled");
15661         }
15662
15663         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15664                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15665
15666                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15667                                                   &pll->config.hw_state);
15668                 pll->config.crtc_mask = 0;
15669                 for_each_intel_crtc(dev, crtc) {
15670                         if (crtc->active && crtc->config->shared_dpll == pll)
15671                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15672                 }
15673                 pll->active_mask = pll->config.crtc_mask;
15674
15675                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15676                               pll->name, pll->config.crtc_mask, pll->on);
15677         }
15678
15679         for_each_intel_encoder(dev, encoder) {
15680                 pipe = 0;
15681
15682                 if (encoder->get_hw_state(encoder, &pipe)) {
15683                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15684                         encoder->base.crtc = &crtc->base;
15685                         encoder->get_config(encoder, crtc->config);
15686                 } else {
15687                         encoder->base.crtc = NULL;
15688                 }
15689
15690                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15691                               encoder->base.base.id,
15692                               encoder->base.name,
15693                               encoder->base.crtc ? "enabled" : "disabled",
15694                               pipe_name(pipe));
15695         }
15696
15697         for_each_intel_connector(dev, connector) {
15698                 if (connector->get_hw_state(connector)) {
15699                         connector->base.dpms = DRM_MODE_DPMS_ON;
15700
15701                         encoder = connector->encoder;
15702                         connector->base.encoder = &encoder->base;
15703
15704                         if (encoder->base.crtc &&
15705                             encoder->base.crtc->state->active) {
15706                                 /*
15707                                  * This has to be done during hardware readout
15708                                  * because anything calling .crtc_disable may
15709                                  * rely on the connector_mask being accurate.
15710                                  */
15711                                 encoder->base.crtc->state->connector_mask |=
15712                                         1 << drm_connector_index(&connector->base);
15713                                 encoder->base.crtc->state->encoder_mask |=
15714                                         1 << drm_encoder_index(&encoder->base);
15715                         }
15716
15717                 } else {
15718                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15719                         connector->base.encoder = NULL;
15720                 }
15721                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15722                               connector->base.base.id,
15723                               connector->base.name,
15724                               connector->base.encoder ? "enabled" : "disabled");
15725         }
15726
15727         for_each_intel_crtc(dev, crtc) {
15728                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15729
15730                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15731                 if (crtc->base.state->active) {
15732                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15733                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15734                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15735
15736                         /*
15737                          * The initial mode needs to be set in order to keep
15738                          * the atomic core happy. It wants a valid mode if the
15739                          * crtc's enabled, so we do the above call.
15740                          *
15741                          * At this point some state updated by the connectors
15742                          * in their ->detect() callback has not run yet, so
15743                          * no recalculation can be done yet.
15744                          *
15745                          * Even if we could do a recalculation and modeset
15746                          * right now it would cause a double modeset if
15747                          * fbdev or userspace chooses a different initial mode.
15748                          *
15749                          * If that happens, someone indicated they wanted a
15750                          * mode change, which means it's safe to do a full
15751                          * recalculation.
15752                          */
15753                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15754
15755                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15756                         update_scanline_offset(crtc);
15757                 }
15758
15759                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15760         }
15761 }
15762
15763 /* Scan out the current hw modeset state,
15764  * and sanitizes it to the current state
15765  */
15766 static void
15767 intel_modeset_setup_hw_state(struct drm_device *dev)
15768 {
15769         struct drm_i915_private *dev_priv = dev->dev_private;
15770         enum pipe pipe;
15771         struct intel_crtc *crtc;
15772         struct intel_encoder *encoder;
15773         int i;
15774
15775         intel_modeset_readout_hw_state(dev);
15776
15777         /* HW state is read out, now we need to sanitize this mess. */
15778         for_each_intel_encoder(dev, encoder) {
15779                 intel_sanitize_encoder(encoder);
15780         }
15781
15782         for_each_pipe(dev_priv, pipe) {
15783                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15784                 intel_sanitize_crtc(crtc);
15785                 intel_dump_pipe_config(crtc, crtc->config,
15786                                        "[setup_hw_state]");
15787         }
15788
15789         intel_modeset_update_connector_atomic_state(dev);
15790
15791         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15792                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15793
15794                 if (!pll->on || pll->active_mask)
15795                         continue;
15796
15797                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15798
15799                 pll->funcs.disable(dev_priv, pll);
15800                 pll->on = false;
15801         }
15802
15803         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15804                 vlv_wm_get_hw_state(dev);
15805         else if (IS_GEN9(dev))
15806                 skl_wm_get_hw_state(dev);
15807         else if (HAS_PCH_SPLIT(dev))
15808                 ilk_wm_get_hw_state(dev);
15809
15810         for_each_intel_crtc(dev, crtc) {
15811                 unsigned long put_domains;
15812
15813                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15814                 if (WARN_ON(put_domains))
15815                         modeset_put_power_domains(dev_priv, put_domains);
15816         }
15817         intel_display_set_init_power(dev_priv, false);
15818
15819         intel_fbc_init_pipe_state(dev_priv);
15820 }
15821
15822 void intel_display_resume(struct drm_device *dev)
15823 {
15824         struct drm_i915_private *dev_priv = to_i915(dev);
15825         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15826         struct drm_modeset_acquire_ctx ctx;
15827         int ret;
15828         bool setup = false;
15829
15830         dev_priv->modeset_restore_state = NULL;
15831
15832         /*
15833          * This is a cludge because with real atomic modeset mode_config.mutex
15834          * won't be taken. Unfortunately some probed state like
15835          * audio_codec_enable is still protected by mode_config.mutex, so lock
15836          * it here for now.
15837          */
15838         mutex_lock(&dev->mode_config.mutex);
15839         drm_modeset_acquire_init(&ctx, 0);
15840
15841 retry:
15842         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15843
15844         if (ret == 0 && !setup) {
15845                 setup = true;
15846
15847                 intel_modeset_setup_hw_state(dev);
15848                 i915_redisable_vga(dev);
15849         }
15850
15851         if (ret == 0 && state) {
15852                 struct drm_crtc_state *crtc_state;
15853                 struct drm_crtc *crtc;
15854                 int i;
15855
15856                 state->acquire_ctx = &ctx;
15857
15858                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15859                         /*
15860                          * Force recalculation even if we restore
15861                          * current state. With fast modeset this may not result
15862                          * in a modeset when the state is compatible.
15863                          */
15864                         crtc_state->mode_changed = true;
15865                 }
15866
15867                 ret = drm_atomic_commit(state);
15868         }
15869
15870         if (ret == -EDEADLK) {
15871                 drm_modeset_backoff(&ctx);
15872                 goto retry;
15873         }
15874
15875         drm_modeset_drop_locks(&ctx);
15876         drm_modeset_acquire_fini(&ctx);
15877         mutex_unlock(&dev->mode_config.mutex);
15878
15879         if (ret) {
15880                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15881                 drm_atomic_state_free(state);
15882         }
15883 }
15884
15885 void intel_modeset_gem_init(struct drm_device *dev)
15886 {
15887         struct drm_crtc *c;
15888         struct drm_i915_gem_object *obj;
15889         int ret;
15890
15891         intel_init_gt_powersave(dev);
15892
15893         intel_modeset_init_hw(dev);
15894
15895         intel_setup_overlay(dev);
15896
15897         /*
15898          * Make sure any fbs we allocated at startup are properly
15899          * pinned & fenced.  When we do the allocation it's too early
15900          * for this.
15901          */
15902         for_each_crtc(dev, c) {
15903                 obj = intel_fb_obj(c->primary->fb);
15904                 if (obj == NULL)
15905                         continue;
15906
15907                 mutex_lock(&dev->struct_mutex);
15908                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15909                                                  c->primary->state->rotation);
15910                 mutex_unlock(&dev->struct_mutex);
15911                 if (ret) {
15912                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15913                                   to_intel_crtc(c)->pipe);
15914                         drm_framebuffer_unreference(c->primary->fb);
15915                         c->primary->fb = NULL;
15916                         c->primary->crtc = c->primary->state->crtc = NULL;
15917                         update_state_fb(c->primary);
15918                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15919                 }
15920         }
15921
15922         intel_backlight_register(dev);
15923 }
15924
15925 void intel_connector_unregister(struct intel_connector *intel_connector)
15926 {
15927         struct drm_connector *connector = &intel_connector->base;
15928
15929         intel_panel_destroy_backlight(connector);
15930         drm_connector_unregister(connector);
15931 }
15932
15933 void intel_modeset_cleanup(struct drm_device *dev)
15934 {
15935         struct drm_i915_private *dev_priv = dev->dev_private;
15936         struct intel_connector *connector;
15937
15938         intel_disable_gt_powersave(dev);
15939
15940         intel_backlight_unregister(dev);
15941
15942         /*
15943          * Interrupts and polling as the first thing to avoid creating havoc.
15944          * Too much stuff here (turning of connectors, ...) would
15945          * experience fancy races otherwise.
15946          */
15947         intel_irq_uninstall(dev_priv);
15948
15949         /*
15950          * Due to the hpd irq storm handling the hotplug work can re-arm the
15951          * poll handlers. Hence disable polling after hpd handling is shut down.
15952          */
15953         drm_kms_helper_poll_fini(dev);
15954
15955         intel_unregister_dsm_handler();
15956
15957         intel_fbc_global_disable(dev_priv);
15958
15959         /* flush any delayed tasks or pending work */
15960         flush_scheduled_work();
15961
15962         /* destroy the backlight and sysfs files before encoders/connectors */
15963         for_each_intel_connector(dev, connector)
15964                 connector->unregister(connector);
15965
15966         drm_mode_config_cleanup(dev);
15967
15968         intel_cleanup_overlay(dev);
15969
15970         intel_cleanup_gt_powersave(dev);
15971
15972         intel_teardown_gmbus(dev);
15973 }
15974
15975 /*
15976  * Return which encoder is currently attached for connector.
15977  */
15978 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15979 {
15980         return &intel_attached_encoder(connector)->base;
15981 }
15982
15983 void intel_connector_attach_encoder(struct intel_connector *connector,
15984                                     struct intel_encoder *encoder)
15985 {
15986         connector->encoder = encoder;
15987         drm_mode_connector_attach_encoder(&connector->base,
15988                                           &encoder->base);
15989 }
15990
15991 /*
15992  * set vga decode state - true == enable VGA decode
15993  */
15994 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15995 {
15996         struct drm_i915_private *dev_priv = dev->dev_private;
15997         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15998         u16 gmch_ctrl;
15999
16000         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16001                 DRM_ERROR("failed to read control word\n");
16002                 return -EIO;
16003         }
16004
16005         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16006                 return 0;
16007
16008         if (state)
16009                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16010         else
16011                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16012
16013         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16014                 DRM_ERROR("failed to write control word\n");
16015                 return -EIO;
16016         }
16017
16018         return 0;
16019 }
16020
16021 struct intel_display_error_state {
16022
16023         u32 power_well_driver;
16024
16025         int num_transcoders;
16026
16027         struct intel_cursor_error_state {
16028                 u32 control;
16029                 u32 position;
16030                 u32 base;
16031                 u32 size;
16032         } cursor[I915_MAX_PIPES];
16033
16034         struct intel_pipe_error_state {
16035                 bool power_domain_on;
16036                 u32 source;
16037                 u32 stat;
16038         } pipe[I915_MAX_PIPES];
16039
16040         struct intel_plane_error_state {
16041                 u32 control;
16042                 u32 stride;
16043                 u32 size;
16044                 u32 pos;
16045                 u32 addr;
16046                 u32 surface;
16047                 u32 tile_offset;
16048         } plane[I915_MAX_PIPES];
16049
16050         struct intel_transcoder_error_state {
16051                 bool power_domain_on;
16052                 enum transcoder cpu_transcoder;
16053
16054                 u32 conf;
16055
16056                 u32 htotal;
16057                 u32 hblank;
16058                 u32 hsync;
16059                 u32 vtotal;
16060                 u32 vblank;
16061                 u32 vsync;
16062         } transcoder[4];
16063 };
16064
16065 struct intel_display_error_state *
16066 intel_display_capture_error_state(struct drm_device *dev)
16067 {
16068         struct drm_i915_private *dev_priv = dev->dev_private;
16069         struct intel_display_error_state *error;
16070         int transcoders[] = {
16071                 TRANSCODER_A,
16072                 TRANSCODER_B,
16073                 TRANSCODER_C,
16074                 TRANSCODER_EDP,
16075         };
16076         int i;
16077
16078         if (INTEL_INFO(dev)->num_pipes == 0)
16079                 return NULL;
16080
16081         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16082         if (error == NULL)
16083                 return NULL;
16084
16085         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16086                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16087
16088         for_each_pipe(dev_priv, i) {
16089                 error->pipe[i].power_domain_on =
16090                         __intel_display_power_is_enabled(dev_priv,
16091                                                          POWER_DOMAIN_PIPE(i));
16092                 if (!error->pipe[i].power_domain_on)
16093                         continue;
16094
16095                 error->cursor[i].control = I915_READ(CURCNTR(i));
16096                 error->cursor[i].position = I915_READ(CURPOS(i));
16097                 error->cursor[i].base = I915_READ(CURBASE(i));
16098
16099                 error->plane[i].control = I915_READ(DSPCNTR(i));
16100                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16101                 if (INTEL_INFO(dev)->gen <= 3) {
16102                         error->plane[i].size = I915_READ(DSPSIZE(i));
16103                         error->plane[i].pos = I915_READ(DSPPOS(i));
16104                 }
16105                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16106                         error->plane[i].addr = I915_READ(DSPADDR(i));
16107                 if (INTEL_INFO(dev)->gen >= 4) {
16108                         error->plane[i].surface = I915_READ(DSPSURF(i));
16109                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16110                 }
16111
16112                 error->pipe[i].source = I915_READ(PIPESRC(i));
16113
16114                 if (HAS_GMCH_DISPLAY(dev))
16115                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16116         }
16117
16118         /* Note: this does not include DSI transcoders. */
16119         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16120         if (HAS_DDI(dev_priv->dev))
16121                 error->num_transcoders++; /* Account for eDP. */
16122
16123         for (i = 0; i < error->num_transcoders; i++) {
16124                 enum transcoder cpu_transcoder = transcoders[i];
16125
16126                 error->transcoder[i].power_domain_on =
16127                         __intel_display_power_is_enabled(dev_priv,
16128                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16129                 if (!error->transcoder[i].power_domain_on)
16130                         continue;
16131
16132                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16133
16134                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16135                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16136                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16137                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16138                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16139                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16140                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16141         }
16142
16143         return error;
16144 }
16145
16146 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16147
16148 void
16149 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16150                                 struct drm_device *dev,
16151                                 struct intel_display_error_state *error)
16152 {
16153         struct drm_i915_private *dev_priv = dev->dev_private;
16154         int i;
16155
16156         if (!error)
16157                 return;
16158
16159         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16160         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16161                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16162                            error->power_well_driver);
16163         for_each_pipe(dev_priv, i) {
16164                 err_printf(m, "Pipe [%d]:\n", i);
16165                 err_printf(m, "  Power: %s\n",
16166                            onoff(error->pipe[i].power_domain_on));
16167                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16168                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16169
16170                 err_printf(m, "Plane [%d]:\n", i);
16171                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16172                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16173                 if (INTEL_INFO(dev)->gen <= 3) {
16174                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16175                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16176                 }
16177                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16178                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16179                 if (INTEL_INFO(dev)->gen >= 4) {
16180                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16181                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16182                 }
16183
16184                 err_printf(m, "Cursor [%d]:\n", i);
16185                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16186                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16187                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16188         }
16189
16190         for (i = 0; i < error->num_transcoders; i++) {
16191                 err_printf(m, "CPU transcoder: %s\n",
16192                            transcoder_name(error->transcoder[i].cpu_transcoder));
16193                 err_printf(m, "  Power: %s\n",
16194                            onoff(error->transcoder[i].power_domain_on));
16195                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16196                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16197                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16198                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16199                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16200                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16201                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16202         }
16203 }