drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 static int
 173 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 174 {
 175         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 176 }
 177
 178 static int
 179 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 180 {
 181         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 182                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 183 }
 184
 185 static int
 186 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 187 {
 188         uint32_t clkcfg;
 189
 190         /* hrawclock is 1/4 the FSB frequency */
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100000;
 195         case CLKCFG_FSB_533:
 196                 return 133333;
 197         case CLKCFG_FSB_667:
 198                 return 166667;
 199         case CLKCFG_FSB_800:
 200                 return 200000;
 201         case CLKCFG_FSB_1067:
 202                 return 266667;
 203         case CLKCFG_FSB_1333:
 204                 return 333333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400000;
 209         default:
 210                 return 133333;
 211         }
 212 }
 213
 214 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (HAS_PCH_SPLIT(dev_priv))
 217                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 218         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 219                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 220         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 221                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 222         else
 223                 return; /* no rawclk on other platforms, or no need to know it */
 224
 225         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 226 }
 227
 228 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 229 {
 230         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 231                 return;
 232
 233         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 234                                                       CCK_CZ_CLOCK_CONTROL);
 235
 236         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 237 }
 238
 239 static inline u32 /* units of 100MHz */
 240 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 241                     const struct intel_crtc_state *pipe_config)
 242 {
 243         if (HAS_DDI(dev_priv))
 244                 return pipe_config->port_clock; /* SPLL */
 245         else if (IS_GEN5(dev_priv))
 246                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 247         else
 248                 return 270000;
 249 }
 250
 251 static const intel_limit_t intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const intel_limit_t intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const intel_limit_t intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const intel_limit_t intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const intel_limit_t intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const intel_limit_t intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const intel_limit_t intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const intel_limit_t intel_limits_pineview_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const intel_limit_t intel_limits_ironlake_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const intel_limit_t intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const intel_limit_t intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const intel_limit_t intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 static bool
 517 needs_modeset(struct drm_crtc_state *state)
 518 {
 519         return drm_atomic_crtc_needs_modeset(state);
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe is of the specified type
 524  */
 525 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 526 {
 527         struct drm_device *dev = crtc->base.dev;
 528         struct intel_encoder *encoder;
 529
 530         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 531                 if (encoder->type == type)
 532                         return true;
 533
 534         return false;
 535 }
 536
 537 /**
 538  * Returns whether any output on the specified pipe will have the specified
 539  * type after a staged modeset is complete, i.e., the same as
 540  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 541  * encoder->crtc.
 542  */
 543 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 544                                       int type)
 545 {
 546         struct drm_atomic_state *state = crtc_state->base.state;
 547         struct drm_connector *connector;
 548         struct drm_connector_state *connector_state;
 549         struct intel_encoder *encoder;
 550         int i, num_connectors = 0;
 551
 552         for_each_connector_in_state(state, connector, connector_state, i) {
 553                 if (connector_state->crtc != crtc_state->base.crtc)
 554                         continue;
 555
 556                 num_connectors++;
 557
 558                 encoder = to_intel_encoder(connector_state->best_encoder);
 559                 if (encoder->type == type)
 560                         return true;
 561         }
 562
 563         WARN_ON(num_connectors == 0);
 564
 565         return false;
 566 }
 567
 568 static const intel_limit_t *
 569 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 570 {
 571         struct drm_device *dev = crtc_state->base.crtc->dev;
 572         const intel_limit_t *limit;
 573
 574         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 575                 if (intel_is_dual_link_lvds(dev)) {
 576                         if (refclk == 100000)
 577                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 578                         else
 579                                 limit = &intel_limits_ironlake_dual_lvds;
 580                 } else {
 581                         if (refclk == 100000)
 582                                 limit = &intel_limits_ironlake_single_lvds_100m;
 583                         else
 584                                 limit = &intel_limits_ironlake_single_lvds;
 585                 }
 586         } else
 587                 limit = &intel_limits_ironlake_dac;
 588
 589         return limit;
 590 }
 591
 592 static const intel_limit_t *
 593 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 594 {
 595         struct drm_device *dev = crtc_state->base.crtc->dev;
 596         const intel_limit_t *limit;
 597
 598         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 599                 if (intel_is_dual_link_lvds(dev))
 600                         limit = &intel_limits_g4x_dual_channel_lvds;
 601                 else
 602                         limit = &intel_limits_g4x_single_channel_lvds;
 603         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 604                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 605                 limit = &intel_limits_g4x_hdmi;
 606         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 607                 limit = &intel_limits_g4x_sdvo;
 608         } else /* The option is for other outputs */
 609                 limit = &intel_limits_i9xx_sdvo;
 610
 611         return limit;
 612 }
 613
 614 static const intel_limit_t *
 615 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 616 {
 617         struct drm_device *dev = crtc_state->base.crtc->dev;
 618         const intel_limit_t *limit;
 619
 620         if (IS_BROXTON(dev))
 621                 limit = &intel_limits_bxt;
 622         else if (HAS_PCH_SPLIT(dev))
 623                 limit = intel_ironlake_limit(crtc_state, refclk);
 624         else if (IS_G4X(dev)) {
 625                 limit = intel_g4x_limit(crtc_state);
 626         } else if (IS_PINEVIEW(dev)) {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_pineview_lvds;
 629                 else
 630                         limit = &intel_limits_pineview_sdvo;
 631         } else if (IS_CHERRYVIEW(dev)) {
 632                 limit = &intel_limits_chv;
 633         } else if (IS_VALLEYVIEW(dev)) {
 634                 limit = &intel_limits_vlv;
 635         } else if (!IS_GEN2(dev)) {
 636                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 637                         limit = &intel_limits_i9xx_lvds;
 638                 else
 639                         limit = &intel_limits_i9xx_sdvo;
 640         } else {
 641                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 642                         limit = &intel_limits_i8xx_lvds;
 643                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 644                         limit = &intel_limits_i8xx_dvo;
 645                 else
 646                         limit = &intel_limits_i8xx_dac;
 647         }
 648         return limit;
 649 }
 650
 651 /*
 652  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 653  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 654  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 655  * The helpers' return value is the rate of the clock that is fed to the
 656  * display engine's pipe which can be the above fast dot clock rate or a
 657  * divided-down version of it.
 658  */
 659 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 660 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 661 {
 662         clock->m = clock->m2 + 2;
 663         clock->p = clock->p1 * clock->p2;
 664         if (WARN_ON(clock->n == 0 || clock->p == 0))
 665                 return 0;
 666         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 667         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 668
 669         return clock->dot;
 670 }
 671
 672 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 673 {
 674         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 675 }
 676
 677 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 678 {
 679         clock->m = i9xx_dpll_compute_m(clock);
 680         clock->p = clock->p1 * clock->p2;
 681         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 682                 return 0;
 683         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 684         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 685
 686         return clock->dot;
 687 }
 688
 689 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 690 {
 691         clock->m = clock->m1 * clock->m2;
 692         clock->p = clock->p1 * clock->p2;
 693         if (WARN_ON(clock->n == 0 || clock->p == 0))
 694                 return 0;
 695         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 696         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 697
 698         return clock->dot / 5;
 699 }
 700
 701 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 702 {
 703         clock->m = clock->m1 * clock->m2;
 704         clock->p = clock->p1 * clock->p2;
 705         if (WARN_ON(clock->n == 0 || clock->p == 0))
 706                 return 0;
 707         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 708                         clock->n << 22);
 709         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 710
 711         return clock->dot / 5;
 712 }
 713
 714 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 715 /**
 716  * Returns whether the given set of divisors are valid for a given refclk with
 717  * the given connectors.
 718  */
 719
 720 static bool intel_PLL_is_valid(struct drm_device *dev,
 721                                const intel_limit_t *limit,
 722                                const intel_clock_t *clock)
 723 {
 724         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 725                 INTELPllInvalid("n out of range\n");
 726         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 727                 INTELPllInvalid("p1 out of range\n");
 728         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 729                 INTELPllInvalid("m2 out of range\n");
 730         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 731                 INTELPllInvalid("m1 out of range\n");
 732
 733         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 734             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 735                 if (clock->m1 <= clock->m2)
 736                         INTELPllInvalid("m1 <= m2\n");
 737
 738         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 739                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 740                         INTELPllInvalid("p out of range\n");
 741                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 742                         INTELPllInvalid("m out of range\n");
 743         }
 744
 745         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 746                 INTELPllInvalid("vco out of range\n");
 747         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 748          * connector, etc., rather than just a single range.
 749          */
 750         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 751                 INTELPllInvalid("dot out of range\n");
 752
 753         return true;
 754 }
 755
 756 static int
 757 i9xx_select_p2_div(const intel_limit_t *limit,
 758                    const struct intel_crtc_state *crtc_state,
 759                    int target)
 760 {
 761         struct drm_device *dev = crtc_state->base.crtc->dev;
 762
 763         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 764                 /*
 765                  * For LVDS just rely on its current settings for dual-channel.
 766                  * We haven't figured out how to reliably set up different
 767                  * single/dual channel state, if we even can.
 768                  */
 769                 if (intel_is_dual_link_lvds(dev))
 770                         return limit->p2.p2_fast;
 771                 else
 772                         return limit->p2.p2_slow;
 773         } else {
 774                 if (target < limit->p2.dot_limit)
 775                         return limit->p2.p2_slow;
 776                 else
 777                         return limit->p2.p2_fast;
 778         }
 779 }
 780
 781 static bool
 782 i9xx_find_best_dpll(const intel_limit_t *limit,
 783                     struct intel_crtc_state *crtc_state,
 784                     int target, int refclk, intel_clock_t *match_clock,
 785                     intel_clock_t *best_clock)
 786 {
 787         struct drm_device *dev = crtc_state->base.crtc->dev;
 788         intel_clock_t clock;
 789         int err = target;
 790
 791         memset(best_clock, 0, sizeof(*best_clock));
 792
 793         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 794
 795         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 796              clock.m1++) {
 797                 for (clock.m2 = limit->m2.min;
 798                      clock.m2 <= limit->m2.max; clock.m2++) {
 799                         if (clock.m2 >= clock.m1)
 800                                 break;
 801                         for (clock.n = limit->n.min;
 802                              clock.n <= limit->n.max; clock.n++) {
 803                                 for (clock.p1 = limit->p1.min;
 804                                         clock.p1 <= limit->p1.max; clock.p1++) {
 805                                         int this_err;
 806
 807                                         i9xx_calc_dpll_params(refclk, &clock);
 808                                         if (!intel_PLL_is_valid(dev, limit,
 809                                                                 &clock))
 810                                                 continue;
 811                                         if (match_clock &&
 812                                             clock.p != match_clock->p)
 813                                                 continue;
 814
 815                                         this_err = abs(clock.dot - target);
 816                                         if (this_err < err) {
 817                                                 *best_clock = clock;
 818                                                 err = this_err;
 819                                         }
 820                                 }
 821                         }
 822                 }
 823         }
 824
 825         return (err != target);
 826 }
 827
 828 static bool
 829 pnv_find_best_dpll(const intel_limit_t *limit,
 830                    struct intel_crtc_state *crtc_state,
 831                    int target, int refclk, intel_clock_t *match_clock,
 832                    intel_clock_t *best_clock)
 833 {
 834         struct drm_device *dev = crtc_state->base.crtc->dev;
 835         intel_clock_t clock;
 836         int err = target;
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         for (clock.n = limit->n.min;
 847                              clock.n <= limit->n.max; clock.n++) {
 848                                 for (clock.p1 = limit->p1.min;
 849                                         clock.p1 <= limit->p1.max; clock.p1++) {
 850                                         int this_err;
 851
 852                                         pnv_calc_dpll_params(refclk, &clock);
 853                                         if (!intel_PLL_is_valid(dev, limit,
 854                                                                 &clock))
 855                                                 continue;
 856                                         if (match_clock &&
 857                                             clock.p != match_clock->p)
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 g4x_find_best_dpll(const intel_limit_t *limit,
 875                    struct intel_crtc_state *crtc_state,
 876                    int target, int refclk, intel_clock_t *match_clock,
 877                    intel_clock_t *best_clock)
 878 {
 879         struct drm_device *dev = crtc_state->base.crtc->dev;
 880         intel_clock_t clock;
 881         int max_n;
 882         bool found = false;
 883         /* approximately equals target * 0.00585 */
 884         int err_most = (target >> 8) + (target >> 9);
 885
 886         memset(best_clock, 0, sizeof(*best_clock));
 887
 888         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 889
 890         max_n = limit->n.max;
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 893                 /* based on hardware requirement, prefere larger m1,m2 */
 894                 for (clock.m1 = limit->m1.max;
 895                      clock.m1 >= limit->m1.min; clock.m1--) {
 896                         for (clock.m2 = limit->m2.max;
 897                              clock.m2 >= limit->m2.min; clock.m2--) {
 898                                 for (clock.p1 = limit->p1.max;
 899                                      clock.p1 >= limit->p1.min; clock.p1--) {
 900                                         int this_err;
 901
 902                                         i9xx_calc_dpll_params(refclk, &clock);
 903                                         if (!intel_PLL_is_valid(dev, limit,
 904                                                                 &clock))
 905                                                 continue;
 906
 907                                         this_err = abs(clock.dot - target);
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918         return found;
 919 }
 920
 921 /*
 922  * Check if the calculated PLL configuration is more optimal compared to the
 923  * best configuration and error found so far. Return the calculated error.
 924  */
 925 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 926                                const intel_clock_t *calculated_clock,
 927                                const intel_clock_t *best_clock,
 928                                unsigned int best_error_ppm,
 929                                unsigned int *error_ppm)
 930 {
 931         /*
 932          * For CHV ignore the error and consider only the P value.
 933          * Prefer a bigger P value based on HW requirements.
 934          */
 935         if (IS_CHERRYVIEW(dev)) {
 936                 *error_ppm = 0;
 937
 938                 return calculated_clock->p > best_clock->p;
 939         }
 940
 941         if (WARN_ON_ONCE(!target_freq))
 942                 return false;
 943
 944         *error_ppm = div_u64(1000000ULL *
 945                                 abs(target_freq - calculated_clock->dot),
 946                              target_freq);
 947         /*
 948          * Prefer a better P value over a better (smaller) error if the error
 949          * is small. Ensure this preference for future configurations too by
 950          * setting the error to 0.
 951          */
 952         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 953                 *error_ppm = 0;
 954
 955                 return true;
 956         }
 957
 958         return *error_ppm + 10 < best_error_ppm;
 959 }
 960
 961 static bool
 962 vlv_find_best_dpll(const intel_limit_t *limit,
 963                    struct intel_crtc_state *crtc_state,
 964                    int target, int refclk, intel_clock_t *match_clock,
 965                    intel_clock_t *best_clock)
 966 {
 967         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 968         struct drm_device *dev = crtc->base.dev;
 969         intel_clock_t clock;
 970         unsigned int bestppm = 1000000;
 971         /* min update 19.2 MHz */
 972         int max_n = min(limit->n.max, refclk / 19200);
 973         bool found = false;
 974
 975         target *= 5; /* fast clock */
 976
 977         memset(best_clock, 0, sizeof(*best_clock));
 978
 979         /* based on hardware requirement, prefer smaller n to precision */
 980         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 981                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 982                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 983                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 984                                 clock.p = clock.p1 * clock.p2;
 985                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 986                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 987                                         unsigned int ppm;
 988
 989                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 990                                                                      refclk * clock.m1);
 991
 992                                         vlv_calc_dpll_params(refclk, &clock);
 993
 994                                         if (!intel_PLL_is_valid(dev, limit,
 995                                                                 &clock))
 996                                                 continue;
 997
 998                                         if (!vlv_PLL_is_optimal(dev, target,
 999                                                                 &clock,
1000                                                                 best_clock,
1001                                                                 bestppm, &ppm))
1002                                                 continue;
1003
1004                                         *best_clock = clock;
1005                                         bestppm = ppm;
1006                                         found = true;
1007                                 }
1008                         }
1009                 }
1010         }
1011
1012         return found;
1013 }
1014
1015 static bool
1016 chv_find_best_dpll(const intel_limit_t *limit,
1017                    struct intel_crtc_state *crtc_state,
1018                    int target, int refclk, intel_clock_t *match_clock,
1019                    intel_clock_t *best_clock)
1020 {
1021         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1022         struct drm_device *dev = crtc->base.dev;
1023         unsigned int best_error_ppm;
1024         intel_clock_t clock;
1025         uint64_t m2;
1026         int found = false;
1027
1028         memset(best_clock, 0, sizeof(*best_clock));
1029         best_error_ppm = 1000000;
1030
1031         /*
1032          * Based on hardware doc, the n always set to 1, and m1 always
1033          * set to 2.  If requires to support 200Mhz refclk, we need to
1034          * revisit this because n may not 1 anymore.
1035          */
1036         clock.n = 1, clock.m1 = 2;
1037         target *= 5;    /* fast clock */
1038
1039         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1040                 for (clock.p2 = limit->p2.p2_fast;
1041                                 clock.p2 >= limit->p2.p2_slow;
1042                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1043                         unsigned int error_ppm;
1044
1045                         clock.p = clock.p1 * clock.p2;
1046
1047                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1048                                         clock.n) << 22, refclk * clock.m1);
1049
1050                         if (m2 > INT_MAX/clock.m1)
1051                                 continue;
1052
1053                         clock.m2 = m2;
1054
1055                         chv_calc_dpll_params(refclk, &clock);
1056
1057                         if (!intel_PLL_is_valid(dev, limit, &clock))
1058                                 continue;
1059
1060                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1061                                                 best_error_ppm, &error_ppm))
1062                                 continue;
1063
1064                         *best_clock = clock;
1065                         best_error_ppm = error_ppm;
1066                         found = true;
1067                 }
1068         }
1069
1070         return found;
1071 }
1072
1073 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1074                         intel_clock_t *best_clock)
1075 {
1076         int refclk = i9xx_get_refclk(crtc_state, 0);
1077
1078         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1079                                   target_clock, refclk, NULL, best_clock);
1080 }
1081
1082 bool intel_crtc_active(struct drm_crtc *crtc)
1083 {
1084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1085
1086         /* Be paranoid as we can arrive here with only partial
1087          * state retrieved from the hardware during setup.
1088          *
1089          * We can ditch the adjusted_mode.crtc_clock check as soon
1090          * as Haswell has gained clock readout/fastboot support.
1091          *
1092          * We can ditch the crtc->primary->fb check as soon as we can
1093          * properly reconstruct framebuffers.
1094          *
1095          * FIXME: The intel_crtc->active here should be switched to
1096          * crtc->state->active once we have proper CRTC states wired up
1097          * for atomic.
1098          */
1099         return intel_crtc->active && crtc->primary->state->fb &&
1100                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1101 }
1102
1103 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1104                                              enum pipe pipe)
1105 {
1106         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1108
1109         return intel_crtc->config->cpu_transcoder;
1110 }
1111
1112 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         i915_reg_t reg = PIPEDSL(pipe);
1116         u32 line1, line2;
1117         u32 line_mask;
1118
1119         if (IS_GEN2(dev))
1120                 line_mask = DSL_LINEMASK_GEN2;
1121         else
1122                 line_mask = DSL_LINEMASK_GEN3;
1123
1124         line1 = I915_READ(reg) & line_mask;
1125         msleep(5);
1126         line2 = I915_READ(reg) & line_mask;
1127
1128         return line1 == line2;
1129 }
1130
1131 /*
1132  * intel_wait_for_pipe_off - wait for pipe to turn off
1133  * @crtc: crtc whose pipe to wait for
1134  *
1135  * After disabling a pipe, we can't wait for vblank in the usual way,
1136  * spinning on the vblank interrupt status bit, since we won't actually
1137  * see an interrupt when the pipe is disabled.
1138  *
1139  * On Gen4 and above:
1140  *   wait for the pipe register state bit to turn off
1141  *
1142  * Otherwise:
1143  *   wait for the display line value to settle (it usually
1144  *   ends up stopping at the start of the next frame).
1145  *
1146  */
1147 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1148 {
1149         struct drm_device *dev = crtc->base.dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1152         enum pipe pipe = crtc->pipe;
1153
1154         if (INTEL_INFO(dev)->gen >= 4) {
1155                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1156
1157                 /* Wait for the Pipe State to go off */
1158                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1159                              100))
1160                         WARN(1, "pipe_off wait timed out\n");
1161         } else {
1162                 /* Wait for the display line to settle */
1163                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1164                         WARN(1, "pipe_off wait timed out\n");
1165         }
1166 }
1167
1168 /* Only for pre-ILK configs */
1169 void assert_pll(struct drm_i915_private *dev_priv,
1170                 enum pipe pipe, bool state)
1171 {
1172         u32 val;
1173         bool cur_state;
1174
1175         val = I915_READ(DPLL(pipe));
1176         cur_state = !!(val & DPLL_VCO_ENABLE);
1177         I915_STATE_WARN(cur_state != state,
1178              "PLL state assertion failure (expected %s, current %s)\n",
1179                         onoff(state), onoff(cur_state));
1180 }
1181
1182 /* XXX: the dsi pll is shared between MIPI DSI ports */
1183 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1184 {
1185         u32 val;
1186         bool cur_state;
1187
1188         mutex_lock(&dev_priv->sb_lock);
1189         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1190         mutex_unlock(&dev_priv->sb_lock);
1191
1192         cur_state = val & DSI_PLL_VCO_EN;
1193         I915_STATE_WARN(cur_state != state,
1194              "DSI PLL state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1198 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1199
1200 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1201                           enum pipe pipe, bool state)
1202 {
1203         bool cur_state;
1204         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205                                                                       pipe);
1206
1207         if (HAS_DDI(dev_priv->dev)) {
1208                 /* DDI does not have a specific FDI_TX register */
1209                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1210                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1211         } else {
1212                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1213                 cur_state = !!(val & FDI_TX_ENABLE);
1214         }
1215         I915_STATE_WARN(cur_state != state,
1216              "FDI TX state assertion failure (expected %s, current %s)\n",
1217                         onoff(state), onoff(cur_state));
1218 }
1219 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1220 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1221
1222 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1223                           enum pipe pipe, bool state)
1224 {
1225         u32 val;
1226         bool cur_state;
1227
1228         val = I915_READ(FDI_RX_CTL(pipe));
1229         cur_state = !!(val & FDI_RX_ENABLE);
1230         I915_STATE_WARN(cur_state != state,
1231              "FDI RX state assertion failure (expected %s, current %s)\n",
1232                         onoff(state), onoff(cur_state));
1233 }
1234 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1235 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1236
1237 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1238                                       enum pipe pipe)
1239 {
1240         u32 val;
1241
1242         /* ILK FDI PLL is always enabled */
1243         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1244                 return;
1245
1246         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1247         if (HAS_DDI(dev_priv->dev))
1248                 return;
1249
1250         val = I915_READ(FDI_TX_CTL(pipe));
1251         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1252 }
1253
1254 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1255                        enum pipe pipe, bool state)
1256 {
1257         u32 val;
1258         bool cur_state;
1259
1260         val = I915_READ(FDI_RX_CTL(pipe));
1261         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1262         I915_STATE_WARN(cur_state != state,
1263              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1264                         onoff(state), onoff(cur_state));
1265 }
1266
1267 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1268                            enum pipe pipe)
1269 {
1270         struct drm_device *dev = dev_priv->dev;
1271         i915_reg_t pp_reg;
1272         u32 val;
1273         enum pipe panel_pipe = PIPE_A;
1274         bool locked = true;
1275
1276         if (WARN_ON(HAS_DDI(dev)))
1277                 return;
1278
1279         if (HAS_PCH_SPLIT(dev)) {
1280                 u32 port_sel;
1281
1282                 pp_reg = PCH_PP_CONTROL;
1283                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284
1285                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1286                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1287                         panel_pipe = PIPE_B;
1288                 /* XXX: else fix for eDP */
1289         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1290                 /* presumably write lock depends on pipe, not port select */
1291                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1292                 panel_pipe = pipe;
1293         } else {
1294                 pp_reg = PP_CONTROL;
1295                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1296                         panel_pipe = PIPE_B;
1297         }
1298
1299         val = I915_READ(pp_reg);
1300         if (!(val & PANEL_POWER_ON) ||
1301             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1302                 locked = false;
1303
1304         I915_STATE_WARN(panel_pipe == pipe && locked,
1305              "panel assertion failure, pipe %c regs locked\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static void assert_cursor(struct drm_i915_private *dev_priv,
1310                           enum pipe pipe, bool state)
1311 {
1312         struct drm_device *dev = dev_priv->dev;
1313         bool cur_state;
1314
1315         if (IS_845G(dev) || IS_I865G(dev))
1316                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1317         else
1318                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1319
1320         I915_STATE_WARN(cur_state != state,
1321              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1322                         pipe_name(pipe), onoff(state), onoff(cur_state));
1323 }
1324 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1325 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326
1327 void assert_pipe(struct drm_i915_private *dev_priv,
1328                  enum pipe pipe, bool state)
1329 {
1330         bool cur_state;
1331         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1332                                                                       pipe);
1333         enum intel_display_power_domain power_domain;
1334
1335         /* if we need the pipe quirk it must be always on */
1336         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338                 state = true;
1339
1340         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1341         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1342                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1343                 cur_state = !!(val & PIPECONF_ENABLE);
1344
1345                 intel_display_power_put(dev_priv, power_domain);
1346         } else {
1347                 cur_state = false;
1348         }
1349
1350         I915_STATE_WARN(cur_state != state,
1351              "pipe %c assertion failure (expected %s, current %s)\n",
1352                         pipe_name(pipe), onoff(state), onoff(cur_state));
1353 }
1354
1355 static void assert_plane(struct drm_i915_private *dev_priv,
1356                          enum plane plane, bool state)
1357 {
1358         u32 val;
1359         bool cur_state;
1360
1361         val = I915_READ(DSPCNTR(plane));
1362         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1363         I915_STATE_WARN(cur_state != state,
1364              "plane %c assertion failure (expected %s, current %s)\n",
1365                         plane_name(plane), onoff(state), onoff(cur_state));
1366 }
1367
1368 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1369 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1370
1371 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe)
1373 {
1374         struct drm_device *dev = dev_priv->dev;
1375         int i;
1376
1377         /* Primary planes are fixed to pipes on gen4+ */
1378         if (INTEL_INFO(dev)->gen >= 4) {
1379                 u32 val = I915_READ(DSPCNTR(pipe));
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 u32 val = I915_READ(DSPCNTR(i));
1389                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390                         DISPPLANE_SEL_PIPE_SHIFT;
1391                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393                      plane_name(i), pipe_name(pipe));
1394         }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398                                     enum pipe pipe)
1399 {
1400         struct drm_device *dev = dev_priv->dev;
1401         int sprite;
1402
1403         if (INTEL_INFO(dev)->gen >= 9) {
1404                 for_each_sprite(dev_priv, pipe, sprite) {
1405                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1406                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1407                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1408                              sprite, pipe_name(pipe));
1409                 }
1410         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1411                 for_each_sprite(dev_priv, pipe, sprite) {
1412                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1413                         I915_STATE_WARN(val & SP_ENABLE,
1414                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415                              sprite_name(pipe, sprite), pipe_name(pipe));
1416                 }
1417         } else if (INTEL_INFO(dev)->gen >= 7) {
1418                 u32 val = I915_READ(SPRCTL(pipe));
1419                 I915_STATE_WARN(val & SPRITE_ENABLE,
1420                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1421                      plane_name(pipe), pipe_name(pipe));
1422         } else if (INTEL_INFO(dev)->gen >= 5) {
1423                 u32 val = I915_READ(DVSCNTR(pipe));
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1437                                     enum pipe pipe)
1438 {
1439         u32 val;
1440         bool enabled;
1441
1442         val = I915_READ(PCH_TRANSCONF(pipe));
1443         enabled = !!(val & TRANS_ENABLE);
1444         I915_STATE_WARN(enabled,
1445              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1446              pipe_name(pipe));
1447 }
1448
1449 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1450                             enum pipe pipe, u32 port_sel, u32 val)
1451 {
1452         if ((val & DP_PORT_EN) == 0)
1453                 return false;
1454
1455         if (HAS_PCH_CPT(dev_priv->dev)) {
1456                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1457                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1458                         return false;
1459         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1460                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1461                         return false;
1462         } else {
1463                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1464                         return false;
1465         }
1466         return true;
1467 }
1468
1469 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1470                               enum pipe pipe, u32 val)
1471 {
1472         if ((val & SDVO_ENABLE) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1477                         return false;
1478         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1479                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1480                         return false;
1481         } else {
1482                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1483                         return false;
1484         }
1485         return true;
1486 }
1487
1488 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1489                               enum pipe pipe, u32 val)
1490 {
1491         if ((val & LVDS_PORT_EN) == 0)
1492                 return false;
1493
1494         if (HAS_PCH_CPT(dev_priv->dev)) {
1495                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & ADPA_DAC_ENABLE) == 0)
1508                 return false;
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511                         return false;
1512         } else {
1513                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1514                         return false;
1515         }
1516         return true;
1517 }
1518
1519 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1520                                    enum pipe pipe, i915_reg_t reg,
1521                                    u32 port_sel)
1522 {
1523         u32 val = I915_READ(reg);
1524         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1525              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1526              i915_mmio_reg_offset(reg), pipe_name(pipe));
1527
1528         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1529              && (val & DP_PIPEB_SELECT),
1530              "IBX PCH dp port still using transcoder B\n");
1531 }
1532
1533 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1534                                      enum pipe pipe, i915_reg_t reg)
1535 {
1536         u32 val = I915_READ(reg);
1537         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1538              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1539              i915_mmio_reg_offset(reg), pipe_name(pipe));
1540
1541         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1542              && (val & SDVO_PIPE_B_SELECT),
1543              "IBX PCH hdmi port still using transcoder B\n");
1544 }
1545
1546 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1547                                       enum pipe pipe)
1548 {
1549         u32 val;
1550
1551         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1552         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1553         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1554
1555         val = I915_READ(PCH_ADPA);
1556         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1557              "PCH VGA enabled on transcoder %c, should be disabled\n",
1558              pipe_name(pipe));
1559
1560         val = I915_READ(PCH_LVDS);
1561         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1562              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1563              pipe_name(pipe));
1564
1565         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1566         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1567         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1568 }
1569
1570 static void vlv_enable_pll(struct intel_crtc *crtc,
1571                            const struct intel_crtc_state *pipe_config)
1572 {
1573         struct drm_device *dev = crtc->base.dev;
1574         struct drm_i915_private *dev_priv = dev->dev_private;
1575         i915_reg_t reg = DPLL(crtc->pipe);
1576         u32 dpll = pipe_config->dpll_hw_state.dpll;
1577
1578         assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580         /* PLL is protected by panel, make sure we can write it */
1581         if (IS_MOBILE(dev_priv->dev))
1582                 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584         I915_WRITE(reg, dpll);
1585         POSTING_READ(reg);
1586         udelay(150);
1587
1588         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1589                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1590
1591         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1592         POSTING_READ(DPLL_MD(crtc->pipe));
1593
1594         /* We do this three times for luck */
1595         I915_WRITE(reg, dpll);
1596         POSTING_READ(reg);
1597         udelay(150); /* wait for warmup */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604 }
1605
1606 static void chv_enable_pll(struct intel_crtc *crtc,
1607                            const struct intel_crtc_state *pipe_config)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int pipe = crtc->pipe;
1612         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1613         u32 tmp;
1614
1615         assert_pipe_disabled(dev_priv, crtc->pipe);
1616
1617         mutex_lock(&dev_priv->sb_lock);
1618
1619         /* Enable back the 10bit clock to display controller */
1620         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1621         tmp |= DPIO_DCLKP_EN;
1622         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1623
1624         mutex_unlock(&dev_priv->sb_lock);
1625
1626         /*
1627          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1628          */
1629         udelay(1);
1630
1631         /* Enable PLL */
1632         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1633
1634         /* Check PLL is locked */
1635         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1636                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1637
1638         /* not sure when this should be written */
1639         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640         POSTING_READ(DPLL_MD(pipe));
1641 }
1642
1643 static int intel_num_dvo_pipes(struct drm_device *dev)
1644 {
1645         struct intel_crtc *crtc;
1646         int count = 0;
1647
1648         for_each_intel_crtc(dev, crtc)
1649                 count += crtc->base.state->active &&
1650                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1651
1652         return count;
1653 }
1654
1655 static void i9xx_enable_pll(struct intel_crtc *crtc)
1656 {
1657         struct drm_device *dev = crtc->base.dev;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659         i915_reg_t reg = DPLL(crtc->pipe);
1660         u32 dpll = crtc->config->dpll_hw_state.dpll;
1661
1662         assert_pipe_disabled(dev_priv, crtc->pipe);
1663
1664         /* No really, not for ILK+ */
1665         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1666
1667         /* PLL is protected by panel, make sure we can write it */
1668         if (IS_MOBILE(dev) && !IS_I830(dev))
1669                 assert_panel_unlocked(dev_priv, crtc->pipe);
1670
1671         /* Enable DVO 2x clock on both PLLs if necessary */
1672         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1673                 /*
1674                  * It appears to be important that we don't enable this
1675                  * for the current pipe before otherwise configuring the
1676                  * PLL. No idea how this should be handled if multiple
1677                  * DVO outputs are enabled simultaneosly.
1678                  */
1679                 dpll |= DPLL_DVO_2X_MODE;
1680                 I915_WRITE(DPLL(!crtc->pipe),
1681                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1682         }
1683
1684         /*
1685          * Apparently we need to have VGA mode enabled prior to changing
1686          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1687          * dividers, even though the register value does change.
1688          */
1689         I915_WRITE(reg, 0);
1690
1691         I915_WRITE(reg, dpll);
1692
1693         /* Wait for the clocks to stabilize. */
1694         POSTING_READ(reg);
1695         udelay(150);
1696
1697         if (INTEL_INFO(dev)->gen >= 4) {
1698                 I915_WRITE(DPLL_MD(crtc->pipe),
1699                            crtc->config->dpll_hw_state.dpll_md);
1700         } else {
1701                 /* The pixel multiplier can only be updated once the
1702                  * DPLL is enabled and the clocks are stable.
1703                  *
1704                  * So write it again.
1705                  */
1706                 I915_WRITE(reg, dpll);
1707         }
1708
1709         /* We do this three times for luck */
1710         I915_WRITE(reg, dpll);
1711         POSTING_READ(reg);
1712         udelay(150); /* wait for warmup */
1713         I915_WRITE(reg, dpll);
1714         POSTING_READ(reg);
1715         udelay(150); /* wait for warmup */
1716         I915_WRITE(reg, dpll);
1717         POSTING_READ(reg);
1718         udelay(150); /* wait for warmup */
1719 }
1720
1721 /**
1722  * i9xx_disable_pll - disable a PLL
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe PLL to disable
1725  *
1726  * Disable the PLL for @pipe, making sure the pipe is off first.
1727  *
1728  * Note!  This is for pre-ILK only.
1729  */
1730 static void i9xx_disable_pll(struct intel_crtc *crtc)
1731 {
1732         struct drm_device *dev = crtc->base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         enum pipe pipe = crtc->pipe;
1735
1736         /* Disable DVO 2x clock on both PLLs if necessary */
1737         if (IS_I830(dev) &&
1738             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1739             !intel_num_dvo_pipes(dev)) {
1740                 I915_WRITE(DPLL(PIPE_B),
1741                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1742                 I915_WRITE(DPLL(PIPE_A),
1743                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1744         }
1745
1746         /* Don't disable pipe or pipe PLLs if needed */
1747         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1748             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1749                 return;
1750
1751         /* Make sure the pipe isn't still relying on us */
1752         assert_pipe_disabled(dev_priv, pipe);
1753
1754         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1755         POSTING_READ(DPLL(pipe));
1756 }
1757
1758 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1759 {
1760         u32 val;
1761
1762         /* Make sure the pipe isn't still relying on us */
1763         assert_pipe_disabled(dev_priv, pipe);
1764
1765         /*
1766          * Leave integrated clock source and reference clock enabled for pipe B.
1767          * The latter is needed for VGA hotplug / manual detection.
1768          */
1769         val = DPLL_VGA_MODE_DIS;
1770         if (pipe == PIPE_B)
1771                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1772         I915_WRITE(DPLL(pipe), val);
1773         POSTING_READ(DPLL(pipe));
1774
1775 }
1776
1777 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1778 {
1779         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1780         u32 val;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         /* Set PLL en = 0 */
1786         val = DPLL_SSC_REF_CLK_CHV |
1787                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1788         if (pipe != PIPE_A)
1789                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1790         I915_WRITE(DPLL(pipe), val);
1791         POSTING_READ(DPLL(pipe));
1792
1793         mutex_lock(&dev_priv->sb_lock);
1794
1795         /* Disable 10bit clock to display controller */
1796         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1797         val &= ~DPIO_DCLKP_EN;
1798         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1799
1800         mutex_unlock(&dev_priv->sb_lock);
1801 }
1802
1803 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1804                          struct intel_digital_port *dport,
1805                          unsigned int expected_mask)
1806 {
1807         u32 port_mask;
1808         i915_reg_t dpll_reg;
1809
1810         switch (dport->port) {
1811         case PORT_B:
1812                 port_mask = DPLL_PORTB_READY_MASK;
1813                 dpll_reg = DPLL(0);
1814                 break;
1815         case PORT_C:
1816                 port_mask = DPLL_PORTC_READY_MASK;
1817                 dpll_reg = DPLL(0);
1818                 expected_mask <<= 4;
1819                 break;
1820         case PORT_D:
1821                 port_mask = DPLL_PORTD_READY_MASK;
1822                 dpll_reg = DPIO_PHY_STATUS;
1823                 break;
1824         default:
1825                 BUG();
1826         }
1827
1828         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1829                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1830                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1831 }
1832
1833 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834                                            enum pipe pipe)
1835 {
1836         struct drm_device *dev = dev_priv->dev;
1837         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839         i915_reg_t reg;
1840         uint32_t val, pipeconf_val;
1841
1842         /* PCH only available on ILK+ */
1843         BUG_ON(!HAS_PCH_SPLIT(dev));
1844
1845         /* Make sure PCH DPLL is enabled */
1846         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1847
1848         /* FDI must be feeding us bits for PCH ports */
1849         assert_fdi_tx_enabled(dev_priv, pipe);
1850         assert_fdi_rx_enabled(dev_priv, pipe);
1851
1852         if (HAS_PCH_CPT(dev)) {
1853                 /* Workaround: Set the timing override bit before enabling the
1854                  * pch transcoder. */
1855                 reg = TRANS_CHICKEN2(pipe);
1856                 val = I915_READ(reg);
1857                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858                 I915_WRITE(reg, val);
1859         }
1860
1861         reg = PCH_TRANSCONF(pipe);
1862         val = I915_READ(reg);
1863         pipeconf_val = I915_READ(PIPECONF(pipe));
1864
1865         if (HAS_PCH_IBX(dev_priv->dev)) {
1866                 /*
1867                  * Make the BPC in transcoder be consistent with
1868                  * that in pipeconf reg. For HDMI we must use 8bpc
1869                  * here for both 8bpc and 12bpc.
1870                  */
1871                 val &= ~PIPECONF_BPC_MASK;
1872                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1873                         val |= PIPECONF_8BPC;
1874                 else
1875                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1876         }
1877
1878         val &= ~TRANS_INTERLACE_MASK;
1879         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1880                 if (HAS_PCH_IBX(dev_priv->dev) &&
1881                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1882                         val |= TRANS_LEGACY_INTERLACED_ILK;
1883                 else
1884                         val |= TRANS_INTERLACED;
1885         else
1886                 val |= TRANS_PROGRESSIVE;
1887
1888         I915_WRITE(reg, val | TRANS_ENABLE);
1889         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1890                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1891 }
1892
1893 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1894                                       enum transcoder cpu_transcoder)
1895 {
1896         u32 val, pipeconf_val;
1897
1898         /* PCH only available on ILK+ */
1899         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1900
1901         /* FDI must be feeding us bits for PCH ports */
1902         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1903         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1904
1905         /* Workaround: set timing override bit. */
1906         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1907         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1908         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1909
1910         val = TRANS_ENABLE;
1911         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1912
1913         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1914             PIPECONF_INTERLACED_ILK)
1915                 val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(LPT_TRANSCONF, val);
1920         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("Failed to enable PCH transcoder\n");
1922 }
1923
1924 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                             enum pipe pipe)
1926 {
1927         struct drm_device *dev = dev_priv->dev;
1928         i915_reg_t reg;
1929         uint32_t val;
1930
1931         /* FDI relies on the transcoder */
1932         assert_fdi_tx_disabled(dev_priv, pipe);
1933         assert_fdi_rx_disabled(dev_priv, pipe);
1934
1935         /* Ports must be off as well */
1936         assert_pch_ports_disabled(dev_priv, pipe);
1937
1938         reg = PCH_TRANSCONF(pipe);
1939         val = I915_READ(reg);
1940         val &= ~TRANS_ENABLE;
1941         I915_WRITE(reg, val);
1942         /* wait for PCH transcoder off, transcoder state */
1943         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1944                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1945
1946         if (HAS_PCH_CPT(dev)) {
1947                 /* Workaround: Clear the timing override chicken bit again. */
1948                 reg = TRANS_CHICKEN2(pipe);
1949                 val = I915_READ(reg);
1950                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951                 I915_WRITE(reg, val);
1952         }
1953 }
1954
1955 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1956 {
1957         u32 val;
1958
1959         val = I915_READ(LPT_TRANSCONF);
1960         val &= ~TRANS_ENABLE;
1961         I915_WRITE(LPT_TRANSCONF, val);
1962         /* wait for PCH transcoder off, transcoder state */
1963         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1964                 DRM_ERROR("Failed to disable PCH transcoder\n");
1965
1966         /* Workaround: clear timing override bit. */
1967         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1968         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1969         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1970 }
1971
1972 /**
1973  * intel_enable_pipe - enable a pipe, asserting requirements
1974  * @crtc: crtc responsible for the pipe
1975  *
1976  * Enable @crtc's pipe, making sure that various hardware specific requirements
1977  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1978  */
1979 static void intel_enable_pipe(struct intel_crtc *crtc)
1980 {
1981         struct drm_device *dev = crtc->base.dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         enum pipe pipe = crtc->pipe;
1984         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1985         enum pipe pch_transcoder;
1986         i915_reg_t reg;
1987         u32 val;
1988
1989         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1990
1991         assert_planes_disabled(dev_priv, pipe);
1992         assert_cursor_disabled(dev_priv, pipe);
1993         assert_sprites_disabled(dev_priv, pipe);
1994
1995         if (HAS_PCH_LPT(dev_priv->dev))
1996                 pch_transcoder = TRANSCODER_A;
1997         else
1998                 pch_transcoder = pipe;
1999
2000         /*
2001          * A pipe without a PLL won't actually be able to drive bits from
2002          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2003          * need the check.
2004          */
2005         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2006                 if (crtc->config->has_dsi_encoder)
2007                         assert_dsi_pll_enabled(dev_priv);
2008                 else
2009                         assert_pll_enabled(dev_priv, pipe);
2010         else {
2011                 if (crtc->config->has_pch_encoder) {
2012                         /* if driving the PCH, we need FDI enabled */
2013                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2014                         assert_fdi_tx_pll_enabled(dev_priv,
2015                                                   (enum pipe) cpu_transcoder);
2016                 }
2017                 /* FIXME: assert CPU port conditions for SNB+ */
2018         }
2019
2020         reg = PIPECONF(cpu_transcoder);
2021         val = I915_READ(reg);
2022         if (val & PIPECONF_ENABLE) {
2023                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2024                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2025                 return;
2026         }
2027
2028         I915_WRITE(reg, val | PIPECONF_ENABLE);
2029         POSTING_READ(reg);
2030
2031         /*
2032          * Until the pipe starts DSL will read as 0, which would cause
2033          * an apparent vblank timestamp jump, which messes up also the
2034          * frame count when it's derived from the timestamps. So let's
2035          * wait for the pipe to start properly before we call
2036          * drm_crtc_vblank_on()
2037          */
2038         if (dev->max_vblank_count == 0 &&
2039             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2040                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2041 }
2042
2043 /**
2044  * intel_disable_pipe - disable a pipe, asserting requirements
2045  * @crtc: crtc whose pipes is to be disabled
2046  *
2047  * Disable the pipe of @crtc, making sure that various hardware
2048  * specific requirements are met, if applicable, e.g. plane
2049  * disabled, panel fitter off, etc.
2050  *
2051  * Will wait until the pipe has shut down before returning.
2052  */
2053 static void intel_disable_pipe(struct intel_crtc *crtc)
2054 {
2055         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2056         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2057         enum pipe pipe = crtc->pipe;
2058         i915_reg_t reg;
2059         u32 val;
2060
2061         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2062
2063         /*
2064          * Make sure planes won't keep trying to pump pixels to us,
2065          * or we might hang the display.
2066          */
2067         assert_planes_disabled(dev_priv, pipe);
2068         assert_cursor_disabled(dev_priv, pipe);
2069         assert_sprites_disabled(dev_priv, pipe);
2070
2071         reg = PIPECONF(cpu_transcoder);
2072         val = I915_READ(reg);
2073         if ((val & PIPECONF_ENABLE) == 0)
2074                 return;
2075
2076         /*
2077          * Double wide has implications for planes
2078          * so best keep it disabled when not needed.
2079          */
2080         if (crtc->config->double_wide)
2081                 val &= ~PIPECONF_DOUBLE_WIDE;
2082
2083         /* Don't disable pipe or pipe PLLs if needed */
2084         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2085             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2086                 val &= ~PIPECONF_ENABLE;
2087
2088         I915_WRITE(reg, val);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 intel_wait_for_pipe_off(crtc);
2091 }
2092
2093 static bool need_vtd_wa(struct drm_device *dev)
2094 {
2095 #ifdef CONFIG_INTEL_IOMMU
2096         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2097                 return true;
2098 #endif
2099         return false;
2100 }
2101
2102 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2103 {
2104         return IS_GEN2(dev_priv) ? 2048 : 4096;
2105 }
2106
2107 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2108                                            uint64_t fb_modifier, unsigned int cpp)
2109 {
2110         switch (fb_modifier) {
2111         case DRM_FORMAT_MOD_NONE:
2112                 return cpp;
2113         case I915_FORMAT_MOD_X_TILED:
2114                 if (IS_GEN2(dev_priv))
2115                         return 128;
2116                 else
2117                         return 512;
2118         case I915_FORMAT_MOD_Y_TILED:
2119                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2120                         return 128;
2121                 else
2122                         return 512;
2123         case I915_FORMAT_MOD_Yf_TILED:
2124                 switch (cpp) {
2125                 case 1:
2126                         return 64;
2127                 case 2:
2128                 case 4:
2129                         return 128;
2130                 case 8:
2131                 case 16:
2132                         return 256;
2133                 default:
2134                         MISSING_CASE(cpp);
2135                         return cpp;
2136                 }
2137                 break;
2138         default:
2139                 MISSING_CASE(fb_modifier);
2140                 return cpp;
2141         }
2142 }
2143
2144 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2145                                uint64_t fb_modifier, unsigned int cpp)
2146 {
2147         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2148                 return 1;
2149         else
2150                 return intel_tile_size(dev_priv) /
2151                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2152 }
2153
2154 /* Return the tile dimensions in pixel units */
2155 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2156                             unsigned int *tile_width,
2157                             unsigned int *tile_height,
2158                             uint64_t fb_modifier,
2159                             unsigned int cpp)
2160 {
2161         unsigned int tile_width_bytes =
2162                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2163
2164         *tile_width = tile_width_bytes / cpp;
2165         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2166 }
2167
2168 unsigned int
2169 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2170                       uint32_t pixel_format, uint64_t fb_modifier)
2171 {
2172         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2173         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2174
2175         return ALIGN(height, tile_height);
2176 }
2177
2178 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2179 {
2180         unsigned int size = 0;
2181         int i;
2182
2183         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2184                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2185
2186         return size;
2187 }
2188
2189 static void
2190 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2191                         const struct drm_framebuffer *fb,
2192                         unsigned int rotation)
2193 {
2194         if (intel_rotation_90_or_270(rotation)) {
2195                 *view = i915_ggtt_view_rotated;
2196                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2197         } else {
2198                 *view = i915_ggtt_view_normal;
2199         }
2200 }
2201
2202 static void
2203 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2204                    struct drm_framebuffer *fb)
2205 {
2206         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2207         unsigned int tile_size, tile_width, tile_height, cpp;
2208
2209         tile_size = intel_tile_size(dev_priv);
2210
2211         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2212         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2213                         fb->modifier[0], cpp);
2214
2215         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2216         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2217
2218         if (info->pixel_format == DRM_FORMAT_NV12) {
2219                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2220                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2221                                 fb->modifier[1], cpp);
2222
2223                 info->uv_offset = fb->offsets[1];
2224                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2225                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2226         }
2227 }
2228
2229 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2230 {
2231         if (INTEL_INFO(dev_priv)->gen >= 9)
2232                 return 256 * 1024;
2233         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2234                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2235                 return 128 * 1024;
2236         else if (INTEL_INFO(dev_priv)->gen >= 4)
2237                 return 4 * 1024;
2238         else
2239                 return 0;
2240 }
2241
2242 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2243                                          uint64_t fb_modifier)
2244 {
2245         switch (fb_modifier) {
2246         case DRM_FORMAT_MOD_NONE:
2247                 return intel_linear_alignment(dev_priv);
2248         case I915_FORMAT_MOD_X_TILED:
2249                 if (INTEL_INFO(dev_priv)->gen >= 9)
2250                         return 256 * 1024;
2251                 return 0;
2252         case I915_FORMAT_MOD_Y_TILED:
2253         case I915_FORMAT_MOD_Yf_TILED:
2254                 return 1 * 1024 * 1024;
2255         default:
2256                 MISSING_CASE(fb_modifier);
2257                 return 0;
2258         }
2259 }
2260
2261 int
2262 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2263                            unsigned int rotation)
2264 {
2265         struct drm_device *dev = fb->dev;
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2268         struct i915_ggtt_view view;
2269         u32 alignment;
2270         int ret;
2271
2272         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2273
2274         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2275
2276         intel_fill_fb_ggtt_view(&view, fb, rotation);
2277
2278         /* Note that the w/a also requires 64 PTE of padding following the
2279          * bo. We currently fill all unused PTE with the shadow page and so
2280          * we should always have valid PTE following the scanout preventing
2281          * the VT-d warning.
2282          */
2283         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2284                 alignment = 256 * 1024;
2285
2286         /*
2287          * Global gtt pte registers are special registers which actually forward
2288          * writes to a chunk of system memory. Which means that there is no risk
2289          * that the register values disappear as soon as we call
2290          * intel_runtime_pm_put(), so it is correct to wrap only the
2291          * pin/unpin/fence and not more.
2292          */
2293         intel_runtime_pm_get(dev_priv);
2294
2295         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2296                                                    &view);
2297         if (ret)
2298                 goto err_pm;
2299
2300         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2301          * fence, whereas 965+ only requires a fence if using
2302          * framebuffer compression.  For simplicity, we always install
2303          * a fence as the cost is not that onerous.
2304          */
2305         if (view.type == I915_GGTT_VIEW_NORMAL) {
2306                 ret = i915_gem_object_get_fence(obj);
2307                 if (ret == -EDEADLK) {
2308                         /*
2309                          * -EDEADLK means there are no free fences
2310                          * no pending flips.
2311                          *
2312                          * This is propagated to atomic, but it uses
2313                          * -EDEADLK to force a locking recovery, so
2314                          * change the returned error to -EBUSY.
2315                          */
2316                         ret = -EBUSY;
2317                         goto err_unpin;
2318                 } else if (ret)
2319                         goto err_unpin;
2320
2321                 i915_gem_object_pin_fence(obj);
2322         }
2323
2324         intel_runtime_pm_put(dev_priv);
2325         return 0;
2326
2327 err_unpin:
2328         i915_gem_object_unpin_from_display_plane(obj, &view);
2329 err_pm:
2330         intel_runtime_pm_put(dev_priv);
2331         return ret;
2332 }
2333
2334 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2335 {
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338
2339         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2340
2341         intel_fill_fb_ggtt_view(&view, fb, rotation);
2342
2343         if (view.type == I915_GGTT_VIEW_NORMAL)
2344                 i915_gem_object_unpin_fence(obj);
2345
2346         i915_gem_object_unpin_from_display_plane(obj, &view);
2347 }
2348
2349 /*
2350  * Adjust the tile offset by moving the difference into
2351  * the x/y offsets.
2352  *
2353  * Input tile dimensions and pitch must already be
2354  * rotated to match x and y, and in pixel units.
2355  */
2356 static u32 intel_adjust_tile_offset(int *x, int *y,
2357                                     unsigned int tile_width,
2358                                     unsigned int tile_height,
2359                                     unsigned int tile_size,
2360                                     unsigned int pitch_tiles,
2361                                     u32 old_offset,
2362                                     u32 new_offset)
2363 {
2364         unsigned int tiles;
2365
2366         WARN_ON(old_offset & (tile_size - 1));
2367         WARN_ON(new_offset & (tile_size - 1));
2368         WARN_ON(new_offset > old_offset);
2369
2370         tiles = (old_offset - new_offset) / tile_size;
2371
2372         *y += tiles / pitch_tiles * tile_height;
2373         *x += tiles % pitch_tiles * tile_width;
2374
2375         return new_offset;
2376 }
2377
2378 /*
2379  * Computes the linear offset to the base tile and adjusts
2380  * x, y. bytes per pixel is assumed to be a power-of-two.
2381  *
2382  * In the 90/270 rotated case, x and y are assumed
2383  * to be already rotated to match the rotated GTT view, and
2384  * pitch is the tile_height aligned framebuffer height.
2385  */
2386 u32 intel_compute_tile_offset(int *x, int *y,
2387                               const struct drm_framebuffer *fb, int plane,
2388                               unsigned int pitch,
2389                               unsigned int rotation)
2390 {
2391         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2392         uint64_t fb_modifier = fb->modifier[plane];
2393         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2394         u32 offset, offset_aligned, alignment;
2395
2396         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2397         if (alignment)
2398                 alignment--;
2399
2400         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2401                 unsigned int tile_size, tile_width, tile_height;
2402                 unsigned int tile_rows, tiles, pitch_tiles;
2403
2404                 tile_size = intel_tile_size(dev_priv);
2405                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2406                                 fb_modifier, cpp);
2407
2408                 if (intel_rotation_90_or_270(rotation)) {
2409                         pitch_tiles = pitch / tile_height;
2410                         swap(tile_width, tile_height);
2411                 } else {
2412                         pitch_tiles = pitch / (tile_width * cpp);
2413                 }
2414
2415                 tile_rows = *y / tile_height;
2416                 *y %= tile_height;
2417
2418                 tiles = *x / tile_width;
2419                 *x %= tile_width;
2420
2421                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2422                 offset_aligned = offset & ~alignment;
2423
2424                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2425                                          tile_size, pitch_tiles,
2426                                          offset, offset_aligned);
2427         } else {
2428                 offset = *y * pitch + *x * cpp;
2429                 offset_aligned = offset & ~alignment;
2430
2431                 *y = (offset & alignment) / pitch;
2432                 *x = ((offset & alignment) - *y * pitch) / cpp;
2433         }
2434
2435         return offset_aligned;
2436 }
2437
2438 static int i9xx_format_to_fourcc(int format)
2439 {
2440         switch (format) {
2441         case DISPPLANE_8BPP:
2442                 return DRM_FORMAT_C8;
2443         case DISPPLANE_BGRX555:
2444                 return DRM_FORMAT_XRGB1555;
2445         case DISPPLANE_BGRX565:
2446                 return DRM_FORMAT_RGB565;
2447         default:
2448         case DISPPLANE_BGRX888:
2449                 return DRM_FORMAT_XRGB8888;
2450         case DISPPLANE_RGBX888:
2451                 return DRM_FORMAT_XBGR8888;
2452         case DISPPLANE_BGRX101010:
2453                 return DRM_FORMAT_XRGB2101010;
2454         case DISPPLANE_RGBX101010:
2455                 return DRM_FORMAT_XBGR2101010;
2456         }
2457 }
2458
2459 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2460 {
2461         switch (format) {
2462         case PLANE_CTL_FORMAT_RGB_565:
2463                 return DRM_FORMAT_RGB565;
2464         default:
2465         case PLANE_CTL_FORMAT_XRGB_8888:
2466                 if (rgb_order) {
2467                         if (alpha)
2468                                 return DRM_FORMAT_ABGR8888;
2469                         else
2470                                 return DRM_FORMAT_XBGR8888;
2471                 } else {
2472                         if (alpha)
2473                                 return DRM_FORMAT_ARGB8888;
2474                         else
2475                                 return DRM_FORMAT_XRGB8888;
2476                 }
2477         case PLANE_CTL_FORMAT_XRGB_2101010:
2478                 if (rgb_order)
2479                         return DRM_FORMAT_XBGR2101010;
2480                 else
2481                         return DRM_FORMAT_XRGB2101010;
2482         }
2483 }
2484
2485 static bool
2486 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2487                               struct intel_initial_plane_config *plane_config)
2488 {
2489         struct drm_device *dev = crtc->base.dev;
2490         struct drm_i915_private *dev_priv = to_i915(dev);
2491         struct drm_i915_gem_object *obj = NULL;
2492         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2493         struct drm_framebuffer *fb = &plane_config->fb->base;
2494         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2495         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2496                                     PAGE_SIZE);
2497
2498         size_aligned -= base_aligned;
2499
2500         if (plane_config->size == 0)
2501                 return false;
2502
2503         /* If the FB is too big, just don't use it since fbdev is not very
2504          * important and we should probably use that space with FBC or other
2505          * features. */
2506         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2507                 return false;
2508
2509         mutex_lock(&dev->struct_mutex);
2510
2511         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2512                                                              base_aligned,
2513                                                              base_aligned,
2514                                                              size_aligned);
2515         if (!obj) {
2516                 mutex_unlock(&dev->struct_mutex);
2517                 return false;
2518         }
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2532                                    &mode_cmd, obj)) {
2533                 DRM_DEBUG_KMS("intel fb init failed\n");
2534                 goto out_unref_obj;
2535         }
2536
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2574         struct intel_plane *intel_plane = to_intel_plane(primary);
2575         struct intel_plane_state *intel_state =
2576                 to_intel_plane_state(plane_state);
2577         struct drm_framebuffer *fb;
2578
2579         if (!plane_config->fb)
2580                 return;
2581
2582         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2583                 fb = &plane_config->fb->base;
2584                 goto valid_fb;
2585         }
2586
2587         kfree(plane_config->fb);
2588
2589         /*
2590          * Failed to alloc the obj, check to see if we should share
2591          * an fb with another CRTC instead
2592          */
2593         for_each_crtc(dev, c) {
2594                 i = to_intel_crtc(c);
2595
2596                 if (c == &intel_crtc->base)
2597                         continue;
2598
2599                 if (!i->active)
2600                         continue;
2601
2602                 fb = c->primary->fb;
2603                 if (!fb)
2604                         continue;
2605
2606                 obj = intel_fb_obj(fb);
2607                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2608                         drm_framebuffer_reference(fb);
2609                         goto valid_fb;
2610                 }
2611         }
2612
2613         /*
2614          * We've failed to reconstruct the BIOS FB.  Current display state
2615          * indicates that the primary plane is visible, but has a NULL FB,
2616          * which will lead to problems later if we don't fix it up.  The
2617          * simplest solution is to just disable the primary plane now and
2618          * pretend the BIOS never had it enabled.
2619          */
2620         to_intel_plane_state(plane_state)->visible = false;
2621         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2623         intel_plane->disable_plane(primary, &intel_crtc->base);
2624
2625         return;
2626
2627 valid_fb:
2628         plane_state->src_x = 0;
2629         plane_state->src_y = 0;
2630         plane_state->src_w = fb->width << 16;
2631         plane_state->src_h = fb->height << 16;
2632
2633         plane_state->crtc_x = 0;
2634         plane_state->crtc_y = 0;
2635         plane_state->crtc_w = fb->width;
2636         plane_state->crtc_h = fb->height;
2637
2638         intel_state->src.x1 = plane_state->src_x;
2639         intel_state->src.y1 = plane_state->src_y;
2640         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2641         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2642         intel_state->dst.x1 = plane_state->crtc_x;
2643         intel_state->dst.y1 = plane_state->crtc_y;
2644         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2645         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2646
2647         obj = intel_fb_obj(fb);
2648         if (obj->tiling_mode != I915_TILING_NONE)
2649                 dev_priv->preserve_bios_swizzle = true;
2650
2651         drm_framebuffer_reference(fb);
2652         primary->fb = primary->state->fb = fb;
2653         primary->crtc = primary->state->crtc = &intel_crtc->base;
2654         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_plane *primary,
2659                                       const struct intel_crtc_state *crtc_state,
2660                                       const struct intel_plane_state *plane_state)
2661 {
2662         struct drm_device *dev = primary->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2665         struct drm_framebuffer *fb = plane_state->base.fb;
2666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2667         int plane = intel_crtc->plane;
2668         u32 linear_offset;
2669         u32 dspcntr;
2670         i915_reg_t reg = DSPCNTR(plane);
2671         unsigned int rotation = plane_state->base.rotation;
2672         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2673         int x = plane_state->src.x1 >> 16;
2674         int y = plane_state->src.y1 >> 16;
2675
2676         dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678         dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680         if (INTEL_INFO(dev)->gen < 4) {
2681                 if (intel_crtc->pipe == PIPE_B)
2682                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684                 /* pipesrc and dspsize control the size that is scaled from,
2685                  * which should always be the user's requested size.
2686                  */
2687                 I915_WRITE(DSPSIZE(plane),
2688                            ((crtc_state->pipe_src_h - 1) << 16) |
2689                            (crtc_state->pipe_src_w - 1));
2690                 I915_WRITE(DSPPOS(plane), 0);
2691         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692                 I915_WRITE(PRIMSIZE(plane),
2693                            ((crtc_state->pipe_src_h - 1) << 16) |
2694                            (crtc_state->pipe_src_w - 1));
2695                 I915_WRITE(PRIMPOS(plane), 0);
2696                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697         }
2698
2699         switch (fb->pixel_format) {
2700         case DRM_FORMAT_C8:
2701                 dspcntr |= DISPPLANE_8BPP;
2702                 break;
2703         case DRM_FORMAT_XRGB1555:
2704                 dspcntr |= DISPPLANE_BGRX555;
2705                 break;
2706         case DRM_FORMAT_RGB565:
2707                 dspcntr |= DISPPLANE_BGRX565;
2708                 break;
2709         case DRM_FORMAT_XRGB8888:
2710                 dspcntr |= DISPPLANE_BGRX888;
2711                 break;
2712         case DRM_FORMAT_XBGR8888:
2713                 dspcntr |= DISPPLANE_RGBX888;
2714                 break;
2715         case DRM_FORMAT_XRGB2101010:
2716                 dspcntr |= DISPPLANE_BGRX101010;
2717                 break;
2718         case DRM_FORMAT_XBGR2101010:
2719                 dspcntr |= DISPPLANE_RGBX101010;
2720                 break;
2721         default:
2722                 BUG();
2723         }
2724
2725         if (INTEL_INFO(dev)->gen >= 4 &&
2726             obj->tiling_mode != I915_TILING_NONE)
2727                 dspcntr |= DISPPLANE_TILED;
2728
2729         if (IS_G4X(dev))
2730                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732         linear_offset = y * fb->pitches[0] + x * cpp;
2733
2734         if (INTEL_INFO(dev)->gen >= 4) {
2735                 intel_crtc->dspaddr_offset =
2736                         intel_compute_tile_offset(&x, &y, fb, 0,
2737                                                   fb->pitches[0], rotation);
2738                 linear_offset -= intel_crtc->dspaddr_offset;
2739         } else {
2740                 intel_crtc->dspaddr_offset = linear_offset;
2741         }
2742
2743         if (rotation == BIT(DRM_ROTATE_180)) {
2744                 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746                 x += (crtc_state->pipe_src_w - 1);
2747                 y += (crtc_state->pipe_src_h - 1);
2748
2749                 /* Finding the last pixel of the last line of the display
2750                 data and adding to linear_offset*/
2751                 linear_offset +=
2752                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2753                         (crtc_state->pipe_src_w - 1) * cpp;
2754         }
2755
2756         intel_crtc->adjusted_x = x;
2757         intel_crtc->adjusted_y = y;
2758
2759         I915_WRITE(reg, dspcntr);
2760
2761         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2762         if (INTEL_INFO(dev)->gen >= 4) {
2763                 I915_WRITE(DSPSURF(plane),
2764                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2766                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767         } else
2768                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769         POSTING_READ(reg);
2770 }
2771
2772 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2773                                        struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int plane = intel_crtc->plane;
2779
2780         I915_WRITE(DSPCNTR(plane), 0);
2781         if (INTEL_INFO(dev_priv)->gen >= 4)
2782                 I915_WRITE(DSPSURF(plane), 0);
2783         else
2784                 I915_WRITE(DSPADDR(plane), 0);
2785         POSTING_READ(DSPCNTR(plane));
2786 }
2787
2788 static void ironlake_update_primary_plane(struct drm_plane *primary,
2789                                           const struct intel_crtc_state *crtc_state,
2790                                           const struct intel_plane_state *plane_state)
2791 {
2792         struct drm_device *dev = primary->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2795         struct drm_framebuffer *fb = plane_state->base.fb;
2796         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2797         int plane = intel_crtc->plane;
2798         u32 linear_offset;
2799         u32 dspcntr;
2800         i915_reg_t reg = DSPCNTR(plane);
2801         unsigned int rotation = plane_state->base.rotation;
2802         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2803         int x = plane_state->src.x1 >> 16;
2804         int y = plane_state->src.y1 >> 16;
2805
2806         dspcntr = DISPPLANE_GAMMA_ENABLE;
2807         dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812         switch (fb->pixel_format) {
2813         case DRM_FORMAT_C8:
2814                 dspcntr |= DISPPLANE_8BPP;
2815                 break;
2816         case DRM_FORMAT_RGB565:
2817                 dspcntr |= DISPPLANE_BGRX565;
2818                 break;
2819         case DRM_FORMAT_XRGB8888:
2820                 dspcntr |= DISPPLANE_BGRX888;
2821                 break;
2822         case DRM_FORMAT_XBGR8888:
2823                 dspcntr |= DISPPLANE_RGBX888;
2824                 break;
2825         case DRM_FORMAT_XRGB2101010:
2826                 dspcntr |= DISPPLANE_BGRX101010;
2827                 break;
2828         case DRM_FORMAT_XBGR2101010:
2829                 dspcntr |= DISPPLANE_RGBX101010;
2830                 break;
2831         default:
2832                 BUG();
2833         }
2834
2835         if (obj->tiling_mode != I915_TILING_NONE)
2836                 dspcntr |= DISPPLANE_TILED;
2837
2838         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2839                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2840
2841         linear_offset = y * fb->pitches[0] + x * cpp;
2842         intel_crtc->dspaddr_offset =
2843                 intel_compute_tile_offset(&x, &y, fb, 0,
2844                                           fb->pitches[0], rotation);
2845         linear_offset -= intel_crtc->dspaddr_offset;
2846         if (rotation == BIT(DRM_ROTATE_180)) {
2847                 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850                         x += (crtc_state->pipe_src_w - 1);
2851                         y += (crtc_state->pipe_src_h - 1);
2852
2853                         /* Finding the last pixel of the last line of the display
2854                         data and adding to linear_offset*/
2855                         linear_offset +=
2856                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2857                                 (crtc_state->pipe_src_w - 1) * cpp;
2858                 }
2859         }
2860
2861         intel_crtc->adjusted_x = x;
2862         intel_crtc->adjusted_y = y;
2863
2864         I915_WRITE(reg, dspcntr);
2865
2866         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867         I915_WRITE(DSPSURF(plane),
2868                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871         } else {
2872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874         }
2875         POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2879                               uint64_t fb_modifier, uint32_t pixel_format)
2880 {
2881         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2882                 return 64;
2883         } else {
2884                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2885
2886                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2887         }
2888 }
2889
2890 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2891                            struct drm_i915_gem_object *obj,
2892                            unsigned int plane)
2893 {
2894         struct i915_ggtt_view view;
2895         struct i915_vma *vma;
2896         u64 offset;
2897
2898         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2899                                 intel_plane->base.state->rotation);
2900
2901         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2902         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2903                 view.type))
2904                 return -1;
2905
2906         offset = vma->node.start;
2907
2908         if (plane == 1) {
2909                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2910                           PAGE_SIZE;
2911         }
2912
2913         WARN_ON(upper_32_bits(offset));
2914
2915         return lower_32_bits(offset);
2916 }
2917
2918 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 {
2920         struct drm_device *dev = intel_crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922
2923         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2925         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2926 }
2927
2928 /*
2929  * This function detaches (aka. unbinds) unused scalers in hardware
2930  */
2931 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 {
2933         struct intel_crtc_scaler_state *scaler_state;
2934         int i;
2935
2936         scaler_state = &intel_crtc->config->scaler_state;
2937
2938         /* loop through and disable scalers that aren't in use */
2939         for (i = 0; i < intel_crtc->num_scalers; i++) {
2940                 if (!scaler_state->scalers[i].in_use)
2941                         skl_detach_scaler(intel_crtc, i);
2942         }
2943 }
2944
2945 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 {
2947         switch (pixel_format) {
2948         case DRM_FORMAT_C8:
2949                 return PLANE_CTL_FORMAT_INDEXED;
2950         case DRM_FORMAT_RGB565:
2951                 return PLANE_CTL_FORMAT_RGB_565;
2952         case DRM_FORMAT_XBGR8888:
2953                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2954         case DRM_FORMAT_XRGB8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888;
2956         /*
2957          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2958          * to be already pre-multiplied. We need to add a knob (or a different
2959          * DRM_FORMAT) for user-space to configure that.
2960          */
2961         case DRM_FORMAT_ABGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2963                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2964         case DRM_FORMAT_ARGB8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888 |
2966                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2967         case DRM_FORMAT_XRGB2101010:
2968                 return PLANE_CTL_FORMAT_XRGB_2101010;
2969         case DRM_FORMAT_XBGR2101010:
2970                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2971         case DRM_FORMAT_YUYV:
2972                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2973         case DRM_FORMAT_YVYU:
2974                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2975         case DRM_FORMAT_UYVY:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2977         case DRM_FORMAT_VYUY:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979         default:
2980                 MISSING_CASE(pixel_format);
2981         }
2982
2983         return 0;
2984 }
2985
2986 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 {
2988         switch (fb_modifier) {
2989         case DRM_FORMAT_MOD_NONE:
2990                 break;
2991         case I915_FORMAT_MOD_X_TILED:
2992                 return PLANE_CTL_TILED_X;
2993         case I915_FORMAT_MOD_Y_TILED:
2994                 return PLANE_CTL_TILED_Y;
2995         case I915_FORMAT_MOD_Yf_TILED:
2996                 return PLANE_CTL_TILED_YF;
2997         default:
2998                 MISSING_CASE(fb_modifier);
2999         }
3000
3001         return 0;
3002 }
3003
3004 u32 skl_plane_ctl_rotation(unsigned int rotation)
3005 {
3006         switch (rotation) {
3007         case BIT(DRM_ROTATE_0):
3008                 break;
3009         /*
3010          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3011          * while i915 HW rotation is clockwise, thats why this swapping.
3012          */
3013         case BIT(DRM_ROTATE_90):
3014                 return PLANE_CTL_ROTATE_270;
3015         case BIT(DRM_ROTATE_180):
3016                 return PLANE_CTL_ROTATE_180;
3017         case BIT(DRM_ROTATE_270):
3018                 return PLANE_CTL_ROTATE_90;
3019         default:
3020                 MISSING_CASE(rotation);
3021         }
3022
3023         return 0;
3024 }
3025
3026 static void skylake_update_primary_plane(struct drm_plane *plane,
3027                                          const struct intel_crtc_state *crtc_state,
3028                                          const struct intel_plane_state *plane_state)
3029 {
3030         struct drm_device *dev = plane->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3033         struct drm_framebuffer *fb = plane_state->base.fb;
3034         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3035         int pipe = intel_crtc->pipe;
3036         u32 plane_ctl, stride_div, stride;
3037         u32 tile_height, plane_offset, plane_size;
3038         unsigned int rotation = plane_state->base.rotation;
3039         int x_offset, y_offset;
3040         u32 surf_addr;
3041         int scaler_id = plane_state->scaler_id;
3042         int src_x = plane_state->src.x1 >> 16;
3043         int src_y = plane_state->src.y1 >> 16;
3044         int src_w = drm_rect_width(&plane_state->src) >> 16;
3045         int src_h = drm_rect_height(&plane_state->src) >> 16;
3046         int dst_x = plane_state->dst.x1;
3047         int dst_y = plane_state->dst.y1;
3048         int dst_w = drm_rect_width(&plane_state->dst);
3049         int dst_h = drm_rect_height(&plane_state->dst);
3050
3051         plane_ctl = PLANE_CTL_ENABLE |
3052                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3053                     PLANE_CTL_PIPE_CSC_ENABLE;
3054
3055         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3056         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3057         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3058         plane_ctl |= skl_plane_ctl_rotation(rotation);
3059
3060         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3061                                                fb->pixel_format);
3062         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3063
3064         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3065
3066         if (intel_rotation_90_or_270(rotation)) {
3067                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3068
3069                 /* stride = Surface height in tiles */
3070                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3071                 stride = DIV_ROUND_UP(fb->height, tile_height);
3072                 x_offset = stride * tile_height - src_y - src_h;
3073                 y_offset = src_x;
3074                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3075         } else {
3076                 stride = fb->pitches[0] / stride_div;
3077                 x_offset = src_x;
3078                 y_offset = src_y;
3079                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3080         }
3081         plane_offset = y_offset << 16 | x_offset;
3082
3083         intel_crtc->adjusted_x = x_offset;
3084         intel_crtc->adjusted_y = y_offset;
3085
3086         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3087         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3088         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3089         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3090
3091         if (scaler_id >= 0) {
3092                 uint32_t ps_ctrl = 0;
3093
3094                 WARN_ON(!dst_w || !dst_h);
3095                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3096                         crtc_state->scaler_state.scalers[scaler_id].mode;
3097                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3098                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3099                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3100                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3101                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3102         } else {
3103                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3104         }
3105
3106         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3107
3108         POSTING_READ(PLANE_SURF(pipe, 0));
3109 }
3110
3111 static void skylake_disable_primary_plane(struct drm_plane *primary,
3112                                           struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int pipe = to_intel_crtc(crtc)->pipe;
3117
3118         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3119         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3120         POSTING_READ(PLANE_SURF(pipe, 0));
3121 }
3122
3123 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3124 static int
3125 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3126                            int x, int y, enum mode_set_atomic state)
3127 {
3128         /* Support for kgdboc is disabled, this needs a major rework. */
3129         DRM_ERROR("legacy panic handler not supported any more.\n");
3130
3131         return -ENODEV;
3132 }
3133
3134 static void intel_complete_page_flips(struct drm_device *dev)
3135 {
3136         struct drm_crtc *crtc;
3137
3138         for_each_crtc(dev, crtc) {
3139                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3140                 enum plane plane = intel_crtc->plane;
3141
3142                 intel_prepare_page_flip(dev, plane);
3143                 intel_finish_page_flip_plane(dev, plane);
3144         }
3145 }
3146
3147 static void intel_update_primary_planes(struct drm_device *dev)
3148 {
3149         struct drm_crtc *crtc;
3150
3151         for_each_crtc(dev, crtc) {
3152                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3153                 struct intel_plane_state *plane_state;
3154
3155                 drm_modeset_lock_crtc(crtc, &plane->base);
3156                 plane_state = to_intel_plane_state(plane->base.state);
3157
3158                 if (plane_state->visible)
3159                         plane->update_plane(&plane->base,
3160                                             to_intel_crtc_state(crtc->state),
3161                                             plane_state);
3162
3163                 drm_modeset_unlock_crtc(crtc);
3164         }
3165 }
3166
3167 void intel_prepare_reset(struct drm_device *dev)
3168 {
3169         /* no reset support for gen2 */
3170         if (IS_GEN2(dev))
3171                 return;
3172
3173         /* reset doesn't touch the display */
3174         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3175                 return;
3176
3177         drm_modeset_lock_all(dev);
3178         /*
3179          * Disabling the crtcs gracefully seems nicer. Also the
3180          * g33 docs say we should at least disable all the planes.
3181          */
3182         intel_display_suspend(dev);
3183 }
3184
3185 void intel_finish_reset(struct drm_device *dev)
3186 {
3187         struct drm_i915_private *dev_priv = to_i915(dev);
3188
3189         /*
3190          * Flips in the rings will be nuked by the reset,
3191          * so complete all pending flips so that user space
3192          * will get its events and not get stuck.
3193          */
3194         intel_complete_page_flips(dev);
3195
3196         /* no reset support for gen2 */
3197         if (IS_GEN2(dev))
3198                 return;
3199
3200         /* reset doesn't touch the display */
3201         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3202                 /*
3203                  * Flips in the rings have been nuked by the reset,
3204                  * so update the base address of all primary
3205                  * planes to the the last fb to make sure we're
3206                  * showing the correct fb after a reset.
3207                  *
3208                  * FIXME: Atomic will make this obsolete since we won't schedule
3209                  * CS-based flips (which might get lost in gpu resets) any more.
3210                  */
3211                 intel_update_primary_planes(dev);
3212                 return;
3213         }
3214
3215         /*
3216          * The display has been reset as well,
3217          * so need a full re-initialization.
3218          */
3219         intel_runtime_pm_disable_interrupts(dev_priv);
3220         intel_runtime_pm_enable_interrupts(dev_priv);
3221
3222         intel_modeset_init_hw(dev);
3223
3224         spin_lock_irq(&dev_priv->irq_lock);
3225         if (dev_priv->display.hpd_irq_setup)
3226                 dev_priv->display.hpd_irq_setup(dev);
3227         spin_unlock_irq(&dev_priv->irq_lock);
3228
3229         intel_display_resume(dev);
3230
3231         intel_hpd_init(dev_priv);
3232
3233         drm_modeset_unlock_all(dev);
3234 }
3235
3236 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         bool pending;
3242
3243         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3244             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3245                 return false;
3246
3247         spin_lock_irq(&dev->event_lock);
3248         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3249         spin_unlock_irq(&dev->event_lock);
3250
3251         return pending;
3252 }
3253
3254 static void intel_update_pipe_config(struct intel_crtc *crtc,
3255                                      struct intel_crtc_state *old_crtc_state)
3256 {
3257         struct drm_device *dev = crtc->base.dev;
3258         struct drm_i915_private *dev_priv = dev->dev_private;
3259         struct intel_crtc_state *pipe_config =
3260                 to_intel_crtc_state(crtc->base.state);
3261
3262         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3263         crtc->base.mode = crtc->base.state->mode;
3264
3265         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3266                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3267                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3268
3269         if (HAS_DDI(dev))
3270                 intel_set_pipe_csc(&crtc->base);
3271
3272         /*
3273          * Update pipe size and adjust fitter if needed: the reason for this is
3274          * that in compute_mode_changes we check the native mode (not the pfit
3275          * mode) to see if we can flip rather than do a full mode set. In the
3276          * fastboot case, we'll flip, but if we don't update the pipesrc and
3277          * pfit state, we'll end up with a big fb scanned out into the wrong
3278          * sized surface.
3279          */
3280
3281         I915_WRITE(PIPESRC(crtc->pipe),
3282                    ((pipe_config->pipe_src_w - 1) << 16) |
3283                    (pipe_config->pipe_src_h - 1));
3284
3285         /* on skylake this is done by detaching scalers */
3286         if (INTEL_INFO(dev)->gen >= 9) {
3287                 skl_detach_scalers(crtc);
3288
3289                 if (pipe_config->pch_pfit.enabled)
3290                         skylake_pfit_enable(crtc);
3291         } else if (HAS_PCH_SPLIT(dev)) {
3292                 if (pipe_config->pch_pfit.enabled)
3293                         ironlake_pfit_enable(crtc);
3294                 else if (old_crtc_state->pch_pfit.enabled)
3295                         ironlake_pfit_disable(crtc, true);
3296         }
3297 }
3298
3299 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3300 {
3301         struct drm_device *dev = crtc->dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304         int pipe = intel_crtc->pipe;
3305         i915_reg_t reg;
3306         u32 temp;
3307
3308         /* enable normal train */
3309         reg = FDI_TX_CTL(pipe);
3310         temp = I915_READ(reg);
3311         if (IS_IVYBRIDGE(dev)) {
3312                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3313                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3314         } else {
3315                 temp &= ~FDI_LINK_TRAIN_NONE;
3316                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3317         }
3318         I915_WRITE(reg, temp);
3319
3320         reg = FDI_RX_CTL(pipe);
3321         temp = I915_READ(reg);
3322         if (HAS_PCH_CPT(dev)) {
3323                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3324                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3325         } else {
3326                 temp &= ~FDI_LINK_TRAIN_NONE;
3327                 temp |= FDI_LINK_TRAIN_NONE;
3328         }
3329         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3330
3331         /* wait one idle pattern time */
3332         POSTING_READ(reg);
3333         udelay(1000);
3334
3335         /* IVB wants error correction enabled */
3336         if (IS_IVYBRIDGE(dev))
3337                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3338                            FDI_FE_ERRC_ENABLE);
3339 }
3340
3341 /* The FDI link training functions for ILK/Ibexpeak. */
3342 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3343 {
3344         struct drm_device *dev = crtc->dev;
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347         int pipe = intel_crtc->pipe;
3348         i915_reg_t reg;
3349         u32 temp, tries;
3350
3351         /* FDI needs bits from pipe first */
3352         assert_pipe_enabled(dev_priv, pipe);
3353
3354         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3355            for train result */
3356         reg = FDI_RX_IMR(pipe);
3357         temp = I915_READ(reg);
3358         temp &= ~FDI_RX_SYMBOL_LOCK;
3359         temp &= ~FDI_RX_BIT_LOCK;
3360         I915_WRITE(reg, temp);
3361         I915_READ(reg);
3362         udelay(150);
3363
3364         /* enable CPU FDI TX and PCH FDI RX */
3365         reg = FDI_TX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3368         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_1;
3371         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3372
3373         reg = FDI_RX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         temp &= ~FDI_LINK_TRAIN_NONE;
3376         temp |= FDI_LINK_TRAIN_PATTERN_1;
3377         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379         POSTING_READ(reg);
3380         udelay(150);
3381
3382         /* Ironlake workaround, enable clock pointer after FDI enable*/
3383         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3384         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3385                    FDI_RX_PHASE_SYNC_POINTER_EN);
3386
3387         reg = FDI_RX_IIR(pipe);
3388         for (tries = 0; tries < 5; tries++) {
3389                 temp = I915_READ(reg);
3390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391
3392                 if ((temp & FDI_RX_BIT_LOCK)) {
3393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3395                         break;
3396                 }
3397         }
3398         if (tries == 5)
3399                 DRM_ERROR("FDI train 1 fail!\n");
3400
3401         /* Train 2 */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_2;
3406         I915_WRITE(reg, temp);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_LINK_TRAIN_NONE;
3411         temp |= FDI_LINK_TRAIN_PATTERN_2;
3412         I915_WRITE(reg, temp);
3413
3414         POSTING_READ(reg);
3415         udelay(150);
3416
3417         reg = FDI_RX_IIR(pipe);
3418         for (tries = 0; tries < 5; tries++) {
3419                 temp = I915_READ(reg);
3420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422                 if (temp & FDI_RX_SYMBOL_LOCK) {
3423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3425                         break;
3426                 }
3427         }
3428         if (tries == 5)
3429                 DRM_ERROR("FDI train 2 fail!\n");
3430
3431         DRM_DEBUG_KMS("FDI train done\n");
3432
3433 }
3434
3435 static const int snb_b_fdi_train_param[] = {
3436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3440 };
3441
3442 /* The FDI link training functions for SNB/Cougarpoint. */
3443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_private *dev_priv = dev->dev_private;
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449         i915_reg_t reg;
3450         u32 temp, i, retry;
3451
3452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453            for train result */
3454         reg = FDI_RX_IMR(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_RX_SYMBOL_LOCK;
3457         temp &= ~FDI_RX_BIT_LOCK;
3458         I915_WRITE(reg, temp);
3459
3460         POSTING_READ(reg);
3461         udelay(150);
3462
3463         /* enable CPU FDI TX and PCH FDI RX */
3464         reg = FDI_TX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3467         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3468         temp &= ~FDI_LINK_TRAIN_NONE;
3469         temp |= FDI_LINK_TRAIN_PATTERN_1;
3470         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471         /* SNB-B */
3472         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3473         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3474
3475         I915_WRITE(FDI_RX_MISC(pipe),
3476                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3477
3478         reg = FDI_RX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         if (HAS_PCH_CPT(dev)) {
3481                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3482                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483         } else {
3484                 temp &= ~FDI_LINK_TRAIN_NONE;
3485                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486         }
3487         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3488
3489         POSTING_READ(reg);
3490         udelay(150);
3491
3492         for (i = 0; i < 4; i++) {
3493                 reg = FDI_TX_CTL(pipe);
3494                 temp = I915_READ(reg);
3495                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3496                 temp |= snb_b_fdi_train_param[i];
3497                 I915_WRITE(reg, temp);
3498
3499                 POSTING_READ(reg);
3500                 udelay(500);
3501
3502                 for (retry = 0; retry < 5; retry++) {
3503                         reg = FDI_RX_IIR(pipe);
3504                         temp = I915_READ(reg);
3505                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3506                         if (temp & FDI_RX_BIT_LOCK) {
3507                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3508                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3509                                 break;
3510                         }
3511                         udelay(50);
3512                 }
3513                 if (retry < 5)
3514                         break;
3515         }
3516         if (i == 4)
3517                 DRM_ERROR("FDI train 1 fail!\n");
3518
3519         /* Train 2 */
3520         reg = FDI_TX_CTL(pipe);
3521         temp = I915_READ(reg);
3522         temp &= ~FDI_LINK_TRAIN_NONE;
3523         temp |= FDI_LINK_TRAIN_PATTERN_2;
3524         if (IS_GEN6(dev)) {
3525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526                 /* SNB-B */
3527                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3528         }
3529         I915_WRITE(reg, temp);
3530
3531         reg = FDI_RX_CTL(pipe);
3532         temp = I915_READ(reg);
3533         if (HAS_PCH_CPT(dev)) {
3534                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3536         } else {
3537                 temp &= ~FDI_LINK_TRAIN_NONE;
3538                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3539         }
3540         I915_WRITE(reg, temp);
3541
3542         POSTING_READ(reg);
3543         udelay(150);
3544
3545         for (i = 0; i < 4; i++) {
3546                 reg = FDI_TX_CTL(pipe);
3547                 temp = I915_READ(reg);
3548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549                 temp |= snb_b_fdi_train_param[i];
3550                 I915_WRITE(reg, temp);
3551
3552                 POSTING_READ(reg);
3553                 udelay(500);
3554
3555                 for (retry = 0; retry < 5; retry++) {
3556                         reg = FDI_RX_IIR(pipe);
3557                         temp = I915_READ(reg);
3558                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3559                         if (temp & FDI_RX_SYMBOL_LOCK) {
3560                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3561                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3562                                 break;
3563                         }
3564                         udelay(50);
3565                 }
3566                 if (retry < 5)
3567                         break;
3568         }
3569         if (i == 4)
3570                 DRM_ERROR("FDI train 2 fail!\n");
3571
3572         DRM_DEBUG_KMS("FDI train done.\n");
3573 }
3574
3575 /* Manual link training for Ivy Bridge A0 parts */
3576 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581         int pipe = intel_crtc->pipe;
3582         i915_reg_t reg;
3583         u32 temp, i, j;
3584
3585         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3586            for train result */
3587         reg = FDI_RX_IMR(pipe);
3588         temp = I915_READ(reg);
3589         temp &= ~FDI_RX_SYMBOL_LOCK;
3590         temp &= ~FDI_RX_BIT_LOCK;
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3597                       I915_READ(FDI_RX_IIR(pipe)));
3598
3599         /* Try each vswing and preemphasis setting twice before moving on */
3600         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3601                 /* disable first in case we need to retry */
3602                 reg = FDI_TX_CTL(pipe);
3603                 temp = I915_READ(reg);
3604                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3605                 temp &= ~FDI_TX_ENABLE;
3606                 I915_WRITE(reg, temp);
3607
3608                 reg = FDI_RX_CTL(pipe);
3609                 temp = I915_READ(reg);
3610                 temp &= ~FDI_LINK_TRAIN_AUTO;
3611                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3612                 temp &= ~FDI_RX_ENABLE;
3613                 I915_WRITE(reg, temp);
3614
3615                 /* enable CPU FDI TX and PCH FDI RX */
3616                 reg = FDI_TX_CTL(pipe);
3617                 temp = I915_READ(reg);
3618                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3619                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3620                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3622                 temp |= snb_b_fdi_train_param[j/2];
3623                 temp |= FDI_COMPOSITE_SYNC;
3624                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3625
3626                 I915_WRITE(FDI_RX_MISC(pipe),
3627                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3628
3629                 reg = FDI_RX_CTL(pipe);
3630                 temp = I915_READ(reg);
3631                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3632                 temp |= FDI_COMPOSITE_SYNC;
3633                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3634
3635                 POSTING_READ(reg);
3636                 udelay(1); /* should be 0.5us */
3637
3638                 for (i = 0; i < 4; i++) {
3639                         reg = FDI_RX_IIR(pipe);
3640                         temp = I915_READ(reg);
3641                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3642
3643                         if (temp & FDI_RX_BIT_LOCK ||
3644                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3645                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3646                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3647                                               i);
3648                                 break;
3649                         }
3650                         udelay(1); /* should be 0.5us */
3651                 }
3652                 if (i == 4) {
3653                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3654                         continue;
3655                 }
3656
3657                 /* Train 2 */
3658                 reg = FDI_TX_CTL(pipe);
3659                 temp = I915_READ(reg);
3660                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3661                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3662                 I915_WRITE(reg, temp);
3663
3664                 reg = FDI_RX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3667                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3668                 I915_WRITE(reg, temp);
3669
3670                 POSTING_READ(reg);
3671                 udelay(2); /* should be 1.5us */
3672
3673                 for (i = 0; i < 4; i++) {
3674                         reg = FDI_RX_IIR(pipe);
3675                         temp = I915_READ(reg);
3676                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678                         if (temp & FDI_RX_SYMBOL_LOCK ||
3679                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3680                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3681                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3682                                               i);
3683                                 goto train_done;
3684                         }
3685                         udelay(2); /* should be 1.5us */
3686                 }
3687                 if (i == 4)
3688                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3689         }
3690
3691 train_done:
3692         DRM_DEBUG_KMS("FDI train done.\n");
3693 }
3694
3695 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3696 {
3697         struct drm_device *dev = intel_crtc->base.dev;
3698         struct drm_i915_private *dev_priv = dev->dev_private;
3699         int pipe = intel_crtc->pipe;
3700         i915_reg_t reg;
3701         u32 temp;
3702
3703         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3704         reg = FDI_RX_CTL(pipe);
3705         temp = I915_READ(reg);
3706         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3707         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3708         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3709         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3710
3711         POSTING_READ(reg);
3712         udelay(200);
3713
3714         /* Switch from Rawclk to PCDclk */
3715         temp = I915_READ(reg);
3716         I915_WRITE(reg, temp | FDI_PCDCLK);
3717
3718         POSTING_READ(reg);
3719         udelay(200);
3720
3721         /* Enable CPU FDI TX PLL, always on for Ironlake */
3722         reg = FDI_TX_CTL(pipe);
3723         temp = I915_READ(reg);
3724         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3725                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3726
3727                 POSTING_READ(reg);
3728                 udelay(100);
3729         }
3730 }
3731
3732 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3733 {
3734         struct drm_device *dev = intel_crtc->base.dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         int pipe = intel_crtc->pipe;
3737         i915_reg_t reg;
3738         u32 temp;
3739
3740         /* Switch from PCDclk to Rawclk */
3741         reg = FDI_RX_CTL(pipe);
3742         temp = I915_READ(reg);
3743         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3744
3745         /* Disable CPU FDI TX PLL */
3746         reg = FDI_TX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3749
3750         POSTING_READ(reg);
3751         udelay(100);
3752
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3756
3757         /* Wait for the clocks to turn off. */
3758         POSTING_READ(reg);
3759         udelay(100);
3760 }
3761
3762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         int pipe = intel_crtc->pipe;
3768         i915_reg_t reg;
3769         u32 temp;
3770
3771         /* disable CPU FDI tx and PCH FDI rx */
3772         reg = FDI_TX_CTL(pipe);
3773         temp = I915_READ(reg);
3774         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3775         POSTING_READ(reg);
3776
3777         reg = FDI_RX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~(0x7 << 16);
3780         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3781         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3782
3783         POSTING_READ(reg);
3784         udelay(100);
3785
3786         /* Ironlake workaround, disable clock pointer after downing FDI */
3787         if (HAS_PCH_IBX(dev))
3788                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3789
3790         /* still set train pattern 1 */
3791         reg = FDI_TX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         temp &= ~FDI_LINK_TRAIN_NONE;
3794         temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         I915_WRITE(reg, temp);
3796
3797         reg = FDI_RX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         if (HAS_PCH_CPT(dev)) {
3800                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3801                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3802         } else {
3803                 temp &= ~FDI_LINK_TRAIN_NONE;
3804                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3805         }
3806         /* BPC in FDI rx is consistent with that in PIPECONF */
3807         temp &= ~(0x07 << 16);
3808         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3809         I915_WRITE(reg, temp);
3810
3811         POSTING_READ(reg);
3812         udelay(100);
3813 }
3814
3815 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3816 {
3817         struct intel_crtc *crtc;
3818
3819         /* Note that we don't need to be called with mode_config.lock here
3820          * as our list of CRTC objects is static for the lifetime of the
3821          * device and so cannot disappear as we iterate. Similarly, we can
3822          * happily treat the predicates as racy, atomic checks as userspace
3823          * cannot claim and pin a new fb without at least acquring the
3824          * struct_mutex and so serialising with us.
3825          */
3826         for_each_intel_crtc(dev, crtc) {
3827                 if (atomic_read(&crtc->unpin_work_count) == 0)
3828                         continue;
3829
3830                 if (crtc->unpin_work)
3831                         intel_wait_for_vblank(dev, crtc->pipe);
3832
3833                 return true;
3834         }
3835
3836         return false;
3837 }
3838
3839 static void page_flip_completed(struct intel_crtc *intel_crtc)
3840 {
3841         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3842         struct intel_unpin_work *work = intel_crtc->unpin_work;
3843
3844         /* ensure that the unpin work is consistent wrt ->pending. */
3845         smp_rmb();
3846         intel_crtc->unpin_work = NULL;
3847
3848         if (work->event)
3849                 drm_send_vblank_event(intel_crtc->base.dev,
3850                                       intel_crtc->pipe,
3851                                       work->event);
3852
3853         drm_crtc_vblank_put(&intel_crtc->base);
3854
3855         wake_up_all(&dev_priv->pending_flip_queue);
3856         queue_work(dev_priv->wq, &work->work);
3857
3858         trace_i915_flip_complete(intel_crtc->plane,
3859                                  work->pending_flip_obj);
3860 }
3861
3862 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3863 {
3864         struct drm_device *dev = crtc->dev;
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         long ret;
3867
3868         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3869
3870         ret = wait_event_interruptible_timeout(
3871                                         dev_priv->pending_flip_queue,
3872                                         !intel_crtc_has_pending_flip(crtc),
3873                                         60*HZ);
3874
3875         if (ret < 0)
3876                 return ret;
3877
3878         if (ret == 0) {
3879                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880
3881                 spin_lock_irq(&dev->event_lock);
3882                 if (intel_crtc->unpin_work) {
3883                         WARN_ONCE(1, "Removing stuck page flip\n");
3884                         page_flip_completed(intel_crtc);
3885                 }
3886                 spin_unlock_irq(&dev->event_lock);
3887         }
3888
3889         return 0;
3890 }
3891
3892 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3893 {
3894         u32 temp;
3895
3896         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3897
3898         mutex_lock(&dev_priv->sb_lock);
3899
3900         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3901         temp |= SBI_SSCCTL_DISABLE;
3902         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3903
3904         mutex_unlock(&dev_priv->sb_lock);
3905 }
3906
3907 /* Program iCLKIP clock to the desired frequency */
3908 static void lpt_program_iclkip(struct drm_crtc *crtc)
3909 {
3910         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3911         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3912         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3913         u32 temp;
3914
3915         lpt_disable_iclkip(dev_priv);
3916
3917         /* The iCLK virtual clock root frequency is in MHz,
3918          * but the adjusted_mode->crtc_clock in in KHz. To get the
3919          * divisors, it is necessary to divide one by another, so we
3920          * convert the virtual clock precision to KHz here for higher
3921          * precision.
3922          */
3923         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3924                 u32 iclk_virtual_root_freq = 172800 * 1000;
3925                 u32 iclk_pi_range = 64;
3926                 u32 desired_divisor;
3927
3928                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3929                                                     clock << auxdiv);
3930                 divsel = (desired_divisor / iclk_pi_range) - 2;
3931                 phaseinc = desired_divisor % iclk_pi_range;
3932
3933                 /*
3934                  * Near 20MHz is a corner case which is
3935                  * out of range for the 7-bit divisor
3936                  */
3937                 if (divsel <= 0x7f)
3938                         break;
3939         }
3940
3941         /* This should not happen with any sane values */
3942         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3943                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3944         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3945                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3946
3947         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3948                         clock,
3949                         auxdiv,
3950                         divsel,
3951                         phasedir,
3952                         phaseinc);
3953
3954         mutex_lock(&dev_priv->sb_lock);
3955
3956         /* Program SSCDIVINTPHASE6 */
3957         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3958         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3959         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3960         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3961         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3962         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3963         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3964         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3965
3966         /* Program SSCAUXDIV */
3967         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3968         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3969         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3970         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3971
3972         /* Enable modulator and associated divider */
3973         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3974         temp &= ~SBI_SSCCTL_DISABLE;
3975         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3976
3977         mutex_unlock(&dev_priv->sb_lock);
3978
3979         /* Wait for initialization time */
3980         udelay(24);
3981
3982         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3983 }
3984
3985 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3986 {
3987         u32 divsel, phaseinc, auxdiv;
3988         u32 iclk_virtual_root_freq = 172800 * 1000;
3989         u32 iclk_pi_range = 64;
3990         u32 desired_divisor;
3991         u32 temp;
3992
3993         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3994                 return 0;
3995
3996         mutex_lock(&dev_priv->sb_lock);
3997
3998         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999         if (temp & SBI_SSCCTL_DISABLE) {
4000                 mutex_unlock(&dev_priv->sb_lock);
4001                 return 0;
4002         }
4003
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4006                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4007         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4008                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4009
4010         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4011         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4012                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4013
4014         mutex_unlock(&dev_priv->sb_lock);
4015
4016         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4017
4018         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4019                                  desired_divisor << auxdiv);
4020 }
4021
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023                                                 enum pipe pch_transcoder)
4024 {
4025         struct drm_device *dev = crtc->base.dev;
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028
4029         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030                    I915_READ(HTOTAL(cpu_transcoder)));
4031         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032                    I915_READ(HBLANK(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034                    I915_READ(HSYNC(cpu_transcoder)));
4035
4036         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037                    I915_READ(VTOTAL(cpu_transcoder)));
4038         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039                    I915_READ(VBLANK(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041                    I915_READ(VSYNC(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044 }
4045
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         uint32_t temp;
4050
4051         temp = I915_READ(SOUTH_CHICKEN1);
4052         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4053                 return;
4054
4055         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
4058         temp &= ~FDI_BC_BIFURCATION_SELECT;
4059         if (enable)
4060                 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4063         I915_WRITE(SOUTH_CHICKEN1, temp);
4064         POSTING_READ(SOUTH_CHICKEN1);
4065 }
4066
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 {
4069         struct drm_device *dev = intel_crtc->base.dev;
4070
4071         switch (intel_crtc->pipe) {
4072         case PIPE_A:
4073                 break;
4074         case PIPE_B:
4075                 if (intel_crtc->config->fdi_lanes > 2)
4076                         cpt_set_fdi_bc_bifurcation(dev, false);
4077                 else
4078                         cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080                 break;
4081         case PIPE_C:
4082                 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084                 break;
4085         default:
4086                 BUG();
4087         }
4088 }
4089
4090 /* Return which DP Port should be selected for Transcoder DP control */
4091 static enum port
4092 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4093 {
4094         struct drm_device *dev = crtc->dev;
4095         struct intel_encoder *encoder;
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder) {
4098                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4099                     encoder->type == INTEL_OUTPUT_EDP)
4100                         return enc_to_dig_port(&encoder->base)->port;
4101         }
4102
4103         return -1;
4104 }
4105
4106 /*
4107  * Enable PCH resources required for PCH ports:
4108  *   - PCH PLLs
4109  *   - FDI training & RX/TX
4110  *   - update transcoder timings
4111  *   - DP transcoding bits
4112  *   - transcoder
4113  */
4114 static void ironlake_pch_enable(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120         u32 temp;
4121
4122         assert_pch_transcoder_disabled(dev_priv, pipe);
4123
4124         if (IS_IVYBRIDGE(dev))
4125                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4126
4127         /* Write the TU size bits before fdi link training, so that error
4128          * detection works. */
4129         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4130                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4131
4132         /*
4133          * Sometimes spurious CPU pipe underruns happen during FDI
4134          * training, at least with VGA+HDMI cloning. Suppress them.
4135          */
4136         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4137
4138         /* For PCH output, training FDI link */
4139         dev_priv->display.fdi_link_train(crtc);
4140
4141         /* We need to program the right clock selection before writing the pixel
4142          * mutliplier into the DPLL. */
4143         if (HAS_PCH_CPT(dev)) {
4144                 u32 sel;
4145
4146                 temp = I915_READ(PCH_DPLL_SEL);
4147                 temp |= TRANS_DPLL_ENABLE(pipe);
4148                 sel = TRANS_DPLLB_SEL(pipe);
4149                 if (intel_crtc->config->shared_dpll ==
4150                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4151                         temp |= sel;
4152                 else
4153                         temp &= ~sel;
4154                 I915_WRITE(PCH_DPLL_SEL, temp);
4155         }
4156
4157         /* XXX: pch pll's can be enabled any time before we enable the PCH
4158          * transcoder, and we actually should do this to not upset any PCH
4159          * transcoder that already use the clock when we share it.
4160          *
4161          * Note that enable_shared_dpll tries to do the right thing, but
4162          * get_shared_dpll unconditionally resets the pll - we need that to have
4163          * the right LVDS enable sequence. */
4164         intel_enable_shared_dpll(intel_crtc);
4165
4166         /* set transcoder timing, panel must allow it */
4167         assert_panel_unlocked(dev_priv, pipe);
4168         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4169
4170         intel_fdi_normal_train(crtc);
4171
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173
4174         /* For PCH DP, enable TRANS_DP_CTL */
4175         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4176                 const struct drm_display_mode *adjusted_mode =
4177                         &intel_crtc->config->base.adjusted_mode;
4178                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4179                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4180                 temp = I915_READ(reg);
4181                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4182                           TRANS_DP_SYNC_MASK |
4183                           TRANS_DP_BPC_MASK);
4184                 temp |= TRANS_DP_OUTPUT_ENABLE;
4185                 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4188                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4190                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192                 switch (intel_trans_dp_port_sel(crtc)) {
4193                 case PORT_B:
4194                         temp |= TRANS_DP_PORT_SEL_B;
4195                         break;
4196                 case PORT_C:
4197                         temp |= TRANS_DP_PORT_SEL_C;
4198                         break;
4199                 case PORT_D:
4200                         temp |= TRANS_DP_PORT_SEL_D;
4201                         break;
4202                 default:
4203                         BUG();
4204                 }
4205
4206                 I915_WRITE(reg, temp);
4207         }
4208
4209         ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221         lpt_program_iclkip(crtc);
4222
4223         /* Set transcoder timing. */
4224         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4230 {
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         i915_reg_t dslreg = PIPEDSL(pipe);
4233         u32 temp;
4234
4235         temp = I915_READ(dslreg);
4236         udelay(500);
4237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4238                 if (wait_for(I915_READ(dslreg) != temp, 5))
4239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4240         }
4241 }
4242
4243 static int
4244 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4245                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4246                   int src_w, int src_h, int dst_w, int dst_h)
4247 {
4248         struct intel_crtc_scaler_state *scaler_state =
4249                 &crtc_state->scaler_state;
4250         struct intel_crtc *intel_crtc =
4251                 to_intel_crtc(crtc_state->base.crtc);
4252         int need_scaling;
4253
4254         need_scaling = intel_rotation_90_or_270(rotation) ?
4255                 (src_h != dst_w || src_w != dst_h):
4256                 (src_w != dst_w || src_h != dst_h);
4257
4258         /*
4259          * if plane is being disabled or scaler is no more required or force detach
4260          *  - free scaler binded to this plane/crtc
4261          *  - in order to do this, update crtc->scaler_usage
4262          *
4263          * Here scaler state in crtc_state is set free so that
4264          * scaler can be assigned to other user. Actual register
4265          * update to free the scaler is done in plane/panel-fit programming.
4266          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4267          */
4268         if (force_detach || !need_scaling) {
4269                 if (*scaler_id >= 0) {
4270                         scaler_state->scaler_users &= ~(1 << scaler_user);
4271                         scaler_state->scalers[*scaler_id].in_use = 0;
4272
4273                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4274                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4275                                 intel_crtc->pipe, scaler_user, *scaler_id,
4276                                 scaler_state->scaler_users);
4277                         *scaler_id = -1;
4278                 }
4279                 return 0;
4280         }
4281
4282         /* range checks */
4283         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4284                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4285
4286                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4287                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4288                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4289                         "size is out of scaler range\n",
4290                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4291                 return -EINVAL;
4292         }
4293
4294         /* mark this plane as a scaler user in crtc_state */
4295         scaler_state->scaler_users |= (1 << scaler_user);
4296         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4297                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4298                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4299                 scaler_state->scaler_users);
4300
4301         return 0;
4302 }
4303
4304 /**
4305  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4306  *
4307  * @state: crtc's scaler state
4308  *
4309  * Return
4310  *     0 - scaler_usage updated successfully
4311  *    error - requested scaling cannot be supported or other error condition
4312  */
4313 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4314 {
4315         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4316         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4317
4318         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4319                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4320
4321         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4322                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4323                 state->pipe_src_w, state->pipe_src_h,
4324                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4325 }
4326
4327 /**
4328  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4329  *
4330  * @state: crtc's scaler state
4331  * @plane_state: atomic plane state to update
4332  *
4333  * Return
4334  *     0 - scaler_usage updated successfully
4335  *    error - requested scaling cannot be supported or other error condition
4336  */
4337 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4338                                    struct intel_plane_state *plane_state)
4339 {
4340
4341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4342         struct intel_plane *intel_plane =
4343                 to_intel_plane(plane_state->base.plane);
4344         struct drm_framebuffer *fb = plane_state->base.fb;
4345         int ret;
4346
4347         bool force_detach = !fb || !plane_state->visible;
4348
4349         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4350                       intel_plane->base.base.id, intel_crtc->pipe,
4351                       drm_plane_index(&intel_plane->base));
4352
4353         ret = skl_update_scaler(crtc_state, force_detach,
4354                                 drm_plane_index(&intel_plane->base),
4355                                 &plane_state->scaler_id,
4356                                 plane_state->base.rotation,
4357                                 drm_rect_width(&plane_state->src) >> 16,
4358                                 drm_rect_height(&plane_state->src) >> 16,
4359                                 drm_rect_width(&plane_state->dst),
4360                                 drm_rect_height(&plane_state->dst));
4361
4362         if (ret || plane_state->scaler_id < 0)
4363                 return ret;
4364
4365         /* check colorkey */
4366         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4367                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4368                               intel_plane->base.base.id);
4369                 return -EINVAL;
4370         }
4371
4372         /* Check src format */
4373         switch (fb->pixel_format) {
4374         case DRM_FORMAT_RGB565:
4375         case DRM_FORMAT_XBGR8888:
4376         case DRM_FORMAT_XRGB8888:
4377         case DRM_FORMAT_ABGR8888:
4378         case DRM_FORMAT_ARGB8888:
4379         case DRM_FORMAT_XRGB2101010:
4380         case DRM_FORMAT_XBGR2101010:
4381         case DRM_FORMAT_YUYV:
4382         case DRM_FORMAT_YVYU:
4383         case DRM_FORMAT_UYVY:
4384         case DRM_FORMAT_VYUY:
4385                 break;
4386         default:
4387                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4388                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4389                 return -EINVAL;
4390         }
4391
4392         return 0;
4393 }
4394
4395 static void skylake_scaler_disable(struct intel_crtc *crtc)
4396 {
4397         int i;
4398
4399         for (i = 0; i < crtc->num_scalers; i++)
4400                 skl_detach_scaler(crtc, i);
4401 }
4402
4403 static void skylake_pfit_enable(struct intel_crtc *crtc)
4404 {
4405         struct drm_device *dev = crtc->base.dev;
4406         struct drm_i915_private *dev_priv = dev->dev_private;
4407         int pipe = crtc->pipe;
4408         struct intel_crtc_scaler_state *scaler_state =
4409                 &crtc->config->scaler_state;
4410
4411         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4412
4413         if (crtc->config->pch_pfit.enabled) {
4414                 int id;
4415
4416                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4417                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4418                         return;
4419                 }
4420
4421                 id = scaler_state->scaler_id;
4422                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4423                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4424                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4425                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4426
4427                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4428         }
4429 }
4430
4431 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4432 {
4433         struct drm_device *dev = crtc->base.dev;
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         int pipe = crtc->pipe;
4436
4437         if (crtc->config->pch_pfit.enabled) {
4438                 /* Force use of hard-coded filter coefficients
4439                  * as some pre-programmed values are broken,
4440                  * e.g. x201.
4441                  */
4442                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4443                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4444                                                  PF_PIPE_SEL_IVB(pipe));
4445                 else
4446                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4447                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4448                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4449         }
4450 }
4451
4452 void hsw_enable_ips(struct intel_crtc *crtc)
4453 {
4454         struct drm_device *dev = crtc->base.dev;
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457         if (!crtc->config->ips_enabled)
4458                 return;
4459
4460         /* We can only enable IPS after we enable a plane and wait for a vblank */
4461         intel_wait_for_vblank(dev, crtc->pipe);
4462
4463         assert_plane_enabled(dev_priv, crtc->plane);
4464         if (IS_BROADWELL(dev)) {
4465                 mutex_lock(&dev_priv->rps.hw_lock);
4466                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4467                 mutex_unlock(&dev_priv->rps.hw_lock);
4468                 /* Quoting Art Runyan: "its not safe to expect any particular
4469                  * value in IPS_CTL bit 31 after enabling IPS through the
4470                  * mailbox." Moreover, the mailbox may return a bogus state,
4471                  * so we need to just enable it and continue on.
4472                  */
4473         } else {
4474                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4475                 /* The bit only becomes 1 in the next vblank, so this wait here
4476                  * is essentially intel_wait_for_vblank. If we don't have this
4477                  * and don't wait for vblanks until the end of crtc_enable, then
4478                  * the HW state readout code will complain that the expected
4479                  * IPS_CTL value is not the one we read. */
4480                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4481                         DRM_ERROR("Timed out waiting for IPS enable\n");
4482         }
4483 }
4484
4485 void hsw_disable_ips(struct intel_crtc *crtc)
4486 {
4487         struct drm_device *dev = crtc->base.dev;
4488         struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490         if (!crtc->config->ips_enabled)
4491                 return;
4492
4493         assert_plane_enabled(dev_priv, crtc->plane);
4494         if (IS_BROADWELL(dev)) {
4495                 mutex_lock(&dev_priv->rps.hw_lock);
4496                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4497                 mutex_unlock(&dev_priv->rps.hw_lock);
4498                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4499                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4500                         DRM_ERROR("Timed out waiting for IPS disable\n");
4501         } else {
4502                 I915_WRITE(IPS_CTL, 0);
4503                 POSTING_READ(IPS_CTL);
4504         }
4505
4506         /* We need to wait for a vblank before we can disable the plane. */
4507         intel_wait_for_vblank(dev, crtc->pipe);
4508 }
4509
4510 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4511 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516         enum pipe pipe = intel_crtc->pipe;
4517         int i;
4518         bool reenable_ips = false;
4519
4520         /* The clocks have to be on to load the palette. */
4521         if (!crtc->state->active)
4522                 return;
4523
4524         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4525                 if (intel_crtc->config->has_dsi_encoder)
4526                         assert_dsi_pll_enabled(dev_priv);
4527                 else
4528                         assert_pll_enabled(dev_priv, pipe);
4529         }
4530
4531         /* Workaround : Do not read or write the pipe palette/gamma data while
4532          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4533          */
4534         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4535             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4536              GAMMA_MODE_MODE_SPLIT)) {
4537                 hsw_disable_ips(intel_crtc);
4538                 reenable_ips = true;
4539         }
4540
4541         for (i = 0; i < 256; i++) {
4542                 i915_reg_t palreg;
4543
4544                 if (HAS_GMCH_DISPLAY(dev))
4545                         palreg = PALETTE(pipe, i);
4546                 else
4547                         palreg = LGC_PALETTE(pipe, i);
4548
4549                 I915_WRITE(palreg,
4550                            (intel_crtc->lut_r[i] << 16) |
4551                            (intel_crtc->lut_g[i] << 8) |
4552                            intel_crtc->lut_b[i]);
4553         }
4554
4555         if (reenable_ips)
4556                 hsw_enable_ips(intel_crtc);
4557 }
4558
4559 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4560 {
4561         if (intel_crtc->overlay) {
4562                 struct drm_device *dev = intel_crtc->base.dev;
4563                 struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565                 mutex_lock(&dev->struct_mutex);
4566                 dev_priv->mm.interruptible = false;
4567                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4568                 dev_priv->mm.interruptible = true;
4569                 mutex_unlock(&dev->struct_mutex);
4570         }
4571
4572         /* Let userspace switch the overlay on again. In most cases userspace
4573          * has to recompute where to put it anyway.
4574          */
4575 }
4576
4577 /**
4578  * intel_post_enable_primary - Perform operations after enabling primary plane
4579  * @crtc: the CRTC whose primary plane was just enabled
4580  *
4581  * Performs potentially sleeping operations that must be done after the primary
4582  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4583  * called due to an explicit primary plane update, or due to an implicit
4584  * re-enable that is caused when a sprite plane is updated to no longer
4585  * completely hide the primary plane.
4586  */
4587 static void
4588 intel_post_enable_primary(struct drm_crtc *crtc)
4589 {
4590         struct drm_device *dev = crtc->dev;
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         int pipe = intel_crtc->pipe;
4594
4595         /*
4596          * FIXME IPS should be fine as long as one plane is
4597          * enabled, but in practice it seems to have problems
4598          * when going from primary only to sprite only and vice
4599          * versa.
4600          */
4601         hsw_enable_ips(intel_crtc);
4602
4603         /*
4604          * Gen2 reports pipe underruns whenever all planes are disabled.
4605          * So don't enable underrun reporting before at least some planes
4606          * are enabled.
4607          * FIXME: Need to fix the logic to work when we turn off all planes
4608          * but leave the pipe running.
4609          */
4610         if (IS_GEN2(dev))
4611                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4612
4613         /* Underruns don't always raise interrupts, so check manually. */
4614         intel_check_cpu_fifo_underruns(dev_priv);
4615         intel_check_pch_fifo_underruns(dev_priv);
4616 }
4617
4618 /* FIXME move all this to pre_plane_update() with proper state tracking */
4619 static void
4620 intel_pre_disable_primary(struct drm_crtc *crtc)
4621 {
4622         struct drm_device *dev = crtc->dev;
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4625         int pipe = intel_crtc->pipe;
4626
4627         /*
4628          * Gen2 reports pipe underruns whenever all planes are disabled.
4629          * So diasble underrun reporting before all the planes get disabled.
4630          * FIXME: Need to fix the logic to work when we turn off all planes
4631          * but leave the pipe running.
4632          */
4633         if (IS_GEN2(dev))
4634                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4635
4636         /*
4637          * FIXME IPS should be fine as long as one plane is
4638          * enabled, but in practice it seems to have problems
4639          * when going from primary only to sprite only and vice
4640          * versa.
4641          */
4642         hsw_disable_ips(intel_crtc);
4643 }
4644
4645 /* FIXME get rid of this and use pre_plane_update */
4646 static void
4647 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4648 {
4649         struct drm_device *dev = crtc->dev;
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4652         int pipe = intel_crtc->pipe;
4653
4654         intel_pre_disable_primary(crtc);
4655
4656         /*
4657          * Vblank time updates from the shadow to live plane control register
4658          * are blocked if the memory self-refresh mode is active at that
4659          * moment. So to make sure the plane gets truly disabled, disable
4660          * first the self-refresh mode. The self-refresh enable bit in turn
4661          * will be checked/applied by the HW only at the next frame start
4662          * event which is after the vblank start event, so we need to have a
4663          * wait-for-vblank between disabling the plane and the pipe.
4664          */
4665         if (HAS_GMCH_DISPLAY(dev)) {
4666                 intel_set_memory_cxsr(dev_priv, false);
4667                 dev_priv->wm.vlv.cxsr = false;
4668                 intel_wait_for_vblank(dev, pipe);
4669         }
4670 }
4671
4672 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4673 {
4674         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4675         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4676         struct intel_crtc_state *pipe_config =
4677                 to_intel_crtc_state(crtc->base.state);
4678         struct drm_device *dev = crtc->base.dev;
4679         struct drm_plane *primary = crtc->base.primary;
4680         struct drm_plane_state *old_pri_state =
4681                 drm_atomic_get_existing_plane_state(old_state, primary);
4682
4683         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4684
4685         crtc->wm.cxsr_allowed = true;
4686
4687         if (pipe_config->update_wm_post && pipe_config->base.active)
4688                 intel_update_watermarks(&crtc->base);
4689
4690         if (old_pri_state) {
4691                 struct intel_plane_state *primary_state =
4692                         to_intel_plane_state(primary->state);
4693                 struct intel_plane_state *old_primary_state =
4694                         to_intel_plane_state(old_pri_state);
4695
4696                 intel_fbc_post_update(crtc);
4697
4698                 if (primary_state->visible &&
4699                     (needs_modeset(&pipe_config->base) ||
4700                      !old_primary_state->visible))
4701                         intel_post_enable_primary(&crtc->base);
4702         }
4703 }
4704
4705 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4706 {
4707         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4708         struct drm_device *dev = crtc->base.dev;
4709         struct drm_i915_private *dev_priv = dev->dev_private;
4710         struct intel_crtc_state *pipe_config =
4711                 to_intel_crtc_state(crtc->base.state);
4712         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4713         struct drm_plane *primary = crtc->base.primary;
4714         struct drm_plane_state *old_pri_state =
4715                 drm_atomic_get_existing_plane_state(old_state, primary);
4716         bool modeset = needs_modeset(&pipe_config->base);
4717
4718         if (old_pri_state) {
4719                 struct intel_plane_state *primary_state =
4720                         to_intel_plane_state(primary->state);
4721                 struct intel_plane_state *old_primary_state =
4722                         to_intel_plane_state(old_pri_state);
4723
4724                 intel_fbc_pre_update(crtc);
4725
4726                 if (old_primary_state->visible &&
4727                     (modeset || !primary_state->visible))
4728                         intel_pre_disable_primary(&crtc->base);
4729         }
4730
4731         if (pipe_config->disable_cxsr) {
4732                 crtc->wm.cxsr_allowed = false;
4733
4734                 /*
4735                  * Vblank time updates from the shadow to live plane control register
4736                  * are blocked if the memory self-refresh mode is active at that
4737                  * moment. So to make sure the plane gets truly disabled, disable
4738                  * first the self-refresh mode. The self-refresh enable bit in turn
4739                  * will be checked/applied by the HW only at the next frame start
4740                  * event which is after the vblank start event, so we need to have a
4741                  * wait-for-vblank between disabling the plane and the pipe.
4742                  */
4743                 if (old_crtc_state->base.active) {
4744                         intel_set_memory_cxsr(dev_priv, false);
4745                         dev_priv->wm.vlv.cxsr = false;
4746                         intel_wait_for_vblank(dev, crtc->pipe);
4747                 }
4748         }
4749
4750         /*
4751          * IVB workaround: must disable low power watermarks for at least
4752          * one frame before enabling scaling.  LP watermarks can be re-enabled
4753          * when scaling is disabled.
4754          *
4755          * WaCxSRDisabledForSpriteScaling:ivb
4756          */
4757         if (pipe_config->disable_lp_wm) {
4758                 ilk_disable_lp_wm(dev);
4759                 intel_wait_for_vblank(dev, crtc->pipe);
4760         }
4761
4762         /*
4763          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4764          * watermark programming here.
4765          */
4766         if (needs_modeset(&pipe_config->base))
4767                 return;
4768
4769         /*
4770          * For platforms that support atomic watermarks, program the
4771          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4772          * will be the intermediate values that are safe for both pre- and
4773          * post- vblank; when vblank happens, the 'active' values will be set
4774          * to the final 'target' values and we'll do this again to get the
4775          * optimal watermarks.  For gen9+ platforms, the values we program here
4776          * will be the final target values which will get automatically latched
4777          * at vblank time; no further programming will be necessary.
4778          *
4779          * If a platform hasn't been transitioned to atomic watermarks yet,
4780          * we'll continue to update watermarks the old way, if flags tell
4781          * us to.
4782          */
4783         if (dev_priv->display.initial_watermarks != NULL)
4784                 dev_priv->display.initial_watermarks(pipe_config);
4785         else if (pipe_config->update_wm_pre)
4786                 intel_update_watermarks(&crtc->base);
4787 }
4788
4789 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4790 {
4791         struct drm_device *dev = crtc->dev;
4792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4793         struct drm_plane *p;
4794         int pipe = intel_crtc->pipe;
4795
4796         intel_crtc_dpms_overlay_disable(intel_crtc);
4797
4798         drm_for_each_plane_mask(p, dev, plane_mask)
4799                 to_intel_plane(p)->disable_plane(p, crtc);
4800
4801         /*
4802          * FIXME: Once we grow proper nuclear flip support out of this we need
4803          * to compute the mask of flip planes precisely. For the time being
4804          * consider this a flip to a NULL plane.
4805          */
4806         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4807 }
4808
4809 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4810 {
4811         struct drm_device *dev = crtc->dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814         struct intel_encoder *encoder;
4815         int pipe = intel_crtc->pipe;
4816
4817         if (WARN_ON(intel_crtc->active))
4818                 return;
4819
4820         if (intel_crtc->config->has_pch_encoder)
4821                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4822
4823         if (intel_crtc->config->has_pch_encoder)
4824                 intel_prepare_shared_dpll(intel_crtc);
4825
4826         if (intel_crtc->config->has_dp_encoder)
4827                 intel_dp_set_m_n(intel_crtc, M1_N1);
4828
4829         intel_set_pipe_timings(intel_crtc);
4830
4831         if (intel_crtc->config->has_pch_encoder) {
4832                 intel_cpu_transcoder_set_m_n(intel_crtc,
4833                                      &intel_crtc->config->fdi_m_n, NULL);
4834         }
4835
4836         ironlake_set_pipeconf(crtc);
4837
4838         intel_crtc->active = true;
4839
4840         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4841
4842         for_each_encoder_on_crtc(dev, crtc, encoder)
4843                 if (encoder->pre_enable)
4844                         encoder->pre_enable(encoder);
4845
4846         if (intel_crtc->config->has_pch_encoder) {
4847                 /* Note: FDI PLL enabling _must_ be done before we enable the
4848                  * cpu pipes, hence this is separate from all the other fdi/pch
4849                  * enabling. */
4850                 ironlake_fdi_pll_enable(intel_crtc);
4851         } else {
4852                 assert_fdi_tx_disabled(dev_priv, pipe);
4853                 assert_fdi_rx_disabled(dev_priv, pipe);
4854         }
4855
4856         ironlake_pfit_enable(intel_crtc);
4857
4858         /*
4859          * On ILK+ LUT must be loaded before the pipe is running but with
4860          * clocks enabled
4861          */
4862         intel_crtc_load_lut(crtc);
4863
4864         if (dev_priv->display.initial_watermarks != NULL)
4865                 dev_priv->display.initial_watermarks(intel_crtc->config);
4866         intel_enable_pipe(intel_crtc);
4867
4868         if (intel_crtc->config->has_pch_encoder)
4869                 ironlake_pch_enable(crtc);
4870
4871         assert_vblank_disabled(crtc);
4872         drm_crtc_vblank_on(crtc);
4873
4874         for_each_encoder_on_crtc(dev, crtc, encoder)
4875                 encoder->enable(encoder);
4876
4877         if (HAS_PCH_CPT(dev))
4878                 cpt_verify_modeset(dev, intel_crtc->pipe);
4879
4880         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4881         if (intel_crtc->config->has_pch_encoder)
4882                 intel_wait_for_vblank(dev, pipe);
4883         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4884 }
4885
4886 /* IPS only exists on ULT machines and is tied to pipe A. */
4887 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4888 {
4889         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4890 }
4891
4892 static void haswell_crtc_enable(struct drm_crtc *crtc)
4893 {
4894         struct drm_device *dev = crtc->dev;
4895         struct drm_i915_private *dev_priv = dev->dev_private;
4896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4897         struct intel_encoder *encoder;
4898         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4899         struct intel_crtc_state *pipe_config =
4900                 to_intel_crtc_state(crtc->state);
4901
4902         if (WARN_ON(intel_crtc->active))
4903                 return;
4904
4905         if (intel_crtc->config->has_pch_encoder)
4906                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4907                                                       false);
4908
4909         if (intel_crtc->config->shared_dpll)
4910                 intel_enable_shared_dpll(intel_crtc);
4911
4912         if (intel_crtc->config->has_dp_encoder)
4913                 intel_dp_set_m_n(intel_crtc, M1_N1);
4914
4915         intel_set_pipe_timings(intel_crtc);
4916
4917         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4918                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4919                            intel_crtc->config->pixel_multiplier - 1);
4920         }
4921
4922         if (intel_crtc->config->has_pch_encoder) {
4923                 intel_cpu_transcoder_set_m_n(intel_crtc,
4924                                      &intel_crtc->config->fdi_m_n, NULL);
4925         }
4926
4927         haswell_set_pipeconf(crtc);
4928
4929         intel_set_pipe_csc(crtc);
4930
4931         intel_crtc->active = true;
4932
4933         if (intel_crtc->config->has_pch_encoder)
4934                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4935         else
4936                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4937
4938         for_each_encoder_on_crtc(dev, crtc, encoder) {
4939                 if (encoder->pre_enable)
4940                         encoder->pre_enable(encoder);
4941         }
4942
4943         if (intel_crtc->config->has_pch_encoder)
4944                 dev_priv->display.fdi_link_train(crtc);
4945
4946         if (!intel_crtc->config->has_dsi_encoder)
4947                 intel_ddi_enable_pipe_clock(intel_crtc);
4948
4949         if (INTEL_INFO(dev)->gen >= 9)
4950                 skylake_pfit_enable(intel_crtc);
4951         else
4952                 ironlake_pfit_enable(intel_crtc);
4953
4954         /*
4955          * On ILK+ LUT must be loaded before the pipe is running but with
4956          * clocks enabled
4957          */
4958         intel_crtc_load_lut(crtc);
4959
4960         intel_ddi_set_pipe_settings(crtc);
4961         if (!intel_crtc->config->has_dsi_encoder)
4962                 intel_ddi_enable_transcoder_func(crtc);
4963
4964         if (dev_priv->display.initial_watermarks != NULL)
4965                 dev_priv->display.initial_watermarks(pipe_config);
4966         else
4967                 intel_update_watermarks(crtc);
4968         intel_enable_pipe(intel_crtc);
4969
4970         if (intel_crtc->config->has_pch_encoder)
4971                 lpt_pch_enable(crtc);
4972
4973         if (intel_crtc->config->dp_encoder_is_mst)
4974                 intel_ddi_set_vc_payload_alloc(crtc, true);
4975
4976         assert_vblank_disabled(crtc);
4977         drm_crtc_vblank_on(crtc);
4978
4979         for_each_encoder_on_crtc(dev, crtc, encoder) {
4980                 encoder->enable(encoder);
4981                 intel_opregion_notify_encoder(encoder, true);
4982         }
4983
4984         if (intel_crtc->config->has_pch_encoder) {
4985                 intel_wait_for_vblank(dev, pipe);
4986                 intel_wait_for_vblank(dev, pipe);
4987                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4989                                                       true);
4990         }
4991
4992         /* If we change the relative order between pipe/planes enabling, we need
4993          * to change the workaround. */
4994         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4995         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4996                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4997                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4998         }
4999 }
5000
5001 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5002 {
5003         struct drm_device *dev = crtc->base.dev;
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005         int pipe = crtc->pipe;
5006
5007         /* To avoid upsetting the power well on haswell only disable the pfit if
5008          * it's in use. The hw state code will make sure we get this right. */
5009         if (force || crtc->config->pch_pfit.enabled) {
5010                 I915_WRITE(PF_CTL(pipe), 0);
5011                 I915_WRITE(PF_WIN_POS(pipe), 0);
5012                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5013         }
5014 }
5015
5016 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5017 {
5018         struct drm_device *dev = crtc->dev;
5019         struct drm_i915_private *dev_priv = dev->dev_private;
5020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021         struct intel_encoder *encoder;
5022         int pipe = intel_crtc->pipe;
5023
5024         if (intel_crtc->config->has_pch_encoder)
5025                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 encoder->disable(encoder);
5029
5030         drm_crtc_vblank_off(crtc);
5031         assert_vblank_disabled(crtc);
5032
5033         /*
5034          * Sometimes spurious CPU pipe underruns happen when the
5035          * pipe is already disabled, but FDI RX/TX is still enabled.
5036          * Happens at least with VGA+HDMI cloning. Suppress them.
5037          */
5038         if (intel_crtc->config->has_pch_encoder)
5039                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5040
5041         intel_disable_pipe(intel_crtc);
5042
5043         ironlake_pfit_disable(intel_crtc, false);
5044
5045         if (intel_crtc->config->has_pch_encoder) {
5046                 ironlake_fdi_disable(crtc);
5047                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5048         }
5049
5050         for_each_encoder_on_crtc(dev, crtc, encoder)
5051                 if (encoder->post_disable)
5052                         encoder->post_disable(encoder);
5053
5054         if (intel_crtc->config->has_pch_encoder) {
5055                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5056
5057                 if (HAS_PCH_CPT(dev)) {
5058                         i915_reg_t reg;
5059                         u32 temp;
5060
5061                         /* disable TRANS_DP_CTL */
5062                         reg = TRANS_DP_CTL(pipe);
5063                         temp = I915_READ(reg);
5064                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5065                                   TRANS_DP_PORT_SEL_MASK);
5066                         temp |= TRANS_DP_PORT_SEL_NONE;
5067                         I915_WRITE(reg, temp);
5068
5069                         /* disable DPLL_SEL */
5070                         temp = I915_READ(PCH_DPLL_SEL);
5071                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5072                         I915_WRITE(PCH_DPLL_SEL, temp);
5073                 }
5074
5075                 ironlake_fdi_pll_disable(intel_crtc);
5076         }
5077
5078         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5079 }
5080
5081 static void haswell_crtc_disable(struct drm_crtc *crtc)
5082 {
5083         struct drm_device *dev = crtc->dev;
5084         struct drm_i915_private *dev_priv = dev->dev_private;
5085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086         struct intel_encoder *encoder;
5087         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5088
5089         if (intel_crtc->config->has_pch_encoder)
5090                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5091                                                       false);
5092
5093         for_each_encoder_on_crtc(dev, crtc, encoder) {
5094                 intel_opregion_notify_encoder(encoder, false);
5095                 encoder->disable(encoder);
5096         }
5097
5098         drm_crtc_vblank_off(crtc);
5099         assert_vblank_disabled(crtc);
5100
5101         intel_disable_pipe(intel_crtc);
5102
5103         if (intel_crtc->config->dp_encoder_is_mst)
5104                 intel_ddi_set_vc_payload_alloc(crtc, false);
5105
5106         if (!intel_crtc->config->has_dsi_encoder)
5107                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5108
5109         if (INTEL_INFO(dev)->gen >= 9)
5110                 skylake_scaler_disable(intel_crtc);
5111         else
5112                 ironlake_pfit_disable(intel_crtc, false);
5113
5114         if (!intel_crtc->config->has_dsi_encoder)
5115                 intel_ddi_disable_pipe_clock(intel_crtc);
5116
5117         for_each_encoder_on_crtc(dev, crtc, encoder)
5118                 if (encoder->post_disable)
5119                         encoder->post_disable(encoder);
5120
5121         if (intel_crtc->config->has_pch_encoder) {
5122                 lpt_disable_pch_transcoder(dev_priv);
5123                 lpt_disable_iclkip(dev_priv);
5124                 intel_ddi_fdi_disable(crtc);
5125
5126                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5127                                                       true);
5128         }
5129 }
5130
5131 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5132 {
5133         struct drm_device *dev = crtc->base.dev;
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         struct intel_crtc_state *pipe_config = crtc->config;
5136
5137         if (!pipe_config->gmch_pfit.control)
5138                 return;
5139
5140         /*
5141          * The panel fitter should only be adjusted whilst the pipe is disabled,
5142          * according to register description and PRM.
5143          */
5144         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5145         assert_pipe_disabled(dev_priv, crtc->pipe);
5146
5147         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5148         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5149
5150         /* Border color in case we don't scale up to the full screen. Black by
5151          * default, change to something else for debugging. */
5152         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5153 }
5154
5155 static enum intel_display_power_domain port_to_power_domain(enum port port)
5156 {
5157         switch (port) {
5158         case PORT_A:
5159                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5160         case PORT_B:
5161                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5162         case PORT_C:
5163                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5164         case PORT_D:
5165                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5166         case PORT_E:
5167                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5168         default:
5169                 MISSING_CASE(port);
5170                 return POWER_DOMAIN_PORT_OTHER;
5171         }
5172 }
5173
5174 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5175 {
5176         switch (port) {
5177         case PORT_A:
5178                 return POWER_DOMAIN_AUX_A;
5179         case PORT_B:
5180                 return POWER_DOMAIN_AUX_B;
5181         case PORT_C:
5182                 return POWER_DOMAIN_AUX_C;
5183         case PORT_D:
5184                 return POWER_DOMAIN_AUX_D;
5185         case PORT_E:
5186                 /* FIXME: Check VBT for actual wiring of PORT E */
5187                 return POWER_DOMAIN_AUX_D;
5188         default:
5189                 MISSING_CASE(port);
5190                 return POWER_DOMAIN_AUX_A;
5191         }
5192 }
5193
5194 enum intel_display_power_domain
5195 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5196 {
5197         struct drm_device *dev = intel_encoder->base.dev;
5198         struct intel_digital_port *intel_dig_port;
5199
5200         switch (intel_encoder->type) {
5201         case INTEL_OUTPUT_UNKNOWN:
5202                 /* Only DDI platforms should ever use this output type */
5203                 WARN_ON_ONCE(!HAS_DDI(dev));
5204         case INTEL_OUTPUT_DISPLAYPORT:
5205         case INTEL_OUTPUT_HDMI:
5206         case INTEL_OUTPUT_EDP:
5207                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5208                 return port_to_power_domain(intel_dig_port->port);
5209         case INTEL_OUTPUT_DP_MST:
5210                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5211                 return port_to_power_domain(intel_dig_port->port);
5212         case INTEL_OUTPUT_ANALOG:
5213                 return POWER_DOMAIN_PORT_CRT;
5214         case INTEL_OUTPUT_DSI:
5215                 return POWER_DOMAIN_PORT_DSI;
5216         default:
5217                 return POWER_DOMAIN_PORT_OTHER;
5218         }
5219 }
5220
5221 enum intel_display_power_domain
5222 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5223 {
5224         struct drm_device *dev = intel_encoder->base.dev;
5225         struct intel_digital_port *intel_dig_port;
5226
5227         switch (intel_encoder->type) {
5228         case INTEL_OUTPUT_UNKNOWN:
5229         case INTEL_OUTPUT_HDMI:
5230                 /*
5231                  * Only DDI platforms should ever use these output types.
5232                  * We can get here after the HDMI detect code has already set
5233                  * the type of the shared encoder. Since we can't be sure
5234                  * what's the status of the given connectors, play safe and
5235                  * run the DP detection too.
5236                  */
5237                 WARN_ON_ONCE(!HAS_DDI(dev));
5238         case INTEL_OUTPUT_DISPLAYPORT:
5239         case INTEL_OUTPUT_EDP:
5240                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5241                 return port_to_aux_power_domain(intel_dig_port->port);
5242         case INTEL_OUTPUT_DP_MST:
5243                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5244                 return port_to_aux_power_domain(intel_dig_port->port);
5245         default:
5246                 MISSING_CASE(intel_encoder->type);
5247                 return POWER_DOMAIN_AUX_A;
5248         }
5249 }
5250
5251 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5252                                             struct intel_crtc_state *crtc_state)
5253 {
5254         struct drm_device *dev = crtc->dev;
5255         struct drm_encoder *encoder;
5256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5257         enum pipe pipe = intel_crtc->pipe;
5258         unsigned long mask;
5259         enum transcoder transcoder = crtc_state->cpu_transcoder;
5260
5261         if (!crtc_state->base.active)
5262                 return 0;
5263
5264         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5265         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5266         if (crtc_state->pch_pfit.enabled ||
5267             crtc_state->pch_pfit.force_thru)
5268                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5269
5270         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5271                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5272
5273                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5274         }
5275
5276         return mask;
5277 }
5278
5279 static unsigned long
5280 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5281                                struct intel_crtc_state *crtc_state)
5282 {
5283         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5285         enum intel_display_power_domain domain;
5286         unsigned long domains, new_domains, old_domains;
5287
5288         old_domains = intel_crtc->enabled_power_domains;
5289         intel_crtc->enabled_power_domains = new_domains =
5290                 get_crtc_power_domains(crtc, crtc_state);
5291
5292         domains = new_domains & ~old_domains;
5293
5294         for_each_power_domain(domain, domains)
5295                 intel_display_power_get(dev_priv, domain);
5296
5297         return old_domains & ~new_domains;
5298 }
5299
5300 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5301                                       unsigned long domains)
5302 {
5303         enum intel_display_power_domain domain;
5304
5305         for_each_power_domain(domain, domains)
5306                 intel_display_power_put(dev_priv, domain);
5307 }
5308
5309 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5310 {
5311         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5312
5313         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5314             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5315                 return max_cdclk_freq;
5316         else if (IS_CHERRYVIEW(dev_priv))
5317                 return max_cdclk_freq*95/100;
5318         else if (INTEL_INFO(dev_priv)->gen < 4)
5319                 return 2*max_cdclk_freq*90/100;
5320         else
5321                 return max_cdclk_freq*90/100;
5322 }
5323
5324 static void intel_update_max_cdclk(struct drm_device *dev)
5325 {
5326         struct drm_i915_private *dev_priv = dev->dev_private;
5327
5328         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5329                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5330
5331                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5332                         dev_priv->max_cdclk_freq = 675000;
5333                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5334                         dev_priv->max_cdclk_freq = 540000;
5335                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5336                         dev_priv->max_cdclk_freq = 450000;
5337                 else
5338                         dev_priv->max_cdclk_freq = 337500;
5339         } else if (IS_BROADWELL(dev))  {
5340                 /*
5341                  * FIXME with extra cooling we can allow
5342                  * 540 MHz for ULX and 675 Mhz for ULT.
5343                  * How can we know if extra cooling is
5344                  * available? PCI ID, VTB, something else?
5345                  */
5346                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5347                         dev_priv->max_cdclk_freq = 450000;
5348                 else if (IS_BDW_ULX(dev))
5349                         dev_priv->max_cdclk_freq = 450000;
5350                 else if (IS_BDW_ULT(dev))
5351                         dev_priv->max_cdclk_freq = 540000;
5352                 else
5353                         dev_priv->max_cdclk_freq = 675000;
5354         } else if (IS_CHERRYVIEW(dev)) {
5355                 dev_priv->max_cdclk_freq = 320000;
5356         } else if (IS_VALLEYVIEW(dev)) {
5357                 dev_priv->max_cdclk_freq = 400000;
5358         } else {
5359                 /* otherwise assume cdclk is fixed */
5360                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5361         }
5362
5363         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5364
5365         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5366                          dev_priv->max_cdclk_freq);
5367
5368         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5369                          dev_priv->max_dotclk_freq);
5370 }
5371
5372 static void intel_update_cdclk(struct drm_device *dev)
5373 {
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375
5376         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5377         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5378                          dev_priv->cdclk_freq);
5379
5380         /*
5381          * Program the gmbus_freq based on the cdclk frequency.
5382          * BSpec erroneously claims we should aim for 4MHz, but
5383          * in fact 1MHz is the correct frequency.
5384          */
5385         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5386                 /*
5387                  * Program the gmbus_freq based on the cdclk frequency.
5388                  * BSpec erroneously claims we should aim for 4MHz, but
5389                  * in fact 1MHz is the correct frequency.
5390                  */
5391                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5392         }
5393
5394         if (dev_priv->max_cdclk_freq == 0)
5395                 intel_update_max_cdclk(dev);
5396 }
5397
5398 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5399 {
5400         struct drm_i915_private *dev_priv = dev->dev_private;
5401         uint32_t divider;
5402         uint32_t ratio;
5403         uint32_t current_freq;
5404         int ret;
5405
5406         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5407         switch (frequency) {
5408         case 144000:
5409                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5410                 ratio = BXT_DE_PLL_RATIO(60);
5411                 break;
5412         case 288000:
5413                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5414                 ratio = BXT_DE_PLL_RATIO(60);
5415                 break;
5416         case 384000:
5417                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5418                 ratio = BXT_DE_PLL_RATIO(60);
5419                 break;
5420         case 576000:
5421                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5422                 ratio = BXT_DE_PLL_RATIO(60);
5423                 break;
5424         case 624000:
5425                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5426                 ratio = BXT_DE_PLL_RATIO(65);
5427                 break;
5428         case 19200:
5429                 /*
5430                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5431                  * to suppress GCC warning.
5432                  */
5433                 ratio = 0;
5434                 divider = 0;
5435                 break;
5436         default:
5437                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5438
5439                 return;
5440         }
5441
5442         mutex_lock(&dev_priv->rps.hw_lock);
5443         /* Inform power controller of upcoming frequency change */
5444         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445                                       0x80000000);
5446         mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448         if (ret) {
5449                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5450                           ret, frequency);
5451                 return;
5452         }
5453
5454         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5455         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5456         current_freq = current_freq * 500 + 1000;
5457
5458         /*
5459          * DE PLL has to be disabled when
5460          * - setting to 19.2MHz (bypass, PLL isn't used)
5461          * - before setting to 624MHz (PLL needs toggling)
5462          * - before setting to any frequency from 624MHz (PLL needs toggling)
5463          */
5464         if (frequency == 19200 || frequency == 624000 ||
5465             current_freq == 624000) {
5466                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5467                 /* Timeout 200us */
5468                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5469                              1))
5470                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5471         }
5472
5473         if (frequency != 19200) {
5474                 uint32_t val;
5475
5476                 val = I915_READ(BXT_DE_PLL_CTL);
5477                 val &= ~BXT_DE_PLL_RATIO_MASK;
5478                 val |= ratio;
5479                 I915_WRITE(BXT_DE_PLL_CTL, val);
5480
5481                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5482                 /* Timeout 200us */
5483                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5484                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5485
5486                 val = I915_READ(CDCLK_CTL);
5487                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5488                 val |= divider;
5489                 /*
5490                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5491                  * enable otherwise.
5492                  */
5493                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5494                 if (frequency >= 500000)
5495                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5496
5497                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5498                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5499                 val |= (frequency - 1000) / 500;
5500                 I915_WRITE(CDCLK_CTL, val);
5501         }
5502
5503         mutex_lock(&dev_priv->rps.hw_lock);
5504         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5505                                       DIV_ROUND_UP(frequency, 25000));
5506         mutex_unlock(&dev_priv->rps.hw_lock);
5507
5508         if (ret) {
5509                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5510                           ret, frequency);
5511                 return;
5512         }
5513
5514         intel_update_cdclk(dev);
5515 }
5516
5517 void broxton_init_cdclk(struct drm_device *dev)
5518 {
5519         struct drm_i915_private *dev_priv = dev->dev_private;
5520         uint32_t val;
5521
5522         /*
5523          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5524          * or else the reset will hang because there is no PCH to respond.
5525          * Move the handshake programming to initialization sequence.
5526          * Previously was left up to BIOS.
5527          */
5528         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5529         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5530         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5531
5532         /* Enable PG1 for cdclk */
5533         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5534
5535         /* check if cd clock is enabled */
5536         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5537                 DRM_DEBUG_KMS("Display already initialized\n");
5538                 return;
5539         }
5540
5541         /*
5542          * FIXME:
5543          * - The initial CDCLK needs to be read from VBT.
5544          *   Need to make this change after VBT has changes for BXT.
5545          * - check if setting the max (or any) cdclk freq is really necessary
5546          *   here, it belongs to modeset time
5547          */
5548         broxton_set_cdclk(dev, 624000);
5549
5550         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5551         POSTING_READ(DBUF_CTL);
5552
5553         udelay(10);
5554
5555         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5556                 DRM_ERROR("DBuf power enable timeout!\n");
5557 }
5558
5559 void broxton_uninit_cdclk(struct drm_device *dev)
5560 {
5561         struct drm_i915_private *dev_priv = dev->dev_private;
5562
5563         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5564         POSTING_READ(DBUF_CTL);
5565
5566         udelay(10);
5567
5568         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5569                 DRM_ERROR("DBuf power disable timeout!\n");
5570
5571         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5572         broxton_set_cdclk(dev, 19200);
5573
5574         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5575 }
5576
5577 static const struct skl_cdclk_entry {
5578         unsigned int freq;
5579         unsigned int vco;
5580 } skl_cdclk_frequencies[] = {
5581         { .freq = 308570, .vco = 8640 },
5582         { .freq = 337500, .vco = 8100 },
5583         { .freq = 432000, .vco = 8640 },
5584         { .freq = 450000, .vco = 8100 },
5585         { .freq = 540000, .vco = 8100 },
5586         { .freq = 617140, .vco = 8640 },
5587         { .freq = 675000, .vco = 8100 },
5588 };
5589
5590 static unsigned int skl_cdclk_decimal(unsigned int freq)
5591 {
5592         return (freq - 1000) / 500;
5593 }
5594
5595 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5596 {
5597         unsigned int i;
5598
5599         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5600                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5601
5602                 if (e->freq == freq)
5603                         return e->vco;
5604         }
5605
5606         return 8100;
5607 }
5608
5609 static void
5610 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5611 {
5612         unsigned int min_freq;
5613         u32 val;
5614
5615         /* select the minimum CDCLK before enabling DPLL 0 */
5616         val = I915_READ(CDCLK_CTL);
5617         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5618         val |= CDCLK_FREQ_337_308;
5619
5620         if (required_vco == 8640)
5621                 min_freq = 308570;
5622         else
5623                 min_freq = 337500;
5624
5625         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5626
5627         I915_WRITE(CDCLK_CTL, val);
5628         POSTING_READ(CDCLK_CTL);
5629
5630         /*
5631          * We always enable DPLL0 with the lowest link rate possible, but still
5632          * taking into account the VCO required to operate the eDP panel at the
5633          * desired frequency. The usual DP link rates operate with a VCO of
5634          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5635          * The modeset code is responsible for the selection of the exact link
5636          * rate later on, with the constraint of choosing a frequency that
5637          * works with required_vco.
5638          */
5639         val = I915_READ(DPLL_CTRL1);
5640
5641         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5642                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5643         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5644         if (required_vco == 8640)
5645                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5646                                             SKL_DPLL0);
5647         else
5648                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5649                                             SKL_DPLL0);
5650
5651         I915_WRITE(DPLL_CTRL1, val);
5652         POSTING_READ(DPLL_CTRL1);
5653
5654         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5655
5656         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5657                 DRM_ERROR("DPLL0 not locked\n");
5658 }
5659
5660 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5661 {
5662         int ret;
5663         u32 val;
5664
5665         /* inform PCU we want to change CDCLK */
5666         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5667         mutex_lock(&dev_priv->rps.hw_lock);
5668         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5669         mutex_unlock(&dev_priv->rps.hw_lock);
5670
5671         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5672 }
5673
5674 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5675 {
5676         unsigned int i;
5677
5678         for (i = 0; i < 15; i++) {
5679                 if (skl_cdclk_pcu_ready(dev_priv))
5680                         return true;
5681                 udelay(10);
5682         }
5683
5684         return false;
5685 }
5686
5687 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5688 {
5689         struct drm_device *dev = dev_priv->dev;
5690         u32 freq_select, pcu_ack;
5691
5692         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5693
5694         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5695                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5696                 return;
5697         }
5698
5699         /* set CDCLK_CTL */
5700         switch(freq) {
5701         case 450000:
5702         case 432000:
5703                 freq_select = CDCLK_FREQ_450_432;
5704                 pcu_ack = 1;
5705                 break;
5706         case 540000:
5707                 freq_select = CDCLK_FREQ_540;
5708                 pcu_ack = 2;
5709                 break;
5710         case 308570:
5711         case 337500:
5712         default:
5713                 freq_select = CDCLK_FREQ_337_308;
5714                 pcu_ack = 0;
5715                 break;
5716         case 617140:
5717         case 675000:
5718                 freq_select = CDCLK_FREQ_675_617;
5719                 pcu_ack = 3;
5720                 break;
5721         }
5722
5723         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5724         POSTING_READ(CDCLK_CTL);
5725
5726         /* inform PCU of the change */
5727         mutex_lock(&dev_priv->rps.hw_lock);
5728         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5729         mutex_unlock(&dev_priv->rps.hw_lock);
5730
5731         intel_update_cdclk(dev);
5732 }
5733
5734 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5735 {
5736         /* disable DBUF power */
5737         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5738         POSTING_READ(DBUF_CTL);
5739
5740         udelay(10);
5741
5742         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5743                 DRM_ERROR("DBuf power disable timeout\n");
5744
5745         /* disable DPLL0 */
5746         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5747         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5748                 DRM_ERROR("Couldn't disable DPLL0\n");
5749 }
5750
5751 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5752 {
5753         unsigned int required_vco;
5754
5755         /* DPLL0 not enabled (happens on early BIOS versions) */
5756         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5757                 /* enable DPLL0 */
5758                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5759                 skl_dpll0_enable(dev_priv, required_vco);
5760         }
5761
5762         /* set CDCLK to the frequency the BIOS chose */
5763         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5764
5765         /* enable DBUF power */
5766         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5767         POSTING_READ(DBUF_CTL);
5768
5769         udelay(10);
5770
5771         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5772                 DRM_ERROR("DBuf power enable timeout\n");
5773 }
5774
5775 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5776 {
5777         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5778         uint32_t cdctl = I915_READ(CDCLK_CTL);
5779         int freq = dev_priv->skl_boot_cdclk;
5780
5781         /*
5782          * check if the pre-os intialized the display
5783          * There is SWF18 scratchpad register defined which is set by the
5784          * pre-os which can be used by the OS drivers to check the status
5785          */
5786         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5787                 goto sanitize;
5788
5789         /* Is PLL enabled and locked ? */
5790         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5791                 goto sanitize;
5792
5793         /* DPLL okay; verify the cdclock
5794          *
5795          * Noticed in some instances that the freq selection is correct but
5796          * decimal part is programmed wrong from BIOS where pre-os does not
5797          * enable display. Verify the same as well.
5798          */
5799         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5800                 /* All well; nothing to sanitize */
5801                 return false;
5802 sanitize:
5803         /*
5804          * As of now initialize with max cdclk till
5805          * we get dynamic cdclk support
5806          * */
5807         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5808         skl_init_cdclk(dev_priv);
5809
5810         /* we did have to sanitize */
5811         return true;
5812 }
5813
5814 /* Adjust CDclk dividers to allow high res or save power if possible */
5815 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5816 {
5817         struct drm_i915_private *dev_priv = dev->dev_private;
5818         u32 val, cmd;
5819
5820         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5821                                         != dev_priv->cdclk_freq);
5822
5823         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5824                 cmd = 2;
5825         else if (cdclk == 266667)
5826                 cmd = 1;
5827         else
5828                 cmd = 0;
5829
5830         mutex_lock(&dev_priv->rps.hw_lock);
5831         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5832         val &= ~DSPFREQGUAR_MASK;
5833         val |= (cmd << DSPFREQGUAR_SHIFT);
5834         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5835         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5836                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5837                      50)) {
5838                 DRM_ERROR("timed out waiting for CDclk change\n");
5839         }
5840         mutex_unlock(&dev_priv->rps.hw_lock);
5841
5842         mutex_lock(&dev_priv->sb_lock);
5843
5844         if (cdclk == 400000) {
5845                 u32 divider;
5846
5847                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5848
5849                 /* adjust cdclk divider */
5850                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5851                 val &= ~CCK_FREQUENCY_VALUES;
5852                 val |= divider;
5853                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5854
5855                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5856                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5857                              50))
5858                         DRM_ERROR("timed out waiting for CDclk change\n");
5859         }
5860
5861         /* adjust self-refresh exit latency value */
5862         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5863         val &= ~0x7f;
5864
5865         /*
5866          * For high bandwidth configs, we set a higher latency in the bunit
5867          * so that the core display fetch happens in time to avoid underruns.
5868          */
5869         if (cdclk == 400000)
5870                 val |= 4500 / 250; /* 4.5 usec */
5871         else
5872                 val |= 3000 / 250; /* 3.0 usec */
5873         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5874
5875         mutex_unlock(&dev_priv->sb_lock);
5876
5877         intel_update_cdclk(dev);
5878 }
5879
5880 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5881 {
5882         struct drm_i915_private *dev_priv = dev->dev_private;
5883         u32 val, cmd;
5884
5885         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5886                                                 != dev_priv->cdclk_freq);
5887
5888         switch (cdclk) {
5889         case 333333:
5890         case 320000:
5891         case 266667:
5892         case 200000:
5893                 break;
5894         default:
5895                 MISSING_CASE(cdclk);
5896                 return;
5897         }
5898
5899         /*
5900          * Specs are full of misinformation, but testing on actual
5901          * hardware has shown that we just need to write the desired
5902          * CCK divider into the Punit register.
5903          */
5904         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5905
5906         mutex_lock(&dev_priv->rps.hw_lock);
5907         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5908         val &= ~DSPFREQGUAR_MASK_CHV;
5909         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5910         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5911         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5912                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5913                      50)) {
5914                 DRM_ERROR("timed out waiting for CDclk change\n");
5915         }
5916         mutex_unlock(&dev_priv->rps.hw_lock);
5917
5918         intel_update_cdclk(dev);
5919 }
5920
5921 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5922                                  int max_pixclk)
5923 {
5924         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5925         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5926
5927         /*
5928          * Really only a few cases to deal with, as only 4 CDclks are supported:
5929          *   200MHz
5930          *   267MHz
5931          *   320/333MHz (depends on HPLL freq)
5932          *   400MHz (VLV only)
5933          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5934          * of the lower bin and adjust if needed.
5935          *
5936          * We seem to get an unstable or solid color picture at 200MHz.
5937          * Not sure what's wrong. For now use 200MHz only when all pipes
5938          * are off.
5939          */
5940         if (!IS_CHERRYVIEW(dev_priv) &&
5941             max_pixclk > freq_320*limit/100)
5942                 return 400000;
5943         else if (max_pixclk > 266667*limit/100)
5944                 return freq_320;
5945         else if (max_pixclk > 0)
5946                 return 266667;
5947         else
5948                 return 200000;
5949 }
5950
5951 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5952                               int max_pixclk)
5953 {
5954         /*
5955          * FIXME:
5956          * - remove the guardband, it's not needed on BXT
5957          * - set 19.2MHz bypass frequency if there are no active pipes
5958          */
5959         if (max_pixclk > 576000*9/10)
5960                 return 624000;
5961         else if (max_pixclk > 384000*9/10)
5962                 return 576000;
5963         else if (max_pixclk > 288000*9/10)
5964                 return 384000;
5965         else if (max_pixclk > 144000*9/10)
5966                 return 288000;
5967         else
5968                 return 144000;
5969 }
5970
5971 /* Compute the max pixel clock for new configuration. */
5972 static int intel_mode_max_pixclk(struct drm_device *dev,
5973                                  struct drm_atomic_state *state)
5974 {
5975         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5976         struct drm_i915_private *dev_priv = dev->dev_private;
5977         struct drm_crtc *crtc;
5978         struct drm_crtc_state *crtc_state;
5979         unsigned max_pixclk = 0, i;
5980         enum pipe pipe;
5981
5982         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5983                sizeof(intel_state->min_pixclk));
5984
5985         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5986                 int pixclk = 0;
5987
5988                 if (crtc_state->enable)
5989                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5990
5991                 intel_state->min_pixclk[i] = pixclk;
5992         }
5993
5994         for_each_pipe(dev_priv, pipe)
5995                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5996
5997         return max_pixclk;
5998 }
5999
6000 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6001 {
6002         struct drm_device *dev = state->dev;
6003         struct drm_i915_private *dev_priv = dev->dev_private;
6004         int max_pixclk = intel_mode_max_pixclk(dev, state);
6005         struct intel_atomic_state *intel_state =
6006                 to_intel_atomic_state(state);
6007
6008         if (max_pixclk < 0)
6009                 return max_pixclk;
6010
6011         intel_state->cdclk = intel_state->dev_cdclk =
6012                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6013
6014         if (!intel_state->active_crtcs)
6015                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6016
6017         return 0;
6018 }
6019
6020 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6021 {
6022         struct drm_device *dev = state->dev;
6023         struct drm_i915_private *dev_priv = dev->dev_private;
6024         int max_pixclk = intel_mode_max_pixclk(dev, state);
6025         struct intel_atomic_state *intel_state =
6026                 to_intel_atomic_state(state);
6027
6028         if (max_pixclk < 0)
6029                 return max_pixclk;
6030
6031         intel_state->cdclk = intel_state->dev_cdclk =
6032                 broxton_calc_cdclk(dev_priv, max_pixclk);
6033
6034         if (!intel_state->active_crtcs)
6035                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6036
6037         return 0;
6038 }
6039
6040 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6041 {
6042         unsigned int credits, default_credits;
6043
6044         if (IS_CHERRYVIEW(dev_priv))
6045                 default_credits = PFI_CREDIT(12);
6046         else
6047                 default_credits = PFI_CREDIT(8);
6048
6049         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6050                 /* CHV suggested value is 31 or 63 */
6051                 if (IS_CHERRYVIEW(dev_priv))
6052                         credits = PFI_CREDIT_63;
6053                 else
6054                         credits = PFI_CREDIT(15);
6055         } else {
6056                 credits = default_credits;
6057         }
6058
6059         /*
6060          * WA - write default credits before re-programming
6061          * FIXME: should we also set the resend bit here?
6062          */
6063         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6064                    default_credits);
6065
6066         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6067                    credits | PFI_CREDIT_RESEND);
6068
6069         /*
6070          * FIXME is this guaranteed to clear
6071          * immediately or should we poll for it?
6072          */
6073         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6074 }
6075
6076 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6077 {
6078         struct drm_device *dev = old_state->dev;
6079         struct drm_i915_private *dev_priv = dev->dev_private;
6080         struct intel_atomic_state *old_intel_state =
6081                 to_intel_atomic_state(old_state);
6082         unsigned req_cdclk = old_intel_state->dev_cdclk;
6083
6084         /*
6085          * FIXME: We can end up here with all power domains off, yet
6086          * with a CDCLK frequency other than the minimum. To account
6087          * for this take the PIPE-A power domain, which covers the HW
6088          * blocks needed for the following programming. This can be
6089          * removed once it's guaranteed that we get here either with
6090          * the minimum CDCLK set, or the required power domains
6091          * enabled.
6092          */
6093         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6094
6095         if (IS_CHERRYVIEW(dev))
6096                 cherryview_set_cdclk(dev, req_cdclk);
6097         else
6098                 valleyview_set_cdclk(dev, req_cdclk);
6099
6100         vlv_program_pfi_credits(dev_priv);
6101
6102         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6103 }
6104
6105 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6106 {
6107         struct drm_device *dev = crtc->dev;
6108         struct drm_i915_private *dev_priv = to_i915(dev);
6109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6110         struct intel_encoder *encoder;
6111         int pipe = intel_crtc->pipe;
6112
6113         if (WARN_ON(intel_crtc->active))
6114                 return;
6115
6116         if (intel_crtc->config->has_dp_encoder)
6117                 intel_dp_set_m_n(intel_crtc, M1_N1);
6118
6119         intel_set_pipe_timings(intel_crtc);
6120
6121         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6122                 struct drm_i915_private *dev_priv = dev->dev_private;
6123
6124                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6125                 I915_WRITE(CHV_CANVAS(pipe), 0);
6126         }
6127
6128         i9xx_set_pipeconf(intel_crtc);
6129
6130         intel_crtc->active = true;
6131
6132         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6133
6134         for_each_encoder_on_crtc(dev, crtc, encoder)
6135                 if (encoder->pre_pll_enable)
6136                         encoder->pre_pll_enable(encoder);
6137
6138         if (!intel_crtc->config->has_dsi_encoder) {
6139                 if (IS_CHERRYVIEW(dev)) {
6140                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6141                         chv_enable_pll(intel_crtc, intel_crtc->config);
6142                 } else {
6143                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6144                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6145                 }
6146         }
6147
6148         for_each_encoder_on_crtc(dev, crtc, encoder)
6149                 if (encoder->pre_enable)
6150                         encoder->pre_enable(encoder);
6151
6152         i9xx_pfit_enable(intel_crtc);
6153
6154         intel_crtc_load_lut(crtc);
6155
6156         intel_update_watermarks(crtc);
6157         intel_enable_pipe(intel_crtc);
6158
6159         assert_vblank_disabled(crtc);
6160         drm_crtc_vblank_on(crtc);
6161
6162         for_each_encoder_on_crtc(dev, crtc, encoder)
6163                 encoder->enable(encoder);
6164 }
6165
6166 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6167 {
6168         struct drm_device *dev = crtc->base.dev;
6169         struct drm_i915_private *dev_priv = dev->dev_private;
6170
6171         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6172         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6173 }
6174
6175 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6176 {
6177         struct drm_device *dev = crtc->dev;
6178         struct drm_i915_private *dev_priv = to_i915(dev);
6179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180         struct intel_encoder *encoder;
6181         int pipe = intel_crtc->pipe;
6182
6183         if (WARN_ON(intel_crtc->active))
6184                 return;
6185
6186         i9xx_set_pll_dividers(intel_crtc);
6187
6188         if (intel_crtc->config->has_dp_encoder)
6189                 intel_dp_set_m_n(intel_crtc, M1_N1);
6190
6191         intel_set_pipe_timings(intel_crtc);
6192
6193         i9xx_set_pipeconf(intel_crtc);
6194
6195         intel_crtc->active = true;
6196
6197         if (!IS_GEN2(dev))
6198                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6199
6200         for_each_encoder_on_crtc(dev, crtc, encoder)
6201                 if (encoder->pre_enable)
6202                         encoder->pre_enable(encoder);
6203
6204         i9xx_enable_pll(intel_crtc);
6205
6206         i9xx_pfit_enable(intel_crtc);
6207
6208         intel_crtc_load_lut(crtc);
6209
6210         intel_update_watermarks(crtc);
6211         intel_enable_pipe(intel_crtc);
6212
6213         assert_vblank_disabled(crtc);
6214         drm_crtc_vblank_on(crtc);
6215
6216         for_each_encoder_on_crtc(dev, crtc, encoder)
6217                 encoder->enable(encoder);
6218 }
6219
6220 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6221 {
6222         struct drm_device *dev = crtc->base.dev;
6223         struct drm_i915_private *dev_priv = dev->dev_private;
6224
6225         if (!crtc->config->gmch_pfit.control)
6226                 return;
6227
6228         assert_pipe_disabled(dev_priv, crtc->pipe);
6229
6230         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6231                          I915_READ(PFIT_CONTROL));
6232         I915_WRITE(PFIT_CONTROL, 0);
6233 }
6234
6235 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6236 {
6237         struct drm_device *dev = crtc->dev;
6238         struct drm_i915_private *dev_priv = dev->dev_private;
6239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240         struct intel_encoder *encoder;
6241         int pipe = intel_crtc->pipe;
6242
6243         /*
6244          * On gen2 planes are double buffered but the pipe isn't, so we must
6245          * wait for planes to fully turn off before disabling the pipe.
6246          * We also need to wait on all gmch platforms because of the
6247          * self-refresh mode constraint explained above.
6248          */
6249         intel_wait_for_vblank(dev, pipe);
6250
6251         for_each_encoder_on_crtc(dev, crtc, encoder)
6252                 encoder->disable(encoder);
6253
6254         drm_crtc_vblank_off(crtc);
6255         assert_vblank_disabled(crtc);
6256
6257         intel_disable_pipe(intel_crtc);
6258
6259         i9xx_pfit_disable(intel_crtc);
6260
6261         for_each_encoder_on_crtc(dev, crtc, encoder)
6262                 if (encoder->post_disable)
6263                         encoder->post_disable(encoder);
6264
6265         if (!intel_crtc->config->has_dsi_encoder) {
6266                 if (IS_CHERRYVIEW(dev))
6267                         chv_disable_pll(dev_priv, pipe);
6268                 else if (IS_VALLEYVIEW(dev))
6269                         vlv_disable_pll(dev_priv, pipe);
6270                 else
6271                         i9xx_disable_pll(intel_crtc);
6272         }
6273
6274         for_each_encoder_on_crtc(dev, crtc, encoder)
6275                 if (encoder->post_pll_disable)
6276                         encoder->post_pll_disable(encoder);
6277
6278         if (!IS_GEN2(dev))
6279                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6280 }
6281
6282 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6283 {
6284         struct intel_encoder *encoder;
6285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6287         enum intel_display_power_domain domain;
6288         unsigned long domains;
6289
6290         if (!intel_crtc->active)
6291                 return;
6292
6293         if (to_intel_plane_state(crtc->primary->state)->visible) {
6294                 WARN_ON(intel_crtc->unpin_work);
6295
6296                 intel_pre_disable_primary_noatomic(crtc);
6297
6298                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6299                 to_intel_plane_state(crtc->primary->state)->visible = false;
6300         }
6301
6302         dev_priv->display.crtc_disable(crtc);
6303
6304         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6305                       crtc->base.id);
6306
6307         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6308         crtc->state->active = false;
6309         intel_crtc->active = false;
6310         crtc->enabled = false;
6311         crtc->state->connector_mask = 0;
6312         crtc->state->encoder_mask = 0;
6313
6314         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6315                 encoder->base.crtc = NULL;
6316
6317         intel_fbc_disable(intel_crtc);
6318         intel_update_watermarks(crtc);
6319         intel_disable_shared_dpll(intel_crtc);
6320
6321         domains = intel_crtc->enabled_power_domains;
6322         for_each_power_domain(domain, domains)
6323                 intel_display_power_put(dev_priv, domain);
6324         intel_crtc->enabled_power_domains = 0;
6325
6326         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6327         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6328 }
6329
6330 /*
6331  * turn all crtc's off, but do not adjust state
6332  * This has to be paired with a call to intel_modeset_setup_hw_state.
6333  */
6334 int intel_display_suspend(struct drm_device *dev)
6335 {
6336         struct drm_i915_private *dev_priv = to_i915(dev);
6337         struct drm_atomic_state *state;
6338         int ret;
6339
6340         state = drm_atomic_helper_suspend(dev);
6341         ret = PTR_ERR_OR_ZERO(state);
6342         if (ret)
6343                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6344         else
6345                 dev_priv->modeset_restore_state = state;
6346         return ret;
6347 }
6348
6349 void intel_encoder_destroy(struct drm_encoder *encoder)
6350 {
6351         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6352
6353         drm_encoder_cleanup(encoder);
6354         kfree(intel_encoder);
6355 }
6356
6357 /* Cross check the actual hw state with our own modeset state tracking (and it's
6358  * internal consistency). */
6359 static void intel_connector_check_state(struct intel_connector *connector)
6360 {
6361         struct drm_crtc *crtc = connector->base.state->crtc;
6362
6363         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6364                       connector->base.base.id,
6365                       connector->base.name);
6366
6367         if (connector->get_hw_state(connector)) {
6368                 struct intel_encoder *encoder = connector->encoder;
6369                 struct drm_connector_state *conn_state = connector->base.state;
6370
6371                 I915_STATE_WARN(!crtc,
6372                          "connector enabled without attached crtc\n");
6373
6374                 if (!crtc)
6375                         return;
6376
6377                 I915_STATE_WARN(!crtc->state->active,
6378                       "connector is active, but attached crtc isn't\n");
6379
6380                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6381                         return;
6382
6383                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6384                         "atomic encoder doesn't match attached encoder\n");
6385
6386                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6387                         "attached encoder crtc differs from connector crtc\n");
6388         } else {
6389                 I915_STATE_WARN(crtc && crtc->state->active,
6390                         "attached crtc is active, but connector isn't\n");
6391                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6392                         "best encoder set without crtc!\n");
6393         }
6394 }
6395
6396 int intel_connector_init(struct intel_connector *connector)
6397 {
6398         drm_atomic_helper_connector_reset(&connector->base);
6399
6400         if (!connector->base.state)
6401                 return -ENOMEM;
6402
6403         return 0;
6404 }
6405
6406 struct intel_connector *intel_connector_alloc(void)
6407 {
6408         struct intel_connector *connector;
6409
6410         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6411         if (!connector)
6412                 return NULL;
6413
6414         if (intel_connector_init(connector) < 0) {
6415                 kfree(connector);
6416                 return NULL;
6417         }
6418
6419         return connector;
6420 }
6421
6422 /* Simple connector->get_hw_state implementation for encoders that support only
6423  * one connector and no cloning and hence the encoder state determines the state
6424  * of the connector. */
6425 bool intel_connector_get_hw_state(struct intel_connector *connector)
6426 {
6427         enum pipe pipe = 0;
6428         struct intel_encoder *encoder = connector->encoder;
6429
6430         return encoder->get_hw_state(encoder, &pipe);
6431 }
6432
6433 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6434 {
6435         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6436                 return crtc_state->fdi_lanes;
6437
6438         return 0;
6439 }
6440
6441 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6442                                      struct intel_crtc_state *pipe_config)
6443 {
6444         struct drm_atomic_state *state = pipe_config->base.state;
6445         struct intel_crtc *other_crtc;
6446         struct intel_crtc_state *other_crtc_state;
6447
6448         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6449                       pipe_name(pipe), pipe_config->fdi_lanes);
6450         if (pipe_config->fdi_lanes > 4) {
6451                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6452                               pipe_name(pipe), pipe_config->fdi_lanes);
6453                 return -EINVAL;
6454         }
6455
6456         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6457                 if (pipe_config->fdi_lanes > 2) {
6458                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6459                                       pipe_config->fdi_lanes);
6460                         return -EINVAL;
6461                 } else {
6462                         return 0;
6463                 }
6464         }
6465
6466         if (INTEL_INFO(dev)->num_pipes == 2)
6467                 return 0;
6468
6469         /* Ivybridge 3 pipe is really complicated */
6470         switch (pipe) {
6471         case PIPE_A:
6472                 return 0;
6473         case PIPE_B:
6474                 if (pipe_config->fdi_lanes <= 2)
6475                         return 0;
6476
6477                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6478                 other_crtc_state =
6479                         intel_atomic_get_crtc_state(state, other_crtc);
6480                 if (IS_ERR(other_crtc_state))
6481                         return PTR_ERR(other_crtc_state);
6482
6483                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6484                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6485                                       pipe_name(pipe), pipe_config->fdi_lanes);
6486                         return -EINVAL;
6487                 }
6488                 return 0;
6489         case PIPE_C:
6490                 if (pipe_config->fdi_lanes > 2) {
6491                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6492                                       pipe_name(pipe), pipe_config->fdi_lanes);
6493                         return -EINVAL;
6494                 }
6495
6496                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6497                 other_crtc_state =
6498                         intel_atomic_get_crtc_state(state, other_crtc);
6499                 if (IS_ERR(other_crtc_state))
6500                         return PTR_ERR(other_crtc_state);
6501
6502                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6503                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6504                         return -EINVAL;
6505                 }
6506                 return 0;
6507         default:
6508                 BUG();
6509         }
6510 }
6511
6512 #define RETRY 1
6513 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6514                                        struct intel_crtc_state *pipe_config)
6515 {
6516         struct drm_device *dev = intel_crtc->base.dev;
6517         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6518         int lane, link_bw, fdi_dotclock, ret;
6519         bool needs_recompute = false;
6520
6521 retry:
6522         /* FDI is a binary signal running at ~2.7GHz, encoding
6523          * each output octet as 10 bits. The actual frequency
6524          * is stored as a divider into a 100MHz clock, and the
6525          * mode pixel clock is stored in units of 1KHz.
6526          * Hence the bw of each lane in terms of the mode signal
6527          * is:
6528          */
6529         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6530
6531         fdi_dotclock = adjusted_mode->crtc_clock;
6532
6533         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6534                                            pipe_config->pipe_bpp);
6535
6536         pipe_config->fdi_lanes = lane;
6537
6538         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6539                                link_bw, &pipe_config->fdi_m_n);
6540
6541         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6542         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6543                 pipe_config->pipe_bpp -= 2*3;
6544                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6545                               pipe_config->pipe_bpp);
6546                 needs_recompute = true;
6547                 pipe_config->bw_constrained = true;
6548
6549                 goto retry;
6550         }
6551
6552         if (needs_recompute)
6553                 return RETRY;
6554
6555         return ret;
6556 }
6557
6558 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6559                                      struct intel_crtc_state *pipe_config)
6560 {
6561         if (pipe_config->pipe_bpp > 24)
6562                 return false;
6563
6564         /* HSW can handle pixel rate up to cdclk? */
6565         if (IS_HASWELL(dev_priv->dev))
6566                 return true;
6567
6568         /*
6569          * We compare against max which means we must take
6570          * the increased cdclk requirement into account when
6571          * calculating the new cdclk.
6572          *
6573          * Should measure whether using a lower cdclk w/o IPS
6574          */
6575         return ilk_pipe_pixel_rate(pipe_config) <=
6576                 dev_priv->max_cdclk_freq * 95 / 100;
6577 }
6578
6579 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6580                                    struct intel_crtc_state *pipe_config)
6581 {
6582         struct drm_device *dev = crtc->base.dev;
6583         struct drm_i915_private *dev_priv = dev->dev_private;
6584
6585         pipe_config->ips_enabled = i915.enable_ips &&
6586                 hsw_crtc_supports_ips(crtc) &&
6587                 pipe_config_supports_ips(dev_priv, pipe_config);
6588 }
6589
6590 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6591 {
6592         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6593
6594         /* GDG double wide on either pipe, otherwise pipe A only */
6595         return INTEL_INFO(dev_priv)->gen < 4 &&
6596                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6597 }
6598
6599 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6600                                      struct intel_crtc_state *pipe_config)
6601 {
6602         struct drm_device *dev = crtc->base.dev;
6603         struct drm_i915_private *dev_priv = dev->dev_private;
6604         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6605
6606         /* FIXME should check pixel clock limits on all platforms */
6607         if (INTEL_INFO(dev)->gen < 4) {
6608                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6609
6610                 /*
6611                  * Enable double wide mode when the dot clock
6612                  * is > 90% of the (display) core speed.
6613                  */
6614                 if (intel_crtc_supports_double_wide(crtc) &&
6615                     adjusted_mode->crtc_clock > clock_limit) {
6616                         clock_limit *= 2;
6617                         pipe_config->double_wide = true;
6618                 }
6619
6620                 if (adjusted_mode->crtc_clock > clock_limit) {
6621                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6622                                       adjusted_mode->crtc_clock, clock_limit,
6623                                       yesno(pipe_config->double_wide));
6624                         return -EINVAL;
6625                 }
6626         }
6627
6628         /*
6629          * Pipe horizontal size must be even in:
6630          * - DVO ganged mode
6631          * - LVDS dual channel mode
6632          * - Double wide pipe
6633          */
6634         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6635              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6636                 pipe_config->pipe_src_w &= ~1;
6637
6638         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6639          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6640          */
6641         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6642                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6643                 return -EINVAL;
6644
6645         if (HAS_IPS(dev))
6646                 hsw_compute_ips_config(crtc, pipe_config);
6647
6648         if (pipe_config->has_pch_encoder)
6649                 return ironlake_fdi_compute_config(crtc, pipe_config);
6650
6651         return 0;
6652 }
6653
6654 static int skylake_get_display_clock_speed(struct drm_device *dev)
6655 {
6656         struct drm_i915_private *dev_priv = to_i915(dev);
6657         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6658         uint32_t cdctl = I915_READ(CDCLK_CTL);
6659         uint32_t linkrate;
6660
6661         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6662                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6663
6664         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6665                 return 540000;
6666
6667         linkrate = (I915_READ(DPLL_CTRL1) &
6668                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6669
6670         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6671             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6672                 /* vco 8640 */
6673                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6674                 case CDCLK_FREQ_450_432:
6675                         return 432000;
6676                 case CDCLK_FREQ_337_308:
6677                         return 308570;
6678                 case CDCLK_FREQ_675_617:
6679                         return 617140;
6680                 default:
6681                         WARN(1, "Unknown cd freq selection\n");
6682                 }
6683         } else {
6684                 /* vco 8100 */
6685                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6686                 case CDCLK_FREQ_450_432:
6687                         return 450000;
6688                 case CDCLK_FREQ_337_308:
6689                         return 337500;
6690                 case CDCLK_FREQ_675_617:
6691                         return 675000;
6692                 default:
6693                         WARN(1, "Unknown cd freq selection\n");
6694                 }
6695         }
6696
6697         /* error case, do as if DPLL0 isn't enabled */
6698         return 24000;
6699 }
6700
6701 static int broxton_get_display_clock_speed(struct drm_device *dev)
6702 {
6703         struct drm_i915_private *dev_priv = to_i915(dev);
6704         uint32_t cdctl = I915_READ(CDCLK_CTL);
6705         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6706         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6707         int cdclk;
6708
6709         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6710                 return 19200;
6711
6712         cdclk = 19200 * pll_ratio / 2;
6713
6714         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6715         case BXT_CDCLK_CD2X_DIV_SEL_1:
6716                 return cdclk;  /* 576MHz or 624MHz */
6717         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6718                 return cdclk * 2 / 3; /* 384MHz */
6719         case BXT_CDCLK_CD2X_DIV_SEL_2:
6720                 return cdclk / 2; /* 288MHz */
6721         case BXT_CDCLK_CD2X_DIV_SEL_4:
6722                 return cdclk / 4; /* 144MHz */
6723         }
6724
6725         /* error case, do as if DE PLL isn't enabled */
6726         return 19200;
6727 }
6728
6729 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6730 {
6731         struct drm_i915_private *dev_priv = dev->dev_private;
6732         uint32_t lcpll = I915_READ(LCPLL_CTL);
6733         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6734
6735         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6736                 return 800000;
6737         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6738                 return 450000;
6739         else if (freq == LCPLL_CLK_FREQ_450)
6740                 return 450000;
6741         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6742                 return 540000;
6743         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6744                 return 337500;
6745         else
6746                 return 675000;
6747 }
6748
6749 static int haswell_get_display_clock_speed(struct drm_device *dev)
6750 {
6751         struct drm_i915_private *dev_priv = dev->dev_private;
6752         uint32_t lcpll = I915_READ(LCPLL_CTL);
6753         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6754
6755         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6756                 return 800000;
6757         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6758                 return 450000;
6759         else if (freq == LCPLL_CLK_FREQ_450)
6760                 return 450000;
6761         else if (IS_HSW_ULT(dev))
6762                 return 337500;
6763         else
6764                 return 540000;
6765 }
6766
6767 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6768 {
6769         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6770                                       CCK_DISPLAY_CLOCK_CONTROL);
6771 }
6772
6773 static int ilk_get_display_clock_speed(struct drm_device *dev)
6774 {
6775         return 450000;
6776 }
6777
6778 static int i945_get_display_clock_speed(struct drm_device *dev)
6779 {
6780         return 400000;
6781 }
6782
6783 static int i915_get_display_clock_speed(struct drm_device *dev)
6784 {
6785         return 333333;
6786 }
6787
6788 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6789 {
6790         return 200000;
6791 }
6792
6793 static int pnv_get_display_clock_speed(struct drm_device *dev)
6794 {
6795         u16 gcfgc = 0;
6796
6797         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6798
6799         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6800         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6801                 return 266667;
6802         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6803                 return 333333;
6804         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6805                 return 444444;
6806         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6807                 return 200000;
6808         default:
6809                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6810         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6811                 return 133333;
6812         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6813                 return 166667;
6814         }
6815 }
6816
6817 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6818 {
6819         u16 gcfgc = 0;
6820
6821         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6822
6823         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6824                 return 133333;
6825         else {
6826                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6827                 case GC_DISPLAY_CLOCK_333_MHZ:
6828                         return 333333;
6829                 default:
6830                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6831                         return 190000;
6832                 }
6833         }
6834 }
6835
6836 static int i865_get_display_clock_speed(struct drm_device *dev)
6837 {
6838         return 266667;
6839 }
6840
6841 static int i85x_get_display_clock_speed(struct drm_device *dev)
6842 {
6843         u16 hpllcc = 0;
6844
6845         /*
6846          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6847          * encoding is different :(
6848          * FIXME is this the right way to detect 852GM/852GMV?
6849          */
6850         if (dev->pdev->revision == 0x1)
6851                 return 133333;
6852
6853         pci_bus_read_config_word(dev->pdev->bus,
6854                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6855
6856         /* Assume that the hardware is in the high speed state.  This
6857          * should be the default.
6858          */
6859         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6860         case GC_CLOCK_133_200:
6861         case GC_CLOCK_133_200_2:
6862         case GC_CLOCK_100_200:
6863                 return 200000;
6864         case GC_CLOCK_166_250:
6865                 return 250000;
6866         case GC_CLOCK_100_133:
6867                 return 133333;
6868         case GC_CLOCK_133_266:
6869         case GC_CLOCK_133_266_2:
6870         case GC_CLOCK_166_266:
6871                 return 266667;
6872         }
6873
6874         /* Shouldn't happen */
6875         return 0;
6876 }
6877
6878 static int i830_get_display_clock_speed(struct drm_device *dev)
6879 {
6880         return 133333;
6881 }
6882
6883 static unsigned int intel_hpll_vco(struct drm_device *dev)
6884 {
6885         struct drm_i915_private *dev_priv = dev->dev_private;
6886         static const unsigned int blb_vco[8] = {
6887                 [0] = 3200000,
6888                 [1] = 4000000,
6889                 [2] = 5333333,
6890                 [3] = 4800000,
6891                 [4] = 6400000,
6892         };
6893         static const unsigned int pnv_vco[8] = {
6894                 [0] = 3200000,
6895                 [1] = 4000000,
6896                 [2] = 5333333,
6897                 [3] = 4800000,
6898                 [4] = 2666667,
6899         };
6900         static const unsigned int cl_vco[8] = {
6901                 [0] = 3200000,
6902                 [1] = 4000000,
6903                 [2] = 5333333,
6904                 [3] = 6400000,
6905                 [4] = 3333333,
6906                 [5] = 3566667,
6907                 [6] = 4266667,
6908         };
6909         static const unsigned int elk_vco[8] = {
6910                 [0] = 3200000,
6911                 [1] = 4000000,
6912                 [2] = 5333333,
6913                 [3] = 4800000,
6914         };
6915         static const unsigned int ctg_vco[8] = {
6916                 [0] = 3200000,
6917                 [1] = 4000000,
6918                 [2] = 5333333,
6919                 [3] = 6400000,
6920                 [4] = 2666667,
6921                 [5] = 4266667,
6922         };
6923         const unsigned int *vco_table;
6924         unsigned int vco;
6925         uint8_t tmp = 0;
6926
6927         /* FIXME other chipsets? */
6928         if (IS_GM45(dev))
6929                 vco_table = ctg_vco;
6930         else if (IS_G4X(dev))
6931                 vco_table = elk_vco;
6932         else if (IS_CRESTLINE(dev))
6933                 vco_table = cl_vco;
6934         else if (IS_PINEVIEW(dev))
6935                 vco_table = pnv_vco;
6936         else if (IS_G33(dev))
6937                 vco_table = blb_vco;
6938         else
6939                 return 0;
6940
6941         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6942
6943         vco = vco_table[tmp & 0x7];
6944         if (vco == 0)
6945                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6946         else
6947                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6948
6949         return vco;
6950 }
6951
6952 static int gm45_get_display_clock_speed(struct drm_device *dev)
6953 {
6954         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6955         uint16_t tmp = 0;
6956
6957         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6958
6959         cdclk_sel = (tmp >> 12) & 0x1;
6960
6961         switch (vco) {
6962         case 2666667:
6963         case 4000000:
6964         case 5333333:
6965                 return cdclk_sel ? 333333 : 222222;
6966         case 3200000:
6967                 return cdclk_sel ? 320000 : 228571;
6968         default:
6969                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6970                 return 222222;
6971         }
6972 }
6973
6974 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6975 {
6976         static const uint8_t div_3200[] = { 16, 10,  8 };
6977         static const uint8_t div_4000[] = { 20, 12, 10 };
6978         static const uint8_t div_5333[] = { 24, 16, 14 };
6979         const uint8_t *div_table;
6980         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6981         uint16_t tmp = 0;
6982
6983         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6984
6985         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6986
6987         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6988                 goto fail;
6989
6990         switch (vco) {
6991         case 3200000:
6992                 div_table = div_3200;
6993                 break;
6994         case 4000000:
6995                 div_table = div_4000;
6996                 break;
6997         case 5333333:
6998                 div_table = div_5333;
6999                 break;
7000         default:
7001                 goto fail;
7002         }
7003
7004         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7005
7006 fail:
7007         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7008         return 200000;
7009 }
7010
7011 static int g33_get_display_clock_speed(struct drm_device *dev)
7012 {
7013         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7014         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7015         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7016         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7017         const uint8_t *div_table;
7018         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7019         uint16_t tmp = 0;
7020
7021         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7022
7023         cdclk_sel = (tmp >> 4) & 0x7;
7024
7025         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7026                 goto fail;
7027
7028         switch (vco) {
7029         case 3200000:
7030                 div_table = div_3200;
7031                 break;
7032         case 4000000:
7033                 div_table = div_4000;
7034                 break;
7035         case 4800000:
7036                 div_table = div_4800;
7037                 break;
7038         case 5333333:
7039                 div_table = div_5333;
7040                 break;
7041         default:
7042                 goto fail;
7043         }
7044
7045         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7046
7047 fail:
7048         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7049         return 190476;
7050 }
7051
7052 static void
7053 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7054 {
7055         while (*num > DATA_LINK_M_N_MASK ||
7056                *den > DATA_LINK_M_N_MASK) {
7057                 *num >>= 1;
7058                 *den >>= 1;
7059         }
7060 }
7061
7062 static void compute_m_n(unsigned int m, unsigned int n,
7063                         uint32_t *ret_m, uint32_t *ret_n)
7064 {
7065         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7066         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7067         intel_reduce_m_n_ratio(ret_m, ret_n);
7068 }
7069
7070 void
7071 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7072                        int pixel_clock, int link_clock,
7073                        struct intel_link_m_n *m_n)
7074 {
7075         m_n->tu = 64;
7076
7077         compute_m_n(bits_per_pixel * pixel_clock,
7078                     link_clock * nlanes * 8,
7079                     &m_n->gmch_m, &m_n->gmch_n);
7080
7081         compute_m_n(pixel_clock, link_clock,
7082                     &m_n->link_m, &m_n->link_n);
7083 }
7084
7085 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7086 {
7087         if (i915.panel_use_ssc >= 0)
7088                 return i915.panel_use_ssc != 0;
7089         return dev_priv->vbt.lvds_use_ssc
7090                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7091 }
7092
7093 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7094                            int num_connectors)
7095 {
7096         struct drm_device *dev = crtc_state->base.crtc->dev;
7097         struct drm_i915_private *dev_priv = dev->dev_private;
7098         int refclk;
7099
7100         WARN_ON(!crtc_state->base.state);
7101
7102         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7103                 refclk = 100000;
7104         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7105             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7106                 refclk = dev_priv->vbt.lvds_ssc_freq;
7107                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7108         } else if (!IS_GEN2(dev)) {
7109                 refclk = 96000;
7110         } else {
7111                 refclk = 48000;
7112         }
7113
7114         return refclk;
7115 }
7116
7117 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7118 {
7119         return (1 << dpll->n) << 16 | dpll->m2;
7120 }
7121
7122 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7123 {
7124         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7125 }
7126
7127 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7128                                      struct intel_crtc_state *crtc_state,
7129                                      intel_clock_t *reduced_clock)
7130 {
7131         struct drm_device *dev = crtc->base.dev;
7132         u32 fp, fp2 = 0;
7133
7134         if (IS_PINEVIEW(dev)) {
7135                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7136                 if (reduced_clock)
7137                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7138         } else {
7139                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7140                 if (reduced_clock)
7141                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7142         }
7143
7144         crtc_state->dpll_hw_state.fp0 = fp;
7145
7146         crtc->lowfreq_avail = false;
7147         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7148             reduced_clock) {
7149                 crtc_state->dpll_hw_state.fp1 = fp2;
7150                 crtc->lowfreq_avail = true;
7151         } else {
7152                 crtc_state->dpll_hw_state.fp1 = fp;
7153         }
7154 }
7155
7156 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7157                 pipe)
7158 {
7159         u32 reg_val;
7160
7161         /*
7162          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7163          * and set it to a reasonable value instead.
7164          */
7165         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7166         reg_val &= 0xffffff00;
7167         reg_val |= 0x00000030;
7168         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7169
7170         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7171         reg_val &= 0x8cffffff;
7172         reg_val = 0x8c000000;
7173         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7174
7175         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7176         reg_val &= 0xffffff00;
7177         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7178
7179         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7180         reg_val &= 0x00ffffff;
7181         reg_val |= 0xb0000000;
7182         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7183 }
7184
7185 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7186                                          struct intel_link_m_n *m_n)
7187 {
7188         struct drm_device *dev = crtc->base.dev;
7189         struct drm_i915_private *dev_priv = dev->dev_private;
7190         int pipe = crtc->pipe;
7191
7192         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7193         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7194         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7195         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7196 }
7197
7198 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7199                                          struct intel_link_m_n *m_n,
7200                                          struct intel_link_m_n *m2_n2)
7201 {
7202         struct drm_device *dev = crtc->base.dev;
7203         struct drm_i915_private *dev_priv = dev->dev_private;
7204         int pipe = crtc->pipe;
7205         enum transcoder transcoder = crtc->config->cpu_transcoder;
7206
7207         if (INTEL_INFO(dev)->gen >= 5) {
7208                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7209                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7210                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7211                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7212                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7213                  * for gen < 8) and if DRRS is supported (to make sure the
7214                  * registers are not unnecessarily accessed).
7215                  */
7216                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7217                         crtc->config->has_drrs) {
7218                         I915_WRITE(PIPE_DATA_M2(transcoder),
7219                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7220                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7221                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7222                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7223                 }
7224         } else {
7225                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7226                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7227                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7228                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7229         }
7230 }
7231
7232 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7233 {
7234         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7235
7236         if (m_n == M1_N1) {
7237                 dp_m_n = &crtc->config->dp_m_n;
7238                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7239         } else if (m_n == M2_N2) {
7240
7241                 /*
7242                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7243                  * needs to be programmed into M1_N1.
7244                  */
7245                 dp_m_n = &crtc->config->dp_m2_n2;
7246         } else {
7247                 DRM_ERROR("Unsupported divider value\n");
7248                 return;
7249         }
7250
7251         if (crtc->config->has_pch_encoder)
7252                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7253         else
7254                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7255 }
7256
7257 static void vlv_compute_dpll(struct intel_crtc *crtc,
7258                              struct intel_crtc_state *pipe_config)
7259 {
7260         u32 dpll, dpll_md;
7261
7262         /*
7263          * Enable DPIO clock input. We should never disable the reference
7264          * clock for pipe B, since VGA hotplug / manual detection depends
7265          * on it.
7266          */
7267         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7268                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7269         /* We should never disable this, set it here for state tracking */
7270         if (crtc->pipe == PIPE_B)
7271                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7272         dpll |= DPLL_VCO_ENABLE;
7273         pipe_config->dpll_hw_state.dpll = dpll;
7274
7275         dpll_md = (pipe_config->pixel_multiplier - 1)
7276                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7277         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7278 }
7279
7280 static void vlv_prepare_pll(struct intel_crtc *crtc,
7281                             const struct intel_crtc_state *pipe_config)
7282 {
7283         struct drm_device *dev = crtc->base.dev;
7284         struct drm_i915_private *dev_priv = dev->dev_private;
7285         int pipe = crtc->pipe;
7286         u32 mdiv;
7287         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7288         u32 coreclk, reg_val;
7289
7290         mutex_lock(&dev_priv->sb_lock);
7291
7292         bestn = pipe_config->dpll.n;
7293         bestm1 = pipe_config->dpll.m1;
7294         bestm2 = pipe_config->dpll.m2;
7295         bestp1 = pipe_config->dpll.p1;
7296         bestp2 = pipe_config->dpll.p2;
7297
7298         /* See eDP HDMI DPIO driver vbios notes doc */
7299
7300         /* PLL B needs special handling */
7301         if (pipe == PIPE_B)
7302                 vlv_pllb_recal_opamp(dev_priv, pipe);
7303
7304         /* Set up Tx target for periodic Rcomp update */
7305         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7306
7307         /* Disable target IRef on PLL */
7308         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7309         reg_val &= 0x00ffffff;
7310         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7311
7312         /* Disable fast lock */
7313         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7314
7315         /* Set idtafcrecal before PLL is enabled */
7316         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7317         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7318         mdiv |= ((bestn << DPIO_N_SHIFT));
7319         mdiv |= (1 << DPIO_K_SHIFT);
7320
7321         /*
7322          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7323          * but we don't support that).
7324          * Note: don't use the DAC post divider as it seems unstable.
7325          */
7326         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7327         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7328
7329         mdiv |= DPIO_ENABLE_CALIBRATION;
7330         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7331
7332         /* Set HBR and RBR LPF coefficients */
7333         if (pipe_config->port_clock == 162000 ||
7334             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7335             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7336                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7337                                  0x009f0003);
7338         else
7339                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7340                                  0x00d0000f);
7341
7342         if (pipe_config->has_dp_encoder) {
7343                 /* Use SSC source */
7344                 if (pipe == PIPE_A)
7345                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7346                                          0x0df40000);
7347                 else
7348                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7349                                          0x0df70000);
7350         } else { /* HDMI or VGA */
7351                 /* Use bend source */
7352                 if (pipe == PIPE_A)
7353                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7354                                          0x0df70000);
7355                 else
7356                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7357                                          0x0df40000);
7358         }
7359
7360         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7361         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7363             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7364                 coreclk |= 0x01000000;
7365         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7366
7367         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7368         mutex_unlock(&dev_priv->sb_lock);
7369 }
7370
7371 static void chv_compute_dpll(struct intel_crtc *crtc,
7372                              struct intel_crtc_state *pipe_config)
7373 {
7374         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7375                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7376                 DPLL_VCO_ENABLE;
7377         if (crtc->pipe != PIPE_A)
7378                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7379
7380         pipe_config->dpll_hw_state.dpll_md =
7381                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7382 }
7383
7384 static void chv_prepare_pll(struct intel_crtc *crtc,
7385                             const struct intel_crtc_state *pipe_config)
7386 {
7387         struct drm_device *dev = crtc->base.dev;
7388         struct drm_i915_private *dev_priv = dev->dev_private;
7389         int pipe = crtc->pipe;
7390         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7391         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7392         u32 loopfilter, tribuf_calcntr;
7393         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7394         u32 dpio_val;
7395         int vco;
7396
7397         bestn = pipe_config->dpll.n;
7398         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7399         bestm1 = pipe_config->dpll.m1;
7400         bestm2 = pipe_config->dpll.m2 >> 22;
7401         bestp1 = pipe_config->dpll.p1;
7402         bestp2 = pipe_config->dpll.p2;
7403         vco = pipe_config->dpll.vco;
7404         dpio_val = 0;
7405         loopfilter = 0;
7406
7407         /*
7408          * Enable Refclk and SSC
7409          */
7410         I915_WRITE(dpll_reg,
7411                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7412
7413         mutex_lock(&dev_priv->sb_lock);
7414
7415         /* p1 and p2 divider */
7416         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7417                         5 << DPIO_CHV_S1_DIV_SHIFT |
7418                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7419                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7420                         1 << DPIO_CHV_K_DIV_SHIFT);
7421
7422         /* Feedback post-divider - m2 */
7423         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7424
7425         /* Feedback refclk divider - n and m1 */
7426         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7427                         DPIO_CHV_M1_DIV_BY_2 |
7428                         1 << DPIO_CHV_N_DIV_SHIFT);
7429
7430         /* M2 fraction division */
7431         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7432
7433         /* M2 fraction division enable */
7434         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7435         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7436         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7437         if (bestm2_frac)
7438                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7439         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7440
7441         /* Program digital lock detect threshold */
7442         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7443         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7444                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7445         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7446         if (!bestm2_frac)
7447                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7448         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7449
7450         /* Loop filter */
7451         if (vco == 5400000) {
7452                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7453                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7454                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7455                 tribuf_calcntr = 0x9;
7456         } else if (vco <= 6200000) {
7457                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7458                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7459                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7460                 tribuf_calcntr = 0x9;
7461         } else if (vco <= 6480000) {
7462                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7463                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7464                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7465                 tribuf_calcntr = 0x8;
7466         } else {
7467                 /* Not supported. Apply the same limits as in the max case */
7468                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7469                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7470                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7471                 tribuf_calcntr = 0;
7472         }
7473         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7474
7475         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7476         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7477         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7478         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7479
7480         /* AFC Recal */
7481         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7482                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7483                         DPIO_AFC_RECAL);
7484
7485         mutex_unlock(&dev_priv->sb_lock);
7486 }
7487
7488 /**
7489  * vlv_force_pll_on - forcibly enable just the PLL
7490  * @dev_priv: i915 private structure
7491  * @pipe: pipe PLL to enable
7492  * @dpll: PLL configuration
7493  *
7494  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7495  * in cases where we need the PLL enabled even when @pipe is not going to
7496  * be enabled.
7497  */
7498 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7499                      const struct dpll *dpll)
7500 {
7501         struct intel_crtc *crtc =
7502                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7503         struct intel_crtc_state *pipe_config;
7504
7505         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7506         if (!pipe_config)
7507                 return -ENOMEM;
7508
7509         pipe_config->base.crtc = &crtc->base;
7510         pipe_config->pixel_multiplier = 1;
7511         pipe_config->dpll = *dpll;
7512
7513         if (IS_CHERRYVIEW(dev)) {
7514                 chv_compute_dpll(crtc, pipe_config);
7515                 chv_prepare_pll(crtc, pipe_config);
7516                 chv_enable_pll(crtc, pipe_config);
7517         } else {
7518                 vlv_compute_dpll(crtc, pipe_config);
7519                 vlv_prepare_pll(crtc, pipe_config);
7520                 vlv_enable_pll(crtc, pipe_config);
7521         }
7522
7523         kfree(pipe_config);
7524
7525         return 0;
7526 }
7527
7528 /**
7529  * vlv_force_pll_off - forcibly disable just the PLL
7530  * @dev_priv: i915 private structure
7531  * @pipe: pipe PLL to disable
7532  *
7533  * Disable the PLL for @pipe. To be used in cases where we need
7534  * the PLL enabled even when @pipe is not going to be enabled.
7535  */
7536 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7537 {
7538         if (IS_CHERRYVIEW(dev))
7539                 chv_disable_pll(to_i915(dev), pipe);
7540         else
7541                 vlv_disable_pll(to_i915(dev), pipe);
7542 }
7543
7544 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7545                               struct intel_crtc_state *crtc_state,
7546                               intel_clock_t *reduced_clock,
7547                               int num_connectors)
7548 {
7549         struct drm_device *dev = crtc->base.dev;
7550         struct drm_i915_private *dev_priv = dev->dev_private;
7551         u32 dpll;
7552         bool is_sdvo;
7553         struct dpll *clock = &crtc_state->dpll;
7554
7555         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7556
7557         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7558                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7559
7560         dpll = DPLL_VGA_MODE_DIS;
7561
7562         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7563                 dpll |= DPLLB_MODE_LVDS;
7564         else
7565                 dpll |= DPLLB_MODE_DAC_SERIAL;
7566
7567         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7568                 dpll |= (crtc_state->pixel_multiplier - 1)
7569                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7570         }
7571
7572         if (is_sdvo)
7573                 dpll |= DPLL_SDVO_HIGH_SPEED;
7574
7575         if (crtc_state->has_dp_encoder)
7576                 dpll |= DPLL_SDVO_HIGH_SPEED;
7577
7578         /* compute bitmask from p1 value */
7579         if (IS_PINEVIEW(dev))
7580                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7581         else {
7582                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7583                 if (IS_G4X(dev) && reduced_clock)
7584                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7585         }
7586         switch (clock->p2) {
7587         case 5:
7588                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7589                 break;
7590         case 7:
7591                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7592                 break;
7593         case 10:
7594                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7595                 break;
7596         case 14:
7597                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7598                 break;
7599         }
7600         if (INTEL_INFO(dev)->gen >= 4)
7601                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7602
7603         if (crtc_state->sdvo_tv_clock)
7604                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7605         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7606                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7607                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7608         else
7609                 dpll |= PLL_REF_INPUT_DREFCLK;
7610
7611         dpll |= DPLL_VCO_ENABLE;
7612         crtc_state->dpll_hw_state.dpll = dpll;
7613
7614         if (INTEL_INFO(dev)->gen >= 4) {
7615                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7616                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7617                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7618         }
7619 }
7620
7621 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7622                               struct intel_crtc_state *crtc_state,
7623                               intel_clock_t *reduced_clock,
7624                               int num_connectors)
7625 {
7626         struct drm_device *dev = crtc->base.dev;
7627         struct drm_i915_private *dev_priv = dev->dev_private;
7628         u32 dpll;
7629         struct dpll *clock = &crtc_state->dpll;
7630
7631         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7632
7633         dpll = DPLL_VGA_MODE_DIS;
7634
7635         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7636                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7637         } else {
7638                 if (clock->p1 == 2)
7639                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7640                 else
7641                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7642                 if (clock->p2 == 4)
7643                         dpll |= PLL_P2_DIVIDE_BY_4;
7644         }
7645
7646         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7647                 dpll |= DPLL_DVO_2X_MODE;
7648
7649         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7650                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7651                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7652         else
7653                 dpll |= PLL_REF_INPUT_DREFCLK;
7654
7655         dpll |= DPLL_VCO_ENABLE;
7656         crtc_state->dpll_hw_state.dpll = dpll;
7657 }
7658
7659 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7660 {
7661         struct drm_device *dev = intel_crtc->base.dev;
7662         struct drm_i915_private *dev_priv = dev->dev_private;
7663         enum pipe pipe = intel_crtc->pipe;
7664         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7665         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7666         uint32_t crtc_vtotal, crtc_vblank_end;
7667         int vsyncshift = 0;
7668
7669         /* We need to be careful not to changed the adjusted mode, for otherwise
7670          * the hw state checker will get angry at the mismatch. */
7671         crtc_vtotal = adjusted_mode->crtc_vtotal;
7672         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7673
7674         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7675                 /* the chip adds 2 halflines automatically */
7676                 crtc_vtotal -= 1;
7677                 crtc_vblank_end -= 1;
7678
7679                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7680                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7681                 else
7682                         vsyncshift = adjusted_mode->crtc_hsync_start -
7683                                 adjusted_mode->crtc_htotal / 2;
7684                 if (vsyncshift < 0)
7685                         vsyncshift += adjusted_mode->crtc_htotal;
7686         }
7687
7688         if (INTEL_INFO(dev)->gen > 3)
7689                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7690
7691         I915_WRITE(HTOTAL(cpu_transcoder),
7692                    (adjusted_mode->crtc_hdisplay - 1) |
7693                    ((adjusted_mode->crtc_htotal - 1) << 16));
7694         I915_WRITE(HBLANK(cpu_transcoder),
7695                    (adjusted_mode->crtc_hblank_start - 1) |
7696                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7697         I915_WRITE(HSYNC(cpu_transcoder),
7698                    (adjusted_mode->crtc_hsync_start - 1) |
7699                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7700
7701         I915_WRITE(VTOTAL(cpu_transcoder),
7702                    (adjusted_mode->crtc_vdisplay - 1) |
7703                    ((crtc_vtotal - 1) << 16));
7704         I915_WRITE(VBLANK(cpu_transcoder),
7705                    (adjusted_mode->crtc_vblank_start - 1) |
7706                    ((crtc_vblank_end - 1) << 16));
7707         I915_WRITE(VSYNC(cpu_transcoder),
7708                    (adjusted_mode->crtc_vsync_start - 1) |
7709                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7710
7711         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7712          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7713          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7714          * bits. */
7715         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7716             (pipe == PIPE_B || pipe == PIPE_C))
7717                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7718
7719         /* pipesrc controls the size that is scaled from, which should
7720          * always be the user's requested size.
7721          */
7722         I915_WRITE(PIPESRC(pipe),
7723                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7724                    (intel_crtc->config->pipe_src_h - 1));
7725 }
7726
7727 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7728                                    struct intel_crtc_state *pipe_config)
7729 {
7730         struct drm_device *dev = crtc->base.dev;
7731         struct drm_i915_private *dev_priv = dev->dev_private;
7732         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7733         uint32_t tmp;
7734
7735         tmp = I915_READ(HTOTAL(cpu_transcoder));
7736         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7737         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7738         tmp = I915_READ(HBLANK(cpu_transcoder));
7739         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7740         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7741         tmp = I915_READ(HSYNC(cpu_transcoder));
7742         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7743         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7744
7745         tmp = I915_READ(VTOTAL(cpu_transcoder));
7746         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7747         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7748         tmp = I915_READ(VBLANK(cpu_transcoder));
7749         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7750         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7751         tmp = I915_READ(VSYNC(cpu_transcoder));
7752         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7753         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7754
7755         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7756                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7757                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7758                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7759         }
7760
7761         tmp = I915_READ(PIPESRC(crtc->pipe));
7762         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7763         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7764
7765         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7766         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7767 }
7768
7769 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7770                                  struct intel_crtc_state *pipe_config)
7771 {
7772         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7773         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7774         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7775         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7776
7777         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7778         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7779         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7780         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7781
7782         mode->flags = pipe_config->base.adjusted_mode.flags;
7783         mode->type = DRM_MODE_TYPE_DRIVER;
7784
7785         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7786         mode->flags |= pipe_config->base.adjusted_mode.flags;
7787
7788         mode->hsync = drm_mode_hsync(mode);
7789         mode->vrefresh = drm_mode_vrefresh(mode);
7790         drm_mode_set_name(mode);
7791 }
7792
7793 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7794 {
7795         struct drm_device *dev = intel_crtc->base.dev;
7796         struct drm_i915_private *dev_priv = dev->dev_private;
7797         uint32_t pipeconf;
7798
7799         pipeconf = 0;
7800
7801         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7802             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7803                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7804
7805         if (intel_crtc->config->double_wide)
7806                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7807
7808         /* only g4x and later have fancy bpc/dither controls */
7809         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7810                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7811                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7812                         pipeconf |= PIPECONF_DITHER_EN |
7813                                     PIPECONF_DITHER_TYPE_SP;
7814
7815                 switch (intel_crtc->config->pipe_bpp) {
7816                 case 18:
7817                         pipeconf |= PIPECONF_6BPC;
7818                         break;
7819                 case 24:
7820                         pipeconf |= PIPECONF_8BPC;
7821                         break;
7822                 case 30:
7823                         pipeconf |= PIPECONF_10BPC;
7824                         break;
7825                 default:
7826                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7827                         BUG();
7828                 }
7829         }
7830
7831         if (HAS_PIPE_CXSR(dev)) {
7832                 if (intel_crtc->lowfreq_avail) {
7833                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7834                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7835                 } else {
7836                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7837                 }
7838         }
7839
7840         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7841                 if (INTEL_INFO(dev)->gen < 4 ||
7842                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7843                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7844                 else
7845                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7846         } else
7847                 pipeconf |= PIPECONF_PROGRESSIVE;
7848
7849         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7850              intel_crtc->config->limited_color_range)
7851                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7852
7853         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7854         POSTING_READ(PIPECONF(intel_crtc->pipe));
7855 }
7856
7857 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7858                                    struct intel_crtc_state *crtc_state)
7859 {
7860         struct drm_device *dev = crtc->base.dev;
7861         struct drm_i915_private *dev_priv = dev->dev_private;
7862         int refclk, num_connectors = 0;
7863         intel_clock_t clock;
7864         bool ok;
7865         const intel_limit_t *limit;
7866         struct drm_atomic_state *state = crtc_state->base.state;
7867         struct drm_connector *connector;
7868         struct drm_connector_state *connector_state;
7869         int i;
7870
7871         memset(&crtc_state->dpll_hw_state, 0,
7872                sizeof(crtc_state->dpll_hw_state));
7873
7874         if (crtc_state->has_dsi_encoder)
7875                 return 0;
7876
7877         for_each_connector_in_state(state, connector, connector_state, i) {
7878                 if (connector_state->crtc == &crtc->base)
7879                         num_connectors++;
7880         }
7881
7882         if (!crtc_state->clock_set) {
7883                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7884
7885                 /*
7886                  * Returns a set of divisors for the desired target clock with
7887                  * the given refclk, or FALSE.  The returned values represent
7888                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7889                  * 2) / p1 / p2.
7890                  */
7891                 limit = intel_limit(crtc_state, refclk);
7892                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7893                                                  crtc_state->port_clock,
7894                                                  refclk, NULL, &clock);
7895                 if (!ok) {
7896                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7897                         return -EINVAL;
7898                 }
7899
7900                 /* Compat-code for transition, will disappear. */
7901                 crtc_state->dpll.n = clock.n;
7902                 crtc_state->dpll.m1 = clock.m1;
7903                 crtc_state->dpll.m2 = clock.m2;
7904                 crtc_state->dpll.p1 = clock.p1;
7905                 crtc_state->dpll.p2 = clock.p2;
7906         }
7907
7908         if (IS_GEN2(dev)) {
7909                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7910                                   num_connectors);
7911         } else if (IS_CHERRYVIEW(dev)) {
7912                 chv_compute_dpll(crtc, crtc_state);
7913         } else if (IS_VALLEYVIEW(dev)) {
7914                 vlv_compute_dpll(crtc, crtc_state);
7915         } else {
7916                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7917                                   num_connectors);
7918         }
7919
7920         return 0;
7921 }
7922
7923 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7924                                  struct intel_crtc_state *pipe_config)
7925 {
7926         struct drm_device *dev = crtc->base.dev;
7927         struct drm_i915_private *dev_priv = dev->dev_private;
7928         uint32_t tmp;
7929
7930         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7931                 return;
7932
7933         tmp = I915_READ(PFIT_CONTROL);
7934         if (!(tmp & PFIT_ENABLE))
7935                 return;
7936
7937         /* Check whether the pfit is attached to our pipe. */
7938         if (INTEL_INFO(dev)->gen < 4) {
7939                 if (crtc->pipe != PIPE_B)
7940                         return;
7941         } else {
7942                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7943                         return;
7944         }
7945
7946         pipe_config->gmch_pfit.control = tmp;
7947         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7948         if (INTEL_INFO(dev)->gen < 5)
7949                 pipe_config->gmch_pfit.lvds_border_bits =
7950                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7951 }
7952
7953 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7954                                struct intel_crtc_state *pipe_config)
7955 {
7956         struct drm_device *dev = crtc->base.dev;
7957         struct drm_i915_private *dev_priv = dev->dev_private;
7958         int pipe = pipe_config->cpu_transcoder;
7959         intel_clock_t clock;
7960         u32 mdiv;
7961         int refclk = 100000;
7962
7963         /* In case of MIPI DPLL will not even be used */
7964         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7965                 return;
7966
7967         mutex_lock(&dev_priv->sb_lock);
7968         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7969         mutex_unlock(&dev_priv->sb_lock);
7970
7971         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7972         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7973         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7974         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7975         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7976
7977         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7978 }
7979
7980 static void
7981 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7982                               struct intel_initial_plane_config *plane_config)
7983 {
7984         struct drm_device *dev = crtc->base.dev;
7985         struct drm_i915_private *dev_priv = dev->dev_private;
7986         u32 val, base, offset;
7987         int pipe = crtc->pipe, plane = crtc->plane;
7988         int fourcc, pixel_format;
7989         unsigned int aligned_height;
7990         struct drm_framebuffer *fb;
7991         struct intel_framebuffer *intel_fb;
7992
7993         val = I915_READ(DSPCNTR(plane));
7994         if (!(val & DISPLAY_PLANE_ENABLE))
7995                 return;
7996
7997         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7998         if (!intel_fb) {
7999                 DRM_DEBUG_KMS("failed to alloc fb\n");
8000                 return;
8001         }
8002
8003         fb = &intel_fb->base;
8004
8005         if (INTEL_INFO(dev)->gen >= 4) {
8006                 if (val & DISPPLANE_TILED) {
8007                         plane_config->tiling = I915_TILING_X;
8008                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8009                 }
8010         }
8011
8012         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8013         fourcc = i9xx_format_to_fourcc(pixel_format);
8014         fb->pixel_format = fourcc;
8015         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8016
8017         if (INTEL_INFO(dev)->gen >= 4) {
8018                 if (plane_config->tiling)
8019                         offset = I915_READ(DSPTILEOFF(plane));
8020                 else
8021                         offset = I915_READ(DSPLINOFF(plane));
8022                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8023         } else {
8024                 base = I915_READ(DSPADDR(plane));
8025         }
8026         plane_config->base = base;
8027
8028         val = I915_READ(PIPESRC(pipe));
8029         fb->width = ((val >> 16) & 0xfff) + 1;
8030         fb->height = ((val >> 0) & 0xfff) + 1;
8031
8032         val = I915_READ(DSPSTRIDE(pipe));
8033         fb->pitches[0] = val & 0xffffffc0;
8034
8035         aligned_height = intel_fb_align_height(dev, fb->height,
8036                                                fb->pixel_format,
8037                                                fb->modifier[0]);
8038
8039         plane_config->size = fb->pitches[0] * aligned_height;
8040
8041         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8042                       pipe_name(pipe), plane, fb->width, fb->height,
8043                       fb->bits_per_pixel, base, fb->pitches[0],
8044                       plane_config->size);
8045
8046         plane_config->fb = intel_fb;
8047 }
8048
8049 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8050                                struct intel_crtc_state *pipe_config)
8051 {
8052         struct drm_device *dev = crtc->base.dev;
8053         struct drm_i915_private *dev_priv = dev->dev_private;
8054         int pipe = pipe_config->cpu_transcoder;
8055         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8056         intel_clock_t clock;
8057         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8058         int refclk = 100000;
8059
8060         mutex_lock(&dev_priv->sb_lock);
8061         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8062         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8063         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8064         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8065         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8066         mutex_unlock(&dev_priv->sb_lock);
8067
8068         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8069         clock.m2 = (pll_dw0 & 0xff) << 22;
8070         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8071                 clock.m2 |= pll_dw2 & 0x3fffff;
8072         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8073         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8074         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8075
8076         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8077 }
8078
8079 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8080                                  struct intel_crtc_state *pipe_config)
8081 {
8082         struct drm_device *dev = crtc->base.dev;
8083         struct drm_i915_private *dev_priv = dev->dev_private;
8084         enum intel_display_power_domain power_domain;
8085         uint32_t tmp;
8086         bool ret;
8087
8088         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8089         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8090                 return false;
8091
8092         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8093         pipe_config->shared_dpll = NULL;
8094
8095         ret = false;
8096
8097         tmp = I915_READ(PIPECONF(crtc->pipe));
8098         if (!(tmp & PIPECONF_ENABLE))
8099                 goto out;
8100
8101         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8102                 switch (tmp & PIPECONF_BPC_MASK) {
8103                 case PIPECONF_6BPC:
8104                         pipe_config->pipe_bpp = 18;
8105                         break;
8106                 case PIPECONF_8BPC:
8107                         pipe_config->pipe_bpp = 24;
8108                         break;
8109                 case PIPECONF_10BPC:
8110                         pipe_config->pipe_bpp = 30;
8111                         break;
8112                 default:
8113                         break;
8114                 }
8115         }
8116
8117         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8118             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8119                 pipe_config->limited_color_range = true;
8120
8121         if (INTEL_INFO(dev)->gen < 4)
8122                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8123
8124         intel_get_pipe_timings(crtc, pipe_config);
8125
8126         i9xx_get_pfit_config(crtc, pipe_config);
8127
8128         if (INTEL_INFO(dev)->gen >= 4) {
8129                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8130                 pipe_config->pixel_multiplier =
8131                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8132                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8133                 pipe_config->dpll_hw_state.dpll_md = tmp;
8134         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8135                 tmp = I915_READ(DPLL(crtc->pipe));
8136                 pipe_config->pixel_multiplier =
8137                         ((tmp & SDVO_MULTIPLIER_MASK)
8138                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8139         } else {
8140                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8141                  * port and will be fixed up in the encoder->get_config
8142                  * function. */
8143                 pipe_config->pixel_multiplier = 1;
8144         }
8145         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8146         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8147                 /*
8148                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8149                  * on 830. Filter it out here so that we don't
8150                  * report errors due to that.
8151                  */
8152                 if (IS_I830(dev))
8153                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8154
8155                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8156                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8157         } else {
8158                 /* Mask out read-only status bits. */
8159                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8160                                                      DPLL_PORTC_READY_MASK |
8161                                                      DPLL_PORTB_READY_MASK);
8162         }
8163
8164         if (IS_CHERRYVIEW(dev))
8165                 chv_crtc_clock_get(crtc, pipe_config);
8166         else if (IS_VALLEYVIEW(dev))
8167                 vlv_crtc_clock_get(crtc, pipe_config);
8168         else
8169                 i9xx_crtc_clock_get(crtc, pipe_config);
8170
8171         /*
8172          * Normally the dotclock is filled in by the encoder .get_config()
8173          * but in case the pipe is enabled w/o any ports we need a sane
8174          * default.
8175          */
8176         pipe_config->base.adjusted_mode.crtc_clock =
8177                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8178
8179         ret = true;
8180
8181 out:
8182         intel_display_power_put(dev_priv, power_domain);
8183
8184         return ret;
8185 }
8186
8187 static void ironlake_init_pch_refclk(struct drm_device *dev)
8188 {
8189         struct drm_i915_private *dev_priv = dev->dev_private;
8190         struct intel_encoder *encoder;
8191         u32 val, final;
8192         bool has_lvds = false;
8193         bool has_cpu_edp = false;
8194         bool has_panel = false;
8195         bool has_ck505 = false;
8196         bool can_ssc = false;
8197
8198         /* We need to take the global config into account */
8199         for_each_intel_encoder(dev, encoder) {
8200                 switch (encoder->type) {
8201                 case INTEL_OUTPUT_LVDS:
8202                         has_panel = true;
8203                         has_lvds = true;
8204                         break;
8205                 case INTEL_OUTPUT_EDP:
8206                         has_panel = true;
8207                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8208                                 has_cpu_edp = true;
8209                         break;
8210                 default:
8211                         break;
8212                 }
8213         }
8214
8215         if (HAS_PCH_IBX(dev)) {
8216                 has_ck505 = dev_priv->vbt.display_clock_mode;
8217                 can_ssc = has_ck505;
8218         } else {
8219                 has_ck505 = false;
8220                 can_ssc = true;
8221         }
8222
8223         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8224                       has_panel, has_lvds, has_ck505);
8225
8226         /* Ironlake: try to setup display ref clock before DPLL
8227          * enabling. This is only under driver's control after
8228          * PCH B stepping, previous chipset stepping should be
8229          * ignoring this setting.
8230          */
8231         val = I915_READ(PCH_DREF_CONTROL);
8232
8233         /* As we must carefully and slowly disable/enable each source in turn,
8234          * compute the final state we want first and check if we need to
8235          * make any changes at all.
8236          */
8237         final = val;
8238         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8239         if (has_ck505)
8240                 final |= DREF_NONSPREAD_CK505_ENABLE;
8241         else
8242                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8243
8244         final &= ~DREF_SSC_SOURCE_MASK;
8245         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8246         final &= ~DREF_SSC1_ENABLE;
8247
8248         if (has_panel) {
8249                 final |= DREF_SSC_SOURCE_ENABLE;
8250
8251                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8252                         final |= DREF_SSC1_ENABLE;
8253
8254                 if (has_cpu_edp) {
8255                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8256                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8257                         else
8258                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8259                 } else
8260                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8261         } else {
8262                 final |= DREF_SSC_SOURCE_DISABLE;
8263                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8264         }
8265
8266         if (final == val)
8267                 return;
8268
8269         /* Always enable nonspread source */
8270         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8271
8272         if (has_ck505)
8273                 val |= DREF_NONSPREAD_CK505_ENABLE;
8274         else
8275                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8276
8277         if (has_panel) {
8278                 val &= ~DREF_SSC_SOURCE_MASK;
8279                 val |= DREF_SSC_SOURCE_ENABLE;
8280
8281                 /* SSC must be turned on before enabling the CPU output  */
8282                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8283                         DRM_DEBUG_KMS("Using SSC on panel\n");
8284                         val |= DREF_SSC1_ENABLE;
8285                 } else
8286                         val &= ~DREF_SSC1_ENABLE;
8287
8288                 /* Get SSC going before enabling the outputs */
8289                 I915_WRITE(PCH_DREF_CONTROL, val);
8290                 POSTING_READ(PCH_DREF_CONTROL);
8291                 udelay(200);
8292
8293                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8294
8295                 /* Enable CPU source on CPU attached eDP */
8296                 if (has_cpu_edp) {
8297                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8298                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8299                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8300                         } else
8301                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8302                 } else
8303                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8304
8305                 I915_WRITE(PCH_DREF_CONTROL, val);
8306                 POSTING_READ(PCH_DREF_CONTROL);
8307                 udelay(200);
8308         } else {
8309                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8310
8311                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8312
8313                 /* Turn off CPU output */
8314                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8315
8316                 I915_WRITE(PCH_DREF_CONTROL, val);
8317                 POSTING_READ(PCH_DREF_CONTROL);
8318                 udelay(200);
8319
8320                 /* Turn off the SSC source */
8321                 val &= ~DREF_SSC_SOURCE_MASK;
8322                 val |= DREF_SSC_SOURCE_DISABLE;
8323
8324                 /* Turn off SSC1 */
8325                 val &= ~DREF_SSC1_ENABLE;
8326
8327                 I915_WRITE(PCH_DREF_CONTROL, val);
8328                 POSTING_READ(PCH_DREF_CONTROL);
8329                 udelay(200);
8330         }
8331
8332         BUG_ON(val != final);
8333 }
8334
8335 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8336 {
8337         uint32_t tmp;
8338
8339         tmp = I915_READ(SOUTH_CHICKEN2);
8340         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8341         I915_WRITE(SOUTH_CHICKEN2, tmp);
8342
8343         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8344                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8345                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8346
8347         tmp = I915_READ(SOUTH_CHICKEN2);
8348         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8349         I915_WRITE(SOUTH_CHICKEN2, tmp);
8350
8351         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8352                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8353                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8354 }
8355
8356 /* WaMPhyProgramming:hsw */
8357 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8358 {
8359         uint32_t tmp;
8360
8361         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8362         tmp &= ~(0xFF << 24);
8363         tmp |= (0x12 << 24);
8364         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8365
8366         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8367         tmp |= (1 << 11);
8368         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8369
8370         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8371         tmp |= (1 << 11);
8372         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8373
8374         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8375         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8376         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8377
8378         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8379         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8380         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8381
8382         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8383         tmp &= ~(7 << 13);
8384         tmp |= (5 << 13);
8385         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8386
8387         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8388         tmp &= ~(7 << 13);
8389         tmp |= (5 << 13);
8390         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8391
8392         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8393         tmp &= ~0xFF;
8394         tmp |= 0x1C;
8395         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8396
8397         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8398         tmp &= ~0xFF;
8399         tmp |= 0x1C;
8400         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8401
8402         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8403         tmp &= ~(0xFF << 16);
8404         tmp |= (0x1C << 16);
8405         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8406
8407         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8408         tmp &= ~(0xFF << 16);
8409         tmp |= (0x1C << 16);
8410         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8411
8412         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8413         tmp |= (1 << 27);
8414         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8415
8416         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8417         tmp |= (1 << 27);
8418         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8419
8420         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8421         tmp &= ~(0xF << 28);
8422         tmp |= (4 << 28);
8423         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8424
8425         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8426         tmp &= ~(0xF << 28);
8427         tmp |= (4 << 28);
8428         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8429 }
8430
8431 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8432  * Programming" based on the parameters passed:
8433  * - Sequence to enable CLKOUT_DP
8434  * - Sequence to enable CLKOUT_DP without spread
8435  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8436  */
8437 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8438                                  bool with_fdi)
8439 {
8440         struct drm_i915_private *dev_priv = dev->dev_private;
8441         uint32_t reg, tmp;
8442
8443         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8444                 with_spread = true;
8445         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8446                 with_fdi = false;
8447
8448         mutex_lock(&dev_priv->sb_lock);
8449
8450         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8451         tmp &= ~SBI_SSCCTL_DISABLE;
8452         tmp |= SBI_SSCCTL_PATHALT;
8453         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8454
8455         udelay(24);
8456
8457         if (with_spread) {
8458                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8459                 tmp &= ~SBI_SSCCTL_PATHALT;
8460                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8461
8462                 if (with_fdi) {
8463                         lpt_reset_fdi_mphy(dev_priv);
8464                         lpt_program_fdi_mphy(dev_priv);
8465                 }
8466         }
8467
8468         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8469         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8470         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8471         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8472
8473         mutex_unlock(&dev_priv->sb_lock);
8474 }
8475
8476 /* Sequence to disable CLKOUT_DP */
8477 static void lpt_disable_clkout_dp(struct drm_device *dev)
8478 {
8479         struct drm_i915_private *dev_priv = dev->dev_private;
8480         uint32_t reg, tmp;
8481
8482         mutex_lock(&dev_priv->sb_lock);
8483
8484         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8485         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8486         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8487         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8488
8489         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8490         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8491                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8492                         tmp |= SBI_SSCCTL_PATHALT;
8493                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8494                         udelay(32);
8495                 }
8496                 tmp |= SBI_SSCCTL_DISABLE;
8497                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8498         }
8499
8500         mutex_unlock(&dev_priv->sb_lock);
8501 }
8502
8503 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8504
8505 static const uint16_t sscdivintphase[] = {
8506         [BEND_IDX( 50)] = 0x3B23,
8507         [BEND_IDX( 45)] = 0x3B23,
8508         [BEND_IDX( 40)] = 0x3C23,
8509         [BEND_IDX( 35)] = 0x3C23,
8510         [BEND_IDX( 30)] = 0x3D23,
8511         [BEND_IDX( 25)] = 0x3D23,
8512         [BEND_IDX( 20)] = 0x3E23,
8513         [BEND_IDX( 15)] = 0x3E23,
8514         [BEND_IDX( 10)] = 0x3F23,
8515         [BEND_IDX(  5)] = 0x3F23,
8516         [BEND_IDX(  0)] = 0x0025,
8517         [BEND_IDX( -5)] = 0x0025,
8518         [BEND_IDX(-10)] = 0x0125,
8519         [BEND_IDX(-15)] = 0x0125,
8520         [BEND_IDX(-20)] = 0x0225,
8521         [BEND_IDX(-25)] = 0x0225,
8522         [BEND_IDX(-30)] = 0x0325,
8523         [BEND_IDX(-35)] = 0x0325,
8524         [BEND_IDX(-40)] = 0x0425,
8525         [BEND_IDX(-45)] = 0x0425,
8526         [BEND_IDX(-50)] = 0x0525,
8527 };
8528
8529 /*
8530  * Bend CLKOUT_DP
8531  * steps -50 to 50 inclusive, in steps of 5
8532  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8533  * change in clock period = -(steps / 10) * 5.787 ps
8534  */
8535 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8536 {
8537         uint32_t tmp;
8538         int idx = BEND_IDX(steps);
8539
8540         if (WARN_ON(steps % 5 != 0))
8541                 return;
8542
8543         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8544                 return;
8545
8546         mutex_lock(&dev_priv->sb_lock);
8547
8548         if (steps % 10 != 0)
8549                 tmp = 0xAAAAAAAB;
8550         else
8551                 tmp = 0x00000000;
8552         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8553
8554         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8555         tmp &= 0xffff0000;
8556         tmp |= sscdivintphase[idx];
8557         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8558
8559         mutex_unlock(&dev_priv->sb_lock);
8560 }
8561
8562 #undef BEND_IDX
8563
8564 static void lpt_init_pch_refclk(struct drm_device *dev)
8565 {
8566         struct intel_encoder *encoder;
8567         bool has_vga = false;
8568
8569         for_each_intel_encoder(dev, encoder) {
8570                 switch (encoder->type) {
8571                 case INTEL_OUTPUT_ANALOG:
8572                         has_vga = true;
8573                         break;
8574                 default:
8575                         break;
8576                 }
8577         }
8578
8579         if (has_vga) {
8580                 lpt_bend_clkout_dp(to_i915(dev), 0);
8581                 lpt_enable_clkout_dp(dev, true, true);
8582         } else {
8583                 lpt_disable_clkout_dp(dev);
8584         }
8585 }
8586
8587 /*
8588  * Initialize reference clocks when the driver loads
8589  */
8590 void intel_init_pch_refclk(struct drm_device *dev)
8591 {
8592         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8593                 ironlake_init_pch_refclk(dev);
8594         else if (HAS_PCH_LPT(dev))
8595                 lpt_init_pch_refclk(dev);
8596 }
8597
8598 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8599 {
8600         struct drm_device *dev = crtc_state->base.crtc->dev;
8601         struct drm_i915_private *dev_priv = dev->dev_private;
8602         struct drm_atomic_state *state = crtc_state->base.state;
8603         struct drm_connector *connector;
8604         struct drm_connector_state *connector_state;
8605         struct intel_encoder *encoder;
8606         int num_connectors = 0, i;
8607         bool is_lvds = false;
8608
8609         for_each_connector_in_state(state, connector, connector_state, i) {
8610                 if (connector_state->crtc != crtc_state->base.crtc)
8611                         continue;
8612
8613                 encoder = to_intel_encoder(connector_state->best_encoder);
8614
8615                 switch (encoder->type) {
8616                 case INTEL_OUTPUT_LVDS:
8617                         is_lvds = true;
8618                         break;
8619                 default:
8620                         break;
8621                 }
8622                 num_connectors++;
8623         }
8624
8625         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8626                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8627                               dev_priv->vbt.lvds_ssc_freq);
8628                 return dev_priv->vbt.lvds_ssc_freq;
8629         }
8630
8631         return 120000;
8632 }
8633
8634 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8635 {
8636         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8638         int pipe = intel_crtc->pipe;
8639         uint32_t val;
8640
8641         val = 0;
8642
8643         switch (intel_crtc->config->pipe_bpp) {
8644         case 18:
8645                 val |= PIPECONF_6BPC;
8646                 break;
8647         case 24:
8648                 val |= PIPECONF_8BPC;
8649                 break;
8650         case 30:
8651                 val |= PIPECONF_10BPC;
8652                 break;
8653         case 36:
8654                 val |= PIPECONF_12BPC;
8655                 break;
8656         default:
8657                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8658                 BUG();
8659         }
8660
8661         if (intel_crtc->config->dither)
8662                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8663
8664         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8665                 val |= PIPECONF_INTERLACED_ILK;
8666         else
8667                 val |= PIPECONF_PROGRESSIVE;
8668
8669         if (intel_crtc->config->limited_color_range)
8670                 val |= PIPECONF_COLOR_RANGE_SELECT;
8671
8672         I915_WRITE(PIPECONF(pipe), val);
8673         POSTING_READ(PIPECONF(pipe));
8674 }
8675
8676 /*
8677  * Set up the pipe CSC unit.
8678  *
8679  * Currently only full range RGB to limited range RGB conversion
8680  * is supported, but eventually this should handle various
8681  * RGB<->YCbCr scenarios as well.
8682  */
8683 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8684 {
8685         struct drm_device *dev = crtc->dev;
8686         struct drm_i915_private *dev_priv = dev->dev_private;
8687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8688         int pipe = intel_crtc->pipe;
8689         uint16_t coeff = 0x7800; /* 1.0 */
8690
8691         /*
8692          * TODO: Check what kind of values actually come out of the pipe
8693          * with these coeff/postoff values and adjust to get the best
8694          * accuracy. Perhaps we even need to take the bpc value into
8695          * consideration.
8696          */
8697
8698         if (intel_crtc->config->limited_color_range)
8699                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8700
8701         /*
8702          * GY/GU and RY/RU should be the other way around according
8703          * to BSpec, but reality doesn't agree. Just set them up in
8704          * a way that results in the correct picture.
8705          */
8706         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8707         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8708
8709         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8710         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8711
8712         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8713         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8714
8715         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8716         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8717         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8718
8719         if (INTEL_INFO(dev)->gen > 6) {
8720                 uint16_t postoff = 0;
8721
8722                 if (intel_crtc->config->limited_color_range)
8723                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8724
8725                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8726                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8727                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8728
8729                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8730         } else {
8731                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8732
8733                 if (intel_crtc->config->limited_color_range)
8734                         mode |= CSC_BLACK_SCREEN_OFFSET;
8735
8736                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8737         }
8738 }
8739
8740 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8741 {
8742         struct drm_device *dev = crtc->dev;
8743         struct drm_i915_private *dev_priv = dev->dev_private;
8744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8745         enum pipe pipe = intel_crtc->pipe;
8746         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8747         uint32_t val;
8748
8749         val = 0;
8750
8751         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8752                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8753
8754         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8755                 val |= PIPECONF_INTERLACED_ILK;
8756         else
8757                 val |= PIPECONF_PROGRESSIVE;
8758
8759         I915_WRITE(PIPECONF(cpu_transcoder), val);
8760         POSTING_READ(PIPECONF(cpu_transcoder));
8761
8762         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8763         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8764
8765         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8766                 val = 0;
8767
8768                 switch (intel_crtc->config->pipe_bpp) {
8769                 case 18:
8770                         val |= PIPEMISC_DITHER_6_BPC;
8771                         break;
8772                 case 24:
8773                         val |= PIPEMISC_DITHER_8_BPC;
8774                         break;
8775                 case 30:
8776                         val |= PIPEMISC_DITHER_10_BPC;
8777                         break;
8778                 case 36:
8779                         val |= PIPEMISC_DITHER_12_BPC;
8780                         break;
8781                 default:
8782                         /* Case prevented by pipe_config_set_bpp. */
8783                         BUG();
8784                 }
8785
8786                 if (intel_crtc->config->dither)
8787                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8788
8789                 I915_WRITE(PIPEMISC(pipe), val);
8790         }
8791 }
8792
8793 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8794                                     struct intel_crtc_state *crtc_state,
8795                                     intel_clock_t *clock,
8796                                     bool *has_reduced_clock,
8797                                     intel_clock_t *reduced_clock)
8798 {
8799         struct drm_device *dev = crtc->dev;
8800         struct drm_i915_private *dev_priv = dev->dev_private;
8801         int refclk;
8802         const intel_limit_t *limit;
8803         bool ret;
8804
8805         refclk = ironlake_get_refclk(crtc_state);
8806
8807         /*
8808          * Returns a set of divisors for the desired target clock with the given
8809          * refclk, or FALSE.  The returned values represent the clock equation:
8810          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8811          */
8812         limit = intel_limit(crtc_state, refclk);
8813         ret = dev_priv->display.find_dpll(limit, crtc_state,
8814                                           crtc_state->port_clock,
8815                                           refclk, NULL, clock);
8816         if (!ret)
8817                 return false;
8818
8819         return true;
8820 }
8821
8822 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8823 {
8824         /*
8825          * Account for spread spectrum to avoid
8826          * oversubscribing the link. Max center spread
8827          * is 2.5%; use 5% for safety's sake.
8828          */
8829         u32 bps = target_clock * bpp * 21 / 20;
8830         return DIV_ROUND_UP(bps, link_bw * 8);
8831 }
8832
8833 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8834 {
8835         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8836 }
8837
8838 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8839                                       struct intel_crtc_state *crtc_state,
8840                                       u32 *fp,
8841                                       intel_clock_t *reduced_clock, u32 *fp2)
8842 {
8843         struct drm_crtc *crtc = &intel_crtc->base;
8844         struct drm_device *dev = crtc->dev;
8845         struct drm_i915_private *dev_priv = dev->dev_private;
8846         struct drm_atomic_state *state = crtc_state->base.state;
8847         struct drm_connector *connector;
8848         struct drm_connector_state *connector_state;
8849         struct intel_encoder *encoder;
8850         uint32_t dpll;
8851         int factor, num_connectors = 0, i;
8852         bool is_lvds = false, is_sdvo = false;
8853
8854         for_each_connector_in_state(state, connector, connector_state, i) {
8855                 if (connector_state->crtc != crtc_state->base.crtc)
8856                         continue;
8857
8858                 encoder = to_intel_encoder(connector_state->best_encoder);
8859
8860                 switch (encoder->type) {
8861                 case INTEL_OUTPUT_LVDS:
8862                         is_lvds = true;
8863                         break;
8864                 case INTEL_OUTPUT_SDVO:
8865                 case INTEL_OUTPUT_HDMI:
8866                         is_sdvo = true;
8867                         break;
8868                 default:
8869                         break;
8870                 }
8871
8872                 num_connectors++;
8873         }
8874
8875         /* Enable autotuning of the PLL clock (if permissible) */
8876         factor = 21;
8877         if (is_lvds) {
8878                 if ((intel_panel_use_ssc(dev_priv) &&
8879                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8880                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8881                         factor = 25;
8882         } else if (crtc_state->sdvo_tv_clock)
8883                 factor = 20;
8884
8885         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8886                 *fp |= FP_CB_TUNE;
8887
8888         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8889                 *fp2 |= FP_CB_TUNE;
8890
8891         dpll = 0;
8892
8893         if (is_lvds)
8894                 dpll |= DPLLB_MODE_LVDS;
8895         else
8896                 dpll |= DPLLB_MODE_DAC_SERIAL;
8897
8898         dpll |= (crtc_state->pixel_multiplier - 1)
8899                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8900
8901         if (is_sdvo)
8902                 dpll |= DPLL_SDVO_HIGH_SPEED;
8903         if (crtc_state->has_dp_encoder)
8904                 dpll |= DPLL_SDVO_HIGH_SPEED;
8905
8906         /* compute bitmask from p1 value */
8907         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8908         /* also FPA1 */
8909         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8910
8911         switch (crtc_state->dpll.p2) {
8912         case 5:
8913                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8914                 break;
8915         case 7:
8916                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8917                 break;
8918         case 10:
8919                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8920                 break;
8921         case 14:
8922                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8923                 break;
8924         }
8925
8926         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8927                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8928         else
8929                 dpll |= PLL_REF_INPUT_DREFCLK;
8930
8931         return dpll | DPLL_VCO_ENABLE;
8932 }
8933
8934 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8935                                        struct intel_crtc_state *crtc_state)
8936 {
8937         struct drm_device *dev = crtc->base.dev;
8938         intel_clock_t clock, reduced_clock;
8939         u32 dpll = 0, fp = 0, fp2 = 0;
8940         bool ok, has_reduced_clock = false;
8941         bool is_lvds = false;
8942         struct intel_shared_dpll *pll;
8943
8944         memset(&crtc_state->dpll_hw_state, 0,
8945                sizeof(crtc_state->dpll_hw_state));
8946
8947         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8948
8949         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8950              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8951
8952         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8953                                      &has_reduced_clock, &reduced_clock);
8954         if (!ok && !crtc_state->clock_set) {
8955                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8956                 return -EINVAL;
8957         }
8958         /* Compat-code for transition, will disappear. */
8959         if (!crtc_state->clock_set) {
8960                 crtc_state->dpll.n = clock.n;
8961                 crtc_state->dpll.m1 = clock.m1;
8962                 crtc_state->dpll.m2 = clock.m2;
8963                 crtc_state->dpll.p1 = clock.p1;
8964                 crtc_state->dpll.p2 = clock.p2;
8965         }
8966
8967         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8968         if (crtc_state->has_pch_encoder) {
8969                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8970                 if (has_reduced_clock)
8971                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8972
8973                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8974                                              &fp, &reduced_clock,
8975                                              has_reduced_clock ? &fp2 : NULL);
8976
8977                 crtc_state->dpll_hw_state.dpll = dpll;
8978                 crtc_state->dpll_hw_state.fp0 = fp;
8979                 if (has_reduced_clock)
8980                         crtc_state->dpll_hw_state.fp1 = fp2;
8981                 else
8982                         crtc_state->dpll_hw_state.fp1 = fp;
8983
8984                 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8985                 if (pll == NULL) {
8986                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8987                                          pipe_name(crtc->pipe));
8988                         return -EINVAL;
8989                 }
8990         }
8991
8992         if (is_lvds && has_reduced_clock)
8993                 crtc->lowfreq_avail = true;
8994         else
8995                 crtc->lowfreq_avail = false;
8996
8997         return 0;
8998 }
8999
9000 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9001                                          struct intel_link_m_n *m_n)
9002 {
9003         struct drm_device *dev = crtc->base.dev;
9004         struct drm_i915_private *dev_priv = dev->dev_private;
9005         enum pipe pipe = crtc->pipe;
9006
9007         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9008         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9009         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9010                 & ~TU_SIZE_MASK;
9011         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9012         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9013                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9014 }
9015
9016 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9017                                          enum transcoder transcoder,
9018                                          struct intel_link_m_n *m_n,
9019                                          struct intel_link_m_n *m2_n2)
9020 {
9021         struct drm_device *dev = crtc->base.dev;
9022         struct drm_i915_private *dev_priv = dev->dev_private;
9023         enum pipe pipe = crtc->pipe;
9024
9025         if (INTEL_INFO(dev)->gen >= 5) {
9026                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9027                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9028                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9029                         & ~TU_SIZE_MASK;
9030                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9031                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9032                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9033                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9034                  * gen < 8) and if DRRS is supported (to make sure the
9035                  * registers are not unnecessarily read).
9036                  */
9037                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9038                         crtc->config->has_drrs) {
9039                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9040                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9041                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9042                                         & ~TU_SIZE_MASK;
9043                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9044                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9045                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9046                 }
9047         } else {
9048                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9049                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9050                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9051                         & ~TU_SIZE_MASK;
9052                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9053                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9054                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9055         }
9056 }
9057
9058 void intel_dp_get_m_n(struct intel_crtc *crtc,
9059                       struct intel_crtc_state *pipe_config)
9060 {
9061         if (pipe_config->has_pch_encoder)
9062                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9063         else
9064                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9065                                              &pipe_config->dp_m_n,
9066                                              &pipe_config->dp_m2_n2);
9067 }
9068
9069 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9070                                         struct intel_crtc_state *pipe_config)
9071 {
9072         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9073                                      &pipe_config->fdi_m_n, NULL);
9074 }
9075
9076 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9077                                     struct intel_crtc_state *pipe_config)
9078 {
9079         struct drm_device *dev = crtc->base.dev;
9080         struct drm_i915_private *dev_priv = dev->dev_private;
9081         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9082         uint32_t ps_ctrl = 0;
9083         int id = -1;
9084         int i;
9085
9086         /* find scaler attached to this pipe */
9087         for (i = 0; i < crtc->num_scalers; i++) {
9088                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9089                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9090                         id = i;
9091                         pipe_config->pch_pfit.enabled = true;
9092                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9093                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9094                         break;
9095                 }
9096         }
9097
9098         scaler_state->scaler_id = id;
9099         if (id >= 0) {
9100                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9101         } else {
9102                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9103         }
9104 }
9105
9106 static void
9107 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9108                                  struct intel_initial_plane_config *plane_config)
9109 {
9110         struct drm_device *dev = crtc->base.dev;
9111         struct drm_i915_private *dev_priv = dev->dev_private;
9112         u32 val, base, offset, stride_mult, tiling;
9113         int pipe = crtc->pipe;
9114         int fourcc, pixel_format;
9115         unsigned int aligned_height;
9116         struct drm_framebuffer *fb;
9117         struct intel_framebuffer *intel_fb;
9118
9119         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9120         if (!intel_fb) {
9121                 DRM_DEBUG_KMS("failed to alloc fb\n");
9122                 return;
9123         }
9124
9125         fb = &intel_fb->base;
9126
9127         val = I915_READ(PLANE_CTL(pipe, 0));
9128         if (!(val & PLANE_CTL_ENABLE))
9129                 goto error;
9130
9131         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9132         fourcc = skl_format_to_fourcc(pixel_format,
9133                                       val & PLANE_CTL_ORDER_RGBX,
9134                                       val & PLANE_CTL_ALPHA_MASK);
9135         fb->pixel_format = fourcc;
9136         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9137
9138         tiling = val & PLANE_CTL_TILED_MASK;
9139         switch (tiling) {
9140         case PLANE_CTL_TILED_LINEAR:
9141                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9142                 break;
9143         case PLANE_CTL_TILED_X:
9144                 plane_config->tiling = I915_TILING_X;
9145                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9146                 break;
9147         case PLANE_CTL_TILED_Y:
9148                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9149                 break;
9150         case PLANE_CTL_TILED_YF:
9151                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9152                 break;
9153         default:
9154                 MISSING_CASE(tiling);
9155                 goto error;
9156         }
9157
9158         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9159         plane_config->base = base;
9160
9161         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9162
9163         val = I915_READ(PLANE_SIZE(pipe, 0));
9164         fb->height = ((val >> 16) & 0xfff) + 1;
9165         fb->width = ((val >> 0) & 0x1fff) + 1;
9166
9167         val = I915_READ(PLANE_STRIDE(pipe, 0));
9168         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9169                                                 fb->pixel_format);
9170         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9171
9172         aligned_height = intel_fb_align_height(dev, fb->height,
9173                                                fb->pixel_format,
9174                                                fb->modifier[0]);
9175
9176         plane_config->size = fb->pitches[0] * aligned_height;
9177
9178         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9179                       pipe_name(pipe), fb->width, fb->height,
9180                       fb->bits_per_pixel, base, fb->pitches[0],
9181                       plane_config->size);
9182
9183         plane_config->fb = intel_fb;
9184         return;
9185
9186 error:
9187         kfree(fb);
9188 }
9189
9190 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9191                                      struct intel_crtc_state *pipe_config)
9192 {
9193         struct drm_device *dev = crtc->base.dev;
9194         struct drm_i915_private *dev_priv = dev->dev_private;
9195         uint32_t tmp;
9196
9197         tmp = I915_READ(PF_CTL(crtc->pipe));
9198
9199         if (tmp & PF_ENABLE) {
9200                 pipe_config->pch_pfit.enabled = true;
9201                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9202                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9203
9204                 /* We currently do not free assignements of panel fitters on
9205                  * ivb/hsw (since we don't use the higher upscaling modes which
9206                  * differentiates them) so just WARN about this case for now. */
9207                 if (IS_GEN7(dev)) {
9208                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9209                                 PF_PIPE_SEL_IVB(crtc->pipe));
9210                 }
9211         }
9212 }
9213
9214 static void
9215 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9216                                   struct intel_initial_plane_config *plane_config)
9217 {
9218         struct drm_device *dev = crtc->base.dev;
9219         struct drm_i915_private *dev_priv = dev->dev_private;
9220         u32 val, base, offset;
9221         int pipe = crtc->pipe;
9222         int fourcc, pixel_format;
9223         unsigned int aligned_height;
9224         struct drm_framebuffer *fb;
9225         struct intel_framebuffer *intel_fb;
9226
9227         val = I915_READ(DSPCNTR(pipe));
9228         if (!(val & DISPLAY_PLANE_ENABLE))
9229                 return;
9230
9231         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9232         if (!intel_fb) {
9233                 DRM_DEBUG_KMS("failed to alloc fb\n");
9234                 return;
9235         }
9236
9237         fb = &intel_fb->base;
9238
9239         if (INTEL_INFO(dev)->gen >= 4) {
9240                 if (val & DISPPLANE_TILED) {
9241                         plane_config->tiling = I915_TILING_X;
9242                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9243                 }
9244         }
9245
9246         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9247         fourcc = i9xx_format_to_fourcc(pixel_format);
9248         fb->pixel_format = fourcc;
9249         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9250
9251         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9252         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9253                 offset = I915_READ(DSPOFFSET(pipe));
9254         } else {
9255                 if (plane_config->tiling)
9256                         offset = I915_READ(DSPTILEOFF(pipe));
9257                 else
9258                         offset = I915_READ(DSPLINOFF(pipe));
9259         }
9260         plane_config->base = base;
9261
9262         val = I915_READ(PIPESRC(pipe));
9263         fb->width = ((val >> 16) & 0xfff) + 1;
9264         fb->height = ((val >> 0) & 0xfff) + 1;
9265
9266         val = I915_READ(DSPSTRIDE(pipe));
9267         fb->pitches[0] = val & 0xffffffc0;
9268
9269         aligned_height = intel_fb_align_height(dev, fb->height,
9270                                                fb->pixel_format,
9271                                                fb->modifier[0]);
9272
9273         plane_config->size = fb->pitches[0] * aligned_height;
9274
9275         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9276                       pipe_name(pipe), fb->width, fb->height,
9277                       fb->bits_per_pixel, base, fb->pitches[0],
9278                       plane_config->size);
9279
9280         plane_config->fb = intel_fb;
9281 }
9282
9283 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9284                                      struct intel_crtc_state *pipe_config)
9285 {
9286         struct drm_device *dev = crtc->base.dev;
9287         struct drm_i915_private *dev_priv = dev->dev_private;
9288         enum intel_display_power_domain power_domain;
9289         uint32_t tmp;
9290         bool ret;
9291
9292         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9293         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9294                 return false;
9295
9296         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9297         pipe_config->shared_dpll = NULL;
9298
9299         ret = false;
9300         tmp = I915_READ(PIPECONF(crtc->pipe));
9301         if (!(tmp & PIPECONF_ENABLE))
9302                 goto out;
9303
9304         switch (tmp & PIPECONF_BPC_MASK) {
9305         case PIPECONF_6BPC:
9306                 pipe_config->pipe_bpp = 18;
9307                 break;
9308         case PIPECONF_8BPC:
9309                 pipe_config->pipe_bpp = 24;
9310                 break;
9311         case PIPECONF_10BPC:
9312                 pipe_config->pipe_bpp = 30;
9313                 break;
9314         case PIPECONF_12BPC:
9315                 pipe_config->pipe_bpp = 36;
9316                 break;
9317         default:
9318                 break;
9319         }
9320
9321         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9322                 pipe_config->limited_color_range = true;
9323
9324         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9325                 struct intel_shared_dpll *pll;
9326                 enum intel_dpll_id pll_id;
9327
9328                 pipe_config->has_pch_encoder = true;
9329
9330                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9331                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9332                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9333
9334                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9335
9336                 if (HAS_PCH_IBX(dev_priv->dev)) {
9337                         pll_id = (enum intel_dpll_id) crtc->pipe;
9338                 } else {
9339                         tmp = I915_READ(PCH_DPLL_SEL);
9340                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9341                                 pll_id = DPLL_ID_PCH_PLL_B;
9342                         else
9343                                 pll_id= DPLL_ID_PCH_PLL_A;
9344                 }
9345
9346                 pipe_config->shared_dpll =
9347                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9348                 pll = pipe_config->shared_dpll;
9349
9350                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9351                                                  &pipe_config->dpll_hw_state));
9352
9353                 tmp = pipe_config->dpll_hw_state.dpll;
9354                 pipe_config->pixel_multiplier =
9355                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9356                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9357
9358                 ironlake_pch_clock_get(crtc, pipe_config);
9359         } else {
9360                 pipe_config->pixel_multiplier = 1;
9361         }
9362
9363         intel_get_pipe_timings(crtc, pipe_config);
9364
9365         ironlake_get_pfit_config(crtc, pipe_config);
9366
9367         ret = true;
9368
9369 out:
9370         intel_display_power_put(dev_priv, power_domain);
9371
9372         return ret;
9373 }
9374
9375 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9376 {
9377         struct drm_device *dev = dev_priv->dev;
9378         struct intel_crtc *crtc;
9379
9380         for_each_intel_crtc(dev, crtc)
9381                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9382                      pipe_name(crtc->pipe));
9383
9384         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9385         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9386         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9387         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9388         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9389         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9390              "CPU PWM1 enabled\n");
9391         if (IS_HASWELL(dev))
9392                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9393                      "CPU PWM2 enabled\n");
9394         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9395              "PCH PWM1 enabled\n");
9396         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9397              "Utility pin enabled\n");
9398         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9399
9400         /*
9401          * In theory we can still leave IRQs enabled, as long as only the HPD
9402          * interrupts remain enabled. We used to check for that, but since it's
9403          * gen-specific and since we only disable LCPLL after we fully disable
9404          * the interrupts, the check below should be enough.
9405          */
9406         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9407 }
9408
9409 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9410 {
9411         struct drm_device *dev = dev_priv->dev;
9412
9413         if (IS_HASWELL(dev))
9414                 return I915_READ(D_COMP_HSW);
9415         else
9416                 return I915_READ(D_COMP_BDW);
9417 }
9418
9419 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9420 {
9421         struct drm_device *dev = dev_priv->dev;
9422
9423         if (IS_HASWELL(dev)) {
9424                 mutex_lock(&dev_priv->rps.hw_lock);
9425                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9426                                             val))
9427                         DRM_ERROR("Failed to write to D_COMP\n");
9428                 mutex_unlock(&dev_priv->rps.hw_lock);
9429         } else {
9430                 I915_WRITE(D_COMP_BDW, val);
9431                 POSTING_READ(D_COMP_BDW);
9432         }
9433 }
9434
9435 /*
9436  * This function implements pieces of two sequences from BSpec:
9437  * - Sequence for display software to disable LCPLL
9438  * - Sequence for display software to allow package C8+
9439  * The steps implemented here are just the steps that actually touch the LCPLL
9440  * register. Callers should take care of disabling all the display engine
9441  * functions, doing the mode unset, fixing interrupts, etc.
9442  */
9443 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9444                               bool switch_to_fclk, bool allow_power_down)
9445 {
9446         uint32_t val;
9447
9448         assert_can_disable_lcpll(dev_priv);
9449
9450         val = I915_READ(LCPLL_CTL);
9451
9452         if (switch_to_fclk) {
9453                 val |= LCPLL_CD_SOURCE_FCLK;
9454                 I915_WRITE(LCPLL_CTL, val);
9455
9456                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9457                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9458                         DRM_ERROR("Switching to FCLK failed\n");
9459
9460                 val = I915_READ(LCPLL_CTL);
9461         }
9462
9463         val |= LCPLL_PLL_DISABLE;
9464         I915_WRITE(LCPLL_CTL, val);
9465         POSTING_READ(LCPLL_CTL);
9466
9467         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9468                 DRM_ERROR("LCPLL still locked\n");
9469
9470         val = hsw_read_dcomp(dev_priv);
9471         val |= D_COMP_COMP_DISABLE;
9472         hsw_write_dcomp(dev_priv, val);
9473         ndelay(100);
9474
9475         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9476                      1))
9477                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9478
9479         if (allow_power_down) {
9480                 val = I915_READ(LCPLL_CTL);
9481                 val |= LCPLL_POWER_DOWN_ALLOW;
9482                 I915_WRITE(LCPLL_CTL, val);
9483                 POSTING_READ(LCPLL_CTL);
9484         }
9485 }
9486
9487 /*
9488  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9489  * source.
9490  */
9491 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9492 {
9493         uint32_t val;
9494
9495         val = I915_READ(LCPLL_CTL);
9496
9497         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9498                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9499                 return;
9500
9501         /*
9502          * Make sure we're not on PC8 state before disabling PC8, otherwise
9503          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9504          */
9505         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9506
9507         if (val & LCPLL_POWER_DOWN_ALLOW) {
9508                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9509                 I915_WRITE(LCPLL_CTL, val);
9510                 POSTING_READ(LCPLL_CTL);
9511         }
9512
9513         val = hsw_read_dcomp(dev_priv);
9514         val |= D_COMP_COMP_FORCE;
9515         val &= ~D_COMP_COMP_DISABLE;
9516         hsw_write_dcomp(dev_priv, val);
9517
9518         val = I915_READ(LCPLL_CTL);
9519         val &= ~LCPLL_PLL_DISABLE;
9520         I915_WRITE(LCPLL_CTL, val);
9521
9522         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9523                 DRM_ERROR("LCPLL not locked yet\n");
9524
9525         if (val & LCPLL_CD_SOURCE_FCLK) {
9526                 val = I915_READ(LCPLL_CTL);
9527                 val &= ~LCPLL_CD_SOURCE_FCLK;
9528                 I915_WRITE(LCPLL_CTL, val);
9529
9530                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9531                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9532                         DRM_ERROR("Switching back to LCPLL failed\n");
9533         }
9534
9535         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9536         intel_update_cdclk(dev_priv->dev);
9537 }
9538
9539 /*
9540  * Package states C8 and deeper are really deep PC states that can only be
9541  * reached when all the devices on the system allow it, so even if the graphics
9542  * device allows PC8+, it doesn't mean the system will actually get to these
9543  * states. Our driver only allows PC8+ when going into runtime PM.
9544  *
9545  * The requirements for PC8+ are that all the outputs are disabled, the power
9546  * well is disabled and most interrupts are disabled, and these are also
9547  * requirements for runtime PM. When these conditions are met, we manually do
9548  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9549  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9550  * hang the machine.
9551  *
9552  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9553  * the state of some registers, so when we come back from PC8+ we need to
9554  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9555  * need to take care of the registers kept by RC6. Notice that this happens even
9556  * if we don't put the device in PCI D3 state (which is what currently happens
9557  * because of the runtime PM support).
9558  *
9559  * For more, read "Display Sequences for Package C8" on the hardware
9560  * documentation.
9561  */
9562 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9563 {
9564         struct drm_device *dev = dev_priv->dev;
9565         uint32_t val;
9566
9567         DRM_DEBUG_KMS("Enabling package C8+\n");
9568
9569         if (HAS_PCH_LPT_LP(dev)) {
9570                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9571                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9572                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9573         }
9574
9575         lpt_disable_clkout_dp(dev);
9576         hsw_disable_lcpll(dev_priv, true, true);
9577 }
9578
9579 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9580 {
9581         struct drm_device *dev = dev_priv->dev;
9582         uint32_t val;
9583
9584         DRM_DEBUG_KMS("Disabling package C8+\n");
9585
9586         hsw_restore_lcpll(dev_priv);
9587         lpt_init_pch_refclk(dev);
9588
9589         if (HAS_PCH_LPT_LP(dev)) {
9590                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9591                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9592                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9593         }
9594 }
9595
9596 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9597 {
9598         struct drm_device *dev = old_state->dev;
9599         struct intel_atomic_state *old_intel_state =
9600                 to_intel_atomic_state(old_state);
9601         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9602
9603         broxton_set_cdclk(dev, req_cdclk);
9604 }
9605
9606 /* compute the max rate for new configuration */
9607 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9608 {
9609         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9610         struct drm_i915_private *dev_priv = state->dev->dev_private;
9611         struct drm_crtc *crtc;
9612         struct drm_crtc_state *cstate;
9613         struct intel_crtc_state *crtc_state;
9614         unsigned max_pixel_rate = 0, i;
9615         enum pipe pipe;
9616
9617         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9618                sizeof(intel_state->min_pixclk));
9619
9620         for_each_crtc_in_state(state, crtc, cstate, i) {
9621                 int pixel_rate;
9622
9623                 crtc_state = to_intel_crtc_state(cstate);
9624                 if (!crtc_state->base.enable) {
9625                         intel_state->min_pixclk[i] = 0;
9626                         continue;
9627                 }
9628
9629                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9630
9631                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9632                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9633                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9634
9635                 intel_state->min_pixclk[i] = pixel_rate;
9636         }
9637
9638         for_each_pipe(dev_priv, pipe)
9639                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9640
9641         return max_pixel_rate;
9642 }
9643
9644 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9645 {
9646         struct drm_i915_private *dev_priv = dev->dev_private;
9647         uint32_t val, data;
9648         int ret;
9649
9650         if (WARN((I915_READ(LCPLL_CTL) &
9651                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9652                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9653                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9654                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9655                  "trying to change cdclk frequency with cdclk not enabled\n"))
9656                 return;
9657
9658         mutex_lock(&dev_priv->rps.hw_lock);
9659         ret = sandybridge_pcode_write(dev_priv,
9660                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9661         mutex_unlock(&dev_priv->rps.hw_lock);
9662         if (ret) {
9663                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9664                 return;
9665         }
9666
9667         val = I915_READ(LCPLL_CTL);
9668         val |= LCPLL_CD_SOURCE_FCLK;
9669         I915_WRITE(LCPLL_CTL, val);
9670
9671         if (wait_for_us(I915_READ(LCPLL_CTL) &
9672                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9673                 DRM_ERROR("Switching to FCLK failed\n");
9674
9675         val = I915_READ(LCPLL_CTL);
9676         val &= ~LCPLL_CLK_FREQ_MASK;
9677
9678         switch (cdclk) {
9679         case 450000:
9680                 val |= LCPLL_CLK_FREQ_450;
9681                 data = 0;
9682                 break;
9683         case 540000:
9684                 val |= LCPLL_CLK_FREQ_54O_BDW;
9685                 data = 1;
9686                 break;
9687         case 337500:
9688                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9689                 data = 2;
9690                 break;
9691         case 675000:
9692                 val |= LCPLL_CLK_FREQ_675_BDW;
9693                 data = 3;
9694                 break;
9695         default:
9696                 WARN(1, "invalid cdclk frequency\n");
9697                 return;
9698         }
9699
9700         I915_WRITE(LCPLL_CTL, val);
9701
9702         val = I915_READ(LCPLL_CTL);
9703         val &= ~LCPLL_CD_SOURCE_FCLK;
9704         I915_WRITE(LCPLL_CTL, val);
9705
9706         if (wait_for_us((I915_READ(LCPLL_CTL) &
9707                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9708                 DRM_ERROR("Switching back to LCPLL failed\n");
9709
9710         mutex_lock(&dev_priv->rps.hw_lock);
9711         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9712         mutex_unlock(&dev_priv->rps.hw_lock);
9713
9714         intel_update_cdclk(dev);
9715
9716         WARN(cdclk != dev_priv->cdclk_freq,
9717              "cdclk requested %d kHz but got %d kHz\n",
9718              cdclk, dev_priv->cdclk_freq);
9719 }
9720
9721 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9722 {
9723         struct drm_i915_private *dev_priv = to_i915(state->dev);
9724         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9725         int max_pixclk = ilk_max_pixel_rate(state);
9726         int cdclk;
9727
9728         /*
9729          * FIXME should also account for plane ratio
9730          * once 64bpp pixel formats are supported.
9731          */
9732         if (max_pixclk > 540000)
9733                 cdclk = 675000;
9734         else if (max_pixclk > 450000)
9735                 cdclk = 540000;
9736         else if (max_pixclk > 337500)
9737                 cdclk = 450000;
9738         else
9739                 cdclk = 337500;
9740
9741         if (cdclk > dev_priv->max_cdclk_freq) {
9742                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9743                               cdclk, dev_priv->max_cdclk_freq);
9744                 return -EINVAL;
9745         }
9746
9747         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9748         if (!intel_state->active_crtcs)
9749                 intel_state->dev_cdclk = 337500;
9750
9751         return 0;
9752 }
9753
9754 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9755 {
9756         struct drm_device *dev = old_state->dev;
9757         struct intel_atomic_state *old_intel_state =
9758                 to_intel_atomic_state(old_state);
9759         unsigned req_cdclk = old_intel_state->dev_cdclk;
9760
9761         broadwell_set_cdclk(dev, req_cdclk);
9762 }
9763
9764 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9765                                       struct intel_crtc_state *crtc_state)
9766 {
9767         struct intel_encoder *intel_encoder =
9768                 intel_ddi_get_crtc_new_encoder(crtc_state);
9769
9770         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9771                 if (!intel_ddi_pll_select(crtc, crtc_state))
9772                         return -EINVAL;
9773         }
9774
9775         crtc->lowfreq_avail = false;
9776
9777         return 0;
9778 }
9779
9780 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9781                                 enum port port,
9782                                 struct intel_crtc_state *pipe_config)
9783 {
9784         enum intel_dpll_id id;
9785
9786         switch (port) {
9787         case PORT_A:
9788                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9789                 id = DPLL_ID_SKL_DPLL0;
9790                 break;
9791         case PORT_B:
9792                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9793                 id = DPLL_ID_SKL_DPLL1;
9794                 break;
9795         case PORT_C:
9796                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9797                 id = DPLL_ID_SKL_DPLL2;
9798                 break;
9799         default:
9800                 DRM_ERROR("Incorrect port type\n");
9801                 return;
9802         }
9803
9804         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9805 }
9806
9807 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9808                                 enum port port,
9809                                 struct intel_crtc_state *pipe_config)
9810 {
9811         enum intel_dpll_id id;
9812         u32 temp;
9813
9814         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9815         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9816
9817         switch (pipe_config->ddi_pll_sel) {
9818         case SKL_DPLL0:
9819                 id = DPLL_ID_SKL_DPLL0;
9820                 break;
9821         case SKL_DPLL1:
9822                 id = DPLL_ID_SKL_DPLL1;
9823                 break;
9824         case SKL_DPLL2:
9825                 id = DPLL_ID_SKL_DPLL2;
9826                 break;
9827         case SKL_DPLL3:
9828                 id = DPLL_ID_SKL_DPLL3;
9829                 break;
9830         default:
9831                 MISSING_CASE(pipe_config->ddi_pll_sel);
9832                 return;
9833         }
9834
9835         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9836 }
9837
9838 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9839                                 enum port port,
9840                                 struct intel_crtc_state *pipe_config)
9841 {
9842         enum intel_dpll_id id;
9843
9844         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9845
9846         switch (pipe_config->ddi_pll_sel) {
9847         case PORT_CLK_SEL_WRPLL1:
9848                 id = DPLL_ID_WRPLL1;
9849                 break;
9850         case PORT_CLK_SEL_WRPLL2:
9851                 id = DPLL_ID_WRPLL2;
9852                 break;
9853         case PORT_CLK_SEL_SPLL:
9854                 id = DPLL_ID_SPLL;
9855                 break;
9856         case PORT_CLK_SEL_LCPLL_810:
9857                 id = DPLL_ID_LCPLL_810;
9858                 break;
9859         case PORT_CLK_SEL_LCPLL_1350:
9860                 id = DPLL_ID_LCPLL_1350;
9861                 break;
9862         case PORT_CLK_SEL_LCPLL_2700:
9863                 id = DPLL_ID_LCPLL_2700;
9864                 break;
9865         default:
9866                 MISSING_CASE(pipe_config->ddi_pll_sel);
9867                 /* fall through */
9868         case PORT_CLK_SEL_NONE:
9869                 return;
9870         }
9871
9872         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9873 }
9874
9875 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9876                                        struct intel_crtc_state *pipe_config)
9877 {
9878         struct drm_device *dev = crtc->base.dev;
9879         struct drm_i915_private *dev_priv = dev->dev_private;
9880         struct intel_shared_dpll *pll;
9881         enum port port;
9882         uint32_t tmp;
9883
9884         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9885
9886         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9887
9888         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9889                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9890         else if (IS_BROXTON(dev))
9891                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9892         else
9893                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9894
9895         pll = pipe_config->shared_dpll;
9896         if (pll) {
9897                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9898                                                  &pipe_config->dpll_hw_state));
9899         }
9900
9901         /*
9902          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9903          * DDI E. So just check whether this pipe is wired to DDI E and whether
9904          * the PCH transcoder is on.
9905          */
9906         if (INTEL_INFO(dev)->gen < 9 &&
9907             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9908                 pipe_config->has_pch_encoder = true;
9909
9910                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9911                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9912                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9913
9914                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9915         }
9916 }
9917
9918 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9919                                     struct intel_crtc_state *pipe_config)
9920 {
9921         struct drm_device *dev = crtc->base.dev;
9922         struct drm_i915_private *dev_priv = dev->dev_private;
9923         enum intel_display_power_domain power_domain;
9924         unsigned long power_domain_mask;
9925         uint32_t tmp;
9926         bool ret;
9927
9928         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9929         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9930                 return false;
9931         power_domain_mask = BIT(power_domain);
9932
9933         ret = false;
9934
9935         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9936         pipe_config->shared_dpll = NULL;
9937
9938         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9939         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9940                 enum pipe trans_edp_pipe;
9941                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9942                 default:
9943                         WARN(1, "unknown pipe linked to edp transcoder\n");
9944                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9945                 case TRANS_DDI_EDP_INPUT_A_ON:
9946                         trans_edp_pipe = PIPE_A;
9947                         break;
9948                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9949                         trans_edp_pipe = PIPE_B;
9950                         break;
9951                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9952                         trans_edp_pipe = PIPE_C;
9953                         break;
9954                 }
9955
9956                 if (trans_edp_pipe == crtc->pipe)
9957                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9958         }
9959
9960         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9961         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9962                 goto out;
9963         power_domain_mask |= BIT(power_domain);
9964
9965         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9966         if (!(tmp & PIPECONF_ENABLE))
9967                 goto out;
9968
9969         haswell_get_ddi_port_state(crtc, pipe_config);
9970
9971         intel_get_pipe_timings(crtc, pipe_config);
9972
9973         if (INTEL_INFO(dev)->gen >= 9) {
9974                 skl_init_scalers(dev, crtc, pipe_config);
9975         }
9976
9977         if (INTEL_INFO(dev)->gen >= 9) {
9978                 pipe_config->scaler_state.scaler_id = -1;
9979                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9980         }
9981
9982         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9983         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9984                 power_domain_mask |= BIT(power_domain);
9985                 if (INTEL_INFO(dev)->gen >= 9)
9986                         skylake_get_pfit_config(crtc, pipe_config);
9987                 else
9988                         ironlake_get_pfit_config(crtc, pipe_config);
9989         }
9990
9991         if (IS_HASWELL(dev))
9992                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9993                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9994
9995         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9996                 pipe_config->pixel_multiplier =
9997                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9998         } else {
9999                 pipe_config->pixel_multiplier = 1;
10000         }
10001
10002         ret = true;
10003
10004 out:
10005         for_each_power_domain(power_domain, power_domain_mask)
10006                 intel_display_power_put(dev_priv, power_domain);
10007
10008         return ret;
10009 }
10010
10011 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10012                                const struct intel_plane_state *plane_state)
10013 {
10014         struct drm_device *dev = crtc->dev;
10015         struct drm_i915_private *dev_priv = dev->dev_private;
10016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10017         uint32_t cntl = 0, size = 0;
10018
10019         if (plane_state && plane_state->visible) {
10020                 unsigned int width = plane_state->base.crtc_w;
10021                 unsigned int height = plane_state->base.crtc_h;
10022                 unsigned int stride = roundup_pow_of_two(width) * 4;
10023
10024                 switch (stride) {
10025                 default:
10026                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10027                                   width, stride);
10028                         stride = 256;
10029                         /* fallthrough */
10030                 case 256:
10031                 case 512:
10032                 case 1024:
10033                 case 2048:
10034                         break;
10035                 }
10036
10037                 cntl |= CURSOR_ENABLE |
10038                         CURSOR_GAMMA_ENABLE |
10039                         CURSOR_FORMAT_ARGB |
10040                         CURSOR_STRIDE(stride);
10041
10042                 size = (height << 12) | width;
10043         }
10044
10045         if (intel_crtc->cursor_cntl != 0 &&
10046             (intel_crtc->cursor_base != base ||
10047              intel_crtc->cursor_size != size ||
10048              intel_crtc->cursor_cntl != cntl)) {
10049                 /* On these chipsets we can only modify the base/size/stride
10050                  * whilst the cursor is disabled.
10051                  */
10052                 I915_WRITE(CURCNTR(PIPE_A), 0);
10053                 POSTING_READ(CURCNTR(PIPE_A));
10054                 intel_crtc->cursor_cntl = 0;
10055         }
10056
10057         if (intel_crtc->cursor_base != base) {
10058                 I915_WRITE(CURBASE(PIPE_A), base);
10059                 intel_crtc->cursor_base = base;
10060         }
10061
10062         if (intel_crtc->cursor_size != size) {
10063                 I915_WRITE(CURSIZE, size);
10064                 intel_crtc->cursor_size = size;
10065         }
10066
10067         if (intel_crtc->cursor_cntl != cntl) {
10068                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10069                 POSTING_READ(CURCNTR(PIPE_A));
10070                 intel_crtc->cursor_cntl = cntl;
10071         }
10072 }
10073
10074 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10075                                const struct intel_plane_state *plane_state)
10076 {
10077         struct drm_device *dev = crtc->dev;
10078         struct drm_i915_private *dev_priv = dev->dev_private;
10079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10080         int pipe = intel_crtc->pipe;
10081         uint32_t cntl = 0;
10082
10083         if (plane_state && plane_state->visible) {
10084                 cntl = MCURSOR_GAMMA_ENABLE;
10085                 switch (plane_state->base.crtc_w) {
10086                         case 64:
10087                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10088                                 break;
10089                         case 128:
10090                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10091                                 break;
10092                         case 256:
10093                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10094                                 break;
10095                         default:
10096                                 MISSING_CASE(plane_state->base.crtc_w);
10097                                 return;
10098                 }
10099                 cntl |= pipe << 28; /* Connect to correct pipe */
10100
10101                 if (HAS_DDI(dev))
10102                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10103
10104                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10105                         cntl |= CURSOR_ROTATE_180;
10106         }
10107
10108         if (intel_crtc->cursor_cntl != cntl) {
10109                 I915_WRITE(CURCNTR(pipe), cntl);
10110                 POSTING_READ(CURCNTR(pipe));
10111                 intel_crtc->cursor_cntl = cntl;
10112         }
10113
10114         /* and commit changes on next vblank */
10115         I915_WRITE(CURBASE(pipe), base);
10116         POSTING_READ(CURBASE(pipe));
10117
10118         intel_crtc->cursor_base = base;
10119 }
10120
10121 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10122 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10123                                      const struct intel_plane_state *plane_state)
10124 {
10125         struct drm_device *dev = crtc->dev;
10126         struct drm_i915_private *dev_priv = dev->dev_private;
10127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10128         int pipe = intel_crtc->pipe;
10129         u32 base = intel_crtc->cursor_addr;
10130         u32 pos = 0;
10131
10132         if (plane_state) {
10133                 int x = plane_state->base.crtc_x;
10134                 int y = plane_state->base.crtc_y;
10135
10136                 if (x < 0) {
10137                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10138                         x = -x;
10139                 }
10140                 pos |= x << CURSOR_X_SHIFT;
10141
10142                 if (y < 0) {
10143                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10144                         y = -y;
10145                 }
10146                 pos |= y << CURSOR_Y_SHIFT;
10147
10148                 /* ILK+ do this automagically */
10149                 if (HAS_GMCH_DISPLAY(dev) &&
10150                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10151                         base += (plane_state->base.crtc_h *
10152                                  plane_state->base.crtc_w - 1) * 4;
10153                 }
10154         }
10155
10156         I915_WRITE(CURPOS(pipe), pos);
10157
10158         if (IS_845G(dev) || IS_I865G(dev))
10159                 i845_update_cursor(crtc, base, plane_state);
10160         else
10161                 i9xx_update_cursor(crtc, base, plane_state);
10162 }
10163
10164 static bool cursor_size_ok(struct drm_device *dev,
10165                            uint32_t width, uint32_t height)
10166 {
10167         if (width == 0 || height == 0)
10168                 return false;
10169
10170         /*
10171          * 845g/865g are special in that they are only limited by
10172          * the width of their cursors, the height is arbitrary up to
10173          * the precision of the register. Everything else requires
10174          * square cursors, limited to a few power-of-two sizes.
10175          */
10176         if (IS_845G(dev) || IS_I865G(dev)) {
10177                 if ((width & 63) != 0)
10178                         return false;
10179
10180                 if (width > (IS_845G(dev) ? 64 : 512))
10181                         return false;
10182
10183                 if (height > 1023)
10184                         return false;
10185         } else {
10186                 switch (width | height) {
10187                 case 256:
10188                 case 128:
10189                         if (IS_GEN2(dev))
10190                                 return false;
10191                 case 64:
10192                         break;
10193                 default:
10194                         return false;
10195                 }
10196         }
10197
10198         return true;
10199 }
10200
10201 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10202                                  u16 *blue, uint32_t start, uint32_t size)
10203 {
10204         int end = (start + size > 256) ? 256 : start + size, i;
10205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10206
10207         for (i = start; i < end; i++) {
10208                 intel_crtc->lut_r[i] = red[i] >> 8;
10209                 intel_crtc->lut_g[i] = green[i] >> 8;
10210                 intel_crtc->lut_b[i] = blue[i] >> 8;
10211         }
10212
10213         intel_crtc_load_lut(crtc);
10214 }
10215
10216 /* VESA 640x480x72Hz mode to set on the pipe */
10217 static struct drm_display_mode load_detect_mode = {
10218         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10219                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10220 };
10221
10222 struct drm_framebuffer *
10223 __intel_framebuffer_create(struct drm_device *dev,
10224                            struct drm_mode_fb_cmd2 *mode_cmd,
10225                            struct drm_i915_gem_object *obj)
10226 {
10227         struct intel_framebuffer *intel_fb;
10228         int ret;
10229
10230         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10231         if (!intel_fb)
10232                 return ERR_PTR(-ENOMEM);
10233
10234         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10235         if (ret)
10236                 goto err;
10237
10238         return &intel_fb->base;
10239
10240 err:
10241         kfree(intel_fb);
10242         return ERR_PTR(ret);
10243 }
10244
10245 static struct drm_framebuffer *
10246 intel_framebuffer_create(struct drm_device *dev,
10247                          struct drm_mode_fb_cmd2 *mode_cmd,
10248                          struct drm_i915_gem_object *obj)
10249 {
10250         struct drm_framebuffer *fb;
10251         int ret;
10252
10253         ret = i915_mutex_lock_interruptible(dev);
10254         if (ret)
10255                 return ERR_PTR(ret);
10256         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10257         mutex_unlock(&dev->struct_mutex);
10258
10259         return fb;
10260 }
10261
10262 static u32
10263 intel_framebuffer_pitch_for_width(int width, int bpp)
10264 {
10265         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10266         return ALIGN(pitch, 64);
10267 }
10268
10269 static u32
10270 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10271 {
10272         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10273         return PAGE_ALIGN(pitch * mode->vdisplay);
10274 }
10275
10276 static struct drm_framebuffer *
10277 intel_framebuffer_create_for_mode(struct drm_device *dev,
10278                                   struct drm_display_mode *mode,
10279                                   int depth, int bpp)
10280 {
10281         struct drm_framebuffer *fb;
10282         struct drm_i915_gem_object *obj;
10283         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10284
10285         obj = i915_gem_alloc_object(dev,
10286                                     intel_framebuffer_size_for_mode(mode, bpp));
10287         if (obj == NULL)
10288                 return ERR_PTR(-ENOMEM);
10289
10290         mode_cmd.width = mode->hdisplay;
10291         mode_cmd.height = mode->vdisplay;
10292         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10293                                                                 bpp);
10294         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10295
10296         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10297         if (IS_ERR(fb))
10298                 drm_gem_object_unreference_unlocked(&obj->base);
10299
10300         return fb;
10301 }
10302
10303 static struct drm_framebuffer *
10304 mode_fits_in_fbdev(struct drm_device *dev,
10305                    struct drm_display_mode *mode)
10306 {
10307 #ifdef CONFIG_DRM_FBDEV_EMULATION
10308         struct drm_i915_private *dev_priv = dev->dev_private;
10309         struct drm_i915_gem_object *obj;
10310         struct drm_framebuffer *fb;
10311
10312         if (!dev_priv->fbdev)
10313                 return NULL;
10314
10315         if (!dev_priv->fbdev->fb)
10316                 return NULL;
10317
10318         obj = dev_priv->fbdev->fb->obj;
10319         BUG_ON(!obj);
10320
10321         fb = &dev_priv->fbdev->fb->base;
10322         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10323                                                                fb->bits_per_pixel))
10324                 return NULL;
10325
10326         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10327                 return NULL;
10328
10329         drm_framebuffer_reference(fb);
10330         return fb;
10331 #else
10332         return NULL;
10333 #endif
10334 }
10335
10336 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10337                                            struct drm_crtc *crtc,
10338                                            struct drm_display_mode *mode,
10339                                            struct drm_framebuffer *fb,
10340                                            int x, int y)
10341 {
10342         struct drm_plane_state *plane_state;
10343         int hdisplay, vdisplay;
10344         int ret;
10345
10346         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10347         if (IS_ERR(plane_state))
10348                 return PTR_ERR(plane_state);
10349
10350         if (mode)
10351                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10352         else
10353                 hdisplay = vdisplay = 0;
10354
10355         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10356         if (ret)
10357                 return ret;
10358         drm_atomic_set_fb_for_plane(plane_state, fb);
10359         plane_state->crtc_x = 0;
10360         plane_state->crtc_y = 0;
10361         plane_state->crtc_w = hdisplay;
10362         plane_state->crtc_h = vdisplay;
10363         plane_state->src_x = x << 16;
10364         plane_state->src_y = y << 16;
10365         plane_state->src_w = hdisplay << 16;
10366         plane_state->src_h = vdisplay << 16;
10367
10368         return 0;
10369 }
10370
10371 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10372                                 struct drm_display_mode *mode,
10373                                 struct intel_load_detect_pipe *old,
10374                                 struct drm_modeset_acquire_ctx *ctx)
10375 {
10376         struct intel_crtc *intel_crtc;
10377         struct intel_encoder *intel_encoder =
10378                 intel_attached_encoder(connector);
10379         struct drm_crtc *possible_crtc;
10380         struct drm_encoder *encoder = &intel_encoder->base;
10381         struct drm_crtc *crtc = NULL;
10382         struct drm_device *dev = encoder->dev;
10383         struct drm_framebuffer *fb;
10384         struct drm_mode_config *config = &dev->mode_config;
10385         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10386         struct drm_connector_state *connector_state;
10387         struct intel_crtc_state *crtc_state;
10388         int ret, i = -1;
10389
10390         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10391                       connector->base.id, connector->name,
10392                       encoder->base.id, encoder->name);
10393
10394         old->restore_state = NULL;
10395
10396 retry:
10397         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10398         if (ret)
10399                 goto fail;
10400
10401         /*
10402          * Algorithm gets a little messy:
10403          *
10404          *   - if the connector already has an assigned crtc, use it (but make
10405          *     sure it's on first)
10406          *
10407          *   - try to find the first unused crtc that can drive this connector,
10408          *     and use that if we find one
10409          */
10410
10411         /* See if we already have a CRTC for this connector */
10412         if (connector->state->crtc) {
10413                 crtc = connector->state->crtc;
10414
10415                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10416                 if (ret)
10417                         goto fail;
10418
10419                 /* Make sure the crtc and connector are running */
10420                 goto found;
10421         }
10422
10423         /* Find an unused one (if possible) */
10424         for_each_crtc(dev, possible_crtc) {
10425                 i++;
10426                 if (!(encoder->possible_crtcs & (1 << i)))
10427                         continue;
10428
10429                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10430                 if (ret)
10431                         goto fail;
10432
10433                 if (possible_crtc->state->enable) {
10434                         drm_modeset_unlock(&possible_crtc->mutex);
10435                         continue;
10436                 }
10437
10438                 crtc = possible_crtc;
10439                 break;
10440         }
10441
10442         /*
10443          * If we didn't find an unused CRTC, don't use any.
10444          */
10445         if (!crtc) {
10446                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10447                 goto fail;
10448         }
10449
10450 found:
10451         intel_crtc = to_intel_crtc(crtc);
10452
10453         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10454         if (ret)
10455                 goto fail;
10456
10457         state = drm_atomic_state_alloc(dev);
10458         restore_state = drm_atomic_state_alloc(dev);
10459         if (!state || !restore_state) {
10460                 ret = -ENOMEM;
10461                 goto fail;
10462         }
10463
10464         state->acquire_ctx = ctx;
10465         restore_state->acquire_ctx = ctx;
10466
10467         connector_state = drm_atomic_get_connector_state(state, connector);
10468         if (IS_ERR(connector_state)) {
10469                 ret = PTR_ERR(connector_state);
10470                 goto fail;
10471         }
10472
10473         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10474         if (ret)
10475                 goto fail;
10476
10477         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10478         if (IS_ERR(crtc_state)) {
10479                 ret = PTR_ERR(crtc_state);
10480                 goto fail;
10481         }
10482
10483         crtc_state->base.active = crtc_state->base.enable = true;
10484
10485         if (!mode)
10486                 mode = &load_detect_mode;
10487
10488         /* We need a framebuffer large enough to accommodate all accesses
10489          * that the plane may generate whilst we perform load detection.
10490          * We can not rely on the fbcon either being present (we get called
10491          * during its initialisation to detect all boot displays, or it may
10492          * not even exist) or that it is large enough to satisfy the
10493          * requested mode.
10494          */
10495         fb = mode_fits_in_fbdev(dev, mode);
10496         if (fb == NULL) {
10497                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10498                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10499         } else
10500                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10501         if (IS_ERR(fb)) {
10502                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10503                 goto fail;
10504         }
10505
10506         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10507         if (ret)
10508                 goto fail;
10509
10510         drm_framebuffer_unreference(fb);
10511
10512         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10513         if (ret)
10514                 goto fail;
10515
10516         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10517         if (!ret)
10518                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10519         if (!ret)
10520                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10521         if (ret) {
10522                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10523                 goto fail;
10524         }
10525
10526         ret = drm_atomic_commit(state);
10527         if (ret) {
10528                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10529                 goto fail;
10530         }
10531
10532         old->restore_state = restore_state;
10533
10534         /* let the connector get through one full cycle before testing */
10535         intel_wait_for_vblank(dev, intel_crtc->pipe);
10536         return true;
10537
10538 fail:
10539         drm_atomic_state_free(state);
10540         drm_atomic_state_free(restore_state);
10541         restore_state = state = NULL;
10542
10543         if (ret == -EDEADLK) {
10544                 drm_modeset_backoff(ctx);
10545                 goto retry;
10546         }
10547
10548         return false;
10549 }
10550
10551 void intel_release_load_detect_pipe(struct drm_connector *connector,
10552                                     struct intel_load_detect_pipe *old,
10553                                     struct drm_modeset_acquire_ctx *ctx)
10554 {
10555         struct intel_encoder *intel_encoder =
10556                 intel_attached_encoder(connector);
10557         struct drm_encoder *encoder = &intel_encoder->base;
10558         struct drm_atomic_state *state = old->restore_state;
10559         int ret;
10560
10561         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10562                       connector->base.id, connector->name,
10563                       encoder->base.id, encoder->name);
10564
10565         if (!state)
10566                 return;
10567
10568         ret = drm_atomic_commit(state);
10569         if (ret) {
10570                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10571                 drm_atomic_state_free(state);
10572         }
10573 }
10574
10575 static int i9xx_pll_refclk(struct drm_device *dev,
10576                            const struct intel_crtc_state *pipe_config)
10577 {
10578         struct drm_i915_private *dev_priv = dev->dev_private;
10579         u32 dpll = pipe_config->dpll_hw_state.dpll;
10580
10581         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10582                 return dev_priv->vbt.lvds_ssc_freq;
10583         else if (HAS_PCH_SPLIT(dev))
10584                 return 120000;
10585         else if (!IS_GEN2(dev))
10586                 return 96000;
10587         else
10588                 return 48000;
10589 }
10590
10591 /* Returns the clock of the currently programmed mode of the given pipe. */
10592 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10593                                 struct intel_crtc_state *pipe_config)
10594 {
10595         struct drm_device *dev = crtc->base.dev;
10596         struct drm_i915_private *dev_priv = dev->dev_private;
10597         int pipe = pipe_config->cpu_transcoder;
10598         u32 dpll = pipe_config->dpll_hw_state.dpll;
10599         u32 fp;
10600         intel_clock_t clock;
10601         int port_clock;
10602         int refclk = i9xx_pll_refclk(dev, pipe_config);
10603
10604         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10605                 fp = pipe_config->dpll_hw_state.fp0;
10606         else
10607                 fp = pipe_config->dpll_hw_state.fp1;
10608
10609         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10610         if (IS_PINEVIEW(dev)) {
10611                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10612                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10613         } else {
10614                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10615                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10616         }
10617
10618         if (!IS_GEN2(dev)) {
10619                 if (IS_PINEVIEW(dev))
10620                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10621                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10622                 else
10623                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10624                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10625
10626                 switch (dpll & DPLL_MODE_MASK) {
10627                 case DPLLB_MODE_DAC_SERIAL:
10628                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10629                                 5 : 10;
10630                         break;
10631                 case DPLLB_MODE_LVDS:
10632                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10633                                 7 : 14;
10634                         break;
10635                 default:
10636                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10637                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10638                         return;
10639                 }
10640
10641                 if (IS_PINEVIEW(dev))
10642                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10643                 else
10644                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10645         } else {
10646                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10647                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10648
10649                 if (is_lvds) {
10650                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10651                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10652
10653                         if (lvds & LVDS_CLKB_POWER_UP)
10654                                 clock.p2 = 7;
10655                         else
10656                                 clock.p2 = 14;
10657                 } else {
10658                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10659                                 clock.p1 = 2;
10660                         else {
10661                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10662                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10663                         }
10664                         if (dpll & PLL_P2_DIVIDE_BY_4)
10665                                 clock.p2 = 4;
10666                         else
10667                                 clock.p2 = 2;
10668                 }
10669
10670                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10671         }
10672
10673         /*
10674          * This value includes pixel_multiplier. We will use
10675          * port_clock to compute adjusted_mode.crtc_clock in the
10676          * encoder's get_config() function.
10677          */
10678         pipe_config->port_clock = port_clock;
10679 }
10680
10681 int intel_dotclock_calculate(int link_freq,
10682                              const struct intel_link_m_n *m_n)
10683 {
10684         /*
10685          * The calculation for the data clock is:
10686          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10687          * But we want to avoid losing precison if possible, so:
10688          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10689          *
10690          * and the link clock is simpler:
10691          * link_clock = (m * link_clock) / n
10692          */
10693
10694         if (!m_n->link_n)
10695                 return 0;
10696
10697         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10698 }
10699
10700 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10701                                    struct intel_crtc_state *pipe_config)
10702 {
10703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10704
10705         /* read out port_clock from the DPLL */
10706         i9xx_crtc_clock_get(crtc, pipe_config);
10707
10708         /*
10709          * In case there is an active pipe without active ports,
10710          * we may need some idea for the dotclock anyway.
10711          * Calculate one based on the FDI configuration.
10712          */
10713         pipe_config->base.adjusted_mode.crtc_clock =
10714                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10715                                          &pipe_config->fdi_m_n);
10716 }
10717
10718 /** Returns the currently programmed mode of the given pipe. */
10719 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10720                                              struct drm_crtc *crtc)
10721 {
10722         struct drm_i915_private *dev_priv = dev->dev_private;
10723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10724         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10725         struct drm_display_mode *mode;
10726         struct intel_crtc_state *pipe_config;
10727         int htot = I915_READ(HTOTAL(cpu_transcoder));
10728         int hsync = I915_READ(HSYNC(cpu_transcoder));
10729         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10730         int vsync = I915_READ(VSYNC(cpu_transcoder));
10731         enum pipe pipe = intel_crtc->pipe;
10732
10733         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10734         if (!mode)
10735                 return NULL;
10736
10737         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10738         if (!pipe_config) {
10739                 kfree(mode);
10740                 return NULL;
10741         }
10742
10743         /*
10744          * Construct a pipe_config sufficient for getting the clock info
10745          * back out of crtc_clock_get.
10746          *
10747          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10748          * to use a real value here instead.
10749          */
10750         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10751         pipe_config->pixel_multiplier = 1;
10752         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10753         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10754         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10755         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10756
10757         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10758         mode->hdisplay = (htot & 0xffff) + 1;
10759         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10760         mode->hsync_start = (hsync & 0xffff) + 1;
10761         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10762         mode->vdisplay = (vtot & 0xffff) + 1;
10763         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10764         mode->vsync_start = (vsync & 0xffff) + 1;
10765         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10766
10767         drm_mode_set_name(mode);
10768
10769         kfree(pipe_config);
10770
10771         return mode;
10772 }
10773
10774 void intel_mark_busy(struct drm_device *dev)
10775 {
10776         struct drm_i915_private *dev_priv = dev->dev_private;
10777
10778         if (dev_priv->mm.busy)
10779                 return;
10780
10781         intel_runtime_pm_get(dev_priv);
10782         i915_update_gfx_val(dev_priv);
10783         if (INTEL_INFO(dev)->gen >= 6)
10784                 gen6_rps_busy(dev_priv);
10785         dev_priv->mm.busy = true;
10786 }
10787
10788 void intel_mark_idle(struct drm_device *dev)
10789 {
10790         struct drm_i915_private *dev_priv = dev->dev_private;
10791
10792         if (!dev_priv->mm.busy)
10793                 return;
10794
10795         dev_priv->mm.busy = false;
10796
10797         if (INTEL_INFO(dev)->gen >= 6)
10798                 gen6_rps_idle(dev->dev_private);
10799
10800         intel_runtime_pm_put(dev_priv);
10801 }
10802
10803 static void intel_crtc_destroy(struct drm_crtc *crtc)
10804 {
10805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10806         struct drm_device *dev = crtc->dev;
10807         struct intel_unpin_work *work;
10808
10809         spin_lock_irq(&dev->event_lock);
10810         work = intel_crtc->unpin_work;
10811         intel_crtc->unpin_work = NULL;
10812         spin_unlock_irq(&dev->event_lock);
10813
10814         if (work) {
10815                 cancel_work_sync(&work->work);
10816                 kfree(work);
10817         }
10818
10819         drm_crtc_cleanup(crtc);
10820
10821         kfree(intel_crtc);
10822 }
10823
10824 static void intel_unpin_work_fn(struct work_struct *__work)
10825 {
10826         struct intel_unpin_work *work =
10827                 container_of(__work, struct intel_unpin_work, work);
10828         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10829         struct drm_device *dev = crtc->base.dev;
10830         struct drm_plane *primary = crtc->base.primary;
10831
10832         mutex_lock(&dev->struct_mutex);
10833         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10834         drm_gem_object_unreference(&work->pending_flip_obj->base);
10835
10836         if (work->flip_queued_req)
10837                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10838         mutex_unlock(&dev->struct_mutex);
10839
10840         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10841         intel_fbc_post_update(crtc);
10842         drm_framebuffer_unreference(work->old_fb);
10843
10844         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10845         atomic_dec(&crtc->unpin_work_count);
10846
10847         kfree(work);
10848 }
10849
10850 static void do_intel_finish_page_flip(struct drm_device *dev,
10851                                       struct drm_crtc *crtc)
10852 {
10853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10854         struct intel_unpin_work *work;
10855         unsigned long flags;
10856
10857         /* Ignore early vblank irqs */
10858         if (intel_crtc == NULL)
10859                 return;
10860
10861         /*
10862          * This is called both by irq handlers and the reset code (to complete
10863          * lost pageflips) so needs the full irqsave spinlocks.
10864          */
10865         spin_lock_irqsave(&dev->event_lock, flags);
10866         work = intel_crtc->unpin_work;
10867
10868         /* Ensure we don't miss a work->pending update ... */
10869         smp_rmb();
10870
10871         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10872                 spin_unlock_irqrestore(&dev->event_lock, flags);
10873                 return;
10874         }
10875
10876         page_flip_completed(intel_crtc);
10877
10878         spin_unlock_irqrestore(&dev->event_lock, flags);
10879 }
10880
10881 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10882 {
10883         struct drm_i915_private *dev_priv = dev->dev_private;
10884         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10885
10886         do_intel_finish_page_flip(dev, crtc);
10887 }
10888
10889 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10890 {
10891         struct drm_i915_private *dev_priv = dev->dev_private;
10892         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10893
10894         do_intel_finish_page_flip(dev, crtc);
10895 }
10896
10897 /* Is 'a' after or equal to 'b'? */
10898 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10899 {
10900         return !((a - b) & 0x80000000);
10901 }
10902
10903 static bool page_flip_finished(struct intel_crtc *crtc)
10904 {
10905         struct drm_device *dev = crtc->base.dev;
10906         struct drm_i915_private *dev_priv = dev->dev_private;
10907
10908         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10909             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10910                 return true;
10911
10912         /*
10913          * The relevant registers doen't exist on pre-ctg.
10914          * As the flip done interrupt doesn't trigger for mmio
10915          * flips on gmch platforms, a flip count check isn't
10916          * really needed there. But since ctg has the registers,
10917          * include it in the check anyway.
10918          */
10919         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10920                 return true;
10921
10922         /*
10923          * BDW signals flip done immediately if the plane
10924          * is disabled, even if the plane enable is already
10925          * armed to occur at the next vblank :(
10926          */
10927
10928         /*
10929          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10930          * used the same base address. In that case the mmio flip might
10931          * have completed, but the CS hasn't even executed the flip yet.
10932          *
10933          * A flip count check isn't enough as the CS might have updated
10934          * the base address just after start of vblank, but before we
10935          * managed to process the interrupt. This means we'd complete the
10936          * CS flip too soon.
10937          *
10938          * Combining both checks should get us a good enough result. It may
10939          * still happen that the CS flip has been executed, but has not
10940          * yet actually completed. But in case the base address is the same
10941          * anyway, we don't really care.
10942          */
10943         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10944                 crtc->unpin_work->gtt_offset &&
10945                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10946                                     crtc->unpin_work->flip_count);
10947 }
10948
10949 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10950 {
10951         struct drm_i915_private *dev_priv = dev->dev_private;
10952         struct intel_crtc *intel_crtc =
10953                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10954         unsigned long flags;
10955
10956
10957         /*
10958          * This is called both by irq handlers and the reset code (to complete
10959          * lost pageflips) so needs the full irqsave spinlocks.
10960          *
10961          * NB: An MMIO update of the plane base pointer will also
10962          * generate a page-flip completion irq, i.e. every modeset
10963          * is also accompanied by a spurious intel_prepare_page_flip().
10964          */
10965         spin_lock_irqsave(&dev->event_lock, flags);
10966         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10967                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10968         spin_unlock_irqrestore(&dev->event_lock, flags);
10969 }
10970
10971 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10972 {
10973         /* Ensure that the work item is consistent when activating it ... */
10974         smp_wmb();
10975         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10976         /* and that it is marked active as soon as the irq could fire. */
10977         smp_wmb();
10978 }
10979
10980 static int intel_gen2_queue_flip(struct drm_device *dev,
10981                                  struct drm_crtc *crtc,
10982                                  struct drm_framebuffer *fb,
10983                                  struct drm_i915_gem_object *obj,
10984                                  struct drm_i915_gem_request *req,
10985                                  uint32_t flags)
10986 {
10987         struct intel_engine_cs *engine = req->engine;
10988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10989         u32 flip_mask;
10990         int ret;
10991
10992         ret = intel_ring_begin(req, 6);
10993         if (ret)
10994                 return ret;
10995
10996         /* Can't queue multiple flips, so wait for the previous
10997          * one to finish before executing the next.
10998          */
10999         if (intel_crtc->plane)
11000                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11001         else
11002                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11003         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11004         intel_ring_emit(engine, MI_NOOP);
11005         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11006                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11007         intel_ring_emit(engine, fb->pitches[0]);
11008         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11009         intel_ring_emit(engine, 0); /* aux display base address, unused */
11010
11011         intel_mark_page_flip_active(intel_crtc->unpin_work);
11012         return 0;
11013 }
11014
11015 static int intel_gen3_queue_flip(struct drm_device *dev,
11016                                  struct drm_crtc *crtc,
11017                                  struct drm_framebuffer *fb,
11018                                  struct drm_i915_gem_object *obj,
11019                                  struct drm_i915_gem_request *req,
11020                                  uint32_t flags)
11021 {
11022         struct intel_engine_cs *engine = req->engine;
11023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11024         u32 flip_mask;
11025         int ret;
11026
11027         ret = intel_ring_begin(req, 6);
11028         if (ret)
11029                 return ret;
11030
11031         if (intel_crtc->plane)
11032                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11033         else
11034                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11035         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11036         intel_ring_emit(engine, MI_NOOP);
11037         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11038                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11039         intel_ring_emit(engine, fb->pitches[0]);
11040         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11041         intel_ring_emit(engine, MI_NOOP);
11042
11043         intel_mark_page_flip_active(intel_crtc->unpin_work);
11044         return 0;
11045 }
11046
11047 static int intel_gen4_queue_flip(struct drm_device *dev,
11048                                  struct drm_crtc *crtc,
11049                                  struct drm_framebuffer *fb,
11050                                  struct drm_i915_gem_object *obj,
11051                                  struct drm_i915_gem_request *req,
11052                                  uint32_t flags)
11053 {
11054         struct intel_engine_cs *engine = req->engine;
11055         struct drm_i915_private *dev_priv = dev->dev_private;
11056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11057         uint32_t pf, pipesrc;
11058         int ret;
11059
11060         ret = intel_ring_begin(req, 4);
11061         if (ret)
11062                 return ret;
11063
11064         /* i965+ uses the linear or tiled offsets from the
11065          * Display Registers (which do not change across a page-flip)
11066          * so we need only reprogram the base address.
11067          */
11068         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11069                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11070         intel_ring_emit(engine, fb->pitches[0]);
11071         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11072                         obj->tiling_mode);
11073
11074         /* XXX Enabling the panel-fitter across page-flip is so far
11075          * untested on non-native modes, so ignore it for now.
11076          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11077          */
11078         pf = 0;
11079         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11080         intel_ring_emit(engine, pf | pipesrc);
11081
11082         intel_mark_page_flip_active(intel_crtc->unpin_work);
11083         return 0;
11084 }
11085
11086 static int intel_gen6_queue_flip(struct drm_device *dev,
11087                                  struct drm_crtc *crtc,
11088                                  struct drm_framebuffer *fb,
11089                                  struct drm_i915_gem_object *obj,
11090                                  struct drm_i915_gem_request *req,
11091                                  uint32_t flags)
11092 {
11093         struct intel_engine_cs *engine = req->engine;
11094         struct drm_i915_private *dev_priv = dev->dev_private;
11095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11096         uint32_t pf, pipesrc;
11097         int ret;
11098
11099         ret = intel_ring_begin(req, 4);
11100         if (ret)
11101                 return ret;
11102
11103         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11104                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11105         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11106         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11107
11108         /* Contrary to the suggestions in the documentation,
11109          * "Enable Panel Fitter" does not seem to be required when page
11110          * flipping with a non-native mode, and worse causes a normal
11111          * modeset to fail.
11112          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11113          */
11114         pf = 0;
11115         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11116         intel_ring_emit(engine, pf | pipesrc);
11117
11118         intel_mark_page_flip_active(intel_crtc->unpin_work);
11119         return 0;
11120 }
11121
11122 static int intel_gen7_queue_flip(struct drm_device *dev,
11123                                  struct drm_crtc *crtc,
11124                                  struct drm_framebuffer *fb,
11125                                  struct drm_i915_gem_object *obj,
11126                                  struct drm_i915_gem_request *req,
11127                                  uint32_t flags)
11128 {
11129         struct intel_engine_cs *engine = req->engine;
11130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11131         uint32_t plane_bit = 0;
11132         int len, ret;
11133
11134         switch (intel_crtc->plane) {
11135         case PLANE_A:
11136                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11137                 break;
11138         case PLANE_B:
11139                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11140                 break;
11141         case PLANE_C:
11142                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11143                 break;
11144         default:
11145                 WARN_ONCE(1, "unknown plane in flip command\n");
11146                 return -ENODEV;
11147         }
11148
11149         len = 4;
11150         if (engine->id == RCS) {
11151                 len += 6;
11152                 /*
11153                  * On Gen 8, SRM is now taking an extra dword to accommodate
11154                  * 48bits addresses, and we need a NOOP for the batch size to
11155                  * stay even.
11156                  */
11157                 if (IS_GEN8(dev))
11158                         len += 2;
11159         }
11160
11161         /*
11162          * BSpec MI_DISPLAY_FLIP for IVB:
11163          * "The full packet must be contained within the same cache line."
11164          *
11165          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11166          * cacheline, if we ever start emitting more commands before
11167          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11168          * then do the cacheline alignment, and finally emit the
11169          * MI_DISPLAY_FLIP.
11170          */
11171         ret = intel_ring_cacheline_align(req);
11172         if (ret)
11173                 return ret;
11174
11175         ret = intel_ring_begin(req, len);
11176         if (ret)
11177                 return ret;
11178
11179         /* Unmask the flip-done completion message. Note that the bspec says that
11180          * we should do this for both the BCS and RCS, and that we must not unmask
11181          * more than one flip event at any time (or ensure that one flip message
11182          * can be sent by waiting for flip-done prior to queueing new flips).
11183          * Experimentation says that BCS works despite DERRMR masking all
11184          * flip-done completion events and that unmasking all planes at once
11185          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11186          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11187          */
11188         if (engine->id == RCS) {
11189                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11190                 intel_ring_emit_reg(engine, DERRMR);
11191                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11192                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11193                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11194                 if (IS_GEN8(dev))
11195                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11196                                               MI_SRM_LRM_GLOBAL_GTT);
11197                 else
11198                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11199                                               MI_SRM_LRM_GLOBAL_GTT);
11200                 intel_ring_emit_reg(engine, DERRMR);
11201                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11202                 if (IS_GEN8(dev)) {
11203                         intel_ring_emit(engine, 0);
11204                         intel_ring_emit(engine, MI_NOOP);
11205                 }
11206         }
11207
11208         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11209         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11210         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11211         intel_ring_emit(engine, (MI_NOOP));
11212
11213         intel_mark_page_flip_active(intel_crtc->unpin_work);
11214         return 0;
11215 }
11216
11217 static bool use_mmio_flip(struct intel_engine_cs *engine,
11218                           struct drm_i915_gem_object *obj)
11219 {
11220         /*
11221          * This is not being used for older platforms, because
11222          * non-availability of flip done interrupt forces us to use
11223          * CS flips. Older platforms derive flip done using some clever
11224          * tricks involving the flip_pending status bits and vblank irqs.
11225          * So using MMIO flips there would disrupt this mechanism.
11226          */
11227
11228         if (engine == NULL)
11229                 return true;
11230
11231         if (INTEL_INFO(engine->dev)->gen < 5)
11232                 return false;
11233
11234         if (i915.use_mmio_flip < 0)
11235                 return false;
11236         else if (i915.use_mmio_flip > 0)
11237                 return true;
11238         else if (i915.enable_execlists)
11239                 return true;
11240         else if (obj->base.dma_buf &&
11241                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11242                                                        false))
11243                 return true;
11244         else
11245                 return engine != i915_gem_request_get_engine(obj->last_write_req);
11246 }
11247
11248 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11249                              unsigned int rotation,
11250                              struct intel_unpin_work *work)
11251 {
11252         struct drm_device *dev = intel_crtc->base.dev;
11253         struct drm_i915_private *dev_priv = dev->dev_private;
11254         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11255         const enum pipe pipe = intel_crtc->pipe;
11256         u32 ctl, stride, tile_height;
11257
11258         ctl = I915_READ(PLANE_CTL(pipe, 0));
11259         ctl &= ~PLANE_CTL_TILED_MASK;
11260         switch (fb->modifier[0]) {
11261         case DRM_FORMAT_MOD_NONE:
11262                 break;
11263         case I915_FORMAT_MOD_X_TILED:
11264                 ctl |= PLANE_CTL_TILED_X;
11265                 break;
11266         case I915_FORMAT_MOD_Y_TILED:
11267                 ctl |= PLANE_CTL_TILED_Y;
11268                 break;
11269         case I915_FORMAT_MOD_Yf_TILED:
11270                 ctl |= PLANE_CTL_TILED_YF;
11271                 break;
11272         default:
11273                 MISSING_CASE(fb->modifier[0]);
11274         }
11275
11276         /*
11277          * The stride is either expressed as a multiple of 64 bytes chunks for
11278          * linear buffers or in number of tiles for tiled buffers.
11279          */
11280         if (intel_rotation_90_or_270(rotation)) {
11281                 /* stride = Surface height in tiles */
11282                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11283                 stride = DIV_ROUND_UP(fb->height, tile_height);
11284         } else {
11285                 stride = fb->pitches[0] /
11286                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11287                                                   fb->pixel_format);
11288         }
11289
11290         /*
11291          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11292          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11293          */
11294         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11295         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11296
11297         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11298         POSTING_READ(PLANE_SURF(pipe, 0));
11299 }
11300
11301 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11302                              struct intel_unpin_work *work)
11303 {
11304         struct drm_device *dev = intel_crtc->base.dev;
11305         struct drm_i915_private *dev_priv = dev->dev_private;
11306         struct intel_framebuffer *intel_fb =
11307                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11308         struct drm_i915_gem_object *obj = intel_fb->obj;
11309         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11310         u32 dspcntr;
11311
11312         dspcntr = I915_READ(reg);
11313
11314         if (obj->tiling_mode != I915_TILING_NONE)
11315                 dspcntr |= DISPPLANE_TILED;
11316         else
11317                 dspcntr &= ~DISPPLANE_TILED;
11318
11319         I915_WRITE(reg, dspcntr);
11320
11321         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11322         POSTING_READ(DSPSURF(intel_crtc->plane));
11323 }
11324
11325 /*
11326  * XXX: This is the temporary way to update the plane registers until we get
11327  * around to using the usual plane update functions for MMIO flips
11328  */
11329 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11330 {
11331         struct intel_crtc *crtc = mmio_flip->crtc;
11332         struct intel_unpin_work *work;
11333
11334         spin_lock_irq(&crtc->base.dev->event_lock);
11335         work = crtc->unpin_work;
11336         spin_unlock_irq(&crtc->base.dev->event_lock);
11337         if (work == NULL)
11338                 return;
11339
11340         intel_mark_page_flip_active(work);
11341
11342         intel_pipe_update_start(crtc);
11343
11344         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11345                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11346         else
11347                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11348                 ilk_do_mmio_flip(crtc, work);
11349
11350         intel_pipe_update_end(crtc);
11351 }
11352
11353 static void intel_mmio_flip_work_func(struct work_struct *work)
11354 {
11355         struct intel_mmio_flip *mmio_flip =
11356                 container_of(work, struct intel_mmio_flip, work);
11357         struct intel_framebuffer *intel_fb =
11358                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11359         struct drm_i915_gem_object *obj = intel_fb->obj;
11360
11361         if (mmio_flip->req) {
11362                 WARN_ON(__i915_wait_request(mmio_flip->req,
11363                                             mmio_flip->crtc->reset_counter,
11364                                             false, NULL,
11365                                             &mmio_flip->i915->rps.mmioflips));
11366                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11367         }
11368
11369         /* For framebuffer backed by dmabuf, wait for fence */
11370         if (obj->base.dma_buf)
11371                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11372                                                             false, false,
11373                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11374
11375         intel_do_mmio_flip(mmio_flip);
11376         kfree(mmio_flip);
11377 }
11378
11379 static int intel_queue_mmio_flip(struct drm_device *dev,
11380                                  struct drm_crtc *crtc,
11381                                  struct drm_i915_gem_object *obj)
11382 {
11383         struct intel_mmio_flip *mmio_flip;
11384
11385         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11386         if (mmio_flip == NULL)
11387                 return -ENOMEM;
11388
11389         mmio_flip->i915 = to_i915(dev);
11390         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11391         mmio_flip->crtc = to_intel_crtc(crtc);
11392         mmio_flip->rotation = crtc->primary->state->rotation;
11393
11394         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11395         schedule_work(&mmio_flip->work);
11396
11397         return 0;
11398 }
11399
11400 static int intel_default_queue_flip(struct drm_device *dev,
11401                                     struct drm_crtc *crtc,
11402                                     struct drm_framebuffer *fb,
11403                                     struct drm_i915_gem_object *obj,
11404                                     struct drm_i915_gem_request *req,
11405                                     uint32_t flags)
11406 {
11407         return -ENODEV;
11408 }
11409
11410 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11411                                          struct drm_crtc *crtc)
11412 {
11413         struct drm_i915_private *dev_priv = dev->dev_private;
11414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11415         struct intel_unpin_work *work = intel_crtc->unpin_work;
11416         u32 addr;
11417
11418         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11419                 return true;
11420
11421         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11422                 return false;
11423
11424         if (!work->enable_stall_check)
11425                 return false;
11426
11427         if (work->flip_ready_vblank == 0) {
11428                 if (work->flip_queued_req &&
11429                     !i915_gem_request_completed(work->flip_queued_req, true))
11430                         return false;
11431
11432                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11433         }
11434
11435         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11436                 return false;
11437
11438         /* Potential stall - if we see that the flip has happened,
11439          * assume a missed interrupt. */
11440         if (INTEL_INFO(dev)->gen >= 4)
11441                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11442         else
11443                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11444
11445         /* There is a potential issue here with a false positive after a flip
11446          * to the same address. We could address this by checking for a
11447          * non-incrementing frame counter.
11448          */
11449         return addr == work->gtt_offset;
11450 }
11451
11452 void intel_check_page_flip(struct drm_device *dev, int pipe)
11453 {
11454         struct drm_i915_private *dev_priv = dev->dev_private;
11455         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11457         struct intel_unpin_work *work;
11458
11459         WARN_ON(!in_interrupt());
11460
11461         if (crtc == NULL)
11462                 return;
11463
11464         spin_lock(&dev->event_lock);
11465         work = intel_crtc->unpin_work;
11466         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11467                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11468                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11469                 page_flip_completed(intel_crtc);
11470                 work = NULL;
11471         }
11472         if (work != NULL &&
11473             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11474                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11475         spin_unlock(&dev->event_lock);
11476 }
11477
11478 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11479                                 struct drm_framebuffer *fb,
11480                                 struct drm_pending_vblank_event *event,
11481                                 uint32_t page_flip_flags)
11482 {
11483         struct drm_device *dev = crtc->dev;
11484         struct drm_i915_private *dev_priv = dev->dev_private;
11485         struct drm_framebuffer *old_fb = crtc->primary->fb;
11486         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11488         struct drm_plane *primary = crtc->primary;
11489         enum pipe pipe = intel_crtc->pipe;
11490         struct intel_unpin_work *work;
11491         struct intel_engine_cs *engine;
11492         bool mmio_flip;
11493         struct drm_i915_gem_request *request = NULL;
11494         int ret;
11495
11496         /*
11497          * drm_mode_page_flip_ioctl() should already catch this, but double
11498          * check to be safe.  In the future we may enable pageflipping from
11499          * a disabled primary plane.
11500          */
11501         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11502                 return -EBUSY;
11503
11504         /* Can't change pixel format via MI display flips. */
11505         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11506                 return -EINVAL;
11507
11508         /*
11509          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11510          * Note that pitch changes could also affect these register.
11511          */
11512         if (INTEL_INFO(dev)->gen > 3 &&
11513             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11514              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11515                 return -EINVAL;
11516
11517         if (i915_terminally_wedged(&dev_priv->gpu_error))
11518                 goto out_hang;
11519
11520         work = kzalloc(sizeof(*work), GFP_KERNEL);
11521         if (work == NULL)
11522                 return -ENOMEM;
11523
11524         work->event = event;
11525         work->crtc = crtc;
11526         work->old_fb = old_fb;
11527         INIT_WORK(&work->work, intel_unpin_work_fn);
11528
11529         ret = drm_crtc_vblank_get(crtc);
11530         if (ret)
11531                 goto free_work;
11532
11533         /* We borrow the event spin lock for protecting unpin_work */
11534         spin_lock_irq(&dev->event_lock);
11535         if (intel_crtc->unpin_work) {
11536                 /* Before declaring the flip queue wedged, check if
11537                  * the hardware completed the operation behind our backs.
11538                  */
11539                 if (__intel_pageflip_stall_check(dev, crtc)) {
11540                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11541                         page_flip_completed(intel_crtc);
11542                 } else {
11543                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11544                         spin_unlock_irq(&dev->event_lock);
11545
11546                         drm_crtc_vblank_put(crtc);
11547                         kfree(work);
11548                         return -EBUSY;
11549                 }
11550         }
11551         intel_crtc->unpin_work = work;
11552         spin_unlock_irq(&dev->event_lock);
11553
11554         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11555                 flush_workqueue(dev_priv->wq);
11556
11557         /* Reference the objects for the scheduled work. */
11558         drm_framebuffer_reference(work->old_fb);
11559         drm_gem_object_reference(&obj->base);
11560
11561         crtc->primary->fb = fb;
11562         update_state_fb(crtc->primary);
11563         intel_fbc_pre_update(intel_crtc);
11564
11565         work->pending_flip_obj = obj;
11566
11567         ret = i915_mutex_lock_interruptible(dev);
11568         if (ret)
11569                 goto cleanup;
11570
11571         atomic_inc(&intel_crtc->unpin_work_count);
11572         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11573
11574         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11575                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11576
11577         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11578                 engine = &dev_priv->engine[BCS];
11579                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11580                         /* vlv: DISPLAY_FLIP fails to change tiling */
11581                         engine = NULL;
11582         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11583                 engine = &dev_priv->engine[BCS];
11584         } else if (INTEL_INFO(dev)->gen >= 7) {
11585                 engine = i915_gem_request_get_engine(obj->last_write_req);
11586                 if (engine == NULL || engine->id != RCS)
11587                         engine = &dev_priv->engine[BCS];
11588         } else {
11589                 engine = &dev_priv->engine[RCS];
11590         }
11591
11592         mmio_flip = use_mmio_flip(engine, obj);
11593
11594         /* When using CS flips, we want to emit semaphores between rings.
11595          * However, when using mmio flips we will create a task to do the
11596          * synchronisation, so all we want here is to pin the framebuffer
11597          * into the display plane and skip any waits.
11598          */
11599         if (!mmio_flip) {
11600                 ret = i915_gem_object_sync(obj, engine, &request);
11601                 if (ret)
11602                         goto cleanup_pending;
11603         }
11604
11605         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11606         if (ret)
11607                 goto cleanup_pending;
11608
11609         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11610                                                   obj, 0);
11611         work->gtt_offset += intel_crtc->dspaddr_offset;
11612
11613         if (mmio_flip) {
11614                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11615                 if (ret)
11616                         goto cleanup_unpin;
11617
11618                 i915_gem_request_assign(&work->flip_queued_req,
11619                                         obj->last_write_req);
11620         } else {
11621                 if (!request) {
11622                         request = i915_gem_request_alloc(engine, NULL);
11623                         if (IS_ERR(request)) {
11624                                 ret = PTR_ERR(request);
11625                                 goto cleanup_unpin;
11626                         }
11627                 }
11628
11629                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11630                                                    page_flip_flags);
11631                 if (ret)
11632                         goto cleanup_unpin;
11633
11634                 i915_gem_request_assign(&work->flip_queued_req, request);
11635         }
11636
11637         if (request)
11638                 i915_add_request_no_flush(request);
11639
11640         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11641         work->enable_stall_check = true;
11642
11643         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11644                           to_intel_plane(primary)->frontbuffer_bit);
11645         mutex_unlock(&dev->struct_mutex);
11646
11647         intel_frontbuffer_flip_prepare(dev,
11648                                        to_intel_plane(primary)->frontbuffer_bit);
11649
11650         trace_i915_flip_request(intel_crtc->plane, obj);
11651
11652         return 0;
11653
11654 cleanup_unpin:
11655         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11656 cleanup_pending:
11657         if (!IS_ERR_OR_NULL(request))
11658                 i915_gem_request_cancel(request);
11659         atomic_dec(&intel_crtc->unpin_work_count);
11660         mutex_unlock(&dev->struct_mutex);
11661 cleanup:
11662         crtc->primary->fb = old_fb;
11663         update_state_fb(crtc->primary);
11664
11665         drm_gem_object_unreference_unlocked(&obj->base);
11666         drm_framebuffer_unreference(work->old_fb);
11667
11668         spin_lock_irq(&dev->event_lock);
11669         intel_crtc->unpin_work = NULL;
11670         spin_unlock_irq(&dev->event_lock);
11671
11672         drm_crtc_vblank_put(crtc);
11673 free_work:
11674         kfree(work);
11675
11676         if (ret == -EIO) {
11677                 struct drm_atomic_state *state;
11678                 struct drm_plane_state *plane_state;
11679
11680 out_hang:
11681                 state = drm_atomic_state_alloc(dev);
11682                 if (!state)
11683                         return -ENOMEM;
11684                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11685
11686 retry:
11687                 plane_state = drm_atomic_get_plane_state(state, primary);
11688                 ret = PTR_ERR_OR_ZERO(plane_state);
11689                 if (!ret) {
11690                         drm_atomic_set_fb_for_plane(plane_state, fb);
11691
11692                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11693                         if (!ret)
11694                                 ret = drm_atomic_commit(state);
11695                 }
11696
11697                 if (ret == -EDEADLK) {
11698                         drm_modeset_backoff(state->acquire_ctx);
11699                         drm_atomic_state_clear(state);
11700                         goto retry;
11701                 }
11702
11703                 if (ret)
11704                         drm_atomic_state_free(state);
11705
11706                 if (ret == 0 && event) {
11707                         spin_lock_irq(&dev->event_lock);
11708                         drm_send_vblank_event(dev, pipe, event);
11709                         spin_unlock_irq(&dev->event_lock);
11710                 }
11711         }
11712         return ret;
11713 }
11714
11715
11716 /**
11717  * intel_wm_need_update - Check whether watermarks need updating
11718  * @plane: drm plane
11719  * @state: new plane state
11720  *
11721  * Check current plane state versus the new one to determine whether
11722  * watermarks need to be recalculated.
11723  *
11724  * Returns true or false.
11725  */
11726 static bool intel_wm_need_update(struct drm_plane *plane,
11727                                  struct drm_plane_state *state)
11728 {
11729         struct intel_plane_state *new = to_intel_plane_state(state);
11730         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11731
11732         /* Update watermarks on tiling or size changes. */
11733         if (new->visible != cur->visible)
11734                 return true;
11735
11736         if (!cur->base.fb || !new->base.fb)
11737                 return false;
11738
11739         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11740             cur->base.rotation != new->base.rotation ||
11741             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11742             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11743             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11744             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11745                 return true;
11746
11747         return false;
11748 }
11749
11750 static bool needs_scaling(struct intel_plane_state *state)
11751 {
11752         int src_w = drm_rect_width(&state->src) >> 16;
11753         int src_h = drm_rect_height(&state->src) >> 16;
11754         int dst_w = drm_rect_width(&state->dst);
11755         int dst_h = drm_rect_height(&state->dst);
11756
11757         return (src_w != dst_w || src_h != dst_h);
11758 }
11759
11760 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11761                                     struct drm_plane_state *plane_state)
11762 {
11763         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11764         struct drm_crtc *crtc = crtc_state->crtc;
11765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11766         struct drm_plane *plane = plane_state->plane;
11767         struct drm_device *dev = crtc->dev;
11768         struct drm_i915_private *dev_priv = to_i915(dev);
11769         struct intel_plane_state *old_plane_state =
11770                 to_intel_plane_state(plane->state);
11771         int idx = intel_crtc->base.base.id, ret;
11772         bool mode_changed = needs_modeset(crtc_state);
11773         bool was_crtc_enabled = crtc->state->active;
11774         bool is_crtc_enabled = crtc_state->active;
11775         bool turn_off, turn_on, visible, was_visible;
11776         struct drm_framebuffer *fb = plane_state->fb;
11777
11778         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11779             plane->type != DRM_PLANE_TYPE_CURSOR) {
11780                 ret = skl_update_scaler_plane(
11781                         to_intel_crtc_state(crtc_state),
11782                         to_intel_plane_state(plane_state));
11783                 if (ret)
11784                         return ret;
11785         }
11786
11787         was_visible = old_plane_state->visible;
11788         visible = to_intel_plane_state(plane_state)->visible;
11789
11790         if (!was_crtc_enabled && WARN_ON(was_visible))
11791                 was_visible = false;
11792
11793         /*
11794          * Visibility is calculated as if the crtc was on, but
11795          * after scaler setup everything depends on it being off
11796          * when the crtc isn't active.
11797          */
11798         if (!is_crtc_enabled)
11799                 to_intel_plane_state(plane_state)->visible = visible = false;
11800
11801         if (!was_visible && !visible)
11802                 return 0;
11803
11804         if (fb != old_plane_state->base.fb)
11805                 pipe_config->fb_changed = true;
11806
11807         turn_off = was_visible && (!visible || mode_changed);
11808         turn_on = visible && (!was_visible || mode_changed);
11809
11810         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11811                          plane->base.id, fb ? fb->base.id : -1);
11812
11813         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11814                          plane->base.id, was_visible, visible,
11815                          turn_off, turn_on, mode_changed);
11816
11817         if (turn_on) {
11818                 pipe_config->update_wm_pre = true;
11819
11820                 /* must disable cxsr around plane enable/disable */
11821                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11822                         pipe_config->disable_cxsr = true;
11823         } else if (turn_off) {
11824                 pipe_config->update_wm_post = true;
11825
11826                 /* must disable cxsr around plane enable/disable */
11827                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11828                         pipe_config->disable_cxsr = true;
11829         } else if (intel_wm_need_update(plane, plane_state)) {
11830                 /* FIXME bollocks */
11831                 pipe_config->update_wm_pre = true;
11832                 pipe_config->update_wm_post = true;
11833         }
11834
11835         /* Pre-gen9 platforms need two-step watermark updates */
11836         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11837             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11838                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11839
11840         if (visible || was_visible)
11841                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11842
11843         /*
11844          * WaCxSRDisabledForSpriteScaling:ivb
11845          *
11846          * cstate->update_wm was already set above, so this flag will
11847          * take effect when we commit and program watermarks.
11848          */
11849         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11850             needs_scaling(to_intel_plane_state(plane_state)) &&
11851             !needs_scaling(old_plane_state))
11852                 pipe_config->disable_lp_wm = true;
11853
11854         return 0;
11855 }
11856
11857 static bool encoders_cloneable(const struct intel_encoder *a,
11858                                const struct intel_encoder *b)
11859 {
11860         /* masks could be asymmetric, so check both ways */
11861         return a == b || (a->cloneable & (1 << b->type) &&
11862                           b->cloneable & (1 << a->type));
11863 }
11864
11865 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11866                                          struct intel_crtc *crtc,
11867                                          struct intel_encoder *encoder)
11868 {
11869         struct intel_encoder *source_encoder;
11870         struct drm_connector *connector;
11871         struct drm_connector_state *connector_state;
11872         int i;
11873
11874         for_each_connector_in_state(state, connector, connector_state, i) {
11875                 if (connector_state->crtc != &crtc->base)
11876                         continue;
11877
11878                 source_encoder =
11879                         to_intel_encoder(connector_state->best_encoder);
11880                 if (!encoders_cloneable(encoder, source_encoder))
11881                         return false;
11882         }
11883
11884         return true;
11885 }
11886
11887 static bool check_encoder_cloning(struct drm_atomic_state *state,
11888                                   struct intel_crtc *crtc)
11889 {
11890         struct intel_encoder *encoder;
11891         struct drm_connector *connector;
11892         struct drm_connector_state *connector_state;
11893         int i;
11894
11895         for_each_connector_in_state(state, connector, connector_state, i) {
11896                 if (connector_state->crtc != &crtc->base)
11897                         continue;
11898
11899                 encoder = to_intel_encoder(connector_state->best_encoder);
11900                 if (!check_single_encoder_cloning(state, crtc, encoder))
11901                         return false;
11902         }
11903
11904         return true;
11905 }
11906
11907 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11908                                    struct drm_crtc_state *crtc_state)
11909 {
11910         struct drm_device *dev = crtc->dev;
11911         struct drm_i915_private *dev_priv = dev->dev_private;
11912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11913         struct intel_crtc_state *pipe_config =
11914                 to_intel_crtc_state(crtc_state);
11915         struct drm_atomic_state *state = crtc_state->state;
11916         int ret;
11917         bool mode_changed = needs_modeset(crtc_state);
11918
11919         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11920                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11921                 return -EINVAL;
11922         }
11923
11924         if (mode_changed && !crtc_state->active)
11925                 pipe_config->update_wm_post = true;
11926
11927         if (mode_changed && crtc_state->enable &&
11928             dev_priv->display.crtc_compute_clock &&
11929             !WARN_ON(pipe_config->shared_dpll)) {
11930                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11931                                                            pipe_config);
11932                 if (ret)
11933                         return ret;
11934         }
11935
11936         ret = 0;
11937         if (dev_priv->display.compute_pipe_wm) {
11938                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11939                 if (ret) {
11940                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11941                         return ret;
11942                 }
11943         }
11944
11945         if (dev_priv->display.compute_intermediate_wm &&
11946             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11947                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11948                         return 0;
11949
11950                 /*
11951                  * Calculate 'intermediate' watermarks that satisfy both the
11952                  * old state and the new state.  We can program these
11953                  * immediately.
11954                  */
11955                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11956                                                                 intel_crtc,
11957                                                                 pipe_config);
11958                 if (ret) {
11959                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11960                         return ret;
11961                 }
11962         }
11963
11964         if (INTEL_INFO(dev)->gen >= 9) {
11965                 if (mode_changed)
11966                         ret = skl_update_scaler_crtc(pipe_config);
11967
11968                 if (!ret)
11969                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11970                                                          pipe_config);
11971         }
11972
11973         return ret;
11974 }
11975
11976 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11977         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11978         .load_lut = intel_crtc_load_lut,
11979         .atomic_begin = intel_begin_crtc_commit,
11980         .atomic_flush = intel_finish_crtc_commit,
11981         .atomic_check = intel_crtc_atomic_check,
11982 };
11983
11984 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11985 {
11986         struct intel_connector *connector;
11987
11988         for_each_intel_connector(dev, connector) {
11989                 if (connector->base.encoder) {
11990                         connector->base.state->best_encoder =
11991                                 connector->base.encoder;
11992                         connector->base.state->crtc =
11993                                 connector->base.encoder->crtc;
11994                 } else {
11995                         connector->base.state->best_encoder = NULL;
11996                         connector->base.state->crtc = NULL;
11997                 }
11998         }
11999 }
12000
12001 static void
12002 connected_sink_compute_bpp(struct intel_connector *connector,
12003                            struct intel_crtc_state *pipe_config)
12004 {
12005         int bpp = pipe_config->pipe_bpp;
12006
12007         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12008                 connector->base.base.id,
12009                 connector->base.name);
12010
12011         /* Don't use an invalid EDID bpc value */
12012         if (connector->base.display_info.bpc &&
12013             connector->base.display_info.bpc * 3 < bpp) {
12014                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12015                               bpp, connector->base.display_info.bpc*3);
12016                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12017         }
12018
12019         /* Clamp bpp to default limit on screens without EDID 1.4 */
12020         if (connector->base.display_info.bpc == 0) {
12021                 int type = connector->base.connector_type;
12022                 int clamp_bpp = 24;
12023
12024                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12025                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12026                     type == DRM_MODE_CONNECTOR_eDP)
12027                         clamp_bpp = 18;
12028
12029                 if (bpp > clamp_bpp) {
12030                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12031                                       bpp, clamp_bpp);
12032                         pipe_config->pipe_bpp = clamp_bpp;
12033                 }
12034         }
12035 }
12036
12037 static int
12038 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12039                           struct intel_crtc_state *pipe_config)
12040 {
12041         struct drm_device *dev = crtc->base.dev;
12042         struct drm_atomic_state *state;
12043         struct drm_connector *connector;
12044         struct drm_connector_state *connector_state;
12045         int bpp, i;
12046
12047         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12048                 bpp = 10*3;
12049         else if (INTEL_INFO(dev)->gen >= 5)
12050                 bpp = 12*3;
12051         else
12052                 bpp = 8*3;
12053
12054
12055         pipe_config->pipe_bpp = bpp;
12056
12057         state = pipe_config->base.state;
12058
12059         /* Clamp display bpp to EDID value */
12060         for_each_connector_in_state(state, connector, connector_state, i) {
12061                 if (connector_state->crtc != &crtc->base)
12062                         continue;
12063
12064                 connected_sink_compute_bpp(to_intel_connector(connector),
12065                                            pipe_config);
12066         }
12067
12068         return bpp;
12069 }
12070
12071 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12072 {
12073         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12074                         "type: 0x%x flags: 0x%x\n",
12075                 mode->crtc_clock,
12076                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12077                 mode->crtc_hsync_end, mode->crtc_htotal,
12078                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12079                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12080 }
12081
12082 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12083                                    struct intel_crtc_state *pipe_config,
12084                                    const char *context)
12085 {
12086         struct drm_device *dev = crtc->base.dev;
12087         struct drm_plane *plane;
12088         struct intel_plane *intel_plane;
12089         struct intel_plane_state *state;
12090         struct drm_framebuffer *fb;
12091
12092         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12093                       context, pipe_config, pipe_name(crtc->pipe));
12094
12095         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12096         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12097                       pipe_config->pipe_bpp, pipe_config->dither);
12098         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12099                       pipe_config->has_pch_encoder,
12100                       pipe_config->fdi_lanes,
12101                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12102                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12103                       pipe_config->fdi_m_n.tu);
12104         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12105                       pipe_config->has_dp_encoder,
12106                       pipe_config->lane_count,
12107                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12108                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12109                       pipe_config->dp_m_n.tu);
12110
12111         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12112                       pipe_config->has_dp_encoder,
12113                       pipe_config->lane_count,
12114                       pipe_config->dp_m2_n2.gmch_m,
12115                       pipe_config->dp_m2_n2.gmch_n,
12116                       pipe_config->dp_m2_n2.link_m,
12117                       pipe_config->dp_m2_n2.link_n,
12118                       pipe_config->dp_m2_n2.tu);
12119
12120         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12121                       pipe_config->has_audio,
12122                       pipe_config->has_infoframe);
12123
12124         DRM_DEBUG_KMS("requested mode:\n");
12125         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12126         DRM_DEBUG_KMS("adjusted mode:\n");
12127         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12128         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12129         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12130         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12131                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12132         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12133                       crtc->num_scalers,
12134                       pipe_config->scaler_state.scaler_users,
12135                       pipe_config->scaler_state.scaler_id);
12136         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12137                       pipe_config->gmch_pfit.control,
12138                       pipe_config->gmch_pfit.pgm_ratios,
12139                       pipe_config->gmch_pfit.lvds_border_bits);
12140         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12141                       pipe_config->pch_pfit.pos,
12142                       pipe_config->pch_pfit.size,
12143                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12144         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12145         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12146
12147         if (IS_BROXTON(dev)) {
12148                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12149                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12150                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12151                               pipe_config->ddi_pll_sel,
12152                               pipe_config->dpll_hw_state.ebb0,
12153                               pipe_config->dpll_hw_state.ebb4,
12154                               pipe_config->dpll_hw_state.pll0,
12155                               pipe_config->dpll_hw_state.pll1,
12156                               pipe_config->dpll_hw_state.pll2,
12157                               pipe_config->dpll_hw_state.pll3,
12158                               pipe_config->dpll_hw_state.pll6,
12159                               pipe_config->dpll_hw_state.pll8,
12160                               pipe_config->dpll_hw_state.pll9,
12161                               pipe_config->dpll_hw_state.pll10,
12162                               pipe_config->dpll_hw_state.pcsdw12);
12163         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12164                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12165                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12166                               pipe_config->ddi_pll_sel,
12167                               pipe_config->dpll_hw_state.ctrl1,
12168                               pipe_config->dpll_hw_state.cfgcr1,
12169                               pipe_config->dpll_hw_state.cfgcr2);
12170         } else if (HAS_DDI(dev)) {
12171                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12172                               pipe_config->ddi_pll_sel,
12173                               pipe_config->dpll_hw_state.wrpll,
12174                               pipe_config->dpll_hw_state.spll);
12175         } else {
12176                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12177                               "fp0: 0x%x, fp1: 0x%x\n",
12178                               pipe_config->dpll_hw_state.dpll,
12179                               pipe_config->dpll_hw_state.dpll_md,
12180                               pipe_config->dpll_hw_state.fp0,
12181                               pipe_config->dpll_hw_state.fp1);
12182         }
12183
12184         DRM_DEBUG_KMS("planes on this crtc\n");
12185         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12186                 intel_plane = to_intel_plane(plane);
12187                 if (intel_plane->pipe != crtc->pipe)
12188                         continue;
12189
12190                 state = to_intel_plane_state(plane->state);
12191                 fb = state->base.fb;
12192                 if (!fb) {
12193                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12194                                 "disabled, scaler_id = %d\n",
12195                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12196                                 plane->base.id, intel_plane->pipe,
12197                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12198                                 drm_plane_index(plane), state->scaler_id);
12199                         continue;
12200                 }
12201
12202                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12203                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12204                         plane->base.id, intel_plane->pipe,
12205                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12206                         drm_plane_index(plane));
12207                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12208                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12209                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12210                         state->scaler_id,
12211                         state->src.x1 >> 16, state->src.y1 >> 16,
12212                         drm_rect_width(&state->src) >> 16,
12213                         drm_rect_height(&state->src) >> 16,
12214                         state->dst.x1, state->dst.y1,
12215                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12216         }
12217 }
12218
12219 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12220 {
12221         struct drm_device *dev = state->dev;
12222         struct drm_connector *connector;
12223         unsigned int used_ports = 0;
12224
12225         /*
12226          * Walk the connector list instead of the encoder
12227          * list to detect the problem on ddi platforms
12228          * where there's just one encoder per digital port.
12229          */
12230         drm_for_each_connector(connector, dev) {
12231                 struct drm_connector_state *connector_state;
12232                 struct intel_encoder *encoder;
12233
12234                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12235                 if (!connector_state)
12236                         connector_state = connector->state;
12237
12238                 if (!connector_state->best_encoder)
12239                         continue;
12240
12241                 encoder = to_intel_encoder(connector_state->best_encoder);
12242
12243                 WARN_ON(!connector_state->crtc);
12244
12245                 switch (encoder->type) {
12246                         unsigned int port_mask;
12247                 case INTEL_OUTPUT_UNKNOWN:
12248                         if (WARN_ON(!HAS_DDI(dev)))
12249                                 break;
12250                 case INTEL_OUTPUT_DISPLAYPORT:
12251                 case INTEL_OUTPUT_HDMI:
12252                 case INTEL_OUTPUT_EDP:
12253                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12254
12255                         /* the same port mustn't appear more than once */
12256                         if (used_ports & port_mask)
12257                                 return false;
12258
12259                         used_ports |= port_mask;
12260                 default:
12261                         break;
12262                 }
12263         }
12264
12265         return true;
12266 }
12267
12268 static void
12269 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12270 {
12271         struct drm_crtc_state tmp_state;
12272         struct intel_crtc_scaler_state scaler_state;
12273         struct intel_dpll_hw_state dpll_hw_state;
12274         struct intel_shared_dpll *shared_dpll;
12275         uint32_t ddi_pll_sel;
12276         bool force_thru;
12277
12278         /* FIXME: before the switch to atomic started, a new pipe_config was
12279          * kzalloc'd. Code that depends on any field being zero should be
12280          * fixed, so that the crtc_state can be safely duplicated. For now,
12281          * only fields that are know to not cause problems are preserved. */
12282
12283         tmp_state = crtc_state->base;
12284         scaler_state = crtc_state->scaler_state;
12285         shared_dpll = crtc_state->shared_dpll;
12286         dpll_hw_state = crtc_state->dpll_hw_state;
12287         ddi_pll_sel = crtc_state->ddi_pll_sel;
12288         force_thru = crtc_state->pch_pfit.force_thru;
12289
12290         memset(crtc_state, 0, sizeof *crtc_state);
12291
12292         crtc_state->base = tmp_state;
12293         crtc_state->scaler_state = scaler_state;
12294         crtc_state->shared_dpll = shared_dpll;
12295         crtc_state->dpll_hw_state = dpll_hw_state;
12296         crtc_state->ddi_pll_sel = ddi_pll_sel;
12297         crtc_state->pch_pfit.force_thru = force_thru;
12298 }
12299
12300 static int
12301 intel_modeset_pipe_config(struct drm_crtc *crtc,
12302                           struct intel_crtc_state *pipe_config)
12303 {
12304         struct drm_atomic_state *state = pipe_config->base.state;
12305         struct intel_encoder *encoder;
12306         struct drm_connector *connector;
12307         struct drm_connector_state *connector_state;
12308         int base_bpp, ret = -EINVAL;
12309         int i;
12310         bool retry = true;
12311
12312         clear_intel_crtc_state(pipe_config);
12313
12314         pipe_config->cpu_transcoder =
12315                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12316
12317         /*
12318          * Sanitize sync polarity flags based on requested ones. If neither
12319          * positive or negative polarity is requested, treat this as meaning
12320          * negative polarity.
12321          */
12322         if (!(pipe_config->base.adjusted_mode.flags &
12323               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12324                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12325
12326         if (!(pipe_config->base.adjusted_mode.flags &
12327               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12328                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12329
12330         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12331                                              pipe_config);
12332         if (base_bpp < 0)
12333                 goto fail;
12334
12335         /*
12336          * Determine the real pipe dimensions. Note that stereo modes can
12337          * increase the actual pipe size due to the frame doubling and
12338          * insertion of additional space for blanks between the frame. This
12339          * is stored in the crtc timings. We use the requested mode to do this
12340          * computation to clearly distinguish it from the adjusted mode, which
12341          * can be changed by the connectors in the below retry loop.
12342          */
12343         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12344                                &pipe_config->pipe_src_w,
12345                                &pipe_config->pipe_src_h);
12346
12347 encoder_retry:
12348         /* Ensure the port clock defaults are reset when retrying. */
12349         pipe_config->port_clock = 0;
12350         pipe_config->pixel_multiplier = 1;
12351
12352         /* Fill in default crtc timings, allow encoders to overwrite them. */
12353         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12354                               CRTC_STEREO_DOUBLE);
12355
12356         /* Pass our mode to the connectors and the CRTC to give them a chance to
12357          * adjust it according to limitations or connector properties, and also
12358          * a chance to reject the mode entirely.
12359          */
12360         for_each_connector_in_state(state, connector, connector_state, i) {
12361                 if (connector_state->crtc != crtc)
12362                         continue;
12363
12364                 encoder = to_intel_encoder(connector_state->best_encoder);
12365
12366                 if (!(encoder->compute_config(encoder, pipe_config))) {
12367                         DRM_DEBUG_KMS("Encoder config failure\n");
12368                         goto fail;
12369                 }
12370         }
12371
12372         /* Set default port clock if not overwritten by the encoder. Needs to be
12373          * done afterwards in case the encoder adjusts the mode. */
12374         if (!pipe_config->port_clock)
12375                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12376                         * pipe_config->pixel_multiplier;
12377
12378         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12379         if (ret < 0) {
12380                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12381                 goto fail;
12382         }
12383
12384         if (ret == RETRY) {
12385                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12386                         ret = -EINVAL;
12387                         goto fail;
12388                 }
12389
12390                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12391                 retry = false;
12392                 goto encoder_retry;
12393         }
12394
12395         /* Dithering seems to not pass-through bits correctly when it should, so
12396          * only enable it on 6bpc panels. */
12397         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12398         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12399                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12400
12401 fail:
12402         return ret;
12403 }
12404
12405 static void
12406 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12407 {
12408         struct drm_crtc *crtc;
12409         struct drm_crtc_state *crtc_state;
12410         int i;
12411
12412         /* Double check state. */
12413         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12414                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12415
12416                 /* Update hwmode for vblank functions */
12417                 if (crtc->state->active)
12418                         crtc->hwmode = crtc->state->adjusted_mode;
12419                 else
12420                         crtc->hwmode.crtc_clock = 0;
12421
12422                 /*
12423                  * Update legacy state to satisfy fbc code. This can
12424                  * be removed when fbc uses the atomic state.
12425                  */
12426                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12427                         struct drm_plane_state *plane_state = crtc->primary->state;
12428
12429                         crtc->primary->fb = plane_state->fb;
12430                         crtc->x = plane_state->src_x >> 16;
12431                         crtc->y = plane_state->src_y >> 16;
12432                 }
12433         }
12434 }
12435
12436 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12437 {
12438         int diff;
12439
12440         if (clock1 == clock2)
12441                 return true;
12442
12443         if (!clock1 || !clock2)
12444                 return false;
12445
12446         diff = abs(clock1 - clock2);
12447
12448         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12449                 return true;
12450
12451         return false;
12452 }
12453
12454 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12455         list_for_each_entry((intel_crtc), \
12456                             &(dev)->mode_config.crtc_list, \
12457                             base.head) \
12458                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12459
12460 static bool
12461 intel_compare_m_n(unsigned int m, unsigned int n,
12462                   unsigned int m2, unsigned int n2,
12463                   bool exact)
12464 {
12465         if (m == m2 && n == n2)
12466                 return true;
12467
12468         if (exact || !m || !n || !m2 || !n2)
12469                 return false;
12470
12471         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12472
12473         if (n > n2) {
12474                 while (n > n2) {
12475                         m2 <<= 1;
12476                         n2 <<= 1;
12477                 }
12478         } else if (n < n2) {
12479                 while (n < n2) {
12480                         m <<= 1;
12481                         n <<= 1;
12482                 }
12483         }
12484
12485         if (n != n2)
12486                 return false;
12487
12488         return intel_fuzzy_clock_check(m, m2);
12489 }
12490
12491 static bool
12492 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12493                        struct intel_link_m_n *m2_n2,
12494                        bool adjust)
12495 {
12496         if (m_n->tu == m2_n2->tu &&
12497             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12498                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12499             intel_compare_m_n(m_n->link_m, m_n->link_n,
12500                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12501                 if (adjust)
12502                         *m2_n2 = *m_n;
12503
12504                 return true;
12505         }
12506
12507         return false;
12508 }
12509
12510 static bool
12511 intel_pipe_config_compare(struct drm_device *dev,
12512                           struct intel_crtc_state *current_config,
12513                           struct intel_crtc_state *pipe_config,
12514                           bool adjust)
12515 {
12516         bool ret = true;
12517
12518 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12519         do { \
12520                 if (!adjust) \
12521                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12522                 else \
12523                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12524         } while (0)
12525
12526 #define PIPE_CONF_CHECK_X(name) \
12527         if (current_config->name != pipe_config->name) { \
12528                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12529                           "(expected 0x%08x, found 0x%08x)\n", \
12530                           current_config->name, \
12531                           pipe_config->name); \
12532                 ret = false; \
12533         }
12534
12535 #define PIPE_CONF_CHECK_I(name) \
12536         if (current_config->name != pipe_config->name) { \
12537                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12538                           "(expected %i, found %i)\n", \
12539                           current_config->name, \
12540                           pipe_config->name); \
12541                 ret = false; \
12542         }
12543
12544 #define PIPE_CONF_CHECK_P(name) \
12545         if (current_config->name != pipe_config->name) { \
12546                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12547                           "(expected %p, found %p)\n", \
12548                           current_config->name, \
12549                           pipe_config->name); \
12550                 ret = false; \
12551         }
12552
12553 #define PIPE_CONF_CHECK_M_N(name) \
12554         if (!intel_compare_link_m_n(&current_config->name, \
12555                                     &pipe_config->name,\
12556                                     adjust)) { \
12557                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12558                           "(expected tu %i gmch %i/%i link %i/%i, " \
12559                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12560                           current_config->name.tu, \
12561                           current_config->name.gmch_m, \
12562                           current_config->name.gmch_n, \
12563                           current_config->name.link_m, \
12564                           current_config->name.link_n, \
12565                           pipe_config->name.tu, \
12566                           pipe_config->name.gmch_m, \
12567                           pipe_config->name.gmch_n, \
12568                           pipe_config->name.link_m, \
12569                           pipe_config->name.link_n); \
12570                 ret = false; \
12571         }
12572
12573 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12574         if (!intel_compare_link_m_n(&current_config->name, \
12575                                     &pipe_config->name, adjust) && \
12576             !intel_compare_link_m_n(&current_config->alt_name, \
12577                                     &pipe_config->name, adjust)) { \
12578                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12579                           "(expected tu %i gmch %i/%i link %i/%i, " \
12580                           "or tu %i gmch %i/%i link %i/%i, " \
12581                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12582                           current_config->name.tu, \
12583                           current_config->name.gmch_m, \
12584                           current_config->name.gmch_n, \
12585                           current_config->name.link_m, \
12586                           current_config->name.link_n, \
12587                           current_config->alt_name.tu, \
12588                           current_config->alt_name.gmch_m, \
12589                           current_config->alt_name.gmch_n, \
12590                           current_config->alt_name.link_m, \
12591                           current_config->alt_name.link_n, \
12592                           pipe_config->name.tu, \
12593                           pipe_config->name.gmch_m, \
12594                           pipe_config->name.gmch_n, \
12595                           pipe_config->name.link_m, \
12596                           pipe_config->name.link_n); \
12597                 ret = false; \
12598         }
12599
12600 /* This is required for BDW+ where there is only one set of registers for
12601  * switching between high and low RR.
12602  * This macro can be used whenever a comparison has to be made between one
12603  * hw state and multiple sw state variables.
12604  */
12605 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12606         if ((current_config->name != pipe_config->name) && \
12607                 (current_config->alt_name != pipe_config->name)) { \
12608                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12609                                   "(expected %i or %i, found %i)\n", \
12610                                   current_config->name, \
12611                                   current_config->alt_name, \
12612                                   pipe_config->name); \
12613                         ret = false; \
12614         }
12615
12616 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12617         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12618                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12619                           "(expected %i, found %i)\n", \
12620                           current_config->name & (mask), \
12621                           pipe_config->name & (mask)); \
12622                 ret = false; \
12623         }
12624
12625 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12626         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12627                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12628                           "(expected %i, found %i)\n", \
12629                           current_config->name, \
12630                           pipe_config->name); \
12631                 ret = false; \
12632         }
12633
12634 #define PIPE_CONF_QUIRK(quirk)  \
12635         ((current_config->quirks | pipe_config->quirks) & (quirk))
12636
12637         PIPE_CONF_CHECK_I(cpu_transcoder);
12638
12639         PIPE_CONF_CHECK_I(has_pch_encoder);
12640         PIPE_CONF_CHECK_I(fdi_lanes);
12641         PIPE_CONF_CHECK_M_N(fdi_m_n);
12642
12643         PIPE_CONF_CHECK_I(has_dp_encoder);
12644         PIPE_CONF_CHECK_I(lane_count);
12645
12646         if (INTEL_INFO(dev)->gen < 8) {
12647                 PIPE_CONF_CHECK_M_N(dp_m_n);
12648
12649                 if (current_config->has_drrs)
12650                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12651         } else
12652                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12653
12654         PIPE_CONF_CHECK_I(has_dsi_encoder);
12655
12656         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12657         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12658         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12659         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12660         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12661         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12662
12663         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12664         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12665         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12666         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12667         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12668         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12669
12670         PIPE_CONF_CHECK_I(pixel_multiplier);
12671         PIPE_CONF_CHECK_I(has_hdmi_sink);
12672         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12673             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12674                 PIPE_CONF_CHECK_I(limited_color_range);
12675         PIPE_CONF_CHECK_I(has_infoframe);
12676
12677         PIPE_CONF_CHECK_I(has_audio);
12678
12679         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12680                               DRM_MODE_FLAG_INTERLACE);
12681
12682         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12683                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12684                                       DRM_MODE_FLAG_PHSYNC);
12685                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12686                                       DRM_MODE_FLAG_NHSYNC);
12687                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12688                                       DRM_MODE_FLAG_PVSYNC);
12689                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12690                                       DRM_MODE_FLAG_NVSYNC);
12691         }
12692
12693         PIPE_CONF_CHECK_X(gmch_pfit.control);
12694         /* pfit ratios are autocomputed by the hw on gen4+ */
12695         if (INTEL_INFO(dev)->gen < 4)
12696                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12697         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12698
12699         if (!adjust) {
12700                 PIPE_CONF_CHECK_I(pipe_src_w);
12701                 PIPE_CONF_CHECK_I(pipe_src_h);
12702
12703                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12704                 if (current_config->pch_pfit.enabled) {
12705                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12706                         PIPE_CONF_CHECK_X(pch_pfit.size);
12707                 }
12708
12709                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12710         }
12711
12712         /* BDW+ don't expose a synchronous way to read the state */
12713         if (IS_HASWELL(dev))
12714                 PIPE_CONF_CHECK_I(ips_enabled);
12715
12716         PIPE_CONF_CHECK_I(double_wide);
12717
12718         PIPE_CONF_CHECK_X(ddi_pll_sel);
12719
12720         PIPE_CONF_CHECK_P(shared_dpll);
12721         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12722         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12723         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12724         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12725         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12726         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12727         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12728         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12729         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12730
12731         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12732                 PIPE_CONF_CHECK_I(pipe_bpp);
12733
12734         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12735         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12736
12737 #undef PIPE_CONF_CHECK_X
12738 #undef PIPE_CONF_CHECK_I
12739 #undef PIPE_CONF_CHECK_P
12740 #undef PIPE_CONF_CHECK_I_ALT
12741 #undef PIPE_CONF_CHECK_FLAGS
12742 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12743 #undef PIPE_CONF_QUIRK
12744 #undef INTEL_ERR_OR_DBG_KMS
12745
12746         return ret;
12747 }
12748
12749 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12750                                            const struct intel_crtc_state *pipe_config)
12751 {
12752         if (pipe_config->has_pch_encoder) {
12753                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12754                                                             &pipe_config->fdi_m_n);
12755                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12756
12757                 /*
12758                  * FDI already provided one idea for the dotclock.
12759                  * Yell if the encoder disagrees.
12760                  */
12761                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12762                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12763                      fdi_dotclock, dotclock);
12764         }
12765 }
12766
12767 static void check_wm_state(struct drm_device *dev)
12768 {
12769         struct drm_i915_private *dev_priv = dev->dev_private;
12770         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12771         struct intel_crtc *intel_crtc;
12772         int plane;
12773
12774         if (INTEL_INFO(dev)->gen < 9)
12775                 return;
12776
12777         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12778         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12779
12780         for_each_intel_crtc(dev, intel_crtc) {
12781                 struct skl_ddb_entry *hw_entry, *sw_entry;
12782                 const enum pipe pipe = intel_crtc->pipe;
12783
12784                 if (!intel_crtc->active)
12785                         continue;
12786
12787                 /* planes */
12788                 for_each_plane(dev_priv, pipe, plane) {
12789                         hw_entry = &hw_ddb.plane[pipe][plane];
12790                         sw_entry = &sw_ddb->plane[pipe][plane];
12791
12792                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12793                                 continue;
12794
12795                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12796                                   "(expected (%u,%u), found (%u,%u))\n",
12797                                   pipe_name(pipe), plane + 1,
12798                                   sw_entry->start, sw_entry->end,
12799                                   hw_entry->start, hw_entry->end);
12800                 }
12801
12802                 /* cursor */
12803                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12804                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12805
12806                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12807                         continue;
12808
12809                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12810                           "(expected (%u,%u), found (%u,%u))\n",
12811                           pipe_name(pipe),
12812                           sw_entry->start, sw_entry->end,
12813                           hw_entry->start, hw_entry->end);
12814         }
12815 }
12816
12817 static void
12818 check_connector_state(struct drm_device *dev,
12819                       struct drm_atomic_state *old_state)
12820 {
12821         struct drm_connector_state *old_conn_state;
12822         struct drm_connector *connector;
12823         int i;
12824
12825         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12826                 struct drm_encoder *encoder = connector->encoder;
12827                 struct drm_connector_state *state = connector->state;
12828
12829                 /* This also checks the encoder/connector hw state with the
12830                  * ->get_hw_state callbacks. */
12831                 intel_connector_check_state(to_intel_connector(connector));
12832
12833                 I915_STATE_WARN(state->best_encoder != encoder,
12834                      "connector's atomic encoder doesn't match legacy encoder\n");
12835         }
12836 }
12837
12838 static void
12839 check_encoder_state(struct drm_device *dev)
12840 {
12841         struct intel_encoder *encoder;
12842         struct intel_connector *connector;
12843
12844         for_each_intel_encoder(dev, encoder) {
12845                 bool enabled = false;
12846                 enum pipe pipe;
12847
12848                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12849                               encoder->base.base.id,
12850                               encoder->base.name);
12851
12852                 for_each_intel_connector(dev, connector) {
12853                         if (connector->base.state->best_encoder != &encoder->base)
12854                                 continue;
12855                         enabled = true;
12856
12857                         I915_STATE_WARN(connector->base.state->crtc !=
12858                                         encoder->base.crtc,
12859                              "connector's crtc doesn't match encoder crtc\n");
12860                 }
12861
12862                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12863                      "encoder's enabled state mismatch "
12864                      "(expected %i, found %i)\n",
12865                      !!encoder->base.crtc, enabled);
12866
12867                 if (!encoder->base.crtc) {
12868                         bool active;
12869
12870                         active = encoder->get_hw_state(encoder, &pipe);
12871                         I915_STATE_WARN(active,
12872                              "encoder detached but still enabled on pipe %c.\n",
12873                              pipe_name(pipe));
12874                 }
12875         }
12876 }
12877
12878 static void
12879 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12880 {
12881         struct drm_i915_private *dev_priv = dev->dev_private;
12882         struct intel_encoder *encoder;
12883         struct drm_crtc_state *old_crtc_state;
12884         struct drm_crtc *crtc;
12885         int i;
12886
12887         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12888                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12889                 struct intel_crtc_state *pipe_config, *sw_config;
12890                 bool active;
12891
12892                 if (!needs_modeset(crtc->state) &&
12893                     !to_intel_crtc_state(crtc->state)->update_pipe)
12894                         continue;
12895
12896                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12897                 pipe_config = to_intel_crtc_state(old_crtc_state);
12898                 memset(pipe_config, 0, sizeof(*pipe_config));
12899                 pipe_config->base.crtc = crtc;
12900                 pipe_config->base.state = old_state;
12901
12902                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12903                               crtc->base.id);
12904
12905                 active = dev_priv->display.get_pipe_config(intel_crtc,
12906                                                            pipe_config);
12907
12908                 /* hw state is inconsistent with the pipe quirk */
12909                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12910                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12911                         active = crtc->state->active;
12912
12913                 I915_STATE_WARN(crtc->state->active != active,
12914                      "crtc active state doesn't match with hw state "
12915                      "(expected %i, found %i)\n", crtc->state->active, active);
12916
12917                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12918                      "transitional active state does not match atomic hw state "
12919                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12920
12921                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12922                         enum pipe pipe;
12923
12924                         active = encoder->get_hw_state(encoder, &pipe);
12925                         I915_STATE_WARN(active != crtc->state->active,
12926                                 "[ENCODER:%i] active %i with crtc active %i\n",
12927                                 encoder->base.base.id, active, crtc->state->active);
12928
12929                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12930                                         "Encoder connected to wrong pipe %c\n",
12931                                         pipe_name(pipe));
12932
12933                         if (active)
12934                                 encoder->get_config(encoder, pipe_config);
12935                 }
12936
12937                 if (!crtc->state->active)
12938                         continue;
12939
12940                 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12941
12942                 sw_config = to_intel_crtc_state(crtc->state);
12943                 if (!intel_pipe_config_compare(dev, sw_config,
12944                                                pipe_config, false)) {
12945                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12946                         intel_dump_pipe_config(intel_crtc, pipe_config,
12947                                                "[hw state]");
12948                         intel_dump_pipe_config(intel_crtc, sw_config,
12949                                                "[sw state]");
12950                 }
12951         }
12952 }
12953
12954 static void
12955 check_shared_dpll_state(struct drm_device *dev)
12956 {
12957         struct drm_i915_private *dev_priv = dev->dev_private;
12958         struct intel_crtc *crtc;
12959         struct intel_dpll_hw_state dpll_hw_state;
12960         int i;
12961
12962         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12963                 struct intel_shared_dpll *pll =
12964                         intel_get_shared_dpll_by_id(dev_priv, i);
12965                 unsigned enabled_crtcs = 0, active_crtcs = 0;
12966                 bool active;
12967
12968                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12969
12970                 DRM_DEBUG_KMS("%s\n", pll->name);
12971
12972                 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12973
12974                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12975                      "more active pll users than references: %x vs %x\n",
12976                      pll->active_mask, pll->config.crtc_mask);
12977
12978                 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12979                         I915_STATE_WARN(!pll->on && pll->active_mask,
12980                              "pll in active use but not on in sw tracking\n");
12981                         I915_STATE_WARN(pll->on && !pll->active_mask,
12982                              "pll is on but not used by any active crtc\n");
12983                         I915_STATE_WARN(pll->on != active,
12984                              "pll on state mismatch (expected %i, found %i)\n",
12985                              pll->on, active);
12986                 }
12987
12988                 for_each_intel_crtc(dev, crtc) {
12989                         if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12990                                 enabled_crtcs |= 1 << drm_crtc_index(&crtc->base);
12991                         if (crtc->base.state->active && crtc->config->shared_dpll == pll)
12992                                 active_crtcs |= 1 << drm_crtc_index(&crtc->base);
12993                 }
12994
12995                 I915_STATE_WARN(pll->active_mask != active_crtcs,
12996                      "pll active crtcs mismatch (expected %x, found %x)\n",
12997                      pll->active_mask, active_crtcs);
12998                 I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs,
12999                      "pll enabled crtcs mismatch (expected %x, found %x)\n",
13000                      pll->config.crtc_mask, enabled_crtcs);
13001
13002                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13003                                        sizeof(dpll_hw_state)),
13004                      "pll hw state mismatch\n");
13005         }
13006 }
13007
13008 static void
13009 intel_modeset_check_state(struct drm_device *dev,
13010                           struct drm_atomic_state *old_state)
13011 {
13012         check_wm_state(dev);
13013         check_connector_state(dev, old_state);
13014         check_encoder_state(dev);
13015         check_crtc_state(dev, old_state);
13016         check_shared_dpll_state(dev);
13017 }
13018
13019 static void update_scanline_offset(struct intel_crtc *crtc)
13020 {
13021         struct drm_device *dev = crtc->base.dev;
13022
13023         /*
13024          * The scanline counter increments at the leading edge of hsync.
13025          *
13026          * On most platforms it starts counting from vtotal-1 on the
13027          * first active line. That means the scanline counter value is
13028          * always one less than what we would expect. Ie. just after
13029          * start of vblank, which also occurs at start of hsync (on the
13030          * last active line), the scanline counter will read vblank_start-1.
13031          *
13032          * On gen2 the scanline counter starts counting from 1 instead
13033          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13034          * to keep the value positive), instead of adding one.
13035          *
13036          * On HSW+ the behaviour of the scanline counter depends on the output
13037          * type. For DP ports it behaves like most other platforms, but on HDMI
13038          * there's an extra 1 line difference. So we need to add two instead of
13039          * one to the value.
13040          */
13041         if (IS_GEN2(dev)) {
13042                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13043                 int vtotal;
13044
13045                 vtotal = adjusted_mode->crtc_vtotal;
13046                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13047                         vtotal /= 2;
13048
13049                 crtc->scanline_offset = vtotal - 1;
13050         } else if (HAS_DDI(dev) &&
13051                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13052                 crtc->scanline_offset = 2;
13053         } else
13054                 crtc->scanline_offset = 1;
13055 }
13056
13057 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13058 {
13059         struct drm_device *dev = state->dev;
13060         struct drm_i915_private *dev_priv = to_i915(dev);
13061         struct intel_shared_dpll_config *shared_dpll = NULL;
13062         struct drm_crtc *crtc;
13063         struct drm_crtc_state *crtc_state;
13064         int i;
13065
13066         if (!dev_priv->display.crtc_compute_clock)
13067                 return;
13068
13069         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13070                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13071                 struct intel_shared_dpll *old_dpll =
13072                         to_intel_crtc_state(crtc->state)->shared_dpll;
13073
13074                 if (!needs_modeset(crtc_state))
13075                         continue;
13076
13077                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13078
13079                 if (!old_dpll)
13080                         continue;
13081
13082                 if (!shared_dpll)
13083                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13084
13085                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13086         }
13087 }
13088
13089 /*
13090  * This implements the workaround described in the "notes" section of the mode
13091  * set sequence documentation. When going from no pipes or single pipe to
13092  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13093  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13094  */
13095 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13096 {
13097         struct drm_crtc_state *crtc_state;
13098         struct intel_crtc *intel_crtc;
13099         struct drm_crtc *crtc;
13100         struct intel_crtc_state *first_crtc_state = NULL;
13101         struct intel_crtc_state *other_crtc_state = NULL;
13102         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13103         int i;
13104
13105         /* look at all crtc's that are going to be enabled in during modeset */
13106         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13107                 intel_crtc = to_intel_crtc(crtc);
13108
13109                 if (!crtc_state->active || !needs_modeset(crtc_state))
13110                         continue;
13111
13112                 if (first_crtc_state) {
13113                         other_crtc_state = to_intel_crtc_state(crtc_state);
13114                         break;
13115                 } else {
13116                         first_crtc_state = to_intel_crtc_state(crtc_state);
13117                         first_pipe = intel_crtc->pipe;
13118                 }
13119         }
13120
13121         /* No workaround needed? */
13122         if (!first_crtc_state)
13123                 return 0;
13124
13125         /* w/a possibly needed, check how many crtc's are already enabled. */
13126         for_each_intel_crtc(state->dev, intel_crtc) {
13127                 struct intel_crtc_state *pipe_config;
13128
13129                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13130                 if (IS_ERR(pipe_config))
13131                         return PTR_ERR(pipe_config);
13132
13133                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13134
13135                 if (!pipe_config->base.active ||
13136                     needs_modeset(&pipe_config->base))
13137                         continue;
13138
13139                 /* 2 or more enabled crtcs means no need for w/a */
13140                 if (enabled_pipe != INVALID_PIPE)
13141                         return 0;
13142
13143                 enabled_pipe = intel_crtc->pipe;
13144         }
13145
13146         if (enabled_pipe != INVALID_PIPE)
13147                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13148         else if (other_crtc_state)
13149                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13150
13151         return 0;
13152 }
13153
13154 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13155 {
13156         struct drm_crtc *crtc;
13157         struct drm_crtc_state *crtc_state;
13158         int ret = 0;
13159
13160         /* add all active pipes to the state */
13161         for_each_crtc(state->dev, crtc) {
13162                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13163                 if (IS_ERR(crtc_state))
13164                         return PTR_ERR(crtc_state);
13165
13166                 if (!crtc_state->active || needs_modeset(crtc_state))
13167                         continue;
13168
13169                 crtc_state->mode_changed = true;
13170
13171                 ret = drm_atomic_add_affected_connectors(state, crtc);
13172                 if (ret)
13173                         break;
13174
13175                 ret = drm_atomic_add_affected_planes(state, crtc);
13176                 if (ret)
13177                         break;
13178         }
13179
13180         return ret;
13181 }
13182
13183 static int intel_modeset_checks(struct drm_atomic_state *state)
13184 {
13185         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13186         struct drm_i915_private *dev_priv = state->dev->dev_private;
13187         struct drm_crtc *crtc;
13188         struct drm_crtc_state *crtc_state;
13189         int ret = 0, i;
13190
13191         if (!check_digital_port_conflicts(state)) {
13192                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13193                 return -EINVAL;
13194         }
13195
13196         intel_state->modeset = true;
13197         intel_state->active_crtcs = dev_priv->active_crtcs;
13198
13199         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13200                 if (crtc_state->active)
13201                         intel_state->active_crtcs |= 1 << i;
13202                 else
13203                         intel_state->active_crtcs &= ~(1 << i);
13204         }
13205
13206         /*
13207          * See if the config requires any additional preparation, e.g.
13208          * to adjust global state with pipes off.  We need to do this
13209          * here so we can get the modeset_pipe updated config for the new
13210          * mode set on this crtc.  For other crtcs we need to use the
13211          * adjusted_mode bits in the crtc directly.
13212          */
13213         if (dev_priv->display.modeset_calc_cdclk) {
13214                 ret = dev_priv->display.modeset_calc_cdclk(state);
13215
13216                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13217                         ret = intel_modeset_all_pipes(state);
13218
13219                 if (ret < 0)
13220                         return ret;
13221
13222                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13223                               intel_state->cdclk, intel_state->dev_cdclk);
13224         } else
13225                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13226
13227         intel_modeset_clear_plls(state);
13228
13229         if (IS_HASWELL(dev_priv))
13230                 return haswell_mode_set_planes_workaround(state);
13231
13232         return 0;
13233 }
13234
13235 /*
13236  * Handle calculation of various watermark data at the end of the atomic check
13237  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13238  * handlers to ensure that all derived state has been updated.
13239  */
13240 static void calc_watermark_data(struct drm_atomic_state *state)
13241 {
13242         struct drm_device *dev = state->dev;
13243         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13244         struct drm_crtc *crtc;
13245         struct drm_crtc_state *cstate;
13246         struct drm_plane *plane;
13247         struct drm_plane_state *pstate;
13248
13249         /*
13250          * Calculate watermark configuration details now that derived
13251          * plane/crtc state is all properly updated.
13252          */
13253         drm_for_each_crtc(crtc, dev) {
13254                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13255                         crtc->state;
13256
13257                 if (cstate->active)
13258                         intel_state->wm_config.num_pipes_active++;
13259         }
13260         drm_for_each_legacy_plane(plane, dev) {
13261                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13262                         plane->state;
13263
13264                 if (!to_intel_plane_state(pstate)->visible)
13265                         continue;
13266
13267                 intel_state->wm_config.sprites_enabled = true;
13268                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13269                     pstate->crtc_h != pstate->src_h >> 16)
13270                         intel_state->wm_config.sprites_scaled = true;
13271         }
13272 }
13273
13274 /**
13275  * intel_atomic_check - validate state object
13276  * @dev: drm device
13277  * @state: state to validate
13278  */
13279 static int intel_atomic_check(struct drm_device *dev,
13280                               struct drm_atomic_state *state)
13281 {
13282         struct drm_i915_private *dev_priv = to_i915(dev);
13283         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13284         struct drm_crtc *crtc;
13285         struct drm_crtc_state *crtc_state;
13286         int ret, i;
13287         bool any_ms = false;
13288
13289         ret = drm_atomic_helper_check_modeset(dev, state);
13290         if (ret)
13291                 return ret;
13292
13293         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13294                 struct intel_crtc_state *pipe_config =
13295                         to_intel_crtc_state(crtc_state);
13296
13297                 /* Catch I915_MODE_FLAG_INHERITED */
13298                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13299                         crtc_state->mode_changed = true;
13300
13301                 if (!crtc_state->enable) {
13302                         if (needs_modeset(crtc_state))
13303                                 any_ms = true;
13304                         continue;
13305                 }
13306
13307                 if (!needs_modeset(crtc_state))
13308                         continue;
13309
13310                 /* FIXME: For only active_changed we shouldn't need to do any
13311                  * state recomputation at all. */
13312
13313                 ret = drm_atomic_add_affected_connectors(state, crtc);
13314                 if (ret)
13315                         return ret;
13316
13317                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13318                 if (ret)
13319                         return ret;
13320
13321                 if (i915.fastboot &&
13322                     intel_pipe_config_compare(dev,
13323                                         to_intel_crtc_state(crtc->state),
13324                                         pipe_config, true)) {
13325                         crtc_state->mode_changed = false;
13326                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13327                 }
13328
13329                 if (needs_modeset(crtc_state)) {
13330                         any_ms = true;
13331
13332                         ret = drm_atomic_add_affected_planes(state, crtc);
13333                         if (ret)
13334                                 return ret;
13335                 }
13336
13337                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13338                                        needs_modeset(crtc_state) ?
13339                                        "[modeset]" : "[fastset]");
13340         }
13341
13342         if (any_ms) {
13343                 ret = intel_modeset_checks(state);
13344
13345                 if (ret)
13346                         return ret;
13347         } else
13348                 intel_state->cdclk = dev_priv->cdclk_freq;
13349
13350         ret = drm_atomic_helper_check_planes(dev, state);
13351         if (ret)
13352                 return ret;
13353
13354         intel_fbc_choose_crtc(dev_priv, state);
13355         calc_watermark_data(state);
13356
13357         return 0;
13358 }
13359
13360 static int intel_atomic_prepare_commit(struct drm_device *dev,
13361                                        struct drm_atomic_state *state,
13362                                        bool async)
13363 {
13364         struct drm_i915_private *dev_priv = dev->dev_private;
13365         struct drm_plane_state *plane_state;
13366         struct drm_crtc_state *crtc_state;
13367         struct drm_plane *plane;
13368         struct drm_crtc *crtc;
13369         int i, ret;
13370
13371         if (async) {
13372                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13373                 return -EINVAL;
13374         }
13375
13376         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13377                 ret = intel_crtc_wait_for_pending_flips(crtc);
13378                 if (ret)
13379                         return ret;
13380
13381                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13382                         flush_workqueue(dev_priv->wq);
13383         }
13384
13385         ret = mutex_lock_interruptible(&dev->struct_mutex);
13386         if (ret)
13387                 return ret;
13388
13389         ret = drm_atomic_helper_prepare_planes(dev, state);
13390         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13391                 u32 reset_counter;
13392
13393                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13394                 mutex_unlock(&dev->struct_mutex);
13395
13396                 for_each_plane_in_state(state, plane, plane_state, i) {
13397                         struct intel_plane_state *intel_plane_state =
13398                                 to_intel_plane_state(plane_state);
13399
13400                         if (!intel_plane_state->wait_req)
13401                                 continue;
13402
13403                         ret = __i915_wait_request(intel_plane_state->wait_req,
13404                                                   reset_counter, true,
13405                                                   NULL, NULL);
13406
13407                         /* Swallow -EIO errors to allow updates during hw lockup. */
13408                         if (ret == -EIO)
13409                                 ret = 0;
13410
13411                         if (ret)
13412                                 break;
13413                 }
13414
13415                 if (!ret)
13416                         return 0;
13417
13418                 mutex_lock(&dev->struct_mutex);
13419                 drm_atomic_helper_cleanup_planes(dev, state);
13420         }
13421
13422         mutex_unlock(&dev->struct_mutex);
13423         return ret;
13424 }
13425
13426 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13427                                           struct drm_i915_private *dev_priv,
13428                                           unsigned crtc_mask)
13429 {
13430         unsigned last_vblank_count[I915_MAX_PIPES];
13431         enum pipe pipe;
13432         int ret;
13433
13434         if (!crtc_mask)
13435                 return;
13436
13437         for_each_pipe(dev_priv, pipe) {
13438                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13439
13440                 if (!((1 << pipe) & crtc_mask))
13441                         continue;
13442
13443                 ret = drm_crtc_vblank_get(crtc);
13444                 if (WARN_ON(ret != 0)) {
13445                         crtc_mask &= ~(1 << pipe);
13446                         continue;
13447                 }
13448
13449                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13450         }
13451
13452         for_each_pipe(dev_priv, pipe) {
13453                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13454                 long lret;
13455
13456                 if (!((1 << pipe) & crtc_mask))
13457                         continue;
13458
13459                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13460                                 last_vblank_count[pipe] !=
13461                                         drm_crtc_vblank_count(crtc),
13462                                 msecs_to_jiffies(50));
13463
13464                 WARN_ON(!lret);
13465
13466                 drm_crtc_vblank_put(crtc);
13467         }
13468 }
13469
13470 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13471 {
13472         /* fb updated, need to unpin old fb */
13473         if (crtc_state->fb_changed)
13474                 return true;
13475
13476         /* wm changes, need vblank before final wm's */
13477         if (crtc_state->update_wm_post)
13478                 return true;
13479
13480         /*
13481          * cxsr is re-enabled after vblank.
13482          * This is already handled by crtc_state->update_wm_post,
13483          * but added for clarity.
13484          */
13485         if (crtc_state->disable_cxsr)
13486                 return true;
13487
13488         return false;
13489 }
13490
13491 /**
13492  * intel_atomic_commit - commit validated state object
13493  * @dev: DRM device
13494  * @state: the top-level driver state object
13495  * @async: asynchronous commit
13496  *
13497  * This function commits a top-level state object that has been validated
13498  * with drm_atomic_helper_check().
13499  *
13500  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13501  * we can only handle plane-related operations and do not yet support
13502  * asynchronous commit.
13503  *
13504  * RETURNS
13505  * Zero for success or -errno.
13506  */
13507 static int intel_atomic_commit(struct drm_device *dev,
13508                                struct drm_atomic_state *state,
13509                                bool async)
13510 {
13511         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13512         struct drm_i915_private *dev_priv = dev->dev_private;
13513         struct drm_crtc_state *old_crtc_state;
13514         struct drm_crtc *crtc;
13515         struct intel_crtc_state *intel_cstate;
13516         int ret = 0, i;
13517         bool hw_check = intel_state->modeset;
13518         unsigned long put_domains[I915_MAX_PIPES] = {};
13519         unsigned crtc_vblank_mask = 0;
13520
13521         ret = intel_atomic_prepare_commit(dev, state, async);
13522         if (ret) {
13523                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13524                 return ret;
13525         }
13526
13527         drm_atomic_helper_swap_state(dev, state);
13528         dev_priv->wm.config = intel_state->wm_config;
13529         intel_shared_dpll_commit(state);
13530
13531         if (intel_state->modeset) {
13532                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13533                        sizeof(intel_state->min_pixclk));
13534                 dev_priv->active_crtcs = intel_state->active_crtcs;
13535                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13536
13537                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13538         }
13539
13540         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13541                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13542
13543                 if (needs_modeset(crtc->state) ||
13544                     to_intel_crtc_state(crtc->state)->update_pipe) {
13545                         hw_check = true;
13546
13547                         put_domains[to_intel_crtc(crtc)->pipe] =
13548                                 modeset_get_crtc_power_domains(crtc,
13549                                         to_intel_crtc_state(crtc->state));
13550                 }
13551
13552                 if (!needs_modeset(crtc->state))
13553                         continue;
13554
13555                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13556
13557                 if (old_crtc_state->active) {
13558                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13559                         dev_priv->display.crtc_disable(crtc);
13560                         intel_crtc->active = false;
13561                         intel_fbc_disable(intel_crtc);
13562                         intel_disable_shared_dpll(intel_crtc);
13563
13564                         /*
13565                          * Underruns don't always raise
13566                          * interrupts, so check manually.
13567                          */
13568                         intel_check_cpu_fifo_underruns(dev_priv);
13569                         intel_check_pch_fifo_underruns(dev_priv);
13570
13571                         if (!crtc->state->active)
13572                                 intel_update_watermarks(crtc);
13573                 }
13574         }
13575
13576         /* Only after disabling all output pipelines that will be changed can we
13577          * update the the output configuration. */
13578         intel_modeset_update_crtc_state(state);
13579
13580         if (intel_state->modeset) {
13581                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13582
13583                 if (dev_priv->display.modeset_commit_cdclk &&
13584                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13585                         dev_priv->display.modeset_commit_cdclk(state);
13586         }
13587
13588         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13589         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13590                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13591                 bool modeset = needs_modeset(crtc->state);
13592                 struct intel_crtc_state *pipe_config =
13593                         to_intel_crtc_state(crtc->state);
13594                 bool update_pipe = !modeset && pipe_config->update_pipe;
13595
13596                 if (modeset && crtc->state->active) {
13597                         update_scanline_offset(to_intel_crtc(crtc));
13598                         dev_priv->display.crtc_enable(crtc);
13599                 }
13600
13601                 if (!modeset)
13602                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13603
13604                 if (crtc->state->active &&
13605                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13606                         intel_fbc_enable(intel_crtc);
13607
13608                 if (crtc->state->active &&
13609                     (crtc->state->planes_changed || update_pipe))
13610                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13611
13612                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13613                         crtc_vblank_mask |= 1 << i;
13614         }
13615
13616         /* FIXME: add subpixel order */
13617
13618         if (!state->legacy_cursor_update)
13619                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13620
13621         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13622                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13623
13624                 if (put_domains[i])
13625                         modeset_put_power_domains(dev_priv, put_domains[i]);
13626         }
13627
13628         if (intel_state->modeset)
13629                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13630
13631         /*
13632          * Now that the vblank has passed, we can go ahead and program the
13633          * optimal watermarks on platforms that need two-step watermark
13634          * programming.
13635          *
13636          * TODO: Move this (and other cleanup) to an async worker eventually.
13637          */
13638         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13639                 intel_cstate = to_intel_crtc_state(crtc->state);
13640
13641                 if (dev_priv->display.optimize_watermarks)
13642                         dev_priv->display.optimize_watermarks(intel_cstate);
13643         }
13644
13645         mutex_lock(&dev->struct_mutex);
13646         drm_atomic_helper_cleanup_planes(dev, state);
13647         mutex_unlock(&dev->struct_mutex);
13648
13649         if (hw_check)
13650                 intel_modeset_check_state(dev, state);
13651
13652         drm_atomic_state_free(state);
13653
13654         /* As one of the primary mmio accessors, KMS has a high likelihood
13655          * of triggering bugs in unclaimed access. After we finish
13656          * modesetting, see if an error has been flagged, and if so
13657          * enable debugging for the next modeset - and hope we catch
13658          * the culprit.
13659          *
13660          * XXX note that we assume display power is on at this point.
13661          * This might hold true now but we need to add pm helper to check
13662          * unclaimed only when the hardware is on, as atomic commits
13663          * can happen also when the device is completely off.
13664          */
13665         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13666
13667         return 0;
13668 }
13669
13670 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13671 {
13672         struct drm_device *dev = crtc->dev;
13673         struct drm_atomic_state *state;
13674         struct drm_crtc_state *crtc_state;
13675         int ret;
13676
13677         state = drm_atomic_state_alloc(dev);
13678         if (!state) {
13679                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13680                               crtc->base.id);
13681                 return;
13682         }
13683
13684         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13685
13686 retry:
13687         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13688         ret = PTR_ERR_OR_ZERO(crtc_state);
13689         if (!ret) {
13690                 if (!crtc_state->active)
13691                         goto out;
13692
13693                 crtc_state->mode_changed = true;
13694                 ret = drm_atomic_commit(state);
13695         }
13696
13697         if (ret == -EDEADLK) {
13698                 drm_atomic_state_clear(state);
13699                 drm_modeset_backoff(state->acquire_ctx);
13700                 goto retry;
13701         }
13702
13703         if (ret)
13704 out:
13705                 drm_atomic_state_free(state);
13706 }
13707
13708 #undef for_each_intel_crtc_masked
13709
13710 static const struct drm_crtc_funcs intel_crtc_funcs = {
13711         .gamma_set = intel_crtc_gamma_set,
13712         .set_config = drm_atomic_helper_set_config,
13713         .destroy = intel_crtc_destroy,
13714         .page_flip = intel_crtc_page_flip,
13715         .atomic_duplicate_state = intel_crtc_duplicate_state,
13716         .atomic_destroy_state = intel_crtc_destroy_state,
13717 };
13718
13719 /**
13720  * intel_prepare_plane_fb - Prepare fb for usage on plane
13721  * @plane: drm plane to prepare for
13722  * @fb: framebuffer to prepare for presentation
13723  *
13724  * Prepares a framebuffer for usage on a display plane.  Generally this
13725  * involves pinning the underlying object and updating the frontbuffer tracking
13726  * bits.  Some older platforms need special physical address handling for
13727  * cursor planes.
13728  *
13729  * Must be called with struct_mutex held.
13730  *
13731  * Returns 0 on success, negative error code on failure.
13732  */
13733 int
13734 intel_prepare_plane_fb(struct drm_plane *plane,
13735                        const struct drm_plane_state *new_state)
13736 {
13737         struct drm_device *dev = plane->dev;
13738         struct drm_framebuffer *fb = new_state->fb;
13739         struct intel_plane *intel_plane = to_intel_plane(plane);
13740         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13741         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13742         int ret = 0;
13743
13744         if (!obj && !old_obj)
13745                 return 0;
13746
13747         if (old_obj) {
13748                 struct drm_crtc_state *crtc_state =
13749                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13750
13751                 /* Big Hammer, we also need to ensure that any pending
13752                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13753                  * current scanout is retired before unpinning the old
13754                  * framebuffer. Note that we rely on userspace rendering
13755                  * into the buffer attached to the pipe they are waiting
13756                  * on. If not, userspace generates a GPU hang with IPEHR
13757                  * point to the MI_WAIT_FOR_EVENT.
13758                  *
13759                  * This should only fail upon a hung GPU, in which case we
13760                  * can safely continue.
13761                  */
13762                 if (needs_modeset(crtc_state))
13763                         ret = i915_gem_object_wait_rendering(old_obj, true);
13764
13765                 /* Swallow -EIO errors to allow updates during hw lockup. */
13766                 if (ret && ret != -EIO)
13767                         return ret;
13768         }
13769
13770         /* For framebuffer backed by dmabuf, wait for fence */
13771         if (obj && obj->base.dma_buf) {
13772                 long lret;
13773
13774                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13775                                                            false, true,
13776                                                            MAX_SCHEDULE_TIMEOUT);
13777                 if (lret == -ERESTARTSYS)
13778                         return lret;
13779
13780                 WARN(lret < 0, "waiting returns %li\n", lret);
13781         }
13782
13783         if (!obj) {
13784                 ret = 0;
13785         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13786             INTEL_INFO(dev)->cursor_needs_physical) {
13787                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13788                 ret = i915_gem_object_attach_phys(obj, align);
13789                 if (ret)
13790                         DRM_DEBUG_KMS("failed to attach phys object\n");
13791         } else {
13792                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13793         }
13794
13795         if (ret == 0) {
13796                 if (obj) {
13797                         struct intel_plane_state *plane_state =
13798                                 to_intel_plane_state(new_state);
13799
13800                         i915_gem_request_assign(&plane_state->wait_req,
13801                                                 obj->last_write_req);
13802                 }
13803
13804                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13805         }
13806
13807         return ret;
13808 }
13809
13810 /**
13811  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13812  * @plane: drm plane to clean up for
13813  * @fb: old framebuffer that was on plane
13814  *
13815  * Cleans up a framebuffer that has just been removed from a plane.
13816  *
13817  * Must be called with struct_mutex held.
13818  */
13819 void
13820 intel_cleanup_plane_fb(struct drm_plane *plane,
13821                        const struct drm_plane_state *old_state)
13822 {
13823         struct drm_device *dev = plane->dev;
13824         struct intel_plane *intel_plane = to_intel_plane(plane);
13825         struct intel_plane_state *old_intel_state;
13826         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13827         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13828
13829         old_intel_state = to_intel_plane_state(old_state);
13830
13831         if (!obj && !old_obj)
13832                 return;
13833
13834         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13835             !INTEL_INFO(dev)->cursor_needs_physical))
13836                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13837
13838         /* prepare_fb aborted? */
13839         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13840             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13841                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13842
13843         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13844 }
13845
13846 int
13847 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13848 {
13849         int max_scale;
13850         struct drm_device *dev;
13851         struct drm_i915_private *dev_priv;
13852         int crtc_clock, cdclk;
13853
13854         if (!intel_crtc || !crtc_state->base.enable)
13855                 return DRM_PLANE_HELPER_NO_SCALING;
13856
13857         dev = intel_crtc->base.dev;
13858         dev_priv = dev->dev_private;
13859         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13860         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13861
13862         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13863                 return DRM_PLANE_HELPER_NO_SCALING;
13864
13865         /*
13866          * skl max scale is lower of:
13867          *    close to 3 but not 3, -1 is for that purpose
13868          *            or
13869          *    cdclk/crtc_clock
13870          */
13871         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13872
13873         return max_scale;
13874 }
13875
13876 static int
13877 intel_check_primary_plane(struct drm_plane *plane,
13878                           struct intel_crtc_state *crtc_state,
13879                           struct intel_plane_state *state)
13880 {
13881         struct drm_crtc *crtc = state->base.crtc;
13882         struct drm_framebuffer *fb = state->base.fb;
13883         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13884         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13885         bool can_position = false;
13886
13887         if (INTEL_INFO(plane->dev)->gen >= 9) {
13888                 /* use scaler when colorkey is not required */
13889                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13890                         min_scale = 1;
13891                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13892                 }
13893                 can_position = true;
13894         }
13895
13896         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13897                                              &state->dst, &state->clip,
13898                                              min_scale, max_scale,
13899                                              can_position, true,
13900                                              &state->visible);
13901 }
13902
13903 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13904                                     struct drm_crtc_state *old_crtc_state)
13905 {
13906         struct drm_device *dev = crtc->dev;
13907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13908         struct intel_crtc_state *old_intel_state =
13909                 to_intel_crtc_state(old_crtc_state);
13910         bool modeset = needs_modeset(crtc->state);
13911
13912         /* Perform vblank evasion around commit operation */
13913         intel_pipe_update_start(intel_crtc);
13914
13915         if (modeset)
13916                 return;
13917
13918         if (to_intel_crtc_state(crtc->state)->update_pipe)
13919                 intel_update_pipe_config(intel_crtc, old_intel_state);
13920         else if (INTEL_INFO(dev)->gen >= 9)
13921                 skl_detach_scalers(intel_crtc);
13922 }
13923
13924 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13925                                      struct drm_crtc_state *old_crtc_state)
13926 {
13927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13928
13929         intel_pipe_update_end(intel_crtc);
13930 }
13931
13932 /**
13933  * intel_plane_destroy - destroy a plane
13934  * @plane: plane to destroy
13935  *
13936  * Common destruction function for all types of planes (primary, cursor,
13937  * sprite).
13938  */
13939 void intel_plane_destroy(struct drm_plane *plane)
13940 {
13941         struct intel_plane *intel_plane = to_intel_plane(plane);
13942         drm_plane_cleanup(plane);
13943         kfree(intel_plane);
13944 }
13945
13946 const struct drm_plane_funcs intel_plane_funcs = {
13947         .update_plane = drm_atomic_helper_update_plane,
13948         .disable_plane = drm_atomic_helper_disable_plane,
13949         .destroy = intel_plane_destroy,
13950         .set_property = drm_atomic_helper_plane_set_property,
13951         .atomic_get_property = intel_plane_atomic_get_property,
13952         .atomic_set_property = intel_plane_atomic_set_property,
13953         .atomic_duplicate_state = intel_plane_duplicate_state,
13954         .atomic_destroy_state = intel_plane_destroy_state,
13955
13956 };
13957
13958 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13959                                                     int pipe)
13960 {
13961         struct intel_plane *primary;
13962         struct intel_plane_state *state;
13963         const uint32_t *intel_primary_formats;
13964         unsigned int num_formats;
13965
13966         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13967         if (primary == NULL)
13968                 return NULL;
13969
13970         state = intel_create_plane_state(&primary->base);
13971         if (!state) {
13972                 kfree(primary);
13973                 return NULL;
13974         }
13975         primary->base.state = &state->base;
13976
13977         primary->can_scale = false;
13978         primary->max_downscale = 1;
13979         if (INTEL_INFO(dev)->gen >= 9) {
13980                 primary->can_scale = true;
13981                 state->scaler_id = -1;
13982         }
13983         primary->pipe = pipe;
13984         primary->plane = pipe;
13985         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13986         primary->check_plane = intel_check_primary_plane;
13987         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13988                 primary->plane = !pipe;
13989
13990         if (INTEL_INFO(dev)->gen >= 9) {
13991                 intel_primary_formats = skl_primary_formats;
13992                 num_formats = ARRAY_SIZE(skl_primary_formats);
13993
13994                 primary->update_plane = skylake_update_primary_plane;
13995                 primary->disable_plane = skylake_disable_primary_plane;
13996         } else if (HAS_PCH_SPLIT(dev)) {
13997                 intel_primary_formats = i965_primary_formats;
13998                 num_formats = ARRAY_SIZE(i965_primary_formats);
13999
14000                 primary->update_plane = ironlake_update_primary_plane;
14001                 primary->disable_plane = i9xx_disable_primary_plane;
14002         } else if (INTEL_INFO(dev)->gen >= 4) {
14003                 intel_primary_formats = i965_primary_formats;
14004                 num_formats = ARRAY_SIZE(i965_primary_formats);
14005
14006                 primary->update_plane = i9xx_update_primary_plane;
14007                 primary->disable_plane = i9xx_disable_primary_plane;
14008         } else {
14009                 intel_primary_formats = i8xx_primary_formats;
14010                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14011
14012                 primary->update_plane = i9xx_update_primary_plane;
14013                 primary->disable_plane = i9xx_disable_primary_plane;
14014         }
14015
14016         drm_universal_plane_init(dev, &primary->base, 0,
14017                                  &intel_plane_funcs,
14018                                  intel_primary_formats, num_formats,
14019                                  DRM_PLANE_TYPE_PRIMARY, NULL);
14020
14021         if (INTEL_INFO(dev)->gen >= 4)
14022                 intel_create_rotation_property(dev, primary);
14023
14024         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14025
14026         return &primary->base;
14027 }
14028
14029 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14030 {
14031         if (!dev->mode_config.rotation_property) {
14032                 unsigned long flags = BIT(DRM_ROTATE_0) |
14033                         BIT(DRM_ROTATE_180);
14034
14035                 if (INTEL_INFO(dev)->gen >= 9)
14036                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14037
14038                 dev->mode_config.rotation_property =
14039                         drm_mode_create_rotation_property(dev, flags);
14040         }
14041         if (dev->mode_config.rotation_property)
14042                 drm_object_attach_property(&plane->base.base,
14043                                 dev->mode_config.rotation_property,
14044                                 plane->base.state->rotation);
14045 }
14046
14047 static int
14048 intel_check_cursor_plane(struct drm_plane *plane,
14049                          struct intel_crtc_state *crtc_state,
14050                          struct intel_plane_state *state)
14051 {
14052         struct drm_crtc *crtc = crtc_state->base.crtc;
14053         struct drm_framebuffer *fb = state->base.fb;
14054         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14055         enum pipe pipe = to_intel_plane(plane)->pipe;
14056         unsigned stride;
14057         int ret;
14058
14059         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14060                                             &state->dst, &state->clip,
14061                                             DRM_PLANE_HELPER_NO_SCALING,
14062                                             DRM_PLANE_HELPER_NO_SCALING,
14063                                             true, true, &state->visible);
14064         if (ret)
14065                 return ret;
14066
14067         /* if we want to turn off the cursor ignore width and height */
14068         if (!obj)
14069                 return 0;
14070
14071         /* Check for which cursor types we support */
14072         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14073                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14074                           state->base.crtc_w, state->base.crtc_h);
14075                 return -EINVAL;
14076         }
14077
14078         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14079         if (obj->base.size < stride * state->base.crtc_h) {
14080                 DRM_DEBUG_KMS("buffer is too small\n");
14081                 return -ENOMEM;
14082         }
14083
14084         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14085                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14086                 return -EINVAL;
14087         }
14088
14089         /*
14090          * There's something wrong with the cursor on CHV pipe C.
14091          * If it straddles the left edge of the screen then
14092          * moving it away from the edge or disabling it often
14093          * results in a pipe underrun, and often that can lead to
14094          * dead pipe (constant underrun reported, and it scans
14095          * out just a solid color). To recover from that, the
14096          * display power well must be turned off and on again.
14097          * Refuse the put the cursor into that compromised position.
14098          */
14099         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14100             state->visible && state->base.crtc_x < 0) {
14101                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14102                 return -EINVAL;
14103         }
14104
14105         return 0;
14106 }
14107
14108 static void
14109 intel_disable_cursor_plane(struct drm_plane *plane,
14110                            struct drm_crtc *crtc)
14111 {
14112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14113
14114         intel_crtc->cursor_addr = 0;
14115         intel_crtc_update_cursor(crtc, NULL);
14116 }
14117
14118 static void
14119 intel_update_cursor_plane(struct drm_plane *plane,
14120                           const struct intel_crtc_state *crtc_state,
14121                           const struct intel_plane_state *state)
14122 {
14123         struct drm_crtc *crtc = crtc_state->base.crtc;
14124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14125         struct drm_device *dev = plane->dev;
14126         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14127         uint32_t addr;
14128
14129         if (!obj)
14130                 addr = 0;
14131         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14132                 addr = i915_gem_obj_ggtt_offset(obj);
14133         else
14134                 addr = obj->phys_handle->busaddr;
14135
14136         intel_crtc->cursor_addr = addr;
14137         intel_crtc_update_cursor(crtc, state);
14138 }
14139
14140 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14141                                                    int pipe)
14142 {
14143         struct intel_plane *cursor;
14144         struct intel_plane_state *state;
14145
14146         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14147         if (cursor == NULL)
14148                 return NULL;
14149
14150         state = intel_create_plane_state(&cursor->base);
14151         if (!state) {
14152                 kfree(cursor);
14153                 return NULL;
14154         }
14155         cursor->base.state = &state->base;
14156
14157         cursor->can_scale = false;
14158         cursor->max_downscale = 1;
14159         cursor->pipe = pipe;
14160         cursor->plane = pipe;
14161         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14162         cursor->check_plane = intel_check_cursor_plane;
14163         cursor->update_plane = intel_update_cursor_plane;
14164         cursor->disable_plane = intel_disable_cursor_plane;
14165
14166         drm_universal_plane_init(dev, &cursor->base, 0,
14167                                  &intel_plane_funcs,
14168                                  intel_cursor_formats,
14169                                  ARRAY_SIZE(intel_cursor_formats),
14170                                  DRM_PLANE_TYPE_CURSOR, NULL);
14171
14172         if (INTEL_INFO(dev)->gen >= 4) {
14173                 if (!dev->mode_config.rotation_property)
14174                         dev->mode_config.rotation_property =
14175                                 drm_mode_create_rotation_property(dev,
14176                                                         BIT(DRM_ROTATE_0) |
14177                                                         BIT(DRM_ROTATE_180));
14178                 if (dev->mode_config.rotation_property)
14179                         drm_object_attach_property(&cursor->base.base,
14180                                 dev->mode_config.rotation_property,
14181                                 state->base.rotation);
14182         }
14183
14184         if (INTEL_INFO(dev)->gen >=9)
14185                 state->scaler_id = -1;
14186
14187         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14188
14189         return &cursor->base;
14190 }
14191
14192 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14193         struct intel_crtc_state *crtc_state)
14194 {
14195         int i;
14196         struct intel_scaler *intel_scaler;
14197         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14198
14199         for (i = 0; i < intel_crtc->num_scalers; i++) {
14200                 intel_scaler = &scaler_state->scalers[i];
14201                 intel_scaler->in_use = 0;
14202                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14203         }
14204
14205         scaler_state->scaler_id = -1;
14206 }
14207
14208 static void intel_crtc_init(struct drm_device *dev, int pipe)
14209 {
14210         struct drm_i915_private *dev_priv = dev->dev_private;
14211         struct intel_crtc *intel_crtc;
14212         struct intel_crtc_state *crtc_state = NULL;
14213         struct drm_plane *primary = NULL;
14214         struct drm_plane *cursor = NULL;
14215         int i, ret;
14216
14217         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14218         if (intel_crtc == NULL)
14219                 return;
14220
14221         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14222         if (!crtc_state)
14223                 goto fail;
14224         intel_crtc->config = crtc_state;
14225         intel_crtc->base.state = &crtc_state->base;
14226         crtc_state->base.crtc = &intel_crtc->base;
14227
14228         /* initialize shared scalers */
14229         if (INTEL_INFO(dev)->gen >= 9) {
14230                 if (pipe == PIPE_C)
14231                         intel_crtc->num_scalers = 1;
14232                 else
14233                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14234
14235                 skl_init_scalers(dev, intel_crtc, crtc_state);
14236         }
14237
14238         primary = intel_primary_plane_create(dev, pipe);
14239         if (!primary)
14240                 goto fail;
14241
14242         cursor = intel_cursor_plane_create(dev, pipe);
14243         if (!cursor)
14244                 goto fail;
14245
14246         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14247                                         cursor, &intel_crtc_funcs, NULL);
14248         if (ret)
14249                 goto fail;
14250
14251         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14252         for (i = 0; i < 256; i++) {
14253                 intel_crtc->lut_r[i] = i;
14254                 intel_crtc->lut_g[i] = i;
14255                 intel_crtc->lut_b[i] = i;
14256         }
14257
14258         /*
14259          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14260          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14261          */
14262         intel_crtc->pipe = pipe;
14263         intel_crtc->plane = pipe;
14264         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14265                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14266                 intel_crtc->plane = !pipe;
14267         }
14268
14269         intel_crtc->cursor_base = ~0;
14270         intel_crtc->cursor_cntl = ~0;
14271         intel_crtc->cursor_size = ~0;
14272
14273         intel_crtc->wm.cxsr_allowed = true;
14274
14275         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14276                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14277         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14278         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14279
14280         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14281
14282         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14283         return;
14284
14285 fail:
14286         if (primary)
14287                 drm_plane_cleanup(primary);
14288         if (cursor)
14289                 drm_plane_cleanup(cursor);
14290         kfree(crtc_state);
14291         kfree(intel_crtc);
14292 }
14293
14294 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14295 {
14296         struct drm_encoder *encoder = connector->base.encoder;
14297         struct drm_device *dev = connector->base.dev;
14298
14299         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14300
14301         if (!encoder || WARN_ON(!encoder->crtc))
14302                 return INVALID_PIPE;
14303
14304         return to_intel_crtc(encoder->crtc)->pipe;
14305 }
14306
14307 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14308                                 struct drm_file *file)
14309 {
14310         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14311         struct drm_crtc *drmmode_crtc;
14312         struct intel_crtc *crtc;
14313
14314         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14315
14316         if (!drmmode_crtc) {
14317                 DRM_ERROR("no such CRTC id\n");
14318                 return -ENOENT;
14319         }
14320
14321         crtc = to_intel_crtc(drmmode_crtc);
14322         pipe_from_crtc_id->pipe = crtc->pipe;
14323
14324         return 0;
14325 }
14326
14327 static int intel_encoder_clones(struct intel_encoder *encoder)
14328 {
14329         struct drm_device *dev = encoder->base.dev;
14330         struct intel_encoder *source_encoder;
14331         int index_mask = 0;
14332         int entry = 0;
14333
14334         for_each_intel_encoder(dev, source_encoder) {
14335                 if (encoders_cloneable(encoder, source_encoder))
14336                         index_mask |= (1 << entry);
14337
14338                 entry++;
14339         }
14340
14341         return index_mask;
14342 }
14343
14344 static bool has_edp_a(struct drm_device *dev)
14345 {
14346         struct drm_i915_private *dev_priv = dev->dev_private;
14347
14348         if (!IS_MOBILE(dev))
14349                 return false;
14350
14351         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14352                 return false;
14353
14354         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14355                 return false;
14356
14357         return true;
14358 }
14359
14360 static bool intel_crt_present(struct drm_device *dev)
14361 {
14362         struct drm_i915_private *dev_priv = dev->dev_private;
14363
14364         if (INTEL_INFO(dev)->gen >= 9)
14365                 return false;
14366
14367         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14368                 return false;
14369
14370         if (IS_CHERRYVIEW(dev))
14371                 return false;
14372
14373         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14374                 return false;
14375
14376         /* DDI E can't be used if DDI A requires 4 lanes */
14377         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14378                 return false;
14379
14380         if (!dev_priv->vbt.int_crt_support)
14381                 return false;
14382
14383         return true;
14384 }
14385
14386 static void intel_setup_outputs(struct drm_device *dev)
14387 {
14388         struct drm_i915_private *dev_priv = dev->dev_private;
14389         struct intel_encoder *encoder;
14390         bool dpd_is_edp = false;
14391
14392         intel_lvds_init(dev);
14393
14394         if (intel_crt_present(dev))
14395                 intel_crt_init(dev);
14396
14397         if (IS_BROXTON(dev)) {
14398                 /*
14399                  * FIXME: Broxton doesn't support port detection via the
14400                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14401                  * detect the ports.
14402                  */
14403                 intel_ddi_init(dev, PORT_A);
14404                 intel_ddi_init(dev, PORT_B);
14405                 intel_ddi_init(dev, PORT_C);
14406         } else if (HAS_DDI(dev)) {
14407                 int found;
14408
14409                 /*
14410                  * Haswell uses DDI functions to detect digital outputs.
14411                  * On SKL pre-D0 the strap isn't connected, so we assume
14412                  * it's there.
14413                  */
14414                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14415                 /* WaIgnoreDDIAStrap: skl */
14416                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14417                         intel_ddi_init(dev, PORT_A);
14418
14419                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14420                  * register */
14421                 found = I915_READ(SFUSE_STRAP);
14422
14423                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14424                         intel_ddi_init(dev, PORT_B);
14425                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14426                         intel_ddi_init(dev, PORT_C);
14427                 if (found & SFUSE_STRAP_DDID_DETECTED)
14428                         intel_ddi_init(dev, PORT_D);
14429                 /*
14430                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14431                  */
14432                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14433                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14434                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14435                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14436                         intel_ddi_init(dev, PORT_E);
14437
14438         } else if (HAS_PCH_SPLIT(dev)) {
14439                 int found;
14440                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14441
14442                 if (has_edp_a(dev))
14443                         intel_dp_init(dev, DP_A, PORT_A);
14444
14445                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14446                         /* PCH SDVOB multiplex with HDMIB */
14447                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14448                         if (!found)
14449                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14450                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14451                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14452                 }
14453
14454                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14455                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14456
14457                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14458                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14459
14460                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14461                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14462
14463                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14464                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14465         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14466                 /*
14467                  * The DP_DETECTED bit is the latched state of the DDC
14468                  * SDA pin at boot. However since eDP doesn't require DDC
14469                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14470                  * eDP ports may have been muxed to an alternate function.
14471                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14472                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14473                  * detect eDP ports.
14474                  */
14475                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14476                     !intel_dp_is_edp(dev, PORT_B))
14477                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14478                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14479                     intel_dp_is_edp(dev, PORT_B))
14480                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14481
14482                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14483                     !intel_dp_is_edp(dev, PORT_C))
14484                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14485                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14486                     intel_dp_is_edp(dev, PORT_C))
14487                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14488
14489                 if (IS_CHERRYVIEW(dev)) {
14490                         /* eDP not supported on port D, so don't check VBT */
14491                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14492                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14493                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14494                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14495                 }
14496
14497                 intel_dsi_init(dev);
14498         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14499                 bool found = false;
14500
14501                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14502                         DRM_DEBUG_KMS("probing SDVOB\n");
14503                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14504                         if (!found && IS_G4X(dev)) {
14505                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14506                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14507                         }
14508
14509                         if (!found && IS_G4X(dev))
14510                                 intel_dp_init(dev, DP_B, PORT_B);
14511                 }
14512
14513                 /* Before G4X SDVOC doesn't have its own detect register */
14514
14515                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14516                         DRM_DEBUG_KMS("probing SDVOC\n");
14517                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14518                 }
14519
14520                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14521
14522                         if (IS_G4X(dev)) {
14523                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14524                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14525                         }
14526                         if (IS_G4X(dev))
14527                                 intel_dp_init(dev, DP_C, PORT_C);
14528                 }
14529
14530                 if (IS_G4X(dev) &&
14531                     (I915_READ(DP_D) & DP_DETECTED))
14532                         intel_dp_init(dev, DP_D, PORT_D);
14533         } else if (IS_GEN2(dev))
14534                 intel_dvo_init(dev);
14535
14536         if (SUPPORTS_TV(dev))
14537                 intel_tv_init(dev);
14538
14539         intel_psr_init(dev);
14540
14541         for_each_intel_encoder(dev, encoder) {
14542                 encoder->base.possible_crtcs = encoder->crtc_mask;
14543                 encoder->base.possible_clones =
14544                         intel_encoder_clones(encoder);
14545         }
14546
14547         intel_init_pch_refclk(dev);
14548
14549         drm_helper_move_panel_connectors_to_head(dev);
14550 }
14551
14552 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14553 {
14554         struct drm_device *dev = fb->dev;
14555         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14556
14557         drm_framebuffer_cleanup(fb);
14558         mutex_lock(&dev->struct_mutex);
14559         WARN_ON(!intel_fb->obj->framebuffer_references--);
14560         drm_gem_object_unreference(&intel_fb->obj->base);
14561         mutex_unlock(&dev->struct_mutex);
14562         kfree(intel_fb);
14563 }
14564
14565 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14566                                                 struct drm_file *file,
14567                                                 unsigned int *handle)
14568 {
14569         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14570         struct drm_i915_gem_object *obj = intel_fb->obj;
14571
14572         if (obj->userptr.mm) {
14573                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14574                 return -EINVAL;
14575         }
14576
14577         return drm_gem_handle_create(file, &obj->base, handle);
14578 }
14579
14580 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14581                                         struct drm_file *file,
14582                                         unsigned flags, unsigned color,
14583                                         struct drm_clip_rect *clips,
14584                                         unsigned num_clips)
14585 {
14586         struct drm_device *dev = fb->dev;
14587         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14588         struct drm_i915_gem_object *obj = intel_fb->obj;
14589
14590         mutex_lock(&dev->struct_mutex);
14591         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14592         mutex_unlock(&dev->struct_mutex);
14593
14594         return 0;
14595 }
14596
14597 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14598         .destroy = intel_user_framebuffer_destroy,
14599         .create_handle = intel_user_framebuffer_create_handle,
14600         .dirty = intel_user_framebuffer_dirty,
14601 };
14602
14603 static
14604 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14605                          uint32_t pixel_format)
14606 {
14607         u32 gen = INTEL_INFO(dev)->gen;
14608
14609         if (gen >= 9) {
14610                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14611
14612                 /* "The stride in bytes must not exceed the of the size of 8K
14613                  *  pixels and 32K bytes."
14614                  */
14615                 return min(8192 * cpp, 32768);
14616         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14617                 return 32*1024;
14618         } else if (gen >= 4) {
14619                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14620                         return 16*1024;
14621                 else
14622                         return 32*1024;
14623         } else if (gen >= 3) {
14624                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14625                         return 8*1024;
14626                 else
14627                         return 16*1024;
14628         } else {
14629                 /* XXX DSPC is limited to 4k tiled */
14630                 return 8*1024;
14631         }
14632 }
14633
14634 static int intel_framebuffer_init(struct drm_device *dev,
14635                                   struct intel_framebuffer *intel_fb,
14636                                   struct drm_mode_fb_cmd2 *mode_cmd,
14637                                   struct drm_i915_gem_object *obj)
14638 {
14639         struct drm_i915_private *dev_priv = to_i915(dev);
14640         unsigned int aligned_height;
14641         int ret;
14642         u32 pitch_limit, stride_alignment;
14643
14644         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14645
14646         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14647                 /* Enforce that fb modifier and tiling mode match, but only for
14648                  * X-tiled. This is needed for FBC. */
14649                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14650                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14651                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14652                         return -EINVAL;
14653                 }
14654         } else {
14655                 if (obj->tiling_mode == I915_TILING_X)
14656                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14657                 else if (obj->tiling_mode == I915_TILING_Y) {
14658                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14659                         return -EINVAL;
14660                 }
14661         }
14662
14663         /* Passed in modifier sanity checking. */
14664         switch (mode_cmd->modifier[0]) {
14665         case I915_FORMAT_MOD_Y_TILED:
14666         case I915_FORMAT_MOD_Yf_TILED:
14667                 if (INTEL_INFO(dev)->gen < 9) {
14668                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14669                                   mode_cmd->modifier[0]);
14670                         return -EINVAL;
14671                 }
14672         case DRM_FORMAT_MOD_NONE:
14673         case I915_FORMAT_MOD_X_TILED:
14674                 break;
14675         default:
14676                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14677                           mode_cmd->modifier[0]);
14678                 return -EINVAL;
14679         }
14680
14681         stride_alignment = intel_fb_stride_alignment(dev_priv,
14682                                                      mode_cmd->modifier[0],
14683                                                      mode_cmd->pixel_format);
14684         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14685                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14686                           mode_cmd->pitches[0], stride_alignment);
14687                 return -EINVAL;
14688         }
14689
14690         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14691                                            mode_cmd->pixel_format);
14692         if (mode_cmd->pitches[0] > pitch_limit) {
14693                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14694                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14695                           "tiled" : "linear",
14696                           mode_cmd->pitches[0], pitch_limit);
14697                 return -EINVAL;
14698         }
14699
14700         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14701             mode_cmd->pitches[0] != obj->stride) {
14702                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14703                           mode_cmd->pitches[0], obj->stride);
14704                 return -EINVAL;
14705         }
14706
14707         /* Reject formats not supported by any plane early. */
14708         switch (mode_cmd->pixel_format) {
14709         case DRM_FORMAT_C8:
14710         case DRM_FORMAT_RGB565:
14711         case DRM_FORMAT_XRGB8888:
14712         case DRM_FORMAT_ARGB8888:
14713                 break;
14714         case DRM_FORMAT_XRGB1555:
14715                 if (INTEL_INFO(dev)->gen > 3) {
14716                         DRM_DEBUG("unsupported pixel format: %s\n",
14717                                   drm_get_format_name(mode_cmd->pixel_format));
14718                         return -EINVAL;
14719                 }
14720                 break;
14721         case DRM_FORMAT_ABGR8888:
14722                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14723                     INTEL_INFO(dev)->gen < 9) {
14724                         DRM_DEBUG("unsupported pixel format: %s\n",
14725                                   drm_get_format_name(mode_cmd->pixel_format));
14726                         return -EINVAL;
14727                 }
14728                 break;
14729         case DRM_FORMAT_XBGR8888:
14730         case DRM_FORMAT_XRGB2101010:
14731         case DRM_FORMAT_XBGR2101010:
14732                 if (INTEL_INFO(dev)->gen < 4) {
14733                         DRM_DEBUG("unsupported pixel format: %s\n",
14734                                   drm_get_format_name(mode_cmd->pixel_format));
14735                         return -EINVAL;
14736                 }
14737                 break;
14738         case DRM_FORMAT_ABGR2101010:
14739                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14740                         DRM_DEBUG("unsupported pixel format: %s\n",
14741                                   drm_get_format_name(mode_cmd->pixel_format));
14742                         return -EINVAL;
14743                 }
14744                 break;
14745         case DRM_FORMAT_YUYV:
14746         case DRM_FORMAT_UYVY:
14747         case DRM_FORMAT_YVYU:
14748         case DRM_FORMAT_VYUY:
14749                 if (INTEL_INFO(dev)->gen < 5) {
14750                         DRM_DEBUG("unsupported pixel format: %s\n",
14751                                   drm_get_format_name(mode_cmd->pixel_format));
14752                         return -EINVAL;
14753                 }
14754                 break;
14755         default:
14756                 DRM_DEBUG("unsupported pixel format: %s\n",
14757                           drm_get_format_name(mode_cmd->pixel_format));
14758                 return -EINVAL;
14759         }
14760
14761         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14762         if (mode_cmd->offsets[0] != 0)
14763                 return -EINVAL;
14764
14765         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14766                                                mode_cmd->pixel_format,
14767                                                mode_cmd->modifier[0]);
14768         /* FIXME drm helper for size checks (especially planar formats)? */
14769         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14770                 return -EINVAL;
14771
14772         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14773         intel_fb->obj = obj;
14774
14775         intel_fill_fb_info(dev_priv, &intel_fb->base);
14776
14777         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14778         if (ret) {
14779                 DRM_ERROR("framebuffer init failed %d\n", ret);
14780                 return ret;
14781         }
14782
14783         intel_fb->obj->framebuffer_references++;
14784
14785         return 0;
14786 }
14787
14788 static struct drm_framebuffer *
14789 intel_user_framebuffer_create(struct drm_device *dev,
14790                               struct drm_file *filp,
14791                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14792 {
14793         struct drm_framebuffer *fb;
14794         struct drm_i915_gem_object *obj;
14795         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14796
14797         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14798                                                 mode_cmd.handles[0]));
14799         if (&obj->base == NULL)
14800                 return ERR_PTR(-ENOENT);
14801
14802         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14803         if (IS_ERR(fb))
14804                 drm_gem_object_unreference_unlocked(&obj->base);
14805
14806         return fb;
14807 }
14808
14809 #ifndef CONFIG_DRM_FBDEV_EMULATION
14810 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14811 {
14812 }
14813 #endif
14814
14815 static const struct drm_mode_config_funcs intel_mode_funcs = {
14816         .fb_create = intel_user_framebuffer_create,
14817         .output_poll_changed = intel_fbdev_output_poll_changed,
14818         .atomic_check = intel_atomic_check,
14819         .atomic_commit = intel_atomic_commit,
14820         .atomic_state_alloc = intel_atomic_state_alloc,
14821         .atomic_state_clear = intel_atomic_state_clear,
14822 };
14823
14824 /* Set up chip specific display functions */
14825 static void intel_init_display(struct drm_device *dev)
14826 {
14827         struct drm_i915_private *dev_priv = dev->dev_private;
14828
14829         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14830                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14831         else if (IS_CHERRYVIEW(dev))
14832                 dev_priv->display.find_dpll = chv_find_best_dpll;
14833         else if (IS_VALLEYVIEW(dev))
14834                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14835         else if (IS_PINEVIEW(dev))
14836                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14837         else
14838                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14839
14840         if (INTEL_INFO(dev)->gen >= 9) {
14841                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14842                 dev_priv->display.get_initial_plane_config =
14843                         skylake_get_initial_plane_config;
14844                 dev_priv->display.crtc_compute_clock =
14845                         haswell_crtc_compute_clock;
14846                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14847                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14848         } else if (HAS_DDI(dev)) {
14849                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14850                 dev_priv->display.get_initial_plane_config =
14851                         ironlake_get_initial_plane_config;
14852                 dev_priv->display.crtc_compute_clock =
14853                         haswell_crtc_compute_clock;
14854                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14855                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14856         } else if (HAS_PCH_SPLIT(dev)) {
14857                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14858                 dev_priv->display.get_initial_plane_config =
14859                         ironlake_get_initial_plane_config;
14860                 dev_priv->display.crtc_compute_clock =
14861                         ironlake_crtc_compute_clock;
14862                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14863                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14864         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14865                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14866                 dev_priv->display.get_initial_plane_config =
14867                         i9xx_get_initial_plane_config;
14868                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14869                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14870                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14871         } else {
14872                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14873                 dev_priv->display.get_initial_plane_config =
14874                         i9xx_get_initial_plane_config;
14875                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14876                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14877                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14878         }
14879
14880         /* Returns the core display clock speed */
14881         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14882                 dev_priv->display.get_display_clock_speed =
14883                         skylake_get_display_clock_speed;
14884         else if (IS_BROXTON(dev))
14885                 dev_priv->display.get_display_clock_speed =
14886                         broxton_get_display_clock_speed;
14887         else if (IS_BROADWELL(dev))
14888                 dev_priv->display.get_display_clock_speed =
14889                         broadwell_get_display_clock_speed;
14890         else if (IS_HASWELL(dev))
14891                 dev_priv->display.get_display_clock_speed =
14892                         haswell_get_display_clock_speed;
14893         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14894                 dev_priv->display.get_display_clock_speed =
14895                         valleyview_get_display_clock_speed;
14896         else if (IS_GEN5(dev))
14897                 dev_priv->display.get_display_clock_speed =
14898                         ilk_get_display_clock_speed;
14899         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14900                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14901                 dev_priv->display.get_display_clock_speed =
14902                         i945_get_display_clock_speed;
14903         else if (IS_GM45(dev))
14904                 dev_priv->display.get_display_clock_speed =
14905                         gm45_get_display_clock_speed;
14906         else if (IS_CRESTLINE(dev))
14907                 dev_priv->display.get_display_clock_speed =
14908                         i965gm_get_display_clock_speed;
14909         else if (IS_PINEVIEW(dev))
14910                 dev_priv->display.get_display_clock_speed =
14911                         pnv_get_display_clock_speed;
14912         else if (IS_G33(dev) || IS_G4X(dev))
14913                 dev_priv->display.get_display_clock_speed =
14914                         g33_get_display_clock_speed;
14915         else if (IS_I915G(dev))
14916                 dev_priv->display.get_display_clock_speed =
14917                         i915_get_display_clock_speed;
14918         else if (IS_I945GM(dev) || IS_845G(dev))
14919                 dev_priv->display.get_display_clock_speed =
14920                         i9xx_misc_get_display_clock_speed;
14921         else if (IS_I915GM(dev))
14922                 dev_priv->display.get_display_clock_speed =
14923                         i915gm_get_display_clock_speed;
14924         else if (IS_I865G(dev))
14925                 dev_priv->display.get_display_clock_speed =
14926                         i865_get_display_clock_speed;
14927         else if (IS_I85X(dev))
14928                 dev_priv->display.get_display_clock_speed =
14929                         i85x_get_display_clock_speed;
14930         else { /* 830 */
14931                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14932                 dev_priv->display.get_display_clock_speed =
14933                         i830_get_display_clock_speed;
14934         }
14935
14936         if (IS_GEN5(dev)) {
14937                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14938         } else if (IS_GEN6(dev)) {
14939                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14940         } else if (IS_IVYBRIDGE(dev)) {
14941                 /* FIXME: detect B0+ stepping and use auto training */
14942                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14943         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14944                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14945                 if (IS_BROADWELL(dev)) {
14946                         dev_priv->display.modeset_commit_cdclk =
14947                                 broadwell_modeset_commit_cdclk;
14948                         dev_priv->display.modeset_calc_cdclk =
14949                                 broadwell_modeset_calc_cdclk;
14950                 }
14951         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14952                 dev_priv->display.modeset_commit_cdclk =
14953                         valleyview_modeset_commit_cdclk;
14954                 dev_priv->display.modeset_calc_cdclk =
14955                         valleyview_modeset_calc_cdclk;
14956         } else if (IS_BROXTON(dev)) {
14957                 dev_priv->display.modeset_commit_cdclk =
14958                         broxton_modeset_commit_cdclk;
14959                 dev_priv->display.modeset_calc_cdclk =
14960                         broxton_modeset_calc_cdclk;
14961         }
14962
14963         switch (INTEL_INFO(dev)->gen) {
14964         case 2:
14965                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14966                 break;
14967
14968         case 3:
14969                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14970                 break;
14971
14972         case 4:
14973         case 5:
14974                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14975                 break;
14976
14977         case 6:
14978                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14979                 break;
14980         case 7:
14981         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14982                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14983                 break;
14984         case 9:
14985                 /* Drop through - unsupported since execlist only. */
14986         default:
14987                 /* Default just returns -ENODEV to indicate unsupported */
14988                 dev_priv->display.queue_flip = intel_default_queue_flip;
14989         }
14990
14991         mutex_init(&dev_priv->pps_mutex);
14992 }
14993
14994 /*
14995  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14996  * resume, or other times.  This quirk makes sure that's the case for
14997  * affected systems.
14998  */
14999 static void quirk_pipea_force(struct drm_device *dev)
15000 {
15001         struct drm_i915_private *dev_priv = dev->dev_private;
15002
15003         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15004         DRM_INFO("applying pipe a force quirk\n");
15005 }
15006
15007 static void quirk_pipeb_force(struct drm_device *dev)
15008 {
15009         struct drm_i915_private *dev_priv = dev->dev_private;
15010
15011         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15012         DRM_INFO("applying pipe b force quirk\n");
15013 }
15014
15015 /*
15016  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15017  */
15018 static void quirk_ssc_force_disable(struct drm_device *dev)
15019 {
15020         struct drm_i915_private *dev_priv = dev->dev_private;
15021         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15022         DRM_INFO("applying lvds SSC disable quirk\n");
15023 }
15024
15025 /*
15026  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15027  * brightness value
15028  */
15029 static void quirk_invert_brightness(struct drm_device *dev)
15030 {
15031         struct drm_i915_private *dev_priv = dev->dev_private;
15032         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15033         DRM_INFO("applying inverted panel brightness quirk\n");
15034 }
15035
15036 /* Some VBT's incorrectly indicate no backlight is present */
15037 static void quirk_backlight_present(struct drm_device *dev)
15038 {
15039         struct drm_i915_private *dev_priv = dev->dev_private;
15040         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15041         DRM_INFO("applying backlight present quirk\n");
15042 }
15043
15044 struct intel_quirk {
15045         int device;
15046         int subsystem_vendor;
15047         int subsystem_device;
15048         void (*hook)(struct drm_device *dev);
15049 };
15050
15051 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15052 struct intel_dmi_quirk {
15053         void (*hook)(struct drm_device *dev);
15054         const struct dmi_system_id (*dmi_id_list)[];
15055 };
15056
15057 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15058 {
15059         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15060         return 1;
15061 }
15062
15063 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15064         {
15065                 .dmi_id_list = &(const struct dmi_system_id[]) {
15066                         {
15067                                 .callback = intel_dmi_reverse_brightness,
15068                                 .ident = "NCR Corporation",
15069                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15070                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15071                                 },
15072                         },
15073                         { }  /* terminating entry */
15074                 },
15075                 .hook = quirk_invert_brightness,
15076         },
15077 };
15078
15079 static struct intel_quirk intel_quirks[] = {
15080         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15081         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15082
15083         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15084         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15085
15086         /* 830 needs to leave pipe A & dpll A up */
15087         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15088
15089         /* 830 needs to leave pipe B & dpll B up */
15090         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15091
15092         /* Lenovo U160 cannot use SSC on LVDS */
15093         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15094
15095         /* Sony Vaio Y cannot use SSC on LVDS */
15096         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15097
15098         /* Acer Aspire 5734Z must invert backlight brightness */
15099         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15100
15101         /* Acer/eMachines G725 */
15102         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15103
15104         /* Acer/eMachines e725 */
15105         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15106
15107         /* Acer/Packard Bell NCL20 */
15108         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15109
15110         /* Acer Aspire 4736Z */
15111         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15112
15113         /* Acer Aspire 5336 */
15114         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15115
15116         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15117         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15118
15119         /* Acer C720 Chromebook (Core i3 4005U) */
15120         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15121
15122         /* Apple Macbook 2,1 (Core 2 T7400) */
15123         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15124
15125         /* Apple Macbook 4,1 */
15126         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15127
15128         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15129         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15130
15131         /* HP Chromebook 14 (Celeron 2955U) */
15132         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15133
15134         /* Dell Chromebook 11 */
15135         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15136
15137         /* Dell Chromebook 11 (2015 version) */
15138         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15139 };
15140
15141 static void intel_init_quirks(struct drm_device *dev)
15142 {
15143         struct pci_dev *d = dev->pdev;
15144         int i;
15145
15146         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15147                 struct intel_quirk *q = &intel_quirks[i];
15148
15149                 if (d->device == q->device &&
15150                     (d->subsystem_vendor == q->subsystem_vendor ||
15151                      q->subsystem_vendor == PCI_ANY_ID) &&
15152                     (d->subsystem_device == q->subsystem_device ||
15153                      q->subsystem_device == PCI_ANY_ID))
15154                         q->hook(dev);
15155         }
15156         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15157                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15158                         intel_dmi_quirks[i].hook(dev);
15159         }
15160 }
15161
15162 /* Disable the VGA plane that we never use */
15163 static void i915_disable_vga(struct drm_device *dev)
15164 {
15165         struct drm_i915_private *dev_priv = dev->dev_private;
15166         u8 sr1;
15167         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15168
15169         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15170         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15171         outb(SR01, VGA_SR_INDEX);
15172         sr1 = inb(VGA_SR_DATA);
15173         outb(sr1 | 1<<5, VGA_SR_DATA);
15174         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15175         udelay(300);
15176
15177         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15178         POSTING_READ(vga_reg);
15179 }
15180
15181 void intel_modeset_init_hw(struct drm_device *dev)
15182 {
15183         struct drm_i915_private *dev_priv = dev->dev_private;
15184
15185         intel_update_cdclk(dev);
15186
15187         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15188
15189         intel_init_clock_gating(dev);
15190         intel_enable_gt_powersave(dev);
15191 }
15192
15193 /*
15194  * Calculate what we think the watermarks should be for the state we've read
15195  * out of the hardware and then immediately program those watermarks so that
15196  * we ensure the hardware settings match our internal state.
15197  *
15198  * We can calculate what we think WM's should be by creating a duplicate of the
15199  * current state (which was constructed during hardware readout) and running it
15200  * through the atomic check code to calculate new watermark values in the
15201  * state object.
15202  */
15203 static void sanitize_watermarks(struct drm_device *dev)
15204 {
15205         struct drm_i915_private *dev_priv = to_i915(dev);
15206         struct drm_atomic_state *state;
15207         struct drm_crtc *crtc;
15208         struct drm_crtc_state *cstate;
15209         struct drm_modeset_acquire_ctx ctx;
15210         int ret;
15211         int i;
15212
15213         /* Only supported on platforms that use atomic watermark design */
15214         if (!dev_priv->display.optimize_watermarks)
15215                 return;
15216
15217         /*
15218          * We need to hold connection_mutex before calling duplicate_state so
15219          * that the connector loop is protected.
15220          */
15221         drm_modeset_acquire_init(&ctx, 0);
15222 retry:
15223         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15224         if (ret == -EDEADLK) {
15225                 drm_modeset_backoff(&ctx);
15226                 goto retry;
15227         } else if (WARN_ON(ret)) {
15228                 goto fail;
15229         }
15230
15231         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15232         if (WARN_ON(IS_ERR(state)))
15233                 goto fail;
15234
15235         /*
15236          * Hardware readout is the only time we don't want to calculate
15237          * intermediate watermarks (since we don't trust the current
15238          * watermarks).
15239          */
15240         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15241
15242         ret = intel_atomic_check(dev, state);
15243         if (ret) {
15244                 /*
15245                  * If we fail here, it means that the hardware appears to be
15246                  * programmed in a way that shouldn't be possible, given our
15247                  * understanding of watermark requirements.  This might mean a
15248                  * mistake in the hardware readout code or a mistake in the
15249                  * watermark calculations for a given platform.  Raise a WARN
15250                  * so that this is noticeable.
15251                  *
15252                  * If this actually happens, we'll have to just leave the
15253                  * BIOS-programmed watermarks untouched and hope for the best.
15254                  */
15255                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15256                 goto fail;
15257         }
15258
15259         /* Write calculated watermark values back */
15260         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15261         for_each_crtc_in_state(state, crtc, cstate, i) {
15262                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15263
15264                 cs->wm.need_postvbl_update = true;
15265                 dev_priv->display.optimize_watermarks(cs);
15266         }
15267
15268         drm_atomic_state_free(state);
15269 fail:
15270         drm_modeset_drop_locks(&ctx);
15271         drm_modeset_acquire_fini(&ctx);
15272 }
15273
15274 void intel_modeset_init(struct drm_device *dev)
15275 {
15276         struct drm_i915_private *dev_priv = dev->dev_private;
15277         int sprite, ret;
15278         enum pipe pipe;
15279         struct intel_crtc *crtc;
15280
15281         drm_mode_config_init(dev);
15282
15283         dev->mode_config.min_width = 0;
15284         dev->mode_config.min_height = 0;
15285
15286         dev->mode_config.preferred_depth = 24;
15287         dev->mode_config.prefer_shadow = 1;
15288
15289         dev->mode_config.allow_fb_modifiers = true;
15290
15291         dev->mode_config.funcs = &intel_mode_funcs;
15292
15293         intel_init_quirks(dev);
15294
15295         intel_init_pm(dev);
15296
15297         if (INTEL_INFO(dev)->num_pipes == 0)
15298                 return;
15299
15300         /*
15301          * There may be no VBT; and if the BIOS enabled SSC we can
15302          * just keep using it to avoid unnecessary flicker.  Whereas if the
15303          * BIOS isn't using it, don't assume it will work even if the VBT
15304          * indicates as much.
15305          */
15306         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15307                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15308                                             DREF_SSC1_ENABLE);
15309
15310                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15311                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15312                                      bios_lvds_use_ssc ? "en" : "dis",
15313                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15314                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15315                 }
15316         }
15317
15318         intel_init_display(dev);
15319         intel_init_audio(dev);
15320
15321         if (IS_GEN2(dev)) {
15322                 dev->mode_config.max_width = 2048;
15323                 dev->mode_config.max_height = 2048;
15324         } else if (IS_GEN3(dev)) {
15325                 dev->mode_config.max_width = 4096;
15326                 dev->mode_config.max_height = 4096;
15327         } else {
15328                 dev->mode_config.max_width = 8192;
15329                 dev->mode_config.max_height = 8192;
15330         }
15331
15332         if (IS_845G(dev) || IS_I865G(dev)) {
15333                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15334                 dev->mode_config.cursor_height = 1023;
15335         } else if (IS_GEN2(dev)) {
15336                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15337                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15338         } else {
15339                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15340                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15341         }
15342
15343         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15344
15345         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15346                       INTEL_INFO(dev)->num_pipes,
15347                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15348
15349         for_each_pipe(dev_priv, pipe) {
15350                 intel_crtc_init(dev, pipe);
15351                 for_each_sprite(dev_priv, pipe, sprite) {
15352                         ret = intel_plane_init(dev, pipe, sprite);
15353                         if (ret)
15354                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15355                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15356                 }
15357         }
15358
15359         intel_update_czclk(dev_priv);
15360         intel_update_rawclk(dev_priv);
15361         intel_update_cdclk(dev);
15362
15363         intel_shared_dpll_init(dev);
15364
15365         /* Just disable it once at startup */
15366         i915_disable_vga(dev);
15367         intel_setup_outputs(dev);
15368
15369         drm_modeset_lock_all(dev);
15370         intel_modeset_setup_hw_state(dev);
15371         drm_modeset_unlock_all(dev);
15372
15373         for_each_intel_crtc(dev, crtc) {
15374                 struct intel_initial_plane_config plane_config = {};
15375
15376                 if (!crtc->active)
15377                         continue;
15378
15379                 /*
15380                  * Note that reserving the BIOS fb up front prevents us
15381                  * from stuffing other stolen allocations like the ring
15382                  * on top.  This prevents some ugliness at boot time, and
15383                  * can even allow for smooth boot transitions if the BIOS
15384                  * fb is large enough for the active pipe configuration.
15385                  */
15386                 dev_priv->display.get_initial_plane_config(crtc,
15387                                                            &plane_config);
15388
15389                 /*
15390                  * If the fb is shared between multiple heads, we'll
15391                  * just get the first one.
15392                  */
15393                 intel_find_initial_plane_obj(crtc, &plane_config);
15394         }
15395
15396         /*
15397          * Make sure hardware watermarks really match the state we read out.
15398          * Note that we need to do this after reconstructing the BIOS fb's
15399          * since the watermark calculation done here will use pstate->fb.
15400          */
15401         sanitize_watermarks(dev);
15402 }
15403
15404 static void intel_enable_pipe_a(struct drm_device *dev)
15405 {
15406         struct intel_connector *connector;
15407         struct drm_connector *crt = NULL;
15408         struct intel_load_detect_pipe load_detect_temp;
15409         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15410
15411         /* We can't just switch on the pipe A, we need to set things up with a
15412          * proper mode and output configuration. As a gross hack, enable pipe A
15413          * by enabling the load detect pipe once. */
15414         for_each_intel_connector(dev, connector) {
15415                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15416                         crt = &connector->base;
15417                         break;
15418                 }
15419         }
15420
15421         if (!crt)
15422                 return;
15423
15424         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15425                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15426 }
15427
15428 static bool
15429 intel_check_plane_mapping(struct intel_crtc *crtc)
15430 {
15431         struct drm_device *dev = crtc->base.dev;
15432         struct drm_i915_private *dev_priv = dev->dev_private;
15433         u32 val;
15434
15435         if (INTEL_INFO(dev)->num_pipes == 1)
15436                 return true;
15437
15438         val = I915_READ(DSPCNTR(!crtc->plane));
15439
15440         if ((val & DISPLAY_PLANE_ENABLE) &&
15441             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15442                 return false;
15443
15444         return true;
15445 }
15446
15447 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15448 {
15449         struct drm_device *dev = crtc->base.dev;
15450         struct intel_encoder *encoder;
15451
15452         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15453                 return true;
15454
15455         return false;
15456 }
15457
15458 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15459 {
15460         struct drm_device *dev = encoder->base.dev;
15461         struct intel_connector *connector;
15462
15463         for_each_connector_on_encoder(dev, &encoder->base, connector)
15464                 return true;
15465
15466         return false;
15467 }
15468
15469 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15470 {
15471         struct drm_device *dev = crtc->base.dev;
15472         struct drm_i915_private *dev_priv = dev->dev_private;
15473         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15474
15475         /* Clear any frame start delays used for debugging left by the BIOS */
15476         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15477
15478         /* restore vblank interrupts to correct state */
15479         drm_crtc_vblank_reset(&crtc->base);
15480         if (crtc->active) {
15481                 struct intel_plane *plane;
15482
15483                 drm_crtc_vblank_on(&crtc->base);
15484
15485                 /* Disable everything but the primary plane */
15486                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15487                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15488                                 continue;
15489
15490                         plane->disable_plane(&plane->base, &crtc->base);
15491                 }
15492         }
15493
15494         /* We need to sanitize the plane -> pipe mapping first because this will
15495          * disable the crtc (and hence change the state) if it is wrong. Note
15496          * that gen4+ has a fixed plane -> pipe mapping.  */
15497         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15498                 bool plane;
15499
15500                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15501                               crtc->base.base.id);
15502
15503                 /* Pipe has the wrong plane attached and the plane is active.
15504                  * Temporarily change the plane mapping and disable everything
15505                  * ...  */
15506                 plane = crtc->plane;
15507                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15508                 crtc->plane = !plane;
15509                 intel_crtc_disable_noatomic(&crtc->base);
15510                 crtc->plane = plane;
15511         }
15512
15513         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15514             crtc->pipe == PIPE_A && !crtc->active) {
15515                 /* BIOS forgot to enable pipe A, this mostly happens after
15516                  * resume. Force-enable the pipe to fix this, the update_dpms
15517                  * call below we restore the pipe to the right state, but leave
15518                  * the required bits on. */
15519                 intel_enable_pipe_a(dev);
15520         }
15521
15522         /* Adjust the state of the output pipe according to whether we
15523          * have active connectors/encoders. */
15524         if (crtc->active && !intel_crtc_has_encoders(crtc))
15525                 intel_crtc_disable_noatomic(&crtc->base);
15526
15527         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15528                 /*
15529                  * We start out with underrun reporting disabled to avoid races.
15530                  * For correct bookkeeping mark this on active crtcs.
15531                  *
15532                  * Also on gmch platforms we dont have any hardware bits to
15533                  * disable the underrun reporting. Which means we need to start
15534                  * out with underrun reporting disabled also on inactive pipes,
15535                  * since otherwise we'll complain about the garbage we read when
15536                  * e.g. coming up after runtime pm.
15537                  *
15538                  * No protection against concurrent access is required - at
15539                  * worst a fifo underrun happens which also sets this to false.
15540                  */
15541                 crtc->cpu_fifo_underrun_disabled = true;
15542                 crtc->pch_fifo_underrun_disabled = true;
15543         }
15544 }
15545
15546 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15547 {
15548         struct intel_connector *connector;
15549         struct drm_device *dev = encoder->base.dev;
15550
15551         /* We need to check both for a crtc link (meaning that the
15552          * encoder is active and trying to read from a pipe) and the
15553          * pipe itself being active. */
15554         bool has_active_crtc = encoder->base.crtc &&
15555                 to_intel_crtc(encoder->base.crtc)->active;
15556
15557         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15558                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15559                               encoder->base.base.id,
15560                               encoder->base.name);
15561
15562                 /* Connector is active, but has no active pipe. This is
15563                  * fallout from our resume register restoring. Disable
15564                  * the encoder manually again. */
15565                 if (encoder->base.crtc) {
15566                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15567                                       encoder->base.base.id,
15568                                       encoder->base.name);
15569                         encoder->disable(encoder);
15570                         if (encoder->post_disable)
15571                                 encoder->post_disable(encoder);
15572                 }
15573                 encoder->base.crtc = NULL;
15574
15575                 /* Inconsistent output/port/pipe state happens presumably due to
15576                  * a bug in one of the get_hw_state functions. Or someplace else
15577                  * in our code, like the register restore mess on resume. Clamp
15578                  * things to off as a safer default. */
15579                 for_each_intel_connector(dev, connector) {
15580                         if (connector->encoder != encoder)
15581                                 continue;
15582                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15583                         connector->base.encoder = NULL;
15584                 }
15585         }
15586         /* Enabled encoders without active connectors will be fixed in
15587          * the crtc fixup. */
15588 }
15589
15590 void i915_redisable_vga_power_on(struct drm_device *dev)
15591 {
15592         struct drm_i915_private *dev_priv = dev->dev_private;
15593         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15594
15595         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15596                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15597                 i915_disable_vga(dev);
15598         }
15599 }
15600
15601 void i915_redisable_vga(struct drm_device *dev)
15602 {
15603         struct drm_i915_private *dev_priv = dev->dev_private;
15604
15605         /* This function can be called both from intel_modeset_setup_hw_state or
15606          * at a very early point in our resume sequence, where the power well
15607          * structures are not yet restored. Since this function is at a very
15608          * paranoid "someone might have enabled VGA while we were not looking"
15609          * level, just check if the power well is enabled instead of trying to
15610          * follow the "don't touch the power well if we don't need it" policy
15611          * the rest of the driver uses. */
15612         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15613                 return;
15614
15615         i915_redisable_vga_power_on(dev);
15616
15617         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15618 }
15619
15620 static bool primary_get_hw_state(struct intel_plane *plane)
15621 {
15622         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15623
15624         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15625 }
15626
15627 /* FIXME read out full plane state for all planes */
15628 static void readout_plane_state(struct intel_crtc *crtc)
15629 {
15630         struct drm_plane *primary = crtc->base.primary;
15631         struct intel_plane_state *plane_state =
15632                 to_intel_plane_state(primary->state);
15633
15634         plane_state->visible = crtc->active &&
15635                 primary_get_hw_state(to_intel_plane(primary));
15636
15637         if (plane_state->visible)
15638                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15639 }
15640
15641 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15642 {
15643         struct drm_i915_private *dev_priv = dev->dev_private;
15644         enum pipe pipe;
15645         struct intel_crtc *crtc;
15646         struct intel_encoder *encoder;
15647         struct intel_connector *connector;
15648         int i;
15649
15650         dev_priv->active_crtcs = 0;
15651
15652         for_each_intel_crtc(dev, crtc) {
15653                 struct intel_crtc_state *crtc_state = crtc->config;
15654                 int pixclk = 0;
15655
15656                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15657                 memset(crtc_state, 0, sizeof(*crtc_state));
15658                 crtc_state->base.crtc = &crtc->base;
15659
15660                 crtc_state->base.active = crtc_state->base.enable =
15661                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15662
15663                 crtc->base.enabled = crtc_state->base.enable;
15664                 crtc->active = crtc_state->base.active;
15665
15666                 if (crtc_state->base.active) {
15667                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15668
15669                         if (IS_BROADWELL(dev_priv)) {
15670                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15671
15672                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15673                                 if (crtc_state->ips_enabled)
15674                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15675                         } else if (IS_VALLEYVIEW(dev_priv) ||
15676                                    IS_CHERRYVIEW(dev_priv) ||
15677                                    IS_BROXTON(dev_priv))
15678                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15679                         else
15680                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15681                 }
15682
15683                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15684
15685                 readout_plane_state(crtc);
15686
15687                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15688                               crtc->base.base.id,
15689                               crtc->active ? "enabled" : "disabled");
15690         }
15691
15692         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15693                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15694
15695                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15696                                                   &pll->config.hw_state);
15697                 pll->config.crtc_mask = 0;
15698                 for_each_intel_crtc(dev, crtc) {
15699                         if (crtc->active && crtc->config->shared_dpll == pll)
15700                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15701                 }
15702                 pll->active_mask = pll->config.crtc_mask;
15703
15704                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15705                               pll->name, pll->config.crtc_mask, pll->on);
15706
15707                 if (pll->config.crtc_mask)
15708                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15709         }
15710
15711         for_each_intel_encoder(dev, encoder) {
15712                 pipe = 0;
15713
15714                 if (encoder->get_hw_state(encoder, &pipe)) {
15715                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15716                         encoder->base.crtc = &crtc->base;
15717                         encoder->get_config(encoder, crtc->config);
15718                 } else {
15719                         encoder->base.crtc = NULL;
15720                 }
15721
15722                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15723                               encoder->base.base.id,
15724                               encoder->base.name,
15725                               encoder->base.crtc ? "enabled" : "disabled",
15726                               pipe_name(pipe));
15727         }
15728
15729         for_each_intel_connector(dev, connector) {
15730                 if (connector->get_hw_state(connector)) {
15731                         connector->base.dpms = DRM_MODE_DPMS_ON;
15732
15733                         encoder = connector->encoder;
15734                         connector->base.encoder = &encoder->base;
15735
15736                         if (encoder->base.crtc &&
15737                             encoder->base.crtc->state->active) {
15738                                 /*
15739                                  * This has to be done during hardware readout
15740                                  * because anything calling .crtc_disable may
15741                                  * rely on the connector_mask being accurate.
15742                                  */
15743                                 encoder->base.crtc->state->connector_mask |=
15744                                         1 << drm_connector_index(&connector->base);
15745                                 encoder->base.crtc->state->encoder_mask |=
15746                                         1 << drm_encoder_index(&encoder->base);
15747                         }
15748
15749                 } else {
15750                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15751                         connector->base.encoder = NULL;
15752                 }
15753                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15754                               connector->base.base.id,
15755                               connector->base.name,
15756                               connector->base.encoder ? "enabled" : "disabled");
15757         }
15758
15759         for_each_intel_crtc(dev, crtc) {
15760                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15761
15762                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15763                 if (crtc->base.state->active) {
15764                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15765                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15766                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15767
15768                         /*
15769                          * The initial mode needs to be set in order to keep
15770                          * the atomic core happy. It wants a valid mode if the
15771                          * crtc's enabled, so we do the above call.
15772                          *
15773                          * At this point some state updated by the connectors
15774                          * in their ->detect() callback has not run yet, so
15775                          * no recalculation can be done yet.
15776                          *
15777                          * Even if we could do a recalculation and modeset
15778                          * right now it would cause a double modeset if
15779                          * fbdev or userspace chooses a different initial mode.
15780                          *
15781                          * If that happens, someone indicated they wanted a
15782                          * mode change, which means it's safe to do a full
15783                          * recalculation.
15784                          */
15785                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15786
15787                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15788                         update_scanline_offset(crtc);
15789                 }
15790
15791                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15792         }
15793 }
15794
15795 /* Scan out the current hw modeset state,
15796  * and sanitizes it to the current state
15797  */
15798 static void
15799 intel_modeset_setup_hw_state(struct drm_device *dev)
15800 {
15801         struct drm_i915_private *dev_priv = dev->dev_private;
15802         enum pipe pipe;
15803         struct intel_crtc *crtc;
15804         struct intel_encoder *encoder;
15805         int i;
15806
15807         intel_modeset_readout_hw_state(dev);
15808
15809         /* HW state is read out, now we need to sanitize this mess. */
15810         for_each_intel_encoder(dev, encoder) {
15811                 intel_sanitize_encoder(encoder);
15812         }
15813
15814         for_each_pipe(dev_priv, pipe) {
15815                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15816                 intel_sanitize_crtc(crtc);
15817                 intel_dump_pipe_config(crtc, crtc->config,
15818                                        "[setup_hw_state]");
15819         }
15820
15821         intel_modeset_update_connector_atomic_state(dev);
15822
15823         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15824                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15825
15826                 if (!pll->on || pll->active_mask)
15827                         continue;
15828
15829                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15830
15831                 pll->funcs.disable(dev_priv, pll);
15832                 pll->on = false;
15833         }
15834
15835         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15836                 vlv_wm_get_hw_state(dev);
15837         else if (IS_GEN9(dev))
15838                 skl_wm_get_hw_state(dev);
15839         else if (HAS_PCH_SPLIT(dev))
15840                 ilk_wm_get_hw_state(dev);
15841
15842         for_each_intel_crtc(dev, crtc) {
15843                 unsigned long put_domains;
15844
15845                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15846                 if (WARN_ON(put_domains))
15847                         modeset_put_power_domains(dev_priv, put_domains);
15848         }
15849         intel_display_set_init_power(dev_priv, false);
15850
15851         intel_fbc_init_pipe_state(dev_priv);
15852 }
15853
15854 void intel_display_resume(struct drm_device *dev)
15855 {
15856         struct drm_i915_private *dev_priv = to_i915(dev);
15857         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15858         struct drm_modeset_acquire_ctx ctx;
15859         int ret;
15860         bool setup = false;
15861
15862         dev_priv->modeset_restore_state = NULL;
15863
15864         /*
15865          * This is a cludge because with real atomic modeset mode_config.mutex
15866          * won't be taken. Unfortunately some probed state like
15867          * audio_codec_enable is still protected by mode_config.mutex, so lock
15868          * it here for now.
15869          */
15870         mutex_lock(&dev->mode_config.mutex);
15871         drm_modeset_acquire_init(&ctx, 0);
15872
15873 retry:
15874         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15875
15876         if (ret == 0 && !setup) {
15877                 setup = true;
15878
15879                 intel_modeset_setup_hw_state(dev);
15880                 i915_redisable_vga(dev);
15881         }
15882
15883         if (ret == 0 && state) {
15884                 struct drm_crtc_state *crtc_state;
15885                 struct drm_crtc *crtc;
15886                 int i;
15887
15888                 state->acquire_ctx = &ctx;
15889
15890                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15891                         /*
15892                          * Force recalculation even if we restore
15893                          * current state. With fast modeset this may not result
15894                          * in a modeset when the state is compatible.
15895                          */
15896                         crtc_state->mode_changed = true;
15897                 }
15898
15899                 ret = drm_atomic_commit(state);
15900         }
15901
15902         if (ret == -EDEADLK) {
15903                 drm_modeset_backoff(&ctx);
15904                 goto retry;
15905         }
15906
15907         drm_modeset_drop_locks(&ctx);
15908         drm_modeset_acquire_fini(&ctx);
15909         mutex_unlock(&dev->mode_config.mutex);
15910
15911         if (ret) {
15912                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15913                 drm_atomic_state_free(state);
15914         }
15915 }
15916
15917 void intel_modeset_gem_init(struct drm_device *dev)
15918 {
15919         struct drm_crtc *c;
15920         struct drm_i915_gem_object *obj;
15921         int ret;
15922
15923         intel_init_gt_powersave(dev);
15924
15925         intel_modeset_init_hw(dev);
15926
15927         intel_setup_overlay(dev);
15928
15929         /*
15930          * Make sure any fbs we allocated at startup are properly
15931          * pinned & fenced.  When we do the allocation it's too early
15932          * for this.
15933          */
15934         for_each_crtc(dev, c) {
15935                 obj = intel_fb_obj(c->primary->fb);
15936                 if (obj == NULL)
15937                         continue;
15938
15939                 mutex_lock(&dev->struct_mutex);
15940                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15941                                                  c->primary->state->rotation);
15942                 mutex_unlock(&dev->struct_mutex);
15943                 if (ret) {
15944                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15945                                   to_intel_crtc(c)->pipe);
15946                         drm_framebuffer_unreference(c->primary->fb);
15947                         c->primary->fb = NULL;
15948                         c->primary->crtc = c->primary->state->crtc = NULL;
15949                         update_state_fb(c->primary);
15950                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15951                 }
15952         }
15953
15954         intel_backlight_register(dev);
15955 }
15956
15957 void intel_connector_unregister(struct intel_connector *intel_connector)
15958 {
15959         struct drm_connector *connector = &intel_connector->base;
15960
15961         intel_panel_destroy_backlight(connector);
15962         drm_connector_unregister(connector);
15963 }
15964
15965 void intel_modeset_cleanup(struct drm_device *dev)
15966 {
15967         struct drm_i915_private *dev_priv = dev->dev_private;
15968         struct intel_connector *connector;
15969
15970         intel_disable_gt_powersave(dev);
15971
15972         intel_backlight_unregister(dev);
15973
15974         /*
15975          * Interrupts and polling as the first thing to avoid creating havoc.
15976          * Too much stuff here (turning of connectors, ...) would
15977          * experience fancy races otherwise.
15978          */
15979         intel_irq_uninstall(dev_priv);
15980
15981         /*
15982          * Due to the hpd irq storm handling the hotplug work can re-arm the
15983          * poll handlers. Hence disable polling after hpd handling is shut down.
15984          */
15985         drm_kms_helper_poll_fini(dev);
15986
15987         intel_unregister_dsm_handler();
15988
15989         intel_fbc_global_disable(dev_priv);
15990
15991         /* flush any delayed tasks or pending work */
15992         flush_scheduled_work();
15993
15994         /* destroy the backlight and sysfs files before encoders/connectors */
15995         for_each_intel_connector(dev, connector)
15996                 connector->unregister(connector);
15997
15998         drm_mode_config_cleanup(dev);
15999
16000         intel_cleanup_overlay(dev);
16001
16002         intel_cleanup_gt_powersave(dev);
16003
16004         intel_teardown_gmbus(dev);
16005 }
16006
16007 /*
16008  * Return which encoder is currently attached for connector.
16009  */
16010 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16011 {
16012         return &intel_attached_encoder(connector)->base;
16013 }
16014
16015 void intel_connector_attach_encoder(struct intel_connector *connector,
16016                                     struct intel_encoder *encoder)
16017 {
16018         connector->encoder = encoder;
16019         drm_mode_connector_attach_encoder(&connector->base,
16020                                           &encoder->base);
16021 }
16022
16023 /*
16024  * set vga decode state - true == enable VGA decode
16025  */
16026 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16027 {
16028         struct drm_i915_private *dev_priv = dev->dev_private;
16029         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16030         u16 gmch_ctrl;
16031
16032         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16033                 DRM_ERROR("failed to read control word\n");
16034                 return -EIO;
16035         }
16036
16037         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16038                 return 0;
16039
16040         if (state)
16041                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16042         else
16043                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16044
16045         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16046                 DRM_ERROR("failed to write control word\n");
16047                 return -EIO;
16048         }
16049
16050         return 0;
16051 }
16052
16053 struct intel_display_error_state {
16054
16055         u32 power_well_driver;
16056
16057         int num_transcoders;
16058
16059         struct intel_cursor_error_state {
16060                 u32 control;
16061                 u32 position;
16062                 u32 base;
16063                 u32 size;
16064         } cursor[I915_MAX_PIPES];
16065
16066         struct intel_pipe_error_state {
16067                 bool power_domain_on;
16068                 u32 source;
16069                 u32 stat;
16070         } pipe[I915_MAX_PIPES];
16071
16072         struct intel_plane_error_state {
16073                 u32 control;
16074                 u32 stride;
16075                 u32 size;
16076                 u32 pos;
16077                 u32 addr;
16078                 u32 surface;
16079                 u32 tile_offset;
16080         } plane[I915_MAX_PIPES];
16081
16082         struct intel_transcoder_error_state {
16083                 bool power_domain_on;
16084                 enum transcoder cpu_transcoder;
16085
16086                 u32 conf;
16087
16088                 u32 htotal;
16089                 u32 hblank;
16090                 u32 hsync;
16091                 u32 vtotal;
16092                 u32 vblank;
16093                 u32 vsync;
16094         } transcoder[4];
16095 };
16096
16097 struct intel_display_error_state *
16098 intel_display_capture_error_state(struct drm_device *dev)
16099 {
16100         struct drm_i915_private *dev_priv = dev->dev_private;
16101         struct intel_display_error_state *error;
16102         int transcoders[] = {
16103                 TRANSCODER_A,
16104                 TRANSCODER_B,
16105                 TRANSCODER_C,
16106                 TRANSCODER_EDP,
16107         };
16108         int i;
16109
16110         if (INTEL_INFO(dev)->num_pipes == 0)
16111                 return NULL;
16112
16113         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16114         if (error == NULL)
16115                 return NULL;
16116
16117         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16118                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16119
16120         for_each_pipe(dev_priv, i) {
16121                 error->pipe[i].power_domain_on =
16122                         __intel_display_power_is_enabled(dev_priv,
16123                                                          POWER_DOMAIN_PIPE(i));
16124                 if (!error->pipe[i].power_domain_on)
16125                         continue;
16126
16127                 error->cursor[i].control = I915_READ(CURCNTR(i));
16128                 error->cursor[i].position = I915_READ(CURPOS(i));
16129                 error->cursor[i].base = I915_READ(CURBASE(i));
16130
16131                 error->plane[i].control = I915_READ(DSPCNTR(i));
16132                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16133                 if (INTEL_INFO(dev)->gen <= 3) {
16134                         error->plane[i].size = I915_READ(DSPSIZE(i));
16135                         error->plane[i].pos = I915_READ(DSPPOS(i));
16136                 }
16137                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16138                         error->plane[i].addr = I915_READ(DSPADDR(i));
16139                 if (INTEL_INFO(dev)->gen >= 4) {
16140                         error->plane[i].surface = I915_READ(DSPSURF(i));
16141                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16142                 }
16143
16144                 error->pipe[i].source = I915_READ(PIPESRC(i));
16145
16146                 if (HAS_GMCH_DISPLAY(dev))
16147                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16148         }
16149
16150         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16151         if (HAS_DDI(dev_priv->dev))
16152                 error->num_transcoders++; /* Account for eDP. */
16153
16154         for (i = 0; i < error->num_transcoders; i++) {
16155                 enum transcoder cpu_transcoder = transcoders[i];
16156
16157                 error->transcoder[i].power_domain_on =
16158                         __intel_display_power_is_enabled(dev_priv,
16159                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16160                 if (!error->transcoder[i].power_domain_on)
16161                         continue;
16162
16163                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16164
16165                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16166                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16167                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16168                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16169                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16170                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16171                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16172         }
16173
16174         return error;
16175 }
16176
16177 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16178
16179 void
16180 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16181                                 struct drm_device *dev,
16182                                 struct intel_display_error_state *error)
16183 {
16184         struct drm_i915_private *dev_priv = dev->dev_private;
16185         int i;
16186
16187         if (!error)
16188                 return;
16189
16190         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16191         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16192                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16193                            error->power_well_driver);
16194         for_each_pipe(dev_priv, i) {
16195                 err_printf(m, "Pipe [%d]:\n", i);
16196                 err_printf(m, "  Power: %s\n",
16197                            onoff(error->pipe[i].power_domain_on));
16198                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16199                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16200
16201                 err_printf(m, "Plane [%d]:\n", i);
16202                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16203                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16204                 if (INTEL_INFO(dev)->gen <= 3) {
16205                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16206                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16207                 }
16208                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16209                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16210                 if (INTEL_INFO(dev)->gen >= 4) {
16211                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16212                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16213                 }
16214
16215                 err_printf(m, "Cursor [%d]:\n", i);
16216                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16217                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16218                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16219         }
16220
16221         for (i = 0; i < error->num_transcoders; i++) {
16222                 err_printf(m, "CPU transcoder: %s\n",
16223                            transcoder_name(error->transcoder[i].cpu_transcoder));
16224                 err_printf(m, "  Power: %s\n",
16225                            onoff(error->transcoder[i].power_domain_on));
16226                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16227                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16228                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16229                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16230                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16231                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16232                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16233         }
16234 }