drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_device *dev,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 623                         INTELPllInvalid("p out of range\n");
 624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 625                         INTELPllInvalid("m out of range\n");
 626         }
 627
 628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 629                 INTELPllInvalid("vco out of range\n");
 630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 631          * connector, etc., rather than just a single range.
 632          */
 633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 634                 INTELPllInvalid("dot out of range\n");
 635
 636         return true;
 637 }
 638
 639 static int
 640 i9xx_select_p2_div(const struct intel_limit *limit,
 641                    const struct intel_crtc_state *crtc_state,
 642                    int target)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645
 646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 647                 /*
 648                  * For LVDS just rely on its current settings for dual-channel.
 649                  * We haven't figured out how to reliably set up different
 650                  * single/dual channel state, if we even can.
 651                  */
 652                 if (intel_is_dual_link_lvds(dev))
 653                         return limit->p2.p2_fast;
 654                 else
 655                         return limit->p2.p2_slow;
 656         } else {
 657                 if (target < limit->p2.dot_limit)
 658                         return limit->p2.p2_slow;
 659                 else
 660                         return limit->p2.p2_fast;
 661         }
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 i9xx_find_best_dpll(const struct intel_limit *limit,
 676                     struct intel_crtc_state *crtc_state,
 677                     int target, int refclk, struct dpll *match_clock,
 678                     struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         if (clock.m2 >= clock.m1)
 693                                 break;
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         i9xx_calc_dpll_params(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 /*
 722  * Returns a set of divisors for the desired target clock with the given
 723  * refclk, or FALSE.  The returned values represent the clock equation:
 724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 725  *
 726  * Target and reference clocks are specified in kHz.
 727  *
 728  * If match_clock is provided, then best_clock P divider must match the P
 729  * divider from @match_clock used for LVDS downclocking.
 730  */
 731 static bool
 732 pnv_find_best_dpll(const struct intel_limit *limit,
 733                    struct intel_crtc_state *crtc_state,
 734                    int target, int refclk, struct dpll *match_clock,
 735                    struct dpll *best_clock)
 736 {
 737         struct drm_device *dev = crtc_state->base.crtc->dev;
 738         struct dpll clock;
 739         int err = target;
 740
 741         memset(best_clock, 0, sizeof(*best_clock));
 742
 743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 744
 745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 746              clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      clock.m2 <= limit->m2.max; clock.m2++) {
 749                         for (clock.n = limit->n.min;
 750                              clock.n <= limit->n.max; clock.n++) {
 751                                 for (clock.p1 = limit->p1.min;
 752                                         clock.p1 <= limit->p1.max; clock.p1++) {
 753                                         int this_err;
 754
 755                                         pnv_calc_dpll_params(refclk, &clock);
 756                                         if (!intel_PLL_is_valid(dev, limit,
 757                                                                 &clock))
 758                                                 continue;
 759                                         if (match_clock &&
 760                                             clock.p != match_clock->p)
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return (err != target);
 774 }
 775
 776 /*
 777  * Returns a set of divisors for the desired target clock with the given
 778  * refclk, or FALSE.  The returned values represent the clock equation:
 779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 780  *
 781  * Target and reference clocks are specified in kHz.
 782  *
 783  * If match_clock is provided, then best_clock P divider must match the P
 784  * divider from @match_clock used for LVDS downclocking.
 785  */
 786 static bool
 787 g4x_find_best_dpll(const struct intel_limit *limit,
 788                    struct intel_crtc_state *crtc_state,
 789                    int target, int refclk, struct dpll *match_clock,
 790                    struct dpll *best_clock)
 791 {
 792         struct drm_device *dev = crtc_state->base.crtc->dev;
 793         struct dpll clock;
 794         int max_n;
 795         bool found = false;
 796         /* approximately equals target * 0.00585 */
 797         int err_most = (target >> 8) + (target >> 9);
 798
 799         memset(best_clock, 0, sizeof(*best_clock));
 800
 801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 802
 803         max_n = limit->n.max;
 804         /* based on hardware requirement, prefer smaller n to precision */
 805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 806                 /* based on hardware requirement, prefere larger m1,m2 */
 807                 for (clock.m1 = limit->m1.max;
 808                      clock.m1 >= limit->m1.min; clock.m1--) {
 809                         for (clock.m2 = limit->m2.max;
 810                              clock.m2 >= limit->m2.min; clock.m2--) {
 811                                 for (clock.p1 = limit->p1.max;
 812                                      clock.p1 >= limit->p1.min; clock.p1--) {
 813                                         int this_err;
 814
 815                                         i9xx_calc_dpll_params(refclk, &clock);
 816                                         if (!intel_PLL_is_valid(dev, limit,
 817                                                                 &clock))
 818                                                 continue;
 819
 820                                         this_err = abs(clock.dot - target);
 821                                         if (this_err < err_most) {
 822                                                 *best_clock = clock;
 823                                                 err_most = this_err;
 824                                                 max_n = clock.n;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831         return found;
 832 }
 833
 834 /*
 835  * Check if the calculated PLL configuration is more optimal compared to the
 836  * best configuration and error found so far. Return the calculated error.
 837  */
 838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 839                                const struct dpll *calculated_clock,
 840                                const struct dpll *best_clock,
 841                                unsigned int best_error_ppm,
 842                                unsigned int *error_ppm)
 843 {
 844         /*
 845          * For CHV ignore the error and consider only the P value.
 846          * Prefer a bigger P value based on HW requirements.
 847          */
 848         if (IS_CHERRYVIEW(dev)) {
 849                 *error_ppm = 0;
 850
 851                 return calculated_clock->p > best_clock->p;
 852         }
 853
 854         if (WARN_ON_ONCE(!target_freq))
 855                 return false;
 856
 857         *error_ppm = div_u64(1000000ULL *
 858                                 abs(target_freq - calculated_clock->dot),
 859                              target_freq);
 860         /*
 861          * Prefer a better P value over a better (smaller) error if the error
 862          * is small. Ensure this preference for future configurations too by
 863          * setting the error to 0.
 864          */
 865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 866                 *error_ppm = 0;
 867
 868                 return true;
 869         }
 870
 871         return *error_ppm + 10 < best_error_ppm;
 872 }
 873
 874 /*
 875  * Returns a set of divisors for the desired target clock with the given
 876  * refclk, or FALSE.  The returned values represent the clock equation:
 877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 878  */
 879 static bool
 880 vlv_find_best_dpll(const struct intel_limit *limit,
 881                    struct intel_crtc_state *crtc_state,
 882                    int target, int refclk, struct dpll *match_clock,
 883                    struct dpll *best_clock)
 884 {
 885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 886         struct drm_device *dev = crtc->base.dev;
 887         struct dpll clock;
 888         unsigned int bestppm = 1000000;
 889         /* min update 19.2 MHz */
 890         int max_n = min(limit->n.max, refclk / 19200);
 891         bool found = false;
 892
 893         target *= 5; /* fast clock */
 894
 895         memset(best_clock, 0, sizeof(*best_clock));
 896
 897         /* based on hardware requirement, prefer smaller n to precision */
 898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 902                                 clock.p = clock.p1 * clock.p2;
 903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 905                                         unsigned int ppm;
 906
 907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 908                                                                      refclk * clock.m1);
 909
 910                                         vlv_calc_dpll_params(refclk, &clock);
 911
 912                                         if (!intel_PLL_is_valid(dev, limit,
 913                                                                 &clock))
 914                                                 continue;
 915
 916                                         if (!vlv_PLL_is_optimal(dev, target,
 917                                                                 &clock,
 918                                                                 best_clock,
 919                                                                 bestppm, &ppm))
 920                                                 continue;
 921
 922                                         *best_clock = clock;
 923                                         bestppm = ppm;
 924                                         found = true;
 925                                 }
 926                         }
 927                 }
 928         }
 929
 930         return found;
 931 }
 932
 933 /*
 934  * Returns a set of divisors for the desired target clock with the given
 935  * refclk, or FALSE.  The returned values represent the clock equation:
 936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 937  */
 938 static bool
 939 chv_find_best_dpll(const struct intel_limit *limit,
 940                    struct intel_crtc_state *crtc_state,
 941                    int target, int refclk, struct dpll *match_clock,
 942                    struct dpll *best_clock)
 943 {
 944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 945         struct drm_device *dev = crtc->base.dev;
 946         unsigned int best_error_ppm;
 947         struct dpll clock;
 948         uint64_t m2;
 949         int found = false;
 950
 951         memset(best_clock, 0, sizeof(*best_clock));
 952         best_error_ppm = 1000000;
 953
 954         /*
 955          * Based on hardware doc, the n always set to 1, and m1 always
 956          * set to 2.  If requires to support 200Mhz refclk, we need to
 957          * revisit this because n may not 1 anymore.
 958          */
 959         clock.n = 1, clock.m1 = 2;
 960         target *= 5;    /* fast clock */
 961
 962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 963                 for (clock.p2 = limit->p2.p2_fast;
 964                                 clock.p2 >= limit->p2.p2_slow;
 965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 966                         unsigned int error_ppm;
 967
 968                         clock.p = clock.p1 * clock.p2;
 969
 970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 971                                         clock.n) << 22, refclk * clock.m1);
 972
 973                         if (m2 > INT_MAX/clock.m1)
 974                                 continue;
 975
 976                         clock.m2 = m2;
 977
 978                         chv_calc_dpll_params(refclk, &clock);
 979
 980                         if (!intel_PLL_is_valid(dev, limit, &clock))
 981                                 continue;
 982
 983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 984                                                 best_error_ppm, &error_ppm))
 985                                 continue;
 986
 987                         *best_clock = clock;
 988                         best_error_ppm = error_ppm;
 989                         found = true;
 990                 }
 991         }
 992
 993         return found;
 994 }
 995
 996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 997                         struct dpll *best_clock)
 998 {
 999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051
1052         return line1 == line2;
1053 }
1054
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516
1517         assert_pipe_disabled(dev_priv, pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537
1538         mutex_lock(&dev_priv->sb_lock);
1539
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545         mutex_unlock(&dev_priv->sb_lock);
1546
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567
1568         assert_pipe_disabled(dev_priv, pipe);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608
1609         return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644
1645         I915_WRITE(reg, dpll);
1646
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743
1744         mutex_lock(&dev_priv->sb_lock);
1745
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (intel_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (intel_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282
2283         return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298
2299         if (intel_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326
2327         tiles = (old_offset - new_offset) / tile_size;
2328
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353         WARN_ON(new_offset > old_offset);
2354
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362
2363                 if (intel_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379
2380         return new_offset;
2381 }
2382
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407
2408         if (alignment)
2409                 alignment--;
2410
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418
2419                 if (intel_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445
2446         return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680
2681         size_aligned -= base_aligned;
2682
2683         if (plane_config->size == 0)
2684                 return false;
2685
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718
2719         mutex_unlock(&dev->struct_mutex);
2720
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760
2761         if (!plane_config->fb)
2762                 return;
2763
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768
2769         kfree(plane_config->fb);
2770
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780
2781                 if (!i->active)
2782                         continue;
2783
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807         return;
2808
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879
2880         return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939
2940         return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968
2969         return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (intel_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width, fb->height, DRM_ROTATE_270);
2982
2983         /*
2984          * Handle the AUX surface first since
2985          * the main surface setup depends on it.
2986          */
2987         if (fb->pixel_format == DRM_FORMAT_NV12) {
2988                 ret = skl_check_nv12_aux_surface(plane_state);
2989                 if (ret)
2990                         return ret;
2991         } else {
2992                 plane_state->aux.offset = ~0xfff;
2993                 plane_state->aux.x = 0;
2994                 plane_state->aux.y = 0;
2995         }
2996
2997         ret = skl_check_main_surface(plane_state);
2998         if (ret)
2999                 return ret;
3000
3001         return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005                                       const struct intel_crtc_state *crtc_state,
3006                                       const struct intel_plane_state *plane_state)
3007 {
3008         struct drm_device *dev = primary->dev;
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_INFO(dev)->gen < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->pixel_format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (IS_G4X(dev))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_INFO(dev)->gen >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation == DRM_ROTATE_180) {
3084                 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086                 x += (crtc_state->pipe_src_w - 1);
3087                 y += (crtc_state->pipe_src_h - 1);
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_INFO(dev)->gen < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_INFO(dev)->gen >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else
3108                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3177                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179         intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181         intel_crtc->dspaddr_offset =
3182                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184         if (rotation == DRM_ROTATE_180) {
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3188                         x += (crtc_state->pipe_src_w - 1);
3189                         y += (crtc_state->pipe_src_h - 1);
3190                 }
3191         }
3192
3193         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195         intel_crtc->adjusted_x = x;
3196         intel_crtc->adjusted_y = y;
3197
3198         I915_WRITE(reg, dspcntr);
3199
3200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201         I915_WRITE(DSPSURF(plane),
3202                    intel_fb_gtt_offset(fb, rotation) +
3203                    intel_crtc->dspaddr_offset);
3204         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3205                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206         } else {
3207                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209         }
3210         POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214                               uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217                 return 64;
3218         } else {
3219                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222         }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226                         unsigned int rotation)
3227 {
3228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229         struct i915_ggtt_view view;
3230         struct i915_vma *vma;
3231
3232         intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234         vma = i915_gem_object_to_ggtt(obj, &view);
3235         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236                  view.type))
3237                 return -1;
3238
3239         return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244         struct drm_device *dev = intel_crtc->base.dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253  * This function detaches (aka. unbinds) unused scalers in hardware
3254  */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257         struct intel_crtc_scaler_state *scaler_state;
3258         int i;
3259
3260         scaler_state = &intel_crtc->config->scaler_state;
3261
3262         /* loop through and disable scalers that aren't in use */
3263         for (i = 0; i < intel_crtc->num_scalers; i++) {
3264                 if (!scaler_state->scalers[i].in_use)
3265                         skl_detach_scaler(intel_crtc, i);
3266         }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270                      unsigned int rotation)
3271 {
3272         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273         u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275         /*
3276          * The stride is either expressed as a multiple of 64 bytes chunks for
3277          * linear buffers or in number of tiles for tiled buffers.
3278          */
3279         if (intel_rotation_90_or_270(rotation)) {
3280                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283         } else {
3284                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285                                                     fb->pixel_format);
3286         }
3287
3288         return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293         switch (pixel_format) {
3294         case DRM_FORMAT_C8:
3295                 return PLANE_CTL_FORMAT_INDEXED;
3296         case DRM_FORMAT_RGB565:
3297                 return PLANE_CTL_FORMAT_RGB_565;
3298         case DRM_FORMAT_XBGR8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300         case DRM_FORMAT_XRGB8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888;
3302         /*
3303          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304          * to be already pre-multiplied. We need to add a knob (or a different
3305          * DRM_FORMAT) for user-space to configure that.
3306          */
3307         case DRM_FORMAT_ABGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310         case DRM_FORMAT_ARGB8888:
3311                 return PLANE_CTL_FORMAT_XRGB_8888 |
3312                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313         case DRM_FORMAT_XRGB2101010:
3314                 return PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_XBGR2101010:
3316                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_YUYV:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319         case DRM_FORMAT_YVYU:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321         case DRM_FORMAT_UYVY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323         case DRM_FORMAT_VYUY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325         default:
3326                 MISSING_CASE(pixel_format);
3327         }
3328
3329         return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334         switch (fb_modifier) {
3335         case DRM_FORMAT_MOD_NONE:
3336                 break;
3337         case I915_FORMAT_MOD_X_TILED:
3338                 return PLANE_CTL_TILED_X;
3339         case I915_FORMAT_MOD_Y_TILED:
3340                 return PLANE_CTL_TILED_Y;
3341         case I915_FORMAT_MOD_Yf_TILED:
3342                 return PLANE_CTL_TILED_YF;
3343         default:
3344                 MISSING_CASE(fb_modifier);
3345         }
3346
3347         return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352         switch (rotation) {
3353         case DRM_ROTATE_0:
3354                 break;
3355         /*
3356          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357          * while i915 HW rotation is clockwise, thats why this swapping.
3358          */
3359         case DRM_ROTATE_90:
3360                 return PLANE_CTL_ROTATE_270;
3361         case DRM_ROTATE_180:
3362                 return PLANE_CTL_ROTATE_180;
3363         case DRM_ROTATE_270:
3364                 return PLANE_CTL_ROTATE_90;
3365         default:
3366                 MISSING_CASE(rotation);
3367         }
3368
3369         return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373                                          const struct intel_crtc_state *crtc_state,
3374                                          const struct intel_plane_state *plane_state)
3375 {
3376         struct drm_device *dev = plane->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379         struct drm_framebuffer *fb = plane_state->base.fb;
3380         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381         int pipe = intel_crtc->pipe;
3382         u32 plane_ctl;
3383         unsigned int rotation = plane_state->base.rotation;
3384         u32 stride = skl_plane_stride(fb, 0, rotation);
3385         u32 surf_addr = plane_state->main.offset;
3386         int scaler_id = plane_state->scaler_id;
3387         int src_x = plane_state->main.x;
3388         int src_y = plane_state->main.y;
3389         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391         int dst_x = plane_state->base.dst.x1;
3392         int dst_y = plane_state->base.dst.y1;
3393         int dst_w = drm_rect_width(&plane_state->base.dst);
3394         int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396         plane_ctl = PLANE_CTL_ENABLE |
3397                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3398                     PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403         plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405         /* Sizes are 0 based */
3406         src_w--;
3407         src_h--;
3408         dst_w--;
3409         dst_h--;
3410
3411         intel_crtc->adjusted_x = src_x;
3412         intel_crtc->adjusted_y = src_y;
3413
3414         if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3415                 skl_write_plane_wm(intel_crtc, wm, 0);
3416
3417         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3418         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3419         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3420         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3421
3422         if (scaler_id >= 0) {
3423                 uint32_t ps_ctrl = 0;
3424
3425                 WARN_ON(!dst_w || !dst_h);
3426                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3427                         crtc_state->scaler_state.scalers[scaler_id].mode;
3428                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3429                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3430                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3431                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3432                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3433         } else {
3434                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3435         }
3436
3437         I915_WRITE(PLANE_SURF(pipe, 0),
3438                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3439
3440         POSTING_READ(PLANE_SURF(pipe, 0));
3441 }
3442
3443 static void skylake_disable_primary_plane(struct drm_plane *primary,
3444                                           struct drm_crtc *crtc)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447         struct drm_i915_private *dev_priv = to_i915(dev);
3448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449         int pipe = intel_crtc->pipe;
3450
3451         /*
3452          * We only populate skl_results on watermark updates, and if the
3453          * plane's visiblity isn't actually changing neither is its watermarks.
3454          */
3455         if (!crtc->primary->state->visible)
3456                 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3457
3458         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3459         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3460         POSTING_READ(PLANE_SURF(pipe, 0));
3461 }
3462
3463 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3464 static int
3465 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3466                            int x, int y, enum mode_set_atomic state)
3467 {
3468         /* Support for kgdboc is disabled, this needs a major rework. */
3469         DRM_ERROR("legacy panic handler not supported any more.\n");
3470
3471         return -ENODEV;
3472 }
3473
3474 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3475 {
3476         struct intel_crtc *crtc;
3477
3478         for_each_intel_crtc(&dev_priv->drm, crtc)
3479                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3480 }
3481
3482 static void intel_update_primary_planes(struct drm_device *dev)
3483 {
3484         struct drm_crtc *crtc;
3485
3486         for_each_crtc(dev, crtc) {
3487                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3488                 struct intel_plane_state *plane_state =
3489                         to_intel_plane_state(plane->base.state);
3490
3491                 if (plane_state->base.visible)
3492                         plane->update_plane(&plane->base,
3493                                             to_intel_crtc_state(crtc->state),
3494                                             plane_state);
3495         }
3496 }
3497
3498 static int
3499 __intel_display_resume(struct drm_device *dev,
3500                        struct drm_atomic_state *state)
3501 {
3502         struct drm_crtc_state *crtc_state;
3503         struct drm_crtc *crtc;
3504         int i, ret;
3505
3506         intel_modeset_setup_hw_state(dev);
3507         i915_redisable_vga(dev);
3508
3509         if (!state)
3510                 return 0;
3511
3512         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3513                 /*
3514                  * Force recalculation even if we restore
3515                  * current state. With fast modeset this may not result
3516                  * in a modeset when the state is compatible.
3517                  */
3518                 crtc_state->mode_changed = true;
3519         }
3520
3521         /* ignore any reset values/BIOS leftovers in the WM registers */
3522         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3523
3524         ret = drm_atomic_commit(state);
3525
3526         WARN_ON(ret == -EDEADLK);
3527         return ret;
3528 }
3529
3530 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3531 {
3532         return intel_has_gpu_reset(dev_priv) &&
3533                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3534 }
3535
3536 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3537 {
3538         struct drm_device *dev = &dev_priv->drm;
3539         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540         struct drm_atomic_state *state;
3541         int ret;
3542
3543         /*
3544          * Need mode_config.mutex so that we don't
3545          * trample ongoing ->detect() and whatnot.
3546          */
3547         mutex_lock(&dev->mode_config.mutex);
3548         drm_modeset_acquire_init(ctx, 0);
3549         while (1) {
3550                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3551                 if (ret != -EDEADLK)
3552                         break;
3553
3554                 drm_modeset_backoff(ctx);
3555         }
3556
3557         /* reset doesn't touch the display, but flips might get nuked anyway, */
3558         if (!i915.force_reset_modeset_test &&
3559             !gpu_reset_clobbers_display(dev_priv))
3560                 return;
3561
3562         /*
3563          * Disabling the crtcs gracefully seems nicer. Also the
3564          * g33 docs say we should at least disable all the planes.
3565          */
3566         state = drm_atomic_helper_duplicate_state(dev, ctx);
3567         if (IS_ERR(state)) {
3568                 ret = PTR_ERR(state);
3569                 state = NULL;
3570                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3571                 goto err;
3572         }
3573
3574         ret = drm_atomic_helper_disable_all(dev, ctx);
3575         if (ret) {
3576                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3577                 goto err;
3578         }
3579
3580         dev_priv->modeset_restore_state = state;
3581         state->acquire_ctx = ctx;
3582         return;
3583
3584 err:
3585         drm_atomic_state_free(state);
3586 }
3587
3588 void intel_finish_reset(struct drm_i915_private *dev_priv)
3589 {
3590         struct drm_device *dev = &dev_priv->drm;
3591         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3592         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3593         int ret;
3594
3595         /*
3596          * Flips in the rings will be nuked by the reset,
3597          * so complete all pending flips so that user space
3598          * will get its events and not get stuck.
3599          */
3600         intel_complete_page_flips(dev_priv);
3601
3602         dev_priv->modeset_restore_state = NULL;
3603
3604         /* reset doesn't touch the display */
3605         if (!gpu_reset_clobbers_display(dev_priv)) {
3606                 if (!state) {
3607                         /*
3608                          * Flips in the rings have been nuked by the reset,
3609                          * so update the base address of all primary
3610                          * planes to the the last fb to make sure we're
3611                          * showing the correct fb after a reset.
3612                          *
3613                          * FIXME: Atomic will make this obsolete since we won't schedule
3614                          * CS-based flips (which might get lost in gpu resets) any more.
3615                          */
3616                         intel_update_primary_planes(dev);
3617                 } else {
3618                         ret = __intel_display_resume(dev, state);
3619                         if (ret)
3620                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3621                 }
3622         } else {
3623                 /*
3624                  * The display has been reset as well,
3625                  * so need a full re-initialization.
3626                  */
3627                 intel_runtime_pm_disable_interrupts(dev_priv);
3628                 intel_runtime_pm_enable_interrupts(dev_priv);
3629
3630                 intel_modeset_init_hw(dev);
3631
3632                 spin_lock_irq(&dev_priv->irq_lock);
3633                 if (dev_priv->display.hpd_irq_setup)
3634                         dev_priv->display.hpd_irq_setup(dev_priv);
3635                 spin_unlock_irq(&dev_priv->irq_lock);
3636
3637                 ret = __intel_display_resume(dev, state);
3638                 if (ret)
3639                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3640
3641                 intel_hpd_init(dev_priv);
3642         }
3643
3644         drm_modeset_drop_locks(ctx);
3645         drm_modeset_acquire_fini(ctx);
3646         mutex_unlock(&dev->mode_config.mutex);
3647 }
3648
3649 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3650 {
3651         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3652
3653         if (i915_reset_in_progress(error))
3654                 return true;
3655
3656         if (crtc->reset_count != i915_reset_count(error))
3657                 return true;
3658
3659         return false;
3660 }
3661
3662 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3663 {
3664         struct drm_device *dev = crtc->dev;
3665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3666         bool pending;
3667
3668         if (abort_flip_on_reset(intel_crtc))
3669                 return false;
3670
3671         spin_lock_irq(&dev->event_lock);
3672         pending = to_intel_crtc(crtc)->flip_work != NULL;
3673         spin_unlock_irq(&dev->event_lock);
3674
3675         return pending;
3676 }
3677
3678 static void intel_update_pipe_config(struct intel_crtc *crtc,
3679                                      struct intel_crtc_state *old_crtc_state)
3680 {
3681         struct drm_device *dev = crtc->base.dev;
3682         struct drm_i915_private *dev_priv = to_i915(dev);
3683         struct intel_crtc_state *pipe_config =
3684                 to_intel_crtc_state(crtc->base.state);
3685
3686         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3687         crtc->base.mode = crtc->base.state->mode;
3688
3689         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3690                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3691                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3692
3693         /*
3694          * Update pipe size and adjust fitter if needed: the reason for this is
3695          * that in compute_mode_changes we check the native mode (not the pfit
3696          * mode) to see if we can flip rather than do a full mode set. In the
3697          * fastboot case, we'll flip, but if we don't update the pipesrc and
3698          * pfit state, we'll end up with a big fb scanned out into the wrong
3699          * sized surface.
3700          */
3701
3702         I915_WRITE(PIPESRC(crtc->pipe),
3703                    ((pipe_config->pipe_src_w - 1) << 16) |
3704                    (pipe_config->pipe_src_h - 1));
3705
3706         /* on skylake this is done by detaching scalers */
3707         if (INTEL_INFO(dev)->gen >= 9) {
3708                 skl_detach_scalers(crtc);
3709
3710                 if (pipe_config->pch_pfit.enabled)
3711                         skylake_pfit_enable(crtc);
3712         } else if (HAS_PCH_SPLIT(dev)) {
3713                 if (pipe_config->pch_pfit.enabled)
3714                         ironlake_pfit_enable(crtc);
3715                 else if (old_crtc_state->pch_pfit.enabled)
3716                         ironlake_pfit_disable(crtc, true);
3717         }
3718 }
3719
3720 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3721 {
3722         struct drm_device *dev = crtc->dev;
3723         struct drm_i915_private *dev_priv = to_i915(dev);
3724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3725         int pipe = intel_crtc->pipe;
3726         i915_reg_t reg;
3727         u32 temp;
3728
3729         /* enable normal train */
3730         reg = FDI_TX_CTL(pipe);
3731         temp = I915_READ(reg);
3732         if (IS_IVYBRIDGE(dev)) {
3733                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3734                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3735         } else {
3736                 temp &= ~FDI_LINK_TRAIN_NONE;
3737                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3738         }
3739         I915_WRITE(reg, temp);
3740
3741         reg = FDI_RX_CTL(pipe);
3742         temp = I915_READ(reg);
3743         if (HAS_PCH_CPT(dev)) {
3744                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3745                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3746         } else {
3747                 temp &= ~FDI_LINK_TRAIN_NONE;
3748                 temp |= FDI_LINK_TRAIN_NONE;
3749         }
3750         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3751
3752         /* wait one idle pattern time */
3753         POSTING_READ(reg);
3754         udelay(1000);
3755
3756         /* IVB wants error correction enabled */
3757         if (IS_IVYBRIDGE(dev))
3758                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3759                            FDI_FE_ERRC_ENABLE);
3760 }
3761
3762 /* The FDI link training functions for ILK/Ibexpeak. */
3763 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3764 {
3765         struct drm_device *dev = crtc->dev;
3766         struct drm_i915_private *dev_priv = to_i915(dev);
3767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3768         int pipe = intel_crtc->pipe;
3769         i915_reg_t reg;
3770         u32 temp, tries;
3771
3772         /* FDI needs bits from pipe first */
3773         assert_pipe_enabled(dev_priv, pipe);
3774
3775         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3776            for train result */
3777         reg = FDI_RX_IMR(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~FDI_RX_SYMBOL_LOCK;
3780         temp &= ~FDI_RX_BIT_LOCK;
3781         I915_WRITE(reg, temp);
3782         I915_READ(reg);
3783         udelay(150);
3784
3785         /* enable CPU FDI TX and PCH FDI RX */
3786         reg = FDI_TX_CTL(pipe);
3787         temp = I915_READ(reg);
3788         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3789         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3790         temp &= ~FDI_LINK_TRAIN_NONE;
3791         temp |= FDI_LINK_TRAIN_PATTERN_1;
3792         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3793
3794         reg = FDI_RX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         temp &= ~FDI_LINK_TRAIN_NONE;
3797         temp |= FDI_LINK_TRAIN_PATTERN_1;
3798         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3799
3800         POSTING_READ(reg);
3801         udelay(150);
3802
3803         /* Ironlake workaround, enable clock pointer after FDI enable*/
3804         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3805         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3806                    FDI_RX_PHASE_SYNC_POINTER_EN);
3807
3808         reg = FDI_RX_IIR(pipe);
3809         for (tries = 0; tries < 5; tries++) {
3810                 temp = I915_READ(reg);
3811                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3812
3813                 if ((temp & FDI_RX_BIT_LOCK)) {
3814                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3815                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3816                         break;
3817                 }
3818         }
3819         if (tries == 5)
3820                 DRM_ERROR("FDI train 1 fail!\n");
3821
3822         /* Train 2 */
3823         reg = FDI_TX_CTL(pipe);
3824         temp = I915_READ(reg);
3825         temp &= ~FDI_LINK_TRAIN_NONE;
3826         temp |= FDI_LINK_TRAIN_PATTERN_2;
3827         I915_WRITE(reg, temp);
3828
3829         reg = FDI_RX_CTL(pipe);
3830         temp = I915_READ(reg);
3831         temp &= ~FDI_LINK_TRAIN_NONE;
3832         temp |= FDI_LINK_TRAIN_PATTERN_2;
3833         I915_WRITE(reg, temp);
3834
3835         POSTING_READ(reg);
3836         udelay(150);
3837
3838         reg = FDI_RX_IIR(pipe);
3839         for (tries = 0; tries < 5; tries++) {
3840                 temp = I915_READ(reg);
3841                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3842
3843                 if (temp & FDI_RX_SYMBOL_LOCK) {
3844                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3845                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3846                         break;
3847                 }
3848         }
3849         if (tries == 5)
3850                 DRM_ERROR("FDI train 2 fail!\n");
3851
3852         DRM_DEBUG_KMS("FDI train done\n");
3853
3854 }
3855
3856 static const int snb_b_fdi_train_param[] = {
3857         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3858         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3859         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3860         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3861 };
3862
3863 /* The FDI link training functions for SNB/Cougarpoint. */
3864 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3865 {
3866         struct drm_device *dev = crtc->dev;
3867         struct drm_i915_private *dev_priv = to_i915(dev);
3868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3869         int pipe = intel_crtc->pipe;
3870         i915_reg_t reg;
3871         u32 temp, i, retry;
3872
3873         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3874            for train result */
3875         reg = FDI_RX_IMR(pipe);
3876         temp = I915_READ(reg);
3877         temp &= ~FDI_RX_SYMBOL_LOCK;
3878         temp &= ~FDI_RX_BIT_LOCK;
3879         I915_WRITE(reg, temp);
3880
3881         POSTING_READ(reg);
3882         udelay(150);
3883
3884         /* enable CPU FDI TX and PCH FDI RX */
3885         reg = FDI_TX_CTL(pipe);
3886         temp = I915_READ(reg);
3887         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3888         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3889         temp &= ~FDI_LINK_TRAIN_NONE;
3890         temp |= FDI_LINK_TRAIN_PATTERN_1;
3891         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3892         /* SNB-B */
3893         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3894         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3895
3896         I915_WRITE(FDI_RX_MISC(pipe),
3897                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3898
3899         reg = FDI_RX_CTL(pipe);
3900         temp = I915_READ(reg);
3901         if (HAS_PCH_CPT(dev)) {
3902                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3903                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3904         } else {
3905                 temp &= ~FDI_LINK_TRAIN_NONE;
3906                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3907         }
3908         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3909
3910         POSTING_READ(reg);
3911         udelay(150);
3912
3913         for (i = 0; i < 4; i++) {
3914                 reg = FDI_TX_CTL(pipe);
3915                 temp = I915_READ(reg);
3916                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3917                 temp |= snb_b_fdi_train_param[i];
3918                 I915_WRITE(reg, temp);
3919
3920                 POSTING_READ(reg);
3921                 udelay(500);
3922
3923                 for (retry = 0; retry < 5; retry++) {
3924                         reg = FDI_RX_IIR(pipe);
3925                         temp = I915_READ(reg);
3926                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3927                         if (temp & FDI_RX_BIT_LOCK) {
3928                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3929                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3930                                 break;
3931                         }
3932                         udelay(50);
3933                 }
3934                 if (retry < 5)
3935                         break;
3936         }
3937         if (i == 4)
3938                 DRM_ERROR("FDI train 1 fail!\n");
3939
3940         /* Train 2 */
3941         reg = FDI_TX_CTL(pipe);
3942         temp = I915_READ(reg);
3943         temp &= ~FDI_LINK_TRAIN_NONE;
3944         temp |= FDI_LINK_TRAIN_PATTERN_2;
3945         if (IS_GEN6(dev)) {
3946                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3947                 /* SNB-B */
3948                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3949         }
3950         I915_WRITE(reg, temp);
3951
3952         reg = FDI_RX_CTL(pipe);
3953         temp = I915_READ(reg);
3954         if (HAS_PCH_CPT(dev)) {
3955                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3956                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3957         } else {
3958                 temp &= ~FDI_LINK_TRAIN_NONE;
3959                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3960         }
3961         I915_WRITE(reg, temp);
3962
3963         POSTING_READ(reg);
3964         udelay(150);
3965
3966         for (i = 0; i < 4; i++) {
3967                 reg = FDI_TX_CTL(pipe);
3968                 temp = I915_READ(reg);
3969                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3970                 temp |= snb_b_fdi_train_param[i];
3971                 I915_WRITE(reg, temp);
3972
3973                 POSTING_READ(reg);
3974                 udelay(500);
3975
3976                 for (retry = 0; retry < 5; retry++) {
3977                         reg = FDI_RX_IIR(pipe);
3978                         temp = I915_READ(reg);
3979                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3980                         if (temp & FDI_RX_SYMBOL_LOCK) {
3981                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3982                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3983                                 break;
3984                         }
3985                         udelay(50);
3986                 }
3987                 if (retry < 5)
3988                         break;
3989         }
3990         if (i == 4)
3991                 DRM_ERROR("FDI train 2 fail!\n");
3992
3993         DRM_DEBUG_KMS("FDI train done.\n");
3994 }
3995
3996 /* Manual link training for Ivy Bridge A0 parts */
3997 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3998 {
3999         struct drm_device *dev = crtc->dev;
4000         struct drm_i915_private *dev_priv = to_i915(dev);
4001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4002         int pipe = intel_crtc->pipe;
4003         i915_reg_t reg;
4004         u32 temp, i, j;
4005
4006         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4007            for train result */
4008         reg = FDI_RX_IMR(pipe);
4009         temp = I915_READ(reg);
4010         temp &= ~FDI_RX_SYMBOL_LOCK;
4011         temp &= ~FDI_RX_BIT_LOCK;
4012         I915_WRITE(reg, temp);
4013
4014         POSTING_READ(reg);
4015         udelay(150);
4016
4017         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4018                       I915_READ(FDI_RX_IIR(pipe)));
4019
4020         /* Try each vswing and preemphasis setting twice before moving on */
4021         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4022                 /* disable first in case we need to retry */
4023                 reg = FDI_TX_CTL(pipe);
4024                 temp = I915_READ(reg);
4025                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4026                 temp &= ~FDI_TX_ENABLE;
4027                 I915_WRITE(reg, temp);
4028
4029                 reg = FDI_RX_CTL(pipe);
4030                 temp = I915_READ(reg);
4031                 temp &= ~FDI_LINK_TRAIN_AUTO;
4032                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4033                 temp &= ~FDI_RX_ENABLE;
4034                 I915_WRITE(reg, temp);
4035
4036                 /* enable CPU FDI TX and PCH FDI RX */
4037                 reg = FDI_TX_CTL(pipe);
4038                 temp = I915_READ(reg);
4039                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4040                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4041                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4042                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4043                 temp |= snb_b_fdi_train_param[j/2];
4044                 temp |= FDI_COMPOSITE_SYNC;
4045                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4046
4047                 I915_WRITE(FDI_RX_MISC(pipe),
4048                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4049
4050                 reg = FDI_RX_CTL(pipe);
4051                 temp = I915_READ(reg);
4052                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4053                 temp |= FDI_COMPOSITE_SYNC;
4054                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4055
4056                 POSTING_READ(reg);
4057                 udelay(1); /* should be 0.5us */
4058
4059                 for (i = 0; i < 4; i++) {
4060                         reg = FDI_RX_IIR(pipe);
4061                         temp = I915_READ(reg);
4062                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4063
4064                         if (temp & FDI_RX_BIT_LOCK ||
4065                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4066                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4067                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4068                                               i);
4069                                 break;
4070                         }
4071                         udelay(1); /* should be 0.5us */
4072                 }
4073                 if (i == 4) {
4074                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4075                         continue;
4076                 }
4077
4078                 /* Train 2 */
4079                 reg = FDI_TX_CTL(pipe);
4080                 temp = I915_READ(reg);
4081                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4082                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4083                 I915_WRITE(reg, temp);
4084
4085                 reg = FDI_RX_CTL(pipe);
4086                 temp = I915_READ(reg);
4087                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4088                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4089                 I915_WRITE(reg, temp);
4090
4091                 POSTING_READ(reg);
4092                 udelay(2); /* should be 1.5us */
4093
4094                 for (i = 0; i < 4; i++) {
4095                         reg = FDI_RX_IIR(pipe);
4096                         temp = I915_READ(reg);
4097                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4098
4099                         if (temp & FDI_RX_SYMBOL_LOCK ||
4100                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4101                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4102                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4103                                               i);
4104                                 goto train_done;
4105                         }
4106                         udelay(2); /* should be 1.5us */
4107                 }
4108                 if (i == 4)
4109                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4110         }
4111
4112 train_done:
4113         DRM_DEBUG_KMS("FDI train done.\n");
4114 }
4115
4116 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4117 {
4118         struct drm_device *dev = intel_crtc->base.dev;
4119         struct drm_i915_private *dev_priv = to_i915(dev);
4120         int pipe = intel_crtc->pipe;
4121         i915_reg_t reg;
4122         u32 temp;
4123
4124         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4125         reg = FDI_RX_CTL(pipe);
4126         temp = I915_READ(reg);
4127         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4128         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4129         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4130         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4131
4132         POSTING_READ(reg);
4133         udelay(200);
4134
4135         /* Switch from Rawclk to PCDclk */
4136         temp = I915_READ(reg);
4137         I915_WRITE(reg, temp | FDI_PCDCLK);
4138
4139         POSTING_READ(reg);
4140         udelay(200);
4141
4142         /* Enable CPU FDI TX PLL, always on for Ironlake */
4143         reg = FDI_TX_CTL(pipe);
4144         temp = I915_READ(reg);
4145         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4146                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4147
4148                 POSTING_READ(reg);
4149                 udelay(100);
4150         }
4151 }
4152
4153 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4154 {
4155         struct drm_device *dev = intel_crtc->base.dev;
4156         struct drm_i915_private *dev_priv = to_i915(dev);
4157         int pipe = intel_crtc->pipe;
4158         i915_reg_t reg;
4159         u32 temp;
4160
4161         /* Switch from PCDclk to Rawclk */
4162         reg = FDI_RX_CTL(pipe);
4163         temp = I915_READ(reg);
4164         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4165
4166         /* Disable CPU FDI TX PLL */
4167         reg = FDI_TX_CTL(pipe);
4168         temp = I915_READ(reg);
4169         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4170
4171         POSTING_READ(reg);
4172         udelay(100);
4173
4174         reg = FDI_RX_CTL(pipe);
4175         temp = I915_READ(reg);
4176         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4177
4178         /* Wait for the clocks to turn off. */
4179         POSTING_READ(reg);
4180         udelay(100);
4181 }
4182
4183 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4184 {
4185         struct drm_device *dev = crtc->dev;
4186         struct drm_i915_private *dev_priv = to_i915(dev);
4187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4188         int pipe = intel_crtc->pipe;
4189         i915_reg_t reg;
4190         u32 temp;
4191
4192         /* disable CPU FDI tx and PCH FDI rx */
4193         reg = FDI_TX_CTL(pipe);
4194         temp = I915_READ(reg);
4195         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4196         POSTING_READ(reg);
4197
4198         reg = FDI_RX_CTL(pipe);
4199         temp = I915_READ(reg);
4200         temp &= ~(0x7 << 16);
4201         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4202         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4203
4204         POSTING_READ(reg);
4205         udelay(100);
4206
4207         /* Ironlake workaround, disable clock pointer after downing FDI */
4208         if (HAS_PCH_IBX(dev))
4209                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4210
4211         /* still set train pattern 1 */
4212         reg = FDI_TX_CTL(pipe);
4213         temp = I915_READ(reg);
4214         temp &= ~FDI_LINK_TRAIN_NONE;
4215         temp |= FDI_LINK_TRAIN_PATTERN_1;
4216         I915_WRITE(reg, temp);
4217
4218         reg = FDI_RX_CTL(pipe);
4219         temp = I915_READ(reg);
4220         if (HAS_PCH_CPT(dev)) {
4221                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4222                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4223         } else {
4224                 temp &= ~FDI_LINK_TRAIN_NONE;
4225                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4226         }
4227         /* BPC in FDI rx is consistent with that in PIPECONF */
4228         temp &= ~(0x07 << 16);
4229         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4230         I915_WRITE(reg, temp);
4231
4232         POSTING_READ(reg);
4233         udelay(100);
4234 }
4235
4236 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4237 {
4238         struct intel_crtc *crtc;
4239
4240         /* Note that we don't need to be called with mode_config.lock here
4241          * as our list of CRTC objects is static for the lifetime of the
4242          * device and so cannot disappear as we iterate. Similarly, we can
4243          * happily treat the predicates as racy, atomic checks as userspace
4244          * cannot claim and pin a new fb without at least acquring the
4245          * struct_mutex and so serialising with us.
4246          */
4247         for_each_intel_crtc(dev, crtc) {
4248                 if (atomic_read(&crtc->unpin_work_count) == 0)
4249                         continue;
4250
4251                 if (crtc->flip_work)
4252                         intel_wait_for_vblank(dev, crtc->pipe);
4253
4254                 return true;
4255         }
4256
4257         return false;
4258 }
4259
4260 static void page_flip_completed(struct intel_crtc *intel_crtc)
4261 {
4262         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4263         struct intel_flip_work *work = intel_crtc->flip_work;
4264
4265         intel_crtc->flip_work = NULL;
4266
4267         if (work->event)
4268                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4269
4270         drm_crtc_vblank_put(&intel_crtc->base);
4271
4272         wake_up_all(&dev_priv->pending_flip_queue);
4273         queue_work(dev_priv->wq, &work->unpin_work);
4274
4275         trace_i915_flip_complete(intel_crtc->plane,
4276                                  work->pending_flip_obj);
4277 }
4278
4279 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4280 {
4281         struct drm_device *dev = crtc->dev;
4282         struct drm_i915_private *dev_priv = to_i915(dev);
4283         long ret;
4284
4285         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4286
4287         ret = wait_event_interruptible_timeout(
4288                                         dev_priv->pending_flip_queue,
4289                                         !intel_crtc_has_pending_flip(crtc),
4290                                         60*HZ);
4291
4292         if (ret < 0)
4293                 return ret;
4294
4295         if (ret == 0) {
4296                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297                 struct intel_flip_work *work;
4298
4299                 spin_lock_irq(&dev->event_lock);
4300                 work = intel_crtc->flip_work;
4301                 if (work && !is_mmio_work(work)) {
4302                         WARN_ONCE(1, "Removing stuck page flip\n");
4303                         page_flip_completed(intel_crtc);
4304                 }
4305                 spin_unlock_irq(&dev->event_lock);
4306         }
4307
4308         return 0;
4309 }
4310
4311 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4312 {
4313         u32 temp;
4314
4315         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4316
4317         mutex_lock(&dev_priv->sb_lock);
4318
4319         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4320         temp |= SBI_SSCCTL_DISABLE;
4321         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4322
4323         mutex_unlock(&dev_priv->sb_lock);
4324 }
4325
4326 /* Program iCLKIP clock to the desired frequency */
4327 static void lpt_program_iclkip(struct drm_crtc *crtc)
4328 {
4329         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4330         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4331         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4332         u32 temp;
4333
4334         lpt_disable_iclkip(dev_priv);
4335
4336         /* The iCLK virtual clock root frequency is in MHz,
4337          * but the adjusted_mode->crtc_clock in in KHz. To get the
4338          * divisors, it is necessary to divide one by another, so we
4339          * convert the virtual clock precision to KHz here for higher
4340          * precision.
4341          */
4342         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4343                 u32 iclk_virtual_root_freq = 172800 * 1000;
4344                 u32 iclk_pi_range = 64;
4345                 u32 desired_divisor;
4346
4347                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4348                                                     clock << auxdiv);
4349                 divsel = (desired_divisor / iclk_pi_range) - 2;
4350                 phaseinc = desired_divisor % iclk_pi_range;
4351
4352                 /*
4353                  * Near 20MHz is a corner case which is
4354                  * out of range for the 7-bit divisor
4355                  */
4356                 if (divsel <= 0x7f)
4357                         break;
4358         }
4359
4360         /* This should not happen with any sane values */
4361         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4362                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4363         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4364                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4365
4366         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4367                         clock,
4368                         auxdiv,
4369                         divsel,
4370                         phasedir,
4371                         phaseinc);
4372
4373         mutex_lock(&dev_priv->sb_lock);
4374
4375         /* Program SSCDIVINTPHASE6 */
4376         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4377         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4378         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4379         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4380         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4381         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4382         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4383         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4384
4385         /* Program SSCAUXDIV */
4386         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4387         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4388         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4389         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4390
4391         /* Enable modulator and associated divider */
4392         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4393         temp &= ~SBI_SSCCTL_DISABLE;
4394         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4395
4396         mutex_unlock(&dev_priv->sb_lock);
4397
4398         /* Wait for initialization time */
4399         udelay(24);
4400
4401         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4402 }
4403
4404 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4405 {
4406         u32 divsel, phaseinc, auxdiv;
4407         u32 iclk_virtual_root_freq = 172800 * 1000;
4408         u32 iclk_pi_range = 64;
4409         u32 desired_divisor;
4410         u32 temp;
4411
4412         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4413                 return 0;
4414
4415         mutex_lock(&dev_priv->sb_lock);
4416
4417         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4418         if (temp & SBI_SSCCTL_DISABLE) {
4419                 mutex_unlock(&dev_priv->sb_lock);
4420                 return 0;
4421         }
4422
4423         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4424         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4425                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4426         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4427                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4428
4429         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4430         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4431                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4432
4433         mutex_unlock(&dev_priv->sb_lock);
4434
4435         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4436
4437         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4438                                  desired_divisor << auxdiv);
4439 }
4440
4441 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4442                                                 enum pipe pch_transcoder)
4443 {
4444         struct drm_device *dev = crtc->base.dev;
4445         struct drm_i915_private *dev_priv = to_i915(dev);
4446         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4447
4448         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4449                    I915_READ(HTOTAL(cpu_transcoder)));
4450         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4451                    I915_READ(HBLANK(cpu_transcoder)));
4452         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4453                    I915_READ(HSYNC(cpu_transcoder)));
4454
4455         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4456                    I915_READ(VTOTAL(cpu_transcoder)));
4457         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4458                    I915_READ(VBLANK(cpu_transcoder)));
4459         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4460                    I915_READ(VSYNC(cpu_transcoder)));
4461         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4462                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4463 }
4464
4465 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4466 {
4467         struct drm_i915_private *dev_priv = to_i915(dev);
4468         uint32_t temp;
4469
4470         temp = I915_READ(SOUTH_CHICKEN1);
4471         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4472                 return;
4473
4474         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4475         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4476
4477         temp &= ~FDI_BC_BIFURCATION_SELECT;
4478         if (enable)
4479                 temp |= FDI_BC_BIFURCATION_SELECT;
4480
4481         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4482         I915_WRITE(SOUTH_CHICKEN1, temp);
4483         POSTING_READ(SOUTH_CHICKEN1);
4484 }
4485
4486 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4487 {
4488         struct drm_device *dev = intel_crtc->base.dev;
4489
4490         switch (intel_crtc->pipe) {
4491         case PIPE_A:
4492                 break;
4493         case PIPE_B:
4494                 if (intel_crtc->config->fdi_lanes > 2)
4495                         cpt_set_fdi_bc_bifurcation(dev, false);
4496                 else
4497                         cpt_set_fdi_bc_bifurcation(dev, true);
4498
4499                 break;
4500         case PIPE_C:
4501                 cpt_set_fdi_bc_bifurcation(dev, true);
4502
4503                 break;
4504         default:
4505                 BUG();
4506         }
4507 }
4508
4509 /* Return which DP Port should be selected for Transcoder DP control */
4510 static enum port
4511 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->dev;
4514         struct intel_encoder *encoder;
4515
4516         for_each_encoder_on_crtc(dev, crtc, encoder) {
4517                 if (encoder->type == INTEL_OUTPUT_DP ||
4518                     encoder->type == INTEL_OUTPUT_EDP)
4519                         return enc_to_dig_port(&encoder->base)->port;
4520         }
4521
4522         return -1;
4523 }
4524
4525 /*
4526  * Enable PCH resources required for PCH ports:
4527  *   - PCH PLLs
4528  *   - FDI training & RX/TX
4529  *   - update transcoder timings
4530  *   - DP transcoding bits
4531  *   - transcoder
4532  */
4533 static void ironlake_pch_enable(struct drm_crtc *crtc)
4534 {
4535         struct drm_device *dev = crtc->dev;
4536         struct drm_i915_private *dev_priv = to_i915(dev);
4537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538         int pipe = intel_crtc->pipe;
4539         u32 temp;
4540
4541         assert_pch_transcoder_disabled(dev_priv, pipe);
4542
4543         if (IS_IVYBRIDGE(dev))
4544                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4545
4546         /* Write the TU size bits before fdi link training, so that error
4547          * detection works. */
4548         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4549                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4550
4551         /* For PCH output, training FDI link */
4552         dev_priv->display.fdi_link_train(crtc);
4553
4554         /* We need to program the right clock selection before writing the pixel
4555          * mutliplier into the DPLL. */
4556         if (HAS_PCH_CPT(dev)) {
4557                 u32 sel;
4558
4559                 temp = I915_READ(PCH_DPLL_SEL);
4560                 temp |= TRANS_DPLL_ENABLE(pipe);
4561                 sel = TRANS_DPLLB_SEL(pipe);
4562                 if (intel_crtc->config->shared_dpll ==
4563                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4564                         temp |= sel;
4565                 else
4566                         temp &= ~sel;
4567                 I915_WRITE(PCH_DPLL_SEL, temp);
4568         }
4569
4570         /* XXX: pch pll's can be enabled any time before we enable the PCH
4571          * transcoder, and we actually should do this to not upset any PCH
4572          * transcoder that already use the clock when we share it.
4573          *
4574          * Note that enable_shared_dpll tries to do the right thing, but
4575          * get_shared_dpll unconditionally resets the pll - we need that to have
4576          * the right LVDS enable sequence. */
4577         intel_enable_shared_dpll(intel_crtc);
4578
4579         /* set transcoder timing, panel must allow it */
4580         assert_panel_unlocked(dev_priv, pipe);
4581         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4582
4583         intel_fdi_normal_train(crtc);
4584
4585         /* For PCH DP, enable TRANS_DP_CTL */
4586         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4587                 const struct drm_display_mode *adjusted_mode =
4588                         &intel_crtc->config->base.adjusted_mode;
4589                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4590                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4591                 temp = I915_READ(reg);
4592                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4593                           TRANS_DP_SYNC_MASK |
4594                           TRANS_DP_BPC_MASK);
4595                 temp |= TRANS_DP_OUTPUT_ENABLE;
4596                 temp |= bpc << 9; /* same format but at 11:9 */
4597
4598                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4599                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4600                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4601                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4602
4603                 switch (intel_trans_dp_port_sel(crtc)) {
4604                 case PORT_B:
4605                         temp |= TRANS_DP_PORT_SEL_B;
4606                         break;
4607                 case PORT_C:
4608                         temp |= TRANS_DP_PORT_SEL_C;
4609                         break;
4610                 case PORT_D:
4611                         temp |= TRANS_DP_PORT_SEL_D;
4612                         break;
4613                 default:
4614                         BUG();
4615                 }
4616
4617                 I915_WRITE(reg, temp);
4618         }
4619
4620         ironlake_enable_pch_transcoder(dev_priv, pipe);
4621 }
4622
4623 static void lpt_pch_enable(struct drm_crtc *crtc)
4624 {
4625         struct drm_device *dev = crtc->dev;
4626         struct drm_i915_private *dev_priv = to_i915(dev);
4627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4628         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4629
4630         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4631
4632         lpt_program_iclkip(crtc);
4633
4634         /* Set transcoder timing. */
4635         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4636
4637         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4638 }
4639
4640 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4641 {
4642         struct drm_i915_private *dev_priv = to_i915(dev);
4643         i915_reg_t dslreg = PIPEDSL(pipe);
4644         u32 temp;
4645
4646         temp = I915_READ(dslreg);
4647         udelay(500);
4648         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4649                 if (wait_for(I915_READ(dslreg) != temp, 5))
4650                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4651         }
4652 }
4653
4654 static int
4655 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4656                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4657                   int src_w, int src_h, int dst_w, int dst_h)
4658 {
4659         struct intel_crtc_scaler_state *scaler_state =
4660                 &crtc_state->scaler_state;
4661         struct intel_crtc *intel_crtc =
4662                 to_intel_crtc(crtc_state->base.crtc);
4663         int need_scaling;
4664
4665         need_scaling = intel_rotation_90_or_270(rotation) ?
4666                 (src_h != dst_w || src_w != dst_h):
4667                 (src_w != dst_w || src_h != dst_h);
4668
4669         /*
4670          * if plane is being disabled or scaler is no more required or force detach
4671          *  - free scaler binded to this plane/crtc
4672          *  - in order to do this, update crtc->scaler_usage
4673          *
4674          * Here scaler state in crtc_state is set free so that
4675          * scaler can be assigned to other user. Actual register
4676          * update to free the scaler is done in plane/panel-fit programming.
4677          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4678          */
4679         if (force_detach || !need_scaling) {
4680                 if (*scaler_id >= 0) {
4681                         scaler_state->scaler_users &= ~(1 << scaler_user);
4682                         scaler_state->scalers[*scaler_id].in_use = 0;
4683
4684                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4685                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4686                                 intel_crtc->pipe, scaler_user, *scaler_id,
4687                                 scaler_state->scaler_users);
4688                         *scaler_id = -1;
4689                 }
4690                 return 0;
4691         }
4692
4693         /* range checks */
4694         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4695                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4696
4697                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4698                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4699                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4700                         "size is out of scaler range\n",
4701                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4702                 return -EINVAL;
4703         }
4704
4705         /* mark this plane as a scaler user in crtc_state */
4706         scaler_state->scaler_users |= (1 << scaler_user);
4707         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4708                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4709                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4710                 scaler_state->scaler_users);
4711
4712         return 0;
4713 }
4714
4715 /**
4716  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4717  *
4718  * @state: crtc's scaler state
4719  *
4720  * Return
4721  *     0 - scaler_usage updated successfully
4722  *    error - requested scaling cannot be supported or other error condition
4723  */
4724 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4725 {
4726         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4727         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4728
4729         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4730                       intel_crtc->base.base.id, intel_crtc->base.name,
4731                       intel_crtc->pipe, SKL_CRTC_INDEX);
4732
4733         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4734                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4735                 state->pipe_src_w, state->pipe_src_h,
4736                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4737 }
4738
4739 /**
4740  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4741  *
4742  * @state: crtc's scaler state
4743  * @plane_state: atomic plane state to update
4744  *
4745  * Return
4746  *     0 - scaler_usage updated successfully
4747  *    error - requested scaling cannot be supported or other error condition
4748  */
4749 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4750                                    struct intel_plane_state *plane_state)
4751 {
4752
4753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4754         struct intel_plane *intel_plane =
4755                 to_intel_plane(plane_state->base.plane);
4756         struct drm_framebuffer *fb = plane_state->base.fb;
4757         int ret;
4758
4759         bool force_detach = !fb || !plane_state->base.visible;
4760
4761         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4762                       intel_plane->base.base.id, intel_plane->base.name,
4763                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4764
4765         ret = skl_update_scaler(crtc_state, force_detach,
4766                                 drm_plane_index(&intel_plane->base),
4767                                 &plane_state->scaler_id,
4768                                 plane_state->base.rotation,
4769                                 drm_rect_width(&plane_state->base.src) >> 16,
4770                                 drm_rect_height(&plane_state->base.src) >> 16,
4771                                 drm_rect_width(&plane_state->base.dst),
4772                                 drm_rect_height(&plane_state->base.dst));
4773
4774         if (ret || plane_state->scaler_id < 0)
4775                 return ret;
4776
4777         /* check colorkey */
4778         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4779                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4780                               intel_plane->base.base.id,
4781                               intel_plane->base.name);
4782                 return -EINVAL;
4783         }
4784
4785         /* Check src format */
4786         switch (fb->pixel_format) {
4787         case DRM_FORMAT_RGB565:
4788         case DRM_FORMAT_XBGR8888:
4789         case DRM_FORMAT_XRGB8888:
4790         case DRM_FORMAT_ABGR8888:
4791         case DRM_FORMAT_ARGB8888:
4792         case DRM_FORMAT_XRGB2101010:
4793         case DRM_FORMAT_XBGR2101010:
4794         case DRM_FORMAT_YUYV:
4795         case DRM_FORMAT_YVYU:
4796         case DRM_FORMAT_UYVY:
4797         case DRM_FORMAT_VYUY:
4798                 break;
4799         default:
4800                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4801                               intel_plane->base.base.id, intel_plane->base.name,
4802                               fb->base.id, fb->pixel_format);
4803                 return -EINVAL;
4804         }
4805
4806         return 0;
4807 }
4808
4809 static void skylake_scaler_disable(struct intel_crtc *crtc)
4810 {
4811         int i;
4812
4813         for (i = 0; i < crtc->num_scalers; i++)
4814                 skl_detach_scaler(crtc, i);
4815 }
4816
4817 static void skylake_pfit_enable(struct intel_crtc *crtc)
4818 {
4819         struct drm_device *dev = crtc->base.dev;
4820         struct drm_i915_private *dev_priv = to_i915(dev);
4821         int pipe = crtc->pipe;
4822         struct intel_crtc_scaler_state *scaler_state =
4823                 &crtc->config->scaler_state;
4824
4825         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4826
4827         if (crtc->config->pch_pfit.enabled) {
4828                 int id;
4829
4830                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4831                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4832                         return;
4833                 }
4834
4835                 id = scaler_state->scaler_id;
4836                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4837                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4838                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4839                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4840
4841                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4842         }
4843 }
4844
4845 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4846 {
4847         struct drm_device *dev = crtc->base.dev;
4848         struct drm_i915_private *dev_priv = to_i915(dev);
4849         int pipe = crtc->pipe;
4850
4851         if (crtc->config->pch_pfit.enabled) {
4852                 /* Force use of hard-coded filter coefficients
4853                  * as some pre-programmed values are broken,
4854                  * e.g. x201.
4855                  */
4856                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4857                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4858                                                  PF_PIPE_SEL_IVB(pipe));
4859                 else
4860                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4861                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4862                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4863         }
4864 }
4865
4866 void hsw_enable_ips(struct intel_crtc *crtc)
4867 {
4868         struct drm_device *dev = crtc->base.dev;
4869         struct drm_i915_private *dev_priv = to_i915(dev);
4870
4871         if (!crtc->config->ips_enabled)
4872                 return;
4873
4874         /*
4875          * We can only enable IPS after we enable a plane and wait for a vblank
4876          * This function is called from post_plane_update, which is run after
4877          * a vblank wait.
4878          */
4879
4880         assert_plane_enabled(dev_priv, crtc->plane);
4881         if (IS_BROADWELL(dev)) {
4882                 mutex_lock(&dev_priv->rps.hw_lock);
4883                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4884                 mutex_unlock(&dev_priv->rps.hw_lock);
4885                 /* Quoting Art Runyan: "its not safe to expect any particular
4886                  * value in IPS_CTL bit 31 after enabling IPS through the
4887                  * mailbox." Moreover, the mailbox may return a bogus state,
4888                  * so we need to just enable it and continue on.
4889                  */
4890         } else {
4891                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4892                 /* The bit only becomes 1 in the next vblank, so this wait here
4893                  * is essentially intel_wait_for_vblank. If we don't have this
4894                  * and don't wait for vblanks until the end of crtc_enable, then
4895                  * the HW state readout code will complain that the expected
4896                  * IPS_CTL value is not the one we read. */
4897                 if (intel_wait_for_register(dev_priv,
4898                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4899                                             50))
4900                         DRM_ERROR("Timed out waiting for IPS enable\n");
4901         }
4902 }
4903
4904 void hsw_disable_ips(struct intel_crtc *crtc)
4905 {
4906         struct drm_device *dev = crtc->base.dev;
4907         struct drm_i915_private *dev_priv = to_i915(dev);
4908
4909         if (!crtc->config->ips_enabled)
4910                 return;
4911
4912         assert_plane_enabled(dev_priv, crtc->plane);
4913         if (IS_BROADWELL(dev)) {
4914                 mutex_lock(&dev_priv->rps.hw_lock);
4915                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4916                 mutex_unlock(&dev_priv->rps.hw_lock);
4917                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4918                 if (intel_wait_for_register(dev_priv,
4919                                             IPS_CTL, IPS_ENABLE, 0,
4920                                             42))
4921                         DRM_ERROR("Timed out waiting for IPS disable\n");
4922         } else {
4923                 I915_WRITE(IPS_CTL, 0);
4924                 POSTING_READ(IPS_CTL);
4925         }
4926
4927         /* We need to wait for a vblank before we can disable the plane. */
4928         intel_wait_for_vblank(dev, crtc->pipe);
4929 }
4930
4931 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4932 {
4933         if (intel_crtc->overlay) {
4934                 struct drm_device *dev = intel_crtc->base.dev;
4935                 struct drm_i915_private *dev_priv = to_i915(dev);
4936
4937                 mutex_lock(&dev->struct_mutex);
4938                 dev_priv->mm.interruptible = false;
4939                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4940                 dev_priv->mm.interruptible = true;
4941                 mutex_unlock(&dev->struct_mutex);
4942         }
4943
4944         /* Let userspace switch the overlay on again. In most cases userspace
4945          * has to recompute where to put it anyway.
4946          */
4947 }
4948
4949 /**
4950  * intel_post_enable_primary - Perform operations after enabling primary plane
4951  * @crtc: the CRTC whose primary plane was just enabled
4952  *
4953  * Performs potentially sleeping operations that must be done after the primary
4954  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4955  * called due to an explicit primary plane update, or due to an implicit
4956  * re-enable that is caused when a sprite plane is updated to no longer
4957  * completely hide the primary plane.
4958  */
4959 static void
4960 intel_post_enable_primary(struct drm_crtc *crtc)
4961 {
4962         struct drm_device *dev = crtc->dev;
4963         struct drm_i915_private *dev_priv = to_i915(dev);
4964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965         int pipe = intel_crtc->pipe;
4966
4967         /*
4968          * FIXME IPS should be fine as long as one plane is
4969          * enabled, but in practice it seems to have problems
4970          * when going from primary only to sprite only and vice
4971          * versa.
4972          */
4973         hsw_enable_ips(intel_crtc);
4974
4975         /*
4976          * Gen2 reports pipe underruns whenever all planes are disabled.
4977          * So don't enable underrun reporting before at least some planes
4978          * are enabled.
4979          * FIXME: Need to fix the logic to work when we turn off all planes
4980          * but leave the pipe running.
4981          */
4982         if (IS_GEN2(dev))
4983                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4984
4985         /* Underruns don't always raise interrupts, so check manually. */
4986         intel_check_cpu_fifo_underruns(dev_priv);
4987         intel_check_pch_fifo_underruns(dev_priv);
4988 }
4989
4990 /* FIXME move all this to pre_plane_update() with proper state tracking */
4991 static void
4992 intel_pre_disable_primary(struct drm_crtc *crtc)
4993 {
4994         struct drm_device *dev = crtc->dev;
4995         struct drm_i915_private *dev_priv = to_i915(dev);
4996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997         int pipe = intel_crtc->pipe;
4998
4999         /*
5000          * Gen2 reports pipe underruns whenever all planes are disabled.
5001          * So diasble underrun reporting before all the planes get disabled.
5002          * FIXME: Need to fix the logic to work when we turn off all planes
5003          * but leave the pipe running.
5004          */
5005         if (IS_GEN2(dev))
5006                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5007
5008         /*
5009          * FIXME IPS should be fine as long as one plane is
5010          * enabled, but in practice it seems to have problems
5011          * when going from primary only to sprite only and vice
5012          * versa.
5013          */
5014         hsw_disable_ips(intel_crtc);
5015 }
5016
5017 /* FIXME get rid of this and use pre_plane_update */
5018 static void
5019 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5020 {
5021         struct drm_device *dev = crtc->dev;
5022         struct drm_i915_private *dev_priv = to_i915(dev);
5023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5024         int pipe = intel_crtc->pipe;
5025
5026         intel_pre_disable_primary(crtc);
5027
5028         /*
5029          * Vblank time updates from the shadow to live plane control register
5030          * are blocked if the memory self-refresh mode is active at that
5031          * moment. So to make sure the plane gets truly disabled, disable
5032          * first the self-refresh mode. The self-refresh enable bit in turn
5033          * will be checked/applied by the HW only at the next frame start
5034          * event which is after the vblank start event, so we need to have a
5035          * wait-for-vblank between disabling the plane and the pipe.
5036          */
5037         if (HAS_GMCH_DISPLAY(dev)) {
5038                 intel_set_memory_cxsr(dev_priv, false);
5039                 dev_priv->wm.vlv.cxsr = false;
5040                 intel_wait_for_vblank(dev, pipe);
5041         }
5042 }
5043
5044 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5045 {
5046         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5047         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5048         struct intel_crtc_state *pipe_config =
5049                 to_intel_crtc_state(crtc->base.state);
5050         struct drm_plane *primary = crtc->base.primary;
5051         struct drm_plane_state *old_pri_state =
5052                 drm_atomic_get_existing_plane_state(old_state, primary);
5053
5054         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5055
5056         crtc->wm.cxsr_allowed = true;
5057
5058         if (pipe_config->update_wm_post && pipe_config->base.active)
5059                 intel_update_watermarks(&crtc->base);
5060
5061         if (old_pri_state) {
5062                 struct intel_plane_state *primary_state =
5063                         to_intel_plane_state(primary->state);
5064                 struct intel_plane_state *old_primary_state =
5065                         to_intel_plane_state(old_pri_state);
5066
5067                 intel_fbc_post_update(crtc);
5068
5069                 if (primary_state->base.visible &&
5070                     (needs_modeset(&pipe_config->base) ||
5071                      !old_primary_state->base.visible))
5072                         intel_post_enable_primary(&crtc->base);
5073         }
5074 }
5075
5076 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5077 {
5078         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5079         struct drm_device *dev = crtc->base.dev;
5080         struct drm_i915_private *dev_priv = to_i915(dev);
5081         struct intel_crtc_state *pipe_config =
5082                 to_intel_crtc_state(crtc->base.state);
5083         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5084         struct drm_plane *primary = crtc->base.primary;
5085         struct drm_plane_state *old_pri_state =
5086                 drm_atomic_get_existing_plane_state(old_state, primary);
5087         bool modeset = needs_modeset(&pipe_config->base);
5088
5089         if (old_pri_state) {
5090                 struct intel_plane_state *primary_state =
5091                         to_intel_plane_state(primary->state);
5092                 struct intel_plane_state *old_primary_state =
5093                         to_intel_plane_state(old_pri_state);
5094
5095                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5096
5097                 if (old_primary_state->base.visible &&
5098                     (modeset || !primary_state->base.visible))
5099                         intel_pre_disable_primary(&crtc->base);
5100         }
5101
5102         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5103                 crtc->wm.cxsr_allowed = false;
5104
5105                 /*
5106                  * Vblank time updates from the shadow to live plane control register
5107                  * are blocked if the memory self-refresh mode is active at that
5108                  * moment. So to make sure the plane gets truly disabled, disable
5109                  * first the self-refresh mode. The self-refresh enable bit in turn
5110                  * will be checked/applied by the HW only at the next frame start
5111                  * event which is after the vblank start event, so we need to have a
5112                  * wait-for-vblank between disabling the plane and the pipe.
5113                  */
5114                 if (old_crtc_state->base.active) {
5115                         intel_set_memory_cxsr(dev_priv, false);
5116                         dev_priv->wm.vlv.cxsr = false;
5117                         intel_wait_for_vblank(dev, crtc->pipe);
5118                 }
5119         }
5120
5121         /*
5122          * IVB workaround: must disable low power watermarks for at least
5123          * one frame before enabling scaling.  LP watermarks can be re-enabled
5124          * when scaling is disabled.
5125          *
5126          * WaCxSRDisabledForSpriteScaling:ivb
5127          */
5128         if (pipe_config->disable_lp_wm) {
5129                 ilk_disable_lp_wm(dev);
5130                 intel_wait_for_vblank(dev, crtc->pipe);
5131         }
5132
5133         /*
5134          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5135          * watermark programming here.
5136          */
5137         if (needs_modeset(&pipe_config->base))
5138                 return;
5139
5140         /*
5141          * For platforms that support atomic watermarks, program the
5142          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5143          * will be the intermediate values that are safe for both pre- and
5144          * post- vblank; when vblank happens, the 'active' values will be set
5145          * to the final 'target' values and we'll do this again to get the
5146          * optimal watermarks.  For gen9+ platforms, the values we program here
5147          * will be the final target values which will get automatically latched
5148          * at vblank time; no further programming will be necessary.
5149          *
5150          * If a platform hasn't been transitioned to atomic watermarks yet,
5151          * we'll continue to update watermarks the old way, if flags tell
5152          * us to.
5153          */
5154         if (dev_priv->display.initial_watermarks != NULL)
5155                 dev_priv->display.initial_watermarks(pipe_config);
5156         else if (pipe_config->update_wm_pre)
5157                 intel_update_watermarks(&crtc->base);
5158 }
5159
5160 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5161 {
5162         struct drm_device *dev = crtc->dev;
5163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5164         struct drm_plane *p;
5165         int pipe = intel_crtc->pipe;
5166
5167         intel_crtc_dpms_overlay_disable(intel_crtc);
5168
5169         drm_for_each_plane_mask(p, dev, plane_mask)
5170                 to_intel_plane(p)->disable_plane(p, crtc);
5171
5172         /*
5173          * FIXME: Once we grow proper nuclear flip support out of this we need
5174          * to compute the mask of flip planes precisely. For the time being
5175          * consider this a flip to a NULL plane.
5176          */
5177         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5178 }
5179
5180 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5181                                           struct intel_crtc_state *crtc_state,
5182                                           struct drm_atomic_state *old_state)
5183 {
5184         struct drm_connector_state *old_conn_state;
5185         struct drm_connector *conn;
5186         int i;
5187
5188         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5189                 struct drm_connector_state *conn_state = conn->state;
5190                 struct intel_encoder *encoder =
5191                         to_intel_encoder(conn_state->best_encoder);
5192
5193                 if (conn_state->crtc != crtc)
5194                         continue;
5195
5196                 if (encoder->pre_pll_enable)
5197                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5198         }
5199 }
5200
5201 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5202                                       struct intel_crtc_state *crtc_state,
5203                                       struct drm_atomic_state *old_state)
5204 {
5205         struct drm_connector_state *old_conn_state;
5206         struct drm_connector *conn;
5207         int i;
5208
5209         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5210                 struct drm_connector_state *conn_state = conn->state;
5211                 struct intel_encoder *encoder =
5212                         to_intel_encoder(conn_state->best_encoder);
5213
5214                 if (conn_state->crtc != crtc)
5215                         continue;
5216
5217                 if (encoder->pre_enable)
5218                         encoder->pre_enable(encoder, crtc_state, conn_state);
5219         }
5220 }
5221
5222 static void intel_encoders_enable(struct drm_crtc *crtc,
5223                                   struct intel_crtc_state *crtc_state,
5224                                   struct drm_atomic_state *old_state)
5225 {
5226         struct drm_connector_state *old_conn_state;
5227         struct drm_connector *conn;
5228         int i;
5229
5230         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5231                 struct drm_connector_state *conn_state = conn->state;
5232                 struct intel_encoder *encoder =
5233                         to_intel_encoder(conn_state->best_encoder);
5234
5235                 if (conn_state->crtc != crtc)
5236                         continue;
5237
5238                 encoder->enable(encoder, crtc_state, conn_state);
5239                 intel_opregion_notify_encoder(encoder, true);
5240         }
5241 }
5242
5243 static void intel_encoders_disable(struct drm_crtc *crtc,
5244                                    struct intel_crtc_state *old_crtc_state,
5245                                    struct drm_atomic_state *old_state)
5246 {
5247         struct drm_connector_state *old_conn_state;
5248         struct drm_connector *conn;
5249         int i;
5250
5251         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5252                 struct intel_encoder *encoder =
5253                         to_intel_encoder(old_conn_state->best_encoder);
5254
5255                 if (old_conn_state->crtc != crtc)
5256                         continue;
5257
5258                 intel_opregion_notify_encoder(encoder, false);
5259                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5260         }
5261 }
5262
5263 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5264                                         struct intel_crtc_state *old_crtc_state,
5265                                         struct drm_atomic_state *old_state)
5266 {
5267         struct drm_connector_state *old_conn_state;
5268         struct drm_connector *conn;
5269         int i;
5270
5271         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5272                 struct intel_encoder *encoder =
5273                         to_intel_encoder(old_conn_state->best_encoder);
5274
5275                 if (old_conn_state->crtc != crtc)
5276                         continue;
5277
5278                 if (encoder->post_disable)
5279                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5280         }
5281 }
5282
5283 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5284                                             struct intel_crtc_state *old_crtc_state,
5285                                             struct drm_atomic_state *old_state)
5286 {
5287         struct drm_connector_state *old_conn_state;
5288         struct drm_connector *conn;
5289         int i;
5290
5291         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5292                 struct intel_encoder *encoder =
5293                         to_intel_encoder(old_conn_state->best_encoder);
5294
5295                 if (old_conn_state->crtc != crtc)
5296                         continue;
5297
5298                 if (encoder->post_pll_disable)
5299                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5300         }
5301 }
5302
5303 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5304                                  struct drm_atomic_state *old_state)
5305 {
5306         struct drm_crtc *crtc = pipe_config->base.crtc;
5307         struct drm_device *dev = crtc->dev;
5308         struct drm_i915_private *dev_priv = to_i915(dev);
5309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310         int pipe = intel_crtc->pipe;
5311
5312         if (WARN_ON(intel_crtc->active))
5313                 return;
5314
5315         /*
5316          * Sometimes spurious CPU pipe underruns happen during FDI
5317          * training, at least with VGA+HDMI cloning. Suppress them.
5318          *
5319          * On ILK we get an occasional spurious CPU pipe underruns
5320          * between eDP port A enable and vdd enable. Also PCH port
5321          * enable seems to result in the occasional CPU pipe underrun.
5322          *
5323          * Spurious PCH underruns also occur during PCH enabling.
5324          */
5325         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5326                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5327         if (intel_crtc->config->has_pch_encoder)
5328                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5329
5330         if (intel_crtc->config->has_pch_encoder)
5331                 intel_prepare_shared_dpll(intel_crtc);
5332
5333         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5334                 intel_dp_set_m_n(intel_crtc, M1_N1);
5335
5336         intel_set_pipe_timings(intel_crtc);
5337         intel_set_pipe_src_size(intel_crtc);
5338
5339         if (intel_crtc->config->has_pch_encoder) {
5340                 intel_cpu_transcoder_set_m_n(intel_crtc,
5341                                      &intel_crtc->config->fdi_m_n, NULL);
5342         }
5343
5344         ironlake_set_pipeconf(crtc);
5345
5346         intel_crtc->active = true;
5347
5348         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5349
5350         if (intel_crtc->config->has_pch_encoder) {
5351                 /* Note: FDI PLL enabling _must_ be done before we enable the
5352                  * cpu pipes, hence this is separate from all the other fdi/pch
5353                  * enabling. */
5354                 ironlake_fdi_pll_enable(intel_crtc);
5355         } else {
5356                 assert_fdi_tx_disabled(dev_priv, pipe);
5357                 assert_fdi_rx_disabled(dev_priv, pipe);
5358         }
5359
5360         ironlake_pfit_enable(intel_crtc);
5361
5362         /*
5363          * On ILK+ LUT must be loaded before the pipe is running but with
5364          * clocks enabled
5365          */
5366         intel_color_load_luts(&pipe_config->base);
5367
5368         if (dev_priv->display.initial_watermarks != NULL)
5369                 dev_priv->display.initial_watermarks(intel_crtc->config);
5370         intel_enable_pipe(intel_crtc);
5371
5372         if (intel_crtc->config->has_pch_encoder)
5373                 ironlake_pch_enable(crtc);
5374
5375         assert_vblank_disabled(crtc);
5376         drm_crtc_vblank_on(crtc);
5377
5378         intel_encoders_enable(crtc, pipe_config, old_state);
5379
5380         if (HAS_PCH_CPT(dev))
5381                 cpt_verify_modeset(dev, intel_crtc->pipe);
5382
5383         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5384         if (intel_crtc->config->has_pch_encoder)
5385                 intel_wait_for_vblank(dev, pipe);
5386         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5387         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5388 }
5389
5390 /* IPS only exists on ULT machines and is tied to pipe A. */
5391 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5392 {
5393         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5394 }
5395
5396 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5397                                 struct drm_atomic_state *old_state)
5398 {
5399         struct drm_crtc *crtc = pipe_config->base.crtc;
5400         struct drm_device *dev = crtc->dev;
5401         struct drm_i915_private *dev_priv = to_i915(dev);
5402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5403         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5404         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5405
5406         if (WARN_ON(intel_crtc->active))
5407                 return;
5408
5409         if (intel_crtc->config->has_pch_encoder)
5410                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5411                                                       false);
5412
5413         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5414
5415         if (intel_crtc->config->shared_dpll)
5416                 intel_enable_shared_dpll(intel_crtc);
5417
5418         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5419                 intel_dp_set_m_n(intel_crtc, M1_N1);
5420
5421         if (!transcoder_is_dsi(cpu_transcoder))
5422                 intel_set_pipe_timings(intel_crtc);
5423
5424         intel_set_pipe_src_size(intel_crtc);
5425
5426         if (cpu_transcoder != TRANSCODER_EDP &&
5427             !transcoder_is_dsi(cpu_transcoder)) {
5428                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5429                            intel_crtc->config->pixel_multiplier - 1);
5430         }
5431
5432         if (intel_crtc->config->has_pch_encoder) {
5433                 intel_cpu_transcoder_set_m_n(intel_crtc,
5434                                      &intel_crtc->config->fdi_m_n, NULL);
5435         }
5436
5437         if (!transcoder_is_dsi(cpu_transcoder))
5438                 haswell_set_pipeconf(crtc);
5439
5440         haswell_set_pipemisc(crtc);
5441
5442         intel_color_set_csc(&pipe_config->base);
5443
5444         intel_crtc->active = true;
5445
5446         if (intel_crtc->config->has_pch_encoder)
5447                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5448         else
5449                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5450
5451         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5452
5453         if (intel_crtc->config->has_pch_encoder)
5454                 dev_priv->display.fdi_link_train(crtc);
5455
5456         if (!transcoder_is_dsi(cpu_transcoder))
5457                 intel_ddi_enable_pipe_clock(intel_crtc);
5458
5459         if (INTEL_INFO(dev)->gen >= 9)
5460                 skylake_pfit_enable(intel_crtc);
5461         else
5462                 ironlake_pfit_enable(intel_crtc);
5463
5464         /*
5465          * On ILK+ LUT must be loaded before the pipe is running but with
5466          * clocks enabled
5467          */
5468         intel_color_load_luts(&pipe_config->base);
5469
5470         intel_ddi_set_pipe_settings(crtc);
5471         if (!transcoder_is_dsi(cpu_transcoder))
5472                 intel_ddi_enable_transcoder_func(crtc);
5473
5474         if (dev_priv->display.initial_watermarks != NULL)
5475                 dev_priv->display.initial_watermarks(pipe_config);
5476         else
5477                 intel_update_watermarks(crtc);
5478
5479         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5480         if (!transcoder_is_dsi(cpu_transcoder))
5481                 intel_enable_pipe(intel_crtc);
5482
5483         if (intel_crtc->config->has_pch_encoder)
5484                 lpt_pch_enable(crtc);
5485
5486         if (intel_crtc->config->dp_encoder_is_mst)
5487                 intel_ddi_set_vc_payload_alloc(crtc, true);
5488
5489         assert_vblank_disabled(crtc);
5490         drm_crtc_vblank_on(crtc);
5491
5492         intel_encoders_enable(crtc, pipe_config, old_state);
5493
5494         if (intel_crtc->config->has_pch_encoder) {
5495                 intel_wait_for_vblank(dev, pipe);
5496                 intel_wait_for_vblank(dev, pipe);
5497                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5498                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5499                                                       true);
5500         }
5501
5502         /* If we change the relative order between pipe/planes enabling, we need
5503          * to change the workaround. */
5504         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5505         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5506                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5507                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5508         }
5509 }
5510
5511 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5512 {
5513         struct drm_device *dev = crtc->base.dev;
5514         struct drm_i915_private *dev_priv = to_i915(dev);
5515         int pipe = crtc->pipe;
5516
5517         /* To avoid upsetting the power well on haswell only disable the pfit if
5518          * it's in use. The hw state code will make sure we get this right. */
5519         if (force || crtc->config->pch_pfit.enabled) {
5520                 I915_WRITE(PF_CTL(pipe), 0);
5521                 I915_WRITE(PF_WIN_POS(pipe), 0);
5522                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5523         }
5524 }
5525
5526 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5527                                   struct drm_atomic_state *old_state)
5528 {
5529         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5530         struct drm_device *dev = crtc->dev;
5531         struct drm_i915_private *dev_priv = to_i915(dev);
5532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5533         int pipe = intel_crtc->pipe;
5534
5535         /*
5536          * Sometimes spurious CPU pipe underruns happen when the
5537          * pipe is already disabled, but FDI RX/TX is still enabled.
5538          * Happens at least with VGA+HDMI cloning. Suppress them.
5539          */
5540         if (intel_crtc->config->has_pch_encoder) {
5541                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5542                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5543         }
5544
5545         intel_encoders_disable(crtc, old_crtc_state, old_state);
5546
5547         drm_crtc_vblank_off(crtc);
5548         assert_vblank_disabled(crtc);
5549
5550         intel_disable_pipe(intel_crtc);
5551
5552         ironlake_pfit_disable(intel_crtc, false);
5553
5554         if (intel_crtc->config->has_pch_encoder)
5555                 ironlake_fdi_disable(crtc);
5556
5557         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5558
5559         if (intel_crtc->config->has_pch_encoder) {
5560                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5561
5562                 if (HAS_PCH_CPT(dev)) {
5563                         i915_reg_t reg;
5564                         u32 temp;
5565
5566                         /* disable TRANS_DP_CTL */
5567                         reg = TRANS_DP_CTL(pipe);
5568                         temp = I915_READ(reg);
5569                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5570                                   TRANS_DP_PORT_SEL_MASK);
5571                         temp |= TRANS_DP_PORT_SEL_NONE;
5572                         I915_WRITE(reg, temp);
5573
5574                         /* disable DPLL_SEL */
5575                         temp = I915_READ(PCH_DPLL_SEL);
5576                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5577                         I915_WRITE(PCH_DPLL_SEL, temp);
5578                 }
5579
5580                 ironlake_fdi_pll_disable(intel_crtc);
5581         }
5582
5583         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5584         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5585 }
5586
5587 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5588                                  struct drm_atomic_state *old_state)
5589 {
5590         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5591         struct drm_device *dev = crtc->dev;
5592         struct drm_i915_private *dev_priv = to_i915(dev);
5593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5594         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5595
5596         if (intel_crtc->config->has_pch_encoder)
5597                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5598                                                       false);
5599
5600         intel_encoders_disable(crtc, old_crtc_state, old_state);
5601
5602         drm_crtc_vblank_off(crtc);
5603         assert_vblank_disabled(crtc);
5604
5605         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5606         if (!transcoder_is_dsi(cpu_transcoder))
5607                 intel_disable_pipe(intel_crtc);
5608
5609         if (intel_crtc->config->dp_encoder_is_mst)
5610                 intel_ddi_set_vc_payload_alloc(crtc, false);
5611
5612         if (!transcoder_is_dsi(cpu_transcoder))
5613                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5614
5615         if (INTEL_INFO(dev)->gen >= 9)
5616                 skylake_scaler_disable(intel_crtc);
5617         else
5618                 ironlake_pfit_disable(intel_crtc, false);
5619
5620         if (!transcoder_is_dsi(cpu_transcoder))
5621                 intel_ddi_disable_pipe_clock(intel_crtc);
5622
5623         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5624
5625         if (old_crtc_state->has_pch_encoder)
5626                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5627                                                       true);
5628 }
5629
5630 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5631 {
5632         struct drm_device *dev = crtc->base.dev;
5633         struct drm_i915_private *dev_priv = to_i915(dev);
5634         struct intel_crtc_state *pipe_config = crtc->config;
5635
5636         if (!pipe_config->gmch_pfit.control)
5637                 return;
5638
5639         /*
5640          * The panel fitter should only be adjusted whilst the pipe is disabled,
5641          * according to register description and PRM.
5642          */
5643         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5644         assert_pipe_disabled(dev_priv, crtc->pipe);
5645
5646         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5647         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5648
5649         /* Border color in case we don't scale up to the full screen. Black by
5650          * default, change to something else for debugging. */
5651         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5652 }
5653
5654 static enum intel_display_power_domain port_to_power_domain(enum port port)
5655 {
5656         switch (port) {
5657         case PORT_A:
5658                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5659         case PORT_B:
5660                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5661         case PORT_C:
5662                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5663         case PORT_D:
5664                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5665         case PORT_E:
5666                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5667         default:
5668                 MISSING_CASE(port);
5669                 return POWER_DOMAIN_PORT_OTHER;
5670         }
5671 }
5672
5673 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5674 {
5675         switch (port) {
5676         case PORT_A:
5677                 return POWER_DOMAIN_AUX_A;
5678         case PORT_B:
5679                 return POWER_DOMAIN_AUX_B;
5680         case PORT_C:
5681                 return POWER_DOMAIN_AUX_C;
5682         case PORT_D:
5683                 return POWER_DOMAIN_AUX_D;
5684         case PORT_E:
5685                 /* FIXME: Check VBT for actual wiring of PORT E */
5686                 return POWER_DOMAIN_AUX_D;
5687         default:
5688                 MISSING_CASE(port);
5689                 return POWER_DOMAIN_AUX_A;
5690         }
5691 }
5692
5693 enum intel_display_power_domain
5694 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5695 {
5696         struct drm_device *dev = intel_encoder->base.dev;
5697         struct intel_digital_port *intel_dig_port;
5698
5699         switch (intel_encoder->type) {
5700         case INTEL_OUTPUT_UNKNOWN:
5701                 /* Only DDI platforms should ever use this output type */
5702                 WARN_ON_ONCE(!HAS_DDI(dev));
5703         case INTEL_OUTPUT_DP:
5704         case INTEL_OUTPUT_HDMI:
5705         case INTEL_OUTPUT_EDP:
5706                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5707                 return port_to_power_domain(intel_dig_port->port);
5708         case INTEL_OUTPUT_DP_MST:
5709                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5710                 return port_to_power_domain(intel_dig_port->port);
5711         case INTEL_OUTPUT_ANALOG:
5712                 return POWER_DOMAIN_PORT_CRT;
5713         case INTEL_OUTPUT_DSI:
5714                 return POWER_DOMAIN_PORT_DSI;
5715         default:
5716                 return POWER_DOMAIN_PORT_OTHER;
5717         }
5718 }
5719
5720 enum intel_display_power_domain
5721 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5722 {
5723         struct drm_device *dev = intel_encoder->base.dev;
5724         struct intel_digital_port *intel_dig_port;
5725
5726         switch (intel_encoder->type) {
5727         case INTEL_OUTPUT_UNKNOWN:
5728         case INTEL_OUTPUT_HDMI:
5729                 /*
5730                  * Only DDI platforms should ever use these output types.
5731                  * We can get here after the HDMI detect code has already set
5732                  * the type of the shared encoder. Since we can't be sure
5733                  * what's the status of the given connectors, play safe and
5734                  * run the DP detection too.
5735                  */
5736                 WARN_ON_ONCE(!HAS_DDI(dev));
5737         case INTEL_OUTPUT_DP:
5738         case INTEL_OUTPUT_EDP:
5739                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5740                 return port_to_aux_power_domain(intel_dig_port->port);
5741         case INTEL_OUTPUT_DP_MST:
5742                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5743                 return port_to_aux_power_domain(intel_dig_port->port);
5744         default:
5745                 MISSING_CASE(intel_encoder->type);
5746                 return POWER_DOMAIN_AUX_A;
5747         }
5748 }
5749
5750 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5751                                             struct intel_crtc_state *crtc_state)
5752 {
5753         struct drm_device *dev = crtc->dev;
5754         struct drm_encoder *encoder;
5755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5756         enum pipe pipe = intel_crtc->pipe;
5757         unsigned long mask;
5758         enum transcoder transcoder = crtc_state->cpu_transcoder;
5759
5760         if (!crtc_state->base.active)
5761                 return 0;
5762
5763         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5764         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5765         if (crtc_state->pch_pfit.enabled ||
5766             crtc_state->pch_pfit.force_thru)
5767                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5768
5769         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5770                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5771
5772                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5773         }
5774
5775         if (crtc_state->shared_dpll)
5776                 mask |= BIT(POWER_DOMAIN_PLLS);
5777
5778         return mask;
5779 }
5780
5781 static unsigned long
5782 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5783                                struct intel_crtc_state *crtc_state)
5784 {
5785         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5787         enum intel_display_power_domain domain;
5788         unsigned long domains, new_domains, old_domains;
5789
5790         old_domains = intel_crtc->enabled_power_domains;
5791         intel_crtc->enabled_power_domains = new_domains =
5792                 get_crtc_power_domains(crtc, crtc_state);
5793
5794         domains = new_domains & ~old_domains;
5795
5796         for_each_power_domain(domain, domains)
5797                 intel_display_power_get(dev_priv, domain);
5798
5799         return old_domains & ~new_domains;
5800 }
5801
5802 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5803                                       unsigned long domains)
5804 {
5805         enum intel_display_power_domain domain;
5806
5807         for_each_power_domain(domain, domains)
5808                 intel_display_power_put(dev_priv, domain);
5809 }
5810
5811 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5812 {
5813         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5814
5815         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5816             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5817                 return max_cdclk_freq;
5818         else if (IS_CHERRYVIEW(dev_priv))
5819                 return max_cdclk_freq*95/100;
5820         else if (INTEL_INFO(dev_priv)->gen < 4)
5821                 return 2*max_cdclk_freq*90/100;
5822         else
5823                 return max_cdclk_freq*90/100;
5824 }
5825
5826 static int skl_calc_cdclk(int max_pixclk, int vco);
5827
5828 static void intel_update_max_cdclk(struct drm_device *dev)
5829 {
5830         struct drm_i915_private *dev_priv = to_i915(dev);
5831
5832         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5833                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5834                 int max_cdclk, vco;
5835
5836                 vco = dev_priv->skl_preferred_vco_freq;
5837                 WARN_ON(vco != 8100000 && vco != 8640000);
5838
5839                 /*
5840                  * Use the lower (vco 8640) cdclk values as a
5841                  * first guess. skl_calc_cdclk() will correct it
5842                  * if the preferred vco is 8100 instead.
5843                  */
5844                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5845                         max_cdclk = 617143;
5846                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5847                         max_cdclk = 540000;
5848                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5849                         max_cdclk = 432000;
5850                 else
5851                         max_cdclk = 308571;
5852
5853                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5854         } else if (IS_BROXTON(dev)) {
5855                 dev_priv->max_cdclk_freq = 624000;
5856         } else if (IS_BROADWELL(dev))  {
5857                 /*
5858                  * FIXME with extra cooling we can allow
5859                  * 540 MHz for ULX and 675 Mhz for ULT.
5860                  * How can we know if extra cooling is
5861                  * available? PCI ID, VTB, something else?
5862                  */
5863                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5864                         dev_priv->max_cdclk_freq = 450000;
5865                 else if (IS_BDW_ULX(dev))
5866                         dev_priv->max_cdclk_freq = 450000;
5867                 else if (IS_BDW_ULT(dev))
5868                         dev_priv->max_cdclk_freq = 540000;
5869                 else
5870                         dev_priv->max_cdclk_freq = 675000;
5871         } else if (IS_CHERRYVIEW(dev)) {
5872                 dev_priv->max_cdclk_freq = 320000;
5873         } else if (IS_VALLEYVIEW(dev)) {
5874                 dev_priv->max_cdclk_freq = 400000;
5875         } else {
5876                 /* otherwise assume cdclk is fixed */
5877                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5878         }
5879
5880         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5881
5882         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5883                          dev_priv->max_cdclk_freq);
5884
5885         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5886                          dev_priv->max_dotclk_freq);
5887 }
5888
5889 static void intel_update_cdclk(struct drm_device *dev)
5890 {
5891         struct drm_i915_private *dev_priv = to_i915(dev);
5892
5893         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5894
5895         if (INTEL_GEN(dev_priv) >= 9)
5896                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5897                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5898                                  dev_priv->cdclk_pll.ref);
5899         else
5900                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5901                                  dev_priv->cdclk_freq);
5902
5903         /*
5904          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5905          * Programmng [sic] note: bit[9:2] should be programmed to the number
5906          * of cdclk that generates 4MHz reference clock freq which is used to
5907          * generate GMBus clock. This will vary with the cdclk freq.
5908          */
5909         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5910                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5911 }
5912
5913 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5914 static int skl_cdclk_decimal(int cdclk)
5915 {
5916         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5917 }
5918
5919 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5920 {
5921         int ratio;
5922
5923         if (cdclk == dev_priv->cdclk_pll.ref)
5924                 return 0;
5925
5926         switch (cdclk) {
5927         default:
5928                 MISSING_CASE(cdclk);
5929         case 144000:
5930         case 288000:
5931         case 384000:
5932         case 576000:
5933                 ratio = 60;
5934                 break;
5935         case 624000:
5936                 ratio = 65;
5937                 break;
5938         }
5939
5940         return dev_priv->cdclk_pll.ref * ratio;
5941 }
5942
5943 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5944 {
5945         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5946
5947         /* Timeout 200us */
5948         if (intel_wait_for_register(dev_priv,
5949                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5950                                     1))
5951                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5952
5953         dev_priv->cdclk_pll.vco = 0;
5954 }
5955
5956 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5957 {
5958         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5959         u32 val;
5960
5961         val = I915_READ(BXT_DE_PLL_CTL);
5962         val &= ~BXT_DE_PLL_RATIO_MASK;
5963         val |= BXT_DE_PLL_RATIO(ratio);
5964         I915_WRITE(BXT_DE_PLL_CTL, val);
5965
5966         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5967
5968         /* Timeout 200us */
5969         if (intel_wait_for_register(dev_priv,
5970                                     BXT_DE_PLL_ENABLE,
5971                                     BXT_DE_PLL_LOCK,
5972                                     BXT_DE_PLL_LOCK,
5973                                     1))
5974                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5975
5976         dev_priv->cdclk_pll.vco = vco;
5977 }
5978
5979 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5980 {
5981         u32 val, divider;
5982         int vco, ret;
5983
5984         vco = bxt_de_pll_vco(dev_priv, cdclk);
5985
5986         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5987
5988         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5989         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5990         case 8:
5991                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5992                 break;
5993         case 4:
5994                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5995                 break;
5996         case 3:
5997                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5998                 break;
5999         case 2:
6000                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6001                 break;
6002         default:
6003                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6004                 WARN_ON(vco != 0);
6005
6006                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6007                 break;
6008         }
6009
6010         /* Inform power controller of upcoming frequency change */
6011         mutex_lock(&dev_priv->rps.hw_lock);
6012         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6013                                       0x80000000);
6014         mutex_unlock(&dev_priv->rps.hw_lock);
6015
6016         if (ret) {
6017                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6018                           ret, cdclk);
6019                 return;
6020         }
6021
6022         if (dev_priv->cdclk_pll.vco != 0 &&
6023             dev_priv->cdclk_pll.vco != vco)
6024                 bxt_de_pll_disable(dev_priv);
6025
6026         if (dev_priv->cdclk_pll.vco != vco)
6027                 bxt_de_pll_enable(dev_priv, vco);
6028
6029         val = divider | skl_cdclk_decimal(cdclk);
6030         /*
6031          * FIXME if only the cd2x divider needs changing, it could be done
6032          * without shutting off the pipe (if only one pipe is active).
6033          */
6034         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6035         /*
6036          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6037          * enable otherwise.
6038          */
6039         if (cdclk >= 500000)
6040                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6041         I915_WRITE(CDCLK_CTL, val);
6042
6043         mutex_lock(&dev_priv->rps.hw_lock);
6044         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6045                                       DIV_ROUND_UP(cdclk, 25000));
6046         mutex_unlock(&dev_priv->rps.hw_lock);
6047
6048         if (ret) {
6049                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6050                           ret, cdclk);
6051                 return;
6052         }
6053
6054         intel_update_cdclk(&dev_priv->drm);
6055 }
6056
6057 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6058 {
6059         u32 cdctl, expected;
6060
6061         intel_update_cdclk(&dev_priv->drm);
6062
6063         if (dev_priv->cdclk_pll.vco == 0 ||
6064             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6065                 goto sanitize;
6066
6067         /* DPLL okay; verify the cdclock
6068          *
6069          * Some BIOS versions leave an incorrect decimal frequency value and
6070          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6071          * so sanitize this register.
6072          */
6073         cdctl = I915_READ(CDCLK_CTL);
6074         /*
6075          * Let's ignore the pipe field, since BIOS could have configured the
6076          * dividers both synching to an active pipe, or asynchronously
6077          * (PIPE_NONE).
6078          */
6079         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6080
6081         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6082                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6083         /*
6084          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6085          * enable otherwise.
6086          */
6087         if (dev_priv->cdclk_freq >= 500000)
6088                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6089
6090         if (cdctl == expected)
6091                 /* All well; nothing to sanitize */
6092                 return;
6093
6094 sanitize:
6095         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6096
6097         /* force cdclk programming */
6098         dev_priv->cdclk_freq = 0;
6099
6100         /* force full PLL disable + enable */
6101         dev_priv->cdclk_pll.vco = -1;
6102 }
6103
6104 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6105 {
6106         bxt_sanitize_cdclk(dev_priv);
6107
6108         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6109                 return;
6110
6111         /*
6112          * FIXME:
6113          * - The initial CDCLK needs to be read from VBT.
6114          *   Need to make this change after VBT has changes for BXT.
6115          */
6116         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6117 }
6118
6119 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6120 {
6121         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6122 }
6123
6124 static int skl_calc_cdclk(int max_pixclk, int vco)
6125 {
6126         if (vco == 8640000) {
6127                 if (max_pixclk > 540000)
6128                         return 617143;
6129                 else if (max_pixclk > 432000)
6130                         return 540000;
6131                 else if (max_pixclk > 308571)
6132                         return 432000;
6133                 else
6134                         return 308571;
6135         } else {
6136                 if (max_pixclk > 540000)
6137                         return 675000;
6138                 else if (max_pixclk > 450000)
6139                         return 540000;
6140                 else if (max_pixclk > 337500)
6141                         return 450000;
6142                 else
6143                         return 337500;
6144         }
6145 }
6146
6147 static void
6148 skl_dpll0_update(struct drm_i915_private *dev_priv)
6149 {
6150         u32 val;
6151
6152         dev_priv->cdclk_pll.ref = 24000;
6153         dev_priv->cdclk_pll.vco = 0;
6154
6155         val = I915_READ(LCPLL1_CTL);
6156         if ((val & LCPLL_PLL_ENABLE) == 0)
6157                 return;
6158
6159         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6160                 return;
6161
6162         val = I915_READ(DPLL_CTRL1);
6163
6164         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6165                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6166                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6167                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6168                 return;
6169
6170         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6171         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6172         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6173         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6174         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6175                 dev_priv->cdclk_pll.vco = 8100000;
6176                 break;
6177         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6179                 dev_priv->cdclk_pll.vco = 8640000;
6180                 break;
6181         default:
6182                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6183                 break;
6184         }
6185 }
6186
6187 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6188 {
6189         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6190
6191         dev_priv->skl_preferred_vco_freq = vco;
6192
6193         if (changed)
6194                 intel_update_max_cdclk(&dev_priv->drm);
6195 }
6196
6197 static void
6198 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6199 {
6200         int min_cdclk = skl_calc_cdclk(0, vco);
6201         u32 val;
6202
6203         WARN_ON(vco != 8100000 && vco != 8640000);
6204
6205         /* select the minimum CDCLK before enabling DPLL 0 */
6206         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6207         I915_WRITE(CDCLK_CTL, val);
6208         POSTING_READ(CDCLK_CTL);
6209
6210         /*
6211          * We always enable DPLL0 with the lowest link rate possible, but still
6212          * taking into account the VCO required to operate the eDP panel at the
6213          * desired frequency. The usual DP link rates operate with a VCO of
6214          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6215          * The modeset code is responsible for the selection of the exact link
6216          * rate later on, with the constraint of choosing a frequency that
6217          * works with vco.
6218          */
6219         val = I915_READ(DPLL_CTRL1);
6220
6221         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6222                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6223         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6224         if (vco == 8640000)
6225                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6226                                             SKL_DPLL0);
6227         else
6228                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6229                                             SKL_DPLL0);
6230
6231         I915_WRITE(DPLL_CTRL1, val);
6232         POSTING_READ(DPLL_CTRL1);
6233
6234         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6235
6236         if (intel_wait_for_register(dev_priv,
6237                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6238                                     5))
6239                 DRM_ERROR("DPLL0 not locked\n");
6240
6241         dev_priv->cdclk_pll.vco = vco;
6242
6243         /* We'll want to keep using the current vco from now on. */
6244         skl_set_preferred_cdclk_vco(dev_priv, vco);
6245 }
6246
6247 static void
6248 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6249 {
6250         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6251         if (intel_wait_for_register(dev_priv,
6252                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6253                                    1))
6254                 DRM_ERROR("Couldn't disable DPLL0\n");
6255
6256         dev_priv->cdclk_pll.vco = 0;
6257 }
6258
6259 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6260 {
6261         int ret;
6262         u32 val;
6263
6264         /* inform PCU we want to change CDCLK */
6265         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6266         mutex_lock(&dev_priv->rps.hw_lock);
6267         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6268         mutex_unlock(&dev_priv->rps.hw_lock);
6269
6270         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6271 }
6272
6273 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6274 {
6275         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6276 }
6277
6278 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6279 {
6280         struct drm_device *dev = &dev_priv->drm;
6281         u32 freq_select, pcu_ack;
6282
6283         WARN_ON((cdclk == 24000) != (vco == 0));
6284
6285         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6286
6287         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6288                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6289                 return;
6290         }
6291
6292         /* set CDCLK_CTL */
6293         switch (cdclk) {
6294         case 450000:
6295         case 432000:
6296                 freq_select = CDCLK_FREQ_450_432;
6297                 pcu_ack = 1;
6298                 break;
6299         case 540000:
6300                 freq_select = CDCLK_FREQ_540;
6301                 pcu_ack = 2;
6302                 break;
6303         case 308571:
6304         case 337500:
6305         default:
6306                 freq_select = CDCLK_FREQ_337_308;
6307                 pcu_ack = 0;
6308                 break;
6309         case 617143:
6310         case 675000:
6311                 freq_select = CDCLK_FREQ_675_617;
6312                 pcu_ack = 3;
6313                 break;
6314         }
6315
6316         if (dev_priv->cdclk_pll.vco != 0 &&
6317             dev_priv->cdclk_pll.vco != vco)
6318                 skl_dpll0_disable(dev_priv);
6319
6320         if (dev_priv->cdclk_pll.vco != vco)
6321                 skl_dpll0_enable(dev_priv, vco);
6322
6323         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6324         POSTING_READ(CDCLK_CTL);
6325
6326         /* inform PCU of the change */
6327         mutex_lock(&dev_priv->rps.hw_lock);
6328         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6329         mutex_unlock(&dev_priv->rps.hw_lock);
6330
6331         intel_update_cdclk(dev);
6332 }
6333
6334 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6335
6336 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6337 {
6338         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6339 }
6340
6341 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6342 {
6343         int cdclk, vco;
6344
6345         skl_sanitize_cdclk(dev_priv);
6346
6347         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6348                 /*
6349                  * Use the current vco as our initial
6350                  * guess as to what the preferred vco is.
6351                  */
6352                 if (dev_priv->skl_preferred_vco_freq == 0)
6353                         skl_set_preferred_cdclk_vco(dev_priv,
6354                                                     dev_priv->cdclk_pll.vco);
6355                 return;
6356         }
6357
6358         vco = dev_priv->skl_preferred_vco_freq;
6359         if (vco == 0)
6360                 vco = 8100000;
6361         cdclk = skl_calc_cdclk(0, vco);
6362
6363         skl_set_cdclk(dev_priv, cdclk, vco);
6364 }
6365
6366 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6367 {
6368         uint32_t cdctl, expected;
6369
6370         /*
6371          * check if the pre-os intialized the display
6372          * There is SWF18 scratchpad register defined which is set by the
6373          * pre-os which can be used by the OS drivers to check the status
6374          */
6375         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6376                 goto sanitize;
6377
6378         intel_update_cdclk(&dev_priv->drm);
6379         /* Is PLL enabled and locked ? */
6380         if (dev_priv->cdclk_pll.vco == 0 ||
6381             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6382                 goto sanitize;
6383
6384         /* DPLL okay; verify the cdclock
6385          *
6386          * Noticed in some instances that the freq selection is correct but
6387          * decimal part is programmed wrong from BIOS where pre-os does not
6388          * enable display. Verify the same as well.
6389          */
6390         cdctl = I915_READ(CDCLK_CTL);
6391         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6392                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6393         if (cdctl == expected)
6394                 /* All well; nothing to sanitize */
6395                 return;
6396
6397 sanitize:
6398         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6399
6400         /* force cdclk programming */
6401         dev_priv->cdclk_freq = 0;
6402         /* force full PLL disable + enable */
6403         dev_priv->cdclk_pll.vco = -1;
6404 }
6405
6406 /* Adjust CDclk dividers to allow high res or save power if possible */
6407 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6408 {
6409         struct drm_i915_private *dev_priv = to_i915(dev);
6410         u32 val, cmd;
6411
6412         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6413                                         != dev_priv->cdclk_freq);
6414
6415         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6416                 cmd = 2;
6417         else if (cdclk == 266667)
6418                 cmd = 1;
6419         else
6420                 cmd = 0;
6421
6422         mutex_lock(&dev_priv->rps.hw_lock);
6423         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6424         val &= ~DSPFREQGUAR_MASK;
6425         val |= (cmd << DSPFREQGUAR_SHIFT);
6426         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6427         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6428                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6429                      50)) {
6430                 DRM_ERROR("timed out waiting for CDclk change\n");
6431         }
6432         mutex_unlock(&dev_priv->rps.hw_lock);
6433
6434         mutex_lock(&dev_priv->sb_lock);
6435
6436         if (cdclk == 400000) {
6437                 u32 divider;
6438
6439                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6440
6441                 /* adjust cdclk divider */
6442                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6443                 val &= ~CCK_FREQUENCY_VALUES;
6444                 val |= divider;
6445                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6446
6447                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6448                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6449                              50))
6450                         DRM_ERROR("timed out waiting for CDclk change\n");
6451         }
6452
6453         /* adjust self-refresh exit latency value */
6454         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6455         val &= ~0x7f;
6456
6457         /*
6458          * For high bandwidth configs, we set a higher latency in the bunit
6459          * so that the core display fetch happens in time to avoid underruns.
6460          */
6461         if (cdclk == 400000)
6462                 val |= 4500 / 250; /* 4.5 usec */
6463         else
6464                 val |= 3000 / 250; /* 3.0 usec */
6465         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6466
6467         mutex_unlock(&dev_priv->sb_lock);
6468
6469         intel_update_cdclk(dev);
6470 }
6471
6472 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6473 {
6474         struct drm_i915_private *dev_priv = to_i915(dev);
6475         u32 val, cmd;
6476
6477         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6478                                                 != dev_priv->cdclk_freq);
6479
6480         switch (cdclk) {
6481         case 333333:
6482         case 320000:
6483         case 266667:
6484         case 200000:
6485                 break;
6486         default:
6487                 MISSING_CASE(cdclk);
6488                 return;
6489         }
6490
6491         /*
6492          * Specs are full of misinformation, but testing on actual
6493          * hardware has shown that we just need to write the desired
6494          * CCK divider into the Punit register.
6495          */
6496         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6497
6498         mutex_lock(&dev_priv->rps.hw_lock);
6499         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6500         val &= ~DSPFREQGUAR_MASK_CHV;
6501         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6502         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6503         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6504                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6505                      50)) {
6506                 DRM_ERROR("timed out waiting for CDclk change\n");
6507         }
6508         mutex_unlock(&dev_priv->rps.hw_lock);
6509
6510         intel_update_cdclk(dev);
6511 }
6512
6513 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6514                                  int max_pixclk)
6515 {
6516         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6517         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6518
6519         /*
6520          * Really only a few cases to deal with, as only 4 CDclks are supported:
6521          *   200MHz
6522          *   267MHz
6523          *   320/333MHz (depends on HPLL freq)
6524          *   400MHz (VLV only)
6525          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6526          * of the lower bin and adjust if needed.
6527          *
6528          * We seem to get an unstable or solid color picture at 200MHz.
6529          * Not sure what's wrong. For now use 200MHz only when all pipes
6530          * are off.
6531          */
6532         if (!IS_CHERRYVIEW(dev_priv) &&
6533             max_pixclk > freq_320*limit/100)
6534                 return 400000;
6535         else if (max_pixclk > 266667*limit/100)
6536                 return freq_320;
6537         else if (max_pixclk > 0)
6538                 return 266667;
6539         else
6540                 return 200000;
6541 }
6542
6543 static int bxt_calc_cdclk(int max_pixclk)
6544 {
6545         if (max_pixclk > 576000)
6546                 return 624000;
6547         else if (max_pixclk > 384000)
6548                 return 576000;
6549         else if (max_pixclk > 288000)
6550                 return 384000;
6551         else if (max_pixclk > 144000)
6552                 return 288000;
6553         else
6554                 return 144000;
6555 }
6556
6557 /* Compute the max pixel clock for new configuration. */
6558 static int intel_mode_max_pixclk(struct drm_device *dev,
6559                                  struct drm_atomic_state *state)
6560 {
6561         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6562         struct drm_i915_private *dev_priv = to_i915(dev);
6563         struct drm_crtc *crtc;
6564         struct drm_crtc_state *crtc_state;
6565         unsigned max_pixclk = 0, i;
6566         enum pipe pipe;
6567
6568         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6569                sizeof(intel_state->min_pixclk));
6570
6571         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6572                 int pixclk = 0;
6573
6574                 if (crtc_state->enable)
6575                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6576
6577                 intel_state->min_pixclk[i] = pixclk;
6578         }
6579
6580         for_each_pipe(dev_priv, pipe)
6581                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6582
6583         return max_pixclk;
6584 }
6585
6586 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6587 {
6588         struct drm_device *dev = state->dev;
6589         struct drm_i915_private *dev_priv = to_i915(dev);
6590         int max_pixclk = intel_mode_max_pixclk(dev, state);
6591         struct intel_atomic_state *intel_state =
6592                 to_intel_atomic_state(state);
6593
6594         intel_state->cdclk = intel_state->dev_cdclk =
6595                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6596
6597         if (!intel_state->active_crtcs)
6598                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6599
6600         return 0;
6601 }
6602
6603 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6604 {
6605         int max_pixclk = ilk_max_pixel_rate(state);
6606         struct intel_atomic_state *intel_state =
6607                 to_intel_atomic_state(state);
6608
6609         intel_state->cdclk = intel_state->dev_cdclk =
6610                 bxt_calc_cdclk(max_pixclk);
6611
6612         if (!intel_state->active_crtcs)
6613                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6614
6615         return 0;
6616 }
6617
6618 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6619 {
6620         unsigned int credits, default_credits;
6621
6622         if (IS_CHERRYVIEW(dev_priv))
6623                 default_credits = PFI_CREDIT(12);
6624         else
6625                 default_credits = PFI_CREDIT(8);
6626
6627         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6628                 /* CHV suggested value is 31 or 63 */
6629                 if (IS_CHERRYVIEW(dev_priv))
6630                         credits = PFI_CREDIT_63;
6631                 else
6632                         credits = PFI_CREDIT(15);
6633         } else {
6634                 credits = default_credits;
6635         }
6636
6637         /*
6638          * WA - write default credits before re-programming
6639          * FIXME: should we also set the resend bit here?
6640          */
6641         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6642                    default_credits);
6643
6644         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6645                    credits | PFI_CREDIT_RESEND);
6646
6647         /*
6648          * FIXME is this guaranteed to clear
6649          * immediately or should we poll for it?
6650          */
6651         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6652 }
6653
6654 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6655 {
6656         struct drm_device *dev = old_state->dev;
6657         struct drm_i915_private *dev_priv = to_i915(dev);
6658         struct intel_atomic_state *old_intel_state =
6659                 to_intel_atomic_state(old_state);
6660         unsigned req_cdclk = old_intel_state->dev_cdclk;
6661
6662         /*
6663          * FIXME: We can end up here with all power domains off, yet
6664          * with a CDCLK frequency other than the minimum. To account
6665          * for this take the PIPE-A power domain, which covers the HW
6666          * blocks needed for the following programming. This can be
6667          * removed once it's guaranteed that we get here either with
6668          * the minimum CDCLK set, or the required power domains
6669          * enabled.
6670          */
6671         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6672
6673         if (IS_CHERRYVIEW(dev))
6674                 cherryview_set_cdclk(dev, req_cdclk);
6675         else
6676                 valleyview_set_cdclk(dev, req_cdclk);
6677
6678         vlv_program_pfi_credits(dev_priv);
6679
6680         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6681 }
6682
6683 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6684                                    struct drm_atomic_state *old_state)
6685 {
6686         struct drm_crtc *crtc = pipe_config->base.crtc;
6687         struct drm_device *dev = crtc->dev;
6688         struct drm_i915_private *dev_priv = to_i915(dev);
6689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6690         int pipe = intel_crtc->pipe;
6691
6692         if (WARN_ON(intel_crtc->active))
6693                 return;
6694
6695         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6696                 intel_dp_set_m_n(intel_crtc, M1_N1);
6697
6698         intel_set_pipe_timings(intel_crtc);
6699         intel_set_pipe_src_size(intel_crtc);
6700
6701         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6702                 struct drm_i915_private *dev_priv = to_i915(dev);
6703
6704                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6705                 I915_WRITE(CHV_CANVAS(pipe), 0);
6706         }
6707
6708         i9xx_set_pipeconf(intel_crtc);
6709
6710         intel_crtc->active = true;
6711
6712         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6713
6714         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6715
6716         if (IS_CHERRYVIEW(dev)) {
6717                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6718                 chv_enable_pll(intel_crtc, intel_crtc->config);
6719         } else {
6720                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6721                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6722         }
6723
6724         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6725
6726         i9xx_pfit_enable(intel_crtc);
6727
6728         intel_color_load_luts(&pipe_config->base);
6729
6730         intel_update_watermarks(crtc);
6731         intel_enable_pipe(intel_crtc);
6732
6733         assert_vblank_disabled(crtc);
6734         drm_crtc_vblank_on(crtc);
6735
6736         intel_encoders_enable(crtc, pipe_config, old_state);
6737 }
6738
6739 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6740 {
6741         struct drm_device *dev = crtc->base.dev;
6742         struct drm_i915_private *dev_priv = to_i915(dev);
6743
6744         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6745         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6746 }
6747
6748 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6749                              struct drm_atomic_state *old_state)
6750 {
6751         struct drm_crtc *crtc = pipe_config->base.crtc;
6752         struct drm_device *dev = crtc->dev;
6753         struct drm_i915_private *dev_priv = to_i915(dev);
6754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6755         enum pipe pipe = intel_crtc->pipe;
6756
6757         if (WARN_ON(intel_crtc->active))
6758                 return;
6759
6760         i9xx_set_pll_dividers(intel_crtc);
6761
6762         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6763                 intel_dp_set_m_n(intel_crtc, M1_N1);
6764
6765         intel_set_pipe_timings(intel_crtc);
6766         intel_set_pipe_src_size(intel_crtc);
6767
6768         i9xx_set_pipeconf(intel_crtc);
6769
6770         intel_crtc->active = true;
6771
6772         if (!IS_GEN2(dev))
6773                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6774
6775         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6776
6777         i9xx_enable_pll(intel_crtc);
6778
6779         i9xx_pfit_enable(intel_crtc);
6780
6781         intel_color_load_luts(&pipe_config->base);
6782
6783         intel_update_watermarks(crtc);
6784         intel_enable_pipe(intel_crtc);
6785
6786         assert_vblank_disabled(crtc);
6787         drm_crtc_vblank_on(crtc);
6788
6789         intel_encoders_enable(crtc, pipe_config, old_state);
6790 }
6791
6792 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6793 {
6794         struct drm_device *dev = crtc->base.dev;
6795         struct drm_i915_private *dev_priv = to_i915(dev);
6796
6797         if (!crtc->config->gmch_pfit.control)
6798                 return;
6799
6800         assert_pipe_disabled(dev_priv, crtc->pipe);
6801
6802         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6803                          I915_READ(PFIT_CONTROL));
6804         I915_WRITE(PFIT_CONTROL, 0);
6805 }
6806
6807 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6808                               struct drm_atomic_state *old_state)
6809 {
6810         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6811         struct drm_device *dev = crtc->dev;
6812         struct drm_i915_private *dev_priv = to_i915(dev);
6813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814         int pipe = intel_crtc->pipe;
6815
6816         /*
6817          * On gen2 planes are double buffered but the pipe isn't, so we must
6818          * wait for planes to fully turn off before disabling the pipe.
6819          */
6820         if (IS_GEN2(dev))
6821                 intel_wait_for_vblank(dev, pipe);
6822
6823         intel_encoders_disable(crtc, old_crtc_state, old_state);
6824
6825         drm_crtc_vblank_off(crtc);
6826         assert_vblank_disabled(crtc);
6827
6828         intel_disable_pipe(intel_crtc);
6829
6830         i9xx_pfit_disable(intel_crtc);
6831
6832         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6833
6834         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6835                 if (IS_CHERRYVIEW(dev))
6836                         chv_disable_pll(dev_priv, pipe);
6837                 else if (IS_VALLEYVIEW(dev))
6838                         vlv_disable_pll(dev_priv, pipe);
6839                 else
6840                         i9xx_disable_pll(intel_crtc);
6841         }
6842
6843         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6844
6845         if (!IS_GEN2(dev))
6846                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6847 }
6848
6849 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6850 {
6851         struct intel_encoder *encoder;
6852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6853         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6854         enum intel_display_power_domain domain;
6855         unsigned long domains;
6856         struct drm_atomic_state *state;
6857         struct intel_crtc_state *crtc_state;
6858         int ret;
6859
6860         if (!intel_crtc->active)
6861                 return;
6862
6863         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6864                 WARN_ON(intel_crtc->flip_work);
6865
6866                 intel_pre_disable_primary_noatomic(crtc);
6867
6868                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6869                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6870         }
6871
6872         state = drm_atomic_state_alloc(crtc->dev);
6873         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6874
6875         /* Everything's already locked, -EDEADLK can't happen. */
6876         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6877         ret = drm_atomic_add_affected_connectors(state, crtc);
6878
6879         WARN_ON(IS_ERR(crtc_state) || ret);
6880
6881         dev_priv->display.crtc_disable(crtc_state, state);
6882
6883         drm_atomic_state_free(state);
6884
6885         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6886                       crtc->base.id, crtc->name);
6887
6888         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6889         crtc->state->active = false;
6890         intel_crtc->active = false;
6891         crtc->enabled = false;
6892         crtc->state->connector_mask = 0;
6893         crtc->state->encoder_mask = 0;
6894
6895         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6896                 encoder->base.crtc = NULL;
6897
6898         intel_fbc_disable(intel_crtc);
6899         intel_update_watermarks(crtc);
6900         intel_disable_shared_dpll(intel_crtc);
6901
6902         domains = intel_crtc->enabled_power_domains;
6903         for_each_power_domain(domain, domains)
6904                 intel_display_power_put(dev_priv, domain);
6905         intel_crtc->enabled_power_domains = 0;
6906
6907         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6908         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6909 }
6910
6911 /*
6912  * turn all crtc's off, but do not adjust state
6913  * This has to be paired with a call to intel_modeset_setup_hw_state.
6914  */
6915 int intel_display_suspend(struct drm_device *dev)
6916 {
6917         struct drm_i915_private *dev_priv = to_i915(dev);
6918         struct drm_atomic_state *state;
6919         int ret;
6920
6921         state = drm_atomic_helper_suspend(dev);
6922         ret = PTR_ERR_OR_ZERO(state);
6923         if (ret)
6924                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6925         else
6926                 dev_priv->modeset_restore_state = state;
6927         return ret;
6928 }
6929
6930 void intel_encoder_destroy(struct drm_encoder *encoder)
6931 {
6932         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6933
6934         drm_encoder_cleanup(encoder);
6935         kfree(intel_encoder);
6936 }
6937
6938 /* Cross check the actual hw state with our own modeset state tracking (and it's
6939  * internal consistency). */
6940 static void intel_connector_verify_state(struct intel_connector *connector)
6941 {
6942         struct drm_crtc *crtc = connector->base.state->crtc;
6943
6944         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6945                       connector->base.base.id,
6946                       connector->base.name);
6947
6948         if (connector->get_hw_state(connector)) {
6949                 struct intel_encoder *encoder = connector->encoder;
6950                 struct drm_connector_state *conn_state = connector->base.state;
6951
6952                 I915_STATE_WARN(!crtc,
6953                          "connector enabled without attached crtc\n");
6954
6955                 if (!crtc)
6956                         return;
6957
6958                 I915_STATE_WARN(!crtc->state->active,
6959                       "connector is active, but attached crtc isn't\n");
6960
6961                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6962                         return;
6963
6964                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6965                         "atomic encoder doesn't match attached encoder\n");
6966
6967                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6968                         "attached encoder crtc differs from connector crtc\n");
6969         } else {
6970                 I915_STATE_WARN(crtc && crtc->state->active,
6971                         "attached crtc is active, but connector isn't\n");
6972                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6973                         "best encoder set without crtc!\n");
6974         }
6975 }
6976
6977 int intel_connector_init(struct intel_connector *connector)
6978 {
6979         drm_atomic_helper_connector_reset(&connector->base);
6980
6981         if (!connector->base.state)
6982                 return -ENOMEM;
6983
6984         return 0;
6985 }
6986
6987 struct intel_connector *intel_connector_alloc(void)
6988 {
6989         struct intel_connector *connector;
6990
6991         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6992         if (!connector)
6993                 return NULL;
6994
6995         if (intel_connector_init(connector) < 0) {
6996                 kfree(connector);
6997                 return NULL;
6998         }
6999
7000         return connector;
7001 }
7002
7003 /* Simple connector->get_hw_state implementation for encoders that support only
7004  * one connector and no cloning and hence the encoder state determines the state
7005  * of the connector. */
7006 bool intel_connector_get_hw_state(struct intel_connector *connector)
7007 {
7008         enum pipe pipe = 0;
7009         struct intel_encoder *encoder = connector->encoder;
7010
7011         return encoder->get_hw_state(encoder, &pipe);
7012 }
7013
7014 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7015 {
7016         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7017                 return crtc_state->fdi_lanes;
7018
7019         return 0;
7020 }
7021
7022 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7023                                      struct intel_crtc_state *pipe_config)
7024 {
7025         struct drm_atomic_state *state = pipe_config->base.state;
7026         struct intel_crtc *other_crtc;
7027         struct intel_crtc_state *other_crtc_state;
7028
7029         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7030                       pipe_name(pipe), pipe_config->fdi_lanes);
7031         if (pipe_config->fdi_lanes > 4) {
7032                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7033                               pipe_name(pipe), pipe_config->fdi_lanes);
7034                 return -EINVAL;
7035         }
7036
7037         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7038                 if (pipe_config->fdi_lanes > 2) {
7039                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7040                                       pipe_config->fdi_lanes);
7041                         return -EINVAL;
7042                 } else {
7043                         return 0;
7044                 }
7045         }
7046
7047         if (INTEL_INFO(dev)->num_pipes == 2)
7048                 return 0;
7049
7050         /* Ivybridge 3 pipe is really complicated */
7051         switch (pipe) {
7052         case PIPE_A:
7053                 return 0;
7054         case PIPE_B:
7055                 if (pipe_config->fdi_lanes <= 2)
7056                         return 0;
7057
7058                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7059                 other_crtc_state =
7060                         intel_atomic_get_crtc_state(state, other_crtc);
7061                 if (IS_ERR(other_crtc_state))
7062                         return PTR_ERR(other_crtc_state);
7063
7064                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7065                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7066                                       pipe_name(pipe), pipe_config->fdi_lanes);
7067                         return -EINVAL;
7068                 }
7069                 return 0;
7070         case PIPE_C:
7071                 if (pipe_config->fdi_lanes > 2) {
7072                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7073                                       pipe_name(pipe), pipe_config->fdi_lanes);
7074                         return -EINVAL;
7075                 }
7076
7077                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7078                 other_crtc_state =
7079                         intel_atomic_get_crtc_state(state, other_crtc);
7080                 if (IS_ERR(other_crtc_state))
7081                         return PTR_ERR(other_crtc_state);
7082
7083                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7084                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7085                         return -EINVAL;
7086                 }
7087                 return 0;
7088         default:
7089                 BUG();
7090         }
7091 }
7092
7093 #define RETRY 1
7094 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7095                                        struct intel_crtc_state *pipe_config)
7096 {
7097         struct drm_device *dev = intel_crtc->base.dev;
7098         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7099         int lane, link_bw, fdi_dotclock, ret;
7100         bool needs_recompute = false;
7101
7102 retry:
7103         /* FDI is a binary signal running at ~2.7GHz, encoding
7104          * each output octet as 10 bits. The actual frequency
7105          * is stored as a divider into a 100MHz clock, and the
7106          * mode pixel clock is stored in units of 1KHz.
7107          * Hence the bw of each lane in terms of the mode signal
7108          * is:
7109          */
7110         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7111
7112         fdi_dotclock = adjusted_mode->crtc_clock;
7113
7114         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7115                                            pipe_config->pipe_bpp);
7116
7117         pipe_config->fdi_lanes = lane;
7118
7119         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7120                                link_bw, &pipe_config->fdi_m_n);
7121
7122         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7123         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7124                 pipe_config->pipe_bpp -= 2*3;
7125                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7126                               pipe_config->pipe_bpp);
7127                 needs_recompute = true;
7128                 pipe_config->bw_constrained = true;
7129
7130                 goto retry;
7131         }
7132
7133         if (needs_recompute)
7134                 return RETRY;
7135
7136         return ret;
7137 }
7138
7139 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7140                                      struct intel_crtc_state *pipe_config)
7141 {
7142         if (pipe_config->pipe_bpp > 24)
7143                 return false;
7144
7145         /* HSW can handle pixel rate up to cdclk? */
7146         if (IS_HASWELL(dev_priv))
7147                 return true;
7148
7149         /*
7150          * We compare against max which means we must take
7151          * the increased cdclk requirement into account when
7152          * calculating the new cdclk.
7153          *
7154          * Should measure whether using a lower cdclk w/o IPS
7155          */
7156         return ilk_pipe_pixel_rate(pipe_config) <=
7157                 dev_priv->max_cdclk_freq * 95 / 100;
7158 }
7159
7160 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7161                                    struct intel_crtc_state *pipe_config)
7162 {
7163         struct drm_device *dev = crtc->base.dev;
7164         struct drm_i915_private *dev_priv = to_i915(dev);
7165
7166         pipe_config->ips_enabled = i915.enable_ips &&
7167                 hsw_crtc_supports_ips(crtc) &&
7168                 pipe_config_supports_ips(dev_priv, pipe_config);
7169 }
7170
7171 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7172 {
7173         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7174
7175         /* GDG double wide on either pipe, otherwise pipe A only */
7176         return INTEL_INFO(dev_priv)->gen < 4 &&
7177                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7178 }
7179
7180 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7181                                      struct intel_crtc_state *pipe_config)
7182 {
7183         struct drm_device *dev = crtc->base.dev;
7184         struct drm_i915_private *dev_priv = to_i915(dev);
7185         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7186         int clock_limit = dev_priv->max_dotclk_freq;
7187
7188         if (INTEL_INFO(dev)->gen < 4) {
7189                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7190
7191                 /*
7192                  * Enable double wide mode when the dot clock
7193                  * is > 90% of the (display) core speed.
7194                  */
7195                 if (intel_crtc_supports_double_wide(crtc) &&
7196                     adjusted_mode->crtc_clock > clock_limit) {
7197                         clock_limit = dev_priv->max_dotclk_freq;
7198                         pipe_config->double_wide = true;
7199                 }
7200         }
7201
7202         if (adjusted_mode->crtc_clock > clock_limit) {
7203                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7204                               adjusted_mode->crtc_clock, clock_limit,
7205                               yesno(pipe_config->double_wide));
7206                 return -EINVAL;
7207         }
7208
7209         /*
7210          * Pipe horizontal size must be even in:
7211          * - DVO ganged mode
7212          * - LVDS dual channel mode
7213          * - Double wide pipe
7214          */
7215         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7216              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7217                 pipe_config->pipe_src_w &= ~1;
7218
7219         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7220          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7221          */
7222         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7223                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7224                 return -EINVAL;
7225
7226         if (HAS_IPS(dev))
7227                 hsw_compute_ips_config(crtc, pipe_config);
7228
7229         if (pipe_config->has_pch_encoder)
7230                 return ironlake_fdi_compute_config(crtc, pipe_config);
7231
7232         return 0;
7233 }
7234
7235 static int skylake_get_display_clock_speed(struct drm_device *dev)
7236 {
7237         struct drm_i915_private *dev_priv = to_i915(dev);
7238         uint32_t cdctl;
7239
7240         skl_dpll0_update(dev_priv);
7241
7242         if (dev_priv->cdclk_pll.vco == 0)
7243                 return dev_priv->cdclk_pll.ref;
7244
7245         cdctl = I915_READ(CDCLK_CTL);
7246
7247         if (dev_priv->cdclk_pll.vco == 8640000) {
7248                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7249                 case CDCLK_FREQ_450_432:
7250                         return 432000;
7251                 case CDCLK_FREQ_337_308:
7252                         return 308571;
7253                 case CDCLK_FREQ_540:
7254                         return 540000;
7255                 case CDCLK_FREQ_675_617:
7256                         return 617143;
7257                 default:
7258                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7259                 }
7260         } else {
7261                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7262                 case CDCLK_FREQ_450_432:
7263                         return 450000;
7264                 case CDCLK_FREQ_337_308:
7265                         return 337500;
7266                 case CDCLK_FREQ_540:
7267                         return 540000;
7268                 case CDCLK_FREQ_675_617:
7269                         return 675000;
7270                 default:
7271                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7272                 }
7273         }
7274
7275         return dev_priv->cdclk_pll.ref;
7276 }
7277
7278 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7279 {
7280         u32 val;
7281
7282         dev_priv->cdclk_pll.ref = 19200;
7283         dev_priv->cdclk_pll.vco = 0;
7284
7285         val = I915_READ(BXT_DE_PLL_ENABLE);
7286         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7287                 return;
7288
7289         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7290                 return;
7291
7292         val = I915_READ(BXT_DE_PLL_CTL);
7293         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7294                 dev_priv->cdclk_pll.ref;
7295 }
7296
7297 static int broxton_get_display_clock_speed(struct drm_device *dev)
7298 {
7299         struct drm_i915_private *dev_priv = to_i915(dev);
7300         u32 divider;
7301         int div, vco;
7302
7303         bxt_de_pll_update(dev_priv);
7304
7305         vco = dev_priv->cdclk_pll.vco;
7306         if (vco == 0)
7307                 return dev_priv->cdclk_pll.ref;
7308
7309         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7310
7311         switch (divider) {
7312         case BXT_CDCLK_CD2X_DIV_SEL_1:
7313                 div = 2;
7314                 break;
7315         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7316                 div = 3;
7317                 break;
7318         case BXT_CDCLK_CD2X_DIV_SEL_2:
7319                 div = 4;
7320                 break;
7321         case BXT_CDCLK_CD2X_DIV_SEL_4:
7322                 div = 8;
7323                 break;
7324         default:
7325                 MISSING_CASE(divider);
7326                 return dev_priv->cdclk_pll.ref;
7327         }
7328
7329         return DIV_ROUND_CLOSEST(vco, div);
7330 }
7331
7332 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7333 {
7334         struct drm_i915_private *dev_priv = to_i915(dev);
7335         uint32_t lcpll = I915_READ(LCPLL_CTL);
7336         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7337
7338         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7339                 return 800000;
7340         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7341                 return 450000;
7342         else if (freq == LCPLL_CLK_FREQ_450)
7343                 return 450000;
7344         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7345                 return 540000;
7346         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7347                 return 337500;
7348         else
7349                 return 675000;
7350 }
7351
7352 static int haswell_get_display_clock_speed(struct drm_device *dev)
7353 {
7354         struct drm_i915_private *dev_priv = to_i915(dev);
7355         uint32_t lcpll = I915_READ(LCPLL_CTL);
7356         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7357
7358         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7359                 return 800000;
7360         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7361                 return 450000;
7362         else if (freq == LCPLL_CLK_FREQ_450)
7363                 return 450000;
7364         else if (IS_HSW_ULT(dev))
7365                 return 337500;
7366         else
7367                 return 540000;
7368 }
7369
7370 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7371 {
7372         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7373                                       CCK_DISPLAY_CLOCK_CONTROL);
7374 }
7375
7376 static int ilk_get_display_clock_speed(struct drm_device *dev)
7377 {
7378         return 450000;
7379 }
7380
7381 static int i945_get_display_clock_speed(struct drm_device *dev)
7382 {
7383         return 400000;
7384 }
7385
7386 static int i915_get_display_clock_speed(struct drm_device *dev)
7387 {
7388         return 333333;
7389 }
7390
7391 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7392 {
7393         return 200000;
7394 }
7395
7396 static int pnv_get_display_clock_speed(struct drm_device *dev)
7397 {
7398         struct pci_dev *pdev = dev->pdev;
7399         u16 gcfgc = 0;
7400
7401         pci_read_config_word(pdev, GCFGC, &gcfgc);
7402
7403         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7404         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7405                 return 266667;
7406         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7407                 return 333333;
7408         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7409                 return 444444;
7410         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7411                 return 200000;
7412         default:
7413                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7414         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7415                 return 133333;
7416         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7417                 return 166667;
7418         }
7419 }
7420
7421 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7422 {
7423         struct pci_dev *pdev = dev->pdev;
7424         u16 gcfgc = 0;
7425
7426         pci_read_config_word(pdev, GCFGC, &gcfgc);
7427
7428         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7429                 return 133333;
7430         else {
7431                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7432                 case GC_DISPLAY_CLOCK_333_MHZ:
7433                         return 333333;
7434                 default:
7435                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7436                         return 190000;
7437                 }
7438         }
7439 }
7440
7441 static int i865_get_display_clock_speed(struct drm_device *dev)
7442 {
7443         return 266667;
7444 }
7445
7446 static int i85x_get_display_clock_speed(struct drm_device *dev)
7447 {
7448         struct pci_dev *pdev = dev->pdev;
7449         u16 hpllcc = 0;
7450
7451         /*
7452          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7453          * encoding is different :(
7454          * FIXME is this the right way to detect 852GM/852GMV?
7455          */
7456         if (pdev->revision == 0x1)
7457                 return 133333;
7458
7459         pci_bus_read_config_word(pdev->bus,
7460                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7461
7462         /* Assume that the hardware is in the high speed state.  This
7463          * should be the default.
7464          */
7465         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7466         case GC_CLOCK_133_200:
7467         case GC_CLOCK_133_200_2:
7468         case GC_CLOCK_100_200:
7469                 return 200000;
7470         case GC_CLOCK_166_250:
7471                 return 250000;
7472         case GC_CLOCK_100_133:
7473                 return 133333;
7474         case GC_CLOCK_133_266:
7475         case GC_CLOCK_133_266_2:
7476         case GC_CLOCK_166_266:
7477                 return 266667;
7478         }
7479
7480         /* Shouldn't happen */
7481         return 0;
7482 }
7483
7484 static int i830_get_display_clock_speed(struct drm_device *dev)
7485 {
7486         return 133333;
7487 }
7488
7489 static unsigned int intel_hpll_vco(struct drm_device *dev)
7490 {
7491         struct drm_i915_private *dev_priv = to_i915(dev);
7492         static const unsigned int blb_vco[8] = {
7493                 [0] = 3200000,
7494                 [1] = 4000000,
7495                 [2] = 5333333,
7496                 [3] = 4800000,
7497                 [4] = 6400000,
7498         };
7499         static const unsigned int pnv_vco[8] = {
7500                 [0] = 3200000,
7501                 [1] = 4000000,
7502                 [2] = 5333333,
7503                 [3] = 4800000,
7504                 [4] = 2666667,
7505         };
7506         static const unsigned int cl_vco[8] = {
7507                 [0] = 3200000,
7508                 [1] = 4000000,
7509                 [2] = 5333333,
7510                 [3] = 6400000,
7511                 [4] = 3333333,
7512                 [5] = 3566667,
7513                 [6] = 4266667,
7514         };
7515         static const unsigned int elk_vco[8] = {
7516                 [0] = 3200000,
7517                 [1] = 4000000,
7518                 [2] = 5333333,
7519                 [3] = 4800000,
7520         };
7521         static const unsigned int ctg_vco[8] = {
7522                 [0] = 3200000,
7523                 [1] = 4000000,
7524                 [2] = 5333333,
7525                 [3] = 6400000,
7526                 [4] = 2666667,
7527                 [5] = 4266667,
7528         };
7529         const unsigned int *vco_table;
7530         unsigned int vco;
7531         uint8_t tmp = 0;
7532
7533         /* FIXME other chipsets? */
7534         if (IS_GM45(dev))
7535                 vco_table = ctg_vco;
7536         else if (IS_G4X(dev))
7537                 vco_table = elk_vco;
7538         else if (IS_CRESTLINE(dev))
7539                 vco_table = cl_vco;
7540         else if (IS_PINEVIEW(dev))
7541                 vco_table = pnv_vco;
7542         else if (IS_G33(dev))
7543                 vco_table = blb_vco;
7544         else
7545                 return 0;
7546
7547         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7548
7549         vco = vco_table[tmp & 0x7];
7550         if (vco == 0)
7551                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7552         else
7553                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7554
7555         return vco;
7556 }
7557
7558 static int gm45_get_display_clock_speed(struct drm_device *dev)
7559 {
7560         struct pci_dev *pdev = dev->pdev;
7561         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7562         uint16_t tmp = 0;
7563
7564         pci_read_config_word(pdev, GCFGC, &tmp);
7565
7566         cdclk_sel = (tmp >> 12) & 0x1;
7567
7568         switch (vco) {
7569         case 2666667:
7570         case 4000000:
7571         case 5333333:
7572                 return cdclk_sel ? 333333 : 222222;
7573         case 3200000:
7574                 return cdclk_sel ? 320000 : 228571;
7575         default:
7576                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7577                 return 222222;
7578         }
7579 }
7580
7581 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7582 {
7583         struct pci_dev *pdev = dev->pdev;
7584         static const uint8_t div_3200[] = { 16, 10,  8 };
7585         static const uint8_t div_4000[] = { 20, 12, 10 };
7586         static const uint8_t div_5333[] = { 24, 16, 14 };
7587         const uint8_t *div_table;
7588         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7589         uint16_t tmp = 0;
7590
7591         pci_read_config_word(pdev, GCFGC, &tmp);
7592
7593         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7594
7595         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7596                 goto fail;
7597
7598         switch (vco) {
7599         case 3200000:
7600                 div_table = div_3200;
7601                 break;
7602         case 4000000:
7603                 div_table = div_4000;
7604                 break;
7605         case 5333333:
7606                 div_table = div_5333;
7607                 break;
7608         default:
7609                 goto fail;
7610         }
7611
7612         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7613
7614 fail:
7615         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7616         return 200000;
7617 }
7618
7619 static int g33_get_display_clock_speed(struct drm_device *dev)
7620 {
7621         struct pci_dev *pdev = dev->pdev;
7622         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7623         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7624         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7625         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7626         const uint8_t *div_table;
7627         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7628         uint16_t tmp = 0;
7629
7630         pci_read_config_word(pdev, GCFGC, &tmp);
7631
7632         cdclk_sel = (tmp >> 4) & 0x7;
7633
7634         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7635                 goto fail;
7636
7637         switch (vco) {
7638         case 3200000:
7639                 div_table = div_3200;
7640                 break;
7641         case 4000000:
7642                 div_table = div_4000;
7643                 break;
7644         case 4800000:
7645                 div_table = div_4800;
7646                 break;
7647         case 5333333:
7648                 div_table = div_5333;
7649                 break;
7650         default:
7651                 goto fail;
7652         }
7653
7654         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7655
7656 fail:
7657         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7658         return 190476;
7659 }
7660
7661 static void
7662 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7663 {
7664         while (*num > DATA_LINK_M_N_MASK ||
7665                *den > DATA_LINK_M_N_MASK) {
7666                 *num >>= 1;
7667                 *den >>= 1;
7668         }
7669 }
7670
7671 static void compute_m_n(unsigned int m, unsigned int n,
7672                         uint32_t *ret_m, uint32_t *ret_n)
7673 {
7674         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7675         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7676         intel_reduce_m_n_ratio(ret_m, ret_n);
7677 }
7678
7679 void
7680 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7681                        int pixel_clock, int link_clock,
7682                        struct intel_link_m_n *m_n)
7683 {
7684         m_n->tu = 64;
7685
7686         compute_m_n(bits_per_pixel * pixel_clock,
7687                     link_clock * nlanes * 8,
7688                     &m_n->gmch_m, &m_n->gmch_n);
7689
7690         compute_m_n(pixel_clock, link_clock,
7691                     &m_n->link_m, &m_n->link_n);
7692 }
7693
7694 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7695 {
7696         if (i915.panel_use_ssc >= 0)
7697                 return i915.panel_use_ssc != 0;
7698         return dev_priv->vbt.lvds_use_ssc
7699                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7700 }
7701
7702 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7703 {
7704         return (1 << dpll->n) << 16 | dpll->m2;
7705 }
7706
7707 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7708 {
7709         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7710 }
7711
7712 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7713                                      struct intel_crtc_state *crtc_state,
7714                                      struct dpll *reduced_clock)
7715 {
7716         struct drm_device *dev = crtc->base.dev;
7717         u32 fp, fp2 = 0;
7718
7719         if (IS_PINEVIEW(dev)) {
7720                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7721                 if (reduced_clock)
7722                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7723         } else {
7724                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7725                 if (reduced_clock)
7726                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7727         }
7728
7729         crtc_state->dpll_hw_state.fp0 = fp;
7730
7731         crtc->lowfreq_avail = false;
7732         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7733             reduced_clock) {
7734                 crtc_state->dpll_hw_state.fp1 = fp2;
7735                 crtc->lowfreq_avail = true;
7736         } else {
7737                 crtc_state->dpll_hw_state.fp1 = fp;
7738         }
7739 }
7740
7741 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7742                 pipe)
7743 {
7744         u32 reg_val;
7745
7746         /*
7747          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7748          * and set it to a reasonable value instead.
7749          */
7750         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7751         reg_val &= 0xffffff00;
7752         reg_val |= 0x00000030;
7753         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7754
7755         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7756         reg_val &= 0x8cffffff;
7757         reg_val = 0x8c000000;
7758         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7759
7760         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7761         reg_val &= 0xffffff00;
7762         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7763
7764         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7765         reg_val &= 0x00ffffff;
7766         reg_val |= 0xb0000000;
7767         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7768 }
7769
7770 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7771                                          struct intel_link_m_n *m_n)
7772 {
7773         struct drm_device *dev = crtc->base.dev;
7774         struct drm_i915_private *dev_priv = to_i915(dev);
7775         int pipe = crtc->pipe;
7776
7777         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7778         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7779         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7780         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7781 }
7782
7783 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7784                                          struct intel_link_m_n *m_n,
7785                                          struct intel_link_m_n *m2_n2)
7786 {
7787         struct drm_device *dev = crtc->base.dev;
7788         struct drm_i915_private *dev_priv = to_i915(dev);
7789         int pipe = crtc->pipe;
7790         enum transcoder transcoder = crtc->config->cpu_transcoder;
7791
7792         if (INTEL_INFO(dev)->gen >= 5) {
7793                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7794                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7795                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7796                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7797                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7798                  * for gen < 8) and if DRRS is supported (to make sure the
7799                  * registers are not unnecessarily accessed).
7800                  */
7801                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7802                         crtc->config->has_drrs) {
7803                         I915_WRITE(PIPE_DATA_M2(transcoder),
7804                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7805                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7806                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7807                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7808                 }
7809         } else {
7810                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7811                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7812                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7813                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7814         }
7815 }
7816
7817 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7818 {
7819         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7820
7821         if (m_n == M1_N1) {
7822                 dp_m_n = &crtc->config->dp_m_n;
7823                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7824         } else if (m_n == M2_N2) {
7825
7826                 /*
7827                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7828                  * needs to be programmed into M1_N1.
7829                  */
7830                 dp_m_n = &crtc->config->dp_m2_n2;
7831         } else {
7832                 DRM_ERROR("Unsupported divider value\n");
7833                 return;
7834         }
7835
7836         if (crtc->config->has_pch_encoder)
7837                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7838         else
7839                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7840 }
7841
7842 static void vlv_compute_dpll(struct intel_crtc *crtc,
7843                              struct intel_crtc_state *pipe_config)
7844 {
7845         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7846                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7847         if (crtc->pipe != PIPE_A)
7848                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7849
7850         /* DPLL not used with DSI, but still need the rest set up */
7851         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7852                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7853                         DPLL_EXT_BUFFER_ENABLE_VLV;
7854
7855         pipe_config->dpll_hw_state.dpll_md =
7856                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7857 }
7858
7859 static void chv_compute_dpll(struct intel_crtc *crtc,
7860                              struct intel_crtc_state *pipe_config)
7861 {
7862         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7863                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7864         if (crtc->pipe != PIPE_A)
7865                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7866
7867         /* DPLL not used with DSI, but still need the rest set up */
7868         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7869                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7870
7871         pipe_config->dpll_hw_state.dpll_md =
7872                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7873 }
7874
7875 static void vlv_prepare_pll(struct intel_crtc *crtc,
7876                             const struct intel_crtc_state *pipe_config)
7877 {
7878         struct drm_device *dev = crtc->base.dev;
7879         struct drm_i915_private *dev_priv = to_i915(dev);
7880         enum pipe pipe = crtc->pipe;
7881         u32 mdiv;
7882         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7883         u32 coreclk, reg_val;
7884
7885         /* Enable Refclk */
7886         I915_WRITE(DPLL(pipe),
7887                    pipe_config->dpll_hw_state.dpll &
7888                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7889
7890         /* No need to actually set up the DPLL with DSI */
7891         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7892                 return;
7893
7894         mutex_lock(&dev_priv->sb_lock);
7895
7896         bestn = pipe_config->dpll.n;
7897         bestm1 = pipe_config->dpll.m1;
7898         bestm2 = pipe_config->dpll.m2;
7899         bestp1 = pipe_config->dpll.p1;
7900         bestp2 = pipe_config->dpll.p2;
7901
7902         /* See eDP HDMI DPIO driver vbios notes doc */
7903
7904         /* PLL B needs special handling */
7905         if (pipe == PIPE_B)
7906                 vlv_pllb_recal_opamp(dev_priv, pipe);
7907
7908         /* Set up Tx target for periodic Rcomp update */
7909         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7910
7911         /* Disable target IRef on PLL */
7912         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7913         reg_val &= 0x00ffffff;
7914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7915
7916         /* Disable fast lock */
7917         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7918
7919         /* Set idtafcrecal before PLL is enabled */
7920         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7921         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7922         mdiv |= ((bestn << DPIO_N_SHIFT));
7923         mdiv |= (1 << DPIO_K_SHIFT);
7924
7925         /*
7926          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7927          * but we don't support that).
7928          * Note: don't use the DAC post divider as it seems unstable.
7929          */
7930         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7931         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7932
7933         mdiv |= DPIO_ENABLE_CALIBRATION;
7934         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7935
7936         /* Set HBR and RBR LPF coefficients */
7937         if (pipe_config->port_clock == 162000 ||
7938             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7939             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7940                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7941                                  0x009f0003);
7942         else
7943                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7944                                  0x00d0000f);
7945
7946         if (intel_crtc_has_dp_encoder(pipe_config)) {
7947                 /* Use SSC source */
7948                 if (pipe == PIPE_A)
7949                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7950                                          0x0df40000);
7951                 else
7952                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7953                                          0x0df70000);
7954         } else { /* HDMI or VGA */
7955                 /* Use bend source */
7956                 if (pipe == PIPE_A)
7957                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7958                                          0x0df70000);
7959                 else
7960                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7961                                          0x0df40000);
7962         }
7963
7964         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7965         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7966         if (intel_crtc_has_dp_encoder(crtc->config))
7967                 coreclk |= 0x01000000;
7968         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7969
7970         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7971         mutex_unlock(&dev_priv->sb_lock);
7972 }
7973
7974 static void chv_prepare_pll(struct intel_crtc *crtc,
7975                             const struct intel_crtc_state *pipe_config)
7976 {
7977         struct drm_device *dev = crtc->base.dev;
7978         struct drm_i915_private *dev_priv = to_i915(dev);
7979         enum pipe pipe = crtc->pipe;
7980         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7981         u32 loopfilter, tribuf_calcntr;
7982         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7983         u32 dpio_val;
7984         int vco;
7985
7986         /* Enable Refclk and SSC */
7987         I915_WRITE(DPLL(pipe),
7988                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7989
7990         /* No need to actually set up the DPLL with DSI */
7991         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7992                 return;
7993
7994         bestn = pipe_config->dpll.n;
7995         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7996         bestm1 = pipe_config->dpll.m1;
7997         bestm2 = pipe_config->dpll.m2 >> 22;
7998         bestp1 = pipe_config->dpll.p1;
7999         bestp2 = pipe_config->dpll.p2;
8000         vco = pipe_config->dpll.vco;
8001         dpio_val = 0;
8002         loopfilter = 0;
8003
8004         mutex_lock(&dev_priv->sb_lock);
8005
8006         /* p1 and p2 divider */
8007         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8008                         5 << DPIO_CHV_S1_DIV_SHIFT |
8009                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8010                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8011                         1 << DPIO_CHV_K_DIV_SHIFT);
8012
8013         /* Feedback post-divider - m2 */
8014         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8015
8016         /* Feedback refclk divider - n and m1 */
8017         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8018                         DPIO_CHV_M1_DIV_BY_2 |
8019                         1 << DPIO_CHV_N_DIV_SHIFT);
8020
8021         /* M2 fraction division */
8022         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8023
8024         /* M2 fraction division enable */
8025         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8026         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8027         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8028         if (bestm2_frac)
8029                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8030         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8031
8032         /* Program digital lock detect threshold */
8033         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8034         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8035                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8036         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8037         if (!bestm2_frac)
8038                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8039         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8040
8041         /* Loop filter */
8042         if (vco == 5400000) {
8043                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8044                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8045                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8046                 tribuf_calcntr = 0x9;
8047         } else if (vco <= 6200000) {
8048                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8049                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8050                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8051                 tribuf_calcntr = 0x9;
8052         } else if (vco <= 6480000) {
8053                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8054                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8055                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8056                 tribuf_calcntr = 0x8;
8057         } else {
8058                 /* Not supported. Apply the same limits as in the max case */
8059                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8060                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8061                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8062                 tribuf_calcntr = 0;
8063         }
8064         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8065
8066         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8067         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8068         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8069         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8070
8071         /* AFC Recal */
8072         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8073                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8074                         DPIO_AFC_RECAL);
8075
8076         mutex_unlock(&dev_priv->sb_lock);
8077 }
8078
8079 /**
8080  * vlv_force_pll_on - forcibly enable just the PLL
8081  * @dev_priv: i915 private structure
8082  * @pipe: pipe PLL to enable
8083  * @dpll: PLL configuration
8084  *
8085  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8086  * in cases where we need the PLL enabled even when @pipe is not going to
8087  * be enabled.
8088  */
8089 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8090                      const struct dpll *dpll)
8091 {
8092         struct intel_crtc *crtc =
8093                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8094         struct intel_crtc_state *pipe_config;
8095
8096         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8097         if (!pipe_config)
8098                 return -ENOMEM;
8099
8100         pipe_config->base.crtc = &crtc->base;
8101         pipe_config->pixel_multiplier = 1;
8102         pipe_config->dpll = *dpll;
8103
8104         if (IS_CHERRYVIEW(dev)) {
8105                 chv_compute_dpll(crtc, pipe_config);
8106                 chv_prepare_pll(crtc, pipe_config);
8107                 chv_enable_pll(crtc, pipe_config);
8108         } else {
8109                 vlv_compute_dpll(crtc, pipe_config);
8110                 vlv_prepare_pll(crtc, pipe_config);
8111                 vlv_enable_pll(crtc, pipe_config);
8112         }
8113
8114         kfree(pipe_config);
8115
8116         return 0;
8117 }
8118
8119 /**
8120  * vlv_force_pll_off - forcibly disable just the PLL
8121  * @dev_priv: i915 private structure
8122  * @pipe: pipe PLL to disable
8123  *
8124  * Disable the PLL for @pipe. To be used in cases where we need
8125  * the PLL enabled even when @pipe is not going to be enabled.
8126  */
8127 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8128 {
8129         if (IS_CHERRYVIEW(dev))
8130                 chv_disable_pll(to_i915(dev), pipe);
8131         else
8132                 vlv_disable_pll(to_i915(dev), pipe);
8133 }
8134
8135 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8136                               struct intel_crtc_state *crtc_state,
8137                               struct dpll *reduced_clock)
8138 {
8139         struct drm_device *dev = crtc->base.dev;
8140         struct drm_i915_private *dev_priv = to_i915(dev);
8141         u32 dpll;
8142         struct dpll *clock = &crtc_state->dpll;
8143
8144         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8145
8146         dpll = DPLL_VGA_MODE_DIS;
8147
8148         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8149                 dpll |= DPLLB_MODE_LVDS;
8150         else
8151                 dpll |= DPLLB_MODE_DAC_SERIAL;
8152
8153         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8154                 dpll |= (crtc_state->pixel_multiplier - 1)
8155                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8156         }
8157
8158         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8159             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8160                 dpll |= DPLL_SDVO_HIGH_SPEED;
8161
8162         if (intel_crtc_has_dp_encoder(crtc_state))
8163                 dpll |= DPLL_SDVO_HIGH_SPEED;
8164
8165         /* compute bitmask from p1 value */
8166         if (IS_PINEVIEW(dev))
8167                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8168         else {
8169                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8170                 if (IS_G4X(dev) && reduced_clock)
8171                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8172         }
8173         switch (clock->p2) {
8174         case 5:
8175                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8176                 break;
8177         case 7:
8178                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8179                 break;
8180         case 10:
8181                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8182                 break;
8183         case 14:
8184                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8185                 break;
8186         }
8187         if (INTEL_INFO(dev)->gen >= 4)
8188                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8189
8190         if (crtc_state->sdvo_tv_clock)
8191                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8192         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8193                  intel_panel_use_ssc(dev_priv))
8194                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8195         else
8196                 dpll |= PLL_REF_INPUT_DREFCLK;
8197
8198         dpll |= DPLL_VCO_ENABLE;
8199         crtc_state->dpll_hw_state.dpll = dpll;
8200
8201         if (INTEL_INFO(dev)->gen >= 4) {
8202                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8203                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8204                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8205         }
8206 }
8207
8208 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8209                               struct intel_crtc_state *crtc_state,
8210                               struct dpll *reduced_clock)
8211 {
8212         struct drm_device *dev = crtc->base.dev;
8213         struct drm_i915_private *dev_priv = to_i915(dev);
8214         u32 dpll;
8215         struct dpll *clock = &crtc_state->dpll;
8216
8217         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8218
8219         dpll = DPLL_VGA_MODE_DIS;
8220
8221         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8222                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8223         } else {
8224                 if (clock->p1 == 2)
8225                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8226                 else
8227                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8228                 if (clock->p2 == 4)
8229                         dpll |= PLL_P2_DIVIDE_BY_4;
8230         }
8231
8232         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8233                 dpll |= DPLL_DVO_2X_MODE;
8234
8235         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8236             intel_panel_use_ssc(dev_priv))
8237                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8238         else
8239                 dpll |= PLL_REF_INPUT_DREFCLK;
8240
8241         dpll |= DPLL_VCO_ENABLE;
8242         crtc_state->dpll_hw_state.dpll = dpll;
8243 }
8244
8245 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8246 {
8247         struct drm_device *dev = intel_crtc->base.dev;
8248         struct drm_i915_private *dev_priv = to_i915(dev);
8249         enum pipe pipe = intel_crtc->pipe;
8250         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8251         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8252         uint32_t crtc_vtotal, crtc_vblank_end;
8253         int vsyncshift = 0;
8254
8255         /* We need to be careful not to changed the adjusted mode, for otherwise
8256          * the hw state checker will get angry at the mismatch. */
8257         crtc_vtotal = adjusted_mode->crtc_vtotal;
8258         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8259
8260         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8261                 /* the chip adds 2 halflines automatically */
8262                 crtc_vtotal -= 1;
8263                 crtc_vblank_end -= 1;
8264
8265                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8266                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8267                 else
8268                         vsyncshift = adjusted_mode->crtc_hsync_start -
8269                                 adjusted_mode->crtc_htotal / 2;
8270                 if (vsyncshift < 0)
8271                         vsyncshift += adjusted_mode->crtc_htotal;
8272         }
8273
8274         if (INTEL_INFO(dev)->gen > 3)
8275                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8276
8277         I915_WRITE(HTOTAL(cpu_transcoder),
8278                    (adjusted_mode->crtc_hdisplay - 1) |
8279                    ((adjusted_mode->crtc_htotal - 1) << 16));
8280         I915_WRITE(HBLANK(cpu_transcoder),
8281                    (adjusted_mode->crtc_hblank_start - 1) |
8282                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8283         I915_WRITE(HSYNC(cpu_transcoder),
8284                    (adjusted_mode->crtc_hsync_start - 1) |
8285                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8286
8287         I915_WRITE(VTOTAL(cpu_transcoder),
8288                    (adjusted_mode->crtc_vdisplay - 1) |
8289                    ((crtc_vtotal - 1) << 16));
8290         I915_WRITE(VBLANK(cpu_transcoder),
8291                    (adjusted_mode->crtc_vblank_start - 1) |
8292                    ((crtc_vblank_end - 1) << 16));
8293         I915_WRITE(VSYNC(cpu_transcoder),
8294                    (adjusted_mode->crtc_vsync_start - 1) |
8295                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8296
8297         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8298          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8299          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8300          * bits. */
8301         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8302             (pipe == PIPE_B || pipe == PIPE_C))
8303                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8304
8305 }
8306
8307 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8308 {
8309         struct drm_device *dev = intel_crtc->base.dev;
8310         struct drm_i915_private *dev_priv = to_i915(dev);
8311         enum pipe pipe = intel_crtc->pipe;
8312
8313         /* pipesrc controls the size that is scaled from, which should
8314          * always be the user's requested size.
8315          */
8316         I915_WRITE(PIPESRC(pipe),
8317                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8318                    (intel_crtc->config->pipe_src_h - 1));
8319 }
8320
8321 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8322                                    struct intel_crtc_state *pipe_config)
8323 {
8324         struct drm_device *dev = crtc->base.dev;
8325         struct drm_i915_private *dev_priv = to_i915(dev);
8326         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8327         uint32_t tmp;
8328
8329         tmp = I915_READ(HTOTAL(cpu_transcoder));
8330         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8331         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8332         tmp = I915_READ(HBLANK(cpu_transcoder));
8333         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8334         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8335         tmp = I915_READ(HSYNC(cpu_transcoder));
8336         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8337         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8338
8339         tmp = I915_READ(VTOTAL(cpu_transcoder));
8340         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8341         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8342         tmp = I915_READ(VBLANK(cpu_transcoder));
8343         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8344         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8345         tmp = I915_READ(VSYNC(cpu_transcoder));
8346         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8347         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8348
8349         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8350                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8351                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8352                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8353         }
8354 }
8355
8356 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8357                                     struct intel_crtc_state *pipe_config)
8358 {
8359         struct drm_device *dev = crtc->base.dev;
8360         struct drm_i915_private *dev_priv = to_i915(dev);
8361         u32 tmp;
8362
8363         tmp = I915_READ(PIPESRC(crtc->pipe));
8364         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8365         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8366
8367         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8368         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8369 }
8370
8371 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8372                                  struct intel_crtc_state *pipe_config)
8373 {
8374         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8375         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8376         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8377         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8378
8379         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8380         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8381         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8382         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8383
8384         mode->flags = pipe_config->base.adjusted_mode.flags;
8385         mode->type = DRM_MODE_TYPE_DRIVER;
8386
8387         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8388         mode->flags |= pipe_config->base.adjusted_mode.flags;
8389
8390         mode->hsync = drm_mode_hsync(mode);
8391         mode->vrefresh = drm_mode_vrefresh(mode);
8392         drm_mode_set_name(mode);
8393 }
8394
8395 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8396 {
8397         struct drm_device *dev = intel_crtc->base.dev;
8398         struct drm_i915_private *dev_priv = to_i915(dev);
8399         uint32_t pipeconf;
8400
8401         pipeconf = 0;
8402
8403         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8404             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8405                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8406
8407         if (intel_crtc->config->double_wide)
8408                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8409
8410         /* only g4x and later have fancy bpc/dither controls */
8411         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8412                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8413                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8414                         pipeconf |= PIPECONF_DITHER_EN |
8415                                     PIPECONF_DITHER_TYPE_SP;
8416
8417                 switch (intel_crtc->config->pipe_bpp) {
8418                 case 18:
8419                         pipeconf |= PIPECONF_6BPC;
8420                         break;
8421                 case 24:
8422                         pipeconf |= PIPECONF_8BPC;
8423                         break;
8424                 case 30:
8425                         pipeconf |= PIPECONF_10BPC;
8426                         break;
8427                 default:
8428                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8429                         BUG();
8430                 }
8431         }
8432
8433         if (HAS_PIPE_CXSR(dev)) {
8434                 if (intel_crtc->lowfreq_avail) {
8435                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8436                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8437                 } else {
8438                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8439                 }
8440         }
8441
8442         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8443                 if (INTEL_INFO(dev)->gen < 4 ||
8444                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8445                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8446                 else
8447                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8448         } else
8449                 pipeconf |= PIPECONF_PROGRESSIVE;
8450
8451         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8452              intel_crtc->config->limited_color_range)
8453                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8454
8455         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8456         POSTING_READ(PIPECONF(intel_crtc->pipe));
8457 }
8458
8459 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8460                                    struct intel_crtc_state *crtc_state)
8461 {
8462         struct drm_device *dev = crtc->base.dev;
8463         struct drm_i915_private *dev_priv = to_i915(dev);
8464         const struct intel_limit *limit;
8465         int refclk = 48000;
8466
8467         memset(&crtc_state->dpll_hw_state, 0,
8468                sizeof(crtc_state->dpll_hw_state));
8469
8470         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8471                 if (intel_panel_use_ssc(dev_priv)) {
8472                         refclk = dev_priv->vbt.lvds_ssc_freq;
8473                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8474                 }
8475
8476                 limit = &intel_limits_i8xx_lvds;
8477         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8478                 limit = &intel_limits_i8xx_dvo;
8479         } else {
8480                 limit = &intel_limits_i8xx_dac;
8481         }
8482
8483         if (!crtc_state->clock_set &&
8484             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8485                                  refclk, NULL, &crtc_state->dpll)) {
8486                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8487                 return -EINVAL;
8488         }
8489
8490         i8xx_compute_dpll(crtc, crtc_state, NULL);
8491
8492         return 0;
8493 }
8494
8495 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8496                                   struct intel_crtc_state *crtc_state)
8497 {
8498         struct drm_device *dev = crtc->base.dev;
8499         struct drm_i915_private *dev_priv = to_i915(dev);
8500         const struct intel_limit *limit;
8501         int refclk = 96000;
8502
8503         memset(&crtc_state->dpll_hw_state, 0,
8504                sizeof(crtc_state->dpll_hw_state));
8505
8506         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8507                 if (intel_panel_use_ssc(dev_priv)) {
8508                         refclk = dev_priv->vbt.lvds_ssc_freq;
8509                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8510                 }
8511
8512                 if (intel_is_dual_link_lvds(dev))
8513                         limit = &intel_limits_g4x_dual_channel_lvds;
8514                 else
8515                         limit = &intel_limits_g4x_single_channel_lvds;
8516         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8517                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8518                 limit = &intel_limits_g4x_hdmi;
8519         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8520                 limit = &intel_limits_g4x_sdvo;
8521         } else {
8522                 /* The option is for other outputs */
8523                 limit = &intel_limits_i9xx_sdvo;
8524         }
8525
8526         if (!crtc_state->clock_set &&
8527             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8528                                 refclk, NULL, &crtc_state->dpll)) {
8529                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8530                 return -EINVAL;
8531         }
8532
8533         i9xx_compute_dpll(crtc, crtc_state, NULL);
8534
8535         return 0;
8536 }
8537
8538 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8539                                   struct intel_crtc_state *crtc_state)
8540 {
8541         struct drm_device *dev = crtc->base.dev;
8542         struct drm_i915_private *dev_priv = to_i915(dev);
8543         const struct intel_limit *limit;
8544         int refclk = 96000;
8545
8546         memset(&crtc_state->dpll_hw_state, 0,
8547                sizeof(crtc_state->dpll_hw_state));
8548
8549         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8550                 if (intel_panel_use_ssc(dev_priv)) {
8551                         refclk = dev_priv->vbt.lvds_ssc_freq;
8552                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8553                 }
8554
8555                 limit = &intel_limits_pineview_lvds;
8556         } else {
8557                 limit = &intel_limits_pineview_sdvo;
8558         }
8559
8560         if (!crtc_state->clock_set &&
8561             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8562                                 refclk, NULL, &crtc_state->dpll)) {
8563                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8564                 return -EINVAL;
8565         }
8566
8567         i9xx_compute_dpll(crtc, crtc_state, NULL);
8568
8569         return 0;
8570 }
8571
8572 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8573                                    struct intel_crtc_state *crtc_state)
8574 {
8575         struct drm_device *dev = crtc->base.dev;
8576         struct drm_i915_private *dev_priv = to_i915(dev);
8577         const struct intel_limit *limit;
8578         int refclk = 96000;
8579
8580         memset(&crtc_state->dpll_hw_state, 0,
8581                sizeof(crtc_state->dpll_hw_state));
8582
8583         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8584                 if (intel_panel_use_ssc(dev_priv)) {
8585                         refclk = dev_priv->vbt.lvds_ssc_freq;
8586                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8587                 }
8588
8589                 limit = &intel_limits_i9xx_lvds;
8590         } else {
8591                 limit = &intel_limits_i9xx_sdvo;
8592         }
8593
8594         if (!crtc_state->clock_set &&
8595             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8596                                  refclk, NULL, &crtc_state->dpll)) {
8597                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8598                 return -EINVAL;
8599         }
8600
8601         i9xx_compute_dpll(crtc, crtc_state, NULL);
8602
8603         return 0;
8604 }
8605
8606 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8607                                   struct intel_crtc_state *crtc_state)
8608 {
8609         int refclk = 100000;
8610         const struct intel_limit *limit = &intel_limits_chv;
8611
8612         memset(&crtc_state->dpll_hw_state, 0,
8613                sizeof(crtc_state->dpll_hw_state));
8614
8615         if (!crtc_state->clock_set &&
8616             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8617                                 refclk, NULL, &crtc_state->dpll)) {
8618                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8619                 return -EINVAL;
8620         }
8621
8622         chv_compute_dpll(crtc, crtc_state);
8623
8624         return 0;
8625 }
8626
8627 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8628                                   struct intel_crtc_state *crtc_state)
8629 {
8630         int refclk = 100000;
8631         const struct intel_limit *limit = &intel_limits_vlv;
8632
8633         memset(&crtc_state->dpll_hw_state, 0,
8634                sizeof(crtc_state->dpll_hw_state));
8635
8636         if (!crtc_state->clock_set &&
8637             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8638                                 refclk, NULL, &crtc_state->dpll)) {
8639                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8640                 return -EINVAL;
8641         }
8642
8643         vlv_compute_dpll(crtc, crtc_state);
8644
8645         return 0;
8646 }
8647
8648 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8649                                  struct intel_crtc_state *pipe_config)
8650 {
8651         struct drm_device *dev = crtc->base.dev;
8652         struct drm_i915_private *dev_priv = to_i915(dev);
8653         uint32_t tmp;
8654
8655         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8656                 return;
8657
8658         tmp = I915_READ(PFIT_CONTROL);
8659         if (!(tmp & PFIT_ENABLE))
8660                 return;
8661
8662         /* Check whether the pfit is attached to our pipe. */
8663         if (INTEL_INFO(dev)->gen < 4) {
8664                 if (crtc->pipe != PIPE_B)
8665                         return;
8666         } else {
8667                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8668                         return;
8669         }
8670
8671         pipe_config->gmch_pfit.control = tmp;
8672         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8673 }
8674
8675 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8676                                struct intel_crtc_state *pipe_config)
8677 {
8678         struct drm_device *dev = crtc->base.dev;
8679         struct drm_i915_private *dev_priv = to_i915(dev);
8680         int pipe = pipe_config->cpu_transcoder;
8681         struct dpll clock;
8682         u32 mdiv;
8683         int refclk = 100000;
8684
8685         /* In case of DSI, DPLL will not be used */
8686         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8687                 return;
8688
8689         mutex_lock(&dev_priv->sb_lock);
8690         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8691         mutex_unlock(&dev_priv->sb_lock);
8692
8693         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8694         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8695         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8696         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8697         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8698
8699         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8700 }
8701
8702 static void
8703 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8704                               struct intel_initial_plane_config *plane_config)
8705 {
8706         struct drm_device *dev = crtc->base.dev;
8707         struct drm_i915_private *dev_priv = to_i915(dev);
8708         u32 val, base, offset;
8709         int pipe = crtc->pipe, plane = crtc->plane;
8710         int fourcc, pixel_format;
8711         unsigned int aligned_height;
8712         struct drm_framebuffer *fb;
8713         struct intel_framebuffer *intel_fb;
8714
8715         val = I915_READ(DSPCNTR(plane));
8716         if (!(val & DISPLAY_PLANE_ENABLE))
8717                 return;
8718
8719         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8720         if (!intel_fb) {
8721                 DRM_DEBUG_KMS("failed to alloc fb\n");
8722                 return;
8723         }
8724
8725         fb = &intel_fb->base;
8726
8727         if (INTEL_INFO(dev)->gen >= 4) {
8728                 if (val & DISPPLANE_TILED) {
8729                         plane_config->tiling = I915_TILING_X;
8730                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8731                 }
8732         }
8733
8734         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8735         fourcc = i9xx_format_to_fourcc(pixel_format);
8736         fb->pixel_format = fourcc;
8737         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8738
8739         if (INTEL_INFO(dev)->gen >= 4) {
8740                 if (plane_config->tiling)
8741                         offset = I915_READ(DSPTILEOFF(plane));
8742                 else
8743                         offset = I915_READ(DSPLINOFF(plane));
8744                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8745         } else {
8746                 base = I915_READ(DSPADDR(plane));
8747         }
8748         plane_config->base = base;
8749
8750         val = I915_READ(PIPESRC(pipe));
8751         fb->width = ((val >> 16) & 0xfff) + 1;
8752         fb->height = ((val >> 0) & 0xfff) + 1;
8753
8754         val = I915_READ(DSPSTRIDE(pipe));
8755         fb->pitches[0] = val & 0xffffffc0;
8756
8757         aligned_height = intel_fb_align_height(dev, fb->height,
8758                                                fb->pixel_format,
8759                                                fb->modifier[0]);
8760
8761         plane_config->size = fb->pitches[0] * aligned_height;
8762
8763         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8764                       pipe_name(pipe), plane, fb->width, fb->height,
8765                       fb->bits_per_pixel, base, fb->pitches[0],
8766                       plane_config->size);
8767
8768         plane_config->fb = intel_fb;
8769 }
8770
8771 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8772                                struct intel_crtc_state *pipe_config)
8773 {
8774         struct drm_device *dev = crtc->base.dev;
8775         struct drm_i915_private *dev_priv = to_i915(dev);
8776         int pipe = pipe_config->cpu_transcoder;
8777         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8778         struct dpll clock;
8779         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8780         int refclk = 100000;
8781
8782         /* In case of DSI, DPLL will not be used */
8783         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8784                 return;
8785
8786         mutex_lock(&dev_priv->sb_lock);
8787         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8788         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8789         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8790         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8791         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8792         mutex_unlock(&dev_priv->sb_lock);
8793
8794         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8795         clock.m2 = (pll_dw0 & 0xff) << 22;
8796         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8797                 clock.m2 |= pll_dw2 & 0x3fffff;
8798         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8799         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8800         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8801
8802         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8803 }
8804
8805 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8806                                  struct intel_crtc_state *pipe_config)
8807 {
8808         struct drm_device *dev = crtc->base.dev;
8809         struct drm_i915_private *dev_priv = to_i915(dev);
8810         enum intel_display_power_domain power_domain;
8811         uint32_t tmp;
8812         bool ret;
8813
8814         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8815         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8816                 return false;
8817
8818         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8819         pipe_config->shared_dpll = NULL;
8820
8821         ret = false;
8822
8823         tmp = I915_READ(PIPECONF(crtc->pipe));
8824         if (!(tmp & PIPECONF_ENABLE))
8825                 goto out;
8826
8827         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8828                 switch (tmp & PIPECONF_BPC_MASK) {
8829                 case PIPECONF_6BPC:
8830                         pipe_config->pipe_bpp = 18;
8831                         break;
8832                 case PIPECONF_8BPC:
8833                         pipe_config->pipe_bpp = 24;
8834                         break;
8835                 case PIPECONF_10BPC:
8836                         pipe_config->pipe_bpp = 30;
8837                         break;
8838                 default:
8839                         break;
8840                 }
8841         }
8842
8843         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8844             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8845                 pipe_config->limited_color_range = true;
8846
8847         if (INTEL_INFO(dev)->gen < 4)
8848                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8849
8850         intel_get_pipe_timings(crtc, pipe_config);
8851         intel_get_pipe_src_size(crtc, pipe_config);
8852
8853         i9xx_get_pfit_config(crtc, pipe_config);
8854
8855         if (INTEL_INFO(dev)->gen >= 4) {
8856                 /* No way to read it out on pipes B and C */
8857                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8858                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8859                 else
8860                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8861                 pipe_config->pixel_multiplier =
8862                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8863                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8864                 pipe_config->dpll_hw_state.dpll_md = tmp;
8865         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8866                 tmp = I915_READ(DPLL(crtc->pipe));
8867                 pipe_config->pixel_multiplier =
8868                         ((tmp & SDVO_MULTIPLIER_MASK)
8869                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8870         } else {
8871                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8872                  * port and will be fixed up in the encoder->get_config
8873                  * function. */
8874                 pipe_config->pixel_multiplier = 1;
8875         }
8876         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8877         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8878                 /*
8879                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8880                  * on 830. Filter it out here so that we don't
8881                  * report errors due to that.
8882                  */
8883                 if (IS_I830(dev))
8884                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8885
8886                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8887                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8888         } else {
8889                 /* Mask out read-only status bits. */
8890                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8891                                                      DPLL_PORTC_READY_MASK |
8892                                                      DPLL_PORTB_READY_MASK);
8893         }
8894
8895         if (IS_CHERRYVIEW(dev))
8896                 chv_crtc_clock_get(crtc, pipe_config);
8897         else if (IS_VALLEYVIEW(dev))
8898                 vlv_crtc_clock_get(crtc, pipe_config);
8899         else
8900                 i9xx_crtc_clock_get(crtc, pipe_config);
8901
8902         /*
8903          * Normally the dotclock is filled in by the encoder .get_config()
8904          * but in case the pipe is enabled w/o any ports we need a sane
8905          * default.
8906          */
8907         pipe_config->base.adjusted_mode.crtc_clock =
8908                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8909
8910         ret = true;
8911
8912 out:
8913         intel_display_power_put(dev_priv, power_domain);
8914
8915         return ret;
8916 }
8917
8918 static void ironlake_init_pch_refclk(struct drm_device *dev)
8919 {
8920         struct drm_i915_private *dev_priv = to_i915(dev);
8921         struct intel_encoder *encoder;
8922         int i;
8923         u32 val, final;
8924         bool has_lvds = false;
8925         bool has_cpu_edp = false;
8926         bool has_panel = false;
8927         bool has_ck505 = false;
8928         bool can_ssc = false;
8929         bool using_ssc_source = false;
8930
8931         /* We need to take the global config into account */
8932         for_each_intel_encoder(dev, encoder) {
8933                 switch (encoder->type) {
8934                 case INTEL_OUTPUT_LVDS:
8935                         has_panel = true;
8936                         has_lvds = true;
8937                         break;
8938                 case INTEL_OUTPUT_EDP:
8939                         has_panel = true;
8940                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8941                                 has_cpu_edp = true;
8942                         break;
8943                 default:
8944                         break;
8945                 }
8946         }
8947
8948         if (HAS_PCH_IBX(dev)) {
8949                 has_ck505 = dev_priv->vbt.display_clock_mode;
8950                 can_ssc = has_ck505;
8951         } else {
8952                 has_ck505 = false;
8953                 can_ssc = true;
8954         }
8955
8956         /* Check if any DPLLs are using the SSC source */
8957         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8958                 u32 temp = I915_READ(PCH_DPLL(i));
8959
8960                 if (!(temp & DPLL_VCO_ENABLE))
8961                         continue;
8962
8963                 if ((temp & PLL_REF_INPUT_MASK) ==
8964                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8965                         using_ssc_source = true;
8966                         break;
8967                 }
8968         }
8969
8970         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8971                       has_panel, has_lvds, has_ck505, using_ssc_source);
8972
8973         /* Ironlake: try to setup display ref clock before DPLL
8974          * enabling. This is only under driver's control after
8975          * PCH B stepping, previous chipset stepping should be
8976          * ignoring this setting.
8977          */
8978         val = I915_READ(PCH_DREF_CONTROL);
8979
8980         /* As we must carefully and slowly disable/enable each source in turn,
8981          * compute the final state we want first and check if we need to
8982          * make any changes at all.
8983          */
8984         final = val;
8985         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8986         if (has_ck505)
8987                 final |= DREF_NONSPREAD_CK505_ENABLE;
8988         else
8989                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8990
8991         final &= ~DREF_SSC_SOURCE_MASK;
8992         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8993         final &= ~DREF_SSC1_ENABLE;
8994
8995         if (has_panel) {
8996                 final |= DREF_SSC_SOURCE_ENABLE;
8997
8998                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8999                         final |= DREF_SSC1_ENABLE;
9000
9001                 if (has_cpu_edp) {
9002                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9003                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9004                         else
9005                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9006                 } else
9007                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9008         } else if (using_ssc_source) {
9009                 final |= DREF_SSC_SOURCE_ENABLE;
9010                 final |= DREF_SSC1_ENABLE;
9011         }
9012
9013         if (final == val)
9014                 return;
9015
9016         /* Always enable nonspread source */
9017         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9018
9019         if (has_ck505)
9020                 val |= DREF_NONSPREAD_CK505_ENABLE;
9021         else
9022                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9023
9024         if (has_panel) {
9025                 val &= ~DREF_SSC_SOURCE_MASK;
9026                 val |= DREF_SSC_SOURCE_ENABLE;
9027
9028                 /* SSC must be turned on before enabling the CPU output  */
9029                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9030                         DRM_DEBUG_KMS("Using SSC on panel\n");
9031                         val |= DREF_SSC1_ENABLE;
9032                 } else
9033                         val &= ~DREF_SSC1_ENABLE;
9034
9035                 /* Get SSC going before enabling the outputs */
9036                 I915_WRITE(PCH_DREF_CONTROL, val);
9037                 POSTING_READ(PCH_DREF_CONTROL);
9038                 udelay(200);
9039
9040                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9041
9042                 /* Enable CPU source on CPU attached eDP */
9043                 if (has_cpu_edp) {
9044                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9045                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9046                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9047                         } else
9048                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9049                 } else
9050                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9051
9052                 I915_WRITE(PCH_DREF_CONTROL, val);
9053                 POSTING_READ(PCH_DREF_CONTROL);
9054                 udelay(200);
9055         } else {
9056                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9057
9058                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9059
9060                 /* Turn off CPU output */
9061                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9062
9063                 I915_WRITE(PCH_DREF_CONTROL, val);
9064                 POSTING_READ(PCH_DREF_CONTROL);
9065                 udelay(200);
9066
9067                 if (!using_ssc_source) {
9068                         DRM_DEBUG_KMS("Disabling SSC source\n");
9069
9070                         /* Turn off the SSC source */
9071                         val &= ~DREF_SSC_SOURCE_MASK;
9072                         val |= DREF_SSC_SOURCE_DISABLE;
9073
9074                         /* Turn off SSC1 */
9075                         val &= ~DREF_SSC1_ENABLE;
9076
9077                         I915_WRITE(PCH_DREF_CONTROL, val);
9078                         POSTING_READ(PCH_DREF_CONTROL);
9079                         udelay(200);
9080                 }
9081         }
9082
9083         BUG_ON(val != final);
9084 }
9085
9086 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9087 {
9088         uint32_t tmp;
9089
9090         tmp = I915_READ(SOUTH_CHICKEN2);
9091         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9092         I915_WRITE(SOUTH_CHICKEN2, tmp);
9093
9094         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9095                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9096                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9097
9098         tmp = I915_READ(SOUTH_CHICKEN2);
9099         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9100         I915_WRITE(SOUTH_CHICKEN2, tmp);
9101
9102         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9103                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9104                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9105 }
9106
9107 /* WaMPhyProgramming:hsw */
9108 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9109 {
9110         uint32_t tmp;
9111
9112         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9113         tmp &= ~(0xFF << 24);
9114         tmp |= (0x12 << 24);
9115         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9116
9117         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9118         tmp |= (1 << 11);
9119         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9120
9121         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9122         tmp |= (1 << 11);
9123         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9124
9125         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9126         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9127         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9128
9129         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9130         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9131         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9132
9133         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9134         tmp &= ~(7 << 13);
9135         tmp |= (5 << 13);
9136         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9137
9138         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9139         tmp &= ~(7 << 13);
9140         tmp |= (5 << 13);
9141         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9142
9143         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9144         tmp &= ~0xFF;
9145         tmp |= 0x1C;
9146         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9147
9148         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9149         tmp &= ~0xFF;
9150         tmp |= 0x1C;
9151         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9152
9153         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9154         tmp &= ~(0xFF << 16);
9155         tmp |= (0x1C << 16);
9156         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9157
9158         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9159         tmp &= ~(0xFF << 16);
9160         tmp |= (0x1C << 16);
9161         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9162
9163         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9164         tmp |= (1 << 27);
9165         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9166
9167         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9168         tmp |= (1 << 27);
9169         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9170
9171         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9172         tmp &= ~(0xF << 28);
9173         tmp |= (4 << 28);
9174         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9175
9176         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9177         tmp &= ~(0xF << 28);
9178         tmp |= (4 << 28);
9179         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9180 }
9181
9182 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9183  * Programming" based on the parameters passed:
9184  * - Sequence to enable CLKOUT_DP
9185  * - Sequence to enable CLKOUT_DP without spread
9186  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9187  */
9188 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9189                                  bool with_fdi)
9190 {
9191         struct drm_i915_private *dev_priv = to_i915(dev);
9192         uint32_t reg, tmp;
9193
9194         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9195                 with_spread = true;
9196         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9197                 with_fdi = false;
9198
9199         mutex_lock(&dev_priv->sb_lock);
9200
9201         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9202         tmp &= ~SBI_SSCCTL_DISABLE;
9203         tmp |= SBI_SSCCTL_PATHALT;
9204         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9205
9206         udelay(24);
9207
9208         if (with_spread) {
9209                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9210                 tmp &= ~SBI_SSCCTL_PATHALT;
9211                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9212
9213                 if (with_fdi) {
9214                         lpt_reset_fdi_mphy(dev_priv);
9215                         lpt_program_fdi_mphy(dev_priv);
9216                 }
9217         }
9218
9219         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9220         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9221         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9222         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9223
9224         mutex_unlock(&dev_priv->sb_lock);
9225 }
9226
9227 /* Sequence to disable CLKOUT_DP */
9228 static void lpt_disable_clkout_dp(struct drm_device *dev)
9229 {
9230         struct drm_i915_private *dev_priv = to_i915(dev);
9231         uint32_t reg, tmp;
9232
9233         mutex_lock(&dev_priv->sb_lock);
9234
9235         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9236         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9237         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9238         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9239
9240         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9241         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9242                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9243                         tmp |= SBI_SSCCTL_PATHALT;
9244                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9245                         udelay(32);
9246                 }
9247                 tmp |= SBI_SSCCTL_DISABLE;
9248                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9249         }
9250
9251         mutex_unlock(&dev_priv->sb_lock);
9252 }
9253
9254 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9255
9256 static const uint16_t sscdivintphase[] = {
9257         [BEND_IDX( 50)] = 0x3B23,
9258         [BEND_IDX( 45)] = 0x3B23,
9259         [BEND_IDX( 40)] = 0x3C23,
9260         [BEND_IDX( 35)] = 0x3C23,
9261         [BEND_IDX( 30)] = 0x3D23,
9262         [BEND_IDX( 25)] = 0x3D23,
9263         [BEND_IDX( 20)] = 0x3E23,
9264         [BEND_IDX( 15)] = 0x3E23,
9265         [BEND_IDX( 10)] = 0x3F23,
9266         [BEND_IDX(  5)] = 0x3F23,
9267         [BEND_IDX(  0)] = 0x0025,
9268         [BEND_IDX( -5)] = 0x0025,
9269         [BEND_IDX(-10)] = 0x0125,
9270         [BEND_IDX(-15)] = 0x0125,
9271         [BEND_IDX(-20)] = 0x0225,
9272         [BEND_IDX(-25)] = 0x0225,
9273         [BEND_IDX(-30)] = 0x0325,
9274         [BEND_IDX(-35)] = 0x0325,
9275         [BEND_IDX(-40)] = 0x0425,
9276         [BEND_IDX(-45)] = 0x0425,
9277         [BEND_IDX(-50)] = 0x0525,
9278 };
9279
9280 /*
9281  * Bend CLKOUT_DP
9282  * steps -50 to 50 inclusive, in steps of 5
9283  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9284  * change in clock period = -(steps / 10) * 5.787 ps
9285  */
9286 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9287 {
9288         uint32_t tmp;
9289         int idx = BEND_IDX(steps);
9290
9291         if (WARN_ON(steps % 5 != 0))
9292                 return;
9293
9294         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9295                 return;
9296
9297         mutex_lock(&dev_priv->sb_lock);
9298
9299         if (steps % 10 != 0)
9300                 tmp = 0xAAAAAAAB;
9301         else
9302                 tmp = 0x00000000;
9303         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9304
9305         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9306         tmp &= 0xffff0000;
9307         tmp |= sscdivintphase[idx];
9308         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9309
9310         mutex_unlock(&dev_priv->sb_lock);
9311 }
9312
9313 #undef BEND_IDX
9314
9315 static void lpt_init_pch_refclk(struct drm_device *dev)
9316 {
9317         struct intel_encoder *encoder;
9318         bool has_vga = false;
9319
9320         for_each_intel_encoder(dev, encoder) {
9321                 switch (encoder->type) {
9322                 case INTEL_OUTPUT_ANALOG:
9323                         has_vga = true;
9324                         break;
9325                 default:
9326                         break;
9327                 }
9328         }
9329
9330         if (has_vga) {
9331                 lpt_bend_clkout_dp(to_i915(dev), 0);
9332                 lpt_enable_clkout_dp(dev, true, true);
9333         } else {
9334                 lpt_disable_clkout_dp(dev);
9335         }
9336 }
9337
9338 /*
9339  * Initialize reference clocks when the driver loads
9340  */
9341 void intel_init_pch_refclk(struct drm_device *dev)
9342 {
9343         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9344                 ironlake_init_pch_refclk(dev);
9345         else if (HAS_PCH_LPT(dev))
9346                 lpt_init_pch_refclk(dev);
9347 }
9348
9349 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9350 {
9351         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9353         int pipe = intel_crtc->pipe;
9354         uint32_t val;
9355
9356         val = 0;
9357
9358         switch (intel_crtc->config->pipe_bpp) {
9359         case 18:
9360                 val |= PIPECONF_6BPC;
9361                 break;
9362         case 24:
9363                 val |= PIPECONF_8BPC;
9364                 break;
9365         case 30:
9366                 val |= PIPECONF_10BPC;
9367                 break;
9368         case 36:
9369                 val |= PIPECONF_12BPC;
9370                 break;
9371         default:
9372                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9373                 BUG();
9374         }
9375
9376         if (intel_crtc->config->dither)
9377                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9378
9379         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9380                 val |= PIPECONF_INTERLACED_ILK;
9381         else
9382                 val |= PIPECONF_PROGRESSIVE;
9383
9384         if (intel_crtc->config->limited_color_range)
9385                 val |= PIPECONF_COLOR_RANGE_SELECT;
9386
9387         I915_WRITE(PIPECONF(pipe), val);
9388         POSTING_READ(PIPECONF(pipe));
9389 }
9390
9391 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9392 {
9393         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9395         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9396         u32 val = 0;
9397
9398         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9399                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9400
9401         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9402                 val |= PIPECONF_INTERLACED_ILK;
9403         else
9404                 val |= PIPECONF_PROGRESSIVE;
9405
9406         I915_WRITE(PIPECONF(cpu_transcoder), val);
9407         POSTING_READ(PIPECONF(cpu_transcoder));
9408 }
9409
9410 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9411 {
9412         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9414
9415         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9416                 u32 val = 0;
9417
9418                 switch (intel_crtc->config->pipe_bpp) {
9419                 case 18:
9420                         val |= PIPEMISC_DITHER_6_BPC;
9421                         break;
9422                 case 24:
9423                         val |= PIPEMISC_DITHER_8_BPC;
9424                         break;
9425                 case 30:
9426                         val |= PIPEMISC_DITHER_10_BPC;
9427                         break;
9428                 case 36:
9429                         val |= PIPEMISC_DITHER_12_BPC;
9430                         break;
9431                 default:
9432                         /* Case prevented by pipe_config_set_bpp. */
9433                         BUG();
9434                 }
9435
9436                 if (intel_crtc->config->dither)
9437                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9438
9439                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9440         }
9441 }
9442
9443 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9444 {
9445         /*
9446          * Account for spread spectrum to avoid
9447          * oversubscribing the link. Max center spread
9448          * is 2.5%; use 5% for safety's sake.
9449          */
9450         u32 bps = target_clock * bpp * 21 / 20;
9451         return DIV_ROUND_UP(bps, link_bw * 8);
9452 }
9453
9454 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9455 {
9456         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9457 }
9458
9459 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9460                                   struct intel_crtc_state *crtc_state,
9461                                   struct dpll *reduced_clock)
9462 {
9463         struct drm_crtc *crtc = &intel_crtc->base;
9464         struct drm_device *dev = crtc->dev;
9465         struct drm_i915_private *dev_priv = to_i915(dev);
9466         u32 dpll, fp, fp2;
9467         int factor;
9468
9469         /* Enable autotuning of the PLL clock (if permissible) */
9470         factor = 21;
9471         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9472                 if ((intel_panel_use_ssc(dev_priv) &&
9473                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9474                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9475                         factor = 25;
9476         } else if (crtc_state->sdvo_tv_clock)
9477                 factor = 20;
9478
9479         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9480
9481         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9482                 fp |= FP_CB_TUNE;
9483
9484         if (reduced_clock) {
9485                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9486
9487                 if (reduced_clock->m < factor * reduced_clock->n)
9488                         fp2 |= FP_CB_TUNE;
9489         } else {
9490                 fp2 = fp;
9491         }
9492
9493         dpll = 0;
9494
9495         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9496                 dpll |= DPLLB_MODE_LVDS;
9497         else
9498                 dpll |= DPLLB_MODE_DAC_SERIAL;
9499
9500         dpll |= (crtc_state->pixel_multiplier - 1)
9501                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9502
9503         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9504             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9505                 dpll |= DPLL_SDVO_HIGH_SPEED;
9506
9507         if (intel_crtc_has_dp_encoder(crtc_state))
9508                 dpll |= DPLL_SDVO_HIGH_SPEED;
9509
9510         /* compute bitmask from p1 value */
9511         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9512         /* also FPA1 */
9513         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9514
9515         switch (crtc_state->dpll.p2) {
9516         case 5:
9517                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9518                 break;
9519         case 7:
9520                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9521                 break;
9522         case 10:
9523                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9524                 break;
9525         case 14:
9526                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9527                 break;
9528         }
9529
9530         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9531             intel_panel_use_ssc(dev_priv))
9532                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9533         else
9534                 dpll |= PLL_REF_INPUT_DREFCLK;
9535
9536         dpll |= DPLL_VCO_ENABLE;
9537
9538         crtc_state->dpll_hw_state.dpll = dpll;
9539         crtc_state->dpll_hw_state.fp0 = fp;
9540         crtc_state->dpll_hw_state.fp1 = fp2;
9541 }
9542
9543 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9544                                        struct intel_crtc_state *crtc_state)
9545 {
9546         struct drm_device *dev = crtc->base.dev;
9547         struct drm_i915_private *dev_priv = to_i915(dev);
9548         struct dpll reduced_clock;
9549         bool has_reduced_clock = false;
9550         struct intel_shared_dpll *pll;
9551         const struct intel_limit *limit;
9552         int refclk = 120000;
9553
9554         memset(&crtc_state->dpll_hw_state, 0,
9555                sizeof(crtc_state->dpll_hw_state));
9556
9557         crtc->lowfreq_avail = false;
9558
9559         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9560         if (!crtc_state->has_pch_encoder)
9561                 return 0;
9562
9563         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9564                 if (intel_panel_use_ssc(dev_priv)) {
9565                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9566                                       dev_priv->vbt.lvds_ssc_freq);
9567                         refclk = dev_priv->vbt.lvds_ssc_freq;
9568                 }
9569
9570                 if (intel_is_dual_link_lvds(dev)) {
9571                         if (refclk == 100000)
9572                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9573                         else
9574                                 limit = &intel_limits_ironlake_dual_lvds;
9575                 } else {
9576                         if (refclk == 100000)
9577                                 limit = &intel_limits_ironlake_single_lvds_100m;
9578                         else
9579                                 limit = &intel_limits_ironlake_single_lvds;
9580                 }
9581         } else {
9582                 limit = &intel_limits_ironlake_dac;
9583         }
9584
9585         if (!crtc_state->clock_set &&
9586             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9587                                 refclk, NULL, &crtc_state->dpll)) {
9588                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9589                 return -EINVAL;
9590         }
9591
9592         ironlake_compute_dpll(crtc, crtc_state,
9593                               has_reduced_clock ? &reduced_clock : NULL);
9594
9595         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9596         if (pll == NULL) {
9597                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9598                                  pipe_name(crtc->pipe));
9599                 return -EINVAL;
9600         }
9601
9602         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9603             has_reduced_clock)
9604                 crtc->lowfreq_avail = true;
9605
9606         return 0;
9607 }
9608
9609 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9610                                          struct intel_link_m_n *m_n)
9611 {
9612         struct drm_device *dev = crtc->base.dev;
9613         struct drm_i915_private *dev_priv = to_i915(dev);
9614         enum pipe pipe = crtc->pipe;
9615
9616         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9617         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9618         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9619                 & ~TU_SIZE_MASK;
9620         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9621         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9622                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9623 }
9624
9625 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9626                                          enum transcoder transcoder,
9627                                          struct intel_link_m_n *m_n,
9628                                          struct intel_link_m_n *m2_n2)
9629 {
9630         struct drm_device *dev = crtc->base.dev;
9631         struct drm_i915_private *dev_priv = to_i915(dev);
9632         enum pipe pipe = crtc->pipe;
9633
9634         if (INTEL_INFO(dev)->gen >= 5) {
9635                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9636                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9637                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9638                         & ~TU_SIZE_MASK;
9639                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9640                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9641                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9642                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9643                  * gen < 8) and if DRRS is supported (to make sure the
9644                  * registers are not unnecessarily read).
9645                  */
9646                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9647                         crtc->config->has_drrs) {
9648                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9649                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9650                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9651                                         & ~TU_SIZE_MASK;
9652                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9653                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9654                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9655                 }
9656         } else {
9657                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9658                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9659                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9660                         & ~TU_SIZE_MASK;
9661                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9662                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9663                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9664         }
9665 }
9666
9667 void intel_dp_get_m_n(struct intel_crtc *crtc,
9668                       struct intel_crtc_state *pipe_config)
9669 {
9670         if (pipe_config->has_pch_encoder)
9671                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9672         else
9673                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9674                                              &pipe_config->dp_m_n,
9675                                              &pipe_config->dp_m2_n2);
9676 }
9677
9678 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9679                                         struct intel_crtc_state *pipe_config)
9680 {
9681         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9682                                      &pipe_config->fdi_m_n, NULL);
9683 }
9684
9685 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9686                                     struct intel_crtc_state *pipe_config)
9687 {
9688         struct drm_device *dev = crtc->base.dev;
9689         struct drm_i915_private *dev_priv = to_i915(dev);
9690         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9691         uint32_t ps_ctrl = 0;
9692         int id = -1;
9693         int i;
9694
9695         /* find scaler attached to this pipe */
9696         for (i = 0; i < crtc->num_scalers; i++) {
9697                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9698                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9699                         id = i;
9700                         pipe_config->pch_pfit.enabled = true;
9701                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9702                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9703                         break;
9704                 }
9705         }
9706
9707         scaler_state->scaler_id = id;
9708         if (id >= 0) {
9709                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9710         } else {
9711                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9712         }
9713 }
9714
9715 static void
9716 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9717                                  struct intel_initial_plane_config *plane_config)
9718 {
9719         struct drm_device *dev = crtc->base.dev;
9720         struct drm_i915_private *dev_priv = to_i915(dev);
9721         u32 val, base, offset, stride_mult, tiling;
9722         int pipe = crtc->pipe;
9723         int fourcc, pixel_format;
9724         unsigned int aligned_height;
9725         struct drm_framebuffer *fb;
9726         struct intel_framebuffer *intel_fb;
9727
9728         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9729         if (!intel_fb) {
9730                 DRM_DEBUG_KMS("failed to alloc fb\n");
9731                 return;
9732         }
9733
9734         fb = &intel_fb->base;
9735
9736         val = I915_READ(PLANE_CTL(pipe, 0));
9737         if (!(val & PLANE_CTL_ENABLE))
9738                 goto error;
9739
9740         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9741         fourcc = skl_format_to_fourcc(pixel_format,
9742                                       val & PLANE_CTL_ORDER_RGBX,
9743                                       val & PLANE_CTL_ALPHA_MASK);
9744         fb->pixel_format = fourcc;
9745         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9746
9747         tiling = val & PLANE_CTL_TILED_MASK;
9748         switch (tiling) {
9749         case PLANE_CTL_TILED_LINEAR:
9750                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9751                 break;
9752         case PLANE_CTL_TILED_X:
9753                 plane_config->tiling = I915_TILING_X;
9754                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9755                 break;
9756         case PLANE_CTL_TILED_Y:
9757                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9758                 break;
9759         case PLANE_CTL_TILED_YF:
9760                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9761                 break;
9762         default:
9763                 MISSING_CASE(tiling);
9764                 goto error;
9765         }
9766
9767         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9768         plane_config->base = base;
9769
9770         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9771
9772         val = I915_READ(PLANE_SIZE(pipe, 0));
9773         fb->height = ((val >> 16) & 0xfff) + 1;
9774         fb->width = ((val >> 0) & 0x1fff) + 1;
9775
9776         val = I915_READ(PLANE_STRIDE(pipe, 0));
9777         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9778                                                 fb->pixel_format);
9779         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9780
9781         aligned_height = intel_fb_align_height(dev, fb->height,
9782                                                fb->pixel_format,
9783                                                fb->modifier[0]);
9784
9785         plane_config->size = fb->pitches[0] * aligned_height;
9786
9787         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9788                       pipe_name(pipe), fb->width, fb->height,
9789                       fb->bits_per_pixel, base, fb->pitches[0],
9790                       plane_config->size);
9791
9792         plane_config->fb = intel_fb;
9793         return;
9794
9795 error:
9796         kfree(intel_fb);
9797 }
9798
9799 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9800                                      struct intel_crtc_state *pipe_config)
9801 {
9802         struct drm_device *dev = crtc->base.dev;
9803         struct drm_i915_private *dev_priv = to_i915(dev);
9804         uint32_t tmp;
9805
9806         tmp = I915_READ(PF_CTL(crtc->pipe));
9807
9808         if (tmp & PF_ENABLE) {
9809                 pipe_config->pch_pfit.enabled = true;
9810                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9811                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9812
9813                 /* We currently do not free assignements of panel fitters on
9814                  * ivb/hsw (since we don't use the higher upscaling modes which
9815                  * differentiates them) so just WARN about this case for now. */
9816                 if (IS_GEN7(dev)) {
9817                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9818                                 PF_PIPE_SEL_IVB(crtc->pipe));
9819                 }
9820         }
9821 }
9822
9823 static void
9824 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9825                                   struct intel_initial_plane_config *plane_config)
9826 {
9827         struct drm_device *dev = crtc->base.dev;
9828         struct drm_i915_private *dev_priv = to_i915(dev);
9829         u32 val, base, offset;
9830         int pipe = crtc->pipe;
9831         int fourcc, pixel_format;
9832         unsigned int aligned_height;
9833         struct drm_framebuffer *fb;
9834         struct intel_framebuffer *intel_fb;
9835
9836         val = I915_READ(DSPCNTR(pipe));
9837         if (!(val & DISPLAY_PLANE_ENABLE))
9838                 return;
9839
9840         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9841         if (!intel_fb) {
9842                 DRM_DEBUG_KMS("failed to alloc fb\n");
9843                 return;
9844         }
9845
9846         fb = &intel_fb->base;
9847
9848         if (INTEL_INFO(dev)->gen >= 4) {
9849                 if (val & DISPPLANE_TILED) {
9850                         plane_config->tiling = I915_TILING_X;
9851                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9852                 }
9853         }
9854
9855         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9856         fourcc = i9xx_format_to_fourcc(pixel_format);
9857         fb->pixel_format = fourcc;
9858         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9859
9860         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9861         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9862                 offset = I915_READ(DSPOFFSET(pipe));
9863         } else {
9864                 if (plane_config->tiling)
9865                         offset = I915_READ(DSPTILEOFF(pipe));
9866                 else
9867                         offset = I915_READ(DSPLINOFF(pipe));
9868         }
9869         plane_config->base = base;
9870
9871         val = I915_READ(PIPESRC(pipe));
9872         fb->width = ((val >> 16) & 0xfff) + 1;
9873         fb->height = ((val >> 0) & 0xfff) + 1;
9874
9875         val = I915_READ(DSPSTRIDE(pipe));
9876         fb->pitches[0] = val & 0xffffffc0;
9877
9878         aligned_height = intel_fb_align_height(dev, fb->height,
9879                                                fb->pixel_format,
9880                                                fb->modifier[0]);
9881
9882         plane_config->size = fb->pitches[0] * aligned_height;
9883
9884         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9885                       pipe_name(pipe), fb->width, fb->height,
9886                       fb->bits_per_pixel, base, fb->pitches[0],
9887                       plane_config->size);
9888
9889         plane_config->fb = intel_fb;
9890 }
9891
9892 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9893                                      struct intel_crtc_state *pipe_config)
9894 {
9895         struct drm_device *dev = crtc->base.dev;
9896         struct drm_i915_private *dev_priv = to_i915(dev);
9897         enum intel_display_power_domain power_domain;
9898         uint32_t tmp;
9899         bool ret;
9900
9901         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9902         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9903                 return false;
9904
9905         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9906         pipe_config->shared_dpll = NULL;
9907
9908         ret = false;
9909         tmp = I915_READ(PIPECONF(crtc->pipe));
9910         if (!(tmp & PIPECONF_ENABLE))
9911                 goto out;
9912
9913         switch (tmp & PIPECONF_BPC_MASK) {
9914         case PIPECONF_6BPC:
9915                 pipe_config->pipe_bpp = 18;
9916                 break;
9917         case PIPECONF_8BPC:
9918                 pipe_config->pipe_bpp = 24;
9919                 break;
9920         case PIPECONF_10BPC:
9921                 pipe_config->pipe_bpp = 30;
9922                 break;
9923         case PIPECONF_12BPC:
9924                 pipe_config->pipe_bpp = 36;
9925                 break;
9926         default:
9927                 break;
9928         }
9929
9930         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9931                 pipe_config->limited_color_range = true;
9932
9933         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9934                 struct intel_shared_dpll *pll;
9935                 enum intel_dpll_id pll_id;
9936
9937                 pipe_config->has_pch_encoder = true;
9938
9939                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9940                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9941                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9942
9943                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9944
9945                 if (HAS_PCH_IBX(dev_priv)) {
9946                         /*
9947                          * The pipe->pch transcoder and pch transcoder->pll
9948                          * mapping is fixed.
9949                          */
9950                         pll_id = (enum intel_dpll_id) crtc->pipe;
9951                 } else {
9952                         tmp = I915_READ(PCH_DPLL_SEL);
9953                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9954                                 pll_id = DPLL_ID_PCH_PLL_B;
9955                         else
9956                                 pll_id= DPLL_ID_PCH_PLL_A;
9957                 }
9958
9959                 pipe_config->shared_dpll =
9960                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9961                 pll = pipe_config->shared_dpll;
9962
9963                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9964                                                  &pipe_config->dpll_hw_state));
9965
9966                 tmp = pipe_config->dpll_hw_state.dpll;
9967                 pipe_config->pixel_multiplier =
9968                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9969                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9970
9971                 ironlake_pch_clock_get(crtc, pipe_config);
9972         } else {
9973                 pipe_config->pixel_multiplier = 1;
9974         }
9975
9976         intel_get_pipe_timings(crtc, pipe_config);
9977         intel_get_pipe_src_size(crtc, pipe_config);
9978
9979         ironlake_get_pfit_config(crtc, pipe_config);
9980
9981         ret = true;
9982
9983 out:
9984         intel_display_power_put(dev_priv, power_domain);
9985
9986         return ret;
9987 }
9988
9989 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9990 {
9991         struct drm_device *dev = &dev_priv->drm;
9992         struct intel_crtc *crtc;
9993
9994         for_each_intel_crtc(dev, crtc)
9995                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9996                      pipe_name(crtc->pipe));
9997
9998         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9999         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10000         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10001         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10002         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10003         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10004              "CPU PWM1 enabled\n");
10005         if (IS_HASWELL(dev))
10006                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10007                      "CPU PWM2 enabled\n");
10008         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10009              "PCH PWM1 enabled\n");
10010         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10011              "Utility pin enabled\n");
10012         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10013
10014         /*
10015          * In theory we can still leave IRQs enabled, as long as only the HPD
10016          * interrupts remain enabled. We used to check for that, but since it's
10017          * gen-specific and since we only disable LCPLL after we fully disable
10018          * the interrupts, the check below should be enough.
10019          */
10020         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10021 }
10022
10023 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10024 {
10025         struct drm_device *dev = &dev_priv->drm;
10026
10027         if (IS_HASWELL(dev))
10028                 return I915_READ(D_COMP_HSW);
10029         else
10030                 return I915_READ(D_COMP_BDW);
10031 }
10032
10033 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10034 {
10035         struct drm_device *dev = &dev_priv->drm;
10036
10037         if (IS_HASWELL(dev)) {
10038                 mutex_lock(&dev_priv->rps.hw_lock);
10039                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10040                                             val))
10041                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10042                 mutex_unlock(&dev_priv->rps.hw_lock);
10043         } else {
10044                 I915_WRITE(D_COMP_BDW, val);
10045                 POSTING_READ(D_COMP_BDW);
10046         }
10047 }
10048
10049 /*
10050  * This function implements pieces of two sequences from BSpec:
10051  * - Sequence for display software to disable LCPLL
10052  * - Sequence for display software to allow package C8+
10053  * The steps implemented here are just the steps that actually touch the LCPLL
10054  * register. Callers should take care of disabling all the display engine
10055  * functions, doing the mode unset, fixing interrupts, etc.
10056  */
10057 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10058                               bool switch_to_fclk, bool allow_power_down)
10059 {
10060         uint32_t val;
10061
10062         assert_can_disable_lcpll(dev_priv);
10063
10064         val = I915_READ(LCPLL_CTL);
10065
10066         if (switch_to_fclk) {
10067                 val |= LCPLL_CD_SOURCE_FCLK;
10068                 I915_WRITE(LCPLL_CTL, val);
10069
10070                 if (wait_for_us(I915_READ(LCPLL_CTL) &
10071                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10072                         DRM_ERROR("Switching to FCLK failed\n");
10073
10074                 val = I915_READ(LCPLL_CTL);
10075         }
10076
10077         val |= LCPLL_PLL_DISABLE;
10078         I915_WRITE(LCPLL_CTL, val);
10079         POSTING_READ(LCPLL_CTL);
10080
10081         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10082                 DRM_ERROR("LCPLL still locked\n");
10083
10084         val = hsw_read_dcomp(dev_priv);
10085         val |= D_COMP_COMP_DISABLE;
10086         hsw_write_dcomp(dev_priv, val);
10087         ndelay(100);
10088
10089         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10090                      1))
10091                 DRM_ERROR("D_COMP RCOMP still in progress\n");
10092
10093         if (allow_power_down) {
10094                 val = I915_READ(LCPLL_CTL);
10095                 val |= LCPLL_POWER_DOWN_ALLOW;
10096                 I915_WRITE(LCPLL_CTL, val);
10097                 POSTING_READ(LCPLL_CTL);
10098         }
10099 }
10100
10101 /*
10102  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10103  * source.
10104  */
10105 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10106 {
10107         uint32_t val;
10108
10109         val = I915_READ(LCPLL_CTL);
10110
10111         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10112                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10113                 return;
10114
10115         /*
10116          * Make sure we're not on PC8 state before disabling PC8, otherwise
10117          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10118          */
10119         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10120
10121         if (val & LCPLL_POWER_DOWN_ALLOW) {
10122                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10123                 I915_WRITE(LCPLL_CTL, val);
10124                 POSTING_READ(LCPLL_CTL);
10125         }
10126
10127         val = hsw_read_dcomp(dev_priv);
10128         val |= D_COMP_COMP_FORCE;
10129         val &= ~D_COMP_COMP_DISABLE;
10130         hsw_write_dcomp(dev_priv, val);
10131
10132         val = I915_READ(LCPLL_CTL);
10133         val &= ~LCPLL_PLL_DISABLE;
10134         I915_WRITE(LCPLL_CTL, val);
10135
10136         if (intel_wait_for_register(dev_priv,
10137                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10138                                     5))
10139                 DRM_ERROR("LCPLL not locked yet\n");
10140
10141         if (val & LCPLL_CD_SOURCE_FCLK) {
10142                 val = I915_READ(LCPLL_CTL);
10143                 val &= ~LCPLL_CD_SOURCE_FCLK;
10144                 I915_WRITE(LCPLL_CTL, val);
10145
10146                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10147                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10148                         DRM_ERROR("Switching back to LCPLL failed\n");
10149         }
10150
10151         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10152         intel_update_cdclk(&dev_priv->drm);
10153 }
10154
10155 /*
10156  * Package states C8 and deeper are really deep PC states that can only be
10157  * reached when all the devices on the system allow it, so even if the graphics
10158  * device allows PC8+, it doesn't mean the system will actually get to these
10159  * states. Our driver only allows PC8+ when going into runtime PM.
10160  *
10161  * The requirements for PC8+ are that all the outputs are disabled, the power
10162  * well is disabled and most interrupts are disabled, and these are also
10163  * requirements for runtime PM. When these conditions are met, we manually do
10164  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10165  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10166  * hang the machine.
10167  *
10168  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10169  * the state of some registers, so when we come back from PC8+ we need to
10170  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10171  * need to take care of the registers kept by RC6. Notice that this happens even
10172  * if we don't put the device in PCI D3 state (which is what currently happens
10173  * because of the runtime PM support).
10174  *
10175  * For more, read "Display Sequences for Package C8" on the hardware
10176  * documentation.
10177  */
10178 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10179 {
10180         struct drm_device *dev = &dev_priv->drm;
10181         uint32_t val;
10182
10183         DRM_DEBUG_KMS("Enabling package C8+\n");
10184
10185         if (HAS_PCH_LPT_LP(dev)) {
10186                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10187                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10188                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10189         }
10190
10191         lpt_disable_clkout_dp(dev);
10192         hsw_disable_lcpll(dev_priv, true, true);
10193 }
10194
10195 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10196 {
10197         struct drm_device *dev = &dev_priv->drm;
10198         uint32_t val;
10199
10200         DRM_DEBUG_KMS("Disabling package C8+\n");
10201
10202         hsw_restore_lcpll(dev_priv);
10203         lpt_init_pch_refclk(dev);
10204
10205         if (HAS_PCH_LPT_LP(dev)) {
10206                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10207                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10208                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10209         }
10210 }
10211
10212 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10213 {
10214         struct drm_device *dev = old_state->dev;
10215         struct intel_atomic_state *old_intel_state =
10216                 to_intel_atomic_state(old_state);
10217         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10218
10219         bxt_set_cdclk(to_i915(dev), req_cdclk);
10220 }
10221
10222 /* compute the max rate for new configuration */
10223 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10224 {
10225         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10226         struct drm_i915_private *dev_priv = to_i915(state->dev);
10227         struct drm_crtc *crtc;
10228         struct drm_crtc_state *cstate;
10229         struct intel_crtc_state *crtc_state;
10230         unsigned max_pixel_rate = 0, i;
10231         enum pipe pipe;
10232
10233         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10234                sizeof(intel_state->min_pixclk));
10235
10236         for_each_crtc_in_state(state, crtc, cstate, i) {
10237                 int pixel_rate;
10238
10239                 crtc_state = to_intel_crtc_state(cstate);
10240                 if (!crtc_state->base.enable) {
10241                         intel_state->min_pixclk[i] = 0;
10242                         continue;
10243                 }
10244
10245                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10246
10247                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10248                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10249                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10250
10251                 intel_state->min_pixclk[i] = pixel_rate;
10252         }
10253
10254         for_each_pipe(dev_priv, pipe)
10255                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10256
10257         return max_pixel_rate;
10258 }
10259
10260 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10261 {
10262         struct drm_i915_private *dev_priv = to_i915(dev);
10263         uint32_t val, data;
10264         int ret;
10265
10266         if (WARN((I915_READ(LCPLL_CTL) &
10267                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10268                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10269                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10270                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10271                  "trying to change cdclk frequency with cdclk not enabled\n"))
10272                 return;
10273
10274         mutex_lock(&dev_priv->rps.hw_lock);
10275         ret = sandybridge_pcode_write(dev_priv,
10276                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10277         mutex_unlock(&dev_priv->rps.hw_lock);
10278         if (ret) {
10279                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10280                 return;
10281         }
10282
10283         val = I915_READ(LCPLL_CTL);
10284         val |= LCPLL_CD_SOURCE_FCLK;
10285         I915_WRITE(LCPLL_CTL, val);
10286
10287         if (wait_for_us(I915_READ(LCPLL_CTL) &
10288                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10289                 DRM_ERROR("Switching to FCLK failed\n");
10290
10291         val = I915_READ(LCPLL_CTL);
10292         val &= ~LCPLL_CLK_FREQ_MASK;
10293
10294         switch (cdclk) {
10295         case 450000:
10296                 val |= LCPLL_CLK_FREQ_450;
10297                 data = 0;
10298                 break;
10299         case 540000:
10300                 val |= LCPLL_CLK_FREQ_54O_BDW;
10301                 data = 1;
10302                 break;
10303         case 337500:
10304                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10305                 data = 2;
10306                 break;
10307         case 675000:
10308                 val |= LCPLL_CLK_FREQ_675_BDW;
10309                 data = 3;
10310                 break;
10311         default:
10312                 WARN(1, "invalid cdclk frequency\n");
10313                 return;
10314         }
10315
10316         I915_WRITE(LCPLL_CTL, val);
10317
10318         val = I915_READ(LCPLL_CTL);
10319         val &= ~LCPLL_CD_SOURCE_FCLK;
10320         I915_WRITE(LCPLL_CTL, val);
10321
10322         if (wait_for_us((I915_READ(LCPLL_CTL) &
10323                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10324                 DRM_ERROR("Switching back to LCPLL failed\n");
10325
10326         mutex_lock(&dev_priv->rps.hw_lock);
10327         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10328         mutex_unlock(&dev_priv->rps.hw_lock);
10329
10330         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10331
10332         intel_update_cdclk(dev);
10333
10334         WARN(cdclk != dev_priv->cdclk_freq,
10335              "cdclk requested %d kHz but got %d kHz\n",
10336              cdclk, dev_priv->cdclk_freq);
10337 }
10338
10339 static int broadwell_calc_cdclk(int max_pixclk)
10340 {
10341         if (max_pixclk > 540000)
10342                 return 675000;
10343         else if (max_pixclk > 450000)
10344                 return 540000;
10345         else if (max_pixclk > 337500)
10346                 return 450000;
10347         else
10348                 return 337500;
10349 }
10350
10351 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10352 {
10353         struct drm_i915_private *dev_priv = to_i915(state->dev);
10354         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10355         int max_pixclk = ilk_max_pixel_rate(state);
10356         int cdclk;
10357
10358         /*
10359          * FIXME should also account for plane ratio
10360          * once 64bpp pixel formats are supported.
10361          */
10362         cdclk = broadwell_calc_cdclk(max_pixclk);
10363
10364         if (cdclk > dev_priv->max_cdclk_freq) {
10365                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10366                               cdclk, dev_priv->max_cdclk_freq);
10367                 return -EINVAL;
10368         }
10369
10370         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10371         if (!intel_state->active_crtcs)
10372                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10373
10374         return 0;
10375 }
10376
10377 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10378 {
10379         struct drm_device *dev = old_state->dev;
10380         struct intel_atomic_state *old_intel_state =
10381                 to_intel_atomic_state(old_state);
10382         unsigned req_cdclk = old_intel_state->dev_cdclk;
10383
10384         broadwell_set_cdclk(dev, req_cdclk);
10385 }
10386
10387 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10388 {
10389         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10390         struct drm_i915_private *dev_priv = to_i915(state->dev);
10391         const int max_pixclk = ilk_max_pixel_rate(state);
10392         int vco = intel_state->cdclk_pll_vco;
10393         int cdclk;
10394
10395         /*
10396          * FIXME should also account for plane ratio
10397          * once 64bpp pixel formats are supported.
10398          */
10399         cdclk = skl_calc_cdclk(max_pixclk, vco);
10400
10401         /*
10402          * FIXME move the cdclk caclulation to
10403          * compute_config() so we can fail gracegully.
10404          */
10405         if (cdclk > dev_priv->max_cdclk_freq) {
10406                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10407                           cdclk, dev_priv->max_cdclk_freq);
10408                 cdclk = dev_priv->max_cdclk_freq;
10409         }
10410
10411         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10412         if (!intel_state->active_crtcs)
10413                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10414
10415         return 0;
10416 }
10417
10418 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10419 {
10420         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10421         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10422         unsigned int req_cdclk = intel_state->dev_cdclk;
10423         unsigned int req_vco = intel_state->cdclk_pll_vco;
10424
10425         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10426 }
10427
10428 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10429                                       struct intel_crtc_state *crtc_state)
10430 {
10431         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10432                 if (!intel_ddi_pll_select(crtc, crtc_state))
10433                         return -EINVAL;
10434         }
10435
10436         crtc->lowfreq_avail = false;
10437
10438         return 0;
10439 }
10440
10441 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10442                                 enum port port,
10443                                 struct intel_crtc_state *pipe_config)
10444 {
10445         enum intel_dpll_id id;
10446
10447         switch (port) {
10448         case PORT_A:
10449                 id = DPLL_ID_SKL_DPLL0;
10450                 break;
10451         case PORT_B:
10452                 id = DPLL_ID_SKL_DPLL1;
10453                 break;
10454         case PORT_C:
10455                 id = DPLL_ID_SKL_DPLL2;
10456                 break;
10457         default:
10458                 DRM_ERROR("Incorrect port type\n");
10459                 return;
10460         }
10461
10462         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10463 }
10464
10465 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10466                                 enum port port,
10467                                 struct intel_crtc_state *pipe_config)
10468 {
10469         enum intel_dpll_id id;
10470         u32 temp;
10471
10472         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10473         id = temp >> (port * 3 + 1);
10474
10475         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10476                 return;
10477
10478         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10479 }
10480
10481 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10482                                 enum port port,
10483                                 struct intel_crtc_state *pipe_config)
10484 {
10485         enum intel_dpll_id id;
10486         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10487
10488         switch (ddi_pll_sel) {
10489         case PORT_CLK_SEL_WRPLL1:
10490                 id = DPLL_ID_WRPLL1;
10491                 break;
10492         case PORT_CLK_SEL_WRPLL2:
10493                 id = DPLL_ID_WRPLL2;
10494                 break;
10495         case PORT_CLK_SEL_SPLL:
10496                 id = DPLL_ID_SPLL;
10497                 break;
10498         case PORT_CLK_SEL_LCPLL_810:
10499                 id = DPLL_ID_LCPLL_810;
10500                 break;
10501         case PORT_CLK_SEL_LCPLL_1350:
10502                 id = DPLL_ID_LCPLL_1350;
10503                 break;
10504         case PORT_CLK_SEL_LCPLL_2700:
10505                 id = DPLL_ID_LCPLL_2700;
10506                 break;
10507         default:
10508                 MISSING_CASE(ddi_pll_sel);
10509                 /* fall through */
10510         case PORT_CLK_SEL_NONE:
10511                 return;
10512         }
10513
10514         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10515 }
10516
10517 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10518                                      struct intel_crtc_state *pipe_config,
10519                                      unsigned long *power_domain_mask)
10520 {
10521         struct drm_device *dev = crtc->base.dev;
10522         struct drm_i915_private *dev_priv = to_i915(dev);
10523         enum intel_display_power_domain power_domain;
10524         u32 tmp;
10525
10526         /*
10527          * The pipe->transcoder mapping is fixed with the exception of the eDP
10528          * transcoder handled below.
10529          */
10530         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10531
10532         /*
10533          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10534          * consistency and less surprising code; it's in always on power).
10535          */
10536         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10537         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10538                 enum pipe trans_edp_pipe;
10539                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10540                 default:
10541                         WARN(1, "unknown pipe linked to edp transcoder\n");
10542                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10543                 case TRANS_DDI_EDP_INPUT_A_ON:
10544                         trans_edp_pipe = PIPE_A;
10545                         break;
10546                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10547                         trans_edp_pipe = PIPE_B;
10548                         break;
10549                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10550                         trans_edp_pipe = PIPE_C;
10551                         break;
10552                 }
10553
10554                 if (trans_edp_pipe == crtc->pipe)
10555                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10556         }
10557
10558         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10559         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10560                 return false;
10561         *power_domain_mask |= BIT(power_domain);
10562
10563         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10564
10565         return tmp & PIPECONF_ENABLE;
10566 }
10567
10568 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10569                                          struct intel_crtc_state *pipe_config,
10570                                          unsigned long *power_domain_mask)
10571 {
10572         struct drm_device *dev = crtc->base.dev;
10573         struct drm_i915_private *dev_priv = to_i915(dev);
10574         enum intel_display_power_domain power_domain;
10575         enum port port;
10576         enum transcoder cpu_transcoder;
10577         u32 tmp;
10578
10579         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10580                 if (port == PORT_A)
10581                         cpu_transcoder = TRANSCODER_DSI_A;
10582                 else
10583                         cpu_transcoder = TRANSCODER_DSI_C;
10584
10585                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10586                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10587                         continue;
10588                 *power_domain_mask |= BIT(power_domain);
10589
10590                 /*
10591                  * The PLL needs to be enabled with a valid divider
10592                  * configuration, otherwise accessing DSI registers will hang
10593                  * the machine. See BSpec North Display Engine
10594                  * registers/MIPI[BXT]. We can break out here early, since we
10595                  * need the same DSI PLL to be enabled for both DSI ports.
10596                  */
10597                 if (!intel_dsi_pll_is_enabled(dev_priv))
10598                         break;
10599
10600                 /* XXX: this works for video mode only */
10601                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10602                 if (!(tmp & DPI_ENABLE))
10603                         continue;
10604
10605                 tmp = I915_READ(MIPI_CTRL(port));
10606                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10607                         continue;
10608
10609                 pipe_config->cpu_transcoder = cpu_transcoder;
10610                 break;
10611         }
10612
10613         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10614 }
10615
10616 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10617                                        struct intel_crtc_state *pipe_config)
10618 {
10619         struct drm_device *dev = crtc->base.dev;
10620         struct drm_i915_private *dev_priv = to_i915(dev);
10621         struct intel_shared_dpll *pll;
10622         enum port port;
10623         uint32_t tmp;
10624
10625         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10626
10627         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10628
10629         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10630                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10631         else if (IS_BROXTON(dev))
10632                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10633         else
10634                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10635
10636         pll = pipe_config->shared_dpll;
10637         if (pll) {
10638                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10639                                                  &pipe_config->dpll_hw_state));
10640         }
10641
10642         /*
10643          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10644          * DDI E. So just check whether this pipe is wired to DDI E and whether
10645          * the PCH transcoder is on.
10646          */
10647         if (INTEL_INFO(dev)->gen < 9 &&
10648             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10649                 pipe_config->has_pch_encoder = true;
10650
10651                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10652                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10653                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10654
10655                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10656         }
10657 }
10658
10659 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10660                                     struct intel_crtc_state *pipe_config)
10661 {
10662         struct drm_device *dev = crtc->base.dev;
10663         struct drm_i915_private *dev_priv = to_i915(dev);
10664         enum intel_display_power_domain power_domain;
10665         unsigned long power_domain_mask;
10666         bool active;
10667
10668         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10669         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10670                 return false;
10671         power_domain_mask = BIT(power_domain);
10672
10673         pipe_config->shared_dpll = NULL;
10674
10675         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10676
10677         if (IS_BROXTON(dev_priv) &&
10678             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10679                 WARN_ON(active);
10680                 active = true;
10681         }
10682
10683         if (!active)
10684                 goto out;
10685
10686         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10687                 haswell_get_ddi_port_state(crtc, pipe_config);
10688                 intel_get_pipe_timings(crtc, pipe_config);
10689         }
10690
10691         intel_get_pipe_src_size(crtc, pipe_config);
10692
10693         pipe_config->gamma_mode =
10694                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10695
10696         if (INTEL_INFO(dev)->gen >= 9) {
10697                 skl_init_scalers(dev, crtc, pipe_config);
10698         }
10699
10700         if (INTEL_INFO(dev)->gen >= 9) {
10701                 pipe_config->scaler_state.scaler_id = -1;
10702                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10703         }
10704
10705         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10706         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10707                 power_domain_mask |= BIT(power_domain);
10708                 if (INTEL_INFO(dev)->gen >= 9)
10709                         skylake_get_pfit_config(crtc, pipe_config);
10710                 else
10711                         ironlake_get_pfit_config(crtc, pipe_config);
10712         }
10713
10714         if (IS_HASWELL(dev))
10715                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10716                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10717
10718         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10719             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10720                 pipe_config->pixel_multiplier =
10721                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10722         } else {
10723                 pipe_config->pixel_multiplier = 1;
10724         }
10725
10726 out:
10727         for_each_power_domain(power_domain, power_domain_mask)
10728                 intel_display_power_put(dev_priv, power_domain);
10729
10730         return active;
10731 }
10732
10733 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10734                                const struct intel_plane_state *plane_state)
10735 {
10736         struct drm_device *dev = crtc->dev;
10737         struct drm_i915_private *dev_priv = to_i915(dev);
10738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10739         uint32_t cntl = 0, size = 0;
10740
10741         if (plane_state && plane_state->base.visible) {
10742                 unsigned int width = plane_state->base.crtc_w;
10743                 unsigned int height = plane_state->base.crtc_h;
10744                 unsigned int stride = roundup_pow_of_two(width) * 4;
10745
10746                 switch (stride) {
10747                 default:
10748                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10749                                   width, stride);
10750                         stride = 256;
10751                         /* fallthrough */
10752                 case 256:
10753                 case 512:
10754                 case 1024:
10755                 case 2048:
10756                         break;
10757                 }
10758
10759                 cntl |= CURSOR_ENABLE |
10760                         CURSOR_GAMMA_ENABLE |
10761                         CURSOR_FORMAT_ARGB |
10762                         CURSOR_STRIDE(stride);
10763
10764                 size = (height << 12) | width;
10765         }
10766
10767         if (intel_crtc->cursor_cntl != 0 &&
10768             (intel_crtc->cursor_base != base ||
10769              intel_crtc->cursor_size != size ||
10770              intel_crtc->cursor_cntl != cntl)) {
10771                 /* On these chipsets we can only modify the base/size/stride
10772                  * whilst the cursor is disabled.
10773                  */
10774                 I915_WRITE(CURCNTR(PIPE_A), 0);
10775                 POSTING_READ(CURCNTR(PIPE_A));
10776                 intel_crtc->cursor_cntl = 0;
10777         }
10778
10779         if (intel_crtc->cursor_base != base) {
10780                 I915_WRITE(CURBASE(PIPE_A), base);
10781                 intel_crtc->cursor_base = base;
10782         }
10783
10784         if (intel_crtc->cursor_size != size) {
10785                 I915_WRITE(CURSIZE, size);
10786                 intel_crtc->cursor_size = size;
10787         }
10788
10789         if (intel_crtc->cursor_cntl != cntl) {
10790                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10791                 POSTING_READ(CURCNTR(PIPE_A));
10792                 intel_crtc->cursor_cntl = cntl;
10793         }
10794 }
10795
10796 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10797                                const struct intel_plane_state *plane_state)
10798 {
10799         struct drm_device *dev = crtc->dev;
10800         struct drm_i915_private *dev_priv = to_i915(dev);
10801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10802         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10803         int pipe = intel_crtc->pipe;
10804         uint32_t cntl = 0;
10805
10806         if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10807                 skl_write_cursor_wm(intel_crtc, wm);
10808
10809         if (plane_state && plane_state->base.visible) {
10810                 cntl = MCURSOR_GAMMA_ENABLE;
10811                 switch (plane_state->base.crtc_w) {
10812                         case 64:
10813                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10814                                 break;
10815                         case 128:
10816                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10817                                 break;
10818                         case 256:
10819                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10820                                 break;
10821                         default:
10822                                 MISSING_CASE(plane_state->base.crtc_w);
10823                                 return;
10824                 }
10825                 cntl |= pipe << 28; /* Connect to correct pipe */
10826
10827                 if (HAS_DDI(dev))
10828                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10829
10830                 if (plane_state->base.rotation == DRM_ROTATE_180)
10831                         cntl |= CURSOR_ROTATE_180;
10832         }
10833
10834         if (intel_crtc->cursor_cntl != cntl) {
10835                 I915_WRITE(CURCNTR(pipe), cntl);
10836                 POSTING_READ(CURCNTR(pipe));
10837                 intel_crtc->cursor_cntl = cntl;
10838         }
10839
10840         /* and commit changes on next vblank */
10841         I915_WRITE(CURBASE(pipe), base);
10842         POSTING_READ(CURBASE(pipe));
10843
10844         intel_crtc->cursor_base = base;
10845 }
10846
10847 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10848 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10849                                      const struct intel_plane_state *plane_state)
10850 {
10851         struct drm_device *dev = crtc->dev;
10852         struct drm_i915_private *dev_priv = to_i915(dev);
10853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10854         int pipe = intel_crtc->pipe;
10855         u32 base = intel_crtc->cursor_addr;
10856         u32 pos = 0;
10857
10858         if (plane_state) {
10859                 int x = plane_state->base.crtc_x;
10860                 int y = plane_state->base.crtc_y;
10861
10862                 if (x < 0) {
10863                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10864                         x = -x;
10865                 }
10866                 pos |= x << CURSOR_X_SHIFT;
10867
10868                 if (y < 0) {
10869                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10870                         y = -y;
10871                 }
10872                 pos |= y << CURSOR_Y_SHIFT;
10873
10874                 /* ILK+ do this automagically */
10875                 if (HAS_GMCH_DISPLAY(dev) &&
10876                     plane_state->base.rotation == DRM_ROTATE_180) {
10877                         base += (plane_state->base.crtc_h *
10878                                  plane_state->base.crtc_w - 1) * 4;
10879                 }
10880         }
10881
10882         I915_WRITE(CURPOS(pipe), pos);
10883
10884         if (IS_845G(dev) || IS_I865G(dev))
10885                 i845_update_cursor(crtc, base, plane_state);
10886         else
10887                 i9xx_update_cursor(crtc, base, plane_state);
10888 }
10889
10890 static bool cursor_size_ok(struct drm_device *dev,
10891                            uint32_t width, uint32_t height)
10892 {
10893         if (width == 0 || height == 0)
10894                 return false;
10895
10896         /*
10897          * 845g/865g are special in that they are only limited by
10898          * the width of their cursors, the height is arbitrary up to
10899          * the precision of the register. Everything else requires
10900          * square cursors, limited to a few power-of-two sizes.
10901          */
10902         if (IS_845G(dev) || IS_I865G(dev)) {
10903                 if ((width & 63) != 0)
10904                         return false;
10905
10906                 if (width > (IS_845G(dev) ? 64 : 512))
10907                         return false;
10908
10909                 if (height > 1023)
10910                         return false;
10911         } else {
10912                 switch (width | height) {
10913                 case 256:
10914                 case 128:
10915                         if (IS_GEN2(dev))
10916                                 return false;
10917                 case 64:
10918                         break;
10919                 default:
10920                         return false;
10921                 }
10922         }
10923
10924         return true;
10925 }
10926
10927 /* VESA 640x480x72Hz mode to set on the pipe */
10928 static struct drm_display_mode load_detect_mode = {
10929         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10930                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10931 };
10932
10933 struct drm_framebuffer *
10934 __intel_framebuffer_create(struct drm_device *dev,
10935                            struct drm_mode_fb_cmd2 *mode_cmd,
10936                            struct drm_i915_gem_object *obj)
10937 {
10938         struct intel_framebuffer *intel_fb;
10939         int ret;
10940
10941         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10942         if (!intel_fb)
10943                 return ERR_PTR(-ENOMEM);
10944
10945         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10946         if (ret)
10947                 goto err;
10948
10949         return &intel_fb->base;
10950
10951 err:
10952         kfree(intel_fb);
10953         return ERR_PTR(ret);
10954 }
10955
10956 static struct drm_framebuffer *
10957 intel_framebuffer_create(struct drm_device *dev,
10958                          struct drm_mode_fb_cmd2 *mode_cmd,
10959                          struct drm_i915_gem_object *obj)
10960 {
10961         struct drm_framebuffer *fb;
10962         int ret;
10963
10964         ret = i915_mutex_lock_interruptible(dev);
10965         if (ret)
10966                 return ERR_PTR(ret);
10967         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10968         mutex_unlock(&dev->struct_mutex);
10969
10970         return fb;
10971 }
10972
10973 static u32
10974 intel_framebuffer_pitch_for_width(int width, int bpp)
10975 {
10976         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10977         return ALIGN(pitch, 64);
10978 }
10979
10980 static u32
10981 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10982 {
10983         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10984         return PAGE_ALIGN(pitch * mode->vdisplay);
10985 }
10986
10987 static struct drm_framebuffer *
10988 intel_framebuffer_create_for_mode(struct drm_device *dev,
10989                                   struct drm_display_mode *mode,
10990                                   int depth, int bpp)
10991 {
10992         struct drm_framebuffer *fb;
10993         struct drm_i915_gem_object *obj;
10994         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10995
10996         obj = i915_gem_object_create(dev,
10997                                     intel_framebuffer_size_for_mode(mode, bpp));
10998         if (IS_ERR(obj))
10999                 return ERR_CAST(obj);
11000
11001         mode_cmd.width = mode->hdisplay;
11002         mode_cmd.height = mode->vdisplay;
11003         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11004                                                                 bpp);
11005         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11006
11007         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11008         if (IS_ERR(fb))
11009                 i915_gem_object_put_unlocked(obj);
11010
11011         return fb;
11012 }
11013
11014 static struct drm_framebuffer *
11015 mode_fits_in_fbdev(struct drm_device *dev,
11016                    struct drm_display_mode *mode)
11017 {
11018 #ifdef CONFIG_DRM_FBDEV_EMULATION
11019         struct drm_i915_private *dev_priv = to_i915(dev);
11020         struct drm_i915_gem_object *obj;
11021         struct drm_framebuffer *fb;
11022
11023         if (!dev_priv->fbdev)
11024                 return NULL;
11025
11026         if (!dev_priv->fbdev->fb)
11027                 return NULL;
11028
11029         obj = dev_priv->fbdev->fb->obj;
11030         BUG_ON(!obj);
11031
11032         fb = &dev_priv->fbdev->fb->base;
11033         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11034                                                                fb->bits_per_pixel))
11035                 return NULL;
11036
11037         if (obj->base.size < mode->vdisplay * fb->pitches[0])
11038                 return NULL;
11039
11040         drm_framebuffer_reference(fb);
11041         return fb;
11042 #else
11043         return NULL;
11044 #endif
11045 }
11046
11047 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11048                                            struct drm_crtc *crtc,
11049                                            struct drm_display_mode *mode,
11050                                            struct drm_framebuffer *fb,
11051                                            int x, int y)
11052 {
11053         struct drm_plane_state *plane_state;
11054         int hdisplay, vdisplay;
11055         int ret;
11056
11057         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11058         if (IS_ERR(plane_state))
11059                 return PTR_ERR(plane_state);
11060
11061         if (mode)
11062                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11063         else
11064                 hdisplay = vdisplay = 0;
11065
11066         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11067         if (ret)
11068                 return ret;
11069         drm_atomic_set_fb_for_plane(plane_state, fb);
11070         plane_state->crtc_x = 0;
11071         plane_state->crtc_y = 0;
11072         plane_state->crtc_w = hdisplay;
11073         plane_state->crtc_h = vdisplay;
11074         plane_state->src_x = x << 16;
11075         plane_state->src_y = y << 16;
11076         plane_state->src_w = hdisplay << 16;
11077         plane_state->src_h = vdisplay << 16;
11078
11079         return 0;
11080 }
11081
11082 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11083                                 struct drm_display_mode *mode,
11084                                 struct intel_load_detect_pipe *old,
11085                                 struct drm_modeset_acquire_ctx *ctx)
11086 {
11087         struct intel_crtc *intel_crtc;
11088         struct intel_encoder *intel_encoder =
11089                 intel_attached_encoder(connector);
11090         struct drm_crtc *possible_crtc;
11091         struct drm_encoder *encoder = &intel_encoder->base;
11092         struct drm_crtc *crtc = NULL;
11093         struct drm_device *dev = encoder->dev;
11094         struct drm_framebuffer *fb;
11095         struct drm_mode_config *config = &dev->mode_config;
11096         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11097         struct drm_connector_state *connector_state;
11098         struct intel_crtc_state *crtc_state;
11099         int ret, i = -1;
11100
11101         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11102                       connector->base.id, connector->name,
11103                       encoder->base.id, encoder->name);
11104
11105         old->restore_state = NULL;
11106
11107 retry:
11108         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11109         if (ret)
11110                 goto fail;
11111
11112         /*
11113          * Algorithm gets a little messy:
11114          *
11115          *   - if the connector already has an assigned crtc, use it (but make
11116          *     sure it's on first)
11117          *
11118          *   - try to find the first unused crtc that can drive this connector,
11119          *     and use that if we find one
11120          */
11121
11122         /* See if we already have a CRTC for this connector */
11123         if (connector->state->crtc) {
11124                 crtc = connector->state->crtc;
11125
11126                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11127                 if (ret)
11128                         goto fail;
11129
11130                 /* Make sure the crtc and connector are running */
11131                 goto found;
11132         }
11133
11134         /* Find an unused one (if possible) */
11135         for_each_crtc(dev, possible_crtc) {
11136                 i++;
11137                 if (!(encoder->possible_crtcs & (1 << i)))
11138                         continue;
11139
11140                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11141                 if (ret)
11142                         goto fail;
11143
11144                 if (possible_crtc->state->enable) {
11145                         drm_modeset_unlock(&possible_crtc->mutex);
11146                         continue;
11147                 }
11148
11149                 crtc = possible_crtc;
11150                 break;
11151         }
11152
11153         /*
11154          * If we didn't find an unused CRTC, don't use any.
11155          */
11156         if (!crtc) {
11157                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11158                 goto fail;
11159         }
11160
11161 found:
11162         intel_crtc = to_intel_crtc(crtc);
11163
11164         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11165         if (ret)
11166                 goto fail;
11167
11168         state = drm_atomic_state_alloc(dev);
11169         restore_state = drm_atomic_state_alloc(dev);
11170         if (!state || !restore_state) {
11171                 ret = -ENOMEM;
11172                 goto fail;
11173         }
11174
11175         state->acquire_ctx = ctx;
11176         restore_state->acquire_ctx = ctx;
11177
11178         connector_state = drm_atomic_get_connector_state(state, connector);
11179         if (IS_ERR(connector_state)) {
11180                 ret = PTR_ERR(connector_state);
11181                 goto fail;
11182         }
11183
11184         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11185         if (ret)
11186                 goto fail;
11187
11188         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11189         if (IS_ERR(crtc_state)) {
11190                 ret = PTR_ERR(crtc_state);
11191                 goto fail;
11192         }
11193
11194         crtc_state->base.active = crtc_state->base.enable = true;
11195
11196         if (!mode)
11197                 mode = &load_detect_mode;
11198
11199         /* We need a framebuffer large enough to accommodate all accesses
11200          * that the plane may generate whilst we perform load detection.
11201          * We can not rely on the fbcon either being present (we get called
11202          * during its initialisation to detect all boot displays, or it may
11203          * not even exist) or that it is large enough to satisfy the
11204          * requested mode.
11205          */
11206         fb = mode_fits_in_fbdev(dev, mode);
11207         if (fb == NULL) {
11208                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11209                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11210         } else
11211                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11212         if (IS_ERR(fb)) {
11213                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11214                 goto fail;
11215         }
11216
11217         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11218         if (ret)
11219                 goto fail;
11220
11221         drm_framebuffer_unreference(fb);
11222
11223         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11224         if (ret)
11225                 goto fail;
11226
11227         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11228         if (!ret)
11229                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11230         if (!ret)
11231                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11232         if (ret) {
11233                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11234                 goto fail;
11235         }
11236
11237         ret = drm_atomic_commit(state);
11238         if (ret) {
11239                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11240                 goto fail;
11241         }
11242
11243         old->restore_state = restore_state;
11244
11245         /* let the connector get through one full cycle before testing */
11246         intel_wait_for_vblank(dev, intel_crtc->pipe);
11247         return true;
11248
11249 fail:
11250         drm_atomic_state_free(state);
11251         drm_atomic_state_free(restore_state);
11252         restore_state = state = NULL;
11253
11254         if (ret == -EDEADLK) {
11255                 drm_modeset_backoff(ctx);
11256                 goto retry;
11257         }
11258
11259         return false;
11260 }
11261
11262 void intel_release_load_detect_pipe(struct drm_connector *connector,
11263                                     struct intel_load_detect_pipe *old,
11264                                     struct drm_modeset_acquire_ctx *ctx)
11265 {
11266         struct intel_encoder *intel_encoder =
11267                 intel_attached_encoder(connector);
11268         struct drm_encoder *encoder = &intel_encoder->base;
11269         struct drm_atomic_state *state = old->restore_state;
11270         int ret;
11271
11272         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11273                       connector->base.id, connector->name,
11274                       encoder->base.id, encoder->name);
11275
11276         if (!state)
11277                 return;
11278
11279         ret = drm_atomic_commit(state);
11280         if (ret) {
11281                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11282                 drm_atomic_state_free(state);
11283         }
11284 }
11285
11286 static int i9xx_pll_refclk(struct drm_device *dev,
11287                            const struct intel_crtc_state *pipe_config)
11288 {
11289         struct drm_i915_private *dev_priv = to_i915(dev);
11290         u32 dpll = pipe_config->dpll_hw_state.dpll;
11291
11292         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11293                 return dev_priv->vbt.lvds_ssc_freq;
11294         else if (HAS_PCH_SPLIT(dev))
11295                 return 120000;
11296         else if (!IS_GEN2(dev))
11297                 return 96000;
11298         else
11299                 return 48000;
11300 }
11301
11302 /* Returns the clock of the currently programmed mode of the given pipe. */
11303 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11304                                 struct intel_crtc_state *pipe_config)
11305 {
11306         struct drm_device *dev = crtc->base.dev;
11307         struct drm_i915_private *dev_priv = to_i915(dev);
11308         int pipe = pipe_config->cpu_transcoder;
11309         u32 dpll = pipe_config->dpll_hw_state.dpll;
11310         u32 fp;
11311         struct dpll clock;
11312         int port_clock;
11313         int refclk = i9xx_pll_refclk(dev, pipe_config);
11314
11315         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11316                 fp = pipe_config->dpll_hw_state.fp0;
11317         else
11318                 fp = pipe_config->dpll_hw_state.fp1;
11319
11320         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11321         if (IS_PINEVIEW(dev)) {
11322                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11323                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11324         } else {
11325                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11326                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11327         }
11328
11329         if (!IS_GEN2(dev)) {
11330                 if (IS_PINEVIEW(dev))
11331                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11332                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11333                 else
11334                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11335                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11336
11337                 switch (dpll & DPLL_MODE_MASK) {
11338                 case DPLLB_MODE_DAC_SERIAL:
11339                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11340                                 5 : 10;
11341                         break;
11342                 case DPLLB_MODE_LVDS:
11343                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11344                                 7 : 14;
11345                         break;
11346                 default:
11347                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11348                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11349                         return;
11350                 }
11351
11352                 if (IS_PINEVIEW(dev))
11353                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11354                 else
11355                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11356         } else {
11357                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11358                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11359
11360                 if (is_lvds) {
11361                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11362                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11363
11364                         if (lvds & LVDS_CLKB_POWER_UP)
11365                                 clock.p2 = 7;
11366                         else
11367                                 clock.p2 = 14;
11368                 } else {
11369                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11370                                 clock.p1 = 2;
11371                         else {
11372                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11373                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11374                         }
11375                         if (dpll & PLL_P2_DIVIDE_BY_4)
11376                                 clock.p2 = 4;
11377                         else
11378                                 clock.p2 = 2;
11379                 }
11380
11381                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11382         }
11383
11384         /*
11385          * This value includes pixel_multiplier. We will use
11386          * port_clock to compute adjusted_mode.crtc_clock in the
11387          * encoder's get_config() function.
11388          */
11389         pipe_config->port_clock = port_clock;
11390 }
11391
11392 int intel_dotclock_calculate(int link_freq,
11393                              const struct intel_link_m_n *m_n)
11394 {
11395         /*
11396          * The calculation for the data clock is:
11397          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11398          * But we want to avoid losing precison if possible, so:
11399          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11400          *
11401          * and the link clock is simpler:
11402          * link_clock = (m * link_clock) / n
11403          */
11404
11405         if (!m_n->link_n)
11406                 return 0;
11407
11408         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11409 }
11410
11411 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11412                                    struct intel_crtc_state *pipe_config)
11413 {
11414         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11415
11416         /* read out port_clock from the DPLL */
11417         i9xx_crtc_clock_get(crtc, pipe_config);
11418
11419         /*
11420          * In case there is an active pipe without active ports,
11421          * we may need some idea for the dotclock anyway.
11422          * Calculate one based on the FDI configuration.
11423          */
11424         pipe_config->base.adjusted_mode.crtc_clock =
11425                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11426                                          &pipe_config->fdi_m_n);
11427 }
11428
11429 /** Returns the currently programmed mode of the given pipe. */
11430 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11431                                              struct drm_crtc *crtc)
11432 {
11433         struct drm_i915_private *dev_priv = to_i915(dev);
11434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11435         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11436         struct drm_display_mode *mode;
11437         struct intel_crtc_state *pipe_config;
11438         int htot = I915_READ(HTOTAL(cpu_transcoder));
11439         int hsync = I915_READ(HSYNC(cpu_transcoder));
11440         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11441         int vsync = I915_READ(VSYNC(cpu_transcoder));
11442         enum pipe pipe = intel_crtc->pipe;
11443
11444         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11445         if (!mode)
11446                 return NULL;
11447
11448         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11449         if (!pipe_config) {
11450                 kfree(mode);
11451                 return NULL;
11452         }
11453
11454         /*
11455          * Construct a pipe_config sufficient for getting the clock info
11456          * back out of crtc_clock_get.
11457          *
11458          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11459          * to use a real value here instead.
11460          */
11461         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11462         pipe_config->pixel_multiplier = 1;
11463         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11464         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11465         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11466         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11467
11468         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11469         mode->hdisplay = (htot & 0xffff) + 1;
11470         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11471         mode->hsync_start = (hsync & 0xffff) + 1;
11472         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11473         mode->vdisplay = (vtot & 0xffff) + 1;
11474         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11475         mode->vsync_start = (vsync & 0xffff) + 1;
11476         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11477
11478         drm_mode_set_name(mode);
11479
11480         kfree(pipe_config);
11481
11482         return mode;
11483 }
11484
11485 static void intel_crtc_destroy(struct drm_crtc *crtc)
11486 {
11487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11488         struct drm_device *dev = crtc->dev;
11489         struct intel_flip_work *work;
11490
11491         spin_lock_irq(&dev->event_lock);
11492         work = intel_crtc->flip_work;
11493         intel_crtc->flip_work = NULL;
11494         spin_unlock_irq(&dev->event_lock);
11495
11496         if (work) {
11497                 cancel_work_sync(&work->mmio_work);
11498                 cancel_work_sync(&work->unpin_work);
11499                 kfree(work);
11500         }
11501
11502         drm_crtc_cleanup(crtc);
11503
11504         kfree(intel_crtc);
11505 }
11506
11507 static void intel_unpin_work_fn(struct work_struct *__work)
11508 {
11509         struct intel_flip_work *work =
11510                 container_of(__work, struct intel_flip_work, unpin_work);
11511         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11512         struct drm_device *dev = crtc->base.dev;
11513         struct drm_plane *primary = crtc->base.primary;
11514
11515         if (is_mmio_work(work))
11516                 flush_work(&work->mmio_work);
11517
11518         mutex_lock(&dev->struct_mutex);
11519         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11520         i915_gem_object_put(work->pending_flip_obj);
11521         mutex_unlock(&dev->struct_mutex);
11522
11523         i915_gem_request_put(work->flip_queued_req);
11524
11525         intel_frontbuffer_flip_complete(to_i915(dev),
11526                                         to_intel_plane(primary)->frontbuffer_bit);
11527         intel_fbc_post_update(crtc);
11528         drm_framebuffer_unreference(work->old_fb);
11529
11530         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11531         atomic_dec(&crtc->unpin_work_count);
11532
11533         kfree(work);
11534 }
11535
11536 /* Is 'a' after or equal to 'b'? */
11537 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11538 {
11539         return !((a - b) & 0x80000000);
11540 }
11541
11542 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11543                                    struct intel_flip_work *work)
11544 {
11545         struct drm_device *dev = crtc->base.dev;
11546         struct drm_i915_private *dev_priv = to_i915(dev);
11547
11548         if (abort_flip_on_reset(crtc))
11549                 return true;
11550
11551         /*
11552          * The relevant registers doen't exist on pre-ctg.
11553          * As the flip done interrupt doesn't trigger for mmio
11554          * flips on gmch platforms, a flip count check isn't
11555          * really needed there. But since ctg has the registers,
11556          * include it in the check anyway.
11557          */
11558         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11559                 return true;
11560
11561         /*
11562          * BDW signals flip done immediately if the plane
11563          * is disabled, even if the plane enable is already
11564          * armed to occur at the next vblank :(
11565          */
11566
11567         /*
11568          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11569          * used the same base address. In that case the mmio flip might
11570          * have completed, but the CS hasn't even executed the flip yet.
11571          *
11572          * A flip count check isn't enough as the CS might have updated
11573          * the base address just after start of vblank, but before we
11574          * managed to process the interrupt. This means we'd complete the
11575          * CS flip too soon.
11576          *
11577          * Combining both checks should get us a good enough result. It may
11578          * still happen that the CS flip has been executed, but has not
11579          * yet actually completed. But in case the base address is the same
11580          * anyway, we don't really care.
11581          */
11582         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11583                 crtc->flip_work->gtt_offset &&
11584                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11585                                     crtc->flip_work->flip_count);
11586 }
11587
11588 static bool
11589 __pageflip_finished_mmio(struct intel_crtc *crtc,
11590                                struct intel_flip_work *work)
11591 {
11592         /*
11593          * MMIO work completes when vblank is different from
11594          * flip_queued_vblank.
11595          *
11596          * Reset counter value doesn't matter, this is handled by
11597          * i915_wait_request finishing early, so no need to handle
11598          * reset here.
11599          */
11600         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11601 }
11602
11603
11604 static bool pageflip_finished(struct intel_crtc *crtc,
11605                               struct intel_flip_work *work)
11606 {
11607         if (!atomic_read(&work->pending))
11608                 return false;
11609
11610         smp_rmb();
11611
11612         if (is_mmio_work(work))
11613                 return __pageflip_finished_mmio(crtc, work);
11614         else
11615                 return __pageflip_finished_cs(crtc, work);
11616 }
11617
11618 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11619 {
11620         struct drm_device *dev = &dev_priv->drm;
11621         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11623         struct intel_flip_work *work;
11624         unsigned long flags;
11625
11626         /* Ignore early vblank irqs */
11627         if (!crtc)
11628                 return;
11629
11630         /*
11631          * This is called both by irq handlers and the reset code (to complete
11632          * lost pageflips) so needs the full irqsave spinlocks.
11633          */
11634         spin_lock_irqsave(&dev->event_lock, flags);
11635         work = intel_crtc->flip_work;
11636
11637         if (work != NULL &&
11638             !is_mmio_work(work) &&
11639             pageflip_finished(intel_crtc, work))
11640                 page_flip_completed(intel_crtc);
11641
11642         spin_unlock_irqrestore(&dev->event_lock, flags);
11643 }
11644
11645 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11646 {
11647         struct drm_device *dev = &dev_priv->drm;
11648         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11650         struct intel_flip_work *work;
11651         unsigned long flags;
11652
11653         /* Ignore early vblank irqs */
11654         if (!crtc)
11655                 return;
11656
11657         /*
11658          * This is called both by irq handlers and the reset code (to complete
11659          * lost pageflips) so needs the full irqsave spinlocks.
11660          */
11661         spin_lock_irqsave(&dev->event_lock, flags);
11662         work = intel_crtc->flip_work;
11663
11664         if (work != NULL &&
11665             is_mmio_work(work) &&
11666             pageflip_finished(intel_crtc, work))
11667                 page_flip_completed(intel_crtc);
11668
11669         spin_unlock_irqrestore(&dev->event_lock, flags);
11670 }
11671
11672 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11673                                                struct intel_flip_work *work)
11674 {
11675         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11676
11677         /* Ensure that the work item is consistent when activating it ... */
11678         smp_mb__before_atomic();
11679         atomic_set(&work->pending, 1);
11680 }
11681
11682 static int intel_gen2_queue_flip(struct drm_device *dev,
11683                                  struct drm_crtc *crtc,
11684                                  struct drm_framebuffer *fb,
11685                                  struct drm_i915_gem_object *obj,
11686                                  struct drm_i915_gem_request *req,
11687                                  uint32_t flags)
11688 {
11689         struct intel_ring *ring = req->ring;
11690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11691         u32 flip_mask;
11692         int ret;
11693
11694         ret = intel_ring_begin(req, 6);
11695         if (ret)
11696                 return ret;
11697
11698         /* Can't queue multiple flips, so wait for the previous
11699          * one to finish before executing the next.
11700          */
11701         if (intel_crtc->plane)
11702                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11703         else
11704                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11705         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11706         intel_ring_emit(ring, MI_NOOP);
11707         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11708                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11709         intel_ring_emit(ring, fb->pitches[0]);
11710         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11711         intel_ring_emit(ring, 0); /* aux display base address, unused */
11712
11713         return 0;
11714 }
11715
11716 static int intel_gen3_queue_flip(struct drm_device *dev,
11717                                  struct drm_crtc *crtc,
11718                                  struct drm_framebuffer *fb,
11719                                  struct drm_i915_gem_object *obj,
11720                                  struct drm_i915_gem_request *req,
11721                                  uint32_t flags)
11722 {
11723         struct intel_ring *ring = req->ring;
11724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11725         u32 flip_mask;
11726         int ret;
11727
11728         ret = intel_ring_begin(req, 6);
11729         if (ret)
11730                 return ret;
11731
11732         if (intel_crtc->plane)
11733                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11734         else
11735                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11736         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11737         intel_ring_emit(ring, MI_NOOP);
11738         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11739                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11740         intel_ring_emit(ring, fb->pitches[0]);
11741         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11742         intel_ring_emit(ring, MI_NOOP);
11743
11744         return 0;
11745 }
11746
11747 static int intel_gen4_queue_flip(struct drm_device *dev,
11748                                  struct drm_crtc *crtc,
11749                                  struct drm_framebuffer *fb,
11750                                  struct drm_i915_gem_object *obj,
11751                                  struct drm_i915_gem_request *req,
11752                                  uint32_t flags)
11753 {
11754         struct intel_ring *ring = req->ring;
11755         struct drm_i915_private *dev_priv = to_i915(dev);
11756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11757         uint32_t pf, pipesrc;
11758         int ret;
11759
11760         ret = intel_ring_begin(req, 4);
11761         if (ret)
11762                 return ret;
11763
11764         /* i965+ uses the linear or tiled offsets from the
11765          * Display Registers (which do not change across a page-flip)
11766          * so we need only reprogram the base address.
11767          */
11768         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11769                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11770         intel_ring_emit(ring, fb->pitches[0]);
11771         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11772                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11773
11774         /* XXX Enabling the panel-fitter across page-flip is so far
11775          * untested on non-native modes, so ignore it for now.
11776          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11777          */
11778         pf = 0;
11779         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11780         intel_ring_emit(ring, pf | pipesrc);
11781
11782         return 0;
11783 }
11784
11785 static int intel_gen6_queue_flip(struct drm_device *dev,
11786                                  struct drm_crtc *crtc,
11787                                  struct drm_framebuffer *fb,
11788                                  struct drm_i915_gem_object *obj,
11789                                  struct drm_i915_gem_request *req,
11790                                  uint32_t flags)
11791 {
11792         struct intel_ring *ring = req->ring;
11793         struct drm_i915_private *dev_priv = to_i915(dev);
11794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11795         uint32_t pf, pipesrc;
11796         int ret;
11797
11798         ret = intel_ring_begin(req, 4);
11799         if (ret)
11800                 return ret;
11801
11802         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11803                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11804         intel_ring_emit(ring, fb->pitches[0] |
11805                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11806         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11807
11808         /* Contrary to the suggestions in the documentation,
11809          * "Enable Panel Fitter" does not seem to be required when page
11810          * flipping with a non-native mode, and worse causes a normal
11811          * modeset to fail.
11812          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11813          */
11814         pf = 0;
11815         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11816         intel_ring_emit(ring, pf | pipesrc);
11817
11818         return 0;
11819 }
11820
11821 static int intel_gen7_queue_flip(struct drm_device *dev,
11822                                  struct drm_crtc *crtc,
11823                                  struct drm_framebuffer *fb,
11824                                  struct drm_i915_gem_object *obj,
11825                                  struct drm_i915_gem_request *req,
11826                                  uint32_t flags)
11827 {
11828         struct intel_ring *ring = req->ring;
11829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11830         uint32_t plane_bit = 0;
11831         int len, ret;
11832
11833         switch (intel_crtc->plane) {
11834         case PLANE_A:
11835                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11836                 break;
11837         case PLANE_B:
11838                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11839                 break;
11840         case PLANE_C:
11841                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11842                 break;
11843         default:
11844                 WARN_ONCE(1, "unknown plane in flip command\n");
11845                 return -ENODEV;
11846         }
11847
11848         len = 4;
11849         if (req->engine->id == RCS) {
11850                 len += 6;
11851                 /*
11852                  * On Gen 8, SRM is now taking an extra dword to accommodate
11853                  * 48bits addresses, and we need a NOOP for the batch size to
11854                  * stay even.
11855                  */
11856                 if (IS_GEN8(dev))
11857                         len += 2;
11858         }
11859
11860         /*
11861          * BSpec MI_DISPLAY_FLIP for IVB:
11862          * "The full packet must be contained within the same cache line."
11863          *
11864          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11865          * cacheline, if we ever start emitting more commands before
11866          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11867          * then do the cacheline alignment, and finally emit the
11868          * MI_DISPLAY_FLIP.
11869          */
11870         ret = intel_ring_cacheline_align(req);
11871         if (ret)
11872                 return ret;
11873
11874         ret = intel_ring_begin(req, len);
11875         if (ret)
11876                 return ret;
11877
11878         /* Unmask the flip-done completion message. Note that the bspec says that
11879          * we should do this for both the BCS and RCS, and that we must not unmask
11880          * more than one flip event at any time (or ensure that one flip message
11881          * can be sent by waiting for flip-done prior to queueing new flips).
11882          * Experimentation says that BCS works despite DERRMR masking all
11883          * flip-done completion events and that unmasking all planes at once
11884          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11885          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11886          */
11887         if (req->engine->id == RCS) {
11888                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11889                 intel_ring_emit_reg(ring, DERRMR);
11890                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11891                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11892                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11893                 if (IS_GEN8(dev))
11894                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11895                                               MI_SRM_LRM_GLOBAL_GTT);
11896                 else
11897                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11898                                               MI_SRM_LRM_GLOBAL_GTT);
11899                 intel_ring_emit_reg(ring, DERRMR);
11900                 intel_ring_emit(ring,
11901                                 i915_ggtt_offset(req->engine->scratch) + 256);
11902                 if (IS_GEN8(dev)) {
11903                         intel_ring_emit(ring, 0);
11904                         intel_ring_emit(ring, MI_NOOP);
11905                 }
11906         }
11907
11908         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11909         intel_ring_emit(ring, fb->pitches[0] |
11910                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11911         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11912         intel_ring_emit(ring, (MI_NOOP));
11913
11914         return 0;
11915 }
11916
11917 static bool use_mmio_flip(struct intel_engine_cs *engine,
11918                           struct drm_i915_gem_object *obj)
11919 {
11920         struct reservation_object *resv;
11921
11922         /*
11923          * This is not being used for older platforms, because
11924          * non-availability of flip done interrupt forces us to use
11925          * CS flips. Older platforms derive flip done using some clever
11926          * tricks involving the flip_pending status bits and vblank irqs.
11927          * So using MMIO flips there would disrupt this mechanism.
11928          */
11929
11930         if (engine == NULL)
11931                 return true;
11932
11933         if (INTEL_GEN(engine->i915) < 5)
11934                 return false;
11935
11936         if (i915.use_mmio_flip < 0)
11937                 return false;
11938         else if (i915.use_mmio_flip > 0)
11939                 return true;
11940         else if (i915.enable_execlists)
11941                 return true;
11942
11943         resv = i915_gem_object_get_dmabuf_resv(obj);
11944         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11945                 return true;
11946
11947         return engine != i915_gem_active_get_engine(&obj->last_write,
11948                                                     &obj->base.dev->struct_mutex);
11949 }
11950
11951 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11952                              unsigned int rotation,
11953                              struct intel_flip_work *work)
11954 {
11955         struct drm_device *dev = intel_crtc->base.dev;
11956         struct drm_i915_private *dev_priv = to_i915(dev);
11957         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11958         const enum pipe pipe = intel_crtc->pipe;
11959         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11960
11961         ctl = I915_READ(PLANE_CTL(pipe, 0));
11962         ctl &= ~PLANE_CTL_TILED_MASK;
11963         switch (fb->modifier[0]) {
11964         case DRM_FORMAT_MOD_NONE:
11965                 break;
11966         case I915_FORMAT_MOD_X_TILED:
11967                 ctl |= PLANE_CTL_TILED_X;
11968                 break;
11969         case I915_FORMAT_MOD_Y_TILED:
11970                 ctl |= PLANE_CTL_TILED_Y;
11971                 break;
11972         case I915_FORMAT_MOD_Yf_TILED:
11973                 ctl |= PLANE_CTL_TILED_YF;
11974                 break;
11975         default:
11976                 MISSING_CASE(fb->modifier[0]);
11977         }
11978
11979         /*
11980          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11981          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11982          */
11983         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11984         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11985
11986         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11987         POSTING_READ(PLANE_SURF(pipe, 0));
11988 }
11989
11990 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11991                              struct intel_flip_work *work)
11992 {
11993         struct drm_device *dev = intel_crtc->base.dev;
11994         struct drm_i915_private *dev_priv = to_i915(dev);
11995         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11996         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11997         u32 dspcntr;
11998
11999         dspcntr = I915_READ(reg);
12000
12001         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12002                 dspcntr |= DISPPLANE_TILED;
12003         else
12004                 dspcntr &= ~DISPPLANE_TILED;
12005
12006         I915_WRITE(reg, dspcntr);
12007
12008         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12009         POSTING_READ(DSPSURF(intel_crtc->plane));
12010 }
12011
12012 static void intel_mmio_flip_work_func(struct work_struct *w)
12013 {
12014         struct intel_flip_work *work =
12015                 container_of(w, struct intel_flip_work, mmio_work);
12016         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12017         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12018         struct intel_framebuffer *intel_fb =
12019                 to_intel_framebuffer(crtc->base.primary->fb);
12020         struct drm_i915_gem_object *obj = intel_fb->obj;
12021         struct reservation_object *resv;
12022
12023         if (work->flip_queued_req)
12024                 WARN_ON(i915_wait_request(work->flip_queued_req,
12025                                           0, NULL, NO_WAITBOOST));
12026
12027         /* For framebuffer backed by dmabuf, wait for fence */
12028         resv = i915_gem_object_get_dmabuf_resv(obj);
12029         if (resv)
12030                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12031                                                             MAX_SCHEDULE_TIMEOUT) < 0);
12032
12033         intel_pipe_update_start(crtc);
12034
12035         if (INTEL_GEN(dev_priv) >= 9)
12036                 skl_do_mmio_flip(crtc, work->rotation, work);
12037         else
12038                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12039                 ilk_do_mmio_flip(crtc, work);
12040
12041         intel_pipe_update_end(crtc, work);
12042 }
12043
12044 static int intel_default_queue_flip(struct drm_device *dev,
12045                                     struct drm_crtc *crtc,
12046                                     struct drm_framebuffer *fb,
12047                                     struct drm_i915_gem_object *obj,
12048                                     struct drm_i915_gem_request *req,
12049                                     uint32_t flags)
12050 {
12051         return -ENODEV;
12052 }
12053
12054 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12055                                       struct intel_crtc *intel_crtc,
12056                                       struct intel_flip_work *work)
12057 {
12058         u32 addr, vblank;
12059
12060         if (!atomic_read(&work->pending))
12061                 return false;
12062
12063         smp_rmb();
12064
12065         vblank = intel_crtc_get_vblank_counter(intel_crtc);
12066         if (work->flip_ready_vblank == 0) {
12067                 if (work->flip_queued_req &&
12068                     !i915_gem_request_completed(work->flip_queued_req))
12069                         return false;
12070
12071                 work->flip_ready_vblank = vblank;
12072         }
12073
12074         if (vblank - work->flip_ready_vblank < 3)
12075                 return false;
12076
12077         /* Potential stall - if we see that the flip has happened,
12078          * assume a missed interrupt. */
12079         if (INTEL_GEN(dev_priv) >= 4)
12080                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12081         else
12082                 addr = I915_READ(DSPADDR(intel_crtc->plane));
12083
12084         /* There is a potential issue here with a false positive after a flip
12085          * to the same address. We could address this by checking for a
12086          * non-incrementing frame counter.
12087          */
12088         return addr == work->gtt_offset;
12089 }
12090
12091 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12092 {
12093         struct drm_device *dev = &dev_priv->drm;
12094         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12096         struct intel_flip_work *work;
12097
12098         WARN_ON(!in_interrupt());
12099
12100         if (crtc == NULL)
12101                 return;
12102
12103         spin_lock(&dev->event_lock);
12104         work = intel_crtc->flip_work;
12105
12106         if (work != NULL && !is_mmio_work(work) &&
12107             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12108                 WARN_ONCE(1,
12109                           "Kicking stuck page flip: queued at %d, now %d\n",
12110                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12111                 page_flip_completed(intel_crtc);
12112                 work = NULL;
12113         }
12114
12115         if (work != NULL && !is_mmio_work(work) &&
12116             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12117                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12118         spin_unlock(&dev->event_lock);
12119 }
12120
12121 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12122                                 struct drm_framebuffer *fb,
12123                                 struct drm_pending_vblank_event *event,
12124                                 uint32_t page_flip_flags)
12125 {
12126         struct drm_device *dev = crtc->dev;
12127         struct drm_i915_private *dev_priv = to_i915(dev);
12128         struct drm_framebuffer *old_fb = crtc->primary->fb;
12129         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12131         struct drm_plane *primary = crtc->primary;
12132         enum pipe pipe = intel_crtc->pipe;
12133         struct intel_flip_work *work;
12134         struct intel_engine_cs *engine;
12135         bool mmio_flip;
12136         struct drm_i915_gem_request *request;
12137         struct i915_vma *vma;
12138         int ret;
12139
12140         /*
12141          * drm_mode_page_flip_ioctl() should already catch this, but double
12142          * check to be safe.  In the future we may enable pageflipping from
12143          * a disabled primary plane.
12144          */
12145         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12146                 return -EBUSY;
12147
12148         /* Can't change pixel format via MI display flips. */
12149         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12150                 return -EINVAL;
12151
12152         /*
12153          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12154          * Note that pitch changes could also affect these register.
12155          */
12156         if (INTEL_INFO(dev)->gen > 3 &&
12157             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12158              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12159                 return -EINVAL;
12160
12161         if (i915_terminally_wedged(&dev_priv->gpu_error))
12162                 goto out_hang;
12163
12164         work = kzalloc(sizeof(*work), GFP_KERNEL);
12165         if (work == NULL)
12166                 return -ENOMEM;
12167
12168         work->event = event;
12169         work->crtc = crtc;
12170         work->old_fb = old_fb;
12171         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12172
12173         ret = drm_crtc_vblank_get(crtc);
12174         if (ret)
12175                 goto free_work;
12176
12177         /* We borrow the event spin lock for protecting flip_work */
12178         spin_lock_irq(&dev->event_lock);
12179         if (intel_crtc->flip_work) {
12180                 /* Before declaring the flip queue wedged, check if
12181                  * the hardware completed the operation behind our backs.
12182                  */
12183                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12184                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12185                         page_flip_completed(intel_crtc);
12186                 } else {
12187                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12188                         spin_unlock_irq(&dev->event_lock);
12189
12190                         drm_crtc_vblank_put(crtc);
12191                         kfree(work);
12192                         return -EBUSY;
12193                 }
12194         }
12195         intel_crtc->flip_work = work;
12196         spin_unlock_irq(&dev->event_lock);
12197
12198         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12199                 flush_workqueue(dev_priv->wq);
12200
12201         /* Reference the objects for the scheduled work. */
12202         drm_framebuffer_reference(work->old_fb);
12203
12204         crtc->primary->fb = fb;
12205         update_state_fb(crtc->primary);
12206
12207         work->pending_flip_obj = i915_gem_object_get(obj);
12208
12209         ret = i915_mutex_lock_interruptible(dev);
12210         if (ret)
12211                 goto cleanup;
12212
12213         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12214         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12215                 ret = -EIO;
12216                 goto cleanup;
12217         }
12218
12219         atomic_inc(&intel_crtc->unpin_work_count);
12220
12221         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12222                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12223
12224         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12225                 engine = &dev_priv->engine[BCS];
12226                 if (fb->modifier[0] != old_fb->modifier[0])
12227                         /* vlv: DISPLAY_FLIP fails to change tiling */
12228                         engine = NULL;
12229         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12230                 engine = &dev_priv->engine[BCS];
12231         } else if (INTEL_INFO(dev)->gen >= 7) {
12232                 engine = i915_gem_active_get_engine(&obj->last_write,
12233                                                     &obj->base.dev->struct_mutex);
12234                 if (engine == NULL || engine->id != RCS)
12235                         engine = &dev_priv->engine[BCS];
12236         } else {
12237                 engine = &dev_priv->engine[RCS];
12238         }
12239
12240         mmio_flip = use_mmio_flip(engine, obj);
12241
12242         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12243         if (IS_ERR(vma)) {
12244                 ret = PTR_ERR(vma);
12245                 goto cleanup_pending;
12246         }
12247
12248         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12249         work->gtt_offset += intel_crtc->dspaddr_offset;
12250         work->rotation = crtc->primary->state->rotation;
12251
12252         /*
12253          * There's the potential that the next frame will not be compatible with
12254          * FBC, so we want to call pre_update() before the actual page flip.
12255          * The problem is that pre_update() caches some information about the fb
12256          * object, so we want to do this only after the object is pinned. Let's
12257          * be on the safe side and do this immediately before scheduling the
12258          * flip.
12259          */
12260         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12261                              to_intel_plane_state(primary->state));
12262
12263         if (mmio_flip) {
12264                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12265
12266                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12267                                                             &obj->base.dev->struct_mutex);
12268                 schedule_work(&work->mmio_work);
12269         } else {
12270                 request = i915_gem_request_alloc(engine, engine->last_context);
12271                 if (IS_ERR(request)) {
12272                         ret = PTR_ERR(request);
12273                         goto cleanup_unpin;
12274                 }
12275
12276                 ret = i915_gem_request_await_object(request, obj, false);
12277                 if (ret)
12278                         goto cleanup_request;
12279
12280                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12281                                                    page_flip_flags);
12282                 if (ret)
12283                         goto cleanup_request;
12284
12285                 intel_mark_page_flip_active(intel_crtc, work);
12286
12287                 work->flip_queued_req = i915_gem_request_get(request);
12288                 i915_add_request_no_flush(request);
12289         }
12290
12291         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12292                           to_intel_plane(primary)->frontbuffer_bit);
12293         mutex_unlock(&dev->struct_mutex);
12294
12295         intel_frontbuffer_flip_prepare(to_i915(dev),
12296                                        to_intel_plane(primary)->frontbuffer_bit);
12297
12298         trace_i915_flip_request(intel_crtc->plane, obj);
12299
12300         return 0;
12301
12302 cleanup_request:
12303         i915_add_request_no_flush(request);
12304 cleanup_unpin:
12305         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12306 cleanup_pending:
12307         atomic_dec(&intel_crtc->unpin_work_count);
12308         mutex_unlock(&dev->struct_mutex);
12309 cleanup:
12310         crtc->primary->fb = old_fb;
12311         update_state_fb(crtc->primary);
12312
12313         i915_gem_object_put_unlocked(obj);
12314         drm_framebuffer_unreference(work->old_fb);
12315
12316         spin_lock_irq(&dev->event_lock);
12317         intel_crtc->flip_work = NULL;
12318         spin_unlock_irq(&dev->event_lock);
12319
12320         drm_crtc_vblank_put(crtc);
12321 free_work:
12322         kfree(work);
12323
12324         if (ret == -EIO) {
12325                 struct drm_atomic_state *state;
12326                 struct drm_plane_state *plane_state;
12327
12328 out_hang:
12329                 state = drm_atomic_state_alloc(dev);
12330                 if (!state)
12331                         return -ENOMEM;
12332                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12333
12334 retry:
12335                 plane_state = drm_atomic_get_plane_state(state, primary);
12336                 ret = PTR_ERR_OR_ZERO(plane_state);
12337                 if (!ret) {
12338                         drm_atomic_set_fb_for_plane(plane_state, fb);
12339
12340                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12341                         if (!ret)
12342                                 ret = drm_atomic_commit(state);
12343                 }
12344
12345                 if (ret == -EDEADLK) {
12346                         drm_modeset_backoff(state->acquire_ctx);
12347                         drm_atomic_state_clear(state);
12348                         goto retry;
12349                 }
12350
12351                 if (ret)
12352                         drm_atomic_state_free(state);
12353
12354                 if (ret == 0 && event) {
12355                         spin_lock_irq(&dev->event_lock);
12356                         drm_crtc_send_vblank_event(crtc, event);
12357                         spin_unlock_irq(&dev->event_lock);
12358                 }
12359         }
12360         return ret;
12361 }
12362
12363
12364 /**
12365  * intel_wm_need_update - Check whether watermarks need updating
12366  * @plane: drm plane
12367  * @state: new plane state
12368  *
12369  * Check current plane state versus the new one to determine whether
12370  * watermarks need to be recalculated.
12371  *
12372  * Returns true or false.
12373  */
12374 static bool intel_wm_need_update(struct drm_plane *plane,
12375                                  struct drm_plane_state *state)
12376 {
12377         struct intel_plane_state *new = to_intel_plane_state(state);
12378         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12379
12380         /* Update watermarks on tiling or size changes. */
12381         if (new->base.visible != cur->base.visible)
12382                 return true;
12383
12384         if (!cur->base.fb || !new->base.fb)
12385                 return false;
12386
12387         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12388             cur->base.rotation != new->base.rotation ||
12389             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12390             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12391             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12392             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12393                 return true;
12394
12395         return false;
12396 }
12397
12398 static bool needs_scaling(struct intel_plane_state *state)
12399 {
12400         int src_w = drm_rect_width(&state->base.src) >> 16;
12401         int src_h = drm_rect_height(&state->base.src) >> 16;
12402         int dst_w = drm_rect_width(&state->base.dst);
12403         int dst_h = drm_rect_height(&state->base.dst);
12404
12405         return (src_w != dst_w || src_h != dst_h);
12406 }
12407
12408 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12409                                     struct drm_plane_state *plane_state)
12410 {
12411         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12412         struct drm_crtc *crtc = crtc_state->crtc;
12413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12414         struct drm_plane *plane = plane_state->plane;
12415         struct drm_device *dev = crtc->dev;
12416         struct drm_i915_private *dev_priv = to_i915(dev);
12417         struct intel_plane_state *old_plane_state =
12418                 to_intel_plane_state(plane->state);
12419         bool mode_changed = needs_modeset(crtc_state);
12420         bool was_crtc_enabled = crtc->state->active;
12421         bool is_crtc_enabled = crtc_state->active;
12422         bool turn_off, turn_on, visible, was_visible;
12423         struct drm_framebuffer *fb = plane_state->fb;
12424         int ret;
12425
12426         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12427                 ret = skl_update_scaler_plane(
12428                         to_intel_crtc_state(crtc_state),
12429                         to_intel_plane_state(plane_state));
12430                 if (ret)
12431                         return ret;
12432         }
12433
12434         was_visible = old_plane_state->base.visible;
12435         visible = to_intel_plane_state(plane_state)->base.visible;
12436
12437         if (!was_crtc_enabled && WARN_ON(was_visible))
12438                 was_visible = false;
12439
12440         /*
12441          * Visibility is calculated as if the crtc was on, but
12442          * after scaler setup everything depends on it being off
12443          * when the crtc isn't active.
12444          *
12445          * FIXME this is wrong for watermarks. Watermarks should also
12446          * be computed as if the pipe would be active. Perhaps move
12447          * per-plane wm computation to the .check_plane() hook, and
12448          * only combine the results from all planes in the current place?
12449          */
12450         if (!is_crtc_enabled)
12451                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12452
12453         if (!was_visible && !visible)
12454                 return 0;
12455
12456         if (fb != old_plane_state->base.fb)
12457                 pipe_config->fb_changed = true;
12458
12459         turn_off = was_visible && (!visible || mode_changed);
12460         turn_on = visible && (!was_visible || mode_changed);
12461
12462         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12463                          intel_crtc->base.base.id,
12464                          intel_crtc->base.name,
12465                          plane->base.id, plane->name,
12466                          fb ? fb->base.id : -1);
12467
12468         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12469                          plane->base.id, plane->name,
12470                          was_visible, visible,
12471                          turn_off, turn_on, mode_changed);
12472
12473         if (turn_on) {
12474                 pipe_config->update_wm_pre = true;
12475
12476                 /* must disable cxsr around plane enable/disable */
12477                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12478                         pipe_config->disable_cxsr = true;
12479         } else if (turn_off) {
12480                 pipe_config->update_wm_post = true;
12481
12482                 /* must disable cxsr around plane enable/disable */
12483                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12484                         pipe_config->disable_cxsr = true;
12485         } else if (intel_wm_need_update(plane, plane_state)) {
12486                 /* FIXME bollocks */
12487                 pipe_config->update_wm_pre = true;
12488                 pipe_config->update_wm_post = true;
12489         }
12490
12491         /* Pre-gen9 platforms need two-step watermark updates */
12492         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12493             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12494                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12495
12496         if (visible || was_visible)
12497                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12498
12499         /*
12500          * WaCxSRDisabledForSpriteScaling:ivb
12501          *
12502          * cstate->update_wm was already set above, so this flag will
12503          * take effect when we commit and program watermarks.
12504          */
12505         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12506             needs_scaling(to_intel_plane_state(plane_state)) &&
12507             !needs_scaling(old_plane_state))
12508                 pipe_config->disable_lp_wm = true;
12509
12510         return 0;
12511 }
12512
12513 static bool encoders_cloneable(const struct intel_encoder *a,
12514                                const struct intel_encoder *b)
12515 {
12516         /* masks could be asymmetric, so check both ways */
12517         return a == b || (a->cloneable & (1 << b->type) &&
12518                           b->cloneable & (1 << a->type));
12519 }
12520
12521 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12522                                          struct intel_crtc *crtc,
12523                                          struct intel_encoder *encoder)
12524 {
12525         struct intel_encoder *source_encoder;
12526         struct drm_connector *connector;
12527         struct drm_connector_state *connector_state;
12528         int i;
12529
12530         for_each_connector_in_state(state, connector, connector_state, i) {
12531                 if (connector_state->crtc != &crtc->base)
12532                         continue;
12533
12534                 source_encoder =
12535                         to_intel_encoder(connector_state->best_encoder);
12536                 if (!encoders_cloneable(encoder, source_encoder))
12537                         return false;
12538         }
12539
12540         return true;
12541 }
12542
12543 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12544                                    struct drm_crtc_state *crtc_state)
12545 {
12546         struct drm_device *dev = crtc->dev;
12547         struct drm_i915_private *dev_priv = to_i915(dev);
12548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12549         struct intel_crtc_state *pipe_config =
12550                 to_intel_crtc_state(crtc_state);
12551         struct drm_atomic_state *state = crtc_state->state;
12552         int ret;
12553         bool mode_changed = needs_modeset(crtc_state);
12554
12555         if (mode_changed && !crtc_state->active)
12556                 pipe_config->update_wm_post = true;
12557
12558         if (mode_changed && crtc_state->enable &&
12559             dev_priv->display.crtc_compute_clock &&
12560             !WARN_ON(pipe_config->shared_dpll)) {
12561                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12562                                                            pipe_config);
12563                 if (ret)
12564                         return ret;
12565         }
12566
12567         if (crtc_state->color_mgmt_changed) {
12568                 ret = intel_color_check(crtc, crtc_state);
12569                 if (ret)
12570                         return ret;
12571
12572                 /*
12573                  * Changing color management on Intel hardware is
12574                  * handled as part of planes update.
12575                  */
12576                 crtc_state->planes_changed = true;
12577         }
12578
12579         ret = 0;
12580         if (dev_priv->display.compute_pipe_wm) {
12581                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12582                 if (ret) {
12583                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12584                         return ret;
12585                 }
12586         }
12587
12588         if (dev_priv->display.compute_intermediate_wm &&
12589             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12590                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12591                         return 0;
12592
12593                 /*
12594                  * Calculate 'intermediate' watermarks that satisfy both the
12595                  * old state and the new state.  We can program these
12596                  * immediately.
12597                  */
12598                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12599                                                                 intel_crtc,
12600                                                                 pipe_config);
12601                 if (ret) {
12602                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12603                         return ret;
12604                 }
12605         } else if (dev_priv->display.compute_intermediate_wm) {
12606                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12607                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12608         }
12609
12610         if (INTEL_INFO(dev)->gen >= 9) {
12611                 if (mode_changed)
12612                         ret = skl_update_scaler_crtc(pipe_config);
12613
12614                 if (!ret)
12615                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12616                                                          pipe_config);
12617         }
12618
12619         return ret;
12620 }
12621
12622 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12623         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12624         .atomic_begin = intel_begin_crtc_commit,
12625         .atomic_flush = intel_finish_crtc_commit,
12626         .atomic_check = intel_crtc_atomic_check,
12627 };
12628
12629 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12630 {
12631         struct intel_connector *connector;
12632
12633         for_each_intel_connector(dev, connector) {
12634                 if (connector->base.state->crtc)
12635                         drm_connector_unreference(&connector->base);
12636
12637                 if (connector->base.encoder) {
12638                         connector->base.state->best_encoder =
12639                                 connector->base.encoder;
12640                         connector->base.state->crtc =
12641                                 connector->base.encoder->crtc;
12642
12643                         drm_connector_reference(&connector->base);
12644                 } else {
12645                         connector->base.state->best_encoder = NULL;
12646                         connector->base.state->crtc = NULL;
12647                 }
12648         }
12649 }
12650
12651 static void
12652 connected_sink_compute_bpp(struct intel_connector *connector,
12653                            struct intel_crtc_state *pipe_config)
12654 {
12655         int bpp = pipe_config->pipe_bpp;
12656
12657         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12658                 connector->base.base.id,
12659                 connector->base.name);
12660
12661         /* Don't use an invalid EDID bpc value */
12662         if (connector->base.display_info.bpc &&
12663             connector->base.display_info.bpc * 3 < bpp) {
12664                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12665                               bpp, connector->base.display_info.bpc*3);
12666                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12667         }
12668
12669         /* Clamp bpp to 8 on screens without EDID 1.4 */
12670         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12671                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12672                               bpp);
12673                 pipe_config->pipe_bpp = 24;
12674         }
12675 }
12676
12677 static int
12678 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12679                           struct intel_crtc_state *pipe_config)
12680 {
12681         struct drm_device *dev = crtc->base.dev;
12682         struct drm_atomic_state *state;
12683         struct drm_connector *connector;
12684         struct drm_connector_state *connector_state;
12685         int bpp, i;
12686
12687         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12688                 bpp = 10*3;
12689         else if (INTEL_INFO(dev)->gen >= 5)
12690                 bpp = 12*3;
12691         else
12692                 bpp = 8*3;
12693
12694
12695         pipe_config->pipe_bpp = bpp;
12696
12697         state = pipe_config->base.state;
12698
12699         /* Clamp display bpp to EDID value */
12700         for_each_connector_in_state(state, connector, connector_state, i) {
12701                 if (connector_state->crtc != &crtc->base)
12702                         continue;
12703
12704                 connected_sink_compute_bpp(to_intel_connector(connector),
12705                                            pipe_config);
12706         }
12707
12708         return bpp;
12709 }
12710
12711 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12712 {
12713         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12714                         "type: 0x%x flags: 0x%x\n",
12715                 mode->crtc_clock,
12716                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12717                 mode->crtc_hsync_end, mode->crtc_htotal,
12718                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12719                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12720 }
12721
12722 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12723                                    struct intel_crtc_state *pipe_config,
12724                                    const char *context)
12725 {
12726         struct drm_device *dev = crtc->base.dev;
12727         struct drm_plane *plane;
12728         struct intel_plane *intel_plane;
12729         struct intel_plane_state *state;
12730         struct drm_framebuffer *fb;
12731
12732         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12733                       crtc->base.base.id, crtc->base.name,
12734                       context, pipe_config, pipe_name(crtc->pipe));
12735
12736         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12737         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12738                       pipe_config->pipe_bpp, pipe_config->dither);
12739         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12740                       pipe_config->has_pch_encoder,
12741                       pipe_config->fdi_lanes,
12742                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12743                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12744                       pipe_config->fdi_m_n.tu);
12745         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12746                       intel_crtc_has_dp_encoder(pipe_config),
12747                       pipe_config->lane_count,
12748                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12749                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12750                       pipe_config->dp_m_n.tu);
12751
12752         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12753                       intel_crtc_has_dp_encoder(pipe_config),
12754                       pipe_config->lane_count,
12755                       pipe_config->dp_m2_n2.gmch_m,
12756                       pipe_config->dp_m2_n2.gmch_n,
12757                       pipe_config->dp_m2_n2.link_m,
12758                       pipe_config->dp_m2_n2.link_n,
12759                       pipe_config->dp_m2_n2.tu);
12760
12761         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12762                       pipe_config->has_audio,
12763                       pipe_config->has_infoframe);
12764
12765         DRM_DEBUG_KMS("requested mode:\n");
12766         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12767         DRM_DEBUG_KMS("adjusted mode:\n");
12768         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12769         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12770         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12771         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12772                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12773         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12774                       crtc->num_scalers,
12775                       pipe_config->scaler_state.scaler_users,
12776                       pipe_config->scaler_state.scaler_id);
12777         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12778                       pipe_config->gmch_pfit.control,
12779                       pipe_config->gmch_pfit.pgm_ratios,
12780                       pipe_config->gmch_pfit.lvds_border_bits);
12781         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12782                       pipe_config->pch_pfit.pos,
12783                       pipe_config->pch_pfit.size,
12784                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12785         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12786         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12787
12788         if (IS_BROXTON(dev)) {
12789                 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12790                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12791                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12792                               pipe_config->dpll_hw_state.ebb0,
12793                               pipe_config->dpll_hw_state.ebb4,
12794                               pipe_config->dpll_hw_state.pll0,
12795                               pipe_config->dpll_hw_state.pll1,
12796                               pipe_config->dpll_hw_state.pll2,
12797                               pipe_config->dpll_hw_state.pll3,
12798                               pipe_config->dpll_hw_state.pll6,
12799                               pipe_config->dpll_hw_state.pll8,
12800                               pipe_config->dpll_hw_state.pll9,
12801                               pipe_config->dpll_hw_state.pll10,
12802                               pipe_config->dpll_hw_state.pcsdw12);
12803         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12804                 DRM_DEBUG_KMS("dpll_hw_state: "
12805                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12806                               pipe_config->dpll_hw_state.ctrl1,
12807                               pipe_config->dpll_hw_state.cfgcr1,
12808                               pipe_config->dpll_hw_state.cfgcr2);
12809         } else if (HAS_DDI(dev)) {
12810                 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12811                               pipe_config->dpll_hw_state.wrpll,
12812                               pipe_config->dpll_hw_state.spll);
12813         } else {
12814                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12815                               "fp0: 0x%x, fp1: 0x%x\n",
12816                               pipe_config->dpll_hw_state.dpll,
12817                               pipe_config->dpll_hw_state.dpll_md,
12818                               pipe_config->dpll_hw_state.fp0,
12819                               pipe_config->dpll_hw_state.fp1);
12820         }
12821
12822         DRM_DEBUG_KMS("planes on this crtc\n");
12823         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12824                 intel_plane = to_intel_plane(plane);
12825                 if (intel_plane->pipe != crtc->pipe)
12826                         continue;
12827
12828                 state = to_intel_plane_state(plane->state);
12829                 fb = state->base.fb;
12830                 if (!fb) {
12831                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12832                                       plane->base.id, plane->name, state->scaler_id);
12833                         continue;
12834                 }
12835
12836                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12837                               plane->base.id, plane->name);
12838                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12839                               fb->base.id, fb->width, fb->height,
12840                               drm_get_format_name(fb->pixel_format));
12841                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12842                               state->scaler_id,
12843                               state->base.src.x1 >> 16,
12844                               state->base.src.y1 >> 16,
12845                               drm_rect_width(&state->base.src) >> 16,
12846                               drm_rect_height(&state->base.src) >> 16,
12847                               state->base.dst.x1, state->base.dst.y1,
12848                               drm_rect_width(&state->base.dst),
12849                               drm_rect_height(&state->base.dst));
12850         }
12851 }
12852
12853 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12854 {
12855         struct drm_device *dev = state->dev;
12856         struct drm_connector *connector;
12857         unsigned int used_ports = 0;
12858         unsigned int used_mst_ports = 0;
12859
12860         /*
12861          * Walk the connector list instead of the encoder
12862          * list to detect the problem on ddi platforms
12863          * where there's just one encoder per digital port.
12864          */
12865         drm_for_each_connector(connector, dev) {
12866                 struct drm_connector_state *connector_state;
12867                 struct intel_encoder *encoder;
12868
12869                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12870                 if (!connector_state)
12871                         connector_state = connector->state;
12872
12873                 if (!connector_state->best_encoder)
12874                         continue;
12875
12876                 encoder = to_intel_encoder(connector_state->best_encoder);
12877
12878                 WARN_ON(!connector_state->crtc);
12879
12880                 switch (encoder->type) {
12881                         unsigned int port_mask;
12882                 case INTEL_OUTPUT_UNKNOWN:
12883                         if (WARN_ON(!HAS_DDI(dev)))
12884                                 break;
12885                 case INTEL_OUTPUT_DP:
12886                 case INTEL_OUTPUT_HDMI:
12887                 case INTEL_OUTPUT_EDP:
12888                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12889
12890                         /* the same port mustn't appear more than once */
12891                         if (used_ports & port_mask)
12892                                 return false;
12893
12894                         used_ports |= port_mask;
12895                         break;
12896                 case INTEL_OUTPUT_DP_MST:
12897                         used_mst_ports |=
12898                                 1 << enc_to_mst(&encoder->base)->primary->port;
12899                         break;
12900                 default:
12901                         break;
12902                 }
12903         }
12904
12905         /* can't mix MST and SST/HDMI on the same port */
12906         if (used_ports & used_mst_ports)
12907                 return false;
12908
12909         return true;
12910 }
12911
12912 static void
12913 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12914 {
12915         struct drm_crtc_state tmp_state;
12916         struct intel_crtc_scaler_state scaler_state;
12917         struct intel_dpll_hw_state dpll_hw_state;
12918         struct intel_shared_dpll *shared_dpll;
12919         bool force_thru;
12920
12921         /* FIXME: before the switch to atomic started, a new pipe_config was
12922          * kzalloc'd. Code that depends on any field being zero should be
12923          * fixed, so that the crtc_state can be safely duplicated. For now,
12924          * only fields that are know to not cause problems are preserved. */
12925
12926         tmp_state = crtc_state->base;
12927         scaler_state = crtc_state->scaler_state;
12928         shared_dpll = crtc_state->shared_dpll;
12929         dpll_hw_state = crtc_state->dpll_hw_state;
12930         force_thru = crtc_state->pch_pfit.force_thru;
12931
12932         memset(crtc_state, 0, sizeof *crtc_state);
12933
12934         crtc_state->base = tmp_state;
12935         crtc_state->scaler_state = scaler_state;
12936         crtc_state->shared_dpll = shared_dpll;
12937         crtc_state->dpll_hw_state = dpll_hw_state;
12938         crtc_state->pch_pfit.force_thru = force_thru;
12939 }
12940
12941 static int
12942 intel_modeset_pipe_config(struct drm_crtc *crtc,
12943                           struct intel_crtc_state *pipe_config)
12944 {
12945         struct drm_atomic_state *state = pipe_config->base.state;
12946         struct intel_encoder *encoder;
12947         struct drm_connector *connector;
12948         struct drm_connector_state *connector_state;
12949         int base_bpp, ret = -EINVAL;
12950         int i;
12951         bool retry = true;
12952
12953         clear_intel_crtc_state(pipe_config);
12954
12955         pipe_config->cpu_transcoder =
12956                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12957
12958         /*
12959          * Sanitize sync polarity flags based on requested ones. If neither
12960          * positive or negative polarity is requested, treat this as meaning
12961          * negative polarity.
12962          */
12963         if (!(pipe_config->base.adjusted_mode.flags &
12964               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12965                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12966
12967         if (!(pipe_config->base.adjusted_mode.flags &
12968               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12969                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12970
12971         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12972                                              pipe_config);
12973         if (base_bpp < 0)
12974                 goto fail;
12975
12976         /*
12977          * Determine the real pipe dimensions. Note that stereo modes can
12978          * increase the actual pipe size due to the frame doubling and
12979          * insertion of additional space for blanks between the frame. This
12980          * is stored in the crtc timings. We use the requested mode to do this
12981          * computation to clearly distinguish it from the adjusted mode, which
12982          * can be changed by the connectors in the below retry loop.
12983          */
12984         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12985                                &pipe_config->pipe_src_w,
12986                                &pipe_config->pipe_src_h);
12987
12988         for_each_connector_in_state(state, connector, connector_state, i) {
12989                 if (connector_state->crtc != crtc)
12990                         continue;
12991
12992                 encoder = to_intel_encoder(connector_state->best_encoder);
12993
12994                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12995                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12996                         goto fail;
12997                 }
12998
12999                 /*
13000                  * Determine output_types before calling the .compute_config()
13001                  * hooks so that the hooks can use this information safely.
13002                  */
13003                 pipe_config->output_types |= 1 << encoder->type;
13004         }
13005
13006 encoder_retry:
13007         /* Ensure the port clock defaults are reset when retrying. */
13008         pipe_config->port_clock = 0;
13009         pipe_config->pixel_multiplier = 1;
13010
13011         /* Fill in default crtc timings, allow encoders to overwrite them. */
13012         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13013                               CRTC_STEREO_DOUBLE);
13014
13015         /* Pass our mode to the connectors and the CRTC to give them a chance to
13016          * adjust it according to limitations or connector properties, and also
13017          * a chance to reject the mode entirely.
13018          */
13019         for_each_connector_in_state(state, connector, connector_state, i) {
13020                 if (connector_state->crtc != crtc)
13021                         continue;
13022
13023                 encoder = to_intel_encoder(connector_state->best_encoder);
13024
13025                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13026                         DRM_DEBUG_KMS("Encoder config failure\n");
13027                         goto fail;
13028                 }
13029         }
13030
13031         /* Set default port clock if not overwritten by the encoder. Needs to be
13032          * done afterwards in case the encoder adjusts the mode. */
13033         if (!pipe_config->port_clock)
13034                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13035                         * pipe_config->pixel_multiplier;
13036
13037         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13038         if (ret < 0) {
13039                 DRM_DEBUG_KMS("CRTC fixup failed\n");
13040                 goto fail;
13041         }
13042
13043         if (ret == RETRY) {
13044                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13045                         ret = -EINVAL;
13046                         goto fail;
13047                 }
13048
13049                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13050                 retry = false;
13051                 goto encoder_retry;
13052         }
13053
13054         /* Dithering seems to not pass-through bits correctly when it should, so
13055          * only enable it on 6bpc panels. */
13056         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13057         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13058                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13059
13060 fail:
13061         return ret;
13062 }
13063
13064 static void
13065 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13066 {
13067         struct drm_crtc *crtc;
13068         struct drm_crtc_state *crtc_state;
13069         int i;
13070
13071         /* Double check state. */
13072         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13073                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13074
13075                 /* Update hwmode for vblank functions */
13076                 if (crtc->state->active)
13077                         crtc->hwmode = crtc->state->adjusted_mode;
13078                 else
13079                         crtc->hwmode.crtc_clock = 0;
13080
13081                 /*
13082                  * Update legacy state to satisfy fbc code. This can
13083                  * be removed when fbc uses the atomic state.
13084                  */
13085                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13086                         struct drm_plane_state *plane_state = crtc->primary->state;
13087
13088                         crtc->primary->fb = plane_state->fb;
13089                         crtc->x = plane_state->src_x >> 16;
13090                         crtc->y = plane_state->src_y >> 16;
13091                 }
13092         }
13093 }
13094
13095 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13096 {
13097         int diff;
13098
13099         if (clock1 == clock2)
13100                 return true;
13101
13102         if (!clock1 || !clock2)
13103                 return false;
13104
13105         diff = abs(clock1 - clock2);
13106
13107         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13108                 return true;
13109
13110         return false;
13111 }
13112
13113 static bool
13114 intel_compare_m_n(unsigned int m, unsigned int n,
13115                   unsigned int m2, unsigned int n2,
13116                   bool exact)
13117 {
13118         if (m == m2 && n == n2)
13119                 return true;
13120
13121         if (exact || !m || !n || !m2 || !n2)
13122                 return false;
13123
13124         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13125
13126         if (n > n2) {
13127                 while (n > n2) {
13128                         m2 <<= 1;
13129                         n2 <<= 1;
13130                 }
13131         } else if (n < n2) {
13132                 while (n < n2) {
13133                         m <<= 1;
13134                         n <<= 1;
13135                 }
13136         }
13137
13138         if (n != n2)
13139                 return false;
13140
13141         return intel_fuzzy_clock_check(m, m2);
13142 }
13143
13144 static bool
13145 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13146                        struct intel_link_m_n *m2_n2,
13147                        bool adjust)
13148 {
13149         if (m_n->tu == m2_n2->tu &&
13150             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13151                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13152             intel_compare_m_n(m_n->link_m, m_n->link_n,
13153                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13154                 if (adjust)
13155                         *m2_n2 = *m_n;
13156
13157                 return true;
13158         }
13159
13160         return false;
13161 }
13162
13163 static bool
13164 intel_pipe_config_compare(struct drm_device *dev,
13165                           struct intel_crtc_state *current_config,
13166                           struct intel_crtc_state *pipe_config,
13167                           bool adjust)
13168 {
13169         bool ret = true;
13170
13171 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13172         do { \
13173                 if (!adjust) \
13174                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13175                 else \
13176                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13177         } while (0)
13178
13179 #define PIPE_CONF_CHECK_X(name) \
13180         if (current_config->name != pipe_config->name) { \
13181                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13182                           "(expected 0x%08x, found 0x%08x)\n", \
13183                           current_config->name, \
13184                           pipe_config->name); \
13185                 ret = false; \
13186         }
13187
13188 #define PIPE_CONF_CHECK_I(name) \
13189         if (current_config->name != pipe_config->name) { \
13190                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13191                           "(expected %i, found %i)\n", \
13192                           current_config->name, \
13193                           pipe_config->name); \
13194                 ret = false; \
13195         }
13196
13197 #define PIPE_CONF_CHECK_P(name) \
13198         if (current_config->name != pipe_config->name) { \
13199                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13200                           "(expected %p, found %p)\n", \
13201                           current_config->name, \
13202                           pipe_config->name); \
13203                 ret = false; \
13204         }
13205
13206 #define PIPE_CONF_CHECK_M_N(name) \
13207         if (!intel_compare_link_m_n(&current_config->name, \
13208                                     &pipe_config->name,\
13209                                     adjust)) { \
13210                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13211                           "(expected tu %i gmch %i/%i link %i/%i, " \
13212                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13213                           current_config->name.tu, \
13214                           current_config->name.gmch_m, \
13215                           current_config->name.gmch_n, \
13216                           current_config->name.link_m, \
13217                           current_config->name.link_n, \
13218                           pipe_config->name.tu, \
13219                           pipe_config->name.gmch_m, \
13220                           pipe_config->name.gmch_n, \
13221                           pipe_config->name.link_m, \
13222                           pipe_config->name.link_n); \
13223                 ret = false; \
13224         }
13225
13226 /* This is required for BDW+ where there is only one set of registers for
13227  * switching between high and low RR.
13228  * This macro can be used whenever a comparison has to be made between one
13229  * hw state and multiple sw state variables.
13230  */
13231 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13232         if (!intel_compare_link_m_n(&current_config->name, \
13233                                     &pipe_config->name, adjust) && \
13234             !intel_compare_link_m_n(&current_config->alt_name, \
13235                                     &pipe_config->name, adjust)) { \
13236                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13237                           "(expected tu %i gmch %i/%i link %i/%i, " \
13238                           "or tu %i gmch %i/%i link %i/%i, " \
13239                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13240                           current_config->name.tu, \
13241                           current_config->name.gmch_m, \
13242                           current_config->name.gmch_n, \
13243                           current_config->name.link_m, \
13244                           current_config->name.link_n, \
13245                           current_config->alt_name.tu, \
13246                           current_config->alt_name.gmch_m, \
13247                           current_config->alt_name.gmch_n, \
13248                           current_config->alt_name.link_m, \
13249                           current_config->alt_name.link_n, \
13250                           pipe_config->name.tu, \
13251                           pipe_config->name.gmch_m, \
13252                           pipe_config->name.gmch_n, \
13253                           pipe_config->name.link_m, \
13254                           pipe_config->name.link_n); \
13255                 ret = false; \
13256         }
13257
13258 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13259         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13260                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13261                           "(expected %i, found %i)\n", \
13262                           current_config->name & (mask), \
13263                           pipe_config->name & (mask)); \
13264                 ret = false; \
13265         }
13266
13267 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13268         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13269                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13270                           "(expected %i, found %i)\n", \
13271                           current_config->name, \
13272                           pipe_config->name); \
13273                 ret = false; \
13274         }
13275
13276 #define PIPE_CONF_QUIRK(quirk)  \
13277         ((current_config->quirks | pipe_config->quirks) & (quirk))
13278
13279         PIPE_CONF_CHECK_I(cpu_transcoder);
13280
13281         PIPE_CONF_CHECK_I(has_pch_encoder);
13282         PIPE_CONF_CHECK_I(fdi_lanes);
13283         PIPE_CONF_CHECK_M_N(fdi_m_n);
13284
13285         PIPE_CONF_CHECK_I(lane_count);
13286         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13287
13288         if (INTEL_INFO(dev)->gen < 8) {
13289                 PIPE_CONF_CHECK_M_N(dp_m_n);
13290
13291                 if (current_config->has_drrs)
13292                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13293         } else
13294                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13295
13296         PIPE_CONF_CHECK_X(output_types);
13297
13298         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13299         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13300         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13301         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13302         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13303         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13304
13305         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13306         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13307         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13308         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13309         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13310         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13311
13312         PIPE_CONF_CHECK_I(pixel_multiplier);
13313         PIPE_CONF_CHECK_I(has_hdmi_sink);
13314         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13315             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13316                 PIPE_CONF_CHECK_I(limited_color_range);
13317         PIPE_CONF_CHECK_I(has_infoframe);
13318
13319         PIPE_CONF_CHECK_I(has_audio);
13320
13321         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13322                               DRM_MODE_FLAG_INTERLACE);
13323
13324         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13325                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13326                                       DRM_MODE_FLAG_PHSYNC);
13327                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13328                                       DRM_MODE_FLAG_NHSYNC);
13329                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13330                                       DRM_MODE_FLAG_PVSYNC);
13331                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13332                                       DRM_MODE_FLAG_NVSYNC);
13333         }
13334
13335         PIPE_CONF_CHECK_X(gmch_pfit.control);
13336         /* pfit ratios are autocomputed by the hw on gen4+ */
13337         if (INTEL_INFO(dev)->gen < 4)
13338                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13339         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13340
13341         if (!adjust) {
13342                 PIPE_CONF_CHECK_I(pipe_src_w);
13343                 PIPE_CONF_CHECK_I(pipe_src_h);
13344
13345                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13346                 if (current_config->pch_pfit.enabled) {
13347                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13348                         PIPE_CONF_CHECK_X(pch_pfit.size);
13349                 }
13350
13351                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13352         }
13353
13354         /* BDW+ don't expose a synchronous way to read the state */
13355         if (IS_HASWELL(dev))
13356                 PIPE_CONF_CHECK_I(ips_enabled);
13357
13358         PIPE_CONF_CHECK_I(double_wide);
13359
13360         PIPE_CONF_CHECK_P(shared_dpll);
13361         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13362         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13363         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13364         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13365         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13366         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13367         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13368         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13369         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13370
13371         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13372         PIPE_CONF_CHECK_X(dsi_pll.div);
13373
13374         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13375                 PIPE_CONF_CHECK_I(pipe_bpp);
13376
13377         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13378         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13379
13380 #undef PIPE_CONF_CHECK_X
13381 #undef PIPE_CONF_CHECK_I
13382 #undef PIPE_CONF_CHECK_P
13383 #undef PIPE_CONF_CHECK_FLAGS
13384 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13385 #undef PIPE_CONF_QUIRK
13386 #undef INTEL_ERR_OR_DBG_KMS
13387
13388         return ret;
13389 }
13390
13391 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13392                                            const struct intel_crtc_state *pipe_config)
13393 {
13394         if (pipe_config->has_pch_encoder) {
13395                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13396                                                             &pipe_config->fdi_m_n);
13397                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13398
13399                 /*
13400                  * FDI already provided one idea for the dotclock.
13401                  * Yell if the encoder disagrees.
13402                  */
13403                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13404                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13405                      fdi_dotclock, dotclock);
13406         }
13407 }
13408
13409 static void verify_wm_state(struct drm_crtc *crtc,
13410                             struct drm_crtc_state *new_state)
13411 {
13412         struct drm_device *dev = crtc->dev;
13413         struct drm_i915_private *dev_priv = to_i915(dev);
13414         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13415         struct skl_ddb_entry *hw_entry, *sw_entry;
13416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13417         const enum pipe pipe = intel_crtc->pipe;
13418         int plane;
13419
13420         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13421                 return;
13422
13423         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13424         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13425
13426         /* planes */
13427         for_each_plane(dev_priv, pipe, plane) {
13428                 hw_entry = &hw_ddb.plane[pipe][plane];
13429                 sw_entry = &sw_ddb->plane[pipe][plane];
13430
13431                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13432                         continue;
13433
13434                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13435                           "(expected (%u,%u), found (%u,%u))\n",
13436                           pipe_name(pipe), plane + 1,
13437                           sw_entry->start, sw_entry->end,
13438                           hw_entry->start, hw_entry->end);
13439         }
13440
13441         /*
13442          * cursor
13443          * If the cursor plane isn't active, we may not have updated it's ddb
13444          * allocation. In that case since the ddb allocation will be updated
13445          * once the plane becomes visible, we can skip this check
13446          */
13447         if (intel_crtc->cursor_addr) {
13448                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13449                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13450
13451                 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13452                         DRM_ERROR("mismatch in DDB state pipe %c cursor "
13453                                   "(expected (%u,%u), found (%u,%u))\n",
13454                                   pipe_name(pipe),
13455                                   sw_entry->start, sw_entry->end,
13456                                   hw_entry->start, hw_entry->end);
13457                 }
13458         }
13459 }
13460
13461 static void
13462 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13463 {
13464         struct drm_connector *connector;
13465
13466         drm_for_each_connector(connector, dev) {
13467                 struct drm_encoder *encoder = connector->encoder;
13468                 struct drm_connector_state *state = connector->state;
13469
13470                 if (state->crtc != crtc)
13471                         continue;
13472
13473                 intel_connector_verify_state(to_intel_connector(connector));
13474
13475                 I915_STATE_WARN(state->best_encoder != encoder,
13476                      "connector's atomic encoder doesn't match legacy encoder\n");
13477         }
13478 }
13479
13480 static void
13481 verify_encoder_state(struct drm_device *dev)
13482 {
13483         struct intel_encoder *encoder;
13484         struct intel_connector *connector;
13485
13486         for_each_intel_encoder(dev, encoder) {
13487                 bool enabled = false;
13488                 enum pipe pipe;
13489
13490                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13491                               encoder->base.base.id,
13492                               encoder->base.name);
13493
13494                 for_each_intel_connector(dev, connector) {
13495                         if (connector->base.state->best_encoder != &encoder->base)
13496                                 continue;
13497                         enabled = true;
13498
13499                         I915_STATE_WARN(connector->base.state->crtc !=
13500                                         encoder->base.crtc,
13501                              "connector's crtc doesn't match encoder crtc\n");
13502                 }
13503
13504                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13505                      "encoder's enabled state mismatch "
13506                      "(expected %i, found %i)\n",
13507                      !!encoder->base.crtc, enabled);
13508
13509                 if (!encoder->base.crtc) {
13510                         bool active;
13511
13512                         active = encoder->get_hw_state(encoder, &pipe);
13513                         I915_STATE_WARN(active,
13514                              "encoder detached but still enabled on pipe %c.\n",
13515                              pipe_name(pipe));
13516                 }
13517         }
13518 }
13519
13520 static void
13521 verify_crtc_state(struct drm_crtc *crtc,
13522                   struct drm_crtc_state *old_crtc_state,
13523                   struct drm_crtc_state *new_crtc_state)
13524 {
13525         struct drm_device *dev = crtc->dev;
13526         struct drm_i915_private *dev_priv = to_i915(dev);
13527         struct intel_encoder *encoder;
13528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13529         struct intel_crtc_state *pipe_config, *sw_config;
13530         struct drm_atomic_state *old_state;
13531         bool active;
13532
13533         old_state = old_crtc_state->state;
13534         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13535         pipe_config = to_intel_crtc_state(old_crtc_state);
13536         memset(pipe_config, 0, sizeof(*pipe_config));
13537         pipe_config->base.crtc = crtc;
13538         pipe_config->base.state = old_state;
13539
13540         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13541
13542         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13543
13544         /* hw state is inconsistent with the pipe quirk */
13545         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13546             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13547                 active = new_crtc_state->active;
13548
13549         I915_STATE_WARN(new_crtc_state->active != active,
13550              "crtc active state doesn't match with hw state "
13551              "(expected %i, found %i)\n", new_crtc_state->active, active);
13552
13553         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13554              "transitional active state does not match atomic hw state "
13555              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13556
13557         for_each_encoder_on_crtc(dev, crtc, encoder) {
13558                 enum pipe pipe;
13559
13560                 active = encoder->get_hw_state(encoder, &pipe);
13561                 I915_STATE_WARN(active != new_crtc_state->active,
13562                         "[ENCODER:%i] active %i with crtc active %i\n",
13563                         encoder->base.base.id, active, new_crtc_state->active);
13564
13565                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13566                                 "Encoder connected to wrong pipe %c\n",
13567                                 pipe_name(pipe));
13568
13569                 if (active) {
13570                         pipe_config->output_types |= 1 << encoder->type;
13571                         encoder->get_config(encoder, pipe_config);
13572                 }
13573         }
13574
13575         if (!new_crtc_state->active)
13576                 return;
13577
13578         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13579
13580         sw_config = to_intel_crtc_state(crtc->state);
13581         if (!intel_pipe_config_compare(dev, sw_config,
13582                                        pipe_config, false)) {
13583                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13584                 intel_dump_pipe_config(intel_crtc, pipe_config,
13585                                        "[hw state]");
13586                 intel_dump_pipe_config(intel_crtc, sw_config,
13587                                        "[sw state]");
13588         }
13589 }
13590
13591 static void
13592 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13593                          struct intel_shared_dpll *pll,
13594                          struct drm_crtc *crtc,
13595                          struct drm_crtc_state *new_state)
13596 {
13597         struct intel_dpll_hw_state dpll_hw_state;
13598         unsigned crtc_mask;
13599         bool active;
13600
13601         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13602
13603         DRM_DEBUG_KMS("%s\n", pll->name);
13604
13605         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13606
13607         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13608                 I915_STATE_WARN(!pll->on && pll->active_mask,
13609                      "pll in active use but not on in sw tracking\n");
13610                 I915_STATE_WARN(pll->on && !pll->active_mask,
13611                      "pll is on but not used by any active crtc\n");
13612                 I915_STATE_WARN(pll->on != active,
13613                      "pll on state mismatch (expected %i, found %i)\n",
13614                      pll->on, active);
13615         }
13616
13617         if (!crtc) {
13618                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13619                                 "more active pll users than references: %x vs %x\n",
13620                                 pll->active_mask, pll->config.crtc_mask);
13621
13622                 return;
13623         }
13624
13625         crtc_mask = 1 << drm_crtc_index(crtc);
13626
13627         if (new_state->active)
13628                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13629                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13630                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13631         else
13632                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13633                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13634                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13635
13636         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13637                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13638                         crtc_mask, pll->config.crtc_mask);
13639
13640         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13641                                           &dpll_hw_state,
13642                                           sizeof(dpll_hw_state)),
13643                         "pll hw state mismatch\n");
13644 }
13645
13646 static void
13647 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13648                          struct drm_crtc_state *old_crtc_state,
13649                          struct drm_crtc_state *new_crtc_state)
13650 {
13651         struct drm_i915_private *dev_priv = to_i915(dev);
13652         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13653         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13654
13655         if (new_state->shared_dpll)
13656                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13657
13658         if (old_state->shared_dpll &&
13659             old_state->shared_dpll != new_state->shared_dpll) {
13660                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13661                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13662
13663                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13664                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13665                                 pipe_name(drm_crtc_index(crtc)));
13666                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13667                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13668                                 pipe_name(drm_crtc_index(crtc)));
13669         }
13670 }
13671
13672 static void
13673 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13674                          struct drm_crtc_state *old_state,
13675                          struct drm_crtc_state *new_state)
13676 {
13677         if (!needs_modeset(new_state) &&
13678             !to_intel_crtc_state(new_state)->update_pipe)
13679                 return;
13680
13681         verify_wm_state(crtc, new_state);
13682         verify_connector_state(crtc->dev, crtc);
13683         verify_crtc_state(crtc, old_state, new_state);
13684         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13685 }
13686
13687 static void
13688 verify_disabled_dpll_state(struct drm_device *dev)
13689 {
13690         struct drm_i915_private *dev_priv = to_i915(dev);
13691         int i;
13692
13693         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13694                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13695 }
13696
13697 static void
13698 intel_modeset_verify_disabled(struct drm_device *dev)
13699 {
13700         verify_encoder_state(dev);
13701         verify_connector_state(dev, NULL);
13702         verify_disabled_dpll_state(dev);
13703 }
13704
13705 static void update_scanline_offset(struct intel_crtc *crtc)
13706 {
13707         struct drm_device *dev = crtc->base.dev;
13708
13709         /*
13710          * The scanline counter increments at the leading edge of hsync.
13711          *
13712          * On most platforms it starts counting from vtotal-1 on the
13713          * first active line. That means the scanline counter value is
13714          * always one less than what we would expect. Ie. just after
13715          * start of vblank, which also occurs at start of hsync (on the
13716          * last active line), the scanline counter will read vblank_start-1.
13717          *
13718          * On gen2 the scanline counter starts counting from 1 instead
13719          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13720          * to keep the value positive), instead of adding one.
13721          *
13722          * On HSW+ the behaviour of the scanline counter depends on the output
13723          * type. For DP ports it behaves like most other platforms, but on HDMI
13724          * there's an extra 1 line difference. So we need to add two instead of
13725          * one to the value.
13726          */
13727         if (IS_GEN2(dev)) {
13728                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13729                 int vtotal;
13730
13731                 vtotal = adjusted_mode->crtc_vtotal;
13732                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13733                         vtotal /= 2;
13734
13735                 crtc->scanline_offset = vtotal - 1;
13736         } else if (HAS_DDI(dev) &&
13737                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13738                 crtc->scanline_offset = 2;
13739         } else
13740                 crtc->scanline_offset = 1;
13741 }
13742
13743 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13744 {
13745         struct drm_device *dev = state->dev;
13746         struct drm_i915_private *dev_priv = to_i915(dev);
13747         struct intel_shared_dpll_config *shared_dpll = NULL;
13748         struct drm_crtc *crtc;
13749         struct drm_crtc_state *crtc_state;
13750         int i;
13751
13752         if (!dev_priv->display.crtc_compute_clock)
13753                 return;
13754
13755         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13756                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13757                 struct intel_shared_dpll *old_dpll =
13758                         to_intel_crtc_state(crtc->state)->shared_dpll;
13759
13760                 if (!needs_modeset(crtc_state))
13761                         continue;
13762
13763                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13764
13765                 if (!old_dpll)
13766                         continue;
13767
13768                 if (!shared_dpll)
13769                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13770
13771                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13772         }
13773 }
13774
13775 /*
13776  * This implements the workaround described in the "notes" section of the mode
13777  * set sequence documentation. When going from no pipes or single pipe to
13778  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13779  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13780  */
13781 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13782 {
13783         struct drm_crtc_state *crtc_state;
13784         struct intel_crtc *intel_crtc;
13785         struct drm_crtc *crtc;
13786         struct intel_crtc_state *first_crtc_state = NULL;
13787         struct intel_crtc_state *other_crtc_state = NULL;
13788         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13789         int i;
13790
13791         /* look at all crtc's that are going to be enabled in during modeset */
13792         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13793                 intel_crtc = to_intel_crtc(crtc);
13794
13795                 if (!crtc_state->active || !needs_modeset(crtc_state))
13796                         continue;
13797
13798                 if (first_crtc_state) {
13799                         other_crtc_state = to_intel_crtc_state(crtc_state);
13800                         break;
13801                 } else {
13802                         first_crtc_state = to_intel_crtc_state(crtc_state);
13803                         first_pipe = intel_crtc->pipe;
13804                 }
13805         }
13806
13807         /* No workaround needed? */
13808         if (!first_crtc_state)
13809                 return 0;
13810
13811         /* w/a possibly needed, check how many crtc's are already enabled. */
13812         for_each_intel_crtc(state->dev, intel_crtc) {
13813                 struct intel_crtc_state *pipe_config;
13814
13815                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13816                 if (IS_ERR(pipe_config))
13817                         return PTR_ERR(pipe_config);
13818
13819                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13820
13821                 if (!pipe_config->base.active ||
13822                     needs_modeset(&pipe_config->base))
13823                         continue;
13824
13825                 /* 2 or more enabled crtcs means no need for w/a */
13826                 if (enabled_pipe != INVALID_PIPE)
13827                         return 0;
13828
13829                 enabled_pipe = intel_crtc->pipe;
13830         }
13831
13832         if (enabled_pipe != INVALID_PIPE)
13833                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13834         else if (other_crtc_state)
13835                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13836
13837         return 0;
13838 }
13839
13840 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13841 {
13842         struct drm_crtc *crtc;
13843         struct drm_crtc_state *crtc_state;
13844         int ret = 0;
13845
13846         /* add all active pipes to the state */
13847         for_each_crtc(state->dev, crtc) {
13848                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13849                 if (IS_ERR(crtc_state))
13850                         return PTR_ERR(crtc_state);
13851
13852                 if (!crtc_state->active || needs_modeset(crtc_state))
13853                         continue;
13854
13855                 crtc_state->mode_changed = true;
13856
13857                 ret = drm_atomic_add_affected_connectors(state, crtc);
13858                 if (ret)
13859                         break;
13860
13861                 ret = drm_atomic_add_affected_planes(state, crtc);
13862                 if (ret)
13863                         break;
13864         }
13865
13866         return ret;
13867 }
13868
13869 static int intel_modeset_checks(struct drm_atomic_state *state)
13870 {
13871         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13872         struct drm_i915_private *dev_priv = to_i915(state->dev);
13873         struct drm_crtc *crtc;
13874         struct drm_crtc_state *crtc_state;
13875         int ret = 0, i;
13876
13877         if (!check_digital_port_conflicts(state)) {
13878                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13879                 return -EINVAL;
13880         }
13881
13882         intel_state->modeset = true;
13883         intel_state->active_crtcs = dev_priv->active_crtcs;
13884
13885         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13886                 if (crtc_state->active)
13887                         intel_state->active_crtcs |= 1 << i;
13888                 else
13889                         intel_state->active_crtcs &= ~(1 << i);
13890
13891                 if (crtc_state->active != crtc->state->active)
13892                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13893         }
13894
13895         /*
13896          * See if the config requires any additional preparation, e.g.
13897          * to adjust global state with pipes off.  We need to do this
13898          * here so we can get the modeset_pipe updated config for the new
13899          * mode set on this crtc.  For other crtcs we need to use the
13900          * adjusted_mode bits in the crtc directly.
13901          */
13902         if (dev_priv->display.modeset_calc_cdclk) {
13903                 if (!intel_state->cdclk_pll_vco)
13904                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13905                 if (!intel_state->cdclk_pll_vco)
13906                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13907
13908                 ret = dev_priv->display.modeset_calc_cdclk(state);
13909                 if (ret < 0)
13910                         return ret;
13911
13912                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13913                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13914                         ret = intel_modeset_all_pipes(state);
13915
13916                 if (ret < 0)
13917                         return ret;
13918
13919                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13920                               intel_state->cdclk, intel_state->dev_cdclk);
13921         } else
13922                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13923
13924         intel_modeset_clear_plls(state);
13925
13926         if (IS_HASWELL(dev_priv))
13927                 return haswell_mode_set_planes_workaround(state);
13928
13929         return 0;
13930 }
13931
13932 /*
13933  * Handle calculation of various watermark data at the end of the atomic check
13934  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13935  * handlers to ensure that all derived state has been updated.
13936  */
13937 static int calc_watermark_data(struct drm_atomic_state *state)
13938 {
13939         struct drm_device *dev = state->dev;
13940         struct drm_i915_private *dev_priv = to_i915(dev);
13941
13942         /* Is there platform-specific watermark information to calculate? */
13943         if (dev_priv->display.compute_global_watermarks)
13944                 return dev_priv->display.compute_global_watermarks(state);
13945
13946         return 0;
13947 }
13948
13949 /**
13950  * intel_atomic_check - validate state object
13951  * @dev: drm device
13952  * @state: state to validate
13953  */
13954 static int intel_atomic_check(struct drm_device *dev,
13955                               struct drm_atomic_state *state)
13956 {
13957         struct drm_i915_private *dev_priv = to_i915(dev);
13958         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13959         struct drm_crtc *crtc;
13960         struct drm_crtc_state *crtc_state;
13961         int ret, i;
13962         bool any_ms = false;
13963
13964         ret = drm_atomic_helper_check_modeset(dev, state);
13965         if (ret)
13966                 return ret;
13967
13968         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13969                 struct intel_crtc_state *pipe_config =
13970                         to_intel_crtc_state(crtc_state);
13971
13972                 /* Catch I915_MODE_FLAG_INHERITED */
13973                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13974                         crtc_state->mode_changed = true;
13975
13976                 if (!needs_modeset(crtc_state))
13977                         continue;
13978
13979                 if (!crtc_state->enable) {
13980                         any_ms = true;
13981                         continue;
13982                 }
13983
13984                 /* FIXME: For only active_changed we shouldn't need to do any
13985                  * state recomputation at all. */
13986
13987                 ret = drm_atomic_add_affected_connectors(state, crtc);
13988                 if (ret)
13989                         return ret;
13990
13991                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13992                 if (ret) {
13993                         intel_dump_pipe_config(to_intel_crtc(crtc),
13994                                                pipe_config, "[failed]");
13995                         return ret;
13996                 }
13997
13998                 if (i915.fastboot &&
13999                     intel_pipe_config_compare(dev,
14000                                         to_intel_crtc_state(crtc->state),
14001                                         pipe_config, true)) {
14002                         crtc_state->mode_changed = false;
14003                         to_intel_crtc_state(crtc_state)->update_pipe = true;
14004                 }
14005
14006                 if (needs_modeset(crtc_state))
14007                         any_ms = true;
14008
14009                 ret = drm_atomic_add_affected_planes(state, crtc);
14010                 if (ret)
14011                         return ret;
14012
14013                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14014                                        needs_modeset(crtc_state) ?
14015                                        "[modeset]" : "[fastset]");
14016         }
14017
14018         if (any_ms) {
14019                 ret = intel_modeset_checks(state);
14020
14021                 if (ret)
14022                         return ret;
14023         } else
14024                 intel_state->cdclk = dev_priv->cdclk_freq;
14025
14026         ret = drm_atomic_helper_check_planes(dev, state);
14027         if (ret)
14028                 return ret;
14029
14030         intel_fbc_choose_crtc(dev_priv, state);
14031         return calc_watermark_data(state);
14032 }
14033
14034 static int intel_atomic_prepare_commit(struct drm_device *dev,
14035                                        struct drm_atomic_state *state,
14036                                        bool nonblock)
14037 {
14038         struct drm_i915_private *dev_priv = to_i915(dev);
14039         struct drm_plane_state *plane_state;
14040         struct drm_crtc_state *crtc_state;
14041         struct drm_plane *plane;
14042         struct drm_crtc *crtc;
14043         int i, ret;
14044
14045         for_each_crtc_in_state(state, crtc, crtc_state, i) {
14046                 if (state->legacy_cursor_update)
14047                         continue;
14048
14049                 ret = intel_crtc_wait_for_pending_flips(crtc);
14050                 if (ret)
14051                         return ret;
14052
14053                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14054                         flush_workqueue(dev_priv->wq);
14055         }
14056
14057         ret = mutex_lock_interruptible(&dev->struct_mutex);
14058         if (ret)
14059                 return ret;
14060
14061         ret = drm_atomic_helper_prepare_planes(dev, state);
14062         mutex_unlock(&dev->struct_mutex);
14063
14064         if (!ret && !nonblock) {
14065                 for_each_plane_in_state(state, plane, plane_state, i) {
14066                         struct intel_plane_state *intel_plane_state =
14067                                 to_intel_plane_state(plane_state);
14068
14069                         if (!intel_plane_state->wait_req)
14070                                 continue;
14071
14072                         ret = i915_wait_request(intel_plane_state->wait_req,
14073                                                 I915_WAIT_INTERRUPTIBLE,
14074                                                 NULL, NULL);
14075                         if (ret) {
14076                                 /* Any hang should be swallowed by the wait */
14077                                 WARN_ON(ret == -EIO);
14078                                 mutex_lock(&dev->struct_mutex);
14079                                 drm_atomic_helper_cleanup_planes(dev, state);
14080                                 mutex_unlock(&dev->struct_mutex);
14081                                 break;
14082                         }
14083                 }
14084         }
14085
14086         return ret;
14087 }
14088
14089 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14090 {
14091         struct drm_device *dev = crtc->base.dev;
14092
14093         if (!dev->max_vblank_count)
14094                 return drm_accurate_vblank_count(&crtc->base);
14095
14096         return dev->driver->get_vblank_counter(dev, crtc->pipe);
14097 }
14098
14099 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14100                                           struct drm_i915_private *dev_priv,
14101                                           unsigned crtc_mask)
14102 {
14103         unsigned last_vblank_count[I915_MAX_PIPES];
14104         enum pipe pipe;
14105         int ret;
14106
14107         if (!crtc_mask)
14108                 return;
14109
14110         for_each_pipe(dev_priv, pipe) {
14111                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14112
14113                 if (!((1 << pipe) & crtc_mask))
14114                         continue;
14115
14116                 ret = drm_crtc_vblank_get(crtc);
14117                 if (WARN_ON(ret != 0)) {
14118                         crtc_mask &= ~(1 << pipe);
14119                         continue;
14120                 }
14121
14122                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14123         }
14124
14125         for_each_pipe(dev_priv, pipe) {
14126                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14127                 long lret;
14128
14129                 if (!((1 << pipe) & crtc_mask))
14130                         continue;
14131
14132                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14133                                 last_vblank_count[pipe] !=
14134                                         drm_crtc_vblank_count(crtc),
14135                                 msecs_to_jiffies(50));
14136
14137                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14138
14139                 drm_crtc_vblank_put(crtc);
14140         }
14141 }
14142
14143 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14144 {
14145         /* fb updated, need to unpin old fb */
14146         if (crtc_state->fb_changed)
14147                 return true;
14148
14149         /* wm changes, need vblank before final wm's */
14150         if (crtc_state->update_wm_post)
14151                 return true;
14152
14153         /*
14154          * cxsr is re-enabled after vblank.
14155          * This is already handled by crtc_state->update_wm_post,
14156          * but added for clarity.
14157          */
14158         if (crtc_state->disable_cxsr)
14159                 return true;
14160
14161         return false;
14162 }
14163
14164 static void intel_update_crtc(struct drm_crtc *crtc,
14165                               struct drm_atomic_state *state,
14166                               struct drm_crtc_state *old_crtc_state,
14167                               unsigned int *crtc_vblank_mask)
14168 {
14169         struct drm_device *dev = crtc->dev;
14170         struct drm_i915_private *dev_priv = to_i915(dev);
14171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14172         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14173         bool modeset = needs_modeset(crtc->state);
14174
14175         if (modeset) {
14176                 update_scanline_offset(intel_crtc);
14177                 dev_priv->display.crtc_enable(pipe_config, state);
14178         } else {
14179                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14180         }
14181
14182         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14183                 intel_fbc_enable(
14184                     intel_crtc, pipe_config,
14185                     to_intel_plane_state(crtc->primary->state));
14186         }
14187
14188         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14189
14190         if (needs_vblank_wait(pipe_config))
14191                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14192 }
14193
14194 static void intel_update_crtcs(struct drm_atomic_state *state,
14195                                unsigned int *crtc_vblank_mask)
14196 {
14197         struct drm_crtc *crtc;
14198         struct drm_crtc_state *old_crtc_state;
14199         int i;
14200
14201         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14202                 if (!crtc->state->active)
14203                         continue;
14204
14205                 intel_update_crtc(crtc, state, old_crtc_state,
14206                                   crtc_vblank_mask);
14207         }
14208 }
14209
14210 static void skl_update_crtcs(struct drm_atomic_state *state,
14211                              unsigned int *crtc_vblank_mask)
14212 {
14213         struct drm_device *dev = state->dev;
14214         struct drm_i915_private *dev_priv = to_i915(dev);
14215         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14216         struct drm_crtc *crtc;
14217         struct drm_crtc_state *old_crtc_state;
14218         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14219         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14220         unsigned int updated = 0;
14221         bool progress;
14222         enum pipe pipe;
14223
14224         /*
14225          * Whenever the number of active pipes changes, we need to make sure we
14226          * update the pipes in the right order so that their ddb allocations
14227          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14228          * cause pipe underruns and other bad stuff.
14229          */
14230         do {
14231                 int i;
14232                 progress = false;
14233
14234                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14235                         bool vbl_wait = false;
14236                         unsigned int cmask = drm_crtc_mask(crtc);
14237                         pipe = to_intel_crtc(crtc)->pipe;
14238
14239                         if (updated & cmask || !crtc->state->active)
14240                                 continue;
14241                         if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14242                                                         pipe))
14243                                 continue;
14244
14245                         updated |= cmask;
14246
14247                         /*
14248                          * If this is an already active pipe, it's DDB changed,
14249                          * and this isn't the last pipe that needs updating
14250                          * then we need to wait for a vblank to pass for the
14251                          * new ddb allocation to take effect.
14252                          */
14253                         if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14254                             !crtc->state->active_changed &&
14255                             intel_state->wm_results.dirty_pipes != updated)
14256                                 vbl_wait = true;
14257
14258                         intel_update_crtc(crtc, state, old_crtc_state,
14259                                           crtc_vblank_mask);
14260
14261                         if (vbl_wait)
14262                                 intel_wait_for_vblank(dev, pipe);
14263
14264                         progress = true;
14265                 }
14266         } while (progress);
14267 }
14268
14269 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14270 {
14271         struct drm_device *dev = state->dev;
14272         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14273         struct drm_i915_private *dev_priv = to_i915(dev);
14274         struct drm_crtc_state *old_crtc_state;
14275         struct drm_crtc *crtc;
14276         struct intel_crtc_state *intel_cstate;
14277         struct drm_plane *plane;
14278         struct drm_plane_state *plane_state;
14279         bool hw_check = intel_state->modeset;
14280         unsigned long put_domains[I915_MAX_PIPES] = {};
14281         unsigned crtc_vblank_mask = 0;
14282         int i, ret;
14283
14284         for_each_plane_in_state(state, plane, plane_state, i) {
14285                 struct intel_plane_state *intel_plane_state =
14286                         to_intel_plane_state(plane_state);
14287
14288                 if (!intel_plane_state->wait_req)
14289                         continue;
14290
14291                 ret = i915_wait_request(intel_plane_state->wait_req,
14292                                         0, NULL, NULL);
14293                 /* EIO should be eaten, and we can't get interrupted in the
14294                  * worker, and blocking commits have waited already. */
14295                 WARN_ON(ret);
14296         }
14297
14298         drm_atomic_helper_wait_for_dependencies(state);
14299
14300         if (intel_state->modeset) {
14301                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14302                        sizeof(intel_state->min_pixclk));
14303                 dev_priv->active_crtcs = intel_state->active_crtcs;
14304                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14305
14306                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14307         }
14308
14309         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14310                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14311
14312                 if (needs_modeset(crtc->state) ||
14313                     to_intel_crtc_state(crtc->state)->update_pipe) {
14314                         hw_check = true;
14315
14316                         put_domains[to_intel_crtc(crtc)->pipe] =
14317                                 modeset_get_crtc_power_domains(crtc,
14318                                         to_intel_crtc_state(crtc->state));
14319                 }
14320
14321                 if (!needs_modeset(crtc->state))
14322                         continue;
14323
14324                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14325
14326                 if (old_crtc_state->active) {
14327                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14328                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14329                         intel_crtc->active = false;
14330                         intel_fbc_disable(intel_crtc);
14331                         intel_disable_shared_dpll(intel_crtc);
14332
14333                         /*
14334                          * Underruns don't always raise
14335                          * interrupts, so check manually.
14336                          */
14337                         intel_check_cpu_fifo_underruns(dev_priv);
14338                         intel_check_pch_fifo_underruns(dev_priv);
14339
14340                         if (!crtc->state->active)
14341                                 intel_update_watermarks(crtc);
14342                 }
14343         }
14344
14345         /* Only after disabling all output pipelines that will be changed can we
14346          * update the the output configuration. */
14347         intel_modeset_update_crtc_state(state);
14348
14349         if (intel_state->modeset) {
14350                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14351
14352                 if (dev_priv->display.modeset_commit_cdclk &&
14353                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14354                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14355                         dev_priv->display.modeset_commit_cdclk(state);
14356
14357                 /*
14358                  * SKL workaround: bspec recommends we disable the SAGV when we
14359                  * have more then one pipe enabled
14360                  */
14361                 if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
14362                         skl_disable_sagv(dev_priv);
14363
14364                 intel_modeset_verify_disabled(dev);
14365         }
14366
14367         /* Complete the events for pipes that have now been disabled */
14368         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14369                 bool modeset = needs_modeset(crtc->state);
14370
14371                 /* Complete events for now disable pipes here. */
14372                 if (modeset && !crtc->state->active && crtc->state->event) {
14373                         spin_lock_irq(&dev->event_lock);
14374                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14375                         spin_unlock_irq(&dev->event_lock);
14376
14377                         crtc->state->event = NULL;
14378                 }
14379         }
14380
14381         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14382         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14383
14384         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14385          * already, but still need the state for the delayed optimization. To
14386          * fix this:
14387          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14388          * - schedule that vblank worker _before_ calling hw_done
14389          * - at the start of commit_tail, cancel it _synchrously
14390          * - switch over to the vblank wait helper in the core after that since
14391          *   we don't need out special handling any more.
14392          */
14393         if (!state->legacy_cursor_update)
14394                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14395
14396         /*
14397          * Now that the vblank has passed, we can go ahead and program the
14398          * optimal watermarks on platforms that need two-step watermark
14399          * programming.
14400          *
14401          * TODO: Move this (and other cleanup) to an async worker eventually.
14402          */
14403         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14404                 intel_cstate = to_intel_crtc_state(crtc->state);
14405
14406                 if (dev_priv->display.optimize_watermarks)
14407                         dev_priv->display.optimize_watermarks(intel_cstate);
14408         }
14409
14410         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14411                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14412
14413                 if (put_domains[i])
14414                         modeset_put_power_domains(dev_priv, put_domains[i]);
14415
14416                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14417         }
14418
14419         if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
14420             skl_can_enable_sagv(state))
14421                 skl_enable_sagv(dev_priv);
14422
14423         drm_atomic_helper_commit_hw_done(state);
14424
14425         if (intel_state->modeset)
14426                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14427
14428         mutex_lock(&dev->struct_mutex);
14429         drm_atomic_helper_cleanup_planes(dev, state);
14430         mutex_unlock(&dev->struct_mutex);
14431
14432         drm_atomic_helper_commit_cleanup_done(state);
14433
14434         drm_atomic_state_free(state);
14435
14436         /* As one of the primary mmio accessors, KMS has a high likelihood
14437          * of triggering bugs in unclaimed access. After we finish
14438          * modesetting, see if an error has been flagged, and if so
14439          * enable debugging for the next modeset - and hope we catch
14440          * the culprit.
14441          *
14442          * XXX note that we assume display power is on at this point.
14443          * This might hold true now but we need to add pm helper to check
14444          * unclaimed only when the hardware is on, as atomic commits
14445          * can happen also when the device is completely off.
14446          */
14447         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14448 }
14449
14450 static void intel_atomic_commit_work(struct work_struct *work)
14451 {
14452         struct drm_atomic_state *state = container_of(work,
14453                                                       struct drm_atomic_state,
14454                                                       commit_work);
14455         intel_atomic_commit_tail(state);
14456 }
14457
14458 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14459 {
14460         struct drm_plane_state *old_plane_state;
14461         struct drm_plane *plane;
14462         int i;
14463
14464         for_each_plane_in_state(state, plane, old_plane_state, i)
14465                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14466                                   intel_fb_obj(plane->state->fb),
14467                                   to_intel_plane(plane)->frontbuffer_bit);
14468 }
14469
14470 /**
14471  * intel_atomic_commit - commit validated state object
14472  * @dev: DRM device
14473  * @state: the top-level driver state object
14474  * @nonblock: nonblocking commit
14475  *
14476  * This function commits a top-level state object that has been validated
14477  * with drm_atomic_helper_check().
14478  *
14479  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14480  * nonblocking commits are only safe for pure plane updates. Everything else
14481  * should work though.
14482  *
14483  * RETURNS
14484  * Zero for success or -errno.
14485  */
14486 static int intel_atomic_commit(struct drm_device *dev,
14487                                struct drm_atomic_state *state,
14488                                bool nonblock)
14489 {
14490         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14491         struct drm_i915_private *dev_priv = to_i915(dev);
14492         int ret = 0;
14493
14494         if (intel_state->modeset && nonblock) {
14495                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14496                 return -EINVAL;
14497         }
14498
14499         ret = drm_atomic_helper_setup_commit(state, nonblock);
14500         if (ret)
14501                 return ret;
14502
14503         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14504
14505         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14506         if (ret) {
14507                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14508                 return ret;
14509         }
14510
14511         drm_atomic_helper_swap_state(state, true);
14512         dev_priv->wm.distrust_bios_wm = false;
14513         dev_priv->wm.skl_results = intel_state->wm_results;
14514         intel_shared_dpll_commit(state);
14515         intel_atomic_track_fbs(state);
14516
14517         if (nonblock)
14518                 queue_work(system_unbound_wq, &state->commit_work);
14519         else
14520                 intel_atomic_commit_tail(state);
14521
14522         return 0;
14523 }
14524
14525 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14526 {
14527         struct drm_device *dev = crtc->dev;
14528         struct drm_atomic_state *state;
14529         struct drm_crtc_state *crtc_state;
14530         int ret;
14531
14532         state = drm_atomic_state_alloc(dev);
14533         if (!state) {
14534                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14535                               crtc->base.id, crtc->name);
14536                 return;
14537         }
14538
14539         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14540
14541 retry:
14542         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14543         ret = PTR_ERR_OR_ZERO(crtc_state);
14544         if (!ret) {
14545                 if (!crtc_state->active)
14546                         goto out;
14547
14548                 crtc_state->mode_changed = true;
14549                 ret = drm_atomic_commit(state);
14550         }
14551
14552         if (ret == -EDEADLK) {
14553                 drm_atomic_state_clear(state);
14554                 drm_modeset_backoff(state->acquire_ctx);
14555                 goto retry;
14556         }
14557
14558         if (ret)
14559 out:
14560                 drm_atomic_state_free(state);
14561 }
14562
14563 /*
14564  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14565  *        drm_atomic_helper_legacy_gamma_set() directly.
14566  */
14567 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14568                                          u16 *red, u16 *green, u16 *blue,
14569                                          uint32_t size)
14570 {
14571         struct drm_device *dev = crtc->dev;
14572         struct drm_mode_config *config = &dev->mode_config;
14573         struct drm_crtc_state *state;
14574         int ret;
14575
14576         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14577         if (ret)
14578                 return ret;
14579
14580         /*
14581          * Make sure we update the legacy properties so this works when
14582          * atomic is not enabled.
14583          */
14584
14585         state = crtc->state;
14586
14587         drm_object_property_set_value(&crtc->base,
14588                                       config->degamma_lut_property,
14589                                       (state->degamma_lut) ?
14590                                       state->degamma_lut->base.id : 0);
14591
14592         drm_object_property_set_value(&crtc->base,
14593                                       config->ctm_property,
14594                                       (state->ctm) ?
14595                                       state->ctm->base.id : 0);
14596
14597         drm_object_property_set_value(&crtc->base,
14598                                       config->gamma_lut_property,
14599                                       (state->gamma_lut) ?
14600                                       state->gamma_lut->base.id : 0);
14601
14602         return 0;
14603 }
14604
14605 static const struct drm_crtc_funcs intel_crtc_funcs = {
14606         .gamma_set = intel_atomic_legacy_gamma_set,
14607         .set_config = drm_atomic_helper_set_config,
14608         .set_property = drm_atomic_helper_crtc_set_property,
14609         .destroy = intel_crtc_destroy,
14610         .page_flip = intel_crtc_page_flip,
14611         .atomic_duplicate_state = intel_crtc_duplicate_state,
14612         .atomic_destroy_state = intel_crtc_destroy_state,
14613 };
14614
14615 /**
14616  * intel_prepare_plane_fb - Prepare fb for usage on plane
14617  * @plane: drm plane to prepare for
14618  * @fb: framebuffer to prepare for presentation
14619  *
14620  * Prepares a framebuffer for usage on a display plane.  Generally this
14621  * involves pinning the underlying object and updating the frontbuffer tracking
14622  * bits.  Some older platforms need special physical address handling for
14623  * cursor planes.
14624  *
14625  * Must be called with struct_mutex held.
14626  *
14627  * Returns 0 on success, negative error code on failure.
14628  */
14629 int
14630 intel_prepare_plane_fb(struct drm_plane *plane,
14631                        const struct drm_plane_state *new_state)
14632 {
14633         struct drm_device *dev = plane->dev;
14634         struct drm_framebuffer *fb = new_state->fb;
14635         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14636         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14637         struct reservation_object *resv;
14638         int ret = 0;
14639
14640         if (!obj && !old_obj)
14641                 return 0;
14642
14643         if (old_obj) {
14644                 struct drm_crtc_state *crtc_state =
14645                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14646
14647                 /* Big Hammer, we also need to ensure that any pending
14648                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14649                  * current scanout is retired before unpinning the old
14650                  * framebuffer. Note that we rely on userspace rendering
14651                  * into the buffer attached to the pipe they are waiting
14652                  * on. If not, userspace generates a GPU hang with IPEHR
14653                  * point to the MI_WAIT_FOR_EVENT.
14654                  *
14655                  * This should only fail upon a hung GPU, in which case we
14656                  * can safely continue.
14657                  */
14658                 if (needs_modeset(crtc_state))
14659                         ret = i915_gem_object_wait_rendering(old_obj, true);
14660                 if (ret) {
14661                         /* GPU hangs should have been swallowed by the wait */
14662                         WARN_ON(ret == -EIO);
14663                         return ret;
14664                 }
14665         }
14666
14667         if (!obj)
14668                 return 0;
14669
14670         /* For framebuffer backed by dmabuf, wait for fence */
14671         resv = i915_gem_object_get_dmabuf_resv(obj);
14672         if (resv) {
14673                 long lret;
14674
14675                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14676                                                            MAX_SCHEDULE_TIMEOUT);
14677                 if (lret == -ERESTARTSYS)
14678                         return lret;
14679
14680                 WARN(lret < 0, "waiting returns %li\n", lret);
14681         }
14682
14683         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14684             INTEL_INFO(dev)->cursor_needs_physical) {
14685                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14686                 ret = i915_gem_object_attach_phys(obj, align);
14687                 if (ret)
14688                         DRM_DEBUG_KMS("failed to attach phys object\n");
14689         } else {
14690                 struct i915_vma *vma;
14691
14692                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14693                 if (IS_ERR(vma))
14694                         ret = PTR_ERR(vma);
14695         }
14696
14697         if (ret == 0) {
14698                 to_intel_plane_state(new_state)->wait_req =
14699                         i915_gem_active_get(&obj->last_write,
14700                                             &obj->base.dev->struct_mutex);
14701         }
14702
14703         return ret;
14704 }
14705
14706 /**
14707  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14708  * @plane: drm plane to clean up for
14709  * @fb: old framebuffer that was on plane
14710  *
14711  * Cleans up a framebuffer that has just been removed from a plane.
14712  *
14713  * Must be called with struct_mutex held.
14714  */
14715 void
14716 intel_cleanup_plane_fb(struct drm_plane *plane,
14717                        const struct drm_plane_state *old_state)
14718 {
14719         struct drm_device *dev = plane->dev;
14720         struct intel_plane_state *old_intel_state;
14721         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14722         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14723         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14724
14725         old_intel_state = to_intel_plane_state(old_state);
14726
14727         if (!obj && !old_obj)
14728                 return;
14729
14730         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14731             !INTEL_INFO(dev)->cursor_needs_physical))
14732                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14733
14734         i915_gem_request_assign(&intel_state->wait_req, NULL);
14735         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14736 }
14737
14738 int
14739 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14740 {
14741         int max_scale;
14742         int crtc_clock, cdclk;
14743
14744         if (!intel_crtc || !crtc_state->base.enable)
14745                 return DRM_PLANE_HELPER_NO_SCALING;
14746
14747         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14748         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14749
14750         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14751                 return DRM_PLANE_HELPER_NO_SCALING;
14752
14753         /*
14754          * skl max scale is lower of:
14755          *    close to 3 but not 3, -1 is for that purpose
14756          *            or
14757          *    cdclk/crtc_clock
14758          */
14759         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14760
14761         return max_scale;
14762 }
14763
14764 static int
14765 intel_check_primary_plane(struct drm_plane *plane,
14766                           struct intel_crtc_state *crtc_state,
14767                           struct intel_plane_state *state)
14768 {
14769         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14770         struct drm_crtc *crtc = state->base.crtc;
14771         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14772         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14773         bool can_position = false;
14774         int ret;
14775
14776         if (INTEL_GEN(dev_priv) >= 9) {
14777                 /* use scaler when colorkey is not required */
14778                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14779                         min_scale = 1;
14780                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14781                 }
14782                 can_position = true;
14783         }
14784
14785         ret = drm_plane_helper_check_state(&state->base,
14786                                            &state->clip,
14787                                            min_scale, max_scale,
14788                                            can_position, true);
14789         if (ret)
14790                 return ret;
14791
14792         if (!state->base.fb)
14793                 return 0;
14794
14795         if (INTEL_GEN(dev_priv) >= 9) {
14796                 ret = skl_check_plane_surface(state);
14797                 if (ret)
14798                         return ret;
14799         }
14800
14801         return 0;
14802 }
14803
14804 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14805                                     struct drm_crtc_state *old_crtc_state)
14806 {
14807         struct drm_device *dev = crtc->dev;
14808         struct drm_i915_private *dev_priv = to_i915(dev);
14809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14810         struct intel_crtc_state *old_intel_state =
14811                 to_intel_crtc_state(old_crtc_state);
14812         bool modeset = needs_modeset(crtc->state);
14813         enum pipe pipe = intel_crtc->pipe;
14814
14815         /* Perform vblank evasion around commit operation */
14816         intel_pipe_update_start(intel_crtc);
14817
14818         if (modeset)
14819                 return;
14820
14821         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14822                 intel_color_set_csc(crtc->state);
14823                 intel_color_load_luts(crtc->state);
14824         }
14825
14826         if (to_intel_crtc_state(crtc->state)->update_pipe)
14827                 intel_update_pipe_config(intel_crtc, old_intel_state);
14828         else if (INTEL_GEN(dev_priv) >= 9) {
14829                 skl_detach_scalers(intel_crtc);
14830
14831                 I915_WRITE(PIPE_WM_LINETIME(pipe),
14832                            dev_priv->wm.skl_hw.wm_linetime[pipe]);
14833         }
14834 }
14835
14836 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14837                                      struct drm_crtc_state *old_crtc_state)
14838 {
14839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14840
14841         intel_pipe_update_end(intel_crtc, NULL);
14842 }
14843
14844 /**
14845  * intel_plane_destroy - destroy a plane
14846  * @plane: plane to destroy
14847  *
14848  * Common destruction function for all types of planes (primary, cursor,
14849  * sprite).
14850  */
14851 void intel_plane_destroy(struct drm_plane *plane)
14852 {
14853         if (!plane)
14854                 return;
14855
14856         drm_plane_cleanup(plane);
14857         kfree(to_intel_plane(plane));
14858 }
14859
14860 const struct drm_plane_funcs intel_plane_funcs = {
14861         .update_plane = drm_atomic_helper_update_plane,
14862         .disable_plane = drm_atomic_helper_disable_plane,
14863         .destroy = intel_plane_destroy,
14864         .set_property = drm_atomic_helper_plane_set_property,
14865         .atomic_get_property = intel_plane_atomic_get_property,
14866         .atomic_set_property = intel_plane_atomic_set_property,
14867         .atomic_duplicate_state = intel_plane_duplicate_state,
14868         .atomic_destroy_state = intel_plane_destroy_state,
14869
14870 };
14871
14872 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14873                                                     int pipe)
14874 {
14875         struct intel_plane *primary = NULL;
14876         struct intel_plane_state *state = NULL;
14877         const uint32_t *intel_primary_formats;
14878         unsigned int num_formats;
14879         int ret;
14880
14881         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14882         if (!primary)
14883                 goto fail;
14884
14885         state = intel_create_plane_state(&primary->base);
14886         if (!state)
14887                 goto fail;
14888         primary->base.state = &state->base;
14889
14890         primary->can_scale = false;
14891         primary->max_downscale = 1;
14892         if (INTEL_INFO(dev)->gen >= 9) {
14893                 primary->can_scale = true;
14894                 state->scaler_id = -1;
14895         }
14896         primary->pipe = pipe;
14897         primary->plane = pipe;
14898         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14899         primary->check_plane = intel_check_primary_plane;
14900         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14901                 primary->plane = !pipe;
14902
14903         if (INTEL_INFO(dev)->gen >= 9) {
14904                 intel_primary_formats = skl_primary_formats;
14905                 num_formats = ARRAY_SIZE(skl_primary_formats);
14906
14907                 primary->update_plane = skylake_update_primary_plane;
14908                 primary->disable_plane = skylake_disable_primary_plane;
14909         } else if (HAS_PCH_SPLIT(dev)) {
14910                 intel_primary_formats = i965_primary_formats;
14911                 num_formats = ARRAY_SIZE(i965_primary_formats);
14912
14913                 primary->update_plane = ironlake_update_primary_plane;
14914                 primary->disable_plane = i9xx_disable_primary_plane;
14915         } else if (INTEL_INFO(dev)->gen >= 4) {
14916                 intel_primary_formats = i965_primary_formats;
14917                 num_formats = ARRAY_SIZE(i965_primary_formats);
14918
14919                 primary->update_plane = i9xx_update_primary_plane;
14920                 primary->disable_plane = i9xx_disable_primary_plane;
14921         } else {
14922                 intel_primary_formats = i8xx_primary_formats;
14923                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14924
14925                 primary->update_plane = i9xx_update_primary_plane;
14926                 primary->disable_plane = i9xx_disable_primary_plane;
14927         }
14928
14929         if (INTEL_INFO(dev)->gen >= 9)
14930                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14931                                                &intel_plane_funcs,
14932                                                intel_primary_formats, num_formats,
14933                                                DRM_PLANE_TYPE_PRIMARY,
14934                                                "plane 1%c", pipe_name(pipe));
14935         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14936                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14937                                                &intel_plane_funcs,
14938                                                intel_primary_formats, num_formats,
14939                                                DRM_PLANE_TYPE_PRIMARY,
14940                                                "primary %c", pipe_name(pipe));
14941         else
14942                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14943                                                &intel_plane_funcs,
14944                                                intel_primary_formats, num_formats,
14945                                                DRM_PLANE_TYPE_PRIMARY,
14946                                                "plane %c", plane_name(primary->plane));
14947         if (ret)
14948                 goto fail;
14949
14950         if (INTEL_INFO(dev)->gen >= 4)
14951                 intel_create_rotation_property(dev, primary);
14952
14953         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14954
14955         return &primary->base;
14956
14957 fail:
14958         kfree(state);
14959         kfree(primary);
14960
14961         return NULL;
14962 }
14963
14964 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14965 {
14966         if (!dev->mode_config.rotation_property) {
14967                 unsigned long flags = DRM_ROTATE_0 |
14968                         DRM_ROTATE_180;
14969
14970                 if (INTEL_INFO(dev)->gen >= 9)
14971                         flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14972
14973                 dev->mode_config.rotation_property =
14974                         drm_mode_create_rotation_property(dev, flags);
14975         }
14976         if (dev->mode_config.rotation_property)
14977                 drm_object_attach_property(&plane->base.base,
14978                                 dev->mode_config.rotation_property,
14979                                 plane->base.state->rotation);
14980 }
14981
14982 static int
14983 intel_check_cursor_plane(struct drm_plane *plane,
14984                          struct intel_crtc_state *crtc_state,
14985                          struct intel_plane_state *state)
14986 {
14987         struct drm_framebuffer *fb = state->base.fb;
14988         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14989         enum pipe pipe = to_intel_plane(plane)->pipe;
14990         unsigned stride;
14991         int ret;
14992
14993         ret = drm_plane_helper_check_state(&state->base,
14994                                            &state->clip,
14995                                            DRM_PLANE_HELPER_NO_SCALING,
14996                                            DRM_PLANE_HELPER_NO_SCALING,
14997                                            true, true);
14998         if (ret)
14999                 return ret;
15000
15001         /* if we want to turn off the cursor ignore width and height */
15002         if (!obj)
15003                 return 0;
15004
15005         /* Check for which cursor types we support */
15006         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15007                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15008                           state->base.crtc_w, state->base.crtc_h);
15009                 return -EINVAL;
15010         }
15011
15012         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15013         if (obj->base.size < stride * state->base.crtc_h) {
15014                 DRM_DEBUG_KMS("buffer is too small\n");
15015                 return -ENOMEM;
15016         }
15017
15018         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15019                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15020                 return -EINVAL;
15021         }
15022
15023         /*
15024          * There's something wrong with the cursor on CHV pipe C.
15025          * If it straddles the left edge of the screen then
15026          * moving it away from the edge or disabling it often
15027          * results in a pipe underrun, and often that can lead to
15028          * dead pipe (constant underrun reported, and it scans
15029          * out just a solid color). To recover from that, the
15030          * display power well must be turned off and on again.
15031          * Refuse the put the cursor into that compromised position.
15032          */
15033         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15034             state->base.visible && state->base.crtc_x < 0) {
15035                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15036                 return -EINVAL;
15037         }
15038
15039         return 0;
15040 }
15041
15042 static void
15043 intel_disable_cursor_plane(struct drm_plane *plane,
15044                            struct drm_crtc *crtc)
15045 {
15046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15047
15048         intel_crtc->cursor_addr = 0;
15049         intel_crtc_update_cursor(crtc, NULL);
15050 }
15051
15052 static void
15053 intel_update_cursor_plane(struct drm_plane *plane,
15054                           const struct intel_crtc_state *crtc_state,
15055                           const struct intel_plane_state *state)
15056 {
15057         struct drm_crtc *crtc = crtc_state->base.crtc;
15058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15059         struct drm_device *dev = plane->dev;
15060         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15061         uint32_t addr;
15062
15063         if (!obj)
15064                 addr = 0;
15065         else if (!INTEL_INFO(dev)->cursor_needs_physical)
15066                 addr = i915_gem_object_ggtt_offset(obj, NULL);
15067         else
15068                 addr = obj->phys_handle->busaddr;
15069
15070         intel_crtc->cursor_addr = addr;
15071         intel_crtc_update_cursor(crtc, state);
15072 }
15073
15074 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15075                                                    int pipe)
15076 {
15077         struct intel_plane *cursor = NULL;
15078         struct intel_plane_state *state = NULL;
15079         int ret;
15080
15081         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15082         if (!cursor)
15083                 goto fail;
15084
15085         state = intel_create_plane_state(&cursor->base);
15086         if (!state)
15087                 goto fail;
15088         cursor->base.state = &state->base;
15089
15090         cursor->can_scale = false;
15091         cursor->max_downscale = 1;
15092         cursor->pipe = pipe;
15093         cursor->plane = pipe;
15094         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15095         cursor->check_plane = intel_check_cursor_plane;
15096         cursor->update_plane = intel_update_cursor_plane;
15097         cursor->disable_plane = intel_disable_cursor_plane;
15098
15099         ret = drm_universal_plane_init(dev, &cursor->base, 0,
15100                                        &intel_plane_funcs,
15101                                        intel_cursor_formats,
15102                                        ARRAY_SIZE(intel_cursor_formats),
15103                                        DRM_PLANE_TYPE_CURSOR,
15104                                        "cursor %c", pipe_name(pipe));
15105         if (ret)
15106                 goto fail;
15107
15108         if (INTEL_INFO(dev)->gen >= 4) {
15109                 if (!dev->mode_config.rotation_property)
15110                         dev->mode_config.rotation_property =
15111                                 drm_mode_create_rotation_property(dev,
15112                                                         DRM_ROTATE_0 |
15113                                                         DRM_ROTATE_180);
15114                 if (dev->mode_config.rotation_property)
15115                         drm_object_attach_property(&cursor->base.base,
15116                                 dev->mode_config.rotation_property,
15117                                 state->base.rotation);
15118         }
15119
15120         if (INTEL_INFO(dev)->gen >=9)
15121                 state->scaler_id = -1;
15122
15123         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15124
15125         return &cursor->base;
15126
15127 fail:
15128         kfree(state);
15129         kfree(cursor);
15130
15131         return NULL;
15132 }
15133
15134 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15135         struct intel_crtc_state *crtc_state)
15136 {
15137         int i;
15138         struct intel_scaler *intel_scaler;
15139         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15140
15141         for (i = 0; i < intel_crtc->num_scalers; i++) {
15142                 intel_scaler = &scaler_state->scalers[i];
15143                 intel_scaler->in_use = 0;
15144                 intel_scaler->mode = PS_SCALER_MODE_DYN;
15145         }
15146
15147         scaler_state->scaler_id = -1;
15148 }
15149
15150 static void intel_crtc_init(struct drm_device *dev, int pipe)
15151 {
15152         struct drm_i915_private *dev_priv = to_i915(dev);
15153         struct intel_crtc *intel_crtc;
15154         struct intel_crtc_state *crtc_state = NULL;
15155         struct drm_plane *primary = NULL;
15156         struct drm_plane *cursor = NULL;
15157         int ret;
15158
15159         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15160         if (intel_crtc == NULL)
15161                 return;
15162
15163         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15164         if (!crtc_state)
15165                 goto fail;
15166         intel_crtc->config = crtc_state;
15167         intel_crtc->base.state = &crtc_state->base;
15168         crtc_state->base.crtc = &intel_crtc->base;
15169
15170         /* initialize shared scalers */
15171         if (INTEL_INFO(dev)->gen >= 9) {
15172                 if (pipe == PIPE_C)
15173                         intel_crtc->num_scalers = 1;
15174                 else
15175                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
15176
15177                 skl_init_scalers(dev, intel_crtc, crtc_state);
15178         }
15179
15180         primary = intel_primary_plane_create(dev, pipe);
15181         if (!primary)
15182                 goto fail;
15183
15184         cursor = intel_cursor_plane_create(dev, pipe);
15185         if (!cursor)
15186                 goto fail;
15187
15188         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15189                                         cursor, &intel_crtc_funcs,
15190                                         "pipe %c", pipe_name(pipe));
15191         if (ret)
15192                 goto fail;
15193
15194         /*
15195          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15196          * is hooked to pipe B. Hence we want plane A feeding pipe B.
15197          */
15198         intel_crtc->pipe = pipe;
15199         intel_crtc->plane = pipe;
15200         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15201                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15202                 intel_crtc->plane = !pipe;
15203         }
15204
15205         intel_crtc->cursor_base = ~0;
15206         intel_crtc->cursor_cntl = ~0;
15207         intel_crtc->cursor_size = ~0;
15208
15209         intel_crtc->wm.cxsr_allowed = true;
15210
15211         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15212                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15213         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15214         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15215
15216         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15217
15218         intel_color_init(&intel_crtc->base);
15219
15220         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15221         return;
15222
15223 fail:
15224         intel_plane_destroy(primary);
15225         intel_plane_destroy(cursor);
15226         kfree(crtc_state);
15227         kfree(intel_crtc);
15228 }
15229
15230 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15231 {
15232         struct drm_encoder *encoder = connector->base.encoder;
15233         struct drm_device *dev = connector->base.dev;
15234
15235         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15236
15237         if (!encoder || WARN_ON(!encoder->crtc))
15238                 return INVALID_PIPE;
15239
15240         return to_intel_crtc(encoder->crtc)->pipe;
15241 }
15242
15243 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15244                                 struct drm_file *file)
15245 {
15246         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15247         struct drm_crtc *drmmode_crtc;
15248         struct intel_crtc *crtc;
15249
15250         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15251         if (!drmmode_crtc)
15252                 return -ENOENT;
15253
15254         crtc = to_intel_crtc(drmmode_crtc);
15255         pipe_from_crtc_id->pipe = crtc->pipe;
15256
15257         return 0;
15258 }
15259
15260 static int intel_encoder_clones(struct intel_encoder *encoder)
15261 {
15262         struct drm_device *dev = encoder->base.dev;
15263         struct intel_encoder *source_encoder;
15264         int index_mask = 0;
15265         int entry = 0;
15266
15267         for_each_intel_encoder(dev, source_encoder) {
15268                 if (encoders_cloneable(encoder, source_encoder))
15269                         index_mask |= (1 << entry);
15270
15271                 entry++;
15272         }
15273
15274         return index_mask;
15275 }
15276
15277 static bool has_edp_a(struct drm_device *dev)
15278 {
15279         struct drm_i915_private *dev_priv = to_i915(dev);
15280
15281         if (!IS_MOBILE(dev))
15282                 return false;
15283
15284         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15285                 return false;
15286
15287         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15288                 return false;
15289
15290         return true;
15291 }
15292
15293 static bool intel_crt_present(struct drm_device *dev)
15294 {
15295         struct drm_i915_private *dev_priv = to_i915(dev);
15296
15297         if (INTEL_INFO(dev)->gen >= 9)
15298                 return false;
15299
15300         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15301                 return false;
15302
15303         if (IS_CHERRYVIEW(dev))
15304                 return false;
15305
15306         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15307                 return false;
15308
15309         /* DDI E can't be used if DDI A requires 4 lanes */
15310         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15311                 return false;
15312
15313         if (!dev_priv->vbt.int_crt_support)
15314                 return false;
15315
15316         return true;
15317 }
15318
15319 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15320 {
15321         int pps_num;
15322         int pps_idx;
15323
15324         if (HAS_DDI(dev_priv))
15325                 return;
15326         /*
15327          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15328          * everywhere where registers can be write protected.
15329          */
15330         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15331                 pps_num = 2;
15332         else
15333                 pps_num = 1;
15334
15335         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15336                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15337
15338                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15339                 I915_WRITE(PP_CONTROL(pps_idx), val);
15340         }
15341 }
15342
15343 static void intel_pps_init(struct drm_i915_private *dev_priv)
15344 {
15345         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15346                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15347         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15348                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15349         else
15350                 dev_priv->pps_mmio_base = PPS_BASE;
15351
15352         intel_pps_unlock_regs_wa(dev_priv);
15353 }
15354
15355 static void intel_setup_outputs(struct drm_device *dev)
15356 {
15357         struct drm_i915_private *dev_priv = to_i915(dev);
15358         struct intel_encoder *encoder;
15359         bool dpd_is_edp = false;
15360
15361         intel_pps_init(dev_priv);
15362
15363         /*
15364          * intel_edp_init_connector() depends on this completing first, to
15365          * prevent the registeration of both eDP and LVDS and the incorrect
15366          * sharing of the PPS.
15367          */
15368         intel_lvds_init(dev);
15369
15370         if (intel_crt_present(dev))
15371                 intel_crt_init(dev);
15372
15373         if (IS_BROXTON(dev)) {
15374                 /*
15375                  * FIXME: Broxton doesn't support port detection via the
15376                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15377                  * detect the ports.
15378                  */
15379                 intel_ddi_init(dev, PORT_A);
15380                 intel_ddi_init(dev, PORT_B);
15381                 intel_ddi_init(dev, PORT_C);
15382
15383                 intel_dsi_init(dev);
15384         } else if (HAS_DDI(dev)) {
15385                 int found;
15386
15387                 /*
15388                  * Haswell uses DDI functions to detect digital outputs.
15389                  * On SKL pre-D0 the strap isn't connected, so we assume
15390                  * it's there.
15391                  */
15392                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15393                 /* WaIgnoreDDIAStrap: skl */
15394                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15395                         intel_ddi_init(dev, PORT_A);
15396
15397                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15398                  * register */
15399                 found = I915_READ(SFUSE_STRAP);
15400
15401                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15402                         intel_ddi_init(dev, PORT_B);
15403                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15404                         intel_ddi_init(dev, PORT_C);
15405                 if (found & SFUSE_STRAP_DDID_DETECTED)
15406                         intel_ddi_init(dev, PORT_D);
15407                 /*
15408                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15409                  */
15410                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15411                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15412                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15413                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15414                         intel_ddi_init(dev, PORT_E);
15415
15416         } else if (HAS_PCH_SPLIT(dev)) {
15417                 int found;
15418                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15419
15420                 if (has_edp_a(dev))
15421                         intel_dp_init(dev, DP_A, PORT_A);
15422
15423                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15424                         /* PCH SDVOB multiplex with HDMIB */
15425                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15426                         if (!found)
15427                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15428                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15429                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15430                 }
15431
15432                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15433                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15434
15435                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15436                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15437
15438                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15439                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15440
15441                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15442                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15443         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15444                 bool has_edp, has_port;
15445
15446                 /*
15447                  * The DP_DETECTED bit is the latched state of the DDC
15448                  * SDA pin at boot. However since eDP doesn't require DDC
15449                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15450                  * eDP ports may have been muxed to an alternate function.
15451                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15452                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15453                  * detect eDP ports.
15454                  *
15455                  * Sadly the straps seem to be missing sometimes even for HDMI
15456                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15457                  * and VBT for the presence of the port. Additionally we can't
15458                  * trust the port type the VBT declares as we've seen at least
15459                  * HDMI ports that the VBT claim are DP or eDP.
15460                  */
15461                 has_edp = intel_dp_is_edp(dev, PORT_B);
15462                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15463                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15464                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15465                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15466                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15467
15468                 has_edp = intel_dp_is_edp(dev, PORT_C);
15469                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15470                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15471                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15472                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15473                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15474
15475                 if (IS_CHERRYVIEW(dev)) {
15476                         /*
15477                          * eDP not supported on port D,
15478                          * so no need to worry about it
15479                          */
15480                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15481                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15482                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15483                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15484                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15485                 }
15486
15487                 intel_dsi_init(dev);
15488         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15489                 bool found = false;
15490
15491                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15492                         DRM_DEBUG_KMS("probing SDVOB\n");
15493                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15494                         if (!found && IS_G4X(dev)) {
15495                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15496                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15497                         }
15498
15499                         if (!found && IS_G4X(dev))
15500                                 intel_dp_init(dev, DP_B, PORT_B);
15501                 }
15502
15503                 /* Before G4X SDVOC doesn't have its own detect register */
15504
15505                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15506                         DRM_DEBUG_KMS("probing SDVOC\n");
15507                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15508                 }
15509
15510                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15511
15512                         if (IS_G4X(dev)) {
15513                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15514                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15515                         }
15516                         if (IS_G4X(dev))
15517                                 intel_dp_init(dev, DP_C, PORT_C);
15518                 }
15519
15520                 if (IS_G4X(dev) &&
15521                     (I915_READ(DP_D) & DP_DETECTED))
15522                         intel_dp_init(dev, DP_D, PORT_D);
15523         } else if (IS_GEN2(dev))
15524                 intel_dvo_init(dev);
15525
15526         if (SUPPORTS_TV(dev))
15527                 intel_tv_init(dev);
15528
15529         intel_psr_init(dev);
15530
15531         for_each_intel_encoder(dev, encoder) {
15532                 encoder->base.possible_crtcs = encoder->crtc_mask;
15533                 encoder->base.possible_clones =
15534                         intel_encoder_clones(encoder);
15535         }
15536
15537         intel_init_pch_refclk(dev);
15538
15539         drm_helper_move_panel_connectors_to_head(dev);
15540 }
15541
15542 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15543 {
15544         struct drm_device *dev = fb->dev;
15545         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15546
15547         drm_framebuffer_cleanup(fb);
15548         mutex_lock(&dev->struct_mutex);
15549         WARN_ON(!intel_fb->obj->framebuffer_references--);
15550         i915_gem_object_put(intel_fb->obj);
15551         mutex_unlock(&dev->struct_mutex);
15552         kfree(intel_fb);
15553 }
15554
15555 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15556                                                 struct drm_file *file,
15557                                                 unsigned int *handle)
15558 {
15559         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15560         struct drm_i915_gem_object *obj = intel_fb->obj;
15561
15562         if (obj->userptr.mm) {
15563                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15564                 return -EINVAL;
15565         }
15566
15567         return drm_gem_handle_create(file, &obj->base, handle);
15568 }
15569
15570 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15571                                         struct drm_file *file,
15572                                         unsigned flags, unsigned color,
15573                                         struct drm_clip_rect *clips,
15574                                         unsigned num_clips)
15575 {
15576         struct drm_device *dev = fb->dev;
15577         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15578         struct drm_i915_gem_object *obj = intel_fb->obj;
15579
15580         mutex_lock(&dev->struct_mutex);
15581         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15582         mutex_unlock(&dev->struct_mutex);
15583
15584         return 0;
15585 }
15586
15587 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15588         .destroy = intel_user_framebuffer_destroy,
15589         .create_handle = intel_user_framebuffer_create_handle,
15590         .dirty = intel_user_framebuffer_dirty,
15591 };
15592
15593 static
15594 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15595                          uint32_t pixel_format)
15596 {
15597         u32 gen = INTEL_INFO(dev)->gen;
15598
15599         if (gen >= 9) {
15600                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15601
15602                 /* "The stride in bytes must not exceed the of the size of 8K
15603                  *  pixels and 32K bytes."
15604                  */
15605                 return min(8192 * cpp, 32768);
15606         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15607                 return 32*1024;
15608         } else if (gen >= 4) {
15609                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15610                         return 16*1024;
15611                 else
15612                         return 32*1024;
15613         } else if (gen >= 3) {
15614                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15615                         return 8*1024;
15616                 else
15617                         return 16*1024;
15618         } else {
15619                 /* XXX DSPC is limited to 4k tiled */
15620                 return 8*1024;
15621         }
15622 }
15623
15624 static int intel_framebuffer_init(struct drm_device *dev,
15625                                   struct intel_framebuffer *intel_fb,
15626                                   struct drm_mode_fb_cmd2 *mode_cmd,
15627                                   struct drm_i915_gem_object *obj)
15628 {
15629         struct drm_i915_private *dev_priv = to_i915(dev);
15630         unsigned int tiling = i915_gem_object_get_tiling(obj);
15631         int ret;
15632         u32 pitch_limit, stride_alignment;
15633
15634         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15635
15636         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15637                 /*
15638                  * If there's a fence, enforce that
15639                  * the fb modifier and tiling mode match.
15640                  */
15641                 if (tiling != I915_TILING_NONE &&
15642                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15643                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15644                         return -EINVAL;
15645                 }
15646         } else {
15647                 if (tiling == I915_TILING_X) {
15648                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15649                 } else if (tiling == I915_TILING_Y) {
15650                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15651                         return -EINVAL;
15652                 }
15653         }
15654
15655         /* Passed in modifier sanity checking. */
15656         switch (mode_cmd->modifier[0]) {
15657         case I915_FORMAT_MOD_Y_TILED:
15658         case I915_FORMAT_MOD_Yf_TILED:
15659                 if (INTEL_INFO(dev)->gen < 9) {
15660                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15661                                   mode_cmd->modifier[0]);
15662                         return -EINVAL;
15663                 }
15664         case DRM_FORMAT_MOD_NONE:
15665         case I915_FORMAT_MOD_X_TILED:
15666                 break;
15667         default:
15668                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15669                           mode_cmd->modifier[0]);
15670                 return -EINVAL;
15671         }
15672
15673         /*
15674          * gen2/3 display engine uses the fence if present,
15675          * so the tiling mode must match the fb modifier exactly.
15676          */
15677         if (INTEL_INFO(dev_priv)->gen < 4 &&
15678             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15679                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15680                 return -EINVAL;
15681         }
15682
15683         stride_alignment = intel_fb_stride_alignment(dev_priv,
15684                                                      mode_cmd->modifier[0],
15685                                                      mode_cmd->pixel_format);
15686         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15687                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15688                           mode_cmd->pitches[0], stride_alignment);
15689                 return -EINVAL;
15690         }
15691
15692         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15693                                            mode_cmd->pixel_format);
15694         if (mode_cmd->pitches[0] > pitch_limit) {
15695                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15696                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15697                           "tiled" : "linear",
15698                           mode_cmd->pitches[0], pitch_limit);
15699                 return -EINVAL;
15700         }
15701
15702         /*
15703          * If there's a fence, enforce that
15704          * the fb pitch and fence stride match.
15705          */
15706         if (tiling != I915_TILING_NONE &&
15707             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15708                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15709                           mode_cmd->pitches[0],
15710                           i915_gem_object_get_stride(obj));
15711                 return -EINVAL;
15712         }
15713
15714         /* Reject formats not supported by any plane early. */
15715         switch (mode_cmd->pixel_format) {
15716         case DRM_FORMAT_C8:
15717         case DRM_FORMAT_RGB565:
15718         case DRM_FORMAT_XRGB8888:
15719         case DRM_FORMAT_ARGB8888:
15720                 break;
15721         case DRM_FORMAT_XRGB1555:
15722                 if (INTEL_INFO(dev)->gen > 3) {
15723                         DRM_DEBUG("unsupported pixel format: %s\n",
15724                                   drm_get_format_name(mode_cmd->pixel_format));
15725                         return -EINVAL;
15726                 }
15727                 break;
15728         case DRM_FORMAT_ABGR8888:
15729                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15730                     INTEL_INFO(dev)->gen < 9) {
15731                         DRM_DEBUG("unsupported pixel format: %s\n",
15732                                   drm_get_format_name(mode_cmd->pixel_format));
15733                         return -EINVAL;
15734                 }
15735                 break;
15736         case DRM_FORMAT_XBGR8888:
15737         case DRM_FORMAT_XRGB2101010:
15738         case DRM_FORMAT_XBGR2101010:
15739                 if (INTEL_INFO(dev)->gen < 4) {
15740                         DRM_DEBUG("unsupported pixel format: %s\n",
15741                                   drm_get_format_name(mode_cmd->pixel_format));
15742                         return -EINVAL;
15743                 }
15744                 break;
15745         case DRM_FORMAT_ABGR2101010:
15746                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15747                         DRM_DEBUG("unsupported pixel format: %s\n",
15748                                   drm_get_format_name(mode_cmd->pixel_format));
15749                         return -EINVAL;
15750                 }
15751                 break;
15752         case DRM_FORMAT_YUYV:
15753         case DRM_FORMAT_UYVY:
15754         case DRM_FORMAT_YVYU:
15755         case DRM_FORMAT_VYUY:
15756                 if (INTEL_INFO(dev)->gen < 5) {
15757                         DRM_DEBUG("unsupported pixel format: %s\n",
15758                                   drm_get_format_name(mode_cmd->pixel_format));
15759                         return -EINVAL;
15760                 }
15761                 break;
15762         default:
15763                 DRM_DEBUG("unsupported pixel format: %s\n",
15764                           drm_get_format_name(mode_cmd->pixel_format));
15765                 return -EINVAL;
15766         }
15767
15768         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15769         if (mode_cmd->offsets[0] != 0)
15770                 return -EINVAL;
15771
15772         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15773         intel_fb->obj = obj;
15774
15775         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15776         if (ret)
15777                 return ret;
15778
15779         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15780         if (ret) {
15781                 DRM_ERROR("framebuffer init failed %d\n", ret);
15782                 return ret;
15783         }
15784
15785         intel_fb->obj->framebuffer_references++;
15786
15787         return 0;
15788 }
15789
15790 static struct drm_framebuffer *
15791 intel_user_framebuffer_create(struct drm_device *dev,
15792                               struct drm_file *filp,
15793                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15794 {
15795         struct drm_framebuffer *fb;
15796         struct drm_i915_gem_object *obj;
15797         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15798
15799         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15800         if (!obj)
15801                 return ERR_PTR(-ENOENT);
15802
15803         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15804         if (IS_ERR(fb))
15805                 i915_gem_object_put_unlocked(obj);
15806
15807         return fb;
15808 }
15809
15810 #ifndef CONFIG_DRM_FBDEV_EMULATION
15811 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15812 {
15813 }
15814 #endif
15815
15816 static const struct drm_mode_config_funcs intel_mode_funcs = {
15817         .fb_create = intel_user_framebuffer_create,
15818         .output_poll_changed = intel_fbdev_output_poll_changed,
15819         .atomic_check = intel_atomic_check,
15820         .atomic_commit = intel_atomic_commit,
15821         .atomic_state_alloc = intel_atomic_state_alloc,
15822         .atomic_state_clear = intel_atomic_state_clear,
15823 };
15824
15825 /**
15826  * intel_init_display_hooks - initialize the display modesetting hooks
15827  * @dev_priv: device private
15828  */
15829 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15830 {
15831         if (INTEL_INFO(dev_priv)->gen >= 9) {
15832                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15833                 dev_priv->display.get_initial_plane_config =
15834                         skylake_get_initial_plane_config;
15835                 dev_priv->display.crtc_compute_clock =
15836                         haswell_crtc_compute_clock;
15837                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15838                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15839         } else if (HAS_DDI(dev_priv)) {
15840                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15841                 dev_priv->display.get_initial_plane_config =
15842                         ironlake_get_initial_plane_config;
15843                 dev_priv->display.crtc_compute_clock =
15844                         haswell_crtc_compute_clock;
15845                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15846                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15847         } else if (HAS_PCH_SPLIT(dev_priv)) {
15848                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15849                 dev_priv->display.get_initial_plane_config =
15850                         ironlake_get_initial_plane_config;
15851                 dev_priv->display.crtc_compute_clock =
15852                         ironlake_crtc_compute_clock;
15853                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15854                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15855         } else if (IS_CHERRYVIEW(dev_priv)) {
15856                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15857                 dev_priv->display.get_initial_plane_config =
15858                         i9xx_get_initial_plane_config;
15859                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15860                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15861                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15862         } else if (IS_VALLEYVIEW(dev_priv)) {
15863                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15864                 dev_priv->display.get_initial_plane_config =
15865                         i9xx_get_initial_plane_config;
15866                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15867                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15868                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15869         } else if (IS_G4X(dev_priv)) {
15870                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15871                 dev_priv->display.get_initial_plane_config =
15872                         i9xx_get_initial_plane_config;
15873                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15874                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15875                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15876         } else if (IS_PINEVIEW(dev_priv)) {
15877                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15878                 dev_priv->display.get_initial_plane_config =
15879                         i9xx_get_initial_plane_config;
15880                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15881                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15882                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15883         } else if (!IS_GEN2(dev_priv)) {
15884                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15885                 dev_priv->display.get_initial_plane_config =
15886                         i9xx_get_initial_plane_config;
15887                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15888                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15889                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15890         } else {
15891                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15892                 dev_priv->display.get_initial_plane_config =
15893                         i9xx_get_initial_plane_config;
15894                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15895                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15896                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15897         }
15898
15899         /* Returns the core display clock speed */
15900         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15901                 dev_priv->display.get_display_clock_speed =
15902                         skylake_get_display_clock_speed;
15903         else if (IS_BROXTON(dev_priv))
15904                 dev_priv->display.get_display_clock_speed =
15905                         broxton_get_display_clock_speed;
15906         else if (IS_BROADWELL(dev_priv))
15907                 dev_priv->display.get_display_clock_speed =
15908                         broadwell_get_display_clock_speed;
15909         else if (IS_HASWELL(dev_priv))
15910                 dev_priv->display.get_display_clock_speed =
15911                         haswell_get_display_clock_speed;
15912         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15913                 dev_priv->display.get_display_clock_speed =
15914                         valleyview_get_display_clock_speed;
15915         else if (IS_GEN5(dev_priv))
15916                 dev_priv->display.get_display_clock_speed =
15917                         ilk_get_display_clock_speed;
15918         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15919                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15920                 dev_priv->display.get_display_clock_speed =
15921                         i945_get_display_clock_speed;
15922         else if (IS_GM45(dev_priv))
15923                 dev_priv->display.get_display_clock_speed =
15924                         gm45_get_display_clock_speed;
15925         else if (IS_CRESTLINE(dev_priv))
15926                 dev_priv->display.get_display_clock_speed =
15927                         i965gm_get_display_clock_speed;
15928         else if (IS_PINEVIEW(dev_priv))
15929                 dev_priv->display.get_display_clock_speed =
15930                         pnv_get_display_clock_speed;
15931         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15932                 dev_priv->display.get_display_clock_speed =
15933                         g33_get_display_clock_speed;
15934         else if (IS_I915G(dev_priv))
15935                 dev_priv->display.get_display_clock_speed =
15936                         i915_get_display_clock_speed;
15937         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15938                 dev_priv->display.get_display_clock_speed =
15939                         i9xx_misc_get_display_clock_speed;
15940         else if (IS_I915GM(dev_priv))
15941                 dev_priv->display.get_display_clock_speed =
15942                         i915gm_get_display_clock_speed;
15943         else if (IS_I865G(dev_priv))
15944                 dev_priv->display.get_display_clock_speed =
15945                         i865_get_display_clock_speed;
15946         else if (IS_I85X(dev_priv))
15947                 dev_priv->display.get_display_clock_speed =
15948                         i85x_get_display_clock_speed;
15949         else { /* 830 */
15950                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15951                 dev_priv->display.get_display_clock_speed =
15952                         i830_get_display_clock_speed;
15953         }
15954
15955         if (IS_GEN5(dev_priv)) {
15956                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15957         } else if (IS_GEN6(dev_priv)) {
15958                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15959         } else if (IS_IVYBRIDGE(dev_priv)) {
15960                 /* FIXME: detect B0+ stepping and use auto training */
15961                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15962         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15963                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15964         }
15965
15966         if (IS_BROADWELL(dev_priv)) {
15967                 dev_priv->display.modeset_commit_cdclk =
15968                         broadwell_modeset_commit_cdclk;
15969                 dev_priv->display.modeset_calc_cdclk =
15970                         broadwell_modeset_calc_cdclk;
15971         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15972                 dev_priv->display.modeset_commit_cdclk =
15973                         valleyview_modeset_commit_cdclk;
15974                 dev_priv->display.modeset_calc_cdclk =
15975                         valleyview_modeset_calc_cdclk;
15976         } else if (IS_BROXTON(dev_priv)) {
15977                 dev_priv->display.modeset_commit_cdclk =
15978                         bxt_modeset_commit_cdclk;
15979                 dev_priv->display.modeset_calc_cdclk =
15980                         bxt_modeset_calc_cdclk;
15981         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15982                 dev_priv->display.modeset_commit_cdclk =
15983                         skl_modeset_commit_cdclk;
15984                 dev_priv->display.modeset_calc_cdclk =
15985                         skl_modeset_calc_cdclk;
15986         }
15987
15988         if (dev_priv->info.gen >= 9)
15989                 dev_priv->display.update_crtcs = skl_update_crtcs;
15990         else
15991                 dev_priv->display.update_crtcs = intel_update_crtcs;
15992
15993         switch (INTEL_INFO(dev_priv)->gen) {
15994         case 2:
15995                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15996                 break;
15997
15998         case 3:
15999                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16000                 break;
16001
16002         case 4:
16003         case 5:
16004                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16005                 break;
16006
16007         case 6:
16008                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16009                 break;
16010         case 7:
16011         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16012                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16013                 break;
16014         case 9:
16015                 /* Drop through - unsupported since execlist only. */
16016         default:
16017                 /* Default just returns -ENODEV to indicate unsupported */
16018                 dev_priv->display.queue_flip = intel_default_queue_flip;
16019         }
16020 }
16021
16022 /*
16023  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16024  * resume, or other times.  This quirk makes sure that's the case for
16025  * affected systems.
16026  */
16027 static void quirk_pipea_force(struct drm_device *dev)
16028 {
16029         struct drm_i915_private *dev_priv = to_i915(dev);
16030
16031         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16032         DRM_INFO("applying pipe a force quirk\n");
16033 }
16034
16035 static void quirk_pipeb_force(struct drm_device *dev)
16036 {
16037         struct drm_i915_private *dev_priv = to_i915(dev);
16038
16039         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16040         DRM_INFO("applying pipe b force quirk\n");
16041 }
16042
16043 /*
16044  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16045  */
16046 static void quirk_ssc_force_disable(struct drm_device *dev)
16047 {
16048         struct drm_i915_private *dev_priv = to_i915(dev);
16049         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16050         DRM_INFO("applying lvds SSC disable quirk\n");
16051 }
16052
16053 /*
16054  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16055  * brightness value
16056  */
16057 static void quirk_invert_brightness(struct drm_device *dev)
16058 {
16059         struct drm_i915_private *dev_priv = to_i915(dev);
16060         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16061         DRM_INFO("applying inverted panel brightness quirk\n");
16062 }
16063
16064 /* Some VBT's incorrectly indicate no backlight is present */
16065 static void quirk_backlight_present(struct drm_device *dev)
16066 {
16067         struct drm_i915_private *dev_priv = to_i915(dev);
16068         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16069         DRM_INFO("applying backlight present quirk\n");
16070 }
16071
16072 struct intel_quirk {
16073         int device;
16074         int subsystem_vendor;
16075         int subsystem_device;
16076         void (*hook)(struct drm_device *dev);
16077 };
16078
16079 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16080 struct intel_dmi_quirk {
16081         void (*hook)(struct drm_device *dev);
16082         const struct dmi_system_id (*dmi_id_list)[];
16083 };
16084
16085 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16086 {
16087         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16088         return 1;
16089 }
16090
16091 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16092         {
16093                 .dmi_id_list = &(const struct dmi_system_id[]) {
16094                         {
16095                                 .callback = intel_dmi_reverse_brightness,
16096                                 .ident = "NCR Corporation",
16097                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16098                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
16099                                 },
16100                         },
16101                         { }  /* terminating entry */
16102                 },
16103                 .hook = quirk_invert_brightness,
16104         },
16105 };
16106
16107 static struct intel_quirk intel_quirks[] = {
16108         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16109         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16110
16111         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16112         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16113
16114         /* 830 needs to leave pipe A & dpll A up */
16115         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16116
16117         /* 830 needs to leave pipe B & dpll B up */
16118         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16119
16120         /* Lenovo U160 cannot use SSC on LVDS */
16121         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16122
16123         /* Sony Vaio Y cannot use SSC on LVDS */
16124         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16125
16126         /* Acer Aspire 5734Z must invert backlight brightness */
16127         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16128
16129         /* Acer/eMachines G725 */
16130         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16131
16132         /* Acer/eMachines e725 */
16133         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16134
16135         /* Acer/Packard Bell NCL20 */
16136         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16137
16138         /* Acer Aspire 4736Z */
16139         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16140
16141         /* Acer Aspire 5336 */
16142         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16143
16144         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16145         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16146
16147         /* Acer C720 Chromebook (Core i3 4005U) */
16148         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16149
16150         /* Apple Macbook 2,1 (Core 2 T7400) */
16151         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16152
16153         /* Apple Macbook 4,1 */
16154         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16155
16156         /* Toshiba CB35 Chromebook (Celeron 2955U) */
16157         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16158
16159         /* HP Chromebook 14 (Celeron 2955U) */
16160         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16161
16162         /* Dell Chromebook 11 */
16163         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16164
16165         /* Dell Chromebook 11 (2015 version) */
16166         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16167 };
16168
16169 static void intel_init_quirks(struct drm_device *dev)
16170 {
16171         struct pci_dev *d = dev->pdev;
16172         int i;
16173
16174         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16175                 struct intel_quirk *q = &intel_quirks[i];
16176
16177                 if (d->device == q->device &&
16178                     (d->subsystem_vendor == q->subsystem_vendor ||
16179                      q->subsystem_vendor == PCI_ANY_ID) &&
16180                     (d->subsystem_device == q->subsystem_device ||
16181                      q->subsystem_device == PCI_ANY_ID))
16182                         q->hook(dev);
16183         }
16184         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16185                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16186                         intel_dmi_quirks[i].hook(dev);
16187         }
16188 }
16189
16190 /* Disable the VGA plane that we never use */
16191 static void i915_disable_vga(struct drm_device *dev)
16192 {
16193         struct drm_i915_private *dev_priv = to_i915(dev);
16194         struct pci_dev *pdev = dev_priv->drm.pdev;
16195         u8 sr1;
16196         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16197
16198         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16199         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16200         outb(SR01, VGA_SR_INDEX);
16201         sr1 = inb(VGA_SR_DATA);
16202         outb(sr1 | 1<<5, VGA_SR_DATA);
16203         vga_put(pdev, VGA_RSRC_LEGACY_IO);
16204         udelay(300);
16205
16206         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16207         POSTING_READ(vga_reg);
16208 }
16209
16210 void intel_modeset_init_hw(struct drm_device *dev)
16211 {
16212         struct drm_i915_private *dev_priv = to_i915(dev);
16213
16214         intel_update_cdclk(dev);
16215
16216         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16217
16218         intel_init_clock_gating(dev);
16219 }
16220
16221 /*
16222  * Calculate what we think the watermarks should be for the state we've read
16223  * out of the hardware and then immediately program those watermarks so that
16224  * we ensure the hardware settings match our internal state.
16225  *
16226  * We can calculate what we think WM's should be by creating a duplicate of the
16227  * current state (which was constructed during hardware readout) and running it
16228  * through the atomic check code to calculate new watermark values in the
16229  * state object.
16230  */
16231 static void sanitize_watermarks(struct drm_device *dev)
16232 {
16233         struct drm_i915_private *dev_priv = to_i915(dev);
16234         struct drm_atomic_state *state;
16235         struct drm_crtc *crtc;
16236         struct drm_crtc_state *cstate;
16237         struct drm_modeset_acquire_ctx ctx;
16238         int ret;
16239         int i;
16240
16241         /* Only supported on platforms that use atomic watermark design */
16242         if (!dev_priv->display.optimize_watermarks)
16243                 return;
16244
16245         /*
16246          * We need to hold connection_mutex before calling duplicate_state so
16247          * that the connector loop is protected.
16248          */
16249         drm_modeset_acquire_init(&ctx, 0);
16250 retry:
16251         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16252         if (ret == -EDEADLK) {
16253                 drm_modeset_backoff(&ctx);
16254                 goto retry;
16255         } else if (WARN_ON(ret)) {
16256                 goto fail;
16257         }
16258
16259         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16260         if (WARN_ON(IS_ERR(state)))
16261                 goto fail;
16262
16263         /*
16264          * Hardware readout is the only time we don't want to calculate
16265          * intermediate watermarks (since we don't trust the current
16266          * watermarks).
16267          */
16268         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16269
16270         ret = intel_atomic_check(dev, state);
16271         if (ret) {
16272                 /*
16273                  * If we fail here, it means that the hardware appears to be
16274                  * programmed in a way that shouldn't be possible, given our
16275                  * understanding of watermark requirements.  This might mean a
16276                  * mistake in the hardware readout code or a mistake in the
16277                  * watermark calculations for a given platform.  Raise a WARN
16278                  * so that this is noticeable.
16279                  *
16280                  * If this actually happens, we'll have to just leave the
16281                  * BIOS-programmed watermarks untouched and hope for the best.
16282                  */
16283                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16284                 goto fail;
16285         }
16286
16287         /* Write calculated watermark values back */
16288         for_each_crtc_in_state(state, crtc, cstate, i) {
16289                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16290
16291                 cs->wm.need_postvbl_update = true;
16292                 dev_priv->display.optimize_watermarks(cs);
16293         }
16294
16295         drm_atomic_state_free(state);
16296 fail:
16297         drm_modeset_drop_locks(&ctx);
16298         drm_modeset_acquire_fini(&ctx);
16299 }
16300
16301 void intel_modeset_init(struct drm_device *dev)
16302 {
16303         struct drm_i915_private *dev_priv = to_i915(dev);
16304         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16305         int sprite, ret;
16306         enum pipe pipe;
16307         struct intel_crtc *crtc;
16308
16309         drm_mode_config_init(dev);
16310
16311         dev->mode_config.min_width = 0;
16312         dev->mode_config.min_height = 0;
16313
16314         dev->mode_config.preferred_depth = 24;
16315         dev->mode_config.prefer_shadow = 1;
16316
16317         dev->mode_config.allow_fb_modifiers = true;
16318
16319         dev->mode_config.funcs = &intel_mode_funcs;
16320
16321         intel_init_quirks(dev);
16322
16323         intel_init_pm(dev);
16324
16325         if (INTEL_INFO(dev)->num_pipes == 0)
16326                 return;
16327
16328         /*
16329          * There may be no VBT; and if the BIOS enabled SSC we can
16330          * just keep using it to avoid unnecessary flicker.  Whereas if the
16331          * BIOS isn't using it, don't assume it will work even if the VBT
16332          * indicates as much.
16333          */
16334         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16335                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16336                                             DREF_SSC1_ENABLE);
16337
16338                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16339                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16340                                      bios_lvds_use_ssc ? "en" : "dis",
16341                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16342                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16343                 }
16344         }
16345
16346         if (IS_GEN2(dev)) {
16347                 dev->mode_config.max_width = 2048;
16348                 dev->mode_config.max_height = 2048;
16349         } else if (IS_GEN3(dev)) {
16350                 dev->mode_config.max_width = 4096;
16351                 dev->mode_config.max_height = 4096;
16352         } else {
16353                 dev->mode_config.max_width = 8192;
16354                 dev->mode_config.max_height = 8192;
16355         }
16356
16357         if (IS_845G(dev) || IS_I865G(dev)) {
16358                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16359                 dev->mode_config.cursor_height = 1023;
16360         } else if (IS_GEN2(dev)) {
16361                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16362                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16363         } else {
16364                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16365                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16366         }
16367
16368         dev->mode_config.fb_base = ggtt->mappable_base;
16369
16370         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16371                       INTEL_INFO(dev)->num_pipes,
16372                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16373
16374         for_each_pipe(dev_priv, pipe) {
16375                 intel_crtc_init(dev, pipe);
16376                 for_each_sprite(dev_priv, pipe, sprite) {
16377                         ret = intel_plane_init(dev, pipe, sprite);
16378                         if (ret)
16379                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16380                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16381                 }
16382         }
16383
16384         intel_update_czclk(dev_priv);
16385         intel_update_cdclk(dev);
16386
16387         intel_shared_dpll_init(dev);
16388
16389         if (dev_priv->max_cdclk_freq == 0)
16390                 intel_update_max_cdclk(dev);
16391
16392         /* Just disable it once at startup */
16393         i915_disable_vga(dev);
16394         intel_setup_outputs(dev);
16395
16396         drm_modeset_lock_all(dev);
16397         intel_modeset_setup_hw_state(dev);
16398         drm_modeset_unlock_all(dev);
16399
16400         for_each_intel_crtc(dev, crtc) {
16401                 struct intel_initial_plane_config plane_config = {};
16402
16403                 if (!crtc->active)
16404                         continue;
16405
16406                 /*
16407                  * Note that reserving the BIOS fb up front prevents us
16408                  * from stuffing other stolen allocations like the ring
16409                  * on top.  This prevents some ugliness at boot time, and
16410                  * can even allow for smooth boot transitions if the BIOS
16411                  * fb is large enough for the active pipe configuration.
16412                  */
16413                 dev_priv->display.get_initial_plane_config(crtc,
16414                                                            &plane_config);
16415
16416                 /*
16417                  * If the fb is shared between multiple heads, we'll
16418                  * just get the first one.
16419                  */
16420                 intel_find_initial_plane_obj(crtc, &plane_config);
16421         }
16422
16423         /*
16424          * Make sure hardware watermarks really match the state we read out.
16425          * Note that we need to do this after reconstructing the BIOS fb's
16426          * since the watermark calculation done here will use pstate->fb.
16427          */
16428         sanitize_watermarks(dev);
16429 }
16430
16431 static void intel_enable_pipe_a(struct drm_device *dev)
16432 {
16433         struct intel_connector *connector;
16434         struct drm_connector *crt = NULL;
16435         struct intel_load_detect_pipe load_detect_temp;
16436         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16437
16438         /* We can't just switch on the pipe A, we need to set things up with a
16439          * proper mode and output configuration. As a gross hack, enable pipe A
16440          * by enabling the load detect pipe once. */
16441         for_each_intel_connector(dev, connector) {
16442                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16443                         crt = &connector->base;
16444                         break;
16445                 }
16446         }
16447
16448         if (!crt)
16449                 return;
16450
16451         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16452                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16453 }
16454
16455 static bool
16456 intel_check_plane_mapping(struct intel_crtc *crtc)
16457 {
16458         struct drm_device *dev = crtc->base.dev;
16459         struct drm_i915_private *dev_priv = to_i915(dev);
16460         u32 val;
16461
16462         if (INTEL_INFO(dev)->num_pipes == 1)
16463                 return true;
16464
16465         val = I915_READ(DSPCNTR(!crtc->plane));
16466
16467         if ((val & DISPLAY_PLANE_ENABLE) &&
16468             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16469                 return false;
16470
16471         return true;
16472 }
16473
16474 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16475 {
16476         struct drm_device *dev = crtc->base.dev;
16477         struct intel_encoder *encoder;
16478
16479         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16480                 return true;
16481
16482         return false;
16483 }
16484
16485 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16486 {
16487         struct drm_device *dev = encoder->base.dev;
16488         struct intel_connector *connector;
16489
16490         for_each_connector_on_encoder(dev, &encoder->base, connector)
16491                 return connector;
16492
16493         return NULL;
16494 }
16495
16496 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16497                               enum transcoder pch_transcoder)
16498 {
16499         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16500                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16501 }
16502
16503 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16504 {
16505         struct drm_device *dev = crtc->base.dev;
16506         struct drm_i915_private *dev_priv = to_i915(dev);
16507         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16508
16509         /* Clear any frame start delays used for debugging left by the BIOS */
16510         if (!transcoder_is_dsi(cpu_transcoder)) {
16511                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16512
16513                 I915_WRITE(reg,
16514                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16515         }
16516
16517         /* restore vblank interrupts to correct state */
16518         drm_crtc_vblank_reset(&crtc->base);
16519         if (crtc->active) {
16520                 struct intel_plane *plane;
16521
16522                 drm_crtc_vblank_on(&crtc->base);
16523
16524                 /* Disable everything but the primary plane */
16525                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16526                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16527                                 continue;
16528
16529                         plane->disable_plane(&plane->base, &crtc->base);
16530                 }
16531         }
16532
16533         /* We need to sanitize the plane -> pipe mapping first because this will
16534          * disable the crtc (and hence change the state) if it is wrong. Note
16535          * that gen4+ has a fixed plane -> pipe mapping.  */
16536         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16537                 bool plane;
16538
16539                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16540                               crtc->base.base.id, crtc->base.name);
16541
16542                 /* Pipe has the wrong plane attached and the plane is active.
16543                  * Temporarily change the plane mapping and disable everything
16544                  * ...  */
16545                 plane = crtc->plane;
16546                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16547                 crtc->plane = !plane;
16548                 intel_crtc_disable_noatomic(&crtc->base);
16549                 crtc->plane = plane;
16550         }
16551
16552         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16553             crtc->pipe == PIPE_A && !crtc->active) {
16554                 /* BIOS forgot to enable pipe A, this mostly happens after
16555                  * resume. Force-enable the pipe to fix this, the update_dpms
16556                  * call below we restore the pipe to the right state, but leave
16557                  * the required bits on. */
16558                 intel_enable_pipe_a(dev);
16559         }
16560
16561         /* Adjust the state of the output pipe according to whether we
16562          * have active connectors/encoders. */
16563         if (crtc->active && !intel_crtc_has_encoders(crtc))
16564                 intel_crtc_disable_noatomic(&crtc->base);
16565
16566         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16567                 /*
16568                  * We start out with underrun reporting disabled to avoid races.
16569                  * For correct bookkeeping mark this on active crtcs.
16570                  *
16571                  * Also on gmch platforms we dont have any hardware bits to
16572                  * disable the underrun reporting. Which means we need to start
16573                  * out with underrun reporting disabled also on inactive pipes,
16574                  * since otherwise we'll complain about the garbage we read when
16575                  * e.g. coming up after runtime pm.
16576                  *
16577                  * No protection against concurrent access is required - at
16578                  * worst a fifo underrun happens which also sets this to false.
16579                  */
16580                 crtc->cpu_fifo_underrun_disabled = true;
16581                 /*
16582                  * We track the PCH trancoder underrun reporting state
16583                  * within the crtc. With crtc for pipe A housing the underrun
16584                  * reporting state for PCH transcoder A, crtc for pipe B housing
16585                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16586                  * and marking underrun reporting as disabled for the non-existing
16587                  * PCH transcoders B and C would prevent enabling the south
16588                  * error interrupt (see cpt_can_enable_serr_int()).
16589                  */
16590                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16591                         crtc->pch_fifo_underrun_disabled = true;
16592         }
16593 }
16594
16595 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16596 {
16597         struct intel_connector *connector;
16598
16599         /* We need to check both for a crtc link (meaning that the
16600          * encoder is active and trying to read from a pipe) and the
16601          * pipe itself being active. */
16602         bool has_active_crtc = encoder->base.crtc &&
16603                 to_intel_crtc(encoder->base.crtc)->active;
16604
16605         connector = intel_encoder_find_connector(encoder);
16606         if (connector && !has_active_crtc) {
16607                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16608                               encoder->base.base.id,
16609                               encoder->base.name);
16610
16611                 /* Connector is active, but has no active pipe. This is
16612                  * fallout from our resume register restoring. Disable
16613                  * the encoder manually again. */
16614                 if (encoder->base.crtc) {
16615                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16616
16617                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16618                                       encoder->base.base.id,
16619                                       encoder->base.name);
16620                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16621                         if (encoder->post_disable)
16622                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16623                 }
16624                 encoder->base.crtc = NULL;
16625
16626                 /* Inconsistent output/port/pipe state happens presumably due to
16627                  * a bug in one of the get_hw_state functions. Or someplace else
16628                  * in our code, like the register restore mess on resume. Clamp
16629                  * things to off as a safer default. */
16630
16631                 connector->base.dpms = DRM_MODE_DPMS_OFF;
16632                 connector->base.encoder = NULL;
16633         }
16634         /* Enabled encoders without active connectors will be fixed in
16635          * the crtc fixup. */
16636 }
16637
16638 void i915_redisable_vga_power_on(struct drm_device *dev)
16639 {
16640         struct drm_i915_private *dev_priv = to_i915(dev);
16641         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16642
16643         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16644                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16645                 i915_disable_vga(dev);
16646         }
16647 }
16648
16649 void i915_redisable_vga(struct drm_device *dev)
16650 {
16651         struct drm_i915_private *dev_priv = to_i915(dev);
16652
16653         /* This function can be called both from intel_modeset_setup_hw_state or
16654          * at a very early point in our resume sequence, where the power well
16655          * structures are not yet restored. Since this function is at a very
16656          * paranoid "someone might have enabled VGA while we were not looking"
16657          * level, just check if the power well is enabled instead of trying to
16658          * follow the "don't touch the power well if we don't need it" policy
16659          * the rest of the driver uses. */
16660         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16661                 return;
16662
16663         i915_redisable_vga_power_on(dev);
16664
16665         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16666 }
16667
16668 static bool primary_get_hw_state(struct intel_plane *plane)
16669 {
16670         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16671
16672         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16673 }
16674
16675 /* FIXME read out full plane state for all planes */
16676 static void readout_plane_state(struct intel_crtc *crtc)
16677 {
16678         struct drm_plane *primary = crtc->base.primary;
16679         struct intel_plane_state *plane_state =
16680                 to_intel_plane_state(primary->state);
16681
16682         plane_state->base.visible = crtc->active &&
16683                 primary_get_hw_state(to_intel_plane(primary));
16684
16685         if (plane_state->base.visible)
16686                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16687 }
16688
16689 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16690 {
16691         struct drm_i915_private *dev_priv = to_i915(dev);
16692         enum pipe pipe;
16693         struct intel_crtc *crtc;
16694         struct intel_encoder *encoder;
16695         struct intel_connector *connector;
16696         int i;
16697
16698         dev_priv->active_crtcs = 0;
16699
16700         for_each_intel_crtc(dev, crtc) {
16701                 struct intel_crtc_state *crtc_state = crtc->config;
16702                 int pixclk = 0;
16703
16704                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16705                 memset(crtc_state, 0, sizeof(*crtc_state));
16706                 crtc_state->base.crtc = &crtc->base;
16707
16708                 crtc_state->base.active = crtc_state->base.enable =
16709                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16710
16711                 crtc->base.enabled = crtc_state->base.enable;
16712                 crtc->active = crtc_state->base.active;
16713
16714                 if (crtc_state->base.active) {
16715                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16716
16717                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16718                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16719                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16720                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16721                         else
16722                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16723
16724                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16725                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16726                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16727                 }
16728
16729                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16730
16731                 readout_plane_state(crtc);
16732
16733                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16734                               crtc->base.base.id, crtc->base.name,
16735                               crtc->active ? "enabled" : "disabled");
16736         }
16737
16738         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16739                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16740
16741                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16742                                                   &pll->config.hw_state);
16743                 pll->config.crtc_mask = 0;
16744                 for_each_intel_crtc(dev, crtc) {
16745                         if (crtc->active && crtc->config->shared_dpll == pll)
16746                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16747                 }
16748                 pll->active_mask = pll->config.crtc_mask;
16749
16750                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16751                               pll->name, pll->config.crtc_mask, pll->on);
16752         }
16753
16754         for_each_intel_encoder(dev, encoder) {
16755                 pipe = 0;
16756
16757                 if (encoder->get_hw_state(encoder, &pipe)) {
16758                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16759                         encoder->base.crtc = &crtc->base;
16760                         crtc->config->output_types |= 1 << encoder->type;
16761                         encoder->get_config(encoder, crtc->config);
16762                 } else {
16763                         encoder->base.crtc = NULL;
16764                 }
16765
16766                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16767                               encoder->base.base.id,
16768                               encoder->base.name,
16769                               encoder->base.crtc ? "enabled" : "disabled",
16770                               pipe_name(pipe));
16771         }
16772
16773         for_each_intel_connector(dev, connector) {
16774                 if (connector->get_hw_state(connector)) {
16775                         connector->base.dpms = DRM_MODE_DPMS_ON;
16776
16777                         encoder = connector->encoder;
16778                         connector->base.encoder = &encoder->base;
16779
16780                         if (encoder->base.crtc &&
16781                             encoder->base.crtc->state->active) {
16782                                 /*
16783                                  * This has to be done during hardware readout
16784                                  * because anything calling .crtc_disable may
16785                                  * rely on the connector_mask being accurate.
16786                                  */
16787                                 encoder->base.crtc->state->connector_mask |=
16788                                         1 << drm_connector_index(&connector->base);
16789                                 encoder->base.crtc->state->encoder_mask |=
16790                                         1 << drm_encoder_index(&encoder->base);
16791                         }
16792
16793                 } else {
16794                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16795                         connector->base.encoder = NULL;
16796                 }
16797                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16798                               connector->base.base.id,
16799                               connector->base.name,
16800                               connector->base.encoder ? "enabled" : "disabled");
16801         }
16802
16803         for_each_intel_crtc(dev, crtc) {
16804                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16805
16806                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16807                 if (crtc->base.state->active) {
16808                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16809                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16810                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16811
16812                         /*
16813                          * The initial mode needs to be set in order to keep
16814                          * the atomic core happy. It wants a valid mode if the
16815                          * crtc's enabled, so we do the above call.
16816                          *
16817                          * At this point some state updated by the connectors
16818                          * in their ->detect() callback has not run yet, so
16819                          * no recalculation can be done yet.
16820                          *
16821                          * Even if we could do a recalculation and modeset
16822                          * right now it would cause a double modeset if
16823                          * fbdev or userspace chooses a different initial mode.
16824                          *
16825                          * If that happens, someone indicated they wanted a
16826                          * mode change, which means it's safe to do a full
16827                          * recalculation.
16828                          */
16829                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16830
16831                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16832                         update_scanline_offset(crtc);
16833                 }
16834
16835                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16836         }
16837 }
16838
16839 /* Scan out the current hw modeset state,
16840  * and sanitizes it to the current state
16841  */
16842 static void
16843 intel_modeset_setup_hw_state(struct drm_device *dev)
16844 {
16845         struct drm_i915_private *dev_priv = to_i915(dev);
16846         enum pipe pipe;
16847         struct intel_crtc *crtc;
16848         struct intel_encoder *encoder;
16849         int i;
16850
16851         intel_modeset_readout_hw_state(dev);
16852
16853         /* HW state is read out, now we need to sanitize this mess. */
16854         for_each_intel_encoder(dev, encoder) {
16855                 intel_sanitize_encoder(encoder);
16856         }
16857
16858         for_each_pipe(dev_priv, pipe) {
16859                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16860                 intel_sanitize_crtc(crtc);
16861                 intel_dump_pipe_config(crtc, crtc->config,
16862                                        "[setup_hw_state]");
16863         }
16864
16865         intel_modeset_update_connector_atomic_state(dev);
16866
16867         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16868                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16869
16870                 if (!pll->on || pll->active_mask)
16871                         continue;
16872
16873                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16874
16875                 pll->funcs.disable(dev_priv, pll);
16876                 pll->on = false;
16877         }
16878
16879         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16880                 vlv_wm_get_hw_state(dev);
16881         else if (IS_GEN9(dev))
16882                 skl_wm_get_hw_state(dev);
16883         else if (HAS_PCH_SPLIT(dev))
16884                 ilk_wm_get_hw_state(dev);
16885
16886         for_each_intel_crtc(dev, crtc) {
16887                 unsigned long put_domains;
16888
16889                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16890                 if (WARN_ON(put_domains))
16891                         modeset_put_power_domains(dev_priv, put_domains);
16892         }
16893         intel_display_set_init_power(dev_priv, false);
16894
16895         intel_fbc_init_pipe_state(dev_priv);
16896 }
16897
16898 void intel_display_resume(struct drm_device *dev)
16899 {
16900         struct drm_i915_private *dev_priv = to_i915(dev);
16901         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16902         struct drm_modeset_acquire_ctx ctx;
16903         int ret;
16904
16905         dev_priv->modeset_restore_state = NULL;
16906         if (state)
16907                 state->acquire_ctx = &ctx;
16908
16909         /*
16910          * This is a cludge because with real atomic modeset mode_config.mutex
16911          * won't be taken. Unfortunately some probed state like
16912          * audio_codec_enable is still protected by mode_config.mutex, so lock
16913          * it here for now.
16914          */
16915         mutex_lock(&dev->mode_config.mutex);
16916         drm_modeset_acquire_init(&ctx, 0);
16917
16918         while (1) {
16919                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16920                 if (ret != -EDEADLK)
16921                         break;
16922
16923                 drm_modeset_backoff(&ctx);
16924         }
16925
16926         if (!ret)
16927                 ret = __intel_display_resume(dev, state);
16928
16929         drm_modeset_drop_locks(&ctx);
16930         drm_modeset_acquire_fini(&ctx);
16931         mutex_unlock(&dev->mode_config.mutex);
16932
16933         if (ret) {
16934                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16935                 drm_atomic_state_free(state);
16936         }
16937 }
16938
16939 void intel_modeset_gem_init(struct drm_device *dev)
16940 {
16941         struct drm_i915_private *dev_priv = to_i915(dev);
16942         struct drm_crtc *c;
16943         struct drm_i915_gem_object *obj;
16944
16945         intel_init_gt_powersave(dev_priv);
16946
16947         intel_modeset_init_hw(dev);
16948
16949         intel_setup_overlay(dev_priv);
16950
16951         /*
16952          * Make sure any fbs we allocated at startup are properly
16953          * pinned & fenced.  When we do the allocation it's too early
16954          * for this.
16955          */
16956         for_each_crtc(dev, c) {
16957                 struct i915_vma *vma;
16958
16959                 obj = intel_fb_obj(c->primary->fb);
16960                 if (obj == NULL)
16961                         continue;
16962
16963                 mutex_lock(&dev->struct_mutex);
16964                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16965                                                  c->primary->state->rotation);
16966                 mutex_unlock(&dev->struct_mutex);
16967                 if (IS_ERR(vma)) {
16968                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16969                                   to_intel_crtc(c)->pipe);
16970                         drm_framebuffer_unreference(c->primary->fb);
16971                         c->primary->fb = NULL;
16972                         c->primary->crtc = c->primary->state->crtc = NULL;
16973                         update_state_fb(c->primary);
16974                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16975                 }
16976         }
16977 }
16978
16979 int intel_connector_register(struct drm_connector *connector)
16980 {
16981         struct intel_connector *intel_connector = to_intel_connector(connector);
16982         int ret;
16983
16984         ret = intel_backlight_device_register(intel_connector);
16985         if (ret)
16986                 goto err;
16987
16988         return 0;
16989
16990 err:
16991         return ret;
16992 }
16993
16994 void intel_connector_unregister(struct drm_connector *connector)
16995 {
16996         struct intel_connector *intel_connector = to_intel_connector(connector);
16997
16998         intel_backlight_device_unregister(intel_connector);
16999         intel_panel_destroy_backlight(connector);
17000 }
17001
17002 void intel_modeset_cleanup(struct drm_device *dev)
17003 {
17004         struct drm_i915_private *dev_priv = to_i915(dev);
17005
17006         intel_disable_gt_powersave(dev_priv);
17007
17008         /*
17009          * Interrupts and polling as the first thing to avoid creating havoc.
17010          * Too much stuff here (turning of connectors, ...) would
17011          * experience fancy races otherwise.
17012          */
17013         intel_irq_uninstall(dev_priv);
17014
17015         /*
17016          * Due to the hpd irq storm handling the hotplug work can re-arm the
17017          * poll handlers. Hence disable polling after hpd handling is shut down.
17018          */
17019         drm_kms_helper_poll_fini(dev);
17020
17021         intel_unregister_dsm_handler();
17022
17023         intel_fbc_global_disable(dev_priv);
17024
17025         /* flush any delayed tasks or pending work */
17026         flush_scheduled_work();
17027
17028         drm_mode_config_cleanup(dev);
17029
17030         intel_cleanup_overlay(dev_priv);
17031
17032         intel_cleanup_gt_powersave(dev_priv);
17033
17034         intel_teardown_gmbus(dev);
17035 }
17036
17037 void intel_connector_attach_encoder(struct intel_connector *connector,
17038                                     struct intel_encoder *encoder)
17039 {
17040         connector->encoder = encoder;
17041         drm_mode_connector_attach_encoder(&connector->base,
17042                                           &encoder->base);
17043 }
17044
17045 /*
17046  * set vga decode state - true == enable VGA decode
17047  */
17048 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17049 {
17050         struct drm_i915_private *dev_priv = to_i915(dev);
17051         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17052         u16 gmch_ctrl;
17053
17054         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17055                 DRM_ERROR("failed to read control word\n");
17056                 return -EIO;
17057         }
17058
17059         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17060                 return 0;
17061
17062         if (state)
17063                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17064         else
17065                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17066
17067         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17068                 DRM_ERROR("failed to write control word\n");
17069                 return -EIO;
17070         }
17071
17072         return 0;
17073 }
17074
17075 struct intel_display_error_state {
17076
17077         u32 power_well_driver;
17078
17079         int num_transcoders;
17080
17081         struct intel_cursor_error_state {
17082                 u32 control;
17083                 u32 position;
17084                 u32 base;
17085                 u32 size;
17086         } cursor[I915_MAX_PIPES];
17087
17088         struct intel_pipe_error_state {
17089                 bool power_domain_on;
17090                 u32 source;
17091                 u32 stat;
17092         } pipe[I915_MAX_PIPES];
17093
17094         struct intel_plane_error_state {
17095                 u32 control;
17096                 u32 stride;
17097                 u32 size;
17098                 u32 pos;
17099                 u32 addr;
17100                 u32 surface;
17101                 u32 tile_offset;
17102         } plane[I915_MAX_PIPES];
17103
17104         struct intel_transcoder_error_state {
17105                 bool power_domain_on;
17106                 enum transcoder cpu_transcoder;
17107
17108                 u32 conf;
17109
17110                 u32 htotal;
17111                 u32 hblank;
17112                 u32 hsync;
17113                 u32 vtotal;
17114                 u32 vblank;
17115                 u32 vsync;
17116         } transcoder[4];
17117 };
17118
17119 struct intel_display_error_state *
17120 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17121 {
17122         struct intel_display_error_state *error;
17123         int transcoders[] = {
17124                 TRANSCODER_A,
17125                 TRANSCODER_B,
17126                 TRANSCODER_C,
17127                 TRANSCODER_EDP,
17128         };
17129         int i;
17130
17131         if (INTEL_INFO(dev_priv)->num_pipes == 0)
17132                 return NULL;
17133
17134         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17135         if (error == NULL)
17136                 return NULL;
17137
17138         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17139                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17140
17141         for_each_pipe(dev_priv, i) {
17142                 error->pipe[i].power_domain_on =
17143                         __intel_display_power_is_enabled(dev_priv,
17144                                                          POWER_DOMAIN_PIPE(i));
17145                 if (!error->pipe[i].power_domain_on)
17146                         continue;
17147
17148                 error->cursor[i].control = I915_READ(CURCNTR(i));
17149                 error->cursor[i].position = I915_READ(CURPOS(i));
17150                 error->cursor[i].base = I915_READ(CURBASE(i));
17151
17152                 error->plane[i].control = I915_READ(DSPCNTR(i));
17153                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17154                 if (INTEL_GEN(dev_priv) <= 3) {
17155                         error->plane[i].size = I915_READ(DSPSIZE(i));
17156                         error->plane[i].pos = I915_READ(DSPPOS(i));
17157                 }
17158                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17159                         error->plane[i].addr = I915_READ(DSPADDR(i));
17160                 if (INTEL_GEN(dev_priv) >= 4) {
17161                         error->plane[i].surface = I915_READ(DSPSURF(i));
17162                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17163                 }
17164
17165                 error->pipe[i].source = I915_READ(PIPESRC(i));
17166
17167                 if (HAS_GMCH_DISPLAY(dev_priv))
17168                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17169         }
17170
17171         /* Note: this does not include DSI transcoders. */
17172         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17173         if (HAS_DDI(dev_priv))
17174                 error->num_transcoders++; /* Account for eDP. */
17175
17176         for (i = 0; i < error->num_transcoders; i++) {
17177                 enum transcoder cpu_transcoder = transcoders[i];
17178
17179                 error->transcoder[i].power_domain_on =
17180                         __intel_display_power_is_enabled(dev_priv,
17181                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17182                 if (!error->transcoder[i].power_domain_on)
17183                         continue;
17184
17185                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17186
17187                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17188                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17189                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17190                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17191                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17192                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17193                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17194         }
17195
17196         return error;
17197 }
17198
17199 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17200
17201 void
17202 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17203                                 struct drm_device *dev,
17204                                 struct intel_display_error_state *error)
17205 {
17206         struct drm_i915_private *dev_priv = to_i915(dev);
17207         int i;
17208
17209         if (!error)
17210                 return;
17211
17212         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17213         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17214                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17215                            error->power_well_driver);
17216         for_each_pipe(dev_priv, i) {
17217                 err_printf(m, "Pipe [%d]:\n", i);
17218                 err_printf(m, "  Power: %s\n",
17219                            onoff(error->pipe[i].power_domain_on));
17220                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17221                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17222
17223                 err_printf(m, "Plane [%d]:\n", i);
17224                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17225                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17226                 if (INTEL_INFO(dev)->gen <= 3) {
17227                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17228                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17229                 }
17230                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17231                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17232                 if (INTEL_INFO(dev)->gen >= 4) {
17233                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17234                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17235                 }
17236
17237                 err_printf(m, "Cursor [%d]:\n", i);
17238                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17239                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17240                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17241         }
17242
17243         for (i = 0; i < error->num_transcoders; i++) {
17244                 err_printf(m, "CPU transcoder: %s\n",
17245                            transcoder_name(error->transcoder[i].cpu_transcoder));
17246                 err_printf(m, "  Power: %s\n",
17247                            onoff(error->transcoder[i].power_domain_on));
17248                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17249                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17250                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17251                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17252                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17253                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17254                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17255         }
17256 }